Coverage Report

Created: 2026-04-04 08:16

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/binutils-gdb/opcodes/arm-dis.c
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Source
1
/* Instruction printing code for the ARM
2
   Copyright (C) 1994-2026 Free Software Foundation, Inc.
3
   Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4
   Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6
   This file is part of libopcodes.
7
8
   This library is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3 of the License, or
11
   (at your option) any later version.
12
13
   It is distributed in the hope that it will be useful, but WITHOUT
14
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16
   License for more details.
17
18
   You should have received a copy of the GNU General Public License
19
   along with this program; if not, write to the Free Software
20
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21
   MA 02110-1301, USA.  */
22
23
#include "sysdep.h"
24
#include <assert.h>
25
26
#include "disassemble.h"
27
#include "opcode/arm.h"
28
#include "opintl.h"
29
#include "safe-ctype.h"
30
#include "libiberty.h"
31
#include "floatformat.h"
32
33
/* FIXME: This shouldn't be done here.  */
34
#include "coff/internal.h"
35
#include "libcoff.h"
36
#include "bfd.h"
37
#include "elf-bfd.h"
38
#include "elf/internal.h"
39
#include "elf/arm.h"
40
#include "mach-o.h"
41
42
/* Cached mapping symbol state.  */
43
enum map_type
44
{
45
  MAP_ARM,
46
  MAP_THUMB,
47
  MAP_DATA
48
};
49
50
struct arm_private_data
51
{
52
  /* The features to use when disassembling optional instructions.  */
53
  arm_feature_set features;
54
55
  /* Track the last type (although this doesn't seem to be useful) */
56
  enum map_type last_type;
57
58
  /* Tracking symbol table information */
59
  int last_mapping_sym;
60
61
  /* The end range of the current range being disassembled.  */
62
  bfd_vma last_stop_offset;
63
  bfd_vma last_mapping_addr;
64
};
65
66
enum mve_instructions
67
{
68
  MVE_VPST,
69
  MVE_VPT_FP_T1,
70
  MVE_VPT_FP_T2,
71
  MVE_VPT_VEC_T1,
72
  MVE_VPT_VEC_T2,
73
  MVE_VPT_VEC_T3,
74
  MVE_VPT_VEC_T4,
75
  MVE_VPT_VEC_T5,
76
  MVE_VPT_VEC_T6,
77
  MVE_VCMP_FP_T1,
78
  MVE_VCMP_FP_T2,
79
  MVE_VCMP_VEC_T1,
80
  MVE_VCMP_VEC_T2,
81
  MVE_VCMP_VEC_T3,
82
  MVE_VCMP_VEC_T4,
83
  MVE_VCMP_VEC_T5,
84
  MVE_VCMP_VEC_T6,
85
  MVE_VDUP,
86
  MVE_VEOR,
87
  MVE_VFMAS_FP_SCALAR,
88
  MVE_VFMA_FP_SCALAR,
89
  MVE_VFMA_FP,
90
  MVE_VFMS_FP,
91
  MVE_VHADD_T1,
92
  MVE_VHADD_T2,
93
  MVE_VHSUB_T1,
94
  MVE_VHSUB_T2,
95
  MVE_VRHADD,
96
  MVE_VLD2,
97
  MVE_VLD4,
98
  MVE_VST2,
99
  MVE_VST4,
100
  MVE_VLDRB_T1,
101
  MVE_VLDRH_T2,
102
  MVE_VLDRB_T5,
103
  MVE_VLDRH_T6,
104
  MVE_VLDRW_T7,
105
  MVE_VSTRB_T1,
106
  MVE_VSTRH_T2,
107
  MVE_VSTRB_T5,
108
  MVE_VSTRH_T6,
109
  MVE_VSTRW_T7,
110
  MVE_VLDRB_GATHER_T1,
111
  MVE_VLDRH_GATHER_T2,
112
  MVE_VLDRW_GATHER_T3,
113
  MVE_VLDRD_GATHER_T4,
114
  MVE_VLDRW_GATHER_T5,
115
  MVE_VLDRD_GATHER_T6,
116
  MVE_VSTRB_SCATTER_T1,
117
  MVE_VSTRH_SCATTER_T2,
118
  MVE_VSTRW_SCATTER_T3,
119
  MVE_VSTRD_SCATTER_T4,
120
  MVE_VSTRW_SCATTER_T5,
121
  MVE_VSTRD_SCATTER_T6,
122
  MVE_VCVT_FP_FIX_VEC,
123
  MVE_VCVT_BETWEEN_FP_INT,
124
  MVE_VCVT_FP_HALF_FP,
125
  MVE_VCVT_FROM_FP_TO_INT,
126
  MVE_VRINT_FP,
127
  MVE_VMOV_HFP_TO_GP,
128
  MVE_VMOV_GP_TO_VEC_LANE,
129
  MVE_VMOV_IMM_TO_VEC,
130
  MVE_VMOV_VEC_TO_VEC,
131
  MVE_VMOV2_VEC_LANE_TO_GP,
132
  MVE_VMOV2_GP_TO_VEC_LANE,
133
  MVE_VMOV_VEC_LANE_TO_GP,
134
  MVE_VMVN_IMM,
135
  MVE_VMVN_REG,
136
  MVE_VORR_IMM,
137
  MVE_VORR_REG,
138
  MVE_VORN,
139
  MVE_VBIC_IMM,
140
  MVE_VBIC_REG,
141
  MVE_VMOVX,
142
  MVE_VMOVL,
143
  MVE_VMOVN,
144
  MVE_VMULL_INT,
145
  MVE_VMULL_POLY,
146
  MVE_VQDMULL_T1,
147
  MVE_VQDMULL_T2,
148
  MVE_VQMOVN,
149
  MVE_VQMOVUN,
150
  MVE_VADDV,
151
  MVE_VMLADAV_T1,
152
  MVE_VMLADAV_T2,
153
  MVE_VMLALDAV,
154
  MVE_VMLAS,
155
  MVE_VADDLV,
156
  MVE_VMLSDAV_T1,
157
  MVE_VMLSDAV_T2,
158
  MVE_VMLSLDAV,
159
  MVE_VRMLALDAVH,
160
  MVE_VRMLSLDAVH,
161
  MVE_VQDMLADH,
162
  MVE_VQRDMLADH,
163
  MVE_VQDMLAH,
164
  MVE_VQRDMLAH,
165
  MVE_VQDMLASH,
166
  MVE_VQRDMLASH,
167
  MVE_VQDMLSDH,
168
  MVE_VQRDMLSDH,
169
  MVE_VQDMULH_T1,
170
  MVE_VQRDMULH_T2,
171
  MVE_VQDMULH_T3,
172
  MVE_VQRDMULH_T4,
173
  MVE_VDDUP,
174
  MVE_VDWDUP,
175
  MVE_VIWDUP,
176
  MVE_VIDUP,
177
  MVE_VCADD_FP,
178
  MVE_VCADD_VEC,
179
  MVE_VHCADD,
180
  MVE_VCMLA_FP,
181
  MVE_VCMUL_FP,
182
  MVE_VQRSHL_T1,
183
  MVE_VQRSHL_T2,
184
  MVE_VQRSHRN,
185
  MVE_VQRSHRUN,
186
  MVE_VQSHL_T1,
187
  MVE_VQSHL_T2,
188
  MVE_VQSHLU_T3,
189
  MVE_VQSHL_T4,
190
  MVE_VQSHRN,
191
  MVE_VQSHRUN,
192
  MVE_VRSHL_T1,
193
  MVE_VRSHL_T2,
194
  MVE_VRSHR,
195
  MVE_VRSHRN,
196
  MVE_VSHL_T1,
197
  MVE_VSHL_T2,
198
  MVE_VSHL_T3,
199
  MVE_VSHLC,
200
  MVE_VSHLL_T1,
201
  MVE_VSHLL_T2,
202
  MVE_VSHR,
203
  MVE_VSHRN,
204
  MVE_VSLI,
205
  MVE_VSRI,
206
  MVE_VADC,
207
  MVE_VABAV,
208
  MVE_VABD_FP,
209
  MVE_VABD_VEC,
210
  MVE_VABS_FP,
211
  MVE_VABS_VEC,
212
  MVE_VADD_FP_T1,
213
  MVE_VADD_FP_T2,
214
  MVE_VADD_VEC_T1,
215
  MVE_VADD_VEC_T2,
216
  MVE_VSBC,
217
  MVE_VSUB_FP_T1,
218
  MVE_VSUB_FP_T2,
219
  MVE_VSUB_VEC_T1,
220
  MVE_VSUB_VEC_T2,
221
  MVE_VAND,
222
  MVE_VBRSR,
223
  MVE_VCLS,
224
  MVE_VCLZ,
225
  MVE_VCTP,
226
  MVE_VMAX,
227
  MVE_VMAXA,
228
  MVE_VMAXNM_FP,
229
  MVE_VMAXNMA_FP,
230
  MVE_VMAXNMV_FP,
231
  MVE_VMAXNMAV_FP,
232
  MVE_VMAXV,
233
  MVE_VMAXAV,
234
  MVE_VMIN,
235
  MVE_VMINA,
236
  MVE_VMINNM_FP,
237
  MVE_VMINNMA_FP,
238
  MVE_VMINNMV_FP,
239
  MVE_VMINNMAV_FP,
240
  MVE_VMINV,
241
  MVE_VMINAV,
242
  MVE_VMLA,
243
  MVE_VMUL_FP_T1,
244
  MVE_VMUL_FP_T2,
245
  MVE_VMUL_VEC_T1,
246
  MVE_VMUL_VEC_T2,
247
  MVE_VMULH,
248
  MVE_VRMULH,
249
  MVE_VNEG_FP,
250
  MVE_VNEG_VEC,
251
  MVE_VPNOT,
252
  MVE_VPSEL,
253
  MVE_VQABS,
254
  MVE_VQADD_T1,
255
  MVE_VQADD_T2,
256
  MVE_VQSUB_T1,
257
  MVE_VQSUB_T2,
258
  MVE_VQNEG,
259
  MVE_VREV16,
260
  MVE_VREV32,
261
  MVE_VREV64,
262
  MVE_LSLL,
263
  MVE_LSLLI,
264
  MVE_LSRL,
265
  MVE_ASRL,
266
  MVE_ASRLI,
267
  MVE_SQRSHRL,
268
  MVE_SQRSHR,
269
  MVE_UQRSHL,
270
  MVE_UQRSHLL,
271
  MVE_UQSHL,
272
  MVE_UQSHLL,
273
  MVE_URSHRL,
274
  MVE_URSHR,
275
  MVE_SRSHRL,
276
  MVE_SRSHR,
277
  MVE_SQSHLL,
278
  MVE_SQSHL,
279
  MVE_CINC,
280
  MVE_CINV,
281
  MVE_CNEG,
282
  MVE_CSINC,
283
  MVE_CSINV,
284
  MVE_CSET,
285
  MVE_CSETM,
286
  MVE_CSNEG,
287
  MVE_CSEL,
288
  MVE_NONE
289
};
290
291
enum mve_unpredictable
292
{
293
  UNPRED_IT_BLOCK,    /* Unpredictable because mve insn in it block.
294
         */
295
  UNPRED_FCA_0_FCB_1,   /* Unpredictable because fcA = 0 and
296
           fcB = 1 (vpt).  */
297
  UNPRED_R13,     /* Unpredictable because r13 (sp) or
298
           r15 (sp) used.  */
299
  UNPRED_R15,     /* Unpredictable because r15 (pc) is used.  */
300
  UNPRED_Q_GT_4,    /* Unpredictable because
301
           vec reg start > 4 (vld4/st4).  */
302
  UNPRED_Q_GT_6,    /* Unpredictable because
303
           vec reg start > 6 (vld2/st2).  */
304
  UNPRED_R13_AND_WB,    /* Unpredictable becase gp reg = r13
305
           and WB bit = 1.  */
306
  UNPRED_Q_REGS_EQUAL,    /* Unpredictable because vector registers are
307
           equal.  */
308
  UNPRED_OS,      /* Unpredictable because offset scaled == 1.  */
309
  UNPRED_GP_REGS_EQUAL,   /* Unpredictable because gp registers are the
310
           same.  */
311
  UNPRED_Q_REGS_EQ_AND_SIZE_1,  /* Unpredictable because q regs equal and
312
           size = 1.  */
313
  UNPRED_Q_REGS_EQ_AND_SIZE_2,  /* Unpredictable because q regs equal and
314
           size = 2.  */
315
  UNPRED_NONE     /* No unpredictable behavior.  */
316
};
317
318
enum mve_undefined
319
{
320
  UNDEF_SIZE,     /* undefined size.  */
321
  UNDEF_SIZE_0,     /* undefined because size == 0.  */
322
  UNDEF_SIZE_2,     /* undefined because size == 2.  */
323
  UNDEF_SIZE_3,     /* undefined because size == 3.  */
324
  UNDEF_SIZE_LE_1,    /* undefined because size <= 1.  */
325
  UNDEF_SIZE_NOT_0,   /* undefined because size != 0.  */
326
  UNDEF_SIZE_NOT_2,   /* undefined because size != 2.  */
327
  UNDEF_SIZE_NOT_3,   /* undefined because size != 3.  */
328
  UNDEF_NOT_UNS_SIZE_0,   /* undefined because U == 0 and
329
           size == 0.  */
330
  UNDEF_NOT_UNS_SIZE_1,   /* undefined because U == 0 and
331
           size == 1.  */
332
  UNDEF_NOT_UNSIGNED,   /* undefined because U == 0.  */
333
  UNDEF_VCVT_IMM6,    /* imm6 < 32.  */
334
  UNDEF_VCVT_FSI_IMM6,    /* fsi = 0 and 32 >= imm6 <= 47.  */
335
  UNDEF_BAD_OP1_OP2,    /* undefined with op2 = 2 and
336
           op1 == (0 or 1).  */
337
  UNDEF_BAD_U_OP1_OP2,    /* undefined with U = 1 and
338
           op2 == 0 and op1 == (0 or 1).  */
339
  UNDEF_OP_0_BAD_CMODE,   /* undefined because op == 0 and cmode
340
           in {0xx1, x0x1}.  */
341
  UNDEF_XCHG_UNS,   /* undefined because X == 1 and U == 1.  */
342
  UNDEF_NONE      /* no undefined behavior.  */
343
};
344
345
struct opcode32
346
{
347
  arm_feature_set arch;   /* Architecture defining this insn.  */
348
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
349
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
350
  const char *  assembler;  /* How to disassemble this insn.  */
351
};
352
353
struct cdeopcode32
354
{
355
  arm_feature_set arch;   /* Architecture defining this insn.  */
356
  uint8_t coproc_shift;   /* coproc is this far into op.  */
357
  uint16_t coproc_mask;   /* Length of coproc field in op.  */
358
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
359
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
360
  const char *  assembler;  /* How to disassemble this insn.  */
361
};
362
363
/* MVE opcodes.  */
364
365
struct mopcode32
366
{
367
  arm_feature_set arch;   /* Architecture defining this insn.  */
368
  enum mve_instructions mve_op;  /* Specific mve instruction for faster
369
            decoding.  */
370
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
371
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
372
  const char *  assembler;  /* How to disassemble this insn.  */
373
};
374
375
enum isa {
376
  ANY,
377
  T32,
378
  ARM
379
};
380
381
382
/* Shared (between Arm and Thumb mode) opcode.  */
383
struct sopcode32
384
{
385
  enum isa isa;     /* Execution mode instruction availability.  */
386
  arm_feature_set arch;   /* Architecture defining this insn.  */
387
  unsigned long value;    /* If arch is 0 then value is a sentinel.  */
388
  unsigned long mask;   /* Recognise insn if (op & mask) == value.  */
389
  const char *  assembler;  /* How to disassemble this insn.  */
390
};
391
392
struct opcode16
393
{
394
  arm_feature_set arch;   /* Architecture defining this insn.  */
395
  unsigned short value, mask; /* Recognise insn if (op & mask) == value.  */
396
  const char *assembler;  /* How to disassemble this insn.  */
397
};
398
399
/* print_insn_coprocessor recognizes the following format control codes:
400
401
   %%     %
402
403
   %c     print condition code (always bits 28-31 in ARM mode)
404
   %b     print condition code allowing cp_num == 9
405
   %q     print shifter argument
406
   %u     print condition code (unconditional in ARM mode,
407
                          UNPREDICTABLE if not AL in Thumb)
408
   %A     print address for ldc/stc instruction
409
   %B     print vstm/vldm register list
410
   %C     print vscclrm register list
411
   %J     print register for VLDR instruction
412
   %K     print address for VLDR instruction
413
414
   %<bitfield>c   print as a condition code (for vsel)
415
   %<bitfield>r   print as an ARM register
416
   %<bitfield>R   as %<>r but r15 is UNPREDICTABLE
417
   %<bitfield>ru        as %<>r but each u register must be unique.
418
   %<bitfield>d   print the bitfield in decimal
419
   %<bitfield>k   print immediate for VFPv3 conversion instruction
420
   %<bitfield>x   print the bitfield in hex
421
   %<bitfield>X   print the bitfield as 1 hex digit without leading "0x"
422
   %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
423
   %<bitfield>g         print as an iWMMXt 64-bit register
424
   %<bitfield>G         print as an iWMMXt general purpose or control register
425
   %<bitfield>D   print as a NEON D register
426
   %<bitfield>Q   print as a NEON Q register
427
   %<bitfield>V   print as a NEON D or Q register
428
   %<bitfield>E   print a quarter-float immediate value
429
430
   %y<code>   print a single precision VFP reg.
431
        Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
432
   %z<code>   print a double precision VFP reg
433
        Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
434
435
   %<bitfield>'c  print specified char iff bitfield is all ones
436
   %<bitfield>`c  print specified char iff bitfield is all zeroes
437
   %<bitfield>?ab...    select from array of values in big endian order
438
439
   %L     print as an iWMMXt N/M width field.
440
   %Z     print the Immediate of a WSHUFH instruction.
441
   %l     like 'A' except use byte offsets for 'B' & 'H'
442
      versions.
443
   %i     print 5-bit immediate in bits 8,3..0
444
      (print "32" when 0)
445
   %r     print register offset address for wldt/wstr instruction.  */
446
447
enum opcode_sentinel_enum
448
{
449
  SENTINEL_IWMMXT_START = 1,
450
  SENTINEL_IWMMXT_END,
451
  SENTINEL_GENERIC_START
452
} opcode_sentinels;
453
454
#define UNDEFINED_INSTRUCTION      "\t\t@ <UNDEFINED> instruction: %0-31x"
455
1.23k
#define UNKNOWN_INSTRUCTION_32BIT  "\t\t@ <UNDEFINED> instruction: %08x"
456
0
#define UNKNOWN_INSTRUCTION_16BIT  "\t\t@ <UNDEFINED> instruction: %04x"
457
81.1k
#define UNPREDICTABLE_INSTRUCTION  "\t@ <UNPREDICTABLE>"
458
459
/* Common coprocessor opcodes shared between Arm and Thumb-2.  */
460
461
/* print_insn_cde recognizes the following format control codes:
462
463
   %%     %
464
465
   %a     print 'a' iff bit 28 is 1
466
   %p     print bits 8-10 as coprocessor
467
   %<bitfield>d   print as decimal
468
   %<bitfield>r   print as an ARM register
469
   %<bitfield>n   print as an ARM register but r15 is APSR_nzcv
470
   %<bitfield>T   print as an ARM register + 1
471
   %<bitfield>R   as %r but r13 is UNPREDICTABLE
472
   %<bitfield>S   as %r but rX where X > 10 is UNPREDICTABLE
473
   %j     print immediate taken from bits (16..21,7,0..5)
474
   %k     print immediate taken from bits (20..21,7,0..5).
475
   %l     print immediate taken from bits (20..22,7,4..5).  */
476
477
/* At the moment there is only one valid position for the coprocessor number,
478
   and hence that's encoded in the macro below.  */
479
#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
480
  { ARCH, 8, 7, VALUE, MASK, ASM }
481
static const struct cdeopcode32 cde_opcodes[] =
482
{
483
  /* Custom Datapath Extension instructions.  */
484
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
485
        0xee000000, 0xefc00840,
486
        "cx1%a\t%p, %12-15n, %{I:#%0-5,7,16-21d%}"),
487
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
488
        0xee000040, 0xefc00840,
489
        "cx1d%a\t%p, %12-15S, %12-15T, %{I:#%0-5,7,16-21d%}"),
490
491
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
492
        0xee400000, 0xefc00840,
493
        "cx2%a\t%p, %12-15n, %16-19n, %{I:#%0-5,7,20-21d%}"),
494
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
495
        0xee400040, 0xefc00840,
496
        "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, %{I:#%0-5,7,20-21d%}"),
497
498
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
499
        0xee800000, 0xef800840,
500
        "cx3%a\t%p, %0-3n, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
501
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
502
        0xee800040, 0xef800840,
503
       "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
504
505
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
506
        0xec200000, 0xeeb00840,
507
        "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19d%}"),
508
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
509
        0xec200040, 0xeeb00840,
510
        "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19,24d%}"),
511
512
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
513
        0xec300000, 0xeeb00840,
514
        "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19d%}"),
515
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
516
        0xec300040, 0xeeb00840,
517
        "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19,24d%}"),
518
519
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
520
        0xec800000, 0xee800840,
521
        "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21d%}"),
522
  CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
523
        0xec800040, 0xee800840,
524
        "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21,24d%}"),
525
526
  CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
527
528
};
529
530
static const struct sopcode32 coprocessor_opcodes[] =
531
{
532
  /* XScale instructions.  */
533
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
534
    0x0e200010, 0x0fff0ff0,
535
    "mia%c\t%{R:acc0%}, %0-3r, %12-15r"},
536
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
537
    0x0e280010, 0x0fff0ff0,
538
    "miaph%c\t%{R:acc0%}, %0-3r, %12-15r"},
539
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
540
    0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\t%{R:acc0%}, %0-3r, %12-15r"},
541
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
542
    0x0c400000, 0x0ff00fff, "mar%c\t%{R:acc0%}, %12-15r, %16-19r"},
543
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
544
    0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, %{R:acc0%}"},
545
546
  /* Intel Wireless MMX technology instructions.  */
547
  {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
548
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
549
    0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
550
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
551
    0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
552
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
553
    0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, %{I:#%0-2d%}"},
554
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
555
    0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, %{I:#%0-2d%}"},
556
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
557
    0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, %{I:#%0-2d%}"},
558
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
559
    0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
560
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
561
    0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
562
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
563
    0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
564
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
565
    0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
566
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
567
    0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
568
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
569
    0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
570
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
571
    0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
572
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
573
    0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
574
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
575
    0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
576
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
577
    0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
578
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
579
    0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
580
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
581
    0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
582
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
583
    0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
584
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
585
    0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
586
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
587
    0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
588
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
589
    0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, %{I:#%20-22d%}"},
590
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
591
    0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
592
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
593
    0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
594
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
595
    0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
596
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
597
    0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
598
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
599
    0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
600
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
601
    0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
602
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
603
    0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
604
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
605
    0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
606
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
607
    0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
608
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
609
    0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
610
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
611
    0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
612
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
613
    0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
614
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
615
    0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
616
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
617
    0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, %{I:#%21-23d%}"},
618
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
619
    0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
620
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
621
    0x0e800120, 0x0f800ff0,
622
    "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
623
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
624
    0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
625
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
626
    0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
627
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
628
    0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
629
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
630
    0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
631
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
632
    0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
633
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
634
    0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
635
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
636
    0x0e8000a0, 0x0f800ff0,
637
    "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
638
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
639
    0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
640
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
641
    0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
642
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
643
    0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
644
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
645
    0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
646
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
647
    0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
648
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
649
    0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
650
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
651
    0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
652
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
653
    0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
654
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
655
    0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, %{I:#%Z%}"},
656
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
657
    0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
658
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
659
    0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
660
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
661
    0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
662
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
663
    0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
664
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
665
    0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
666
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
667
    0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
668
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
669
    0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
670
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
671
    0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
672
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
673
    0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
674
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
675
    0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
676
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
677
    0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
678
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
679
    0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
680
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
681
    0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
682
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
683
    0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
684
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
685
    0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
686
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
687
    0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
688
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
689
    0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
690
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
691
    0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
692
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
693
    0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
694
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
695
    0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
696
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
697
    0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
698
  {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
699
    0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
700
  {ANY, ARM_FEATURE_CORE_LOW (0),
701
    SENTINEL_IWMMXT_END, 0, "" },
702
703
  /* Armv8.1-M Mainline instructions.  */
704
  {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
705
    0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
706
  {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
707
    0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
708
709
  /* ARMv8-M Mainline Security Extensions instructions.  */
710
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
711
    0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
712
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
713
    0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
714
715
  /* Register load/store.  */
716
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
717
    0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
718
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
719
    0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
720
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
721
    0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
722
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
723
    0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
724
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
725
    0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
726
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
727
    0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
728
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
729
    0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
730
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
731
    0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
732
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
733
    0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
734
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
735
    0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
736
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
737
    0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
738
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
739
    0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
740
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
741
    0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
742
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
743
    0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
744
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
745
    0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
746
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
747
    0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
748
  {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
749
    0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
750
  {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
751
    0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
752
753
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
754
    0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
755
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
756
    0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t@ Deprecated"},
757
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
758
    0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
759
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
760
    0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"},
761
762
  /* Data transfer between ARM and NEON registers.  */
763
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
764
    0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
765
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
766
    0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
767
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
768
    0x0e000b10, 0x0fd00f70, "vmov%c.32\t%{R:%16-19,7D[%21d]%}, %12-15r"},
769
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
770
    0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %{R:%16-19,7D[%21d]%}"},
771
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
772
    0x0e000b30, 0x0fd00f30, "vmov%c.16\t%{R:%16-19,7D[%6,21d]%}, %12-15r"},
773
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
774
    0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %{R:%16-19,7D[%6,21d]%}"},
775
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
776
    0x0e400b10, 0x0fd00f10, "vmov%c.8\t%{R:%16-19,7D[%5,6,21d]%}, %12-15r"},
777
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
778
    0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %{R:%16-19,7D[%5,6,21d]%}"},
779
  /* Half-precision conversion instructions.  */
780
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
781
    0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
782
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
783
    0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
784
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
785
    0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
786
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
787
    0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
788
789
  /* Floating point coprocessor (VFP) instructions.  */
790
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
791
    0x0ee00a10, 0x0fff0fff, "vmsr%c\t%{R:fpsid%}, %12-15r"},
792
  {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
793
    0x0ee10a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr%}, %12-15r"},
794
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
795
    0x0ee20a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr_nzcvqc%}, %12-15r"},
796
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
797
    0x0ee60a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr1%}, %12-15r"},
798
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
799
    0x0ee70a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr0%}, %12-15r"},
800
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
801
    0x0ee50a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr2%}, %12-15r"},
802
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
803
    0x0ee80a10, 0x0fff0fff, "vmsr%c\t%{R:fpexc%}, %12-15r"},
804
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
805
    0x0ee90a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst%}, %12-15r\t@ Impl def"},
806
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
807
    0x0eea0a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst2%}, %12-15r\t@ Impl def"},
808
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
809
    0x0eec0a10, 0x0fff0fff, "vmsr%c\t%{R:vpr%}, %12-15r"},
810
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
811
    0x0eed0a10, 0x0fff0fff, "vmsr%c\t%{R:p0%}, %12-15r"},
812
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
813
    0x0eee0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_ns%}, %12-15r"},
814
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
815
    0x0eef0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_s%}, %12-15r"},
816
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
817
    0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpsid%}"},
818
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
819
    0x0ef1fa10, 0x0fffffff, "vmrs%c\t%{R:APSR_nzcv%}, %{R:fpscr%}"},
820
  {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
821
    0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr%}"},
822
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
823
    0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr_nzcvqc%}"},
824
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
825
    0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr2%}"},
826
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
827
    0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr1%}"},
828
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
829
    0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr0%}"},
830
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
831
    0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpexc%}"},
832
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
833
    0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst%}\t@ Impl def"},
834
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
835
    0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst2%}\t@ Impl def"},
836
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
837
    0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:vpr%}"},
838
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
839
    0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:p0%}"},
840
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
841
    0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_ns%}"},
842
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
843
    0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_s%}"},
844
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
845
    0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%{I:%21d%}], %12-15r"},
846
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
847
    0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%{I:%21d%}]"},
848
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
849
    0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
850
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
851
    0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
852
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
853
    0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
854
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
855
    0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
856
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
857
    0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, %{I:#0.0%}"},
858
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
859
    0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, %{I:#0.0%}"},
860
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
861
    0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
862
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
863
    0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
864
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
865
    0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
866
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
867
    0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
868
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
869
    0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
870
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
871
    0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
872
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
873
    0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
874
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
875
    0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
876
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
877
    0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
878
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
879
    0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
880
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
881
    0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
882
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
883
    0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
884
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
885
    0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
886
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
887
    0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
888
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
889
    0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
890
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
891
    0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, %{I:#%5,0-3k%}"},
892
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
893
    0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
894
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
895
    0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
896
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
897
    0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, %{I:#%5,0-3k%}"},
898
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
899
    0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, %{I:#%5,0-3k%}"},
900
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
901
    0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
902
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
903
    0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, %{I:#%0-3,16-19E%}"},
904
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
905
    0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, %{I:#%0-3,16-19E%}"},
906
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
907
    0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
908
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
909
    0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
910
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
911
    0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
912
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
913
    0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
914
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
915
    0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
916
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
917
    0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
918
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
919
    0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
920
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
921
    0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
922
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
923
    0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
924
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
925
    0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
926
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
927
    0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
928
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
929
    0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
930
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
931
    0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
932
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
933
    0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
934
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
935
    0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
936
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
937
    0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
938
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
939
    0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
940
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
941
    0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
942
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
943
    0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
944
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
945
    0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
946
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
947
    0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
948
949
  /* VFP Fused multiply add instructions.  */
950
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
951
    0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
952
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
953
    0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
954
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
955
    0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
956
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
957
    0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
958
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
959
    0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
960
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
961
    0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
962
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
963
    0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
964
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
965
    0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
966
967
  /* FP v5.  */
968
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
969
    0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
970
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
971
    0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
972
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
973
    0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
974
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
975
    0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
976
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
977
    0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
978
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
979
    0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
980
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
981
    0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
982
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
983
    0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
984
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
985
    0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
986
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
987
    0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
988
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
989
    0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
990
  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
991
    0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
992
993
  {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
994
  /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
995
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
996
    0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
997
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
998
    0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
999
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1000
    0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
1001
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1002
    0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
1003
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1004
    0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
1005
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1006
    0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
1007
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1008
    0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20'90%}"},
1009
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1010
    0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20?21%20?780%}"},
1011
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1012
    0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20'90%}"},
1013
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1014
    0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20?21%20?780%}"},
1015
1016
  /* BFloat16 instructions.  */
1017
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1018
    0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1019
1020
  /* Dot Product instructions in the space of coprocessor 13.  */
1021
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1022
    0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1023
  {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1024
    0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}"},
1025
1026
  /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
1027
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1028
    0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
1029
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1030
    0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
1031
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1032
    0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
1033
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1034
    0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
1035
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1036
    0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
1037
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1038
    0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
1039
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1040
    0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
1041
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1042
    0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
1043
1044
  /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1045
     cp_num: bit <11:8> == 0b1001.
1046
     cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
1047
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1048
    0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1049
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1050
    0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1051
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1052
    0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1053
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1054
    0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, %{I:#0.0%}"},
1055
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1056
    0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
1057
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1058
    0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, %{I:#%5,0-3k%}"},
1059
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1060
    0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1061
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1062
    0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1063
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1064
    0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1065
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1066
    0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1067
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1068
    0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1069
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1070
    0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1071
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1072
    0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1073
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1074
    0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1075
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1076
    0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1077
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1078
    0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1079
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1080
    0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1081
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1082
    0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1083
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1084
    0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1085
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1086
    0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1087
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1088
    0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1089
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1090
    0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1091
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1092
    0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1093
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1094
    0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1095
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1096
    0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, %{I:#%0-3,16-19E%}"},
1097
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1098
    0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1099
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1100
    0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1101
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1102
    0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1103
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1104
    0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1105
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1106
    0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1107
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1108
    0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1109
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1110
    0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1111
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1112
    0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1113
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1114
    0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1115
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1116
    0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1117
1118
  /* ARMv8.3 javascript conversion instruction.  */
1119
  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1120
    0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1121
1122
  {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1123
};
1124
1125
/* Generic coprocessor instructions.  These are only matched if a more specific
1126
   SIMD or co-processor instruction does not match first.  */
1127
1128
static const struct sopcode32 generic_coprocessor_opcodes[] =
1129
{
1130
  /* Generic coprocessor instructions.  */
1131
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1132
    0x0c400000, 0x0ff00000, "mcrr%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19r, %{R:cr%0-3d%}"},
1133
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1134
    0x0c500000, 0x0ff00000,
1135
    "mrrc%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
1136
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1137
    0x0e000000, 0x0f000010,
1138
    "cdp%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1139
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1140
    0x0e10f010, 0x0f10f010,
1141
    "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %{R:APSR_nzcv%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1142
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1143
    0x0e100010, 0x0f100010,
1144
    "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1145
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1146
    0x0e000010, 0x0f100010,
1147
    "mcr%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1148
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1149
    0x0c000000, 0x0e100000, "stc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1150
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1151
    0x0c100000, 0x0e100000, "ldc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1152
1153
  /* V6 coprocessor instructions.  */
1154
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1155
    0xfc500000, 0xfff00000,
1156
    "mrrc2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
1157
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1158
    0xfc400000, 0xfff00000,
1159
    "mcrr2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19R, %{R:cr%0-3d%}"},
1160
1161
  /* V5 coprocessor instructions.  */
1162
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1163
    0xfc100000, 0xfe100000, "ldc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1164
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1165
    0xfc000000, 0xfe100000, "stc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
1166
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1167
    0xfe000000, 0xff000010,
1168
    "cdp2%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1169
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1170
    0xfe000010, 0xff100010,
1171
    "mcr2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1172
  {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1173
    0xfe100010, 0xff100010,
1174
    "mrc2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
1175
1176
  {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1177
};
1178
1179
/* Neon opcode table:  This does not encode the top byte -- that is
1180
   checked by the print_insn_neon routine, as it depends on whether we are
1181
   doing thumb32 or arm32 disassembly.  */
1182
1183
/* print_insn_neon recognizes the following format control codes:
1184
1185
   %%     %
1186
1187
   %c     print condition code
1188
   %u     print condition code (unconditional in ARM mode,
1189
                          UNPREDICTABLE if not AL in Thumb)
1190
   %A     print v{st,ld}[1234] operands
1191
   %B     print v{st,ld}[1234] any one operands
1192
   %C     print v{st,ld}[1234] single->all operands
1193
   %D     print scalar
1194
   %E     print vmov, vmvn, vorr, vbic encoded constant
1195
   %F     print vtbl,vtbx register list
1196
1197
   %<bitfield>r   print as an ARM register
1198
   %<bitfield>d   print the bitfield in decimal
1199
   %<bitfield>e         print the 2^N - bitfield in decimal
1200
   %<bitfield>D   print as a NEON D register
1201
   %<bitfield>Q   print as a NEON Q register
1202
   %<bitfield>R   print as a NEON D or Q register
1203
   %<bitfield>Sn  print byte scaled width limited by n
1204
   %<bitfield>Tn  print short scaled width limited by n
1205
   %<bitfield>Un  print long scaled width limited by n
1206
1207
   %<bitfield>'c  print specified char iff bitfield is all ones
1208
   %<bitfield>`c  print specified char iff bitfield is all zeroes
1209
   %<bitfield>?ab...    select from array of values in big endian order.  */
1210
1211
static const struct opcode32 neon_opcodes[] =
1212
{
1213
  /* Extract.  */
1214
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1215
    0xf2b00840, 0xffb00850,
1216
    "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
1217
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218
    0xf2b00000, 0xffb00810,
1219
    "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
1220
1221
  /* Data transfer between ARM and NEON registers.  */
1222
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1223
    0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1224
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1225
    0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1226
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1227
    0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1228
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1229
    0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1230
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1231
    0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1232
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1233
    0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1234
1235
  /* Move data element to all lanes.  */
1236
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1237
    0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %{R:%0-3,5D[%19d]%}"},
1238
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1239
    0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %{R:%0-3,5D[%18-19d]%}"},
1240
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1241
    0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %{R:%0-3,5D[%17-19d]%}"},
1242
1243
  /* Table lookup.  */
1244
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1245
    0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1246
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1247
    0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1248
1249
  /* Half-precision conversions.  */
1250
  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1251
    0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1252
  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1253
    0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1254
1255
  /* NEON fused multiply add instructions.  */
1256
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1257
    0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1258
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1259
    0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1260
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1261
    0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1262
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1263
    0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1264
1265
  /* BFloat16 instructions.  */
1266
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1267
    0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1268
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1269
    0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
1270
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1271
    0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1272
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1273
    0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1274
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1275
    0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1276
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1277
    0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %{R:%0-2D[%3,5d]%}"},
1278
1279
  /* Matrix Multiply instructions.  */
1280
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1281
    0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1282
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1283
    0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1284
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1285
    0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1286
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1287
    0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1288
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1289
    0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
1290
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1291
    0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
1292
1293
  /* Two registers, miscellaneous.  */
1294
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1295
    0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1296
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1297
    0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1298
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1299
    0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1300
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1301
    0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1302
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1303
    0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1304
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1305
    0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1306
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1307
    0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1308
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1309
    0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1310
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1311
    0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1312
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1313
    0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1314
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1315
    0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1316
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317
    0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1318
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1319
    0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1320
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321
    0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1322
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323
    0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1324
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1325
    0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1326
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327
    0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1328
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329
    0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1330
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331
    0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1332
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333
    0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1334
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335
    0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1336
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337
    0xf3b20300, 0xffb30fd0,
1338
    "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, %{I:#%18-19S2%}"},
1339
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1340
    0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1341
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1342
    0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1343
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344
    0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1345
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1346
    0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1347
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348
    0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1349
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350
    0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1351
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1352
    0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1353
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354
    0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1355
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356
    0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1357
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1358
    0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1359
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360
    0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1361
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362
    0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1363
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1364
    0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1365
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1366
    0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1367
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368
    0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1369
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1370
    0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1371
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1372
    0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1373
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374
    0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1375
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1376
    0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
1377
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378
    0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1379
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380
    0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1381
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382
    0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1383
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384
    0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1385
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386
    0xf3bb0600, 0xffbf0e10,
1387
    "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1388
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1389
    0xf3b70600, 0xffbf0e10,
1390
    "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1391
1392
  /* Three registers of the same length.  */
1393
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1394
    0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1395
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1396
    0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1397
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1398
    0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1399
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1400
    0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1401
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1402
    0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1403
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1404
    0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1405
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1406
    0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1407
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1408
    0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1409
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1410
    0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1411
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1412
    0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1413
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1414
    0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1415
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416
    0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1417
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418
    0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1419
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420
    0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1421
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422
    0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1423
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424
    0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1425
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426
    0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1427
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428
    0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1429
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430
    0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1431
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432
    0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1433
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1434
    0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1435
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436
    0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1437
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1438
    0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1439
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440
    0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1441
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1442
    0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1443
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444
    0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1445
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1446
    0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1447
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448
    0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1449
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1450
    0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1451
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452
    0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1453
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1454
    0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1455
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456
    0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1457
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1458
    0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1459
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1460
    0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1461
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1462
    0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1463
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1464
    0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1465
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1466
    0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1467
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1468
    0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1469
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1470
    0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1471
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1472
    0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1473
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1474
    0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1475
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476
    0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1477
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1478
    0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1479
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480
    0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1481
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1482
    0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1483
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484
    0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1485
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1486
    0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1487
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488
    0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1489
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1490
    0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1491
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492
    0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1493
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1494
    0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1495
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496
    0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1497
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1498
    0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1499
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500
    0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1501
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1502
    0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1503
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504
    0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1505
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506
    0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1507
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508
    0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1509
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510
    0xf2000b00, 0xff800f10,
1511
    "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1512
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1513
    0xf2000b10, 0xff800f10,
1514
    "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1515
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516
    0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1517
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518
    0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1519
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520
    0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1521
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522
    0xf3000b00, 0xff800f10,
1523
    "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1524
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1525
    0xf2000000, 0xfe800f10,
1526
    "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528
    0xf2000010, 0xfe800f10,
1529
    "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1530
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1531
    0xf2000100, 0xfe800f10,
1532
    "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534
    0xf2000200, 0xfe800f10,
1535
    "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1537
    0xf2000210, 0xfe800f10,
1538
    "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1539
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540
    0xf2000300, 0xfe800f10,
1541
    "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1542
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1543
    0xf2000310, 0xfe800f10,
1544
    "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1545
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546
    0xf2000400, 0xfe800f10,
1547
    "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1548
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1549
    0xf2000410, 0xfe800f10,
1550
    "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1551
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552
    0xf2000500, 0xfe800f10,
1553
    "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1554
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555
    0xf2000510, 0xfe800f10,
1556
    "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1557
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558
    0xf2000600, 0xfe800f10,
1559
    "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561
    0xf2000610, 0xfe800f10,
1562
    "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564
    0xf2000700, 0xfe800f10,
1565
    "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1566
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567
    0xf2000710, 0xfe800f10,
1568
    "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1569
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570
    0xf2000910, 0xfe800f10,
1571
    "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1572
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573
    0xf2000a00, 0xfe800f10,
1574
    "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576
    0xf2000a10, 0xfe800f10,
1577
    "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1578
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1579
    0xf3000b10, 0xff800f10,
1580
    "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1582
    0xf3000c10, 0xff800f10,
1583
    "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1584
1585
  /* One register and an immediate value.  */
1586
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587
    0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1588
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1589
    0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1590
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591
    0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1592
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593
    0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1594
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1595
    0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1596
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597
    0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1598
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599
    0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1600
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601
    0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1602
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603
    0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1604
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605
    0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1606
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1607
    0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1608
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609
    0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1610
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611
    0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1612
1613
  /* Two registers and a shift amount.  */
1614
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1615
    0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1616
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617
    0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1618
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619
    0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1620
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621
    0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1622
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623
    0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1624
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625
    0xf2880950, 0xfeb80fd0,
1626
    "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
1627
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628
    0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, %{I:#%16-18d%}"},
1629
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630
    0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1631
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632
    0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1633
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634
    0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1635
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636
    0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1637
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638
    0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1639
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640
    0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1641
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642
    0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1643
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644
    0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1645
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646
    0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1647
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648
    0xf2900950, 0xfeb00fd0,
1649
    "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
1650
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651
    0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, %{I:#%16-19d%}"},
1652
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653
    0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1654
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655
    0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1656
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1657
    0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1658
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1659
    0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
1660
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1661
    0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
1662
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1663
    0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1664
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1665
    0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1666
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1667
    0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1668
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1669
    0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1670
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1671
    0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1672
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1673
    0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1674
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1675
    0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, %{I:#%16-20d%}"},
1676
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1677
    0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1678
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1679
    0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1680
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1681
    0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1682
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1683
    0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
1684
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685
    0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
1686
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687
    0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1688
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689
    0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1690
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691
    0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1692
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693
    0xf2a00950, 0xfea00fd0,
1694
    "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
1695
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696
    0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1697
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698
    0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1699
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700
    0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1701
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702
    0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1703
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704
    0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1705
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706
    0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1707
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708
    0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1709
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710
    0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1711
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712
    0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
1713
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714
    0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1715
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1716
    0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1717
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718
    0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1719
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1720
    0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1721
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1722
    0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1723
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724
    0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1725
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726
    0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1727
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1728
    0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
1729
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730
    0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
1731
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732
    0xf2a00e10, 0xfea00e90,
1733
    "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1734
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1735
    0xf2a00c10, 0xfea00e90,
1736
    "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
1737
1738
  /* Three registers of different lengths.  */
1739
  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1740
    0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1741
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1742
    0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1743
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1744
    0xf2800400, 0xff800f50,
1745
    "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1746
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747
    0xf2800600, 0xff800f50,
1748
    "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1749
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1750
    0xf2800900, 0xff800f50,
1751
    "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1752
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753
    0xf2800b00, 0xff800f50,
1754
    "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1755
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1756
    0xf2800d00, 0xff800f50,
1757
    "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1758
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759
    0xf3800400, 0xff800f50,
1760
    "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1761
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1762
    0xf3800600, 0xff800f50,
1763
    "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1764
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765
    0xf2800000, 0xfe800f50,
1766
    "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1767
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1768
    0xf2800100, 0xfe800f50,
1769
    "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1770
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771
    0xf2800200, 0xfe800f50,
1772
    "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1773
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1774
    0xf2800300, 0xfe800f50,
1775
    "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1776
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777
    0xf2800500, 0xfe800f50,
1778
    "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1779
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1780
    0xf2800700, 0xfe800f50,
1781
    "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1782
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1783
    0xf2800800, 0xfe800f50,
1784
    "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1785
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786
    0xf2800a00, 0xfe800f50,
1787
    "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1788
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789
    0xf2800c00, 0xfe800f50,
1790
    "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1791
1792
  /* Two registers and a scalar.  */
1793
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794
    0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1795
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796
    0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1797
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1798
    0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1799
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800
    0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1801
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802
    0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1803
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804
    0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1805
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1806
    0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1807
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1808
    0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1809
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810
    0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1811
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812
    0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1813
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1814
    0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1815
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1816
    0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1817
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818
    0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1819
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1820
    0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1821
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1822
    0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1823
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1824
    0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1825
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1826
    0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1827
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1828
    0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1829
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1830
    0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1831
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1832
    0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1833
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1834
    0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1835
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1836
    0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1837
  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1838
    0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1839
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1840
    0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1841
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842
    0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1843
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1844
    0xf2800240, 0xfe800f50,
1845
    "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1846
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1847
    0xf2800640, 0xfe800f50,
1848
    "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1849
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1850
    0xf2800a40, 0xfe800f50,
1851
    "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1852
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1853
    0xf2800e40, 0xff800f50,
1854
   "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1855
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1856
    0xf2800f40, 0xff800f50,
1857
   "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1858
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1859
    0xf3800e40, 0xff800f50,
1860
   "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1861
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1862
    0xf3800f40, 0xff800f50,
1863
   "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1864
  },
1865
1866
  /* Element and structure load/store.  */
1867
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868
    0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1869
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870
    0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1871
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872
    0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1873
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874
    0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1875
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876
    0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1877
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878
    0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1879
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880
    0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1881
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1882
    0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1883
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884
    0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1885
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886
    0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1887
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1888
    0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1889
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1890
    0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1891
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1892
    0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1893
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1894
    0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1895
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1896
    0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1897
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1898
    0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1899
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1900
    0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1901
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1902
    0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1903
  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1904
    0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1905
1906
  {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1907
};
1908
1909
/* mve opcode table.  */
1910
1911
/* print_insn_mve recognizes the following format control codes:
1912
1913
   %%     %
1914
1915
   %a     print '+' or '-' or imm offset in vldr[bhwd] and
1916
      vstr[bhwd]
1917
   %c     print condition code
1918
   %d     print addr mode of MVE vldr[bhw] and vstr[bhw]
1919
   %u     print 'U' (unsigned) or 'S' for various mve instructions
1920
   %i     print MVE predicate(s) for vpt and vpst
1921
   %j     print a 5-bit immediate from hw2[14:12,7:6]
1922
   %k     print 48 if the 7th position bit is set else print 64.
1923
   %m     print rounding mode for vcvt and vrint
1924
   %n     print vector comparison code for predicated instruction
1925
   %s     print size for various vcvt instructions
1926
   %v     print vector predicate for instruction in predicated
1927
      block
1928
   %o     print offset scaled for vldr[hwd] and vstr[hwd]
1929
   %w     print writeback mode for MVE v{st,ld}[24]
1930
   %B     print v{st,ld}[24] any one operands
1931
   %E     print vmov, vmvn, vorr, vbic encoded constant
1932
   %N     print generic index for vmov
1933
   %T     print bottom ('b') or top ('t') of source register
1934
   %X     print exchange field in vmla* instructions
1935
1936
   %<bitfield>r   print as an ARM register
1937
   %<bitfield>d   print the bitfield in decimal
1938
   %<bitfield>A   print accumulate or not
1939
   %<bitfield>c   print bitfield as a condition code
1940
   %<bitfield>C   print bitfield as an inverted condition code
1941
   %<bitfield>Q   print as a MVE Q register
1942
   %<bitfield>F   print as a MVE S register
1943
   %<bitfield>Z   as %<>r but r15 is ZR instead of PC and r13 is
1944
      UNPREDICTABLE
1945
1946
   %<bitfield>S   as %<>r but r15 or r13 is UNPREDICTABLE
1947
   %<bitfield>s   print size for vector predicate & non VMOV instructions
1948
   %<bitfield>I   print carry flag or not
1949
   %<bitfield>i   print immediate for vstr/vldr reg +/- imm
1950
   %<bitfield>h   print high half of 64-bit destination reg
1951
   %<bitfield>k   print immediate for vector conversion instruction
1952
   %<bitfield>l   print low half of 64-bit destination reg
1953
   %<bitfield>o   print rotate value for vcmul
1954
   %<bitfield>u   print immediate value for vddup/vdwdup
1955
   %<bitfield>x   print the bitfield in hex.
1956
  */
1957
1958
static const struct mopcode32 mve_opcodes[] =
1959
{
1960
  /* MVE.  */
1961
1962
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1963
   MVE_VPST,
1964
   0xfe310f4d, 0xffbf1fff,
1965
   "vpst%i"
1966
  },
1967
1968
  /* Floating point VPT T1.  */
1969
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
1970
   MVE_VPT_FP_T1,
1971
   0xee310f00, 0xefb10f50,
1972
   "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1973
  /* Floating point VPT T2.  */
1974
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
1975
   MVE_VPT_FP_T2,
1976
   0xee310f40, 0xefb10f50,
1977
   "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1978
1979
  /* Vector VPT T1.  */
1980
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1981
   MVE_VPT_VEC_T1,
1982
   0xfe010f00, 0xff811f51,
1983
   "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1984
  /* Vector VPT T2.  */
1985
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1986
   MVE_VPT_VEC_T2,
1987
   0xfe010f01, 0xff811f51,
1988
   "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1989
  /* Vector VPT T3.  */
1990
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1991
   MVE_VPT_VEC_T3,
1992
   0xfe011f00, 0xff811f50,
1993
   "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1994
  /* Vector VPT T4.  */
1995
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1996
   MVE_VPT_VEC_T4,
1997
   0xfe010f40, 0xff811f70,
1998
   "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
1999
  /* Vector VPT T5.  */
2000
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2001
   MVE_VPT_VEC_T5,
2002
   0xfe010f60, 0xff811f70,
2003
   "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2004
  /* Vector VPT T6.  */
2005
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2006
   MVE_VPT_VEC_T6,
2007
   0xfe011f40, 0xff811f50,
2008
   "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2009
2010
  /* Vector VBIC immediate.  */
2011
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2012
   MVE_VBIC_IMM,
2013
   0xef800070, 0xefb81070,
2014
   "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2015
2016
  /* Vector VBIC register.  */
2017
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2018
   MVE_VBIC_REG,
2019
   0xef100150, 0xffb11f51,
2020
   "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2021
2022
  /* Vector VABAV.  */
2023
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2024
   MVE_VABAV,
2025
   0xee800f01, 0xefc10f51,
2026
   "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2027
2028
  /* Vector VABD floating point.  */
2029
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2030
   MVE_VABD_FP,
2031
   0xff200d40, 0xffa11f51,
2032
   "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2033
2034
  /* Vector VABD.  */
2035
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2036
   MVE_VABD_VEC,
2037
   0xef000740, 0xef811f51,
2038
   "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2039
2040
  /* Vector VABS floating point.  */
2041
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2042
   MVE_VABS_FP,
2043
   0xFFB10740, 0xFFB31FD1,
2044
   "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2045
  /* Vector VABS.  */
2046
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2047
   MVE_VABS_VEC,
2048
   0xffb10340, 0xffb31fd1,
2049
   "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2050
2051
  /* Vector VADD floating point T1.  */
2052
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2053
   MVE_VADD_FP_T1,
2054
   0xef000d40, 0xffa11f51,
2055
   "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2056
  /* Vector VADD floating point T2.  */
2057
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2058
   MVE_VADD_FP_T2,
2059
   0xee300f40, 0xefb11f70,
2060
   "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2061
  /* Vector VADD T1.  */
2062
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2063
   MVE_VADD_VEC_T1,
2064
   0xef000840, 0xff811f51,
2065
   "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2066
  /* Vector VADD T2.  */
2067
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2068
   MVE_VADD_VEC_T2,
2069
   0xee010f40, 0xff811f70,
2070
   "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2071
2072
  /* Vector VADDLV.  */
2073
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2074
   MVE_VADDLV,
2075
   0xee890f00, 0xef8f1fd1,
2076
   "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2077
2078
  /* Vector VADDV.  */
2079
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2080
   MVE_VADDV,
2081
   0xeef10f00, 0xeff31fd1,
2082
   "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2083
2084
  /* Vector VADC.  */
2085
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2086
   MVE_VADC,
2087
   0xee300f00, 0xffb10f51,
2088
   "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2089
2090
  /* Vector VAND.  */
2091
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2092
   MVE_VAND,
2093
   0xef000150, 0xffb11f51,
2094
   "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2095
2096
  /* Vector VBRSR register.  */
2097
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2098
   MVE_VBRSR,
2099
   0xfe011e60, 0xff811f70,
2100
   "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2101
2102
  /* Vector VCADD floating point.  */
2103
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2104
   MVE_VCADD_FP,
2105
   0xfc800840, 0xfea11f51,
2106
   "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%24o%}"},
2107
2108
  /* Vector VCADD.  */
2109
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2110
   MVE_VCADD_VEC,
2111
   0xfe000f00, 0xff810f51,
2112
   "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
2113
2114
  /* Vector VCLS.  */
2115
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2116
   MVE_VCLS,
2117
   0xffb00440, 0xffb31fd1,
2118
   "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2119
2120
  /* Vector VCLZ.  */
2121
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2122
   MVE_VCLZ,
2123
   0xffb004c0, 0xffb31fd1,
2124
   "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2125
2126
  /* Vector VCMLA.  */
2127
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2128
   MVE_VCMLA_FP,
2129
   0xfc200840, 0xfe211f51,
2130
   "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%23-24o%}"},
2131
2132
  /* Vector VCMP floating point T1.  */
2133
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2134
   MVE_VCMP_FP_T1,
2135
   0xee310f00, 0xeff1ef50,
2136
   "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2137
2138
  /* Vector VCMP floating point T2.  */
2139
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2140
   MVE_VCMP_FP_T2,
2141
   0xee310f40, 0xeff1ef50,
2142
   "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2143
2144
  /* Vector VCMP T1.  */
2145
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2146
   MVE_VCMP_VEC_T1,
2147
   0xfe010f00, 0xffc1ff51,
2148
   "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2149
  /* Vector VCMP T2.  */
2150
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2151
   MVE_VCMP_VEC_T2,
2152
   0xfe010f01, 0xffc1ff51,
2153
   "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2154
  /* Vector VCMP T3.  */
2155
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2156
   MVE_VCMP_VEC_T3,
2157
   0xfe011f00, 0xffc1ff50,
2158
   "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2159
  /* Vector VCMP T4.  */
2160
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2161
   MVE_VCMP_VEC_T4,
2162
   0xfe010f40, 0xffc1ff70,
2163
   "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2164
  /* Vector VCMP T5.  */
2165
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2166
   MVE_VCMP_VEC_T5,
2167
   0xfe010f60, 0xffc1ff70,
2168
   "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2169
  /* Vector VCMP T6.  */
2170
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2171
   MVE_VCMP_VEC_T6,
2172
   0xfe011f40, 0xffc1ff50,
2173
   "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2174
2175
  /* Vector VDUP.  */
2176
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2177
   MVE_VDUP,
2178
   0xeea00b10, 0xffb10f5f,
2179
   "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2180
2181
  /* Vector VEOR.  */
2182
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2183
   MVE_VEOR,
2184
   0xff000150, 0xffd11f51,
2185
   "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2186
2187
  /* Vector VFMA, vector * scalar.  */
2188
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2189
   MVE_VFMA_FP_SCALAR,
2190
   0xee310e40, 0xefb11f70,
2191
   "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2192
2193
  /* Vector VFMA floating point.  */
2194
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2195
   MVE_VFMA_FP,
2196
   0xef000c50, 0xffa11f51,
2197
   "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2198
2199
  /* Vector VFMS floating point.  */
2200
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2201
   MVE_VFMS_FP,
2202
   0xef200c50, 0xffa11f51,
2203
   "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2204
2205
  /* Vector VFMAS, vector * scalar.  */
2206
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2207
   MVE_VFMAS_FP_SCALAR,
2208
   0xee311e40, 0xefb11f70,
2209
   "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2210
2211
  /* Vector VHADD T1.  */
2212
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2213
   MVE_VHADD_T1,
2214
   0xef000040, 0xef811f51,
2215
   "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2216
2217
  /* Vector VHADD T2.  */
2218
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2219
   MVE_VHADD_T2,
2220
   0xee000f40, 0xef811f70,
2221
   "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2222
2223
  /* Vector VHSUB T1.  */
2224
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2225
   MVE_VHSUB_T1,
2226
   0xef000240, 0xef811f51,
2227
   "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2228
2229
  /* Vector VHSUB T2.  */
2230
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2231
   MVE_VHSUB_T2,
2232
   0xee001f40, 0xef811f70,
2233
   "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2234
2235
  /* Vector VCMUL.  */
2236
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2237
   MVE_VCMUL_FP,
2238
   0xee300e00, 0xefb10f50,
2239
   "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%0,12o%}"},
2240
2241
   /* Vector VCTP.  */
2242
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2243
   MVE_VCTP,
2244
   0xf000e801, 0xffc0ffff,
2245
   "vctp%v.%20-21s\t%16-19r"},
2246
2247
  /* Vector VDUP.  */
2248
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2249
   MVE_VDUP,
2250
   0xeea00b10, 0xffb10f5f,
2251
   "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2252
2253
  /* Vector VRHADD.  */
2254
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2255
   MVE_VRHADD,
2256
   0xef000140, 0xef811f51,
2257
   "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2258
2259
  /* Vector VCVT.  */
2260
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2261
   MVE_VCVT_FP_FIX_VEC,
2262
   0xef800c50, 0xef801cd1,
2263
   "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, %{I:#%16-21k%}"},
2264
2265
  /* Vector VCVT.  */
2266
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2267
   MVE_VCVT_BETWEEN_FP_INT,
2268
   0xffb30640, 0xffb31e51,
2269
   "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2270
2271
  /* Vector VCVT between single and half-precision float, bottom half.  */
2272
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2273
   MVE_VCVT_FP_HALF_FP,
2274
   0xee3f0e01, 0xefbf1fd1,
2275
   "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2276
2277
  /* Vector VCVT between single and half-precision float, top half.  */
2278
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2279
   MVE_VCVT_FP_HALF_FP,
2280
   0xee3f1e01, 0xefbf1fd1,
2281
   "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2282
2283
  /* Vector VCVT.  */
2284
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2285
   MVE_VCVT_FROM_FP_TO_INT,
2286
   0xffb30040, 0xffb31c51,
2287
   "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2288
2289
  /* Vector VDDUP.  */
2290
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2291
   MVE_VDDUP,
2292
   0xee011f6e, 0xff811f7e,
2293
   "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
2294
2295
  /* Vector VDWDUP.  */
2296
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2297
   MVE_VDWDUP,
2298
   0xee011f60, 0xff811f70,
2299
   "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
2300
2301
  /* Vector VHCADD.  */
2302
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2303
   MVE_VHCADD,
2304
   0xee000f00, 0xff810f51,
2305
   "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
2306
2307
  /* Vector VIWDUP.  */
2308
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2309
   MVE_VIWDUP,
2310
   0xee010f60, 0xff811f70,
2311
   "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
2312
2313
  /* Vector VIDUP.  */
2314
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2315
   MVE_VIDUP,
2316
   0xee010f6e, 0xff811f7e,
2317
   "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
2318
2319
  /* Vector VLD2.  */
2320
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2321
   MVE_VLD2,
2322
   0xfc901e00, 0xff901e5f,
2323
   "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2324
2325
  /* Vector VLD4.  */
2326
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2327
   MVE_VLD4,
2328
   0xfc901e01, 0xff901e1f,
2329
   "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2330
2331
  /* Vector VLDRB gather load.  */
2332
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2333
   MVE_VLDRB_GATHER_T1,
2334
   0xec900e00, 0xefb01e50,
2335
   "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2336
2337
  /* Vector VLDRH gather load.  */
2338
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2339
   MVE_VLDRH_GATHER_T2,
2340
   0xec900e10, 0xefb01e50,
2341
   "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2342
2343
  /* Vector VLDRW gather load.  */
2344
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2345
   MVE_VLDRW_GATHER_T3,
2346
   0xfc900f40, 0xffb01fd0,
2347
   "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2348
2349
  /* Vector VLDRD gather load.  */
2350
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2351
   MVE_VLDRD_GATHER_T4,
2352
   0xec900fd0, 0xefb01fd0,
2353
   "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2354
2355
  /* Vector VLDRW gather load.  */
2356
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2357
   MVE_VLDRW_GATHER_T5,
2358
   0xfd101e00, 0xff111f00,
2359
   "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
2360
2361
  /* Vector VLDRD gather load, variant T6.  */
2362
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2363
   MVE_VLDRD_GATHER_T6,
2364
   0xfd101f00, 0xff111f00,
2365
   "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
2366
2367
  /* Vector VLDRB.  */
2368
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2369
   MVE_VLDRB_T1,
2370
   0xec100e00, 0xee581e00,
2371
   "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2372
2373
  /* Vector VLDRH.  */
2374
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2375
   MVE_VLDRH_T2,
2376
   0xec180e00, 0xee581e00,
2377
   "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2378
2379
  /* Vector VLDRB unsigned, variant T5.  */
2380
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2381
   MVE_VLDRB_T5,
2382
   0xec101e00, 0xfe101f80,
2383
   "vldrb%v.u8\t%13-15,22Q, %d"},
2384
2385
  /* Vector VLDRH unsigned, variant T6.  */
2386
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2387
   MVE_VLDRH_T6,
2388
   0xec101e80, 0xfe101f80,
2389
   "vldrh%v.u16\t%13-15,22Q, %d"},
2390
2391
  /* Vector VLDRW unsigned, variant T7.  */
2392
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2393
   MVE_VLDRW_T7,
2394
   0xec101f00, 0xfe101f80,
2395
   "vldrw%v.u32\t%13-15,22Q, %d"},
2396
2397
  /* Vector VMAX.  */
2398
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2399
   MVE_VMAX,
2400
   0xef000640, 0xef811f51,
2401
   "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2402
2403
  /* Vector VMAXA.  */
2404
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2405
   MVE_VMAXA,
2406
   0xee330e81, 0xffb31fd1,
2407
   "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2408
2409
  /* Vector VMAXNM floating point.  */
2410
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2411
   MVE_VMAXNM_FP,
2412
   0xff000f50, 0xffa11f51,
2413
   "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2414
2415
  /* Vector VMAXNMA floating point.  */
2416
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2417
   MVE_VMAXNMA_FP,
2418
   0xee3f0e81, 0xefbf1fd1,
2419
   "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2420
2421
  /* Vector VMAXNMV floating point.  */
2422
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2423
   MVE_VMAXNMV_FP,
2424
   0xeeee0f00, 0xefff0fd1,
2425
   "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2426
2427
  /* Vector VMAXNMAV floating point.  */
2428
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2429
   MVE_VMAXNMAV_FP,
2430
   0xeeec0f00, 0xefff0fd1,
2431
   "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2432
2433
  /* Vector VMAXV.  */
2434
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2435
   MVE_VMAXV,
2436
   0xeee20f00, 0xeff30fd1,
2437
   "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2438
2439
  /* Vector VMAXAV.  */
2440
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2441
   MVE_VMAXAV,
2442
   0xeee00f00, 0xfff30fd1,
2443
   "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2444
2445
  /* Vector VMIN.  */
2446
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2447
   MVE_VMIN,
2448
   0xef000650, 0xef811f51,
2449
   "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2450
2451
  /* Vector VMINA.  */
2452
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2453
   MVE_VMINA,
2454
   0xee331e81, 0xffb31fd1,
2455
   "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2456
2457
  /* Vector VMINNM floating point.  */
2458
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2459
   MVE_VMINNM_FP,
2460
   0xff200f50, 0xffa11f51,
2461
   "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2462
2463
  /* Vector VMINNMA floating point.  */
2464
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2465
   MVE_VMINNMA_FP,
2466
   0xee3f1e81, 0xefbf1fd1,
2467
   "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2468
2469
  /* Vector VMINNMV floating point.  */
2470
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2471
   MVE_VMINNMV_FP,
2472
   0xeeee0f80, 0xefff0fd1,
2473
   "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2474
2475
  /* Vector VMINNMAV floating point.  */
2476
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2477
   MVE_VMINNMAV_FP,
2478
   0xeeec0f80, 0xefff0fd1,
2479
   "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2480
2481
  /* Vector VMINV.  */
2482
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2483
   MVE_VMINV,
2484
   0xeee20f80, 0xeff30fd1,
2485
   "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2486
2487
  /* Vector VMINAV.  */
2488
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2489
   MVE_VMINAV,
2490
   0xeee00f80, 0xfff30fd1,
2491
   "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2492
2493
  /* Vector VMLA.  */
2494
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2495
   MVE_VMLA,
2496
   0xee010e40, 0xef811f70,
2497
   "vmla%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2498
2499
  /* Vector VMLALDAV.  Note must appear before VMLADAV due to instruction
2500
     opcode aliasing.  */
2501
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2502
   MVE_VMLALDAV,
2503
   0xee801e00, 0xef801f51,
2504
   "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2505
2506
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2507
   MVE_VMLALDAV,
2508
   0xee800e00, 0xef801f51,
2509
   "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2510
2511
  /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0.  */
2512
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2513
   MVE_VMLADAV_T1,
2514
   0xeef00e00, 0xeff01f51,
2515
   "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2516
2517
  /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0.  */
2518
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2519
   MVE_VMLADAV_T2,
2520
   0xeef00f00, 0xeff11f51,
2521
   "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2522
2523
  /* Vector VMLADAV T1 variant.  */
2524
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2525
   MVE_VMLADAV_T1,
2526
   0xeef01e00, 0xeff01f51,
2527
   "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2528
2529
  /* Vector VMLADAV T2 variant.  */
2530
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2531
   MVE_VMLADAV_T2,
2532
   0xeef01f00, 0xeff11f51,
2533
   "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2534
2535
  /* Vector VMLAS.  */
2536
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2537
   MVE_VMLAS,
2538
   0xee011e40, 0xef811f70,
2539
   "vmlas%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2540
2541
  /* Vector VRMLSLDAVH.  Note must appear before VMLSDAV due to instruction
2542
     opcode aliasing.  */
2543
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2544
   MVE_VRMLSLDAVH,
2545
   0xfe800e01, 0xff810f51,
2546
   "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2547
2548
  /* Vector VMLSLDAV.  Note must appear before VMLSDAV due to instruction
2549
     opcdoe aliasing.  */
2550
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2551
   MVE_VMLSLDAV,
2552
   0xee800e01, 0xff800f51,
2553
   "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2554
2555
  /* Vector VMLSDAV T1 Variant.  */
2556
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2557
   MVE_VMLSDAV_T1,
2558
   0xeef00e01, 0xfff00f51,
2559
   "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2560
2561
  /* Vector VMLSDAV T2 Variant.  */
2562
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2563
   MVE_VMLSDAV_T2,
2564
   0xfef00e01, 0xfff10f51,
2565
   "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2566
2567
  /* Vector VMOV between gpr and half precision register, op == 0.  */
2568
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2569
   MVE_VMOV_HFP_TO_GP,
2570
   0xee000910, 0xfff00f7f,
2571
   "vmov.f16\t%7,16-19F, %12-15r"},
2572
2573
  /* Vector VMOV between gpr and half precision register, op == 1.  */
2574
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2575
   MVE_VMOV_HFP_TO_GP,
2576
   0xee100910, 0xfff00f7f,
2577
   "vmov.f16\t%12-15r, %7,16-19F"},
2578
2579
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2580
   MVE_VMOV_GP_TO_VEC_LANE,
2581
   0xee000b10, 0xff900f1f,
2582
   "vmov%c.%5-6,21-22s\t%{R:%17-19,7Q[%N]%}, %12-15r"},
2583
2584
  /* Vector VORR immediate to vector.
2585
     NOTE: MVE_VORR_IMM must appear in the table
2586
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2587
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2588
   MVE_VORR_IMM,
2589
   0xef800050, 0xefb810f0,
2590
   "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2591
2592
  /* Vector VQSHL T2 Variant.
2593
     NOTE: MVE_VQSHL_T2 must appear in the table before
2594
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2595
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2596
   MVE_VQSHL_T2,
2597
   0xef800750, 0xef801fd1,
2598
   "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2599
2600
  /* Vector VQSHLU T3 Variant
2601
     NOTE: MVE_VQSHL_T2 must appear in the table before
2602
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2603
2604
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2605
   MVE_VQSHLU_T3,
2606
   0xff800650, 0xff801fd1,
2607
   "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2608
2609
  /* Vector VRSHR
2610
     NOTE: MVE_VRSHR must appear in the table before
2611
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2612
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2613
   MVE_VRSHR,
2614
   0xef800250, 0xef801fd1,
2615
   "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2616
2617
  /* Vector VSHL.
2618
     NOTE: MVE_VSHL must appear in the table before
2619
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2620
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2621
   MVE_VSHL_T1,
2622
   0xef800550, 0xff801fd1,
2623
   "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2624
2625
  /* Vector VSHR
2626
     NOTE: MVE_VSHR must appear in the table before
2627
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2628
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2629
   MVE_VSHR,
2630
   0xef800050, 0xef801fd1,
2631
   "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2632
2633
  /* Vector VSLI
2634
     NOTE: MVE_VSLI must appear in the table before
2635
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2636
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2637
   MVE_VSLI,
2638
   0xff800550, 0xff801fd1,
2639
   "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2640
2641
  /* Vector VSRI
2642
     NOTE: MVE_VSRI must appear in the table before
2643
     before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2644
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2645
   MVE_VSRI,
2646
   0xff800450, 0xff801fd1,
2647
   "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2648
2649
  /* Vector VMOV immediate to vector,
2650
     undefinded for cmode == 1111 */
2651
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2652
   MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2653
2654
  /* Vector VMOV immediate to vector,
2655
     cmode == 1101 */
2656
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2657
   MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2658
   "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2659
2660
  /* Vector VMOV immediate to vector.  */
2661
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2662
   MVE_VMOV_IMM_TO_VEC,
2663
   0xef800050, 0xefb810d0,
2664
   "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2665
2666
  /* Vector VMOV two 32-bit lanes to two gprs, idx = 0.  */
2667
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2668
   MVE_VMOV2_VEC_LANE_TO_GP,
2669
   0xec000f00, 0xffb01ff0,
2670
   "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}"},
2671
2672
  /* Vector VMOV two 32-bit lanes to two gprs, idx = 1.  */
2673
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2674
   MVE_VMOV2_VEC_LANE_TO_GP,
2675
   0xec000f10, 0xffb01ff0,
2676
   "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}"},
2677
2678
  /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0.  */
2679
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2680
   MVE_VMOV2_GP_TO_VEC_LANE,
2681
   0xec100f00, 0xffb01ff0,
2682
   "vmov%c\t%{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19r"},
2683
2684
  /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1.  */
2685
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2686
   MVE_VMOV2_GP_TO_VEC_LANE,
2687
   0xec100f10, 0xffb01ff0,
2688
   "vmov%c\t%{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19r"},
2689
2690
  /* Vector VMOV Vector lane to gpr.  */
2691
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2692
   MVE_VMOV_VEC_LANE_TO_GP,
2693
   0xee100b10, 0xff100f1f,
2694
   "vmov%c.%u%5-6,21-22s\t%12-15r, %{R:%17-19,7Q[%N]%}"},
2695
2696
  /* Vector VSHLL T1 Variant.  Note: VSHLL T1 must appear before MVE_VMOVL due
2697
     to instruction opcode aliasing.  */
2698
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2699
   MVE_VSHLL_T1,
2700
   0xeea00f40, 0xefa00fd1,
2701
   "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2702
2703
  /* Vector VMOVL long.  */
2704
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2705
   MVE_VMOVL,
2706
   0xeea00f40, 0xefa70fd1,
2707
   "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2708
2709
  /* Vector VMOV and narrow.  */
2710
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2711
   MVE_VMOVN,
2712
   0xfe310e81, 0xffb30fd1,
2713
   "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2714
2715
  /* Floating point move extract.  */
2716
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2717
   MVE_VMOVX,
2718
   0xfeb00a40, 0xffbf0fd0,
2719
   "vmovx.f16\t%22,12-15F, %5,0-3F"},
2720
2721
  /* Vector VMUL floating-point T1 variant.  */
2722
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2723
   MVE_VMUL_FP_T1,
2724
   0xff000d50, 0xffa11f51,
2725
   "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2726
2727
  /* Vector VMUL floating-point T2 variant.  */
2728
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2729
   MVE_VMUL_FP_T2,
2730
   0xee310e60, 0xefb11f70,
2731
   "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2732
2733
  /* Vector VMUL T1 variant.  */
2734
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2735
   MVE_VMUL_VEC_T1,
2736
   0xef000950, 0xff811f51,
2737
   "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2738
2739
  /* Vector VMUL T2 variant.  */
2740
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2741
   MVE_VMUL_VEC_T2,
2742
   0xee011e60, 0xff811f70,
2743
   "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2744
2745
  /* Vector VMULH.  */
2746
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2747
   MVE_VMULH,
2748
   0xee010e01, 0xef811f51,
2749
   "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2750
2751
  /* Vector VRMULH.  */
2752
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2753
   MVE_VRMULH,
2754
   0xee011e01, 0xef811f51,
2755
   "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2756
2757
  /* Vector VMULL integer.  */
2758
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2759
   MVE_VMULL_INT,
2760
   0xee010e00, 0xef810f51,
2761
   "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2762
2763
  /* Vector VMULL polynomial.  */
2764
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2765
   MVE_VMULL_POLY,
2766
   0xee310e00, 0xefb10f51,
2767
   "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2768
2769
  /* Vector VMVN immediate to vector.  */
2770
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2771
   MVE_VMVN_IMM,
2772
   0xef800070, 0xefb810f0,
2773
   "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2774
2775
  /* Vector VMVN register.  */
2776
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2777
   MVE_VMVN_REG,
2778
   0xffb005c0, 0xffbf1fd1,
2779
   "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2780
2781
  /* Vector VNEG floating point.  */
2782
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2783
   MVE_VNEG_FP,
2784
   0xffb107c0, 0xffb31fd1,
2785
   "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2786
2787
  /* Vector VNEG.  */
2788
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2789
   MVE_VNEG_VEC,
2790
   0xffb103c0, 0xffb31fd1,
2791
   "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2792
2793
  /* Vector VORN, vector bitwise or not.  */
2794
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2795
   MVE_VORN,
2796
   0xef300150, 0xffb11f51,
2797
   "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2798
2799
  /* Vector VORR register.  */
2800
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2801
   MVE_VORR_REG,
2802
   0xef200150, 0xffb11f51,
2803
   "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2804
2805
  /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
2806
     "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
2807
     MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
2808
     array.  */
2809
2810
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2811
   MVE_VMOV_VEC_TO_VEC,
2812
   0xef200150, 0xffb11f51,
2813
   "vmov%v\t%13-15,22Q, %17-19,7Q"},
2814
2815
  /* Vector VQDMULL T1 variant.  */
2816
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2817
   MVE_VQDMULL_T1,
2818
   0xee300f01, 0xefb10f51,
2819
   "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2820
2821
  /* Vector VPNOT.  */
2822
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2823
   MVE_VPNOT,
2824
   0xfe310f4d, 0xffffffff,
2825
   "vpnot%v"},
2826
2827
  /* Vector VPSEL.  */
2828
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2829
   MVE_VPSEL,
2830
   0xfe310f01, 0xffb11f51,
2831
   "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2832
2833
  /* Vector VQABS.  */
2834
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2835
   MVE_VQABS,
2836
   0xffb00740, 0xffb31fd1,
2837
   "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2838
2839
  /* Vector VQADD T1 variant.  */
2840
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2841
   MVE_VQADD_T1,
2842
   0xef000050, 0xef811f51,
2843
   "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2844
2845
  /* Vector VQADD T2 variant.  */
2846
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2847
   MVE_VQADD_T2,
2848
   0xee000f60, 0xef811f70,
2849
   "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2850
2851
  /* Vector VQDMULL T2 variant.  */
2852
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2853
   MVE_VQDMULL_T2,
2854
   0xee300f60, 0xefb10f70,
2855
   "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2856
2857
  /* Vector VQMOVN.  */
2858
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2859
   MVE_VQMOVN,
2860
   0xee330e01, 0xefb30fd1,
2861
   "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2862
2863
  /* Vector VQMOVUN.  */
2864
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2865
   MVE_VQMOVUN,
2866
   0xee310e81, 0xffb30fd1,
2867
   "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2868
2869
  /* Vector VQDMLADH.  */
2870
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2871
   MVE_VQDMLADH,
2872
   0xee000e00, 0xff810f51,
2873
   "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2874
2875
  /* Vector VQRDMLADH.  */
2876
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2877
   MVE_VQRDMLADH,
2878
   0xee000e01, 0xff810f51,
2879
   "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2880
2881
  /* Vector VQDMLAH.  */
2882
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2883
   MVE_VQDMLAH,
2884
   0xee000e60, 0xff811f70,
2885
   "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2886
2887
  /* Vector VQRDMLAH.  */
2888
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2889
   MVE_VQRDMLAH,
2890
   0xee000e40, 0xff811f70,
2891
   "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2892
2893
  /* Vector VQDMLASH.  */
2894
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2895
   MVE_VQDMLASH,
2896
   0xee001e60, 0xff811f70,
2897
   "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2898
2899
  /* Vector VQRDMLASH.  */
2900
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2901
   MVE_VQRDMLASH,
2902
   0xee001e40, 0xff811f70,
2903
   "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2904
2905
  /* Vector VQDMLSDH.  */
2906
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2907
   MVE_VQDMLSDH,
2908
   0xfe000e00, 0xff810f51,
2909
   "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2910
2911
  /* Vector VQRDMLSDH.  */
2912
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2913
   MVE_VQRDMLSDH,
2914
   0xfe000e01, 0xff810f51,
2915
   "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2916
2917
  /* Vector VQDMULH T1 variant.  */
2918
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2919
   MVE_VQDMULH_T1,
2920
   0xef000b40, 0xff811f51,
2921
   "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2922
2923
  /* Vector VQRDMULH T2 variant.  */
2924
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2925
   MVE_VQRDMULH_T2,
2926
   0xff000b40, 0xff811f51,
2927
   "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2928
2929
  /* Vector VQDMULH T3 variant.  */
2930
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2931
   MVE_VQDMULH_T3,
2932
   0xee010e60, 0xff811f70,
2933
   "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2934
2935
  /* Vector VQRDMULH T4 variant.  */
2936
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2937
   MVE_VQRDMULH_T4,
2938
   0xfe010e60, 0xff811f70,
2939
   "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2940
2941
  /* Vector VQNEG.  */
2942
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2943
   MVE_VQNEG,
2944
   0xffb007c0, 0xffb31fd1,
2945
   "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2946
2947
  /* Vector VQRSHL T1 variant.  */
2948
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2949
   MVE_VQRSHL_T1,
2950
   0xef000550, 0xef811f51,
2951
   "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2952
2953
  /* Vector VQRSHL T2 variant.  */
2954
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2955
   MVE_VQRSHL_T2,
2956
   0xee331ee0, 0xefb31ff0,
2957
   "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2958
2959
  /* Vector VQRSHRN.  */
2960
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2961
   MVE_VQRSHRN,
2962
   0xee800f41, 0xefa00fd1,
2963
   "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2964
2965
  /* Vector VQRSHRUN.  */
2966
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2967
   MVE_VQRSHRUN,
2968
   0xfe800fc0, 0xffa00fd1,
2969
   "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2970
2971
  /* Vector VQSHL T1 Variant.  */
2972
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2973
   MVE_VQSHL_T1,
2974
   0xee311ee0, 0xefb31ff0,
2975
   "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2976
2977
  /* Vector VQSHL T4 Variant.  */
2978
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2979
   MVE_VQSHL_T4,
2980
   0xef000450, 0xef811f51,
2981
   "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2982
2983
  /* Vector VQSHRN.  */
2984
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2985
   MVE_VQSHRN,
2986
   0xee800f40, 0xefa00fd1,
2987
   "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2988
2989
  /* Vector VQSHRUN.  */
2990
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2991
   MVE_VQSHRUN,
2992
   0xee800fc0, 0xffa00fd1,
2993
   "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
2994
2995
  /* Vector VQSUB T1 Variant.  */
2996
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2997
   MVE_VQSUB_T1,
2998
   0xef000250, 0xef811f51,
2999
   "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3000
3001
  /* Vector VQSUB T2 Variant.  */
3002
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3003
   MVE_VQSUB_T2,
3004
   0xee001f60, 0xef811f70,
3005
   "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3006
3007
  /* Vector VREV16.  */
3008
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3009
   MVE_VREV16,
3010
   0xffb00140, 0xffb31fd1,
3011
   "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3012
3013
  /* Vector VREV32.  */
3014
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3015
   MVE_VREV32,
3016
   0xffb000c0, 0xffb31fd1,
3017
   "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3018
3019
  /* Vector VREV64.  */
3020
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3021
   MVE_VREV64,
3022
   0xffb00040, 0xffb31fd1,
3023
   "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3024
3025
  /* Vector VRINT floating point.  */
3026
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3027
   MVE_VRINT_FP,
3028
   0xffb20440, 0xffb31c51,
3029
   "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3030
3031
  /* Vector VRMLALDAVH.  */
3032
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3033
   MVE_VRMLALDAVH,
3034
   0xee800f00, 0xef811f51,
3035
   "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3036
3037
  /* Vector VRMLALDAVH.  */
3038
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3039
   MVE_VRMLALDAVH,
3040
   0xee801f00, 0xef811f51,
3041
   "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3042
3043
  /* Vector VRSHL T1 Variant.  */
3044
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3045
   MVE_VRSHL_T1,
3046
   0xef000540, 0xef811f51,
3047
   "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3048
3049
  /* Vector VRSHL T2 Variant.  */
3050
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3051
   MVE_VRSHL_T2,
3052
   0xee331e60, 0xefb31ff0,
3053
   "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3054
3055
  /* Vector VRSHRN.  */
3056
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3057
   MVE_VRSHRN,
3058
   0xfe800fc1, 0xffa00fd1,
3059
   "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3060
3061
  /* Vector VSBC.  */
3062
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3063
   MVE_VSBC,
3064
   0xfe300f00, 0xffb10f51,
3065
   "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3066
3067
  /* Vector VSHL T2 Variant.  */
3068
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3069
   MVE_VSHL_T2,
3070
   0xee311e60, 0xefb31ff0,
3071
   "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3072
3073
  /* Vector VSHL T3 Variant.  */
3074
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3075
   MVE_VSHL_T3,
3076
   0xef000440, 0xef811f51,
3077
   "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3078
3079
  /* Vector VSHLC.  */
3080
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3081
   MVE_VSHLC,
3082
   0xeea00fc0, 0xffa01ff0,
3083
   "vshlc%v\t%13-15,22Q, %0-3r, %{I:#%16-20d%}"},
3084
3085
  /* Vector VSHLL T2 Variant.  */
3086
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3087
   MVE_VSHLL_T2,
3088
   0xee310e01, 0xefb30fd1,
3089
   "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, %{I:#%18-19d%}"},
3090
3091
  /* Vector VSHRN.  */
3092
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3093
   MVE_VSHRN,
3094
   0xee800fc1, 0xffa00fd1,
3095
   "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
3096
3097
  /* Vector VST2 no writeback.  */
3098
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3099
   MVE_VST2,
3100
   0xfc801e00, 0xffb01e5f,
3101
   "vst2%5d.%7-8s\t%B, [%16-19r]"},
3102
3103
  /* Vector VST2 writeback.  */
3104
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3105
   MVE_VST2,
3106
   0xfca01e00, 0xffb01e5f,
3107
   "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3108
3109
  /* Vector VST4 no writeback.  */
3110
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3111
   MVE_VST4,
3112
   0xfc801e01, 0xffb01e1f,
3113
   "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3114
3115
  /* Vector VST4 writeback.  */
3116
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3117
   MVE_VST4,
3118
   0xfca01e01, 0xffb01e1f,
3119
   "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3120
3121
  /* Vector VSTRB scatter store, T1 variant.  */
3122
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3123
   MVE_VSTRB_SCATTER_T1,
3124
   0xec800e00, 0xffb01e50,
3125
   "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3126
3127
  /* Vector VSTRH scatter store, T2 variant.  */
3128
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3129
   MVE_VSTRH_SCATTER_T2,
3130
   0xec800e10, 0xffb01e50,
3131
   "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3132
3133
  /* Vector VSTRW scatter store, T3 variant.  */
3134
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3135
   MVE_VSTRW_SCATTER_T3,
3136
   0xec800e40, 0xffb01e50,
3137
   "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3138
3139
  /* Vector VSTRD scatter store, T4 variant.  */
3140
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3141
   MVE_VSTRD_SCATTER_T4,
3142
   0xec800fd0, 0xffb01fd0,
3143
   "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3144
3145
  /* Vector VSTRW scatter store, T5 variant.  */
3146
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3147
   MVE_VSTRW_SCATTER_T5,
3148
   0xfd001e00, 0xff111f00,
3149
   "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
3150
3151
  /* Vector VSTRD scatter store, T6 variant.  */
3152
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3153
   MVE_VSTRD_SCATTER_T6,
3154
   0xfd001f00, 0xff111f00,
3155
   "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
3156
3157
  /* Vector VSTRB.  */
3158
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3159
   MVE_VSTRB_T1,
3160
   0xec000e00, 0xfe581e00,
3161
   "vstrb%v.%7-8s\t%13-15Q, %d"},
3162
3163
  /* Vector VSTRH.  */
3164
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3165
   MVE_VSTRH_T2,
3166
   0xec080e00, 0xfe581e00,
3167
   "vstrh%v.%7-8s\t%13-15Q, %d"},
3168
3169
  /* Vector VSTRB variant T5.  */
3170
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3171
   MVE_VSTRB_T5,
3172
   0xec001e00, 0xfe101f80,
3173
   "vstrb%v.8\t%13-15,22Q, %d"},
3174
3175
  /* Vector VSTRH variant T6.  */
3176
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3177
   MVE_VSTRH_T6,
3178
   0xec001e80, 0xfe101f80,
3179
   "vstrh%v.16\t%13-15,22Q, %d"},
3180
3181
  /* Vector VSTRW variant T7.  */
3182
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3183
   MVE_VSTRW_T7,
3184
   0xec001f00, 0xfe101f80,
3185
   "vstrw%v.32\t%13-15,22Q, %d"},
3186
3187
  /* Vector VSUB floating point T1 variant.  */
3188
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3189
   MVE_VSUB_FP_T1,
3190
   0xef200d40, 0xffa11f51,
3191
   "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3192
3193
  /* Vector VSUB floating point T2 variant.  */
3194
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3195
   MVE_VSUB_FP_T2,
3196
   0xee301f40, 0xefb11f70,
3197
   "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3198
3199
  /* Vector VSUB T1 variant.  */
3200
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3201
   MVE_VSUB_VEC_T1,
3202
   0xff000840, 0xff811f51,
3203
   "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3204
3205
  /* Vector VSUB T2 variant.  */
3206
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3207
   MVE_VSUB_VEC_T2,
3208
   0xee011f40, 0xff811f70,
3209
   "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3210
3211
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3212
   MVE_ASRLI,
3213
   0xea50012f, 0xfff1813f,
3214
   "asrl%c\t%17-19l, %9-11h, %j"},
3215
3216
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3217
   MVE_ASRL,
3218
   0xea50012d, 0xfff101ff,
3219
   "asrl%c\t%17-19l, %9-11h, %12-15S"},
3220
3221
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3222
   MVE_LSLLI,
3223
   0xea50010f, 0xfff1813f,
3224
   "lsll%c\t%17-19l, %9-11h, %j"},
3225
3226
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3227
   MVE_LSLL,
3228
   0xea50010d, 0xfff101ff,
3229
   "lsll%c\t%17-19l, %9-11h, %12-15S"},
3230
3231
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3232
   MVE_LSRL,
3233
   0xea50011f, 0xfff1813f,
3234
   "lsrl%c\t%17-19l, %9-11h, %j"},
3235
3236
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3237
   MVE_SQRSHRL,
3238
   0xea51012d, 0xfff1017f,
3239
   "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3240
3241
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3242
   MVE_SQRSHR,
3243
   0xea500f2d, 0xfff00fff,
3244
   "sqrshr%c\t%16-19S, %12-15S"},
3245
3246
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3247
   MVE_SQSHLL,
3248
   0xea51013f, 0xfff1813f,
3249
   "sqshll%c\t%17-19l, %9-11h, %j"},
3250
3251
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3252
   MVE_SQSHL,
3253
   0xea500f3f, 0xfff08f3f,
3254
   "sqshl%c\t%16-19S, %j"},
3255
3256
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3257
   MVE_SRSHRL,
3258
   0xea51012f, 0xfff1813f,
3259
   "srshrl%c\t%17-19l, %9-11h, %j"},
3260
3261
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3262
   MVE_SRSHR,
3263
   0xea500f2f, 0xfff08f3f,
3264
   "srshr%c\t%16-19S, %j"},
3265
3266
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3267
   MVE_UQRSHLL,
3268
   0xea51010d, 0xfff1017f,
3269
   "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3270
3271
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3272
   MVE_UQRSHL,
3273
   0xea500f0d, 0xfff00fff,
3274
   "uqrshl%c\t%16-19S, %12-15S"},
3275
3276
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3277
   MVE_UQSHLL,
3278
    0xea51010f, 0xfff1813f,
3279
   "uqshll%c\t%17-19l, %9-11h, %j"},
3280
3281
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3282
   MVE_UQSHL,
3283
   0xea500f0f, 0xfff08f3f,
3284
   "uqshl%c\t%16-19S, %j"},
3285
3286
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3287
   MVE_URSHRL,
3288
    0xea51011f, 0xfff1813f,
3289
   "urshrl%c\t%17-19l, %9-11h, %j"},
3290
3291
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3292
   MVE_URSHR,
3293
   0xea500f1f, 0xfff08f3f,
3294
   "urshr%c\t%16-19S, %j"},
3295
3296
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3297
   MVE_CSINC,
3298
   0xea509000, 0xfff0f000,
3299
   "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3300
3301
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3302
   MVE_CSINV,
3303
   0xea50a000, 0xfff0f000,
3304
   "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3305
3306
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3307
   MVE_CSET,
3308
   0xea5f900f, 0xfffff00f,
3309
   "cset\t%8-11S, %4-7C"},
3310
3311
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3312
   MVE_CSETM,
3313
   0xea5fa00f, 0xfffff00f,
3314
   "csetm\t%8-11S, %4-7C"},
3315
3316
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3317
   MVE_CSEL,
3318
   0xea508000, 0xfff0f000,
3319
   "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3320
3321
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3322
   MVE_CSNEG,
3323
   0xea50b000, 0xfff0f000,
3324
   "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3325
3326
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3327
   MVE_CINC,
3328
   0xea509000, 0xfff0f000,
3329
   "cinc\t%8-11S, %16-19Z, %4-7C"},
3330
3331
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3332
   MVE_CINV,
3333
   0xea50a000, 0xfff0f000,
3334
   "cinv\t%8-11S, %16-19Z, %4-7C"},
3335
3336
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3337
   MVE_CNEG,
3338
   0xea50b000, 0xfff0f000,
3339
   "cneg\t%8-11S, %16-19Z, %4-7C"},
3340
3341
  {ARM_FEATURE_CORE_LOW (0),
3342
   MVE_NONE,
3343
   0x00000000, 0x00000000, 0}
3344
};
3345
3346
/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
3347
   ordered: they must be searched linearly from the top to obtain a correct
3348
   match.  */
3349
3350
/* print_insn_arm recognizes the following format control codes:
3351
3352
   %%     %
3353
3354
   %a     print address for ldr/str instruction
3355
   %s                   print address for ldr/str halfword/signextend instruction
3356
   %S                   like %s but allow UNPREDICTABLE addressing
3357
   %b     print branch destination
3358
   %c     print condition code (always bits 28-31)
3359
   %m     print register mask for ldm/stm instruction
3360
   %o     print operand2 (immediate or register + shift)
3361
   %p     print 'p' iff bits 12-15 are 15
3362
   %O     print 'OBSOLETE' iff bits 12-15 are 15
3363
   %t     print 't' iff bit 21 set and bit 24 clear
3364
   %B     print arm BLX(1) destination
3365
   %C     print the PSR sub type.
3366
   %U     print barrier type.
3367
   %P     print address for pli instruction.
3368
   %T     print 'from Armv4T onwards'
3369
3370
   %<bitfield>r   print as an ARM register
3371
   %<bitfield>T   print as an ARM register + 1
3372
   %<bitfield>R   as %r but r15 is UNPREDICTABLE
3373
   %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3374
   %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3375
   %<bitfield>d   print the bitfield in decimal
3376
   %<bitfield>W         print the bitfield plus one in decimal
3377
   %<bitfield>x   print the bitfield in hex
3378
   %<bitfield>X   print the bitfield as 1 hex digit without leading "0x"
3379
3380
   %<bitfield>'c  print specified char iff bitfield is all ones
3381
   %<bitfield>`c  print specified char iff bitfield is all zeroes
3382
   %<bitfield>?ab...    select from array of values in big endian order
3383
3384
   %e                   print arm SMI operand (bits 0..7,8..19).
3385
   %E     print the LSB and WIDTH fields of a BFI or BFC instruction.
3386
   %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
3387
   %R     print the SPSR/CPSR or banked register of an MRS.  */
3388
3389
static const struct opcode32 arm_opcodes[] =
3390
{
3391
  /* ARM instructions.  */
3392
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3393
    0xe1a00000, 0xffffffff, "nop\t\t\t@ (mov r0, r0)"},
3394
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3395
    0xe7f000f0, 0xfff000f0, "udf\t%{I:#%e%}"},
3396
3397
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4),
3398
    0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r%T"},
3399
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3400
    0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3401
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3402
    0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3403
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3404
    0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3405
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3406
    0x00800090, 0x0fa000f0,
3407
    "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3408
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3409
    0x00a00090, 0x0fa000f0,
3410
    "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3411
3412
  /* V8.2 RAS extension instructions.  */
3413
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3414
    0xe320f010, 0xffffffff, "esb"},
3415
3416
  /* V8-R instructions.  */
3417
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
3418
    0xf57ff04c, 0xffffffff, "dfb"},
3419
3420
  /* V8 instructions.  */
3421
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3422
    0x0320f005, 0x0fffffff, "sevl"},
3423
  /* Defined in V8 but is in NOP space so available to all arch.  */
3424
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3425
    0xe1000070, 0xfff000f0, "hlt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
3426
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
3427
    0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3428
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3429
    0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3430
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3431
    0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3432
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3433
    0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3434
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3435
    0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3436
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3437
    0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3438
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3439
    0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3440
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3441
    0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3442
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3443
    0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3444
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3445
    0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3446
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3447
    0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3448
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3449
    0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3450
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3451
    0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3452
  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3453
    0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3454
  /* CRC32 instructions.  */
3455
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3456
    0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3457
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3458
    0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3459
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3460
    0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3461
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3462
    0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3463
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3464
    0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3465
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3466
    0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3467
3468
  /* Privileged Access Never extension instructions.  */
3469
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3470
    0xf1100000, 0xfffffdff, "setpan\t%{I:#%9-9d%}"},
3471
3472
  /* Virtualization Extension instructions.  */
3473
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3474
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3475
3476
  /* Integer Divide Extension instructions.  */
3477
  {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3478
    0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3479
  {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3480
    0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3481
3482
  /* MP Extension instructions.  */
3483
  {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3484
3485
  /* Speculation Barriers.  */
3486
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3487
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3488
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3489
3490
  /* V7 instructions.  */
3491
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3492
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t%{I:#%0-3d%}"},
3493
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3494
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3495
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3496
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3497
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3498
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3499
    0x0320f000, 0x0fffffff, "nop%c\t{%{I:%0-7d%}}"},
3500
3501
  /* ARM V6T2 instructions.  */
3502
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3503
    0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3504
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3505
    0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3506
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3507
    0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3508
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3509
    0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3510
3511
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3512
    0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3513
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3514
    0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3515
3516
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3517
    0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3518
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3519
    0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3520
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3521
    0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3522
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3523
    0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, %{I:#%7-11d%}, %{I:#%16-20W%}"},
3524
3525
  /* ARM Security extension instructions.  */
3526
  {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3527
    0x01600070, 0x0ff000f0, "smc%c\t%e"},
3528
3529
  /* ARM V6K instructions.  */
3530
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3531
    0xf57ff01f, 0xffffffff, "clrex"},
3532
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3533
    0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3534
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3535
    0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3536
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3537
    0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3538
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3539
    0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3540
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3541
    0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3542
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3543
    0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3544
3545
  /* ARMv8.5-A instructions.  */
3546
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3547
3548
  /* ARM V6K NOP hints.  */
3549
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3550
    0x0320f001, 0x0fffffff, "yield%c"},
3551
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3552
    0x0320f002, 0x0fffffff, "wfe%c"},
3553
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3554
    0x0320f003, 0x0fffffff, "wfi%c"},
3555
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3556
    0x0320f004, 0x0fffffff, "sev%c"},
3557
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3558
    0x0320f000, 0x0fffff00, "nop%c\t{%{I:%0-7d%}}"},
3559
3560
  /* ARM V6 instructions.  */
3561
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3562
    0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"},
3563
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3564
    0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
3565
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3566
    0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"},
3567
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3568
    0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
3569
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3570
    0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"},
3571
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3572
    0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3573
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3574
    0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
3575
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3576
    0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#32%}"},
3577
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3578
    0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
3579
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3580
    0x01900f9f, 0x0ff00fff, "ldrex%c\t%{R:r%12-15d%}, [%16-19R]"},
3581
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3582
    0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3583
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3584
    0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3585
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3586
    0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3587
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3588
    0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3589
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3590
    0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3591
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3592
    0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3593
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3594
    0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3595
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3596
    0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3597
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3598
    0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3599
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3600
    0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3601
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3602
    0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3603
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3604
    0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3605
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3606
    0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3607
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3608
    0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3609
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3610
    0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3611
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3612
    0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3613
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3614
    0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3615
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3616
    0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3617
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3618
    0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3619
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3620
    0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3621
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3622
    0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3623
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3624
    0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3625
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3626
    0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3627
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3628
    0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3629
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3630
    0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3631
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3632
    0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3633
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3634
    0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3635
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3636
    0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3637
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3638
    0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3639
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3640
    0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3641
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3642
    0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3643
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3644
    0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3645
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3646
    0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3647
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3648
    0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3649
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3650
    0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3651
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3652
    0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3653
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3654
    0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3655
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3656
    0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3657
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3658
    0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3659
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3660
    0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3661
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3662
    0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3663
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3664
    0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3665
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3666
    0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3667
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3668
    0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3669
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3670
    0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3671
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3672
    0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3673
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3674
    0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3675
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3676
    0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3677
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3678
    0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3679
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3680
    0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3681
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3682
    0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3683
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3684
    0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3685
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3686
    0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3687
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3688
    0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3689
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3690
    0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3691
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3692
    0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3693
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3694
    0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3695
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3696
    0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3697
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3698
    0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3699
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3700
    0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3701
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3702
    0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3703
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3704
    0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
3705
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3706
    0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
3707
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3708
    0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
3709
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3710
    0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3711
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3712
    0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3713
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3714
    0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3715
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3716
    0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3717
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3718
    0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3719
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3720
    0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3721
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3722
    0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3723
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3724
    0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3725
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3726
    0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3727
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3728
    0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3729
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3730
    0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3731
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3732
    0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3733
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3734
    0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3735
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3736
    0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3737
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3738
    0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3739
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3740
    0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3741
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3742
    0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3743
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3744
    0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3745
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3746
    0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3747
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3748
    0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR %{I:#24%}"},
3749
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3750
    0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3751
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3752
    0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
3753
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3754
    0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
3755
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3756
    0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
3757
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3758
    0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3759
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3760
    0xf1010000, 0xfffffc00, "setend\t%{B:%9?ble%}"},
3761
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3762
    0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3763
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3764
    0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3765
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3766
    0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3767
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3768
    0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3769
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3770
    0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3771
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3772
    0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3773
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3774
    0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3775
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3776
    0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3777
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3778
    0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3779
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3780
    0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, %{I:#%0-4d%}"},
3781
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3782
    0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R"},
3783
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3784
    0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
3785
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3786
    0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
3787
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3788
    0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, %{I:#%16-19W%}, %0-3r"},
3789
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3790
    0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3791
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3792
    0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3793
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3794
    0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3795
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3796
    0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3797
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3798
    0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R"},
3799
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3800
    0x06e00010, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
3801
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3802
    0x06e00050, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
3803
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3804
    0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, %{I:#%16-19d%}, %0-3R"},
3805
3806
  /* V5J instruction.  */
3807
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3808
    0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3809
3810
  /* V5 Instructions.  */
3811
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3812
    0xe1200070, 0xfff000f0,
3813
    "bkpt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
3814
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3815
    0xfa000000, 0xfe000000, "blx\t%B"},
3816
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3817
    0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3818
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3819
    0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3820
3821
  /* V5E "El Segundo" Instructions.  */
3822
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3823
    0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3824
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3825
    0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3826
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3827
    0xf450f000, 0xfc70f000, "pld\t%a"},
3828
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3829
    0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3830
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3831
    0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3832
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3833
    0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3834
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3835
    0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3836
3837
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3838
    0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3839
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3840
    0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3841
3842
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3843
    0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3844
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3845
    0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3846
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3847
    0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3848
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3849
    0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3850
3851
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3852
    0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3853
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3854
    0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3855
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3856
    0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3857
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3858
    0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3859
3860
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3861
    0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3862
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3863
    0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3864
3865
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3866
    0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
3867
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3868
    0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3869
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3870
    0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
3871
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3872
    0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
3873
3874
  /* ARM Instructions.  */
3875
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3876
    0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t@ (str%c %12-15r, %a)"},
3877
3878
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3879
    0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3880
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3881
    0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3882
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3883
    0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3884
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3885
    0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3886
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3887
    0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3888
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3889
    0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3890
3891
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3892
    0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3893
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3894
    0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3895
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3896
    0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3897
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3898
    0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3899
3900
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3901
    0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3902
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3903
    0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3904
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3905
    0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3906
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3907
    0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3908
3909
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3910
    0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3911
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3912
    0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3913
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3914
    0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3915
3916
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3917
    0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3918
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3919
    0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3920
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3921
    0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3922
3923
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3924
    0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3925
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3926
    0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3927
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3928
    0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3929
3930
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3931
    0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3932
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3933
    0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3934
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3935
    0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3936
3937
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3938
    0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3939
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3940
    0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3941
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3942
    0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3943
3944
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3945
    0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3946
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3947
    0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3948
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3949
    0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3950
3951
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3952
    0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3953
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3954
    0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3955
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3956
    0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3957
3958
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3959
    0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3960
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3961
    0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3962
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3963
    0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3964
3965
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
3966
    0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3967
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3968
    0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3969
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3970
    0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3971
3972
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3973
    0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o%O"},
3974
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3975
    0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o%O"},
3976
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3977
    0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o%O"},
3978
3979
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3980
    0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o%O"},
3981
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3982
    0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o%O"},
3983
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3984
    0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o%O"},
3985
3986
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3987
    0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o%O"},
3988
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3989
    0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o%O"},
3990
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3991
    0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o%O"},
3992
3993
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3994
    0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o%O"},
3995
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3996
    0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o%O"},
3997
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3998
    0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o%O"},
3999
4000
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4001
    0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4002
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4003
    0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4004
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4005
    0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4006
4007
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4008
    0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4009
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4010
    0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4011
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4012
    0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4013
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4014
    0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4015
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4016
    0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4017
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4018
    0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4019
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4020
    0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4021
4022
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4023
    0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4024
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4025
    0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4026
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4027
    0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4028
4029
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4030
    0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4031
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4032
    0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4033
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4034
    0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4035
4036
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4037
    0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4038
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4039
    0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t@ (ldr%c %12-15r, %a)"},
4040
4041
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4042
    0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4043
4044
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4045
    0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4046
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4047
    0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4048
4049
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4050
    0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4051
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4052
    0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4053
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4054
    0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4055
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4056
    0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4057
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4058
    0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4059
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4060
    0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4061
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4062
    0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4063
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4064
    0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4065
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4066
    0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4067
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4068
    0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4069
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4070
    0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4071
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4072
    0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4073
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4074
    0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4075
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4076
    0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4077
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4078
    0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4079
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4080
    0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4081
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4082
    0x092d0000, 0x0fff0000, "push%c\t%m"},
4083
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4084
    0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4085
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4086
    0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4087
4088
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4089
    0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4090
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4091
    0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4092
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4093
    0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4094
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4095
    0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4096
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4097
    0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4098
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4099
    0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4100
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4101
    0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4102
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4103
    0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4104
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4105
    0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4106
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4107
    0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4108
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4109
    0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4110
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4111
    0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4112
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4113
    0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4114
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4115
    0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4116
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4117
    0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4118
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4119
    0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4120
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4121
    0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4122
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4123
    0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4124
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4125
    0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4126
4127
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4128
    0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4129
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4130
    0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4131
4132
  /* The rest.  */
4133
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4134
    0x03200000, 0x0fff00ff, "nop%c\t{%{I:%0-7d%}}" UNPREDICTABLE_INSTRUCTION},
4135
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4136
    0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4137
  {ARM_FEATURE_CORE_LOW (0),
4138
    0x00000000, 0x00000000, 0}
4139
};
4140
4141
/* print_insn_thumb16 recognizes the following format control codes:
4142
4143
   %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
4144
   %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
4145
   %<bitfield>I         print bitfield as a signed decimal
4146
          (top bit of range being the sign bit)
4147
   %N                   print Thumb register mask (with LR)
4148
   %O                   print Thumb register mask (with PC)
4149
   %M                   print Thumb register mask
4150
   %b     print CZB's 6-bit unsigned branch destination
4151
   %s     print Thumb right-shift immediate (6..10; 0 == 32).
4152
   %c     print the condition code
4153
   %C     print the condition code, or "s" if not conditional
4154
   %x     print warning if conditional an not at end of IT block"
4155
   %X     print "\t@ unpredictable <IT:code>" if conditional
4156
   %I     print IT instruction suffix and operands
4157
   %W     print Thumb Writeback indicator for LDMIA
4158
   %<bitfield>r   print bitfield as an ARM register
4159
   %<bitfield>d   print bitfield as a decimal
4160
   %<bitfield>H         print (bitfield * 2) as a decimal
4161
   %<bitfield>W         print (bitfield * 4) as a decimal
4162
   %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
4163
   %<bitfield>B         print Thumb branch destination (signed displacement)
4164
   %<bitfield>c         print bitfield as a condition code
4165
   %<bitnum>'c    print specified char iff bit is one
4166
   %<bitnum>?ab   print a if bit is one else print b.  */
4167
4168
static const struct opcode16 thumb_opcodes[] =
4169
{
4170
  /* Thumb instructions.  */
4171
4172
  /* ARMv8-M Security Extensions instructions.  */
4173
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
4174
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
4175
4176
  /* ARM V8 instructions.  */
4177
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
4178
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
4179
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t%{I:#%3-3d%}"},
4180
4181
  /* ARM V6K no-argument instructions.  */
4182
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4183
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4184
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4185
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4186
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4187
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4188
4189
  /* ARM V6T2 instructions.  */
4190
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4191
    0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4192
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4193
    0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4194
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
4195
4196
  /* ARM V6.  */
4197
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%{B:%2'a%1'i%0'f%}%X"},
4198
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%{B:%2'a%1'i%0'f%}%X"},
4199
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4200
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4201
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4202
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4203
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%{B:%3?ble%}%X"},
4204
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4205
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4206
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4207
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4208
4209
  /* ARM V5 ISA extends Thumb.  */
4210
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4211
    0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
4212
  /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
4213
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4214
    0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
4215
  /* ARM V4T ISA (Thumb v1).  */
4216
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4217
    0x46C0, 0xFFFF, "nop%c\t\t\t@ (mov r8, r8)"},
4218
  /* Format 4.  */
4219
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4220
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4221
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4222
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4223
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4224
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4225
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4226
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4227
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4228
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4229
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4230
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4231
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4232
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4233
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4234
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4235
  /* format 13 */
4236
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\t%{R:sp%}, %{I:#%0-6W%}"},
4237
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\t%{R:sp%}, %{I:#%0-6W%}"},
4238
  /* format 5 */
4239
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4240
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4241
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4242
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4243
  /* format 14 */
4244
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4245
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
4246
  /* format 2 */
4247
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4248
    0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4249
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4250
    0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4251
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4252
    0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
4253
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4254
    0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
4255
  /* format 8 */
4256
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4257
    0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4258
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4259
    0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4260
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4261
    0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4262
  /* format 7 */
4263
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4264
    0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4265
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4266
    0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4267
  /* format 1 */
4268
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4269
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4270
    0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, %{I:#%6-10d%}"},
4271
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4272
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4273
  /* format 3 */
4274
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, %{I:#%0-7d%}"},
4275
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, %{I:#%0-7d%}"},
4276
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, %{I:#%0-7d%}"},
4277
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, %{I:#%0-7d%}"},
4278
  /* format 6 */
4279
  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4280
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4281
    0x4800, 0xF800,
4282
    "ldr%c\t%8-10r, [%{R:pc%}, %{I:#%0-7W%}]\t@ (%0-7a)"},
4283
  /* format 9 */
4284
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4285
    0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
4286
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4287
    0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
4288
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4289
    0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
4290
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4291
    0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
4292
  /* format 10 */
4293
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4294
    0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
4295
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4296
    0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
4297
  /* format 11 */
4298
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4299
    0x9000, 0xF800, "str%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
4300
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4301
    0x9800, 0xF800, "ldr%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
4302
  /* format 12 */
4303
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4304
    0xA000, 0xF800, "add%c\t%8-10r, %{R:pc%}, %{I:#%0-7W%}\t@ (adr %8-10r, %0-7a)"},
4305
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4306
    0xA800, 0xF800, "add%c\t%8-10r, %{R:sp%}, %{I:#%0-7W%}"},
4307
  /* format 15 */
4308
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4309
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4310
  /* format 17 */
4311
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4312
  /* format 16 */
4313
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t%{I:#%0-7d%}"},
4314
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4315
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4316
  /* format 18 */
4317
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4318
4319
  /* The E800 .. FFFF range is unconditionally redirected to the
4320
     32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4321
     are processed via that table.  Thus, we can never encounter a
4322
     bare "second half of BL/BLX(1)" instruction here.  */
4323
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4324
  {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4325
};
4326
4327
/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4328
   We adopt the convention that hw1 is the high 16 bits of .value and
4329
   .mask, hw2 the low 16 bits.
4330
4331
   print_insn_thumb32 recognizes the following format control codes:
4332
4333
       %%   %
4334
4335
       %I   print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4336
       %M   print a modified 12-bit immediate (same location)
4337
       %J   print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4338
       %K   print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4339
       %H   print a 16-bit immediate from hw2[3:0],hw1[11:0]
4340
       %S   print a possibly-shifted Rm
4341
4342
       %L   print address for a ldrd/strd instruction
4343
       %a   print the address of a plain load/store
4344
       %w   print the width and signedness of a core load/store
4345
       %m   print register mask for ldm/stm
4346
       %n   print register mask for clrm
4347
4348
       %E   print the lsb and width fields of a bfc/bfi instruction
4349
       %F   print the lsb and width fields of a sbfx/ubfx instruction
4350
       %G   print a fallback offset for Branch Future instructions
4351
       %W   print an offset for BF instruction
4352
       %Y   print an offset for BFL instruction
4353
       %Z   print an offset for BFCSEL instruction
4354
       %Q   print an offset for Low Overhead Loop instructions
4355
       %P   print an offset for Low Overhead Loop end instructions
4356
       %b   print a conditional branch offset
4357
       %B   print an unconditional branch offset
4358
       %s   print the shift field of an SSAT instruction
4359
       %R   print the rotation field of an SXT instruction
4360
       %U   print barrier type.
4361
       %P   print address for pli instruction.
4362
       %c   print the condition code
4363
       %x   print warning if conditional an not at end of IT block"
4364
       %X   print "\t@ unpredictable <IT:code>" if conditional
4365
4366
       %<bitfield>d print bitfield in decimal
4367
       %<bitfield>D     print bitfield plus one in decimal
4368
       %<bitfield>W print bitfield*4 in decimal
4369
       %<bitfield>r print bitfield as an ARM register
4370
       %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4371
       %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4372
       %<bitfield>c print bitfield as a condition code
4373
4374
       %<bitfield>'c  print specified char iff bitfield is all ones
4375
       %<bitfield>`c  print specified char iff bitfield is all zeroes
4376
       %<bitfield>?ab... select from array of values in big endian order
4377
4378
   With one exception at the bottom (done because BL and BLX(1) need
4379
   to come dead last), this table was machine-sorted first in
4380
   decreasing order of number of bits set in the mask, then in
4381
   increasing numeric order of mask, then in increasing numeric order
4382
   of opcode.  This order is not the clearest for a human reader, but
4383
   is guaranteed never to catch a special-case bit pattern with a more
4384
   general mask, which is important, because this instruction encoding
4385
   makes heavy use of special-case bit patterns.  */
4386
static const struct opcode32 thumb32_opcodes[] =
4387
{
4388
  /* Arm v8.1-M Mainline Pointer Authentication and Branch Target
4389
     Identification Extension.  */
4390
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4391
   0xf3af802d, 0xffffffff, "aut\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
4392
  {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4393
   0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"},
4394
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4395
   0xf3af800f, 0xffffffff, "bti"},
4396
  {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4397
   0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"},
4398
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4399
   0xf3af801d, 0xffffffff, "pac\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
4400
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4401
   0xf3af800d, 0xffffffff, "pacbti\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
4402
  {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4403
   0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"},
4404
4405
  /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4406
     instructions.  */
4407
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4408
    0xf00fe001, 0xffffffff, "lctp%c"},
4409
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4410
    0xf02fc001, 0xfffff001, "le\t%P"},
4411
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4412
    0xf00fc001, 0xfffff001, "le\t%{R:lr%}, %P"},
4413
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4414
    0xf01fc001, 0xfffff001, "letp\t%{R:lr%}, %P"},
4415
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4416
    0xf040c001, 0xfff0f001, "wls\t%{R:lr%}, %16-19S, %Q"},
4417
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4418
    0xf000c001, 0xffc0f001, "wlstp.%20-21s\t%{R:lr%}, %16-19S, %Q"},
4419
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4420
    0xf040e001, 0xfff0ffff, "dls\t%{R:lr%}, %16-19S"},
4421
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4422
    0xf000e001, 0xffc0ffff, "dlstp.%20-21s\t%{R:lr%}, %16-19S"},
4423
4424
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4425
    0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4426
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4427
    0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4428
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4429
    0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4430
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4431
    0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4432
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4433
    0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %{B:%18-21c%}"},
4434
4435
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4436
    0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4437
4438
  /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
4439
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4440
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4441
    0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4442
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4443
    0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4444
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4445
    0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4446
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4447
    0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4448
4449
  /* ARM V8.2 RAS extension instructions.  */
4450
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
4451
    0xf3af8010, 0xffffffff, "esb"},
4452
4453
  /* V8 instructions.  */
4454
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4455
    0xf3af8005, 0xffffffff, "sevl%c.w"},
4456
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4457
    0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4458
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4459
    0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4460
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4461
    0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4462
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4463
    0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4464
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4465
    0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4466
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4467
    0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4468
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4469
    0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4470
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4471
    0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4472
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4473
    0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4474
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4475
    0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4476
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4477
    0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4478
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4479
    0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4480
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4481
    0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4482
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4483
    0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4484
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4485
    0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4486
4487
  /* V8-R instructions.  */
4488
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
4489
    0xf3bf8f4c, 0xffffffff, "dfb%c"},
4490
4491
  /* CRC32 instructions.  */
4492
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4493
    0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4494
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4495
    0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4496
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4497
    0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4498
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4499
    0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4500
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4501
    0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4502
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4503
    0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4504
4505
  /* Speculation Barriers.  */
4506
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4507
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4508
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4509
4510
  /* V7 instructions.  */
4511
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4512
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t%{I:#%0-3d%}"},
4513
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4514
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4515
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4516
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4517
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4518
  {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4519
    0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4520
  {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4521
    0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4522
4523
  /* Virtualization Extension instructions.  */
4524
  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4525
  /* We skip ERET as that is SUBS pc, lr, #0.  */
4526
4527
  /* MP Extension instructions.  */
4528
  {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
4529
4530
  /* Security extension instructions.  */
4531
  {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4532
4533
  /* ARMv8.5-A instructions.  */
4534
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4535
4536
  /* Instructions defined in the basic V6T2 set.  */
4537
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4538
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4539
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4540
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4541
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4542
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4543
    0xf3af8000, 0xffffff00, "nop%c.w\t{%{I:%0-7d%}}"},
4544
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4545
4546
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4547
    0xf3bf8f2f, 0xffffffff, "clrex%c"},
4548
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4549
    0xf3af8400, 0xffffff1f, "cpsie.w\t%{B:%7'a%6'i%5'f%}%X"},
4550
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4551
    0xf3af8600, 0xffffff1f, "cpsid.w\t%{B:%7'a%6'i%5'f%}%X"},
4552
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4553
    0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4554
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4555
    0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4556
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4557
    0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4558
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4559
    0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4560
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4561
    0xf3af8100, 0xffffffe0, "cps\t%{I:#%0-4d%}%X"},
4562
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4563
    0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4564
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4565
    0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, %{B:lsl%} %{I:#1%}]%x"},
4566
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4567
    0xf3af8500, 0xffffff00, "cpsie\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
4568
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4569
    0xf3af8700, 0xffffff00, "cpsid\t%{B:%7'a%6'i%5'f%}, %{I:#%0-4d%}%X"},
4570
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4571
    0xf3de8f00, 0xffffff00, "subs%c\t%{R:pc%}, %{R:lr%}, %{I:#%0-7d%}"},
4572
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4573
    0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4574
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4575
    0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4576
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4577
    0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4578
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4579
    0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, %{I:#%0-4d%}"},
4580
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4581
    0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, %{I:#%0-4d%}"},
4582
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4583
    0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4584
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4585
    0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4586
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4587
    0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4588
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4589
    0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4590
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4591
    0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4592
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4593
    0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4594
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4595
    0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4596
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4597
    0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4598
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4599
    0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4600
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4601
    0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4602
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4603
    0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4604
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4605
    0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4606
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4607
    0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4608
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4609
    0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4610
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4611
    0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4612
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4613
    0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4614
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4615
    0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4616
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4617
    0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4618
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4619
    0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4620
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4621
    0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4622
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4623
    0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4624
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4625
    0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4626
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4627
    0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4628
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4629
    0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4630
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4631
    0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4632
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4633
    0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4634
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4635
    0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4636
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4637
    0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4638
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4639
    0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4640
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4641
    0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4642
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4643
    0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4644
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4645
    0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4646
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4647
    0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4648
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4649
    0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4650
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4651
    0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4652
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4653
    0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4654
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4655
    0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4656
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4657
    0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4658
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4659
    0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4660
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4661
    0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4662
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4663
    0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4664
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4665
    0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4666
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4667
    0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4668
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4669
    0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4670
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4671
    0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4672
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4673
    0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4674
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4675
    0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4676
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4677
    0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4678
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4679
    0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4680
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4681
    0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4682
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4683
    0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4684
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4685
    0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4686
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4687
    0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4688
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4689
    0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4690
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4691
    0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4692
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4693
    0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4694
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4695
    0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4696
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4697
    0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4698
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4699
    0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4700
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4701
    0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4702
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4703
    0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4704
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4705
    0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, %{I:#%0-4D%}, %16-19r"},
4706
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4707
    0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, %{I:#%0-4d%}, %16-19r"},
4708
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4709
    0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4710
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4711
    0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4712
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4713
    0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4714
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4715
    0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4716
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4717
    0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4718
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4719
    0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4720
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4721
    0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4722
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4723
    0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4724
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4725
    0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4726
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4727
    0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4728
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4729
    0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4730
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4731
    0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4732
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4733
    0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4734
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4735
    0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4736
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4737
    0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4738
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4739
    0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4740
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4741
    0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4742
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4743
    0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4744
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4745
    0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4746
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4747
    0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4748
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4749
    0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4750
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4751
    0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4752
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4753
    0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4754
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4755
    0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4756
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4757
    0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4758
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4759
    0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4760
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4761
    0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4762
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4763
    0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4764
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4765
    0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4766
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4767
    0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4768
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4769
    0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4770
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4771
    0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, %{I:#%0-7W%}]"},
4772
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4773
    0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4774
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4775
    0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4776
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4777
    0xf810f000, 0xff70f000, "pld%c\t%a"},
4778
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4779
    0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4780
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4781
    0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4782
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4783
    0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4784
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4785
    0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4786
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4787
    0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4788
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4789
    0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4790
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4791
    0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4792
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4793
    0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4794
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4795
    0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4796
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4797
    0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4798
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4799
    0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4800
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4801
    0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4802
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4803
    0xfb100000, 0xfff000c0,
4804
    "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4805
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4806
    0xfbc00080, 0xfff000c0,
4807
    "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4808
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4809
    0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4810
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4811
    0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4812
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4813
    0xf3000000, 0xffd08020, "ssat%c\t%8-11r, %{I:#%0-4D%}, %16-19r%s"},
4814
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4815
    0xf3800000, 0xffd08020, "usat%c\t%8-11r, %{I:#%0-4d%}, %16-19r%s"},
4816
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4817
    0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4818
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4819
    0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4820
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4821
    0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4822
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4823
    0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4824
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4825
    0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4826
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4827
    0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4828
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4829
    0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4830
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4831
    0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4832
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4833
    0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4834
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4835
    0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4836
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4837
    0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4838
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4839
    0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4840
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4841
    0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4842
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4843
    0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4844
  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4845
    0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, %{I:#%0-7W%}]"},
4846
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4847
    0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4848
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4849
    0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4850
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4851
    0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4852
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4853
    0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4854
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4855
    0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4856
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4857
    0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4858
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4859
    0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4860
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4861
    0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4862
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4863
    0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4864
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4865
    0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4866
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4867
    0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4868
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4869
    0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4870
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4871
    0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4872
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4873
    0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4874
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4875
    0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4876
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4877
    0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4878
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4879
    0xe9400000, 0xff500000,
4880
    "strd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
4881
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882
    0xe9500000, 0xff500000,
4883
    "ldrd%c\t%12-15r, %8-11r, [%16-19r, %{I:#%23`-%0-7W%}]%21'!%L"},
4884
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4885
    0xe8600000, 0xff700000,
4886
    "strd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
4887
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888
    0xe8700000, 0xff700000,
4889
    "ldrd%c\t%12-15r, %8-11r, [%16-19r], %{I:#%23`-%0-7W%}%L"},
4890
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4891
    0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4892
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4893
    0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
4894
4895
  /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
4896
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4897
    0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4898
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4899
    0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4900
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4901
    0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4902
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4903
    0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
4904
4905
  /* These have been 32-bit since the invention of Thumb.  */
4906
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4907
     0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4908
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4909
     0xf000d000, 0xf800d000, "bl%c\t%B%x"},
4910
4911
  /* Fallback.  */
4912
  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4913
      0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4914
  {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4915
};
4916
4917
static const char *const arm_conditional[] =
4918
{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
4919
 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
4920
4921
static const char *const arm_shift[] =
4922
{"lsl", "lsr", "asr", "ror"};
4923
4924
typedef struct
4925
{
4926
  const char *name;
4927
  const char *description;
4928
  const char *reg_names[16];
4929
}
4930
arm_regname;
4931
4932
static const arm_regname regnames[] =
4933
{
4934
  { "reg-names-raw", N_("Select raw register names"),
4935
    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
4936
  { "reg-names-gcc", N_("Select register names used by GCC"),
4937
    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
4938
  { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
4939
    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
4940
  { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
4941
  { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
4942
  { "reg-names-apcs", N_("Select register names used in the APCS"),
4943
    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
4944
  { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
4945
    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
4946
  { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4947
    { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }},
4948
  { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
4949
};
4950
4951
static const char *const iwmmxt_wwnames[] =
4952
{"b", "h", "w", "d"};
4953
4954
static const char *const iwmmxt_wwssnames[] =
4955
{"b", "bus", "bc", "bss",
4956
 "h", "hus", "hc", "hss",
4957
 "w", "wus", "wc", "wss",
4958
 "d", "dus", "dc", "dss"
4959
};
4960
4961
static const char *const iwmmxt_regnames[] =
4962
{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4963
  "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4964
};
4965
4966
static const char *const iwmmxt_cregnames[] =
4967
{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4968
  "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4969
};
4970
4971
static const char *const vec_condnames[] =
4972
{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4973
};
4974
4975
static const char *const mve_predicatenames[] =
4976
{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4977
  "eee", "ee", "eet", "e", "ett", "et", "ete"
4978
};
4979
4980
/* Names for 2-bit size field for mve vector isntructions.  */
4981
static const char *const mve_vec_sizename[] =
4982
  { "8", "16", "32", "64"};
4983
4984
/* Indicates whether we are processing a then predicate,
4985
   else predicate or none at all.  */
4986
enum vpt_pred_state
4987
{
4988
  PRED_NONE,
4989
  PRED_THEN,
4990
  PRED_ELSE
4991
};
4992
4993
/* Information used to process a vpt block and subsequent instructions.  */
4994
struct vpt_block
4995
{
4996
  /* Are we in a vpt block.  */
4997
  bool in_vpt_block;
4998
4999
  /* Next predicate state if in vpt block.  */
5000
  enum vpt_pred_state next_pred_state;
5001
5002
  /* Mask from vpt/vpst instruction.  */
5003
  long predicate_mask;
5004
5005
  /* Instruction number in vpt block.  */
5006
  long current_insn_num;
5007
5008
  /* Number of instructions in vpt block..   */
5009
  long num_pred_insn;
5010
};
5011
5012
static struct vpt_block vpt_block_state =
5013
{
5014
  false,
5015
  PRED_NONE,
5016
  0,
5017
  0,
5018
  0
5019
};
5020
5021
/* Default to GCC register name set.  */
5022
static unsigned int regname_selected = 1;
5023
5024
4.47k
#define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
5025
7.08M
#define arm_regnames      regnames[regname_selected].reg_names
5026
5027
static bool force_thumb = false;
5028
static uint16_t cde_coprocs = 0;
5029
5030
/* Current IT instruction state.  This contains the same state as the IT
5031
   bits in the CPSR.  */
5032
static unsigned int ifthen_state;
5033
/* IT state for the next instruction.  */
5034
static unsigned int ifthen_next_state;
5035
/* The address of the insn for which the IT state is valid.  */
5036
static bfd_vma ifthen_address;
5037
4.26M
#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5038
/* Indicates that the current Conditional state is unconditional or outside
5039
   an IT block.  */
5040
240M
#define COND_UNCOND 16
5041
5042

5043
/* Functions.  */
5044
/* Extract the predicate mask for a VPT or VPST instruction.
5045
   The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh).  */
5046
5047
static long
5048
mve_extract_pred_mask (long given)
5049
18.5k
{
5050
18.5k
  return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5051
18.5k
}
5052
5053
/* Return the number of instructions in a MVE predicate block.  */
5054
static long
5055
num_instructions_vpt_block (long given)
5056
4.19k
{
5057
4.19k
  long mask = mve_extract_pred_mask (given);
5058
4.19k
  if (mask == 0)
5059
0
    return 0;
5060
5061
4.19k
  if (mask == 8)
5062
1.12k
    return 1;
5063
5064
3.06k
  if ((mask & 7) == 4)
5065
1.09k
    return 2;
5066
5067
1.97k
  if ((mask & 3) == 2)
5068
432
    return 3;
5069
5070
1.54k
  if ((mask & 1) == 1)
5071
1.54k
    return 4;
5072
5073
0
  return 0;
5074
1.54k
}
5075
5076
static void
5077
mark_outside_vpt_block (void)
5078
4.19k
{
5079
4.19k
  vpt_block_state.in_vpt_block = false;
5080
4.19k
  vpt_block_state.next_pred_state = PRED_NONE;
5081
4.19k
  vpt_block_state.predicate_mask = 0;
5082
4.19k
  vpt_block_state.current_insn_num = 0;
5083
4.19k
  vpt_block_state.num_pred_insn = 0;
5084
4.19k
}
5085
5086
static void
5087
mark_inside_vpt_block (long given)
5088
4.19k
{
5089
4.19k
  vpt_block_state.in_vpt_block = true;
5090
4.19k
  vpt_block_state.next_pred_state = PRED_THEN;
5091
4.19k
  vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5092
4.19k
  vpt_block_state.current_insn_num = 0;
5093
4.19k
  vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5094
4.19k
  assert (vpt_block_state.num_pred_insn >= 1);
5095
4.19k
}
5096
5097
static enum vpt_pred_state
5098
invert_next_predicate_state (enum vpt_pred_state astate)
5099
3.57k
{
5100
3.57k
  if (astate == PRED_THEN)
5101
2.24k
    return PRED_ELSE;
5102
1.32k
  else if (astate == PRED_ELSE)
5103
1.32k
    return PRED_THEN;
5104
0
  else
5105
0
    return PRED_NONE;
5106
3.57k
}
5107
5108
static enum vpt_pred_state
5109
update_next_predicate_state (void)
5110
6.58k
{
5111
6.58k
  long pred_mask = vpt_block_state.predicate_mask;
5112
6.58k
  long mask_for_insn = 0;
5113
5114
6.58k
  switch (vpt_block_state.current_insn_num)
5115
6.58k
    {
5116
3.06k
    case 1:
5117
3.06k
      mask_for_insn = 8;
5118
3.06k
      break;
5119
5120
1.97k
    case 2:
5121
1.97k
      mask_for_insn = 4;
5122
1.97k
      break;
5123
5124
1.54k
    case 3:
5125
1.54k
      mask_for_insn = 2;
5126
1.54k
      break;
5127
5128
0
    case 4:
5129
0
      return PRED_NONE;
5130
6.58k
    }
5131
5132
6.58k
  if (pred_mask & mask_for_insn)
5133
3.57k
    return invert_next_predicate_state (vpt_block_state.next_pred_state);
5134
3.00k
  else
5135
3.00k
    return vpt_block_state.next_pred_state;
5136
6.58k
}
5137
5138
static void
5139
update_vpt_block_state (void)
5140
10.7k
{
5141
10.7k
  vpt_block_state.current_insn_num++;
5142
10.7k
  if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5143
4.19k
    {
5144
      /* No more instructions to process in vpt block.  */
5145
4.19k
      mark_outside_vpt_block ();
5146
4.19k
      return;
5147
4.19k
    }
5148
5149
6.58k
  vpt_block_state.next_pred_state = update_next_predicate_state ();
5150
6.58k
}
5151
5152
/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5153
   Returns pointer to following character of the format string and
5154
   fills in *VALUEP and *WIDTHP with the extracted value and number of
5155
   bits extracted.  WIDTHP can be NULL.  */
5156
5157
static const char *
5158
arm_decode_bitfield (const char *ptr,
5159
         unsigned long insn,
5160
         unsigned long *valuep,
5161
         int *widthp)
5162
4.71M
{
5163
4.71M
  unsigned long value = 0;
5164
4.71M
  int width = 0;
5165
5166
4.71M
  do
5167
5.05M
    {
5168
5.05M
      int start, end;
5169
5.05M
      int bits;
5170
5171
13.8M
      for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5172
8.75M
  start = start * 10 + *ptr - '0';
5173
5.05M
      if (*ptr == '-')
5174
9.91M
  for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5175
6.48M
    end = end * 10 + *ptr - '0';
5176
1.63M
      else
5177
1.63M
  end = start;
5178
5.05M
      bits = end - start;
5179
5.05M
      if (bits < 0)
5180
0
  abort ();
5181
5.05M
      value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5182
5.05M
      width += bits + 1;
5183
5.05M
    }
5184
5.05M
  while (*ptr++ == ',');
5185
4.71M
  *valuep = value;
5186
4.71M
  if (widthp)
5187
4.71M
    *widthp = width;
5188
4.71M
  return ptr - 1;
5189
4.71M
}
5190
5191
static void
5192
arm_decode_shift (long given, fprintf_styled_ftype func, void *stream,
5193
      bool print_shift)
5194
539k
{
5195
539k
  func (stream, dis_style_register, "%s", arm_regnames[given & 0xf]);
5196
5197
539k
  if ((given & 0xff0) != 0)
5198
336k
    {
5199
336k
      if ((given & 0x10) == 0)
5200
267k
  {
5201
267k
    int amount = (given & 0xf80) >> 7;
5202
267k
    int shift = (given & 0x60) >> 5;
5203
5204
267k
    if (amount == 0)
5205
26.7k
      {
5206
26.7k
        if (shift == 3)
5207
4.59k
    {
5208
4.59k
      func (stream, dis_style_text, ", ");
5209
4.59k
      func (stream, dis_style_sub_mnemonic, "rrx");
5210
4.59k
      return;
5211
4.59k
    }
5212
5213
22.1k
        amount = 32;
5214
22.1k
      }
5215
5216
263k
    if (print_shift)
5217
262k
      {
5218
262k
        func (stream, dis_style_text, ", ");
5219
262k
        func (stream, dis_style_sub_mnemonic, "%s ", arm_shift[shift]);
5220
262k
        func (stream, dis_style_immediate, "#%d", amount);
5221
262k
      }
5222
930
    else
5223
930
      {
5224
930
        func (stream, dis_style_text, ", ");
5225
930
        func (stream, dis_style_immediate, "#%d", amount);
5226
930
      }
5227
263k
  }
5228
68.7k
      else if ((given & 0x80) == 0x80)
5229
1.09k
  func (stream, dis_style_comment_start,
5230
1.09k
        "\t@ <illegal shifter operand>");
5231
67.6k
      else if (print_shift)
5232
67.3k
  {
5233
67.3k
    func (stream, dis_style_text, ", ");
5234
67.3k
    func (stream, dis_style_sub_mnemonic, "%s ",
5235
67.3k
    arm_shift[(given & 0x60) >> 5]);
5236
67.3k
    func (stream, dis_style_register, "%s",
5237
67.3k
    arm_regnames[(given & 0xf00) >> 8]);
5238
67.3k
  }
5239
238
      else
5240
238
  {
5241
238
    func (stream, dis_style_text, ", ");
5242
238
    func (stream, dis_style_register, "%s",
5243
238
    arm_regnames[(given & 0xf00) >> 8]);
5244
238
  }
5245
336k
    }
5246
539k
}
5247
5248
/* Return TRUE if the MATCHED_INSN can be inside an IT block.  */
5249
5250
static bool
5251
is_mve_okay_in_it (enum mve_instructions matched_insn)
5252
8.83k
{
5253
8.83k
  switch (matched_insn)
5254
8.83k
    {
5255
499
    case MVE_VMOV_GP_TO_VEC_LANE:
5256
762
    case MVE_VMOV2_VEC_LANE_TO_GP:
5257
1.26k
    case MVE_VMOV2_GP_TO_VEC_LANE:
5258
1.49k
    case MVE_VMOV_VEC_LANE_TO_GP:
5259
1.76k
    case MVE_LSLL:
5260
2.17k
    case MVE_LSLLI:
5261
2.74k
    case MVE_LSRL:
5262
3.15k
    case MVE_ASRL:
5263
3.62k
    case MVE_ASRLI:
5264
3.87k
    case MVE_SQRSHRL:
5265
4.30k
    case MVE_SQRSHR:
5266
4.59k
    case MVE_UQRSHL:
5267
5.06k
    case MVE_UQRSHLL:
5268
5.43k
    case MVE_UQSHL:
5269
5.69k
    case MVE_UQSHLL:
5270
5.92k
    case MVE_URSHRL:
5271
6.15k
    case MVE_URSHR:
5272
6.34k
    case MVE_SRSHRL:
5273
6.54k
    case MVE_SRSHR:
5274
6.78k
    case MVE_SQSHLL:
5275
7.08k
    case MVE_SQSHL:
5276
7.08k
      return true;
5277
1.74k
    default:
5278
1.74k
      return false;
5279
8.83k
    }
5280
8.83k
}
5281
5282
static bool
5283
is_v81m_architecture (struct disassemble_info *info)
5284
649k
{
5285
649k
  struct arm_private_data *private_data = info->private_data;
5286
649k
  arm_feature_set allowed_arches = private_data->features;
5287
5288
649k
  arm_feature_set arm_ext_v8_1m_main
5289
649k
    = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5290
5291
649k
  if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5292
569k
      && !ARM_CPU_IS_ANY (allowed_arches))
5293
475k
    return true;
5294
174k
  else
5295
174k
    return false;
5296
649k
}
5297
5298
static bool
5299
is_vpt_instruction (long given)
5300
120k
{
5301
5302
  /* If mkh:mkl is '0000' then its not a vpt/vpst instruction.  */
5303
120k
  if ((given & 0x0040e000) == 0)
5304
11.5k
    return false;
5305
5306
  /* VPT floating point T1 variant.  */
5307
108k
  if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5308
  /* VPT floating point T2 variant.  */
5309
108k
      || ((given & 0xefb10f50) == 0xee310f40)
5310
  /* VPT vector T1 variant.  */
5311
107k
      || ((given & 0xff811f51) == 0xfe010f00)
5312
  /* VPT vector T2 variant.  */
5313
107k
      || ((given & 0xff811f51) == 0xfe010f01
5314
830
    && ((given & 0x300000) != 0x300000))
5315
  /* VPT vector T3 variant.  */
5316
106k
      || ((given & 0xff811f50) == 0xfe011f00)
5317
  /* VPT vector T4 variant.  */
5318
106k
      || ((given & 0xff811f70) == 0xfe010f40)
5319
  /* VPT vector T5 variant.  */
5320
105k
      || ((given & 0xff811f70) == 0xfe010f60)
5321
  /* VPT vector T6 variant.  */
5322
105k
      || ((given & 0xff811f50) == 0xfe011f40)
5323
  /* VPST vector T variant.  */
5324
104k
      || ((given & 0xffbf1fff) == 0xfe310f4d))
5325
4.19k
    return true;
5326
104k
  else
5327
104k
    return false;
5328
108k
}
5329
5330
/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5331
   and ending bitfield = END.  END must be greater than START.  */
5332
5333
static unsigned long
5334
arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5335
487k
{
5336
487k
  int bits = end - start;
5337
5338
487k
  if (bits < 0)
5339
0
    abort ();
5340
5341
487k
  return ((given >> start) & ((2ul << bits) - 1));
5342
487k
}
5343
5344
/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5345
   START:END and START2:END2.  END/END2 must be greater than
5346
   START/START2.  */
5347
5348
static unsigned long
5349
arm_decode_field_multiple (unsigned long given, unsigned int start,
5350
         unsigned int end, unsigned int start2,
5351
         unsigned int end2)
5352
52.5k
{
5353
52.5k
  int bits = end - start;
5354
52.5k
  int bits2 = end2 - start2;
5355
52.5k
  unsigned long value = 0;
5356
52.5k
  int width = 0;
5357
5358
52.5k
  if (bits2 < 0)
5359
0
    abort ();
5360
5361
52.5k
  value = arm_decode_field (given, start, end);
5362
52.5k
  width += bits + 1;
5363
5364
52.5k
  value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5365
52.5k
  return value;
5366
52.5k
}
5367
5368
/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5369
   This helps us decode instructions that change mnemonic depending on specific
5370
   operand values/encodings.  */
5371
5372
static bool
5373
is_mve_encoding_conflict (unsigned long given,
5374
        enum mve_instructions matched_insn)
5375
175k
{
5376
175k
  switch (matched_insn)
5377
175k
    {
5378
568
    case MVE_VPST:
5379
568
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5380
318
  return true;
5381
250
      else
5382
250
  return false;
5383
5384
3.03k
    case MVE_VPT_FP_T1:
5385
3.03k
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5386
719
  return true;
5387
2.31k
      if ((arm_decode_field (given, 12, 12) == 0)
5388
957
    && (arm_decode_field (given, 0, 0) == 1))
5389
454
  return true;
5390
1.86k
      return false;
5391
5392
3.09k
    case MVE_VPT_FP_T2:
5393
3.09k
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5394
957
  return true;
5395
2.14k
      if (arm_decode_field (given, 0, 3) == 0xd)
5396
272
  return true;
5397
1.86k
      return false;
5398
5399
1.43k
    case MVE_VPT_VEC_T1:
5400
3.40k
    case MVE_VPT_VEC_T2:
5401
4.83k
    case MVE_VPT_VEC_T3:
5402
6.98k
    case MVE_VPT_VEC_T4:
5403
7.99k
    case MVE_VPT_VEC_T5:
5404
9.62k
    case MVE_VPT_VEC_T6:
5405
9.62k
      if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5406
2.97k
  return true;
5407
6.64k
      if (arm_decode_field (given, 20, 21) == 3)
5408
499
  return true;
5409
6.15k
      return false;
5410
5411
719
    case MVE_VCMP_FP_T1:
5412
719
      if ((arm_decode_field (given, 12, 12) == 0)
5413
507
    && (arm_decode_field (given, 0, 0) == 1))
5414
238
  return true;
5415
481
      else
5416
481
  return false;
5417
5418
957
    case MVE_VCMP_FP_T2:
5419
957
      if (arm_decode_field (given, 0, 3) == 0xd)
5420
477
  return true;
5421
480
      else
5422
480
  return false;
5423
5424
1.59k
    case MVE_VQADD_T2:
5425
2.05k
    case MVE_VQSUB_T2:
5426
3.03k
    case MVE_VMUL_VEC_T2:
5427
3.87k
    case MVE_VMULH:
5428
5.45k
    case MVE_VRMULH:
5429
5.86k
    case MVE_VMLA:
5430
6.23k
    case MVE_VMAX:
5431
6.72k
    case MVE_VMIN:
5432
7.91k
    case MVE_VBRSR:
5433
8.40k
    case MVE_VADD_VEC_T2:
5434
8.61k
    case MVE_VSUB_VEC_T2:
5435
9.04k
    case MVE_VABAV:
5436
9.31k
    case MVE_VQRSHL_T1:
5437
9.58k
    case MVE_VQSHL_T4:
5438
9.93k
    case MVE_VRSHL_T1:
5439
10.3k
    case MVE_VSHL_T3:
5440
11.9k
    case MVE_VCADD_VEC:
5441
12.8k
    case MVE_VHCADD:
5442
14.1k
    case MVE_VDDUP:
5443
14.5k
    case MVE_VIDUP:
5444
15.1k
    case MVE_VQRDMLADH:
5445
16.0k
    case MVE_VQDMLAH:
5446
16.3k
    case MVE_VQRDMLAH:
5447
16.5k
    case MVE_VQDMLASH:
5448
16.9k
    case MVE_VQRDMLASH:
5449
17.2k
    case MVE_VQDMLSDH:
5450
17.9k
    case MVE_VQRDMLSDH:
5451
18.4k
    case MVE_VQDMULH_T3:
5452
18.9k
    case MVE_VQRDMULH_T4:
5453
19.2k
    case MVE_VQDMLADH:
5454
19.5k
    case MVE_VMLAS:
5455
21.7k
    case MVE_VMULL_INT:
5456
22.6k
    case MVE_VHADD_T2:
5457
23.2k
    case MVE_VHSUB_T2:
5458
23.5k
    case MVE_VCMP_VEC_T1:
5459
23.9k
    case MVE_VCMP_VEC_T2:
5460
24.2k
    case MVE_VCMP_VEC_T3:
5461
25.1k
    case MVE_VCMP_VEC_T4:
5462
25.3k
    case MVE_VCMP_VEC_T5:
5463
25.7k
    case MVE_VCMP_VEC_T6:
5464
25.7k
      if (arm_decode_field (given, 20, 21) == 3)
5465
6.15k
  return true;
5466
19.6k
      else
5467
19.6k
  return false;
5468
5469
690
    case MVE_VLD2:
5470
959
    case MVE_VLD4:
5471
2.10k
    case MVE_VST2:
5472
3.03k
    case MVE_VST4:
5473
3.03k
      if (arm_decode_field (given, 7, 8) == 3)
5474
341
  return true;
5475
2.69k
      else
5476
2.69k
  return false;
5477
5478
983
    case MVE_VSTRB_T1:
5479
1.79k
    case MVE_VSTRH_T2:
5480
1.79k
      if ((arm_decode_field (given, 24, 24) == 0)
5481
1.35k
    && (arm_decode_field (given, 21, 21) == 0))
5482
675
  {
5483
675
      return true;
5484
675
  }
5485
1.11k
      else if ((arm_decode_field (given, 7, 8) == 3))
5486
0
  return true;
5487
1.11k
      else
5488
1.11k
  return false;
5489
5490
1.31k
    case MVE_VLDRB_T1:
5491
2.30k
    case MVE_VLDRH_T2:
5492
3.13k
    case MVE_VLDRW_T7:
5493
4.08k
    case MVE_VSTRB_T5:
5494
4.96k
    case MVE_VSTRH_T6:
5495
5.53k
    case MVE_VSTRW_T7:
5496
5.53k
      if ((arm_decode_field (given, 24, 24) == 0)
5497
3.47k
    && (arm_decode_field (given, 21, 21) == 0))
5498
1.43k
  {
5499
1.43k
      return true;
5500
1.43k
  }
5501
4.10k
      else
5502
4.10k
  return false;
5503
5504
5.82k
    case MVE_VCVT_FP_FIX_VEC:
5505
5.82k
      return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5506
5507
6.41k
    case MVE_VBIC_IMM:
5508
9.55k
    case MVE_VORR_IMM:
5509
9.55k
      {
5510
9.55k
  unsigned long cmode = arm_decode_field (given, 8, 11);
5511
5512
9.55k
  if ((cmode & 1) == 0)
5513
5.82k
    return true;
5514
3.73k
  else if ((cmode & 0xc) == 0xc)
5515
1.16k
    return true;
5516
2.56k
  else
5517
2.56k
    return false;
5518
9.55k
      }
5519
5520
3.04k
    case MVE_VMVN_IMM:
5521
3.04k
      {
5522
3.04k
  unsigned long cmode = arm_decode_field (given, 8, 11);
5523
5524
3.04k
  if (cmode == 0xe)
5525
0
    return true;
5526
3.04k
  else if ((cmode & 0x9) == 1)
5527
0
    return true;
5528
3.04k
  else if ((cmode & 0xd) == 9)
5529
0
    return true;
5530
3.04k
  else
5531
3.04k
    return false;
5532
3.04k
      }
5533
5534
6.71k
    case MVE_VMOV_IMM_TO_VEC:
5535
6.71k
      if ((arm_decode_field (given, 5, 5) == 1)
5536
3.86k
    && (arm_decode_field (given, 8, 11) != 0xe))
5537
3.17k
  return true;
5538
3.54k
      else
5539
3.54k
  return false;
5540
5541
862
    case MVE_VMOVL:
5542
862
      {
5543
862
  unsigned long size = arm_decode_field (given, 19, 20);
5544
862
  if ((size == 0) || (size == 3))
5545
0
    return true;
5546
862
  else
5547
862
    return false;
5548
862
      }
5549
5550
662
    case MVE_VMAXA:
5551
1.25k
    case MVE_VMINA:
5552
1.78k
    case MVE_VMAXV:
5553
2.08k
    case MVE_VMAXAV:
5554
2.30k
    case MVE_VMINV:
5555
2.64k
    case MVE_VMINAV:
5556
2.92k
    case MVE_VQRSHL_T2:
5557
3.17k
    case MVE_VQSHL_T1:
5558
3.42k
    case MVE_VRSHL_T2:
5559
3.76k
    case MVE_VSHL_T2:
5560
4.04k
    case MVE_VSHLL_T2:
5561
4.24k
    case MVE_VADDV:
5562
4.65k
    case MVE_VMOVN:
5563
5.00k
    case MVE_VQMOVUN:
5564
5.44k
    case MVE_VQMOVN:
5565
5.44k
      if (arm_decode_field (given, 18, 19) == 3)
5566
660
  return true;
5567
4.78k
      else
5568
4.78k
  return false;
5569
5570
812
    case MVE_VMLSLDAV:
5571
1.44k
    case MVE_VRMLSLDAVH:
5572
3.26k
    case MVE_VMLALDAV:
5573
3.74k
    case MVE_VADDLV:
5574
3.74k
      if (arm_decode_field (given, 20, 22) == 7)
5575
1.20k
  return true;
5576
2.53k
      else
5577
2.53k
  return false;
5578
5579
1.55k
    case MVE_VRMLALDAVH:
5580
1.55k
      if ((arm_decode_field (given, 20, 22) & 6) == 6)
5581
204
  return true;
5582
1.34k
      else
5583
1.34k
  return false;
5584
5585
913
    case MVE_VDWDUP:
5586
2.60k
    case MVE_VIWDUP:
5587
2.60k
      if ((arm_decode_field (given, 20, 21) == 3)
5588
2.39k
    || (arm_decode_field (given, 1, 3) == 7))
5589
656
  return true;
5590
1.95k
      else
5591
1.95k
  return false;
5592
5593
5594
1.95k
    case MVE_VSHLL_T1:
5595
1.95k
      if (arm_decode_field (given, 16, 18) == 0)
5596
1.11k
  {
5597
1.11k
    unsigned long sz = arm_decode_field (given, 19, 20);
5598
5599
1.11k
    if ((sz == 1) || (sz == 2))
5600
862
      return true;
5601
256
    else
5602
256
      return false;
5603
1.11k
  }
5604
833
      else
5605
833
  return false;
5606
5607
429
    case MVE_VQSHL_T2:
5608
1.27k
    case MVE_VQSHLU_T3:
5609
2.12k
    case MVE_VRSHR:
5610
2.52k
    case MVE_VSHL_T1:
5611
3.22k
    case MVE_VSHR:
5612
3.45k
    case MVE_VSLI:
5613
3.89k
    case MVE_VSRI:
5614
3.89k
      if (arm_decode_field (given, 19, 21) == 0)
5615
733
  return true;
5616
3.16k
      else
5617
3.16k
  return false;
5618
5619
645
    case MVE_VCTP:
5620
645
    if (arm_decode_field (given, 16, 19) == 0xf)
5621
200
      return true;
5622
445
    else
5623
445
      return false;
5624
5625
685
    case MVE_ASRLI:
5626
1.24k
    case MVE_ASRL:
5627
2.50k
    case MVE_LSLLI:
5628
3.02k
    case MVE_LSLL:
5629
4.07k
    case MVE_LSRL:
5630
5.01k
    case MVE_SQRSHRL:
5631
5.65k
    case MVE_SQSHLL:
5632
6.11k
    case MVE_SRSHRL:
5633
6.94k
    case MVE_UQRSHLL:
5634
7.36k
    case MVE_UQSHLL:
5635
7.88k
    case MVE_URSHRL:
5636
7.88k
      if (arm_decode_field (given, 9, 11) == 0x7)
5637
2.48k
  return true;
5638
5.39k
      else
5639
5.39k
  return false;
5640
5641
577
    case MVE_CSINC:
5642
1.55k
    case MVE_CSINV:
5643
1.55k
      {
5644
1.55k
  unsigned long rm, rn;
5645
1.55k
  rm = arm_decode_field (given, 0, 3);
5646
1.55k
  rn = arm_decode_field (given, 16, 19);
5647
  /* CSET/CSETM.  */
5648
1.55k
  if (rm == 0xf && rn == 0xf)
5649
201
    return true;
5650
  /* CINC/CINV.  */
5651
1.35k
  else if (rn == rm && rn != 0xf)
5652
447
    return true;
5653
1.55k
      }
5654
    /* Fall through.  */
5655
1.46k
    case MVE_CSEL:
5656
2.35k
    case MVE_CSNEG:
5657
2.35k
      if (arm_decode_field (given, 0, 3) == 0xd)
5658
295
  return true;
5659
      /* CNEG.  */
5660
2.05k
      else if (matched_insn == MVE_CSNEG)
5661
735
  if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5662
276
    return true;
5663
1.78k
      return false;
5664
5665
63.9k
    default:
5666
64.3k
    case MVE_VADD_FP_T1:
5667
64.7k
    case MVE_VADD_FP_T2:
5668
65.0k
    case MVE_VADD_VEC_T1:
5669
65.0k
      return false;
5670
5671
175k
    }
5672
175k
}
5673
5674
static void
5675
print_mve_vld_str_addr (struct disassemble_info *info,
5676
      unsigned long given,
5677
      enum mve_instructions matched_insn)
5678
6.78k
{
5679
6.78k
  void *stream = info->stream;
5680
6.78k
  fprintf_styled_ftype func = info->fprintf_styled_func;
5681
5682
6.78k
  unsigned long p, w, gpr, imm, add, mod_imm;
5683
5684
6.78k
  imm = arm_decode_field (given, 0, 6);
5685
6.78k
  mod_imm = imm;
5686
5687
6.78k
  switch (matched_insn)
5688
6.78k
    {
5689
745
    case MVE_VLDRB_T1:
5690
1.29k
    case MVE_VSTRB_T1:
5691
1.29k
      gpr = arm_decode_field (given, 16, 18);
5692
1.29k
      break;
5693
5694
487
    case MVE_VLDRH_T2:
5695
1.05k
    case MVE_VSTRH_T2:
5696
1.05k
      gpr = arm_decode_field (given, 16, 18);
5697
1.05k
      mod_imm = imm << 1;
5698
1.05k
      break;
5699
5700
1.25k
    case MVE_VLDRH_T6:
5701
2.02k
    case MVE_VSTRH_T6:
5702
2.02k
      gpr = arm_decode_field (given, 16, 19);
5703
2.02k
      mod_imm = imm << 1;
5704
2.02k
      break;
5705
5706
787
    case MVE_VLDRW_T7:
5707
1.18k
    case MVE_VSTRW_T7:
5708
1.18k
      gpr = arm_decode_field (given, 16, 19);
5709
1.18k
      mod_imm = imm << 2;
5710
1.18k
      break;
5711
5712
316
    case MVE_VLDRB_T5:
5713
1.22k
    case MVE_VSTRB_T5:
5714
1.22k
      gpr = arm_decode_field (given, 16, 19);
5715
1.22k
      break;
5716
5717
0
    default:
5718
0
      return;
5719
6.78k
    }
5720
5721
6.78k
  p = arm_decode_field (given, 24, 24);
5722
6.78k
  w = arm_decode_field (given, 21, 21);
5723
5724
6.78k
  add = arm_decode_field (given, 23, 23);
5725
5726
6.78k
  char * add_sub;
5727
5728
  /* Don't print anything for '+' as it is implied.  */
5729
6.78k
  if (add == 1)
5730
4.53k
    add_sub = "";
5731
2.24k
  else
5732
2.24k
    add_sub = "-";
5733
5734
6.78k
  func (stream, dis_style_text, "[");
5735
6.78k
  func (stream, dis_style_register, "%s", arm_regnames[gpr]);
5736
6.78k
  if (p == 1)
5737
3.45k
    {
5738
3.45k
      func (stream, dis_style_text, ", ");
5739
3.45k
      func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
5740
      /* Offset mode.  */
5741
3.45k
      if (w == 0)
5742
1.41k
  func (stream, dis_style_text, "]");
5743
      /* Pre-indexed mode.  */
5744
2.04k
      else
5745
2.04k
  func (stream, dis_style_text, "]!");
5746
3.45k
    }
5747
3.32k
  else if ((p == 0) && (w == 1))
5748
2.97k
    {
5749
      /* Post-index mode.  */
5750
2.97k
      func (stream, dis_style_text, "], ");
5751
2.97k
      func (stream, dis_style_immediate, "#%s%lu", add_sub, mod_imm);
5752
2.97k
    }
5753
6.78k
}
5754
5755
/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5756
   Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5757
   this encoding is undefined.  */
5758
5759
static bool
5760
is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5761
      enum mve_undefined *undefined_code)
5762
140k
{
5763
140k
  *undefined_code = UNDEF_NONE;
5764
5765
140k
  switch (matched_insn)
5766
140k
    {
5767
1.01k
    case MVE_VDUP:
5768
1.01k
      if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5769
227
  {
5770
227
    *undefined_code = UNDEF_SIZE_3;
5771
227
    return true;
5772
227
  }
5773
787
      else
5774
787
  return false;
5775
5776
877
    case MVE_VQADD_T1:
5777
1.12k
    case MVE_VQSUB_T1:
5778
1.58k
    case MVE_VMUL_VEC_T1:
5779
2.01k
    case MVE_VABD_VEC:
5780
2.29k
    case MVE_VADD_VEC_T1:
5781
2.53k
    case MVE_VSUB_VEC_T1:
5782
2.79k
    case MVE_VQDMULH_T1:
5783
3.36k
    case MVE_VQRDMULH_T2:
5784
4.39k
    case MVE_VRHADD:
5785
5.17k
    case MVE_VHADD_T1:
5786
5.60k
    case MVE_VHSUB_T1:
5787
5.60k
      if (arm_decode_field (given, 20, 21) == 3)
5788
696
  {
5789
696
    *undefined_code = UNDEF_SIZE_3;
5790
696
    return true;
5791
696
  }
5792
4.90k
      else
5793
4.90k
  return false;
5794
5795
745
    case MVE_VLDRB_T1:
5796
745
      if (arm_decode_field (given, 7, 8) == 3)
5797
225
  {
5798
225
    *undefined_code = UNDEF_SIZE_3;
5799
225
    return true;
5800
225
  }
5801
520
      else
5802
520
  return false;
5803
5804
487
    case MVE_VLDRH_T2:
5805
487
      if (arm_decode_field (given, 7, 8) <= 1)
5806
244
  {
5807
244
    *undefined_code = UNDEF_SIZE_LE_1;
5808
244
    return true;
5809
244
  }
5810
243
      else
5811
243
  return false;
5812
5813
549
    case MVE_VSTRB_T1:
5814
549
      if ((arm_decode_field (given, 7, 8) == 0))
5815
223
  {
5816
223
    *undefined_code = UNDEF_SIZE_0;
5817
223
    return true;
5818
223
  }
5819
326
      else
5820
326
  return false;
5821
5822
570
    case MVE_VSTRH_T2:
5823
570
      if ((arm_decode_field (given, 7, 8) <= 1))
5824
249
  {
5825
249
    *undefined_code = UNDEF_SIZE_LE_1;
5826
249
    return true;
5827
249
  }
5828
321
      else
5829
321
  return false;
5830
5831
1.17k
    case MVE_VLDRB_GATHER_T1:
5832
1.17k
      if (arm_decode_field (given, 7, 8) == 3)
5833
337
  {
5834
337
    *undefined_code = UNDEF_SIZE_3;
5835
337
    return true;
5836
337
  }
5837
837
      else if ((arm_decode_field (given, 28, 28) == 0)
5838
621
         && (arm_decode_field (given, 7, 8) == 0))
5839
226
  {
5840
226
    *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5841
226
    return true;
5842
226
  }
5843
611
      else
5844
611
  return false;
5845
5846
1.48k
    case MVE_VLDRH_GATHER_T2:
5847
1.48k
      if (arm_decode_field (given, 7, 8) == 3)
5848
743
  {
5849
743
    *undefined_code = UNDEF_SIZE_3;
5850
743
    return true;
5851
743
  }
5852
739
      else if ((arm_decode_field (given, 28, 28) == 0)
5853
531
         && (arm_decode_field (given, 7, 8) == 1))
5854
207
  {
5855
207
    *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5856
207
    return true;
5857
207
  }
5858
532
      else if (arm_decode_field (given, 7, 8) == 0)
5859
306
  {
5860
306
    *undefined_code = UNDEF_SIZE_0;
5861
306
    return true;
5862
306
  }
5863
226
      else
5864
226
  return false;
5865
5866
230
    case MVE_VLDRW_GATHER_T3:
5867
230
      if (arm_decode_field (given, 7, 8) != 2)
5868
0
  {
5869
0
    *undefined_code = UNDEF_SIZE_NOT_2;
5870
0
    return true;
5871
0
  }
5872
230
      else if (arm_decode_field (given, 28, 28) == 0)
5873
0
  {
5874
0
    *undefined_code = UNDEF_NOT_UNSIGNED;
5875
0
    return true;
5876
0
  }
5877
230
      else
5878
230
  return false;
5879
5880
482
    case MVE_VLDRD_GATHER_T4:
5881
482
      if (arm_decode_field (given, 7, 8) != 3)
5882
0
  {
5883
0
    *undefined_code = UNDEF_SIZE_NOT_3;
5884
0
    return true;
5885
0
  }
5886
482
      else if (arm_decode_field (given, 28, 28) == 0)
5887
255
  {
5888
255
    *undefined_code = UNDEF_NOT_UNSIGNED;
5889
255
    return true;
5890
255
  }
5891
227
      else
5892
227
  return false;
5893
5894
1.72k
    case MVE_VSTRB_SCATTER_T1:
5895
1.72k
      if (arm_decode_field (given, 7, 8) == 3)
5896
405
  {
5897
405
    *undefined_code = UNDEF_SIZE_3;
5898
405
    return true;
5899
405
  }
5900
1.32k
      else
5901
1.32k
  return false;
5902
5903
1.00k
    case MVE_VSTRH_SCATTER_T2:
5904
1.00k
      {
5905
1.00k
  unsigned long size = arm_decode_field (given, 7, 8);
5906
1.00k
  if (size == 3)
5907
308
    {
5908
308
      *undefined_code = UNDEF_SIZE_3;
5909
308
      return true;
5910
308
    }
5911
697
  else if (size == 0)
5912
279
    {
5913
279
      *undefined_code = UNDEF_SIZE_0;
5914
279
      return true;
5915
279
    }
5916
418
  else
5917
418
    return false;
5918
1.00k
      }
5919
5920
964
    case MVE_VSTRW_SCATTER_T3:
5921
964
      if (arm_decode_field (given, 7, 8) != 2)
5922
742
  {
5923
742
    *undefined_code = UNDEF_SIZE_NOT_2;
5924
742
    return true;
5925
742
  }
5926
222
      else
5927
222
  return false;
5928
5929
292
    case MVE_VSTRD_SCATTER_T4:
5930
292
      if (arm_decode_field (given, 7, 8) != 3)
5931
0
  {
5932
0
    *undefined_code = UNDEF_SIZE_NOT_3;
5933
0
    return true;
5934
0
  }
5935
292
      else
5936
292
  return false;
5937
5938
4.59k
    case MVE_VCVT_FP_FIX_VEC:
5939
4.59k
      {
5940
4.59k
  unsigned long imm6 = arm_decode_field (given, 16, 21);
5941
4.59k
  if ((imm6 & 0x20) == 0)
5942
364
    {
5943
364
      *undefined_code = UNDEF_VCVT_IMM6;
5944
364
      return true;
5945
364
    }
5946
5947
4.23k
  if ((arm_decode_field (given, 9, 9) == 0)
5948
1.49k
      && ((imm6 & 0x30) == 0x20))
5949
1.13k
    {
5950
1.13k
      *undefined_code = UNDEF_VCVT_FSI_IMM6;
5951
1.13k
      return true;
5952
1.13k
    }
5953
5954
3.09k
  return false;
5955
4.23k
      }
5956
5957
245
    case MVE_VNEG_FP:
5958
452
    case MVE_VABS_FP:
5959
3.25k
    case MVE_VCVT_BETWEEN_FP_INT:
5960
6.89k
    case MVE_VCVT_FROM_FP_TO_INT:
5961
6.89k
      {
5962
6.89k
  unsigned long size = arm_decode_field (given, 18, 19);
5963
6.89k
  if (size == 0)
5964
682
    {
5965
682
      *undefined_code = UNDEF_SIZE_0;
5966
682
      return true;
5967
682
    }
5968
6.21k
  else if (size == 3)
5969
1.80k
    {
5970
1.80k
      *undefined_code = UNDEF_SIZE_3;
5971
1.80k
      return true;
5972
1.80k
    }
5973
4.40k
  else
5974
4.40k
    return false;
5975
6.89k
      }
5976
5977
650
    case MVE_VMOV_VEC_LANE_TO_GP:
5978
650
      {
5979
650
  unsigned long op1 = arm_decode_field (given, 21, 22);
5980
650
  unsigned long op2 = arm_decode_field (given, 5, 6);
5981
650
  unsigned long u = arm_decode_field (given, 23, 23);
5982
5983
650
  if ((op2 == 0) && (u == 1))
5984
0
    {
5985
0
      if ((op1 == 0) || (op1 == 1))
5986
0
        {
5987
0
    *undefined_code = UNDEF_BAD_U_OP1_OP2;
5988
0
    return true;
5989
0
        }
5990
0
      else
5991
0
        return false;
5992
0
    }
5993
650
  else if (op2 == 2)
5994
650
    {
5995
650
      if ((op1 == 0) || (op1 == 1))
5996
650
        {
5997
650
    *undefined_code = UNDEF_BAD_OP1_OP2;
5998
650
    return true;
5999
650
        }
6000
0
      else
6001
0
        return false;
6002
650
    }
6003
6004
0
  return false;
6005
650
      }
6006
6007
922
    case MVE_VMOV_GP_TO_VEC_LANE:
6008
922
      if (arm_decode_field (given, 5, 6) == 2)
6009
922
  {
6010
922
    unsigned long op1 = arm_decode_field (given, 21, 22);
6011
922
    if ((op1 == 0) || (op1 == 1))
6012
922
      {
6013
922
        *undefined_code = UNDEF_BAD_OP1_OP2;
6014
922
        return true;
6015
922
      }
6016
0
    else
6017
0
      return false;
6018
922
  }
6019
0
      else
6020
0
  return false;
6021
6022
778
    case MVE_VMOV_VEC_TO_VEC:
6023
778
      if ((arm_decode_field (given, 5, 5) == 1)
6024
453
    || (arm_decode_field (given, 22, 22) == 1))
6025
580
    return true;
6026
198
      return false;
6027
6028
3.54k
    case MVE_VMOV_IMM_TO_VEC:
6029
3.54k
      if (arm_decode_field (given, 5, 5) == 0)
6030
2.85k
      {
6031
2.85k
  unsigned long cmode = arm_decode_field (given, 8, 11);
6032
6033
2.85k
  if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6034
0
    {
6035
0
      *undefined_code = UNDEF_OP_0_BAD_CMODE;
6036
0
      return true;
6037
0
    }
6038
2.85k
  else
6039
2.85k
    return false;
6040
2.85k
      }
6041
688
      else
6042
688
  return false;
6043
6044
279
    case MVE_VSHLL_T2:
6045
688
    case MVE_VMOVN:
6046
688
      if (arm_decode_field (given, 18, 19) == 2)
6047
408
  {
6048
408
    *undefined_code = UNDEF_SIZE_2;
6049
408
    return true;
6050
408
  }
6051
280
      else
6052
280
  return false;
6053
6054
1.34k
    case MVE_VRMLALDAVH:
6055
2.02k
    case MVE_VMLADAV_T1:
6056
2.40k
    case MVE_VMLADAV_T2:
6057
3.54k
    case MVE_VMLALDAV:
6058
3.54k
      if ((arm_decode_field (given, 28, 28) == 1)
6059
1.30k
    && (arm_decode_field (given, 12, 12) == 1))
6060
756
  {
6061
756
    *undefined_code = UNDEF_XCHG_UNS;
6062
756
    return true;
6063
756
  }
6064
2.79k
      else
6065
2.79k
  return false;
6066
6067
386
    case MVE_VQSHRN:
6068
872
    case MVE_VQSHRUN:
6069
1.96k
    case MVE_VSHLL_T1:
6070
2.33k
    case MVE_VSHRN:
6071
2.33k
      {
6072
2.33k
  unsigned long sz = arm_decode_field (given, 19, 20);
6073
2.33k
  if (sz == 1)
6074
788
    return false;
6075
1.54k
  else if ((sz & 2) == 2)
6076
904
    return false;
6077
640
  else
6078
640
    {
6079
640
      *undefined_code = UNDEF_SIZE;
6080
640
      return true;
6081
640
    }
6082
2.33k
      }
6083
0
      break;
6084
6085
429
    case MVE_VQSHL_T2:
6086
1.06k
    case MVE_VQSHLU_T3:
6087
1.62k
    case MVE_VRSHR:
6088
2.02k
    case MVE_VSHL_T1:
6089
2.69k
    case MVE_VSHR:
6090
2.91k
    case MVE_VSLI:
6091
3.16k
    case MVE_VSRI:
6092
3.16k
      {
6093
3.16k
  unsigned long sz = arm_decode_field (given, 19, 21);
6094
3.16k
  if ((sz & 7) == 1)
6095
598
    return false;
6096
2.56k
  else if ((sz & 6) == 2)
6097
297
    return false;
6098
2.26k
  else if ((sz & 4) == 4)
6099
2.26k
    return false;
6100
0
  else
6101
0
    {
6102
0
      *undefined_code = UNDEF_SIZE;
6103
0
      return true;
6104
0
    }
6105
3.16k
      }
6106
6107
372
    case MVE_VQRSHRN:
6108
894
    case MVE_VQRSHRUN:
6109
894
      if (arm_decode_field (given, 19, 20) == 0)
6110
354
  {
6111
354
    *undefined_code = UNDEF_SIZE_0;
6112
354
    return true;
6113
354
  }
6114
540
      else
6115
540
  return false;
6116
6117
580
    case MVE_VABS_VEC:
6118
580
  if (arm_decode_field (given, 18, 19) == 3)
6119
319
  {
6120
319
    *undefined_code = UNDEF_SIZE_3;
6121
319
    return true;
6122
319
  }
6123
261
  else
6124
261
    return false;
6125
6126
200
    case MVE_VQNEG:
6127
702
    case MVE_VQABS:
6128
1.06k
    case MVE_VNEG_VEC:
6129
1.26k
    case MVE_VCLS:
6130
1.47k
    case MVE_VCLZ:
6131
1.47k
      if (arm_decode_field (given, 18, 19) == 3)
6132
673
  {
6133
673
    *undefined_code = UNDEF_SIZE_3;
6134
673
    return true;
6135
673
  }
6136
805
      else
6137
805
  return false;
6138
6139
4.69k
    case MVE_VREV16:
6140
4.69k
      if (arm_decode_field (given, 18, 19) == 0)
6141
4.39k
  return false;
6142
294
      else
6143
294
  {
6144
294
    *undefined_code = UNDEF_SIZE_NOT_0;
6145
294
    return true;
6146
294
  }
6147
6148
642
    case MVE_VREV32:
6149
642
      {
6150
642
  unsigned long size = arm_decode_field (given, 18, 19);
6151
642
  if ((size & 2) == 2)
6152
201
    {
6153
201
      *undefined_code = UNDEF_SIZE_2;
6154
201
      return true;
6155
201
    }
6156
441
  else
6157
441
    return false;
6158
642
      }
6159
6160
568
    case MVE_VREV64:
6161
568
      if (arm_decode_field (given, 18, 19) != 3)
6162
237
  return false;
6163
331
      else
6164
331
  {
6165
331
    *undefined_code = UNDEF_SIZE_3;
6166
331
    return true;
6167
331
  }
6168
6169
88.4k
    default:
6170
88.4k
      return false;
6171
140k
    }
6172
140k
}
6173
6174
/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6175
   Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6176
   why this encoding is unpredictable.  */
6177
6178
static bool
6179
is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6180
          enum mve_unpredictable *unpredictable_code)
6181
139k
{
6182
139k
  *unpredictable_code = UNPRED_NONE;
6183
6184
139k
  switch (matched_insn)
6185
139k
    {
6186
480
    case MVE_VCMP_FP_T2:
6187
2.34k
    case MVE_VPT_FP_T2:
6188
2.34k
      if ((arm_decode_field (given, 12, 12) == 0)
6189
877
    && (arm_decode_field (given, 5, 5) == 1))
6190
501
  {
6191
501
    *unpredictable_code = UNPRED_FCA_0_FCB_1;
6192
501
    return true;
6193
501
  }
6194
1.84k
      else
6195
1.84k
  return false;
6196
6197
1.17k
    case MVE_VPT_VEC_T4:
6198
1.78k
    case MVE_VPT_VEC_T5:
6199
3.01k
    case MVE_VPT_VEC_T6:
6200
3.45k
    case MVE_VCMP_VEC_T4:
6201
3.69k
    case MVE_VCMP_VEC_T5:
6202
4.03k
    case MVE_VCMP_VEC_T6:
6203
4.03k
      if (arm_decode_field (given, 0, 3) == 0xd)
6204
703
  {
6205
703
    *unpredictable_code = UNPRED_R13;
6206
703
    return true;
6207
703
  }
6208
3.33k
      else
6209
3.33k
  return false;
6210
6211
1.01k
    case MVE_VDUP:
6212
1.01k
      {
6213
1.01k
  unsigned long gpr = arm_decode_field (given, 12, 15);
6214
1.01k
  if (gpr == 0xd)
6215
209
    {
6216
209
      *unpredictable_code = UNPRED_R13;
6217
209
      return true;
6218
209
    }
6219
805
  else if (gpr == 0xf)
6220
276
    {
6221
276
      *unpredictable_code = UNPRED_R15;
6222
276
      return true;
6223
276
    }
6224
6225
529
  return false;
6226
1.01k
      }
6227
6228
590
    case MVE_VQADD_T2:
6229
1.04k
    case MVE_VQSUB_T2:
6230
1.36k
    case MVE_VMUL_FP_T2:
6231
1.80k
    case MVE_VMUL_VEC_T2:
6232
2.21k
    case MVE_VMLA:
6233
2.81k
    case MVE_VBRSR:
6234
3.24k
    case MVE_VADD_FP_T2:
6235
3.56k
    case MVE_VSUB_FP_T2:
6236
3.98k
    case MVE_VADD_VEC_T2:
6237
4.20k
    case MVE_VSUB_VEC_T2:
6238
4.41k
    case MVE_VQRSHL_T2:
6239
4.66k
    case MVE_VQSHL_T1:
6240
4.90k
    case MVE_VRSHL_T2:
6241
5.24k
    case MVE_VSHL_T2:
6242
6.12k
    case MVE_VSHLC:
6243
6.80k
    case MVE_VQDMLAH:
6244
7.06k
    case MVE_VQRDMLAH:
6245
7.33k
    case MVE_VQDMLASH:
6246
7.71k
    case MVE_VQRDMLASH:
6247
8.20k
    case MVE_VQDMULH_T3:
6248
8.68k
    case MVE_VQRDMULH_T4:
6249
8.99k
    case MVE_VMLAS:
6250
9.24k
    case MVE_VFMA_FP_SCALAR:
6251
9.65k
    case MVE_VFMAS_FP_SCALAR:
6252
10.5k
    case MVE_VHADD_T2:
6253
10.8k
    case MVE_VHSUB_T2:
6254
10.8k
      {
6255
10.8k
  unsigned long gpr = arm_decode_field (given, 0, 3);
6256
10.8k
  if (gpr == 0xd)
6257
789
    {
6258
789
      *unpredictable_code = UNPRED_R13;
6259
789
      return true;
6260
789
    }
6261
10.0k
  else if (gpr == 0xf)
6262
2.27k
    {
6263
2.27k
      *unpredictable_code = UNPRED_R15;
6264
2.27k
      return true;
6265
2.27k
    }
6266
6267
7.80k
  return false;
6268
10.8k
      }
6269
6270
509
    case MVE_VLD2:
6271
1.63k
    case MVE_VST2:
6272
1.63k
      {
6273
1.63k
  unsigned long rn = arm_decode_field (given, 16, 19);
6274
6275
1.63k
  if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6276
722
    {
6277
722
      *unpredictable_code = UNPRED_R13_AND_WB;
6278
722
      return true;
6279
722
    }
6280
6281
914
  if (rn == 0xf)
6282
298
    {
6283
298
      *unpredictable_code = UNPRED_R15;
6284
298
      return true;
6285
298
    }
6286
6287
616
  if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6288
283
    {
6289
283
      *unpredictable_code = UNPRED_Q_GT_6;
6290
283
      return true;
6291
283
    }
6292
333
  else
6293
333
    return false;
6294
616
      }
6295
6296
269
    case MVE_VLD4:
6297
1.05k
    case MVE_VST4:
6298
1.05k
      {
6299
1.05k
  unsigned long rn = arm_decode_field (given, 16, 19);
6300
6301
1.05k
  if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6302
299
    {
6303
299
      *unpredictable_code = UNPRED_R13_AND_WB;
6304
299
      return true;
6305
299
    }
6306
6307
755
  if (rn == 0xf)
6308
230
    {
6309
230
      *unpredictable_code = UNPRED_R15;
6310
230
      return true;
6311
230
    }
6312
6313
525
  if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6314
250
    {
6315
250
      *unpredictable_code = UNPRED_Q_GT_4;
6316
250
      return true;
6317
250
    }
6318
275
  else
6319
275
    return false;
6320
525
      }
6321
6322
316
    case MVE_VLDRB_T5:
6323
1.56k
    case MVE_VLDRH_T6:
6324
2.34k
    case MVE_VLDRW_T7:
6325
3.25k
    case MVE_VSTRB_T5:
6326
4.02k
    case MVE_VSTRH_T6:
6327
4.42k
    case MVE_VSTRW_T7:
6328
4.42k
      {
6329
4.42k
  unsigned long rn = arm_decode_field (given, 16, 19);
6330
6331
4.42k
  if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6332
288
    {
6333
288
      *unpredictable_code = UNPRED_R13_AND_WB;
6334
288
      return true;
6335
288
    }
6336
4.13k
  else if (rn == 0xf)
6337
660
    {
6338
660
      *unpredictable_code = UNPRED_R15;
6339
660
      return true;
6340
660
    }
6341
3.47k
  else
6342
3.47k
    return false;
6343
4.42k
      }
6344
6345
1.17k
    case MVE_VLDRB_GATHER_T1:
6346
1.17k
      if (arm_decode_field (given, 0, 0) == 1)
6347
512
  {
6348
512
    *unpredictable_code = UNPRED_OS;
6349
512
    return true;
6350
512
  }
6351
6352
      /*  fall through.  */
6353
      /* To handle common code with T2-T4 variants.  */
6354
2.14k
    case MVE_VLDRH_GATHER_T2:
6355
2.37k
    case MVE_VLDRW_GATHER_T3:
6356
2.85k
    case MVE_VLDRD_GATHER_T4:
6357
2.85k
      {
6358
2.85k
  unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6359
2.85k
  unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6360
6361
2.85k
  if (qd == qm)
6362
443
    {
6363
443
      *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6364
443
      return true;
6365
443
    }
6366
6367
2.41k
  if (arm_decode_field (given, 16, 19) == 0xf)
6368
685
    {
6369
685
      *unpredictable_code = UNPRED_R15;
6370
685
      return true;
6371
685
    }
6372
6373
1.72k
  return false;
6374
2.41k
      }
6375
6376
728
    case MVE_VLDRW_GATHER_T5:
6377
1.04k
    case MVE_VLDRD_GATHER_T6:
6378
1.04k
      {
6379
1.04k
  unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6380
1.04k
  unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6381
6382
1.04k
  if (qd == qm)
6383
605
    {
6384
605
      *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6385
605
      return true;
6386
605
    }
6387
435
  else
6388
435
    return false;
6389
1.04k
      }
6390
6391
1.72k
    case MVE_VSTRB_SCATTER_T1:
6392
1.72k
      if (arm_decode_field (given, 16, 19) == 0xf)
6393
560
  {
6394
560
    *unpredictable_code = UNPRED_R15;
6395
560
    return true;
6396
560
  }
6397
1.16k
      else if (arm_decode_field (given, 0, 0) == 1)
6398
712
  {
6399
712
    *unpredictable_code = UNPRED_OS;
6400
712
    return true;
6401
712
  }
6402
457
      else
6403
457
  return false;
6404
6405
1.00k
    case MVE_VSTRH_SCATTER_T2:
6406
1.96k
    case MVE_VSTRW_SCATTER_T3:
6407
2.25k
    case MVE_VSTRD_SCATTER_T4:
6408
2.25k
      if (arm_decode_field (given, 16, 19) == 0xf)
6409
428
  {
6410
428
    *unpredictable_code = UNPRED_R15;
6411
428
    return true;
6412
428
  }
6413
1.82k
      else
6414
1.82k
  return false;
6415
6416
960
    case MVE_VMOV2_VEC_LANE_TO_GP:
6417
2.01k
    case MVE_VMOV2_GP_TO_VEC_LANE:
6418
4.80k
    case MVE_VCVT_BETWEEN_FP_INT:
6419
8.44k
    case MVE_VCVT_FROM_FP_TO_INT:
6420
8.44k
      {
6421
8.44k
  unsigned long rt = arm_decode_field (given, 0, 3);
6422
8.44k
  unsigned long rt2 = arm_decode_field (given, 16, 19);
6423
6424
8.44k
  if ((rt == 0xd) || (rt2 == 0xd))
6425
723
    {
6426
723
      *unpredictable_code = UNPRED_R13;
6427
723
      return true;
6428
723
    }
6429
7.71k
  else if ((rt == 0xf) || (rt2 == 0xf))
6430
2.10k
    {
6431
2.10k
      *unpredictable_code = UNPRED_R15;
6432
2.10k
      return true;
6433
2.10k
    }
6434
5.61k
  else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE)
6435
212
    {
6436
212
      *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6437
212
      return true;
6438
212
    }
6439
6440
5.40k
  return false;
6441
8.44k
      }
6442
6443
521
    case MVE_VMAXV:
6444
826
    case MVE_VMAXAV:
6445
1.02k
    case MVE_VMAXNMV_FP:
6446
1.33k
    case MVE_VMAXNMAV_FP:
6447
1.58k
    case MVE_VMINNMV_FP:
6448
1.80k
    case MVE_VMINNMAV_FP:
6449
2.02k
    case MVE_VMINV:
6450
2.36k
    case MVE_VMINAV:
6451
2.77k
    case MVE_VABAV:
6452
2.77k
    case MVE_VMOV_HFP_TO_GP:
6453
3.70k
    case MVE_VMOV_GP_TO_VEC_LANE:
6454
4.35k
    case MVE_VMOV_VEC_LANE_TO_GP:
6455
4.35k
      {
6456
4.35k
  unsigned long rda = arm_decode_field (given, 12, 15);
6457
4.35k
  if (rda == 0xd)
6458
239
    {
6459
239
      *unpredictable_code = UNPRED_R13;
6460
239
      return true;
6461
239
    }
6462
4.11k
  else if (rda == 0xf)
6463
894
    {
6464
894
      *unpredictable_code = UNPRED_R15;
6465
894
      return true;
6466
894
    }
6467
6468
3.21k
  return false;
6469
4.35k
      }
6470
6471
983
    case MVE_VMULL_INT:
6472
983
      {
6473
983
  unsigned long Qd;
6474
983
  unsigned long Qm;
6475
983
  unsigned long Qn;
6476
6477
983
  if (arm_decode_field (given, 20, 21) == 2)
6478
712
    {
6479
712
      Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6480
712
      Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6481
712
      Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6482
6483
712
      if ((Qd == Qn) || (Qd == Qm))
6484
471
        {
6485
471
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6486
471
    return true;
6487
471
        }
6488
241
      else
6489
241
        return false;
6490
712
    }
6491
271
  else
6492
271
    return false;
6493
983
      }
6494
6495
924
    case MVE_VCMUL_FP:
6496
1.72k
    case MVE_VQDMULL_T1:
6497
1.72k
      {
6498
1.72k
  unsigned long Qd;
6499
1.72k
  unsigned long Qm;
6500
1.72k
  unsigned long Qn;
6501
6502
1.72k
  if (arm_decode_field (given, 28, 28) == 1)
6503
1.16k
    {
6504
1.16k
      Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6505
1.16k
      Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6506
1.16k
      Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6507
6508
1.16k
      if ((Qd == Qn) || (Qd == Qm))
6509
534
        {
6510
534
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6511
534
    return true;
6512
534
        }
6513
629
      else
6514
629
        return false;
6515
1.16k
    }
6516
566
  else
6517
566
    return false;
6518
1.72k
      }
6519
6520
2.04k
    case MVE_VQDMULL_T2:
6521
2.04k
      {
6522
2.04k
  unsigned long gpr = arm_decode_field (given, 0, 3);
6523
2.04k
  if (gpr == 0xd)
6524
344
    {
6525
344
      *unpredictable_code = UNPRED_R13;
6526
344
      return true;
6527
344
    }
6528
1.70k
  else if (gpr == 0xf)
6529
330
    {
6530
330
      *unpredictable_code = UNPRED_R15;
6531
330
      return true;
6532
330
    }
6533
6534
1.37k
  if (arm_decode_field (given, 28, 28) == 1)
6535
569
    {
6536
569
      unsigned long Qd
6537
569
        = arm_decode_field_multiple (given, 13, 15, 22, 22);
6538
569
      unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6539
6540
569
      if (Qd == Qn)
6541
292
        {
6542
292
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6543
292
    return true;
6544
292
        }
6545
277
      else
6546
277
        return false;
6547
569
    }
6548
6549
806
  return false;
6550
1.37k
      }
6551
6552
569
    case MVE_VMLSLDAV:
6553
1.10k
    case MVE_VRMLSLDAVH:
6554
2.22k
    case MVE_VMLALDAV:
6555
2.50k
    case MVE_VADDLV:
6556
2.50k
      if (arm_decode_field (given, 20, 22) == 6)
6557
1.34k
  {
6558
1.34k
    *unpredictable_code = UNPRED_R13;
6559
1.34k
    return true;
6560
1.34k
  }
6561
1.16k
      else
6562
1.16k
  return false;
6563
6564
718
    case MVE_VDWDUP:
6565
1.95k
    case MVE_VIWDUP:
6566
1.95k
      if (arm_decode_field (given, 1, 3) == 6)
6567
1.02k
  {
6568
1.02k
    *unpredictable_code = UNPRED_R13;
6569
1.02k
    return true;
6570
1.02k
  }
6571
930
      else
6572
930
  return false;
6573
6574
961
    case MVE_VCADD_VEC:
6575
1.91k
    case MVE_VHCADD:
6576
1.91k
      {
6577
1.91k
  unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6578
1.91k
  unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6579
1.91k
  if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6580
183
    {
6581
183
      *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6582
183
      return true;
6583
183
    }
6584
1.72k
  else
6585
1.72k
    return false;
6586
1.91k
      }
6587
6588
769
    case MVE_VCADD_FP:
6589
769
      {
6590
769
  unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6591
769
  unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6592
769
  if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6593
316
    {
6594
316
      *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6595
316
      return true;
6596
316
    }
6597
453
  else
6598
453
    return false;
6599
769
      }
6600
6601
1.54k
    case MVE_VCMLA_FP:
6602
1.54k
      {
6603
1.54k
  unsigned long Qda;
6604
1.54k
  unsigned long Qm;
6605
1.54k
  unsigned long Qn;
6606
6607
1.54k
  if (arm_decode_field (given, 20, 20) == 1)
6608
1.05k
    {
6609
1.05k
      Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6610
1.05k
      Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6611
1.05k
      Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6612
6613
1.05k
      if ((Qda == Qn) || (Qda == Qm))
6614
729
        {
6615
729
    *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6616
729
    return true;
6617
729
        }
6618
328
      else
6619
328
        return false;
6620
1.05k
    }
6621
485
  else
6622
485
    return false;
6623
6624
1.54k
      }
6625
6626
445
    case MVE_VCTP:
6627
445
      if (arm_decode_field (given, 16, 19) == 0xd)
6628
267
  {
6629
267
    *unpredictable_code = UNPRED_R13;
6630
267
    return true;
6631
267
  }
6632
178
      else
6633
178
  return false;
6634
6635
568
    case MVE_VREV64:
6636
568
      {
6637
568
  unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6638
568
  unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6639
6640
568
  if (qd == qm)
6641
216
    {
6642
216
      *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6643
216
      return true;
6644
216
    }
6645
352
  else
6646
352
    return false;
6647
568
      }
6648
6649
320
    case MVE_LSLL:
6650
932
    case MVE_LSLLI:
6651
1.76k
    case MVE_LSRL:
6652
2.26k
    case MVE_ASRL:
6653
2.94k
    case MVE_ASRLI:
6654
3.32k
    case MVE_UQSHLL:
6655
3.86k
    case MVE_UQRSHLL:
6656
4.30k
    case MVE_URSHRL:
6657
4.56k
    case MVE_SRSHRL:
6658
5.06k
    case MVE_SQSHLL:
6659
5.39k
    case MVE_SQRSHRL:
6660
5.39k
      {
6661
5.39k
  unsigned long gpr = arm_decode_field (given, 9, 11);
6662
5.39k
  gpr = ((gpr << 1) | 1);
6663
5.39k
  if (gpr == 0xd)
6664
2.08k
    {
6665
2.08k
      *unpredictable_code = UNPRED_R13;
6666
2.08k
      return true;
6667
2.08k
    }
6668
3.30k
  else if (gpr == 0xf)
6669
0
    {
6670
0
      *unpredictable_code = UNPRED_R15;
6671
0
      return true;
6672
0
    }
6673
6674
3.30k
  return false;
6675
5.39k
      }
6676
6677
72.6k
    default:
6678
72.6k
      return false;
6679
139k
    }
6680
139k
}
6681
6682
static void
6683
print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6684
1.57k
{
6685
1.57k
  unsigned long op1 = arm_decode_field (given, 21, 22);
6686
1.57k
  unsigned long op2 = arm_decode_field (given, 5, 6);
6687
1.57k
  unsigned long h = arm_decode_field (given, 16, 16);
6688
1.57k
  unsigned long index_operand, esize, targetBeat, idx;
6689
1.57k
  void *stream = info->stream;
6690
1.57k
  fprintf_styled_ftype func = info->fprintf_styled_func;
6691
6692
1.57k
  if ((op1 & 0x2) == 0x2)
6693
0
    {
6694
0
      index_operand = op2;
6695
0
      esize = 8;
6696
0
    }
6697
1.57k
  else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6698
0
    {
6699
0
      index_operand = op2  >> 1;
6700
0
      esize = 16;
6701
0
    }
6702
1.57k
  else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6703
0
    {
6704
0
      index_operand = 0;
6705
0
      esize = 32;
6706
0
    }
6707
1.57k
  else
6708
1.57k
    {
6709
1.57k
      func (stream, dis_style_text, "<undefined index>");
6710
1.57k
      return;
6711
1.57k
    }
6712
6713
0
  targetBeat =  (op1 & 0x1) | (h << 1);
6714
0
  idx = index_operand + targetBeat * (32/esize);
6715
6716
0
  func (stream, dis_style_immediate, "%lu", idx);
6717
0
}
6718
6719
/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6720
   in length and integer of floating-point type.  */
6721
static void
6722
print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6723
     unsigned int ibit_loc, const struct mopcode32 *insn)
6724
8.93k
{
6725
8.93k
  int bits = 0;
6726
8.93k
  int cmode = (given >> 8) & 0xf;
6727
8.93k
  int op = (given >> 5) & 0x1;
6728
8.93k
  unsigned long value = 0, hival = 0;
6729
8.93k
  unsigned shift;
6730
8.93k
  int size = 0;
6731
8.93k
  int isfloat = 0;
6732
8.93k
  void *stream = info->stream;
6733
8.93k
  fprintf_styled_ftype func = info->fprintf_styled_func;
6734
6735
  /* On Neon the 'i' bit is at bit 24, on mve it is
6736
     at bit 28.  */
6737
8.93k
  bits |= ((given >> ibit_loc) & 1) << 7;
6738
8.93k
  bits |= ((given >> 16) & 7) << 4;
6739
8.93k
  bits |= ((given >> 0) & 15) << 0;
6740
6741
8.93k
  if (cmode < 8)
6742
4.41k
    {
6743
4.41k
      shift = (cmode >> 1) & 3;
6744
4.41k
      value = (unsigned long) bits << (8 * shift);
6745
4.41k
      size = 32;
6746
4.41k
    }
6747
4.52k
  else if (cmode < 12)
6748
1.97k
    {
6749
1.97k
      shift = (cmode >> 1) & 1;
6750
1.97k
      value = (unsigned long) bits << (8 * shift);
6751
1.97k
      size = 16;
6752
1.97k
    }
6753
2.55k
  else if (cmode < 14)
6754
1.31k
    {
6755
1.31k
      shift = (cmode & 1) + 1;
6756
1.31k
      value = (unsigned long) bits << (8 * shift);
6757
1.31k
      value |= (1ul << (8 * shift)) - 1;
6758
1.31k
      size = 32;
6759
1.31k
    }
6760
1.23k
  else if (cmode == 14)
6761
928
    {
6762
928
      if (op)
6763
688
  {
6764
    /* Bit replication into bytes.  */
6765
688
    int ix;
6766
688
    unsigned long mask;
6767
6768
688
    value = 0;
6769
688
    hival = 0;
6770
6.19k
    for (ix = 7; ix >= 0; ix--)
6771
5.50k
      {
6772
5.50k
        mask = ((bits >> ix) & 1) ? 0xff : 0;
6773
5.50k
        if (ix <= 3)
6774
2.75k
    value = (value << 8) | mask;
6775
2.75k
        else
6776
2.75k
    hival = (hival << 8) | mask;
6777
5.50k
      }
6778
688
    size = 64;
6779
688
  }
6780
240
      else
6781
240
  {
6782
    /* Byte replication.  */
6783
240
    value = (unsigned long) bits;
6784
240
    size = 8;
6785
240
  }
6786
928
    }
6787
309
  else if (!op)
6788
309
    {
6789
      /* Floating point encoding.  */
6790
309
      int tmp;
6791
6792
309
      value = (unsigned long)  (bits & 0x7f) << 19;
6793
309
      value |= (unsigned long) (bits & 0x80) << 24;
6794
309
      tmp = bits & 0x40 ? 0x3c : 0x40;
6795
309
      value |= (unsigned long) tmp << 24;
6796
309
      size = 32;
6797
309
      isfloat = 1;
6798
309
    }
6799
0
  else
6800
0
    {
6801
0
      func (stream, dis_style_text, "<illegal constant %.8x:%x:%x>",
6802
0
      bits, cmode, op);
6803
0
      size = 32;
6804
0
      return;
6805
0
    }
6806
6807
  /* printU determines whether the immediate value should be printed as
6808
     unsigned.  */
6809
8.93k
  unsigned printU = 0;
6810
8.93k
  switch (insn->mve_op)
6811
8.93k
    {
6812
0
    default:
6813
0
      break;
6814
    /* We want this for instructions that don't have a 'signed' type.  */
6815
2.28k
    case MVE_VBIC_IMM:
6816
2.56k
    case MVE_VORR_IMM:
6817
5.39k
    case MVE_VMVN_IMM:
6818
8.93k
    case MVE_VMOV_IMM_TO_VEC:
6819
8.93k
      printU = 1;
6820
8.93k
      break;
6821
8.93k
    }
6822
8.93k
  switch (size)
6823
8.93k
    {
6824
240
    case 8:
6825
240
      func (stream, dis_style_immediate, "#%ld", value);
6826
240
      func (stream, dis_style_comment_start, "\t@ 0x%.2lx", value);
6827
240
      break;
6828
6829
1.97k
    case 16:
6830
1.97k
      func (stream, dis_style_immediate, printU ? "#%lu" : "#%ld", value);
6831
1.97k
      func (stream, dis_style_comment_start, "\t@ 0x%.4lx", value);
6832
1.97k
      break;
6833
6834
6.03k
    case 32:
6835
6.03k
      if (isfloat)
6836
309
  {
6837
309
    unsigned char valbytes[4];
6838
309
    double fvalue;
6839
6840
    /* Do this a byte at a time so we don't have to
6841
       worry about the host's endianness.  */
6842
309
    valbytes[0] = value & 0xff;
6843
309
    valbytes[1] = (value >> 8) & 0xff;
6844
309
    valbytes[2] = (value >> 16) & 0xff;
6845
309
    valbytes[3] = (value >> 24) & 0xff;
6846
6847
309
    floatformat_to_double
6848
309
      (& floatformat_ieee_single_little, valbytes,
6849
309
       & fvalue);
6850
6851
309
    func (stream, dis_style_immediate, "#%.7g", fvalue);
6852
309
    func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
6853
309
  }
6854
5.72k
      else
6855
5.72k
  {
6856
5.72k
    func (stream, dis_style_immediate,
6857
5.72k
    printU ? "#%lu" : "#%ld",
6858
5.72k
    (long) (((value & 0x80000000L) != 0)
6859
1.11k
      && !printU
6860
5.72k
      ? value | ~0xffffffffL : value));
6861
5.72k
    func (stream, dis_style_comment_start, "\t@ 0x%.8lx", value);
6862
5.72k
  }
6863
6.03k
      break;
6864
6865
688
    case 64:
6866
688
      func (stream, dis_style_immediate, "#0x%.8lx%.8lx", hival, value);
6867
688
      break;
6868
6869
0
    default:
6870
0
      abort ();
6871
8.93k
    }
6872
6873
8.93k
}
6874
6875
static void
6876
print_mve_undefined (struct disassemble_info *info,
6877
         enum mve_undefined undefined_code)
6878
16.8k
{
6879
16.8k
  void *stream = info->stream;
6880
16.8k
  fprintf_styled_ftype func = info->fprintf_styled_func;
6881
  /* Initialize REASON to avoid compiler warning about uninitialized
6882
     usage, though such usage should be impossible.  */
6883
16.8k
  const char *reason = "??";
6884
6885
16.8k
  switch (undefined_code)
6886
16.8k
    {
6887
640
    case UNDEF_SIZE:
6888
640
      reason = "illegal size";
6889
640
      break;
6890
6891
2.86k
    case UNDEF_SIZE_0:
6892
2.86k
      reason = "size equals zero";
6893
2.86k
      break;
6894
6895
609
    case UNDEF_SIZE_2:
6896
609
      reason = "size equals two";
6897
609
      break;
6898
6899
6.07k
    case UNDEF_SIZE_3:
6900
6.07k
      reason = "size equals three";
6901
6.07k
      break;
6902
6903
493
    case UNDEF_SIZE_LE_1:
6904
493
      reason = "size <= 1";
6905
493
      break;
6906
6907
294
    case UNDEF_SIZE_NOT_0:
6908
294
      reason = "size not equal to 0";
6909
294
      break;
6910
6911
742
    case UNDEF_SIZE_NOT_2:
6912
742
      reason = "size not equal to 2";
6913
742
      break;
6914
6915
0
    case UNDEF_SIZE_NOT_3:
6916
0
      reason = "size not equal to 3";
6917
0
      break;
6918
6919
226
    case UNDEF_NOT_UNS_SIZE_0:
6920
226
      reason = "not unsigned and size = zero";
6921
226
      break;
6922
6923
207
    case UNDEF_NOT_UNS_SIZE_1:
6924
207
      reason = "not unsigned and size = one";
6925
207
      break;
6926
6927
255
    case UNDEF_NOT_UNSIGNED:
6928
255
      reason = "not unsigned";
6929
255
      break;
6930
6931
364
    case UNDEF_VCVT_IMM6:
6932
364
      reason = "invalid imm6";
6933
364
      break;
6934
6935
1.13k
    case UNDEF_VCVT_FSI_IMM6:
6936
1.13k
      reason = "fsi = 0 and invalid imm6";
6937
1.13k
      break;
6938
6939
1.57k
    case UNDEF_BAD_OP1_OP2:
6940
1.57k
      reason = "bad size with op2 = 2 and op1 = 0 or 1";
6941
1.57k
      break;
6942
6943
0
    case UNDEF_BAD_U_OP1_OP2:
6944
0
      reason = "unsigned with op2 = 0 and op1 = 0 or 1";
6945
0
      break;
6946
6947
0
    case UNDEF_OP_0_BAD_CMODE:
6948
0
      reason = "op field equal 0 and bad cmode";
6949
0
      break;
6950
6951
756
    case UNDEF_XCHG_UNS:
6952
756
      reason = "exchange and unsigned together";
6953
756
      break;
6954
6955
580
    case UNDEF_NONE:
6956
580
      reason = "";
6957
580
      break;
6958
16.8k
    }
6959
6960
16.8k
  func (stream, dis_style_text, "\t\tundefined instruction: %s", reason);
6961
16.8k
}
6962
6963
static void
6964
print_mve_unpredictable (struct disassemble_info *info,
6965
       enum mve_unpredictable unpredict_code)
6966
28.5k
{
6967
28.5k
  void *stream = info->stream;
6968
28.5k
  fprintf_styled_ftype func = info->fprintf_styled_func;
6969
  /* Initialize REASON to avoid compiler warning about uninitialized
6970
     usage, though such usage should be impossible.  */
6971
28.5k
  const char *reason = "??";
6972
6973
28.5k
  switch (unpredict_code)
6974
28.5k
    {
6975
1.74k
    case UNPRED_IT_BLOCK:
6976
1.74k
      reason = "mve instruction in it block";
6977
1.74k
      break;
6978
6979
501
    case UNPRED_FCA_0_FCB_1:
6980
501
      reason = "condition bits, fca = 0 and fcb = 1";
6981
501
      break;
6982
6983
7.72k
    case UNPRED_R13:
6984
7.72k
      reason = "use of r13 (sp)";
6985
7.72k
      break;
6986
6987
8.74k
    case UNPRED_R15:
6988
8.74k
      reason = "use of r15 (pc)";
6989
8.74k
      break;
6990
6991
250
    case UNPRED_Q_GT_4:
6992
250
      reason = "start register block > r4";
6993
250
      break;
6994
6995
283
    case UNPRED_Q_GT_6:
6996
283
      reason = "start register block > r6";
6997
283
      break;
6998
6999
1.30k
    case UNPRED_R13_AND_WB:
7000
1.30k
      reason = "use of r13 and write back";
7001
1.30k
      break;
7002
7003
1.26k
    case UNPRED_Q_REGS_EQUAL:
7004
1.26k
      reason = "same vector register used for destination and other operand";
7005
1.26k
      break;
7006
7007
1.22k
    case UNPRED_OS:
7008
1.22k
      reason = "use of offset scaled";
7009
1.22k
      break;
7010
7011
212
    case UNPRED_GP_REGS_EQUAL:
7012
212
      reason = "same general-purpose register used for both operands";
7013
212
      break;
7014
7015
1.87k
    case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7016
1.87k
      reason = "use of identical q registers and size = 1";
7017
1.87k
      break;
7018
7019
654
    case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7020
654
      reason = "use of identical q registers and size = 1";
7021
654
      break;
7022
7023
2.72k
    case UNPRED_NONE:
7024
2.72k
      reason = "";
7025
2.72k
      break;
7026
28.5k
    }
7027
7028
28.5k
  func (stream, dis_style_comment_start, "%s: %s",
7029
28.5k
  UNPREDICTABLE_INSTRUCTION, reason);
7030
28.5k
}
7031
7032
/* Print register block operand for mve vld2/vld4/vst2/vld4.  */
7033
7034
static void
7035
print_mve_register_blocks (struct disassemble_info *info,
7036
         unsigned long given,
7037
         enum mve_instructions matched_insn)
7038
2.69k
{
7039
2.69k
  void *stream = info->stream;
7040
2.69k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7041
7042
2.69k
  unsigned long q_reg_start = arm_decode_field_multiple (given,
7043
2.69k
               13, 15,
7044
2.69k
               22, 22);
7045
2.69k
  switch (matched_insn)
7046
2.69k
    {
7047
509
    case MVE_VLD2:
7048
1.63k
    case MVE_VST2:
7049
1.63k
      if (q_reg_start <= 6)
7050
340
  {
7051
340
    func (stream, dis_style_text, "{");
7052
340
    func (stream, dis_style_register, "q%ld", q_reg_start);
7053
340
    func (stream, dis_style_text, ", ");
7054
340
    func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7055
340
    func (stream, dis_style_text, "}");
7056
340
  }
7057
1.29k
      else
7058
1.29k
  func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
7059
1.63k
      break;
7060
7061
269
    case MVE_VLD4:
7062
1.05k
    case MVE_VST4:
7063
1.05k
      if (q_reg_start <= 4)
7064
484
  {
7065
484
    func (stream, dis_style_text, "{");
7066
484
    func (stream, dis_style_register, "q%ld", q_reg_start);
7067
484
    func (stream, dis_style_text, ", ");
7068
484
    func (stream, dis_style_register, "q%ld", q_reg_start + 1);
7069
484
    func (stream, dis_style_text, ", ");
7070
484
    func (stream, dis_style_register, "q%ld", q_reg_start + 2);
7071
484
    func (stream, dis_style_text, ", ");
7072
484
    func (stream, dis_style_register, "q%ld", q_reg_start + 3);
7073
484
    func (stream, dis_style_text, "}");
7074
484
  }
7075
570
      else
7076
570
  func (stream, dis_style_text, "<illegal reg q%ld>", q_reg_start);
7077
1.05k
      break;
7078
7079
0
    default:
7080
0
      break;
7081
2.69k
    }
7082
2.69k
}
7083
7084
static void
7085
print_mve_rounding_mode (struct disassemble_info *info,
7086
       unsigned long given,
7087
       enum mve_instructions matched_insn)
7088
6.00k
{
7089
6.00k
  void *stream = info->stream;
7090
6.00k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7091
7092
6.00k
  switch (matched_insn)
7093
6.00k
    {
7094
3.64k
    case MVE_VCVT_FROM_FP_TO_INT:
7095
3.64k
      {
7096
3.64k
  switch (arm_decode_field (given, 8, 9))
7097
3.64k
    {
7098
1.21k
    case 0:
7099
1.21k
      func (stream, dis_style_mnemonic, "a");
7100
1.21k
      break;
7101
7102
1.00k
    case 1:
7103
1.00k
      func (stream, dis_style_mnemonic, "n");
7104
1.00k
      break;
7105
7106
1.01k
    case 2:
7107
1.01k
      func (stream, dis_style_mnemonic, "p");
7108
1.01k
      break;
7109
7110
404
    case 3:
7111
404
      func (stream, dis_style_mnemonic, "m");
7112
404
      break;
7113
7114
0
    default:
7115
0
      break;
7116
3.64k
    }
7117
3.64k
      }
7118
3.64k
      break;
7119
7120
3.64k
    case MVE_VRINT_FP:
7121
2.36k
      {
7122
2.36k
  switch (arm_decode_field (given, 7, 9))
7123
2.36k
    {
7124
250
    case 0:
7125
250
      func (stream, dis_style_mnemonic, "n");
7126
250
      break;
7127
7128
762
    case 1:
7129
762
      func (stream, dis_style_mnemonic, "x");
7130
762
      break;
7131
7132
213
    case 2:
7133
213
      func (stream, dis_style_mnemonic, "a");
7134
213
      break;
7135
7136
341
    case 3:
7137
341
      func (stream, dis_style_mnemonic, "z");
7138
341
      break;
7139
7140
283
    case 5:
7141
283
      func (stream, dis_style_mnemonic, "m");
7142
283
      break;
7143
7144
269
    case 7:
7145
269
      func (stream, dis_style_mnemonic, "p");
7146
7147
322
    case 4:
7148
516
    case 6:
7149
516
    default:
7150
516
      break;
7151
2.36k
    }
7152
2.36k
      }
7153
2.36k
      break;
7154
7155
2.36k
    default:
7156
0
      break;
7157
6.00k
    }
7158
6.00k
}
7159
7160
static void
7161
print_mve_vcvt_size (struct disassemble_info *info,
7162
         unsigned long given,
7163
         enum mve_instructions matched_insn)
7164
11.9k
{
7165
11.9k
  unsigned long mode = 0;
7166
11.9k
  void *stream = info->stream;
7167
11.9k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7168
7169
11.9k
  switch (matched_insn)
7170
11.9k
    {
7171
4.59k
    case MVE_VCVT_FP_FIX_VEC:
7172
4.59k
      {
7173
4.59k
  mode = (((given & 0x200) >> 7)
7174
4.59k
    | ((given & 0x10000000) >> 27)
7175
4.59k
    | ((given & 0x100) >> 8));
7176
7177
4.59k
  switch (mode)
7178
4.59k
    {
7179
574
    case 0:
7180
574
      func (stream, dis_style_mnemonic, "f16.s16");
7181
574
      break;
7182
7183
257
    case 1:
7184
257
      func (stream, dis_style_mnemonic, "s16.f16");
7185
257
      break;
7186
7187
266
    case 2:
7188
266
      func (stream, dis_style_mnemonic, "f16.u16");
7189
266
      break;
7190
7191
405
    case 3:
7192
405
      func (stream, dis_style_mnemonic, "u16.f16");
7193
405
      break;
7194
7195
788
    case 4:
7196
788
      func (stream, dis_style_mnemonic, "f32.s32");
7197
788
      break;
7198
7199
346
    case 5:
7200
346
      func (stream, dis_style_mnemonic, "s32.f32");
7201
346
      break;
7202
7203
278
    case 6:
7204
278
      func (stream, dis_style_mnemonic, "f32.u32");
7205
278
      break;
7206
7207
1.68k
    case 7:
7208
1.68k
      func (stream, dis_style_mnemonic, "u32.f32");
7209
1.68k
      break;
7210
7211
0
    default:
7212
0
      break;
7213
4.59k
    }
7214
4.59k
  break;
7215
4.59k
      }
7216
4.59k
    case MVE_VCVT_BETWEEN_FP_INT:
7217
2.79k
      {
7218
2.79k
  unsigned long size = arm_decode_field (given, 18, 19);
7219
2.79k
  unsigned long op = arm_decode_field (given, 7, 8);
7220
7221
2.79k
  if (size == 1)
7222
1.16k
    {
7223
1.16k
      switch (op)
7224
1.16k
        {
7225
356
        case 0:
7226
356
    func (stream, dis_style_mnemonic, "f16.s16");
7227
356
    break;
7228
7229
265
        case 1:
7230
265
    func (stream, dis_style_mnemonic, "f16.u16");
7231
265
    break;
7232
7233
233
        case 2:
7234
233
    func (stream, dis_style_mnemonic, "s16.f16");
7235
233
    break;
7236
7237
312
        case 3:
7238
312
    func (stream, dis_style_mnemonic, "u16.f16");
7239
312
    break;
7240
7241
0
        default:
7242
0
    break;
7243
1.16k
        }
7244
1.16k
    }
7245
1.63k
  else if (size == 2)
7246
1.25k
    {
7247
1.25k
      switch (op)
7248
1.25k
        {
7249
243
        case 0:
7250
243
    func (stream, dis_style_mnemonic, "f32.s32");
7251
243
    break;
7252
7253
259
        case 1:
7254
259
    func (stream, dis_style_mnemonic, "f32.u32");
7255
259
    break;
7256
7257
247
        case 2:
7258
247
    func (stream, dis_style_mnemonic, "s32.f32");
7259
247
    break;
7260
7261
503
        case 3:
7262
503
    func (stream, dis_style_mnemonic, "u32.f32");
7263
503
    break;
7264
1.25k
        }
7265
1.25k
    }
7266
2.79k
      }
7267
2.79k
      break;
7268
7269
2.79k
    case MVE_VCVT_FP_HALF_FP:
7270
872
      {
7271
872
  unsigned long op = arm_decode_field (given, 28, 28);
7272
872
  if (op == 0)
7273
487
    func (stream, dis_style_mnemonic, "f16.f32");
7274
385
  else if (op == 1)
7275
385
    func (stream, dis_style_mnemonic, "f32.f16");
7276
872
      }
7277
872
      break;
7278
7279
3.64k
    case MVE_VCVT_FROM_FP_TO_INT:
7280
3.64k
      {
7281
3.64k
  unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7282
7283
3.64k
  switch (size)
7284
3.64k
    {
7285
460
    case 2:
7286
460
      func (stream, dis_style_mnemonic, "s16.f16");
7287
460
      break;
7288
7289
418
    case 3:
7290
418
      func (stream, dis_style_mnemonic, "u16.f16");
7291
418
      break;
7292
7293
690
    case 4:
7294
690
      func (stream, dis_style_mnemonic, "s32.f32");
7295
690
      break;
7296
7297
223
    case 5:
7298
223
      func (stream, dis_style_mnemonic, "u32.f32");
7299
223
      break;
7300
7301
1.85k
    default:
7302
1.85k
      break;
7303
3.64k
    }
7304
3.64k
      }
7305
3.64k
      break;
7306
7307
3.64k
    default:
7308
0
      break;
7309
11.9k
    }
7310
11.9k
}
7311
7312
static void
7313
print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7314
      unsigned long rot_width)
7315
5.18k
{
7316
5.18k
  void *stream = info->stream;
7317
5.18k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7318
7319
5.18k
  if (rot_width == 1)
7320
2.71k
    {
7321
2.71k
      switch (rot)
7322
2.71k
  {
7323
1.70k
  case 0:
7324
1.70k
    func (stream, dis_style_immediate, "90");
7325
1.70k
    break;
7326
1.01k
  case 1:
7327
1.01k
    func (stream, dis_style_immediate, "270");
7328
1.01k
    break;
7329
0
  default:
7330
0
    break;
7331
2.71k
  }
7332
2.71k
    }
7333
2.46k
  else if (rot_width == 2)
7334
2.46k
    {
7335
2.46k
      switch (rot)
7336
2.46k
  {
7337
285
  case 0:
7338
285
    func (stream, dis_style_immediate, "0");
7339
285
    break;
7340
1.18k
  case 1:
7341
1.18k
    func (stream, dis_style_immediate, "90");
7342
1.18k
    break;
7343
456
  case 2:
7344
456
    func (stream, dis_style_immediate, "180");
7345
456
    break;
7346
542
  case 3:
7347
542
    func (stream, dis_style_immediate, "270");
7348
542
    break;
7349
0
  default:
7350
0
    break;
7351
2.46k
  }
7352
2.46k
    }
7353
5.18k
}
7354
7355
static void
7356
print_instruction_predicate (struct disassemble_info *info)
7357
112k
{
7358
112k
  void *stream = info->stream;
7359
112k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7360
7361
112k
  if (vpt_block_state.next_pred_state == PRED_THEN)
7362
3.28k
    func (stream, dis_style_mnemonic, "t");
7363
108k
  else if (vpt_block_state.next_pred_state == PRED_ELSE)
7364
1.38k
    func (stream, dis_style_mnemonic, "e");
7365
112k
}
7366
7367
static void
7368
print_mve_size (struct disassemble_info *info,
7369
    unsigned long size,
7370
    enum mve_instructions matched_insn)
7371
95.5k
{
7372
95.5k
  void *stream = info->stream;
7373
95.5k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7374
7375
95.5k
  switch (matched_insn)
7376
95.5k
    {
7377
424
    case MVE_VABAV:
7378
863
    case MVE_VABD_VEC:
7379
1.07k
    case MVE_VABS_FP:
7380
1.65k
    case MVE_VABS_VEC:
7381
1.92k
    case MVE_VADD_VEC_T1:
7382
2.41k
    case MVE_VADD_VEC_T2:
7383
2.61k
    case MVE_VADDV:
7384
3.21k
    case MVE_VBRSR:
7385
4.20k
    case MVE_VCADD_VEC:
7386
4.40k
    case MVE_VCLS:
7387
4.62k
    case MVE_VCLZ:
7388
4.89k
    case MVE_VCMP_VEC_T1:
7389
5.28k
    case MVE_VCMP_VEC_T2:
7390
5.55k
    case MVE_VCMP_VEC_T3:
7391
5.99k
    case MVE_VCMP_VEC_T4:
7392
6.23k
    case MVE_VCMP_VEC_T5:
7393
6.57k
    case MVE_VCMP_VEC_T6:
7394
7.02k
    case MVE_VCTP:
7395
8.27k
    case MVE_VDDUP:
7396
8.98k
    case MVE_VDWDUP:
7397
9.76k
    case MVE_VHADD_T1:
7398
10.7k
    case MVE_VHADD_T2:
7399
11.6k
    case MVE_VHCADD:
7400
12.0k
    case MVE_VHSUB_T1:
7401
12.3k
    case MVE_VHSUB_T2:
7402
12.8k
    case MVE_VIDUP:
7403
14.0k
    case MVE_VIWDUP:
7404
14.5k
    case MVE_VLD2:
7405
14.8k
    case MVE_VLD4:
7406
15.9k
    case MVE_VLDRB_GATHER_T1:
7407
17.4k
    case MVE_VLDRH_GATHER_T2:
7408
17.4k
    case MVE_VLDRW_GATHER_T3:
7409
17.4k
    case MVE_VLDRD_GATHER_T4:
7410
18.2k
    case MVE_VLDRB_T1:
7411
18.7k
    case MVE_VLDRH_T2:
7412
18.9k
    case MVE_VMAX:
7413
19.3k
    case MVE_VMAXA:
7414
19.8k
    case MVE_VMAXV:
7415
20.1k
    case MVE_VMAXAV:
7416
20.4k
    case MVE_VMIN:
7417
20.8k
    case MVE_VMINA:
7418
21.0k
    case MVE_VMINV:
7419
21.4k
    case MVE_VMINAV:
7420
21.8k
    case MVE_VMLA:
7421
22.1k
    case MVE_VMLAS:
7422
22.5k
    case MVE_VMUL_VEC_T1:
7423
23.0k
    case MVE_VMUL_VEC_T2:
7424
23.4k
    case MVE_VMULH:
7425
24.3k
    case MVE_VRMULH:
7426
25.3k
    case MVE_VMULL_INT:
7427
25.6k
    case MVE_VNEG_FP:
7428
25.9k
    case MVE_VNEG_VEC:
7429
26.8k
    case MVE_VPT_VEC_T1:
7430
27.9k
    case MVE_VPT_VEC_T2:
7431
29.1k
    case MVE_VPT_VEC_T3:
7432
30.2k
    case MVE_VPT_VEC_T4:
7433
30.8k
    case MVE_VPT_VEC_T5:
7434
32.1k
    case MVE_VPT_VEC_T6:
7435
32.6k
    case MVE_VQABS:
7436
33.5k
    case MVE_VQADD_T1:
7437
34.1k
    case MVE_VQADD_T2:
7438
34.4k
    case MVE_VQDMLADH:
7439
35.0k
    case MVE_VQRDMLADH:
7440
35.7k
    case MVE_VQDMLAH:
7441
36.0k
    case MVE_VQRDMLAH:
7442
36.2k
    case MVE_VQDMLASH:
7443
36.6k
    case MVE_VQRDMLASH:
7444
36.9k
    case MVE_VQDMLSDH:
7445
37.6k
    case MVE_VQRDMLSDH:
7446
37.9k
    case MVE_VQDMULH_T1:
7447
38.5k
    case MVE_VQRDMULH_T2:
7448
39.0k
    case MVE_VQDMULH_T3:
7449
39.4k
    case MVE_VQRDMULH_T4:
7450
39.6k
    case MVE_VQNEG:
7451
39.9k
    case MVE_VQRSHL_T1:
7452
40.1k
    case MVE_VQRSHL_T2:
7453
40.4k
    case MVE_VQSHL_T1:
7454
40.6k
    case MVE_VQSHL_T4:
7455
40.9k
    case MVE_VQSUB_T1:
7456
41.3k
    case MVE_VQSUB_T2:
7457
42.0k
    case MVE_VREV32:
7458
42.5k
    case MVE_VREV64:
7459
43.6k
    case MVE_VRHADD:
7460
45.9k
    case MVE_VRINT_FP:
7461
46.3k
    case MVE_VRSHL_T1:
7462
46.5k
    case MVE_VRSHL_T2:
7463
46.9k
    case MVE_VSHL_T2:
7464
47.3k
    case MVE_VSHL_T3:
7465
47.6k
    case MVE_VSHLL_T2:
7466
48.7k
    case MVE_VST2:
7467
49.5k
    case MVE_VST4:
7468
51.2k
    case MVE_VSTRB_SCATTER_T1:
7469
52.2k
    case MVE_VSTRH_SCATTER_T2:
7470
53.2k
    case MVE_VSTRW_SCATTER_T3:
7471
53.8k
    case MVE_VSTRB_T1:
7472
54.3k
    case MVE_VSTRH_T2:
7473
54.6k
    case MVE_VSUB_VEC_T1:
7474
54.8k
    case MVE_VSUB_VEC_T2:
7475
54.8k
      if (size <= 3)
7476
54.8k
  func (stream, dis_style_mnemonic, "%s", mve_vec_sizename[size]);
7477
0
      else
7478
0
  func (stream, dis_style_text, "<undef size>");
7479
54.8k
      break;
7480
7481
251
    case MVE_VABD_FP:
7482
596
    case MVE_VADD_FP_T1:
7483
1.02k
    case MVE_VADD_FP_T2:
7484
1.23k
    case MVE_VSUB_FP_T1:
7485
1.56k
    case MVE_VSUB_FP_T2:
7486
2.04k
    case MVE_VCMP_FP_T1:
7487
2.52k
    case MVE_VCMP_FP_T2:
7488
2.76k
    case MVE_VFMA_FP_SCALAR:
7489
3.07k
    case MVE_VFMA_FP:
7490
3.31k
    case MVE_VFMS_FP:
7491
3.73k
    case MVE_VFMAS_FP_SCALAR:
7492
4.28k
    case MVE_VMAXNM_FP:
7493
4.80k
    case MVE_VMAXNMA_FP:
7494
5.00k
    case MVE_VMAXNMV_FP:
7495
5.31k
    case MVE_VMAXNMAV_FP:
7496
5.61k
    case MVE_VMINNM_FP:
7497
5.85k
    case MVE_VMINNMA_FP:
7498
6.10k
    case MVE_VMINNMV_FP:
7499
6.32k
    case MVE_VMINNMAV_FP:
7500
6.59k
    case MVE_VMUL_FP_T1:
7501
6.91k
    case MVE_VMUL_FP_T2:
7502
8.77k
    case MVE_VPT_FP_T1:
7503
10.6k
    case MVE_VPT_FP_T2:
7504
10.6k
      if (size == 0)
7505
6.74k
  func (stream, dis_style_mnemonic, "32");
7506
3.90k
      else if (size == 1)
7507
3.90k
  func (stream, dis_style_mnemonic, "16");
7508
10.6k
      break;
7509
7510
772
    case MVE_VCADD_FP:
7511
2.31k
    case MVE_VCMLA_FP:
7512
3.24k
    case MVE_VCMUL_FP:
7513
3.91k
    case MVE_VMLADAV_T1:
7514
5.06k
    case MVE_VMLALDAV:
7515
5.30k
    case MVE_VMLSDAV_T1:
7516
5.87k
    case MVE_VMLSLDAV:
7517
6.28k
    case MVE_VMOVN:
7518
7.09k
    case MVE_VQDMULL_T1:
7519
9.14k
    case MVE_VQDMULL_T2:
7520
9.58k
    case MVE_VQMOVN:
7521
9.92k
    case MVE_VQMOVUN:
7522
9.92k
      if (size == 0)
7523
4.41k
  func (stream, dis_style_mnemonic, "16");
7524
5.51k
      else if (size == 1)
7525
4.87k
  func (stream, dis_style_mnemonic, "32");
7526
9.92k
      break;
7527
7528
862
    case MVE_VMOVL:
7529
862
      if (size == 1)
7530
247
  func (stream, dis_style_mnemonic, "8");
7531
615
      else if (size == 2)
7532
615
  func (stream, dis_style_mnemonic, "16");
7533
862
      break;
7534
7535
1.01k
    case MVE_VDUP:
7536
1.01k
      switch (size)
7537
1.01k
  {
7538
196
  case 0:
7539
196
    func (stream, dis_style_mnemonic, "32");
7540
196
    break;
7541
226
  case 1:
7542
226
    func (stream, dis_style_mnemonic, "16");
7543
226
    break;
7544
365
  case 2:
7545
365
    func (stream, dis_style_mnemonic, "8");
7546
365
    break;
7547
227
  default:
7548
227
    break;
7549
1.01k
  }
7550
1.01k
      break;
7551
7552
1.01k
    case MVE_VMOV_GP_TO_VEC_LANE:
7553
1.57k
    case MVE_VMOV_VEC_LANE_TO_GP:
7554
1.57k
      switch (size)
7555
1.57k
  {
7556
0
  case 0: case 4:
7557
0
    func (stream, dis_style_mnemonic, "32");
7558
0
    break;
7559
7560
0
  case 1: case 3:
7561
0
  case 5: case 7:
7562
0
    func (stream, dis_style_mnemonic, "16");
7563
0
    break;
7564
7565
0
  case 8: case 9: case 10: case 11:
7566
0
  case 12: case 13: case 14: case 15:
7567
0
    func (stream, dis_style_mnemonic, "8");
7568
0
    break;
7569
7570
1.57k
  default:
7571
1.57k
    break;
7572
1.57k
  }
7573
1.57k
      break;
7574
7575
3.54k
    case MVE_VMOV_IMM_TO_VEC:
7576
3.54k
      switch (size)
7577
3.54k
  {
7578
849
  case 0: case 4: case 8:
7579
1.72k
  case 12: case 24: case 26:
7580
1.72k
    func (stream, dis_style_mnemonic, "i32");
7581
1.72k
    break;
7582
578
  case 16: case 20:
7583
578
    func (stream, dis_style_mnemonic, "i16");
7584
578
    break;
7585
240
  case 28:
7586
240
    func (stream, dis_style_mnemonic, "i8");
7587
240
    break;
7588
688
  case 29:
7589
688
    func (stream, dis_style_mnemonic, "i64");
7590
688
    break;
7591
309
  case 30:
7592
309
    func (stream, dis_style_mnemonic, "f32");
7593
309
    break;
7594
0
  default:
7595
0
    break;
7596
3.54k
  }
7597
3.54k
      break;
7598
7599
3.54k
    case MVE_VMULL_POLY:
7600
1.16k
      if (size == 0)
7601
717
  func (stream, dis_style_mnemonic, "p8");
7602
448
      else if (size == 1)
7603
448
  func (stream, dis_style_mnemonic, "p16");
7604
1.16k
      break;
7605
7606
2.82k
    case MVE_VMVN_IMM:
7607
2.82k
      switch (size)
7608
2.82k
  {
7609
1.26k
  case 0: case 2: case 4:
7610
2.16k
  case 6: case 12: case 13:
7611
2.16k
    func (stream, dis_style_mnemonic, "32");
7612
2.16k
    break;
7613
7614
657
  case 8: case 10:
7615
657
    func (stream, dis_style_mnemonic, "16");
7616
657
    break;
7617
7618
0
  default:
7619
0
    break;
7620
2.82k
  }
7621
2.82k
      break;
7622
7623
2.82k
    case MVE_VBIC_IMM:
7624
2.56k
    case MVE_VORR_IMM:
7625
2.56k
      switch (size)
7626
2.56k
  {
7627
793
  case 1: case 3:
7628
1.83k
  case 5: case 7:
7629
1.83k
    func (stream, dis_style_mnemonic, "32");
7630
1.83k
    break;
7631
7632
735
  case 9: case 11:
7633
735
    func (stream, dis_style_mnemonic, "16");
7634
735
    break;
7635
7636
0
  default:
7637
0
    break;
7638
2.56k
  }
7639
2.56k
      break;
7640
7641
2.56k
    case MVE_VQSHRN:
7642
872
    case MVE_VQSHRUN:
7643
1.24k
    case MVE_VQRSHRN:
7644
1.76k
    case MVE_VQRSHRUN:
7645
2.01k
    case MVE_VRSHRN:
7646
2.38k
    case MVE_VSHRN:
7647
2.38k
      {
7648
2.38k
  switch (size)
7649
2.38k
  {
7650
951
  case 1:
7651
951
    func (stream, dis_style_mnemonic, "16");
7652
951
    break;
7653
7654
881
  case 2: case 3:
7655
881
    func (stream, dis_style_mnemonic, "32");
7656
881
    break;
7657
7658
556
  default:
7659
556
    break;
7660
2.38k
  }
7661
2.38k
      }
7662
2.38k
      break;
7663
7664
2.38k
    case MVE_VQSHL_T2:
7665
1.06k
    case MVE_VQSHLU_T3:
7666
1.62k
    case MVE_VRSHR:
7667
2.02k
    case MVE_VSHL_T1:
7668
3.11k
    case MVE_VSHLL_T1:
7669
3.78k
    case MVE_VSHR:
7670
4.00k
    case MVE_VSLI:
7671
4.25k
    case MVE_VSRI:
7672
4.25k
      {
7673
4.25k
  switch (size)
7674
4.25k
  {
7675
733
  case 1:
7676
733
    func (stream, dis_style_mnemonic, "8");
7677
733
    break;
7678
7679
787
  case 2: case 3:
7680
787
    func (stream, dis_style_mnemonic, "16");
7681
787
    break;
7682
7683
2.26k
  case 4: case 5: case 6: case 7:
7684
2.26k
    func (stream, dis_style_mnemonic, "32");
7685
2.26k
    break;
7686
7687
464
  default:
7688
464
    break;
7689
4.25k
  }
7690
4.25k
      }
7691
4.25k
      break;
7692
7693
4.25k
    default:
7694
0
      break;
7695
95.5k
    }
7696
95.5k
}
7697
7698
/* Return true if INSN is a shift insn with an immediate shift amount
7699
   which needs decoding as per print_mve_shift_n.  */
7700
7701
static bool
7702
mve_shift_insn_p (enum mve_instructions insn)
7703
10.4k
{
7704
10.4k
  switch (insn)
7705
10.4k
    {
7706
429
    case MVE_VQSHL_T2:
7707
1.06k
    case MVE_VQSHLU_T3:
7708
1.45k
    case MVE_VQSHRN:
7709
1.94k
    case MVE_VQSHRUN:
7710
2.31k
    case MVE_VQRSHRN:
7711
2.83k
    case MVE_VQRSHRUN:
7712
3.38k
    case MVE_VRSHR:
7713
3.64k
    case MVE_VRSHRN:
7714
4.04k
    case MVE_VSHL_T1:
7715
5.12k
    case MVE_VSHLL_T1:
7716
5.79k
    case MVE_VSHR:
7717
6.16k
    case MVE_VSHRN:
7718
6.39k
    case MVE_VSLI:
7719
6.64k
    case MVE_VSRI:
7720
6.64k
      return true;
7721
3.84k
    default:
7722
3.84k
      return false;
7723
10.4k
    }
7724
10.4k
}
7725
7726
static void
7727
print_mve_shift_n (struct disassemble_info *info, long given,
7728
       enum mve_instructions matched_insn)
7729
6.64k
{
7730
6.64k
  void *stream = info->stream;
7731
6.64k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7732
7733
6.64k
  int startAt0
7734
6.64k
    = matched_insn == MVE_VQSHL_T2
7735
6.21k
      || matched_insn == MVE_VQSHLU_T3
7736
5.57k
      || matched_insn == MVE_VSHL_T1
7737
5.17k
      || matched_insn == MVE_VSHLL_T1
7738
4.08k
      || matched_insn == MVE_VSLI;
7739
7740
6.64k
  unsigned imm6 = (given & 0x3f0000) >> 16;
7741
7742
6.64k
  if (matched_insn == MVE_VSHLL_T1)
7743
1.08k
    imm6 &= 0x1f;
7744
7745
6.64k
  unsigned shiftAmount = 0;
7746
6.64k
  if ((imm6 & 0x20) != 0)
7747
2.26k
    shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7748
4.37k
  else if ((imm6 & 0x10) != 0)
7749
1.66k
    shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7750
2.70k
  else if ((imm6 & 0x08) != 0)
7751
1.68k
    shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7752
1.02k
  else
7753
1.02k
    print_mve_undefined (info, UNDEF_SIZE_0);
7754
7755
6.64k
  func (stream, dis_style_immediate, "%u", shiftAmount);
7756
6.64k
}
7757
7758
static void
7759
print_vec_condition (struct disassemble_info *info, long given,
7760
         enum mve_instructions matched_insn)
7761
12.7k
{
7762
12.7k
  void *stream = info->stream;
7763
12.7k
  fprintf_styled_ftype func = info->fprintf_styled_func;
7764
12.7k
  long vec_cond = 0;
7765
7766
12.7k
  switch (matched_insn)
7767
12.7k
    {
7768
1.86k
    case MVE_VPT_FP_T1:
7769
2.34k
    case MVE_VCMP_FP_T1:
7770
2.34k
      vec_cond = (((given & 0x1000) >> 10)
7771
2.34k
      | ((given & 1) << 1)
7772
2.34k
      | ((given & 0x0080) >> 7));
7773
2.34k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7774
2.34k
      break;
7775
7776
1.86k
    case MVE_VPT_FP_T2:
7777
2.34k
    case MVE_VCMP_FP_T2:
7778
2.34k
      vec_cond = (((given & 0x1000) >> 10)
7779
2.34k
      | ((given & 0x0020) >> 4)
7780
2.34k
      | ((given & 0x0080) >> 7));
7781
2.34k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7782
2.34k
      break;
7783
7784
901
    case MVE_VPT_VEC_T1:
7785
1.17k
    case MVE_VCMP_VEC_T1:
7786
1.17k
      vec_cond = (given & 0x0080) >> 7;
7787
1.17k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7788
1.17k
      break;
7789
7790
1.08k
    case MVE_VPT_VEC_T2:
7791
1.48k
    case MVE_VCMP_VEC_T2:
7792
1.48k
      vec_cond = 2 | ((given & 0x0080) >> 7);
7793
1.48k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7794
1.48k
      break;
7795
7796
1.14k
    case MVE_VPT_VEC_T3:
7797
1.41k
    case MVE_VCMP_VEC_T3:
7798
1.41k
      vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7799
1.41k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7800
1.41k
      break;
7801
7802
1.18k
    case MVE_VPT_VEC_T4:
7803
1.61k
    case MVE_VCMP_VEC_T4:
7804
1.61k
      vec_cond = (given & 0x0080) >> 7;
7805
1.61k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7806
1.61k
      break;
7807
7808
603
    case MVE_VPT_VEC_T5:
7809
841
    case MVE_VCMP_VEC_T5:
7810
841
      vec_cond = 2 | ((given & 0x0080) >> 7);
7811
841
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7812
841
      break;
7813
7814
1.23k
    case MVE_VPT_VEC_T6:
7815
1.58k
    case MVE_VCMP_VEC_T6:
7816
1.58k
      vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7817
1.58k
      func (stream, dis_style_sub_mnemonic, "%s", vec_condnames[vec_cond]);
7818
1.58k
      break;
7819
7820
0
    case MVE_NONE:
7821
0
    case MVE_VPST:
7822
0
    default:
7823
0
      break;
7824
12.7k
    }
7825
12.7k
}
7826
7827
314k
#define W_BIT 21
7828
30.7k
#define I_BIT 22
7829
528k
#define U_BIT 23
7830
422k
#define P_BIT 24
7831
7832
382k
#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7833
41.7k
#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7834
608k
#define NEGATIVE_BIT_SET  ((given & (1 << U_BIT)) == 0)
7835
543k
#define PRE_BIT_SET   (given & (1 << P_BIT))
7836
7837
/* The assembler string for an instruction can include %{X:...%} patterns,
7838
   where the 'X' is one of the characters understood by this function.
7839
7840
   This function takes the X character, and returns a new style.  This new
7841
   style will be used by the caller to temporarily change the current base
7842
   style.  */
7843
7844
static enum disassembler_style
7845
decode_base_style (const char x)
7846
2.04M
{
7847
2.04M
  switch (x)
7848
2.04M
    {
7849
0
    case 'A': return dis_style_address;
7850
3.24k
    case 'B': return dis_style_sub_mnemonic;
7851
0
    case 'C': return dis_style_comment_start;
7852
0
    case 'D': return dis_style_assembler_directive;
7853
1.49M
    case 'I': return dis_style_immediate;
7854
0
    case 'M': return dis_style_mnemonic;
7855
0
    case 'O': return dis_style_address_offset;
7856
554k
    case 'R': return dis_style_register;
7857
0
    case 'S': return dis_style_symbol;
7858
0
    case 'T': return dis_style_text;
7859
0
    default:
7860
0
      abort ();
7861
2.04M
    }
7862
2.04M
}
7863
7864
/* Print one coprocessor instruction on INFO->STREAM.
7865
   Return TRUE if the instuction matched, FALSE if this is not a
7866
   recognised coprocessor instruction.  */
7867
7868
static bool
7869
print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
7870
        bfd_vma pc,
7871
        struct disassemble_info *info,
7872
        long given,
7873
        bool thumb)
7874
3.85M
{
7875
3.85M
  const struct sopcode32 *insn;
7876
3.85M
  void *stream = info->stream;
7877
3.85M
  fprintf_styled_ftype func = info->fprintf_styled_func;
7878
3.85M
  unsigned long mask;
7879
3.85M
  unsigned long value = 0;
7880
3.85M
  int cond;
7881
3.85M
  int cp_num;
7882
3.85M
  struct arm_private_data *private_data = info->private_data;
7883
3.85M
  arm_feature_set allowed_arches = ARM_ARCH_NONE;
7884
3.85M
  arm_feature_set arm_ext_v8_1m_main =
7885
3.85M
    ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
7886
3.85M
  enum disassembler_style base_style = dis_style_mnemonic;
7887
3.85M
  enum disassembler_style old_base_style = base_style;
7888
7889
3.85M
  allowed_arches = private_data->features;
7890
7891
438M
  for (insn = opcodes; insn->assembler; insn++)
7892
434M
    {
7893
434M
      unsigned long u_reg = 16;
7894
434M
      bool is_unpredictable = false;
7895
434M
      signed long value_in_comment = 0;
7896
434M
      const char *c;
7897
7898
434M
      if (ARM_FEATURE_ZERO (insn->arch))
7899
4.09M
  switch (insn->value)
7900
4.09M
    {
7901
2.04M
    case SENTINEL_IWMMXT_START:
7902
2.04M
      if (info->mach != bfd_mach_arm_XScale
7903
2.02M
    && info->mach != bfd_mach_arm_iWMMXt
7904
2.01M
    && info->mach != bfd_mach_arm_iWMMXt2)
7905
1.99M
        do
7906
151M
    insn++;
7907
151M
        while ((! ARM_FEATURE_ZERO (insn->arch))
7908
149M
         && insn->value != SENTINEL_IWMMXT_END);
7909
2.04M
      continue;
7910
7911
41.1k
    case SENTINEL_IWMMXT_END:
7912
41.1k
      continue;
7913
7914
2.01M
    case SENTINEL_GENERIC_START:
7915
2.01M
      allowed_arches = private_data->features;
7916
2.01M
      continue;
7917
7918
0
    default:
7919
0
      abort ();
7920
4.09M
    }
7921
7922
430M
      mask = insn->mask;
7923
430M
      value = insn->value;
7924
430M
      cp_num = (given >> 8) & 0xf;
7925
7926
430M
      if (thumb)
7927
129M
  {
7928
    /* The high 4 bits are 0xe for Arm conditional instructions, and
7929
       0xe for arm unconditional instructions.  The rest of the
7930
       encoding is the same.  */
7931
129M
    mask |= 0xf0000000;
7932
129M
    value |= 0xe0000000;
7933
129M
    if (ifthen_state)
7934
4.05M
      cond = IFTHEN_COND;
7935
125M
    else
7936
125M
      cond = COND_UNCOND;
7937
129M
  }
7938
301M
      else
7939
301M
  {
7940
    /* Only match unconditional instuctions against unconditional
7941
       patterns.  */
7942
301M
    if ((given & 0xf0000000) == 0xf0000000)
7943
28.4M
      {
7944
28.4M
        mask |= 0xf0000000;
7945
28.4M
        cond = COND_UNCOND;
7946
28.4M
      }
7947
273M
    else
7948
273M
      {
7949
273M
        cond = (given >> 28) & 0xf;
7950
273M
        if (cond == 0xe)
7951
12.0M
    cond = COND_UNCOND;
7952
273M
      }
7953
301M
  }
7954
7955
430M
      if ((insn->isa == T32 && !thumb)
7956
428M
    || (insn->isa == ARM && thumb))
7957
2.83M
  continue;
7958
7959
428M
      if ((given & mask) != value)
7960
427M
  continue;
7961
7962
312k
      if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
7963
60.8k
  continue;
7964
7965
251k
      if (insn->value == 0xfe000010     /* mcr2  */
7966
244k
    || insn->value == 0xfe100010  /* mrc2  */
7967
236k
    || insn->value == 0xfc100000  /* ldc2  */
7968
219k
    || insn->value == 0xfc000000) /* stc2  */
7969
43.2k
  {
7970
43.2k
    if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7971
4.35k
      is_unpredictable = true;
7972
7973
    /* Armv8.1-M Mainline FP & MVE instructions.  */
7974
43.2k
    if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7975
37.1k
        && !ARM_CPU_IS_ANY (allowed_arches)
7976
27.8k
        && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7977
9.72k
      continue;
7978
7979
43.2k
  }
7980
208k
      else if (insn->value == 0x0e000000     /* cdp  */
7981
166k
         || insn->value == 0xfe000000  /* cdp2  */
7982
151k
         || insn->value == 0x0e000010  /* mcr  */
7983
141k
         || insn->value == 0x0e100010  /* mrc  */
7984
130k
         || insn->value == 0x0c100000  /* ldc  */
7985
91.2k
         || insn->value == 0x0c000000) /* stc  */
7986
169k
  {
7987
    /* Floating-point instructions.  */
7988
169k
    if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7989
10.4k
      continue;
7990
7991
    /* Armv8.1-M Mainline FP & MVE instructions.  */
7992
159k
    if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7993
41.9k
        && !ARM_CPU_IS_ANY (allowed_arches)
7994
7.58k
        && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7995
2.41k
      continue;
7996
159k
  }
7997
38.3k
      else if ((insn->value == 0xec100f80      /* vldr (system register) */
7998
36.7k
    || insn->value == 0xec000f80)  /* vstr (system register) */
7999
7.24k
         && arm_decode_field (given, 24, 24) == 0
8000
5.54k
         && arm_decode_field (given, 21, 21) == 0)
8001
  /* If the P and W bits are both 0 then these encodings match the MVE
8002
     VLDR and VSTR instructions, these are in a different table, so we
8003
     don't let it match here.  */
8004
3.73k
  continue;
8005
8006
6.10M
      for (c = insn->assembler; *c; c++)
8007
5.88M
  {
8008
5.88M
    if (*c == '%')
8009
2.62M
      {
8010
2.62M
        const char mod = *++c;
8011
8012
2.62M
        switch (mod)
8013
2.62M
    {
8014
688k
    case '{':
8015
688k
      ++c;
8016
688k
      if (*c == '\0')
8017
0
        abort ();
8018
688k
      old_base_style = base_style;
8019
688k
      base_style = decode_base_style (*c);
8020
688k
      ++c;
8021
688k
      if (*c != ':')
8022
0
        abort ();
8023
688k
      break;
8024
8025
688k
    case '}':
8026
688k
      base_style = old_base_style;
8027
688k
      break;
8028
8029
0
    case '%':
8030
0
      func (stream, base_style, "%%");
8031
0
      break;
8032
8033
108k
    case 'A':
8034
112k
    case 'K':
8035
112k
      {
8036
112k
        int rn = (given >> 16) & 0xf;
8037
112k
        bfd_vma offset = given & 0xff;
8038
8039
112k
        if (mod == 'K')
8040
3.50k
          offset = given & 0x7f;
8041
8042
112k
        func (stream, dis_style_text, "[");
8043
112k
        func (stream, dis_style_register, "%s",
8044
112k
        arm_regnames [(given >> 16) & 0xf]);
8045
8046
112k
        if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8047
85.7k
          {
8048
      /* Not unindexed.  The offset is scaled.  */
8049
85.7k
      if (cp_num == 9)
8050
        /* vldr.16/vstr.16 will shift the address
8051
           left by 1 bit only.  */
8052
845
        offset = offset * 2;
8053
84.9k
      else
8054
84.9k
        offset = offset * 4;
8055
8056
85.7k
      if (NEGATIVE_BIT_SET)
8057
43.6k
        offset = - offset;
8058
85.7k
      if (rn != 15)
8059
77.7k
        value_in_comment = offset;
8060
85.7k
          }
8061
8062
112k
        if (PRE_BIT_SET)
8063
57.1k
          {
8064
57.1k
      if (offset)
8065
49.3k
        {
8066
49.3k
          func (stream, dis_style_text, ", ");
8067
49.3k
          func (stream, dis_style_immediate, "#%d",
8068
49.3k
          (int) offset);
8069
49.3k
          func (stream, dis_style_text, "]%s",
8070
49.3k
          WRITEBACK_BIT_SET ? "!" : "");
8071
49.3k
        }
8072
7.81k
      else if (NEGATIVE_BIT_SET)
8073
5.55k
        {
8074
5.55k
          func (stream, dis_style_text, ", ");
8075
5.55k
          func (stream, dis_style_immediate, "#-0");
8076
5.55k
          func (stream, dis_style_text, "]");
8077
5.55k
        }
8078
2.25k
      else
8079
2.25k
        func (stream, dis_style_text, "]");
8080
57.1k
          }
8081
54.9k
        else
8082
54.9k
          {
8083
54.9k
      func (stream, dis_style_text, "]");
8084
8085
54.9k
      if (WRITEBACK_BIT_SET)
8086
28.5k
        {
8087
28.5k
          if (offset)
8088
26.2k
            {
8089
26.2k
        func (stream, dis_style_text, ", ");
8090
26.2k
        func (stream, dis_style_immediate,
8091
26.2k
              "#%d", (int) offset);
8092
26.2k
            }
8093
2.30k
          else if (NEGATIVE_BIT_SET)
8094
1.15k
            {
8095
1.15k
        func (stream, dis_style_text, ", ");
8096
1.15k
        func (stream, dis_style_immediate, "#-0");
8097
1.15k
            }
8098
28.5k
        }
8099
26.3k
      else
8100
26.3k
        {
8101
26.3k
          func (stream, dis_style_text, ", {");
8102
26.3k
          func (stream, dis_style_immediate, "%s%d",
8103
26.3k
          (NEGATIVE_BIT_SET && !offset) ? "-" : "",
8104
26.3k
          (int) offset);
8105
26.3k
          func (stream, dis_style_text, "}");
8106
26.3k
          value_in_comment = offset;
8107
26.3k
        }
8108
54.9k
          }
8109
112k
        if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8110
8.04k
          {
8111
8.04k
      func (stream, dis_style_comment_start, "\t@ ");
8112
      /* For unaligned PCs, apply off-by-alignment
8113
         correction.  */
8114
8.04k
      info->print_address_func (offset + pc
8115
8.04k
              + info->bytes_per_chunk * 2
8116
8.04k
              - (pc & 3),
8117
8.04k
              info);
8118
8.04k
          }
8119
112k
      }
8120
112k
      break;
8121
8122
1.65k
    case 'B':
8123
1.65k
      {
8124
1.65k
        int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8125
1.65k
        int offset = (given >> 1) & 0x3f;
8126
8127
1.65k
        func (stream, dis_style_text, "{");
8128
1.65k
        if (offset == 1)
8129
202
          func (stream, dis_style_register, "d%d", regno);
8130
1.45k
        else if (regno + offset > 32)
8131
975
          {
8132
975
      func (stream, dis_style_register, "d%d", regno);
8133
975
      func (stream, dis_style_text, "-<overflow reg d%d>",
8134
975
            regno + offset - 1);
8135
975
          }
8136
479
        else
8137
479
          {
8138
479
      func (stream, dis_style_register, "d%d", regno);
8139
479
      func (stream, dis_style_text, "-");
8140
479
      func (stream, dis_style_register, "d%d",
8141
479
            regno + offset - 1);
8142
479
          }
8143
1.65k
        func (stream, dis_style_text, "}");
8144
1.65k
      }
8145
1.65k
      break;
8146
8147
2.47k
    case 'C':
8148
2.47k
      {
8149
2.47k
        bool single = ((given >> 8) & 1) == 0;
8150
2.47k
        char reg_prefix = single ? 's' : 'd';
8151
2.47k
        int Dreg = (given >> 22) & 0x1;
8152
2.47k
        int Vdreg = (given >> 12) & 0xf;
8153
2.47k
        int reg = single ? ((Vdreg << 1) | Dreg)
8154
2.47k
             : ((Dreg << 4) | Vdreg);
8155
2.47k
        int num = (given >> (single ? 0 : 1)) & 0x7f;
8156
2.47k
        int maxreg = single ? 31 : 15;
8157
2.47k
        int topreg = reg + num - 1;
8158
8159
2.47k
        func (stream, dis_style_text, "{");
8160
2.47k
        if (!num)
8161
414
          {
8162
      /* Nothing.  */
8163
414
          }
8164
2.06k
        else if (num == 1)
8165
302
          {
8166
302
      func (stream, dis_style_register,
8167
302
            "%c%d", reg_prefix, reg);
8168
302
      func (stream, dis_style_text, ", ");
8169
302
          }
8170
1.75k
        else if (topreg > maxreg)
8171
1.52k
          {
8172
1.52k
      func (stream, dis_style_register, "%c%d",
8173
1.52k
            reg_prefix, reg);
8174
1.52k
      func (stream, dis_style_text, "-<overflow reg d%d, ",
8175
1.52k
            single ? topreg >> 1 : topreg);
8176
1.52k
          }
8177
239
        else
8178
239
          {
8179
239
      func (stream, dis_style_register,
8180
239
            "%c%d", reg_prefix, reg);
8181
239
      func (stream, dis_style_text, "-");
8182
239
      func (stream, dis_style_register, "%c%d",
8183
239
            reg_prefix, topreg);
8184
239
      func (stream, dis_style_text, ", ");
8185
239
          }
8186
2.47k
        func (stream, dis_style_register, "VPR");
8187
2.47k
        func (stream, dis_style_text, "}");
8188
2.47k
      }
8189
2.47k
      break;
8190
8191
3.04k
    case 'u':
8192
3.04k
      if (cond != COND_UNCOND)
8193
595
        is_unpredictable = true;
8194
8195
      /* Fall through.  */
8196
219k
    case 'c':
8197
219k
      if (cond != COND_UNCOND && cp_num == 9)
8198
400
        is_unpredictable = true;
8199
8200
      /* Fall through.  */
8201
219k
    case 'b':
8202
219k
      func (stream, dis_style_mnemonic, "%s",
8203
219k
      arm_conditional[cond]);
8204
219k
      break;
8205
8206
3.50k
    case 'J':
8207
3.50k
      {
8208
3.50k
        unsigned long regno
8209
3.50k
          = arm_decode_field_multiple (given, 13, 15, 22, 22);
8210
8211
3.50k
        switch (regno)
8212
3.50k
          {
8213
321
          case 0x1:
8214
321
      func (stream, dis_style_register, "FPSCR");
8215
321
      break;
8216
231
          case 0x2:
8217
231
      func (stream, dis_style_register, "FPSCR_nzcvqc");
8218
231
      break;
8219
384
          case 0xc:
8220
384
      func (stream, dis_style_register, "VPR");
8221
384
      break;
8222
287
          case 0xd:
8223
287
      func (stream, dis_style_register, "P0");
8224
287
      break;
8225
710
          case 0xe:
8226
710
      func (stream, dis_style_register, "FPCXTNS");
8227
710
      break;
8228
251
          case 0xf:
8229
251
      func (stream, dis_style_register, "FPCXTS");
8230
251
      break;
8231
1.32k
          default:
8232
1.32k
      func (stream, dis_style_text, "<invalid reg %lu>",
8233
1.32k
            regno);
8234
1.32k
      break;
8235
3.50k
          }
8236
3.50k
      }
8237
3.50k
      break;
8238
8239
591k
    case '0': case '1': case '2': case '3': case '4':
8240
868k
    case '5': case '6': case '7': case '8': case '9':
8241
868k
      {
8242
868k
        int width;
8243
8244
868k
        c = arm_decode_bitfield (c, given, &value, &width);
8245
8246
868k
        switch (*c)
8247
868k
          {
8248
18.3k
          case 'R':
8249
18.3k
      if (value == 15)
8250
3.08k
        is_unpredictable = true;
8251
      /* Fall through.  */
8252
41.5k
          case 'r':
8253
41.5k
      if (c[1] == 'u')
8254
2.26k
        {
8255
          /* Eat the 'u' character.  */
8256
2.26k
          ++ c;
8257
8258
2.26k
          if (u_reg == value)
8259
316
            is_unpredictable = true;
8260
2.26k
          u_reg = value;
8261
2.26k
        }
8262
41.5k
      func (stream, dis_style_register, "%s",
8263
41.5k
            arm_regnames[value]);
8264
41.5k
      break;
8265
4.32k
          case 'V':
8266
4.32k
      if (given & (1 << 6))
8267
2.50k
        goto Q;
8268
      /* FALLTHROUGH */
8269
5.04k
          case 'D':
8270
5.04k
      func (stream, dis_style_register, "d%ld", value);
8271
5.04k
      break;
8272
1.09k
          case 'Q':
8273
3.60k
          Q:
8274
3.60k
      if (value & 1)
8275
842
        func (stream, dis_style_text,
8276
842
        "<illegal reg q%ld.5>", value >> 1);
8277
2.76k
      else
8278
2.76k
        func (stream, dis_style_register,
8279
2.76k
        "q%ld", value >> 1);
8280
3.60k
      break;
8281
683k
          case 'd':
8282
683k
      func (stream, base_style, "%ld", value);
8283
683k
      value_in_comment = value;
8284
683k
      break;
8285
868
          case 'E':
8286
868
                        {
8287
        /* Converts immediate 8 bit back to float value.  */
8288
868
        unsigned floatVal = (value & 0x80) << 24
8289
868
          | (value & 0x3F) << 19
8290
868
          | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8291
8292
        /* Quarter float have a maximum value of 31.0.
8293
           Get floating point value multiplied by 1e7.
8294
           The maximum value stays in limit of a 32-bit int.  */
8295
868
        unsigned decVal =
8296
868
          (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8297
868
          (16 + (value & 0xF));
8298
8299
868
        if (!(decVal % 1000000))
8300
298
          {
8301
298
            func (stream, dis_style_immediate, "%ld", value);
8302
298
            func (stream, dis_style_comment_start,
8303
298
            "\t@ 0x%08x %c%u.%01u",
8304
298
            floatVal, value & 0x80 ? '-' : ' ',
8305
298
            decVal / 10000000,
8306
298
            decVal % 10000000 / 1000000);
8307
298
          }
8308
570
        else if (!(decVal % 10000))
8309
285
          {
8310
285
            func (stream, dis_style_immediate, "%ld", value);
8311
285
            func (stream, dis_style_comment_start,
8312
285
            "\t@ 0x%08x %c%u.%03u",
8313
285
            floatVal, value & 0x80 ? '-' : ' ',
8314
285
            decVal / 10000000,
8315
285
            decVal % 10000000 / 10000);
8316
285
          }
8317
285
        else
8318
285
          {
8319
285
            func (stream, dis_style_immediate, "%ld", value);
8320
285
            func (stream, dis_style_comment_start,
8321
285
            "\t@ 0x%08x %c%u.%07u",
8322
285
            floatVal, value & 0x80 ? '-' : ' ',
8323
285
            decVal / 10000000, decVal % 10000000);
8324
285
          }
8325
868
        break;
8326
1.09k
      }
8327
914
          case 'k':
8328
914
      {
8329
914
        int from = (given & (1 << 7)) ? 32 : 16;
8330
914
        func (stream, dis_style_immediate, "%ld",
8331
914
        from - value);
8332
914
      }
8333
914
      break;
8334
8335
730
          case 'w':
8336
730
      if (width == 2)
8337
480
        func (stream, dis_style_mnemonic, "%s",
8338
480
        iwmmxt_wwnames[value]);
8339
250
      else
8340
250
        func (stream, dis_style_mnemonic, "%s",
8341
250
        iwmmxt_wwssnames[value]);
8342
730
      break;
8343
8344
8.69k
          case 'g':
8345
8.69k
      func (stream, dis_style_register, "%s",
8346
8.69k
            iwmmxt_regnames[value]);
8347
8.69k
      break;
8348
284
          case 'G':
8349
284
      func (stream, dis_style_register, "%s",
8350
284
            iwmmxt_cregnames[value]);
8351
284
      break;
8352
8353
194
          case 'x':
8354
194
      func (stream, dis_style_immediate, "0x%lx",
8355
194
            (value & 0xffffffffUL));
8356
194
      break;
8357
8358
2.36k
          case 'c':
8359
2.36k
      switch (value)
8360
2.36k
        {
8361
715
        case 0:
8362
715
          func (stream, dis_style_mnemonic, "eq");
8363
715
          break;
8364
8365
269
        case 1:
8366
269
          func (stream, dis_style_mnemonic, "vs");
8367
269
          break;
8368
8369
570
        case 2:
8370
570
          func (stream, dis_style_mnemonic, "ge");
8371
570
          break;
8372
8373
808
        case 3:
8374
808
          func (stream, dis_style_mnemonic, "gt");
8375
808
          break;
8376
8377
0
        default:
8378
0
          func (stream, dis_style_text, "??");
8379
0
          break;
8380
2.36k
        }
8381
2.36k
      break;
8382
8383
2.36k
          case '`':
8384
488
      c++;
8385
488
      if (value == 0)
8386
215
        func (stream, dis_style_mnemonic, "%c", *c);
8387
488
      break;
8388
112k
          case '\'':
8389
112k
      c++;
8390
112k
      if (value == ((1ul << width) - 1))
8391
59.3k
        func (stream, base_style, "%c", *c);
8392
112k
      break;
8393
8.13k
          case '?':
8394
8.13k
      func (stream, base_style, "%c",
8395
8.13k
            c[(1 << width) - (int) value]);
8396
8.13k
      c += 1 << width;
8397
8.13k
      break;
8398
0
          default:
8399
0
      abort ();
8400
868k
          }
8401
868k
      }
8402
868k
      break;
8403
8404
868k
    case 'y':
8405
28.8k
    case 'z':
8406
28.8k
      {
8407
28.8k
        int single = *c++ == 'y';
8408
28.8k
        int regno;
8409
8410
28.8k
        switch (*c)
8411
28.8k
          {
8412
324
          case '4': /* Sm pair */
8413
7.68k
          case '0': /* Sm, Dm */
8414
7.68k
      regno = given & 0x0000000f;
8415
7.68k
      if (single)
8416
4.46k
        {
8417
4.46k
          regno <<= 1;
8418
4.46k
          regno += (given >> 5) & 1;
8419
4.46k
        }
8420
3.21k
      else
8421
3.21k
        regno += ((given >> 5) & 1) << 4;
8422
7.68k
      break;
8423
8424
10.9k
          case '1': /* Sd, Dd */
8425
10.9k
      regno = (given >> 12) & 0x0000000f;
8426
10.9k
      if (single)
8427
6.69k
        {
8428
6.69k
          regno <<= 1;
8429
6.69k
          regno += (given >> 22) & 1;
8430
6.69k
        }
8431
4.22k
      else
8432
4.22k
        regno += ((given >> 22) & 1) << 4;
8433
10.9k
      break;
8434
8435
6.17k
          case '2': /* Sn, Dn */
8436
6.17k
      regno = (given >> 16) & 0x0000000f;
8437
6.17k
      if (single)
8438
3.47k
        {
8439
3.47k
          regno <<= 1;
8440
3.47k
          regno += (given >> 7) & 1;
8441
3.47k
        }
8442
2.70k
      else
8443
2.70k
        regno += ((given >> 7) & 1) << 4;
8444
6.17k
      break;
8445
8446
4.04k
          case '3': /* List */
8447
4.04k
      func (stream, dis_style_text, "{");
8448
4.04k
      regno = (given >> 12) & 0x0000000f;
8449
4.04k
      if (single)
8450
2.76k
        {
8451
2.76k
          regno <<= 1;
8452
2.76k
          regno += (given >> 22) & 1;
8453
2.76k
        }
8454
1.27k
      else
8455
1.27k
        regno += ((given >> 22) & 1) << 4;
8456
4.04k
      break;
8457
8458
0
          default:
8459
0
      abort ();
8460
28.8k
          }
8461
8462
28.8k
        func (stream, dis_style_register, "%c%d",
8463
28.8k
        single ? 's' : 'd', regno);
8464
8465
28.8k
        if (*c == '3')
8466
4.04k
          {
8467
4.04k
      int count = given & 0xff;
8468
8469
4.04k
      if (single == 0)
8470
1.27k
        count >>= 1;
8471
8472
4.04k
      if (--count)
8473
3.79k
        {
8474
3.79k
          func (stream, dis_style_text, "-");
8475
3.79k
          func (stream, dis_style_register, "%c%d",
8476
3.79k
          single ? 's' : 'd',
8477
3.79k
          regno + count);
8478
3.79k
        }
8479
8480
4.04k
      func (stream, dis_style_text, "}");
8481
4.04k
          }
8482
24.7k
        else if (*c == '4')
8483
324
          {
8484
324
      func (stream, dis_style_text, ", ");
8485
324
      func (stream, dis_style_register, "%c%d",
8486
324
            single ? 's' : 'd', regno + 1);
8487
324
          }
8488
28.8k
      }
8489
0
      break;
8490
8491
3.29k
    case 'L':
8492
3.29k
      switch (given & 0x00400100)
8493
3.29k
        {
8494
652
        case 0x00000000:
8495
652
          func (stream, dis_style_mnemonic, "b");
8496
652
          break;
8497
486
        case 0x00400000:
8498
486
          func (stream, dis_style_mnemonic, "h");
8499
486
          break;
8500
1.10k
        case 0x00000100:
8501
1.10k
          func (stream, dis_style_mnemonic, "w");
8502
1.10k
          break;
8503
1.04k
        case 0x00400100:
8504
1.04k
          func (stream, dis_style_mnemonic, "d");
8505
1.04k
          break;
8506
0
        default:
8507
0
          break;
8508
3.29k
        }
8509
3.29k
      break;
8510
8511
3.29k
    case 'Z':
8512
292
      {
8513
        /* given (20, 23) | given (0, 3) */
8514
292
        value = ((given >> 16) & 0xf0) | (given & 0xf);
8515
292
        func (stream, dis_style_immediate, "%d", (int) value);
8516
292
      }
8517
292
      break;
8518
8519
3.29k
    case 'l':
8520
      /* This is like the 'A' operator, except that if
8521
         the width field "M" is zero, then the offset is
8522
         *not* multiplied by four.  */
8523
3.29k
      {
8524
3.29k
        int offset = given & 0xff;
8525
3.29k
        int multiplier = (given & 0x00000100) ? 4 : 1;
8526
8527
3.29k
        func (stream, dis_style_text, "[");
8528
3.29k
        func (stream, dis_style_register, "%s",
8529
3.29k
        arm_regnames [(given >> 16) & 0xf]);
8530
8531
3.29k
        if (multiplier > 1)
8532
2.15k
          {
8533
2.15k
      value_in_comment = offset * multiplier;
8534
2.15k
      if (NEGATIVE_BIT_SET)
8535
977
        value_in_comment = - value_in_comment;
8536
2.15k
          }
8537
8538
3.29k
        if (offset)
8539
2.64k
          {
8540
2.64k
      if (PRE_BIT_SET)
8541
421
        {
8542
421
          func (stream, dis_style_text, ", ");
8543
421
          func (stream, dis_style_immediate, "#%s%d",
8544
421
          NEGATIVE_BIT_SET ? "-" : "",
8545
421
          offset * multiplier);
8546
421
          func (stream, dis_style_text, "]%s",
8547
421
          WRITEBACK_BIT_SET ? "!" : "");
8548
421
        }
8549
2.22k
      else
8550
2.22k
        {
8551
2.22k
          func (stream, dis_style_text, "], ");
8552
2.22k
          func (stream, dis_style_immediate, "#%s%d",
8553
2.22k
          NEGATIVE_BIT_SET ? "-" : "",
8554
2.22k
          offset * multiplier);
8555
2.22k
        }
8556
2.64k
          }
8557
646
        else
8558
646
          func (stream, dis_style_text, "]");
8559
3.29k
      }
8560
3.29k
      break;
8561
8562
2.30k
    case 'r':
8563
2.30k
      {
8564
2.30k
        int imm4 = (given >> 4) & 0xf;
8565
2.30k
        int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8566
2.30k
        int ubit = ! NEGATIVE_BIT_SET;
8567
2.30k
        const char *rm = arm_regnames [given & 0xf];
8568
2.30k
        const char *rn = arm_regnames [(given >> 16) & 0xf];
8569
8570
2.30k
        switch (puw_bits)
8571
2.30k
          {
8572
217
          case 1:
8573
781
          case 3:
8574
781
      func (stream, dis_style_text, "[");
8575
781
      func (stream, dis_style_register, "%s", rn);
8576
781
      func (stream, dis_style_text, "], ");
8577
781
      func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8578
781
      func (stream, dis_style_register, "%s", rm);
8579
781
      if (imm4)
8580
321
        {
8581
321
          func (stream, dis_style_text, ", ");
8582
321
          func (stream, dis_style_sub_mnemonic, "lsl ");
8583
321
          func (stream, dis_style_immediate, "#%d", imm4);
8584
321
        }
8585
781
      break;
8586
8587
292
          case 4:
8588
557
          case 5:
8589
775
          case 6:
8590
1.29k
          case 7:
8591
1.29k
      func (stream, dis_style_text, "[");
8592
1.29k
      func (stream, dis_style_register, "%s", rn);
8593
1.29k
      func (stream, dis_style_text, ", ");
8594
1.29k
      func (stream, dis_style_text, "%c", ubit ? '+' : '-');
8595
1.29k
      func (stream, dis_style_register, "%s", rm);
8596
1.29k
      if (imm4 > 0)
8597
1.01k
        {
8598
1.01k
          func (stream, dis_style_text, ", ");
8599
1.01k
          func (stream, dis_style_sub_mnemonic, "lsl ");
8600
1.01k
          func (stream, dis_style_immediate, "#%d", imm4);
8601
1.01k
        }
8602
1.29k
      func (stream, dis_style_text, "]");
8603
1.29k
      if (puw_bits == 5 || puw_bits == 7)
8604
788
        func (stream, dis_style_text, "!");
8605
1.29k
      break;
8606
8607
228
          default:
8608
228
      func (stream, dis_style_text, "INVALID");
8609
2.30k
          }
8610
2.30k
      }
8611
2.30k
      break;
8612
8613
2.30k
    case 'i':
8614
471
      {
8615
471
        long imm5;
8616
471
        imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8617
471
        func (stream, dis_style_immediate, "%ld",
8618
471
        (imm5 == 0) ? 32 : imm5);
8619
471
      }
8620
471
      break;
8621
8622
0
    default:
8623
0
      abort ();
8624
2.62M
    }
8625
2.62M
      }
8626
3.26M
    else
8627
3.26M
      {
8628
3.26M
        if (*c == '@')
8629
1.27k
    base_style = dis_style_comment_start;
8630
8631
3.26M
        if (*c == '\t')
8632
226k
    base_style = dis_style_text;
8633
8634
3.26M
        func (stream, base_style, "%c", *c);
8635
3.26M
      }
8636
5.88M
  }
8637
8638
224k
      if (value_in_comment > 32 || value_in_comment < -16)
8639
86.5k
  func (stream, dis_style_comment_start, "\t@ 0x%lx",
8640
86.5k
        (value_in_comment & 0xffffffffUL));
8641
8642
224k
      if (is_unpredictable)
8643
8.21k
  func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
8644
8645
224k
      return true;
8646
224k
    }
8647
3.63M
  return false;
8648
3.85M
}
8649
8650
static bool
8651
print_insn_coprocessor (bfd_vma pc,
8652
      struct disassemble_info *info,
8653
      long given,
8654
      bool thumb)
8655
2.04M
{
8656
2.04M
  return print_insn_coprocessor_1 (coprocessor_opcodes,
8657
2.04M
           pc, info, given, thumb);
8658
2.04M
}
8659
8660
static bool
8661
print_insn_generic_coprocessor (bfd_vma pc,
8662
        struct disassemble_info *info,
8663
        long given,
8664
        bool thumb)
8665
1.81M
{
8666
1.81M
  return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8667
1.81M
           pc, info, given, thumb);
8668
1.81M
}
8669
8670
/* Decodes and prints ARM addressing modes.  Returns the offset
8671
   used in the address, if any, if it is worthwhile printing the
8672
   offset as a hexadecimal value in a comment at the end of the
8673
   line of disassembly.  */
8674
8675
static signed long
8676
print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8677
159k
{
8678
159k
  void *stream = info->stream;
8679
159k
  fprintf_styled_ftype func = info->fprintf_styled_func;
8680
159k
  bfd_vma offset = 0;
8681
8682
159k
  if (((given & 0x000f0000) == 0x000f0000)
8683
9.31k
      && ((given & 0x02000000) == 0))
8684
6.57k
    {
8685
6.57k
      offset = given & 0xfff;
8686
8687
6.57k
      func (stream, dis_style_text, "[");
8688
6.57k
      func (stream, dis_style_register, "pc");
8689
8690
6.57k
      if (PRE_BIT_SET)
8691
3.17k
  {
8692
    /* Pre-indexed.  Elide offset of positive zero when
8693
       non-writeback.  */
8694
3.17k
    if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8695
2.83k
      {
8696
2.83k
        func (stream, dis_style_text, ", ");
8697
2.83k
        func (stream, dis_style_immediate, "#%s%d",
8698
2.83k
        NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8699
2.83k
      }
8700
8701
3.17k
    if (NEGATIVE_BIT_SET)
8702
1.24k
      offset = -offset;
8703
8704
3.17k
    offset += pc + 8;
8705
8706
    /* Cope with the possibility of write-back
8707
       being used.  Probably a very dangerous thing
8708
       for the programmer to do, but who are we to
8709
       argue ?  */
8710
3.17k
    func (stream, dis_style_text, "]%s", WRITEBACK_BIT_SET ? "!" : "");
8711
3.17k
  }
8712
3.40k
      else  /* Post indexed.  */
8713
3.40k
  {
8714
3.40k
    func (stream, dis_style_text, "], ");
8715
3.40k
    func (stream, dis_style_immediate, "#%s%d",
8716
3.40k
    NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8717
8718
    /* Ie ignore the offset.  */
8719
3.40k
    offset = pc + 8;
8720
3.40k
  }
8721
8722
6.57k
      func (stream, dis_style_comment_start, "\t@ ");
8723
6.57k
      info->print_address_func (offset, info);
8724
6.57k
      offset = 0;
8725
6.57k
    }
8726
152k
  else
8727
152k
    {
8728
152k
      func (stream, dis_style_text, "[");
8729
152k
      func (stream, dis_style_register, "%s",
8730
152k
      arm_regnames[(given >> 16) & 0xf]);
8731
8732
152k
      if (PRE_BIT_SET)
8733
69.3k
  {
8734
69.3k
    if ((given & 0x02000000) == 0)
8735
47.9k
      {
8736
        /* Elide offset of positive zero when non-writeback.  */
8737
47.9k
        offset = given & 0xfff;
8738
47.9k
        if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8739
46.6k
    {
8740
46.6k
      func (stream, dis_style_text, ", ");
8741
46.6k
      func (stream, dis_style_immediate, "#%s%d",
8742
46.6k
      NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8743
46.6k
    }
8744
47.9k
      }
8745
21.3k
    else
8746
21.3k
      {
8747
21.3k
        func (stream, dis_style_text, ", %s",
8748
21.3k
        NEGATIVE_BIT_SET ? "-" : "");
8749
21.3k
        arm_decode_shift (given, func, stream, true);
8750
21.3k
      }
8751
8752
69.3k
    func (stream, dis_style_text, "]%s",
8753
69.3k
    WRITEBACK_BIT_SET ? "!" : "");
8754
69.3k
  }
8755
83.5k
      else
8756
83.5k
  {
8757
83.5k
    if ((given & 0x02000000) == 0)
8758
60.8k
      {
8759
        /* Always show offset.  */
8760
60.8k
        offset = given & 0xfff;
8761
60.8k
        func (stream, dis_style_text, "], ");
8762
60.8k
        func (stream, dis_style_immediate, "#%s%d",
8763
60.8k
        NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8764
60.8k
      }
8765
22.7k
    else
8766
22.7k
      {
8767
22.7k
        func (stream, dis_style_text, "], %s",
8768
22.7k
        NEGATIVE_BIT_SET ? "-" : "");
8769
22.7k
        arm_decode_shift (given, func, stream, true);
8770
22.7k
      }
8771
83.5k
  }
8772
152k
      if (NEGATIVE_BIT_SET)
8773
94.6k
  offset = -offset;
8774
152k
    }
8775
8776
159k
  return (signed long) offset;
8777
159k
}
8778
8779
8780
/* Print one cde instruction on INFO->STREAM.
8781
   Return TRUE if the instuction matched, FALSE if this is not a
8782
   recognised cde instruction.  */
8783
static bool
8784
print_insn_cde (struct disassemble_info *info, long given, bool thumb)
8785
424k
{
8786
424k
  const struct cdeopcode32 *insn;
8787
424k
  void *stream = info->stream;
8788
424k
  fprintf_styled_ftype func = info->fprintf_styled_func;
8789
424k
  enum disassembler_style base_style = dis_style_mnemonic;
8790
424k
  enum disassembler_style old_base_style = base_style;
8791
8792
424k
  if (thumb)
8793
424k
  {
8794
    /* Manually extract the coprocessor code from a known point.
8795
       This position is the same across all CDE instructions.  */
8796
5.48M
    for (insn = cde_opcodes; insn->assembler; insn++)
8797
5.06M
    {
8798
5.06M
      uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
8799
5.06M
      uint16_t coproc_mask = 1 << coproc;
8800
5.06M
      if (! (coproc_mask & cde_coprocs))
8801
4.41M
  continue;
8802
8803
650k
      if ((given & insn->mask) == insn->value)
8804
5.79k
      {
8805
5.79k
  bool is_unpredictable = false;
8806
5.79k
  const char *c;
8807
8808
136k
  for (c = insn->assembler; *c; c++)
8809
131k
  {
8810
131k
    if (*c == '%')
8811
47.7k
    {
8812
47.7k
      switch (*++c)
8813
47.7k
      {
8814
5.79k
        case '{':
8815
5.79k
    ++c;
8816
5.79k
    if (*c == '\0')
8817
0
      abort ();
8818
5.79k
    old_base_style = base_style;
8819
5.79k
    base_style = decode_base_style (*c);
8820
5.79k
    ++c;
8821
5.79k
    if (*c != ':')
8822
0
      abort ();
8823
5.79k
    break;
8824
8825
5.79k
        case '}':
8826
5.79k
    base_style = old_base_style;
8827
5.79k
    break;
8828
8829
0
        case '%':
8830
0
    func (stream, base_style, "%%");
8831
0
    break;
8832
8833
24.5k
        case '0': case '1': case '2': case '3': case '4':
8834
24.5k
        case '5': case '6': case '7': case '8': case '9':
8835
24.5k
        {
8836
24.5k
    int width;
8837
24.5k
    unsigned long value;
8838
8839
24.5k
    c = arm_decode_bitfield (c, given, &value, &width);
8840
8841
24.5k
    switch (*c)
8842
24.5k
    {
8843
3.44k
      case 'S':
8844
3.44k
        if (value > 10)
8845
1.43k
          is_unpredictable = true;
8846
        /* Fall through.  */
8847
3.44k
      case 'R':
8848
3.44k
        if (value == 13)
8849
231
          is_unpredictable = true;
8850
        /* Fall through.  */
8851
3.44k
      case 'r':
8852
3.44k
        func (stream, dis_style_register, "%s",
8853
3.44k
        arm_regnames[value]);
8854
3.44k
        break;
8855
8856
6.77k
      case 'n':
8857
6.77k
        if (value == 15)
8858
628
          func (stream, dis_style_register, "%s", "APSR_nzcv");
8859
6.15k
        else
8860
6.15k
          func (stream, dis_style_register, "%s",
8861
6.15k
          arm_regnames[value]);
8862
6.77k
        break;
8863
8864
3.44k
      case 'T':
8865
3.44k
        func (stream, dis_style_register, "%s",
8866
3.44k
        arm_regnames[(value + 1) & 15]);
8867
3.44k
        break;
8868
8869
5.79k
      case 'd':
8870
5.79k
        func (stream, dis_style_immediate, "%ld", value);
8871
5.79k
        break;
8872
8873
5.07k
      case 'V':
8874
5.07k
        if (given & (1 << 6))
8875
2.48k
          func (stream, dis_style_register, "q%ld", value >> 1);
8876
2.59k
        else if (given & (1 << 24))
8877
553
          func (stream, dis_style_register, "d%ld", value);
8878
2.04k
        else
8879
2.04k
          {
8880
      /* Encoding for S register is different than for D and
8881
         Q registers.  S registers are encoded using the top
8882
         single bit in position 22 as the lowest bit of the
8883
         register number, while for Q and D it represents the
8884
         highest bit of the register number.  */
8885
2.04k
      uint8_t top_bit = (value >> 4) & 1;
8886
2.04k
      uint8_t tmp = (value << 1) & 0x1e;
8887
2.04k
      uint8_t res = tmp | top_bit;
8888
2.04k
      func (stream, dis_style_register, "s%u", res);
8889
2.04k
          }
8890
5.07k
        break;
8891
8892
0
    default:
8893
0
      abort ();
8894
24.5k
    }
8895
24.5k
        }
8896
24.5k
      break;
8897
8898
24.5k
      case 'p':
8899
5.79k
        {
8900
5.79k
    uint8_t proc_number = (given >> 8) & 0x7;
8901
5.79k
    func (stream, dis_style_register, "p%u", proc_number);
8902
5.79k
    break;
8903
24.5k
        }
8904
8905
5.79k
      case 'a':
8906
5.79k
        {
8907
5.79k
    uint8_t a_offset = 28;
8908
5.79k
    if (given & (1 << a_offset))
8909
2.99k
      func (stream, dis_style_mnemonic, "a");
8910
5.79k
    break;
8911
24.5k
        }
8912
0
    default:
8913
0
      abort ();
8914
47.7k
    }
8915
47.7k
  }
8916
83.2k
  else
8917
83.2k
    {
8918
83.2k
      if (*c == '@')
8919
0
        base_style = dis_style_comment_start;
8920
83.2k
      if (*c == '\t')
8921
5.79k
        base_style = dis_style_text;
8922
8923
83.2k
      func (stream, base_style, "%c", *c);
8924
83.2k
    }
8925
131k
      }
8926
8927
5.79k
      if (is_unpredictable)
8928
1.43k
  func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
8929
8930
5.79k
      return true;
8931
5.79k
      }
8932
650k
    }
8933
419k
    return false;
8934
424k
  }
8935
0
  else
8936
0
    return false;
8937
424k
}
8938
8939
8940
/* Print one neon instruction on INFO->STREAM.
8941
   Return TRUE if the instuction matched, FALSE if this is not a
8942
   recognised neon instruction.  */
8943
8944
static bool
8945
print_insn_neon (struct disassemble_info *info, long given, bool thumb)
8946
1.55M
{
8947
1.55M
  const struct opcode32 *insn;
8948
1.55M
  void *stream = info->stream;
8949
1.55M
  fprintf_styled_ftype func = info->fprintf_styled_func;
8950
1.55M
  enum disassembler_style base_style = dis_style_mnemonic;
8951
1.55M
  enum disassembler_style old_base_style = base_style;
8952
8953
1.55M
  if (thumb)
8954
146k
    {
8955
146k
      if ((given & 0xef000000) == 0xef000000)
8956
43.0k
  {
8957
    /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
8958
43.0k
    unsigned long bit28 = given & (1 << 28);
8959
8960
43.0k
    given &= 0x00ffffff;
8961
43.0k
    if (bit28)
8962
39.4k
            given |= 0xf3000000;
8963
3.63k
          else
8964
3.63k
      given |= 0xf2000000;
8965
43.0k
  }
8966
103k
      else if ((given & 0xff000000) == 0xf9000000)
8967
14.3k
  given ^= 0xf9000000 ^ 0xf4000000;
8968
      /* BFloat16 neon instructions without special top byte handling.  */
8969
88.9k
      else if ((given & 0xff000000) == 0xfe000000
8970
78.5k
         || (given & 0xff000000) == 0xfc000000)
8971
15.8k
  ;
8972
      /* vdup is also a valid neon instruction.  */
8973
73.1k
      else if ((given & 0xff900f5f) != 0xee800b10)
8974
72.7k
  return false;
8975
146k
    }
8976
8977
445M
  for (insn = neon_opcodes; insn->assembler; insn++)
8978
443M
    {
8979
443M
      unsigned long cond_mask = insn->mask;
8980
443M
      unsigned long cond_value = insn->value;
8981
443M
      int cond;
8982
8983
443M
      if (thumb)
8984
18.3M
        {
8985
18.3M
          if ((cond_mask & 0xf0000000) == 0) {
8986
              /* For the entries in neon_opcodes, an opcode mask/value with
8987
                 the high 4 bits equal to 0 indicates a conditional
8988
                 instruction. For thumb however, we need to include those
8989
                 bits in the instruction matching.  */
8990
440k
              cond_mask |= 0xf0000000;
8991
              /* Furthermore, the thumb encoding of a conditional instruction
8992
                 will have the high 4 bits equal to 0xe.  */
8993
440k
              cond_value |= 0xe0000000;
8994
440k
          }
8995
18.3M
          if (ifthen_state)
8996
141k
            cond = IFTHEN_COND;
8997
18.1M
          else
8998
18.1M
            cond = COND_UNCOND;
8999
18.3M
        }
9000
425M
      else
9001
425M
        {
9002
425M
          if ((given & 0xf0000000) == 0xf0000000)
9003
38.9M
            {
9004
              /* If the instruction is unconditional, update the mask to only
9005
                 match against unconditional opcode values.  */
9006
38.9M
              cond_mask |= 0xf0000000;
9007
38.9M
              cond = COND_UNCOND;
9008
38.9M
            }
9009
386M
          else
9010
386M
            {
9011
386M
              cond = (given >> 28) & 0xf;
9012
386M
              if (cond == 0xe)
9013
16.9M
                cond = COND_UNCOND;
9014
386M
            }
9015
425M
        }
9016
9017
443M
      if ((given & cond_mask) == cond_value)
9018
50.4k
  {
9019
50.4k
    signed long value_in_comment = 0;
9020
50.4k
    bool is_unpredictable = false;
9021
50.4k
    const char *c;
9022
9023
814k
    for (c = insn->assembler; *c; c++)
9024
766k
      {
9025
766k
        if (*c == '%')
9026
257k
    {
9027
257k
      switch (*++c)
9028
257k
        {
9029
8.96k
        case '{':
9030
8.96k
          ++c;
9031
8.96k
          if (*c == '\0')
9032
0
      abort ();
9033
8.96k
          old_base_style = base_style;
9034
8.96k
          base_style = decode_base_style (*c);
9035
8.96k
          ++c;
9036
8.96k
          if (*c != ':')
9037
0
      abort ();
9038
8.96k
          break;
9039
9040
8.96k
        case '}':
9041
8.96k
          base_style = old_base_style;
9042
8.96k
          break;
9043
9044
0
        case '%':
9045
0
          func (stream, base_style, "%%");
9046
0
          break;
9047
9048
4.05k
        case 'u':
9049
4.05k
          if (thumb && ifthen_state)
9050
266
      is_unpredictable = true;
9051
9052
          /* Fall through.  */
9053
49.5k
        case 'c':
9054
49.5k
          func (stream, dis_style_mnemonic, "%s",
9055
49.5k
          arm_conditional[cond]);
9056
49.5k
          break;
9057
9058
5.59k
        case 'A':
9059
5.59k
          {
9060
5.59k
      static const unsigned char enc[16] =
9061
5.59k
      {
9062
5.59k
        0x4, 0x14, /* st4 0,1 */
9063
5.59k
        0x4, /* st1 2 */
9064
5.59k
        0x4, /* st2 3 */
9065
5.59k
        0x3, /* st3 4 */
9066
5.59k
        0x13, /* st3 5 */
9067
5.59k
        0x3, /* st1 6 */
9068
5.59k
        0x1, /* st1 7 */
9069
5.59k
        0x2, /* st2 8 */
9070
5.59k
        0x12, /* st2 9 */
9071
5.59k
        0x2, /* st1 10 */
9072
5.59k
        0, 0, 0, 0, 0
9073
5.59k
      };
9074
5.59k
      int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9075
5.59k
      int rn = ((given >> 16) & 0xf);
9076
5.59k
      int rm = ((given >> 0) & 0xf);
9077
5.59k
      int align = ((given >> 4) & 0x3);
9078
5.59k
      int type = ((given >> 8) & 0xf);
9079
5.59k
      int n = enc[type] & 0xf;
9080
5.59k
      int stride = (enc[type] >> 4) + 1;
9081
5.59k
      int ix;
9082
9083
5.59k
      func (stream, dis_style_text, "{");
9084
5.59k
      if (stride > 1)
9085
6.86k
        for (ix = 0; ix != n; ix++)
9086
5.05k
          {
9087
5.05k
            if (ix > 0)
9088
3.24k
        func (stream, dis_style_text, ",");
9089
5.05k
            func (stream, dis_style_register, "d%d",
9090
5.05k
            rd + ix * stride);
9091
5.05k
          }
9092
3.78k
      else if (n == 1)
9093
737
        func (stream, dis_style_register, "d%d", rd);
9094
3.05k
      else
9095
3.05k
        {
9096
3.05k
          func (stream, dis_style_register, "d%d", rd);
9097
3.05k
          func (stream, dis_style_text, "-");
9098
3.05k
          func (stream, dis_style_register, "d%d",
9099
3.05k
          rd + n - 1);
9100
3.05k
        }
9101
5.59k
      func (stream, dis_style_text, "}, [");
9102
5.59k
      func (stream, dis_style_register, "%s",
9103
5.59k
            arm_regnames[rn]);
9104
5.59k
      if (align)
9105
4.10k
        {
9106
4.10k
          func (stream, dis_style_text, " :");
9107
4.10k
          func (stream, dis_style_immediate, "%d",
9108
4.10k
          32 << align);
9109
4.10k
        }
9110
5.59k
      func (stream, dis_style_text, "]");
9111
5.59k
      if (rm == 0xd)
9112
1.27k
        func (stream, dis_style_text, "!");
9113
4.31k
      else if (rm != 0xf)
9114
3.87k
        {
9115
3.87k
          func (stream, dis_style_text, ", ");
9116
3.87k
          func (stream, dis_style_register, "%s",
9117
3.87k
          arm_regnames[rm]);
9118
3.87k
        }
9119
5.59k
          }
9120
5.59k
          break;
9121
9122
7.10k
        case 'B':
9123
7.10k
          {
9124
7.10k
      int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9125
7.10k
      int rn = ((given >> 16) & 0xf);
9126
7.10k
      int rm = ((given >> 0) & 0xf);
9127
7.10k
      int idx_align = ((given >> 4) & 0xf);
9128
7.10k
                        int align = 0;
9129
7.10k
      int size = ((given >> 10) & 0x3);
9130
7.10k
      int idx = idx_align >> (size + 1);
9131
7.10k
                        int length = ((given >> 8) & 3) + 1;
9132
7.10k
                        int stride = 1;
9133
7.10k
                        int i;
9134
9135
7.10k
                        if (length > 1 && size > 0)
9136
3.71k
                          stride = (idx_align & (1 << size)) ? 2 : 1;
9137
9138
7.10k
                        switch (length)
9139
7.10k
                          {
9140
2.70k
                          case 1:
9141
2.70k
                            {
9142
2.70k
                              int amask = (1 << size) - 1;
9143
2.70k
                              if ((idx_align & (1 << size)) != 0)
9144
999
                                return false;
9145
1.70k
                              if (size > 0)
9146
1.14k
                                {
9147
1.14k
                                  if ((idx_align & amask) == amask)
9148
288
                                    align = 8 << size;
9149
852
                                  else if ((idx_align & amask) != 0)
9150
400
                                    return false;
9151
1.14k
                                }
9152
1.70k
                              }
9153
1.30k
                            break;
9154
9155
1.47k
                          case 2:
9156
1.47k
                            if (size == 2 && (idx_align & 2) != 0)
9157
311
                              return false;
9158
1.16k
                            align = (idx_align & 1) ? 16 << size : 0;
9159
1.16k
                            break;
9160
9161
1.32k
                          case 3:
9162
1.32k
                            if ((size == 2 && (idx_align & 3) != 0)
9163
927
                                || (idx_align & 1) != 0)
9164
891
                              return false;
9165
430
                            break;
9166
9167
1.59k
                          case 4:
9168
1.59k
                            if (size == 2)
9169
634
                              {
9170
634
                                if ((idx_align & 3) == 3)
9171
252
                                  return false;
9172
382
                                align = (idx_align & 3) * 64;
9173
382
                              }
9174
964
                            else
9175
964
                              align = (idx_align & 1) ? 32 << size : 0;
9176
1.34k
                            break;
9177
9178
1.34k
                          default:
9179
0
                            abort ();
9180
7.10k
                          }
9181
9182
4.25k
      func (stream, dis_style_text, "{");
9183
14.5k
                        for (i = 0; i < length; i++)
9184
10.3k
        {
9185
10.3k
          if (i > 0)
9186
6.06k
            func (stream, dis_style_text, ",");
9187
10.3k
          func (stream, dis_style_register, "d%d[%d]",
9188
10.3k
          rd + i * stride, idx);
9189
10.3k
        }
9190
4.25k
      func (stream, dis_style_text, "}, [");
9191
4.25k
      func (stream, dis_style_register, "%s",
9192
4.25k
            arm_regnames[rn]);
9193
4.25k
      if (align)
9194
1.75k
        {
9195
1.75k
          func (stream, dis_style_text, " :");
9196
1.75k
          func (stream, dis_style_immediate, "%d", align);
9197
1.75k
        }
9198
4.25k
      func (stream, dis_style_text, "]");
9199
4.25k
      if (rm == 0xd)
9200
490
        func (stream, dis_style_text, "!");
9201
3.76k
      else if (rm != 0xf)
9202
2.85k
        {
9203
2.85k
          func (stream, dis_style_text, ", ");
9204
2.85k
          func (stream, dis_style_register, "%s",
9205
2.85k
          arm_regnames[rm]);
9206
2.85k
        }
9207
4.25k
          }
9208
0
          break;
9209
9210
2.55k
        case 'C':
9211
2.55k
          {
9212
2.55k
      int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9213
2.55k
      int rn = ((given >> 16) & 0xf);
9214
2.55k
      int rm = ((given >> 0) & 0xf);
9215
2.55k
      int align = ((given >> 4) & 0x1);
9216
2.55k
      int size = ((given >> 6) & 0x3);
9217
2.55k
      int type = ((given >> 8) & 0x3);
9218
2.55k
      int n = type + 1;
9219
2.55k
      int stride = ((given >> 5) & 0x1);
9220
2.55k
      int ix;
9221
9222
2.55k
      if (stride && (n == 1))
9223
799
        n++;
9224
1.75k
      else
9225
1.75k
        stride++;
9226
9227
2.55k
      func (stream, dis_style_text, "{");
9228
2.55k
      if (stride > 1)
9229
4.59k
        for (ix = 0; ix != n; ix++)
9230
3.61k
          {
9231
3.61k
            if (ix > 0)
9232
2.64k
        func (stream, dis_style_text, ",");
9233
3.61k
            func (stream, dis_style_register, "d%d[]",
9234
3.61k
            rd + ix * stride);
9235
3.61k
          }
9236
1.58k
      else if (n == 1)
9237
248
        func (stream, dis_style_register, "d%d[]", rd);
9238
1.33k
      else
9239
1.33k
        {
9240
1.33k
          func (stream, dis_style_register, "d%d[]", rd);
9241
1.33k
          func (stream, dis_style_text, "-");
9242
1.33k
          func (stream, dis_style_register, "d%d[]",
9243
1.33k
          rd + n - 1);
9244
1.33k
        }
9245
2.55k
      func (stream, dis_style_text, "}, [");
9246
2.55k
      func (stream, dis_style_register, "%s",
9247
2.55k
            arm_regnames[rn]);
9248
2.55k
      if (align)
9249
1.88k
        {
9250
1.88k
                            align = (8 * (type + 1)) << size;
9251
1.88k
                            if (type == 3)
9252
650
                              align = (size > 1) ? align >> 1 : align;
9253
1.88k
          if (type == 2 || (type == 0 && !size))
9254
774
            func (stream, dis_style_text,
9255
774
            " :<bad align %d>", align);
9256
1.11k
          else
9257
1.11k
            {
9258
1.11k
        func (stream, dis_style_text, " :");
9259
1.11k
        func (stream, dis_style_immediate,
9260
1.11k
              "%d", align);
9261
1.11k
            }
9262
1.88k
        }
9263
2.55k
      func (stream, dis_style_text, "]");
9264
2.55k
      if (rm == 0xd)
9265
434
        func (stream, dis_style_text, "!");
9266
2.12k
      else if (rm != 0xf)
9267
1.67k
        {
9268
1.67k
          func (stream, dis_style_text, ", ");
9269
1.67k
          func (stream, dis_style_register, "%s",
9270
1.67k
          arm_regnames[rm]);
9271
1.67k
        }
9272
2.55k
          }
9273
2.55k
          break;
9274
9275
2.41k
        case 'D':
9276
2.41k
          {
9277
2.41k
      int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9278
2.41k
      int size = (given >> 20) & 3;
9279
2.41k
      int reg = raw_reg & ((4 << size) - 1);
9280
2.41k
      int ix = raw_reg >> size >> 2;
9281
9282
2.41k
      func (stream, dis_style_register, "d%d[%d]", reg, ix);
9283
2.41k
          }
9284
2.41k
          break;
9285
9286
2.95k
        case 'E':
9287
          /* Neon encoded constant for mov, mvn, vorr, vbic.  */
9288
2.95k
          {
9289
2.95k
      int bits = 0;
9290
2.95k
      int cmode = (given >> 8) & 0xf;
9291
2.95k
      int op = (given >> 5) & 0x1;
9292
2.95k
      unsigned long value = 0, hival = 0;
9293
2.95k
      unsigned shift;
9294
2.95k
                        int size = 0;
9295
2.95k
                        int isfloat = 0;
9296
9297
2.95k
      bits |= ((given >> 24) & 1) << 7;
9298
2.95k
      bits |= ((given >> 16) & 7) << 4;
9299
2.95k
      bits |= ((given >> 0) & 15) << 0;
9300
9301
2.95k
      if (cmode < 8)
9302
853
        {
9303
853
          shift = (cmode >> 1) & 3;
9304
853
          value = (unsigned long) bits << (8 * shift);
9305
853
                            size = 32;
9306
853
        }
9307
2.09k
      else if (cmode < 12)
9308
387
        {
9309
387
          shift = (cmode >> 1) & 1;
9310
387
          value = (unsigned long) bits << (8 * shift);
9311
387
                            size = 16;
9312
387
        }
9313
1.71k
      else if (cmode < 14)
9314
281
        {
9315
281
          shift = (cmode & 1) + 1;
9316
281
          value = (unsigned long) bits << (8 * shift);
9317
281
          value |= (1ul << (8 * shift)) - 1;
9318
281
                            size = 32;
9319
281
        }
9320
1.43k
      else if (cmode == 14)
9321
831
        {
9322
831
          if (op)
9323
603
            {
9324
        /* Bit replication into bytes.  */
9325
603
        int ix;
9326
603
        unsigned long mask;
9327
9328
603
        value = 0;
9329
603
                                hival = 0;
9330
5.42k
        for (ix = 7; ix >= 0; ix--)
9331
4.82k
          {
9332
4.82k
            mask = ((bits >> ix) & 1) ? 0xff : 0;
9333
4.82k
                                    if (ix <= 3)
9334
2.41k
              value = (value << 8) | mask;
9335
2.41k
                                    else
9336
2.41k
                                      hival = (hival << 8) | mask;
9337
4.82k
          }
9338
603
                                size = 64;
9339
603
            }
9340
228
                            else
9341
228
                              {
9342
                                /* Byte replication.  */
9343
228
                                value = (unsigned long) bits;
9344
228
                                size = 8;
9345
228
                              }
9346
831
        }
9347
599
      else if (!op)
9348
599
        {
9349
          /* Floating point encoding.  */
9350
599
          int tmp;
9351
9352
599
          value = (unsigned long)  (bits & 0x7f) << 19;
9353
599
          value |= (unsigned long) (bits & 0x80) << 24;
9354
599
          tmp = bits & 0x40 ? 0x3c : 0x40;
9355
599
          value |= (unsigned long) tmp << 24;
9356
599
                            size = 32;
9357
599
                            isfloat = 1;
9358
599
        }
9359
0
      else
9360
0
        {
9361
0
          func (stream, dis_style_text,
9362
0
          "<illegal constant %.8x:%x:%x>",
9363
0
                                  bits, cmode, op);
9364
0
                            size = 32;
9365
0
          break;
9366
0
        }
9367
2.95k
                        switch (size)
9368
2.95k
                          {
9369
228
                          case 8:
9370
228
          func (stream, dis_style_immediate, "#%ld", value);
9371
228
          func (stream, dis_style_comment_start,
9372
228
          "\t@ 0x%.2lx", value);
9373
228
                            break;
9374
9375
387
                          case 16:
9376
387
          func (stream, dis_style_immediate, "#%ld", value);
9377
387
          func (stream, dis_style_comment_start,
9378
387
          "\t@ 0x%.4lx", value);
9379
387
                            break;
9380
9381
1.73k
                          case 32:
9382
1.73k
                            if (isfloat)
9383
599
                              {
9384
599
                                unsigned char valbytes[4];
9385
599
                                double fvalue;
9386
9387
                                /* Do this a byte at a time so we don't have to
9388
                                   worry about the host's endianness.  */
9389
599
                                valbytes[0] = value & 0xff;
9390
599
                                valbytes[1] = (value >> 8) & 0xff;
9391
599
                                valbytes[2] = (value >> 16) & 0xff;
9392
599
                                valbytes[3] = (value >> 24) & 0xff;
9393
9394
599
                                floatformat_to_double
9395
599
                                  (& floatformat_ieee_single_little, valbytes,
9396
599
                                  & fvalue);
9397
9398
599
        func (stream, dis_style_immediate,
9399
599
              "#%.7g", fvalue);
9400
599
        func (stream, dis_style_comment_start,
9401
599
              "\t@ 0x%.8lx", value);
9402
599
                              }
9403
1.13k
                            else
9404
1.13k
            {
9405
1.13k
        func (stream, dis_style_immediate, "#%ld",
9406
1.13k
              (long) (((value & 0x80000000L) != 0)
9407
1.13k
                ? value | ~0xffffffffL : value));
9408
1.13k
        func (stream, dis_style_comment_start,
9409
1.13k
              "\t@ 0x%.8lx", value);
9410
1.13k
            }
9411
1.73k
                            break;
9412
9413
603
                          case 64:
9414
603
          func (stream, dis_style_immediate,
9415
603
          "#0x%.8lx%.8lx", hival, value);
9416
603
                            break;
9417
9418
0
                          default:
9419
0
                            abort ();
9420
2.95k
                          }
9421
2.95k
          }
9422
2.95k
          break;
9423
9424
2.95k
        case 'F':
9425
1.52k
          {
9426
1.52k
      int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9427
1.52k
      int num = (given >> 8) & 0x3;
9428
9429
1.52k
      func (stream, dis_style_text, "{");
9430
1.52k
      if (!num)
9431
414
        func (stream, dis_style_register, "d%d", regno);
9432
1.11k
      else if (num + regno >= 32)
9433
588
        {
9434
588
          func (stream, dis_style_register, "d%d", regno);
9435
588
          func (stream, dis_style_text, "-<overflow reg d%d",
9436
588
          regno + num);
9437
588
        }
9438
523
      else
9439
523
        {
9440
523
          func (stream, dis_style_register, "d%d", regno);
9441
523
          func (stream, dis_style_text, "-");
9442
523
          func (stream, dis_style_register, "d%d",
9443
523
          regno + num);
9444
523
        }
9445
1.52k
      func (stream, dis_style_text, "}");
9446
1.52k
          }
9447
1.52k
          break;
9448
9449
9450
158k
        case '0': case '1': case '2': case '3': case '4':
9451
168k
        case '5': case '6': case '7': case '8': case '9':
9452
168k
          {
9453
168k
      int width;
9454
168k
      unsigned long value;
9455
9456
168k
      c = arm_decode_bitfield (c, given, &value, &width);
9457
9458
168k
      switch (*c)
9459
168k
        {
9460
390
        case 'r':
9461
390
          func (stream, dis_style_register, "%s",
9462
390
          arm_regnames[value]);
9463
390
          break;
9464
4.00k
        case 'd':
9465
4.00k
          func (stream, base_style, "%ld", value);
9466
4.00k
          value_in_comment = value;
9467
4.00k
          break;
9468
5.28k
        case 'e':
9469
5.28k
          func (stream, dis_style_immediate, "%ld",
9470
5.28k
          (1ul << width) - value);
9471
5.28k
          break;
9472
9473
28.6k
        case 'S':
9474
29.4k
        case 'T':
9475
29.4k
        case 'U':
9476
          /* Various width encodings.  */
9477
29.4k
          {
9478
29.4k
            int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9479
29.4k
            int limit;
9480
29.4k
            unsigned low, high;
9481
9482
29.4k
            c++;
9483
29.4k
            if (*c >= '0' && *c <= '9')
9484
28.7k
        limit = *c - '0';
9485
705
            else if (*c >= 'a' && *c <= 'f')
9486
705
        limit = *c - 'a' + 10;
9487
0
            else
9488
0
        abort ();
9489
29.4k
            low = limit >> 2;
9490
29.4k
            high = limit & 3;
9491
9492
29.4k
            if (value < low || value > high)
9493
8.23k
        func (stream, dis_style_text,
9494
8.23k
              "<illegal width %d>", base << value);
9495
21.2k
            else
9496
21.2k
        func (stream, base_style, "%d",
9497
21.2k
              base << value);
9498
29.4k
          }
9499
0
          break;
9500
61.2k
        case 'R':
9501
61.2k
          if (given & (1 << 6))
9502
39.6k
            goto Q;
9503
          /* FALLTHROUGH */
9504
33.8k
        case 'D':
9505
33.8k
          func (stream, dis_style_register, "d%ld", value);
9506
33.8k
          break;
9507
12.4k
        case 'Q':
9508
52.0k
        Q:
9509
52.0k
          if (value & 1)
9510
25.7k
            func (stream, dis_style_text,
9511
25.7k
            "<illegal reg q%ld.5>", value >> 1);
9512
26.2k
          else
9513
26.2k
            func (stream, dis_style_register,
9514
26.2k
            "q%ld", value >> 1);
9515
52.0k
          break;
9516
9517
0
        case '`':
9518
0
          c++;
9519
0
          if (value == 0)
9520
0
            func (stream, dis_style_text, "%c", *c);
9521
0
          break;
9522
0
        case '\'':
9523
0
          c++;
9524
0
          if (value == ((1ul << width) - 1))
9525
0
            func (stream, dis_style_text, "%c", *c);
9526
0
          break;
9527
43.0k
        case '?':
9528
43.0k
          func (stream, dis_style_mnemonic, "%c",
9529
43.0k
          c[(1 << width) - (int) value]);
9530
43.0k
          c += 1 << width;
9531
43.0k
          break;
9532
0
        default:
9533
0
          abort ();
9534
168k
        }
9535
168k
          }
9536
168k
          break;
9537
9538
168k
        default:
9539
0
          abort ();
9540
257k
        }
9541
257k
    }
9542
508k
        else
9543
508k
    {
9544
508k
      if (*c == '@')
9545
0
        base_style = dis_style_comment_start;
9546
9547
508k
      if (*c == '\t')
9548
50.4k
        base_style = dis_style_text;
9549
9550
508k
      func (stream, base_style, "%c", *c);
9551
9552
508k
    }
9553
766k
      }
9554
9555
47.5k
    if (value_in_comment > 32 || value_in_comment < -16)
9556
1.46k
      func (stream, dis_style_comment_start, "\t@ 0x%lx",
9557
1.46k
      value_in_comment);
9558
9559
47.5k
    if (is_unpredictable)
9560
266
      func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
9561
9562
47.5k
    return true;
9563
50.4k
  }
9564
443M
    }
9565
1.43M
  return false;
9566
1.48M
}
9567
9568
/* Print one mve instruction on INFO->STREAM.
9569
   Return TRUE if the instuction matched, FALSE if this is not a
9570
   recognised mve instruction.  */
9571
9572
static bool
9573
print_insn_mve (struct disassemble_info *info, long given)
9574
454k
{
9575
454k
  const struct mopcode32 *insn;
9576
454k
  void *stream = info->stream;
9577
454k
  fprintf_styled_ftype func = info->fprintf_styled_func;
9578
454k
  enum disassembler_style base_style = dis_style_mnemonic;
9579
454k
  enum disassembler_style old_base_style = base_style;
9580
9581
88.9M
  for (insn = mve_opcodes; insn->assembler; insn++)
9582
88.5M
    {
9583
88.5M
      if (((given & insn->mask) == insn->value)
9584
175k
    && !is_mve_encoding_conflict (given, insn->mve_op))
9585
140k
  {
9586
140k
    signed long value_in_comment = 0;
9587
140k
    bool is_unpredictable = false;
9588
140k
    bool is_undefined = false;
9589
140k
    const char *c;
9590
140k
    enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9591
140k
    enum mve_undefined undefined_cond = UNDEF_NONE;
9592
9593
    /* Most vector mve instruction are illegal in a it block.
9594
       There are a few exceptions; check for them.  */
9595
140k
    if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9596
1.74k
      {
9597
1.74k
        is_unpredictable = true;
9598
1.74k
        unpredictable_cond = UNPRED_IT_BLOCK;
9599
1.74k
      }
9600
139k
    else if (is_mve_unpredictable (given, insn->mve_op,
9601
139k
           &unpredictable_cond))
9602
24.0k
      is_unpredictable = true;
9603
9604
140k
    if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9605
15.7k
      is_undefined = true;
9606
9607
    /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9608
       i.e "VMOV Qd, Qm".  */
9609
140k
    if ((insn->mve_op == MVE_VORR_REG)
9610
1.01k
        && (arm_decode_field (given, 1, 3)
9611
1.01k
      == arm_decode_field (given, 17, 19)))
9612
778
      continue;
9613
9614
2.49M
    for (c = insn->assembler; *c; c++)
9615
2.35M
      {
9616
2.35M
        if (*c == '%')
9617
753k
    {
9618
753k
      switch (*++c)
9619
753k
        {
9620
29.5k
        case '{':
9621
29.5k
          ++c;
9622
29.5k
          if (*c == '\0')
9623
0
      abort ();
9624
29.5k
          old_base_style = base_style;
9625
29.5k
          base_style = decode_base_style (*c);
9626
29.5k
          ++c;
9627
29.5k
          if (*c != ':')
9628
0
      abort ();
9629
29.5k
          break;
9630
9631
29.5k
        case '}':
9632
29.5k
          base_style = old_base_style;
9633
29.5k
          break;
9634
9635
0
        case '%':
9636
0
          func (stream, base_style, "%%");
9637
0
          break;
9638
9639
2.71k
        case 'a':
9640
          /* Don't print anything for '+' as it is implied.  */
9641
2.71k
          if (arm_decode_field (given, 23, 23) == 0)
9642
1.99k
      func (stream, dis_style_immediate, "-");
9643
2.71k
          break;
9644
9645
11.6k
        case 'c':
9646
11.6k
          if (ifthen_state)
9647
7.08k
      func (stream, dis_style_mnemonic, "%s",
9648
7.08k
            arm_conditional[IFTHEN_COND]);
9649
11.6k
          break;
9650
9651
6.78k
        case 'd':
9652
6.78k
          print_mve_vld_str_addr (info, given, insn->mve_op);
9653
6.78k
          break;
9654
9655
10.1k
        case 'i':
9656
10.1k
          {
9657
10.1k
      long mve_mask = mve_extract_pred_mask (given);
9658
10.1k
      func (stream, dis_style_mnemonic, "%s",
9659
10.1k
            mve_predicatenames[mve_mask]);
9660
10.1k
          }
9661
10.1k
          break;
9662
9663
5.26k
        case 'j':
9664
5.26k
          {
9665
5.26k
      unsigned int imm5 = 0;
9666
5.26k
      imm5 |= arm_decode_field (given, 6, 7);
9667
5.26k
      imm5 |= (arm_decode_field (given, 12, 14) << 2);
9668
5.26k
      func (stream, dis_style_immediate, "#%u",
9669
5.26k
            (imm5 == 0) ? 32 : imm5);
9670
5.26k
          }
9671
5.26k
          break;
9672
9673
864
        case 'k':
9674
864
          func (stream, dis_style_immediate, "#%u",
9675
864
          (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9676
864
          break;
9677
9678
12.7k
        case 'n':
9679
12.7k
          print_vec_condition (info, given, insn->mve_op);
9680
12.7k
          break;
9681
9682
4.45k
        case 'o':
9683
4.45k
          if (arm_decode_field (given, 0, 0) == 1)
9684
2.62k
      {
9685
2.62k
        unsigned long size
9686
2.62k
          = arm_decode_field (given, 4, 4)
9687
2.62k
            | (arm_decode_field (given, 6, 6) << 1);
9688
9689
2.62k
        func (stream, dis_style_text, ", ");
9690
2.62k
        func (stream, dis_style_sub_mnemonic, "uxtw ");
9691
2.62k
        func (stream, dis_style_immediate, "#%lu", size);
9692
2.62k
      }
9693
4.45k
          break;
9694
9695
6.00k
        case 'm':
9696
6.00k
          print_mve_rounding_mode (info, given, insn->mve_op);
9697
6.00k
          break;
9698
9699
11.9k
        case 's':
9700
11.9k
          print_mve_vcvt_size (info, given, insn->mve_op);
9701
11.9k
          break;
9702
9703
28.4k
        case 'u':
9704
28.4k
          {
9705
28.4k
      unsigned long op1 = arm_decode_field (given, 21, 22);
9706
9707
28.4k
      if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9708
650
        {
9709
          /* Check for signed.  */
9710
650
          if (arm_decode_field (given, 23, 23) == 0)
9711
242
            {
9712
        /* We don't print 's' for S32.  */
9713
242
        if ((arm_decode_field (given, 5, 6) == 0)
9714
0
            && ((op1 == 0) || (op1 == 1)))
9715
0
          ;
9716
242
        else
9717
242
          func (stream, dis_style_mnemonic, "s");
9718
242
            }
9719
408
          else
9720
408
            func (stream, dis_style_mnemonic, "u");
9721
650
        }
9722
27.7k
      else
9723
27.7k
        {
9724
27.7k
          if (arm_decode_field (given, 28, 28) == 0)
9725
13.9k
            func (stream, dis_style_mnemonic, "s");
9726
13.8k
          else
9727
13.8k
            func (stream, dis_style_mnemonic, "u");
9728
27.7k
        }
9729
28.4k
          }
9730
28.4k
          break;
9731
9732
112k
        case 'v':
9733
112k
          print_instruction_predicate (info);
9734
112k
          break;
9735
9736
3.49k
        case 'w':
9737
3.49k
          if (arm_decode_field (given, 21, 21) == 1)
9738
1.67k
      func (stream, dis_style_text, "!");
9739
3.49k
          break;
9740
9741
2.69k
        case 'B':
9742
2.69k
          print_mve_register_blocks (info, given, insn->mve_op);
9743
2.69k
          break;
9744
9745
8.93k
        case 'E':
9746
          /* SIMD encoded constant for mov, mvn, vorr, vbic.  */
9747
9748
8.93k
          print_simd_imm8 (info, given, 28, insn);
9749
8.93k
          break;
9750
9751
1.57k
        case 'N':
9752
1.57k
          print_mve_vmov_index (info, given);
9753
1.57k
          break;
9754
9755
10.8k
        case 'T':
9756
10.8k
          if (arm_decode_field (given, 12, 12) == 0)
9757
6.05k
      func (stream, dis_style_mnemonic, "b");
9758
4.76k
          else
9759
4.76k
      func (stream, dis_style_mnemonic, "t");
9760
10.8k
          break;
9761
9762
3.40k
        case 'X':
9763
3.40k
          if (arm_decode_field (given, 12, 12) == 1)
9764
1.32k
      func (stream, dis_style_mnemonic, "x");
9765
3.40k
          break;
9766
9767
410k
        case '0': case '1': case '2': case '3': case '4':
9768
450k
        case '5': case '6': case '7': case '8': case '9':
9769
450k
          {
9770
450k
      int width;
9771
450k
      unsigned long value;
9772
9773
450k
      c = arm_decode_bitfield (c, given, &value, &width);
9774
9775
450k
      switch (*c)
9776
450k
        {
9777
10.9k
        case 'Z':
9778
10.9k
          if (value == 13)
9779
1.60k
            is_unpredictable = true;
9780
9.33k
          else if (value == 15)
9781
1.82k
            func (stream, dis_style_register, "zr");
9782
7.50k
          else
9783
7.50k
            func (stream, dis_style_register, "%s",
9784
7.50k
            arm_regnames[value]);
9785
10.9k
          break;
9786
9787
1.78k
        case 'c':
9788
1.78k
          func (stream, dis_style_sub_mnemonic, "%s",
9789
1.78k
          arm_conditional[value]);
9790
1.78k
          break;
9791
9792
1.18k
        case 'C':
9793
1.18k
          value ^= 1;
9794
1.18k
          func (stream, dis_style_sub_mnemonic, "%s",
9795
1.18k
          arm_conditional[value]);
9796
1.18k
          break;
9797
9798
8.51k
        case 'S':
9799
8.51k
          if (value == 13 || value == 15)
9800
2.12k
            is_unpredictable = true;
9801
6.39k
          else
9802
6.39k
            func (stream, dis_style_register, "%s",
9803
6.39k
            arm_regnames[value]);
9804
8.51k
          break;
9805
9806
95.5k
        case 's':
9807
95.5k
          print_mve_size (info,
9808
95.5k
              value,
9809
95.5k
              insn->mve_op);
9810
95.5k
          break;
9811
736
        case 'I':
9812
736
          if (value == 1)
9813
378
            func (stream, dis_style_mnemonic, "i");
9814
736
          break;
9815
5.47k
        case 'A':
9816
5.47k
          if (value == 1)
9817
1.78k
            func (stream, dis_style_mnemonic, "a");
9818
5.47k
          break;
9819
11.2k
        case 'h':
9820
11.2k
          {
9821
11.2k
            unsigned int odd_reg = (value << 1) | 1;
9822
11.2k
            func (stream, dis_style_register, "%s",
9823
11.2k
            arm_regnames[odd_reg]);
9824
11.2k
          }
9825
11.2k
          break;
9826
2.71k
        case 'i':
9827
2.71k
          {
9828
2.71k
            unsigned long imm
9829
2.71k
        = arm_decode_field (given, 0, 6);
9830
2.71k
            unsigned long mod_imm = imm;
9831
9832
2.71k
            switch (insn->mve_op)
9833
2.71k
        {
9834
729
        case MVE_VLDRW_GATHER_T5:
9835
1.33k
        case MVE_VSTRW_SCATTER_T5:
9836
1.33k
          mod_imm = mod_imm << 2;
9837
1.33k
          break;
9838
1.06k
        case MVE_VSTRD_SCATTER_T6:
9839
1.37k
        case MVE_VLDRD_GATHER_T6:
9840
1.37k
          mod_imm = mod_imm << 3;
9841
1.37k
          break;
9842
9843
0
        default:
9844
0
          break;
9845
2.71k
        }
9846
9847
2.71k
            func (stream, dis_style_immediate, "%lu",
9848
2.71k
            mod_imm);
9849
2.71k
          }
9850
0
          break;
9851
4.59k
        case 'k':
9852
4.59k
          func (stream, dis_style_immediate, "%lu",
9853
4.59k
          64 - value);
9854
4.59k
          break;
9855
14.5k
        case 'l':
9856
14.5k
          {
9857
14.5k
            unsigned int even_reg = value << 1;
9858
14.5k
            func (stream, dis_style_register, "%s",
9859
14.5k
            arm_regnames[even_reg]);
9860
14.5k
          }
9861
14.5k
          break;
9862
3.64k
        case 'u':
9863
3.64k
          switch (value)
9864
3.64k
            {
9865
490
            case 0:
9866
490
        func (stream, dis_style_immediate, "1");
9867
490
        break;
9868
314
            case 1:
9869
314
        func (stream, dis_style_immediate, "2");
9870
314
        break;
9871
2.21k
            case 2:
9872
2.21k
        func (stream, dis_style_immediate, "4");
9873
2.21k
        break;
9874
631
            case 3:
9875
631
        func (stream, dis_style_immediate, "8");
9876
631
        break;
9877
0
            default:
9878
0
        break;
9879
3.64k
            }
9880
3.64k
          break;
9881
5.18k
        case 'o':
9882
5.18k
          print_mve_rotate (info, value, width);
9883
5.18k
          break;
9884
32.9k
        case 'r':
9885
32.9k
          func (stream, dis_style_register, "%s",
9886
32.9k
          arm_regnames[value]);
9887
32.9k
          break;
9888
10.4k
        case 'd':
9889
10.4k
          if (mve_shift_insn_p (insn->mve_op))
9890
6.64k
            print_mve_shift_n (info, given, insn->mve_op);
9891
3.84k
          else if (insn->mve_op == MVE_VSHLL_T2)
9892
279
            func (stream, dis_style_immediate, "%s",
9893
279
            mve_vec_sizename[value]);
9894
3.56k
          else
9895
3.56k
            {
9896
3.56k
        if (insn->mve_op == MVE_VSHLC && value == 0)
9897
477
          value = 32;
9898
3.56k
        func (stream, base_style, "%ld", value);
9899
3.56k
        value_in_comment = value;
9900
3.56k
            }
9901
10.4k
          break;
9902
0
        case 'F':
9903
0
          func (stream, dis_style_register, "s%ld", value);
9904
0
          break;
9905
240k
        case 'Q':
9906
240k
          if (value & 0x8)
9907
111k
            func (stream, dis_style_text,
9908
111k
            "<illegal reg q%ld.5>", value);
9909
129k
          else
9910
129k
            func (stream, dis_style_register, "q%ld", value);
9911
240k
          break;
9912
223
        case 'x':
9913
223
          func (stream, dis_style_immediate,
9914
223
          "0x%08lx", value);
9915
223
          break;
9916
0
        default:
9917
0
          abort ();
9918
450k
        }
9919
450k
      break;
9920
450k
          default:
9921
0
      abort ();
9922
450k
          }
9923
753k
        }
9924
753k
    }
9925
1.60M
        else
9926
1.60M
    {
9927
1.60M
      if (*c == '@')
9928
223
        base_style = dis_style_comment_start;
9929
9930
1.60M
      if (*c == '\t')
9931
139k
        base_style = dis_style_text;
9932
9933
1.60M
      func (stream, base_style, "%c", *c);
9934
1.60M
    }
9935
2.35M
      }
9936
9937
139k
    if (value_in_comment > 32 || value_in_comment < -16)
9938
0
      func (stream, dis_style_comment_start, "\t@ 0x%lx",
9939
0
      value_in_comment);
9940
9941
139k
    if (is_unpredictable)
9942
28.5k
      print_mve_unpredictable (info, unpredictable_cond);
9943
9944
139k
    if (is_undefined)
9945
15.7k
      print_mve_undefined (info, undefined_cond);
9946
9947
139k
    if (!vpt_block_state.in_vpt_block
9948
129k
        && !ifthen_state
9949
120k
        && is_vpt_instruction (given))
9950
4.19k
      mark_inside_vpt_block (given);
9951
135k
    else if (vpt_block_state.in_vpt_block)
9952
10.7k
      update_vpt_block_state ();
9953
9954
139k
    return true;
9955
139k
  }
9956
88.5M
    }
9957
314k
  return false;
9958
454k
}
9959
9960
9961
/* Return the name of a v7A special register.  */
9962
9963
static const char *
9964
banked_regname (unsigned reg)
9965
25.2k
{
9966
25.2k
  switch (reg)
9967
25.2k
    {
9968
300
      case 15: return "CPSR";
9969
427
      case 32: return "R8_usr";
9970
337
      case 33: return "R9_usr";
9971
360
      case 34: return "R10_usr";
9972
241
      case 35: return "R11_usr";
9973
204
      case 36: return "R12_usr";
9974
242
      case 37: return "SP_usr";
9975
306
      case 38: return "LR_usr";
9976
378
      case 40: return "R8_fiq";
9977
230
      case 41: return "R9_fiq";
9978
411
      case 42: return "R10_fiq";
9979
300
      case 43: return "R11_fiq";
9980
201
      case 44: return "R12_fiq";
9981
214
      case 45: return "SP_fiq";
9982
378
      case 46: return "LR_fiq";
9983
649
      case 48: return "LR_irq";
9984
321
      case 49: return "SP_irq";
9985
286
      case 50: return "LR_svc";
9986
274
      case 51: return "SP_svc";
9987
233
      case 52: return "LR_abt";
9988
479
      case 53: return "SP_abt";
9989
385
      case 54: return "LR_und";
9990
266
      case 55: return "SP_und";
9991
353
      case 60: return "LR_mon";
9992
264
      case 61: return "SP_mon";
9993
245
      case 62: return "ELR_hyp";
9994
283
      case 63: return "SP_hyp";
9995
222
      case 79: return "SPSR";
9996
275
      case 110: return "SPSR_fiq";
9997
392
      case 112: return "SPSR_irq";
9998
283
      case 114: return "SPSR_svc";
9999
257
      case 116: return "SPSR_abt";
10000
209
      case 118: return "SPSR_und";
10001
477
      case 124: return "SPSR_mon";
10002
328
      case 126: return "SPSR_hyp";
10003
14.2k
      default: return NULL;
10004
25.2k
    }
10005
25.2k
}
10006
10007
/* Return the name of the DMB/DSB option.  */
10008
static const char *
10009
data_barrier_option (unsigned option)
10010
1.09k
{
10011
1.09k
  switch (option & 0xf)
10012
1.09k
    {
10013
33
    case 0xf: return "sy";
10014
11
    case 0xe: return "st";
10015
1
    case 0xd: return "ld";
10016
4
    case 0xb: return "ish";
10017
217
    case 0xa: return "ishst";
10018
11
    case 0x9: return "ishld";
10019
39
    case 0x7: return "un";
10020
66
    case 0x6: return "unst";
10021
123
    case 0x5: return "nshld";
10022
0
    case 0x3: return "osh";
10023
5
    case 0x2: return "oshst";
10024
2
    case 0x1: return "oshld";
10025
579
    default:  return NULL;
10026
1.09k
    }
10027
1.09k
}
10028
10029
/* Print one ARM instruction from PC on INFO->STREAM.  */
10030
10031
static void
10032
print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
10033
1.41M
{
10034
1.41M
  const struct opcode32 *insn;
10035
1.41M
  void *stream = info->stream;
10036
1.41M
  fprintf_styled_ftype func = info->fprintf_styled_func;
10037
1.41M
  struct arm_private_data *private_data = info->private_data;
10038
1.41M
  enum disassembler_style base_style = dis_style_mnemonic;
10039
1.41M
  enum disassembler_style old_base_style = base_style;
10040
10041
1.41M
  if (print_insn_coprocessor (pc, info, given, false))
10042
11.7k
    return;
10043
10044
1.40M
  if (print_insn_neon (info, given, false))
10045
11.8k
    return;
10046
10047
1.39M
  if (print_insn_generic_coprocessor (pc, info, given, false))
10048
139k
    return;
10049
10050
344M
  for (insn = arm_opcodes; insn->assembler; insn++)
10051
344M
    {
10052
344M
      if ((given & insn->mask) != insn->value)
10053
343M
  continue;
10054
10055
1.41M
      if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
10056
51.8k
  continue;
10057
10058
      /* Special case: an instruction with all bits set in the condition field
10059
   (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
10060
   or by the catchall at the end of the table.  */
10061
1.36M
      if ((given & 0xF0000000) != 0xF0000000
10062
226k
    || (insn->mask & 0xF0000000) == 0xF0000000
10063
223k
    || (insn->mask == 0 && insn->value == 0))
10064
1.25M
  {
10065
1.25M
    unsigned long u_reg = 16;
10066
1.25M
    unsigned long U_reg = 16;
10067
1.25M
    bool is_unpredictable = false;
10068
1.25M
    signed long value_in_comment = 0;
10069
1.25M
    const char *c;
10070
10071
19.1M
    for (c = insn->assembler; *c; c++)
10072
17.8M
      {
10073
17.8M
        if (*c == '%')
10074
5.12M
    {
10075
5.12M
      bool allow_unpredictable = false;
10076
10077
5.12M
      switch (*++c)
10078
5.12M
        {
10079
3.09k
        case '{':
10080
3.09k
          ++c;
10081
3.09k
          if (*c == '\0')
10082
0
      abort ();
10083
3.09k
          old_base_style = base_style;
10084
3.09k
          base_style = decode_base_style (*c);
10085
3.09k
          ++c;
10086
3.09k
          if (*c != ':')
10087
0
      abort ();
10088
3.09k
          break;
10089
10090
3.09k
        case '}':
10091
3.09k
          base_style = old_base_style;
10092
3.09k
          break;
10093
10094
0
        case '%':
10095
0
          func (stream, base_style, "%%");
10096
0
          break;
10097
10098
159k
        case 'a':
10099
159k
          value_in_comment = print_arm_address (pc, info, given);
10100
159k
          break;
10101
10102
194
        case 'P':
10103
          /* Set P address bit and use normal address
10104
       printing routine.  */
10105
194
          value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
10106
194
          break;
10107
10108
391
        case 'T':
10109
          /* Armv4 does not have a BX instruction, however, when
10110
       assembled with the --fix-v4bx option GAS will accept
10111
       and assemble a BX instruction when assembling for
10112
       Armv4.  When disassembling we also disassemble it as a
10113
       BX instruction, but do make the user aware that this
10114
       instruction is only supported on HW from Armv4T
10115
       onwards.  */
10116
391
          if (info->mach == bfd_mach_arm_4)
10117
194
      func (stream, dis_style_text, "\t@ from Armv4T onwards");
10118
391
          break;
10119
10120
3.70k
        case 'S':
10121
3.70k
          allow_unpredictable = true;
10122
          /* Fall through.  */
10123
25.8k
        case 's':
10124
25.8k
                      if ((given & 0x004f0000) == 0x004f0000)
10125
6.06k
      {
10126
                          /* PC relative with immediate offset.  */
10127
6.06k
        bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
10128
10129
6.06k
        if (PRE_BIT_SET)
10130
1.37k
          {
10131
            /* Elide positive zero offset.  */
10132
1.37k
            if (offset || NEGATIVE_BIT_SET)
10133
971
        {
10134
971
          func (stream, dis_style_text, "[");
10135
971
          func (stream, dis_style_register, "pc");
10136
971
          func (stream, dis_style_text, ", ");
10137
971
          func (stream, dis_style_immediate, "#%s%d",
10138
971
          (NEGATIVE_BIT_SET ? "-" : ""),
10139
971
          (int) offset);
10140
971
          func (stream, dis_style_text, "]");
10141
971
        }
10142
399
            else
10143
399
        {
10144
399
          func (stream, dis_style_text, "[");
10145
399
          func (stream, dis_style_register, "pc");
10146
399
          func (stream, dis_style_text, "]");
10147
399
        }
10148
1.37k
            if (NEGATIVE_BIT_SET)
10149
435
        offset = -offset;
10150
1.37k
            func (stream, dis_style_comment_start, "\t@ ");
10151
1.37k
            info->print_address_func (offset + pc + 8, info);
10152
1.37k
          }
10153
4.69k
        else
10154
4.69k
          {
10155
            /* Always show the offset.  */
10156
4.69k
            func (stream, dis_style_text, "[");
10157
4.69k
            func (stream, dis_style_register, "pc");
10158
4.69k
            func (stream, dis_style_text, "], ");
10159
4.69k
            func (stream, dis_style_immediate, "#%s%d",
10160
4.69k
            NEGATIVE_BIT_SET ? "-" : "", (int) offset);
10161
4.69k
            if (! allow_unpredictable)
10162
2.36k
        is_unpredictable = true;
10163
4.69k
          }
10164
6.06k
      }
10165
19.7k
          else
10166
19.7k
      {
10167
19.7k
        int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10168
10169
19.7k
        func (stream, dis_style_text, "[");
10170
19.7k
        func (stream, dis_style_register, "%s",
10171
19.7k
        arm_regnames[(given >> 16) & 0xf]);
10172
10173
19.7k
        if (PRE_BIT_SET)
10174
3.92k
          {
10175
3.92k
            if (IMMEDIATE_BIT_SET)
10176
2.62k
        {
10177
          /* Elide offset for non-writeback
10178
             positive zero.  */
10179
2.62k
          if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
10180
864
              || offset)
10181
2.42k
            {
10182
2.42k
              func (stream, dis_style_text, ", ");
10183
2.42k
              func (stream, dis_style_immediate,
10184
2.42k
              "#%s%d",
10185
2.42k
              (NEGATIVE_BIT_SET ? "-" : ""),
10186
2.42k
              offset);
10187
2.42k
            }
10188
10189
2.62k
          if (NEGATIVE_BIT_SET)
10190
886
            offset = -offset;
10191
10192
2.62k
          value_in_comment = offset;
10193
2.62k
        }
10194
1.30k
            else
10195
1.30k
        {
10196
          /* Register Offset or Register Pre-Indexed.  */
10197
1.30k
          func (stream, dis_style_text, ", %s",
10198
1.30k
          NEGATIVE_BIT_SET ? "-" : "");
10199
1.30k
          func (stream, dis_style_register, "%s",
10200
1.30k
          arm_regnames[given & 0xf]);
10201
10202
          /* Writing back to the register that is the source/
10203
             destination of the load/store is unpredictable.  */
10204
1.30k
          if (! allow_unpredictable
10205
1.30k
              && WRITEBACK_BIT_SET
10206
819
              && ((given & 0xf) == ((given >> 12) & 0xf)))
10207
209
            is_unpredictable = true;
10208
1.30k
        }
10209
10210
3.92k
            func (stream, dis_style_text, "]%s",
10211
3.92k
            WRITEBACK_BIT_SET ? "!" : "");
10212
3.92k
          }
10213
15.8k
        else
10214
15.8k
          {
10215
15.8k
            if (IMMEDIATE_BIT_SET)
10216
5.45k
        {
10217
          /* Immediate Post-indexed.  */
10218
          /* PR 10924: Offset must be printed, even if it is zero.  */
10219
5.45k
          func (stream, dis_style_text, "], ");
10220
5.45k
          func (stream, dis_style_immediate, "#%s%d",
10221
5.45k
          NEGATIVE_BIT_SET ? "-" : "", offset);
10222
5.45k
          if (NEGATIVE_BIT_SET)
10223
2.15k
            offset = -offset;
10224
5.45k
          value_in_comment = offset;
10225
5.45k
        }
10226
10.3k
            else
10227
10.3k
        {
10228
          /* Register Post-indexed.  */
10229
10.3k
          func (stream, dis_style_text, "], %s",
10230
10.3k
          NEGATIVE_BIT_SET ? "-" : "");
10231
10.3k
          func (stream, dis_style_register, "%s",
10232
10.3k
          arm_regnames[given & 0xf]);
10233
10234
          /* Writing back to the register that is the source/
10235
             destination of the load/store is unpredictable.  */
10236
10.3k
          if (! allow_unpredictable
10237
9.79k
              && (given & 0xf) == ((given >> 12) & 0xf))
10238
2.31k
            is_unpredictable = true;
10239
10.3k
        }
10240
10241
15.8k
            if (! allow_unpredictable)
10242
14.4k
        {
10243
          /* Writeback is automatically implied by post- addressing.
10244
             Setting the W bit is unnecessary and ARM specify it as
10245
             being unpredictable.  */
10246
14.4k
          if (WRITEBACK_BIT_SET
10247
              /* Specifying the PC register as the post-indexed
10248
           registers is also unpredictable.  */
10249
11.0k
              || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
10250
7.59k
            is_unpredictable = true;
10251
14.4k
        }
10252
15.8k
          }
10253
19.7k
      }
10254
25.8k
          break;
10255
10256
79.2k
        case 'b':
10257
79.2k
          {
10258
79.2k
      bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
10259
79.2k
      bfd_vma target = disp * 4 + pc + 8;
10260
79.2k
      info->print_address_func (target, info);
10261
10262
      /* Fill in instruction information.  */
10263
79.2k
      info->insn_info_valid = 1;
10264
79.2k
      info->insn_type = dis_branch;
10265
79.2k
      info->target = target;
10266
79.2k
          }
10267
79.2k
          break;
10268
10269
1.06M
        case 'c':
10270
1.06M
          if (((given >> 28) & 0xf) != 0xe)
10271
1.01M
      func (stream, dis_style_mnemonic, "%s",
10272
1.01M
            arm_conditional [(given >> 28) & 0xf]);
10273
1.06M
          break;
10274
10275
106k
        case 'm':
10276
106k
          {
10277
106k
      int started = 0;
10278
106k
      int reg;
10279
10280
106k
      func (stream, dis_style_text, "{");
10281
1.80M
      for (reg = 0; reg < 16; reg++)
10282
1.69M
        if ((given & (1 << reg)) != 0)
10283
664k
          {
10284
664k
            if (started)
10285
568k
        func (stream, dis_style_text, ", ");
10286
664k
            started = 1;
10287
664k
            func (stream, dis_style_register, "%s",
10288
664k
            arm_regnames[reg]);
10289
664k
          }
10290
106k
      func (stream, dis_style_text, "}");
10291
106k
      if (! started)
10292
10.4k
        is_unpredictable = true;
10293
106k
          }
10294
106k
          break;
10295
10296
1.18k
        case 'q':
10297
1.18k
          arm_decode_shift (given, func, stream, false);
10298
1.18k
          break;
10299
10300
611k
        case 'o':
10301
611k
          if ((given & 0x02000000) != 0)
10302
117k
      {
10303
117k
        unsigned int rotate = (given & 0xf00) >> 7;
10304
117k
        unsigned int immed = (given & 0xff);
10305
117k
        unsigned int a, i;
10306
10307
117k
        a = (immed << ((32 - rotate) & 31)
10308
117k
             | immed >> rotate) & 0xffffffff;
10309
        /* If there is another encoding with smaller rotate,
10310
           the rotate should be specified directly.  */
10311
613k
        for (i = 0; i < 32; i += 2)
10312
613k
          if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
10313
117k
            break;
10314
10315
117k
        if (i != rotate)
10316
20.4k
          {
10317
20.4k
            func (stream, dis_style_immediate, "#%d", immed);
10318
20.4k
            func (stream, dis_style_text, ", ");
10319
20.4k
            func (stream, dis_style_immediate, "%d", rotate);
10320
20.4k
          }
10321
97.2k
        else
10322
97.2k
          func (stream, dis_style_immediate, "#%d", a);
10323
117k
        value_in_comment = a;
10324
117k
      }
10325
494k
          else
10326
494k
      arm_decode_shift (given, func, stream, true);
10327
611k
          break;
10328
10329
61.2k
        case 'p':
10330
61.2k
          if ((given & 0x0000f000) == 0x0000f000)
10331
2.04k
      func (stream, dis_style_mnemonic, "p");
10332
61.2k
          break;
10333
61.2k
        case 'O':
10334
61.2k
          if ((given & 0x0000f000) == 0x0000f000)
10335
2.04k
      func (stream, dis_style_text,
10336
2.04k
            "\t@ p-variant is OBSOLETE");
10337
61.2k
          break;
10338
10339
133k
        case 't':
10340
133k
          if ((given & 0x01200000) == 0x00200000)
10341
28.7k
      func (stream, dis_style_mnemonic, "t");
10342
133k
          break;
10343
10344
0
        case 'A':
10345
0
          {
10346
0
      int offset = given & 0xff;
10347
10348
0
      value_in_comment = offset * 4;
10349
0
      if (NEGATIVE_BIT_SET)
10350
0
        value_in_comment = - value_in_comment;
10351
10352
0
      func (stream, dis_style_text, "[%s",
10353
0
            arm_regnames [(given >> 16) & 0xf]);
10354
10355
0
      if (PRE_BIT_SET)
10356
0
        {
10357
0
          if (offset)
10358
0
            func (stream, dis_style_text, ", #%d]%s",
10359
0
            (int) value_in_comment,
10360
0
            WRITEBACK_BIT_SET ? "!" : "");
10361
0
          else
10362
0
            func (stream, dis_style_text, "]");
10363
0
        }
10364
0
      else
10365
0
        {
10366
0
          func (stream, dis_style_text, "]");
10367
10368
0
          if (WRITEBACK_BIT_SET)
10369
0
            {
10370
0
        if (offset)
10371
0
          func (stream, dis_style_text,
10372
0
          ", #%d", (int) value_in_comment);
10373
0
            }
10374
0
          else
10375
0
            {
10376
0
        func (stream, dis_style_text,
10377
0
              ", {%d}", (int) offset);
10378
0
        value_in_comment = offset;
10379
0
            }
10380
0
        }
10381
0
          }
10382
0
          break;
10383
10384
1.95k
        case 'B':
10385
          /* Print ARM V5 BLX(1) address: pc+25 bits.  */
10386
1.95k
          {
10387
1.95k
      bfd_vma address;
10388
1.95k
      bfd_vma offset = 0;
10389
10390
1.95k
      if (! NEGATIVE_BIT_SET)
10391
        /* Is signed, hi bits should be ones.  */
10392
504
        offset = (-1) ^ 0x00ffffff;
10393
10394
      /* Offset is (SignExtend(offset field)<<2).  */
10395
1.95k
      offset += given & 0x00ffffff;
10396
1.95k
      offset <<= 2;
10397
1.95k
      address = offset + pc + 8;
10398
10399
1.95k
      if (given & 0x01000000)
10400
        /* H bit allows addressing to 2-byte boundaries.  */
10401
784
        address += 2;
10402
10403
1.95k
            info->print_address_func (address, info);
10404
10405
      /* Fill in instruction information.  */
10406
1.95k
      info->insn_info_valid = 1;
10407
1.95k
      info->insn_type = dis_branch;
10408
1.95k
      info->target = address;
10409
1.95k
          }
10410
1.95k
          break;
10411
10412
2.76k
        case 'C':
10413
2.76k
          if ((given & 0x02000200) == 0x200)
10414
1.14k
      {
10415
1.14k
        const char * name;
10416
1.14k
        unsigned sysm = (given & 0x004f0000) >> 16;
10417
10418
1.14k
        sysm |= (given & 0x300) >> 4;
10419
1.14k
        name = banked_regname (sysm);
10420
10421
1.14k
        if (name != NULL)
10422
894
          func (stream, dis_style_register, "%s", name);
10423
252
        else
10424
252
          func (stream, dis_style_text,
10425
252
          "(UNDEF: %lu)", (unsigned long) sysm);
10426
1.14k
      }
10427
1.61k
          else
10428
1.61k
      {
10429
1.61k
        func (stream, dis_style_register, "%cPSR_",
10430
1.61k
        (given & 0x00400000) ? 'S' : 'C');
10431
10432
1.61k
        if (given & 0x80000)
10433
476
          func (stream, dis_style_register, "f");
10434
1.61k
        if (given & 0x40000)
10435
934
          func (stream, dis_style_register, "s");
10436
1.61k
        if (given & 0x20000)
10437
1.06k
          func (stream, dis_style_register, "x");
10438
1.61k
        if (given & 0x10000)
10439
1.08k
          func (stream, dis_style_register, "c");
10440
1.61k
      }
10441
2.76k
          break;
10442
10443
651
        case 'U':
10444
651
          if ((given & 0xf0) == 0x60)
10445
263
      {
10446
263
        switch (given & 0xf)
10447
263
          {
10448
69
          case 0xf:
10449
69
            func (stream, dis_style_sub_mnemonic, "sy");
10450
69
            break;
10451
194
          default:
10452
194
            func (stream, dis_style_immediate, "#%d",
10453
194
            (int) given & 0xf);
10454
194
            break;
10455
263
          }
10456
263
      }
10457
388
          else
10458
388
      {
10459
388
        const char * opt = data_barrier_option (given & 0xf);
10460
388
        if (opt != NULL)
10461
194
          func (stream, dis_style_sub_mnemonic, "%s", opt);
10462
194
        else
10463
194
          func (stream, dis_style_immediate,
10464
194
          "#%d", (int) given & 0xf);
10465
388
      }
10466
651
          break;
10467
10468
2.75M
        case '0': case '1': case '2': case '3': case '4':
10469
2.78M
        case '5': case '6': case '7': case '8': case '9':
10470
2.78M
          {
10471
2.78M
      int width;
10472
2.78M
      unsigned long value;
10473
10474
2.78M
      c = arm_decode_bitfield (c, given, &value, &width);
10475
10476
2.78M
      switch (*c)
10477
2.78M
        {
10478
380k
        case 'R':
10479
380k
          if (value == 15)
10480
23.6k
            is_unpredictable = true;
10481
          /* Fall through.  */
10482
1.48M
        case 'r':
10483
1.48M
        case 'T':
10484
          /* We want register + 1 when decoding T.  */
10485
1.48M
          if (*c == 'T')
10486
194
            value = (value + 1) & 0xf;
10487
10488
1.48M
          if (c[1] == 'u')
10489
6.92k
            {
10490
        /* Eat the 'u' character.  */
10491
6.92k
        ++ c;
10492
10493
6.92k
        if (u_reg == value)
10494
522
          is_unpredictable = true;
10495
6.92k
        u_reg = value;
10496
6.92k
            }
10497
1.48M
          if (c[1] == 'U')
10498
1.18k
            {
10499
        /* Eat the 'U' character.  */
10500
1.18k
        ++ c;
10501
10502
1.18k
        if (U_reg == value)
10503
336
          is_unpredictable = true;
10504
1.18k
        U_reg = value;
10505
1.18k
            }
10506
1.48M
          func (stream, dis_style_register, "%s",
10507
1.48M
          arm_regnames[value]);
10508
1.48M
          break;
10509
1.31k
        case 'd':
10510
1.31k
          func (stream, base_style, "%ld", value);
10511
1.31k
          value_in_comment = value;
10512
1.31k
          break;
10513
0
        case 'b':
10514
0
          func (stream, dis_style_immediate,
10515
0
          "%ld", value * 8);
10516
0
          value_in_comment = value * 8;
10517
0
          break;
10518
693
        case 'W':
10519
693
          func (stream, dis_style_immediate,
10520
693
          "%ld", value + 1);
10521
693
          value_in_comment = value + 1;
10522
693
          break;
10523
240k
        case 'x':
10524
240k
          func (stream, dis_style_immediate,
10525
240k
          "0x%08lx", value);
10526
10527
          /* Some SWI instructions have special
10528
             meanings.  */
10529
240k
          if ((given & 0x0fffffff) == 0x0FF00000)
10530
231
            func (stream, dis_style_comment_start,
10531
231
            "\t@ IMB");
10532
240k
          else if ((given & 0x0fffffff) == 0x0FF00001)
10533
202
            func (stream, dis_style_comment_start,
10534
202
            "\t@ IMBRange");
10535
240k
          break;
10536
276
        case 'X':
10537
276
          func (stream, dis_style_immediate,
10538
276
          "%01lx", value & 0xf);
10539
276
          value_in_comment = value;
10540
276
          break;
10541
0
        case '`':
10542
0
          c++;
10543
0
          if (value == 0)
10544
0
            func (stream, dis_style_text, "%c", *c);
10545
0
          break;
10546
859k
        case '\'':
10547
859k
          c++;
10548
859k
          if (value == ((1ul << width) - 1))
10549
243k
            func (stream, base_style, "%c", *c);
10550
859k
          break;
10551
202k
        case '?':
10552
202k
          func (stream, base_style, "%c",
10553
202k
          c[(1 << width) - (int) value]);
10554
202k
          c += 1 << width;
10555
202k
          break;
10556
0
        default:
10557
0
          abort ();
10558
2.78M
        }
10559
2.78M
          }
10560
2.78M
          break;
10561
10562
2.78M
        case 'e':
10563
751
          {
10564
751
      int imm;
10565
10566
751
      imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10567
751
      func (stream, dis_style_immediate, "%d", imm);
10568
751
      value_in_comment = imm;
10569
751
          }
10570
751
          break;
10571
10572
477
        case 'E':
10573
          /* LSB and WIDTH fields of BFI or BFC.  The machine-
10574
       language instruction encodes LSB and MSB.  */
10575
477
          {
10576
477
      long msb = (given & 0x001f0000) >> 16;
10577
477
      long lsb = (given & 0x00000f80) >> 7;
10578
477
      long w = msb - lsb + 1;
10579
10580
477
      if (w > 0)
10581
279
        {
10582
279
          func (stream, dis_style_immediate, "#%lu", lsb);
10583
279
          func (stream, dis_style_text, ", ");
10584
279
          func (stream, dis_style_immediate, "#%lu", w);
10585
279
        }
10586
198
      else
10587
198
        func (stream, dis_style_text,
10588
198
        "(invalid: %lu:%lu)", lsb, msb);
10589
477
          }
10590
477
          break;
10591
10592
13.8k
        case 'R':
10593
          /* Get the PSR/banked register name.  */
10594
13.8k
          {
10595
13.8k
      const char * name;
10596
13.8k
      unsigned sysm = (given & 0x004f0000) >> 16;
10597
10598
13.8k
      sysm |= (given & 0x300) >> 4;
10599
13.8k
      name = banked_regname (sysm);
10600
10601
13.8k
      if (name != NULL)
10602
1.30k
        func (stream, dis_style_register, "%s", name);
10603
12.5k
      else
10604
12.5k
        func (stream, dis_style_text,
10605
12.5k
        "(UNDEF: %lu)", (unsigned long) sysm);
10606
13.8k
          }
10607
13.8k
          break;
10608
10609
3.48k
        case 'V':
10610
          /* 16-bit unsigned immediate from a MOVT or MOVW
10611
       instruction, encoded in bits 0:11 and 15:19.  */
10612
3.48k
          {
10613
3.48k
      long hi = (given & 0x000f0000) >> 4;
10614
3.48k
      long lo = (given & 0x00000fff);
10615
3.48k
      long imm16 = hi | lo;
10616
10617
3.48k
      func (stream, dis_style_immediate, "#%lu", imm16);
10618
3.48k
      value_in_comment = imm16;
10619
3.48k
          }
10620
3.48k
          break;
10621
10622
0
        default:
10623
0
          abort ();
10624
5.12M
        }
10625
5.12M
    }
10626
12.7M
        else
10627
12.7M
    {
10628
10629
12.7M
      if (*c == '@')
10630
191k
        base_style = dis_style_comment_start;
10631
10632
12.7M
      if (*c == '\t')
10633
1.44M
        base_style = dis_style_text;
10634
10635
12.7M
      func (stream, base_style, "%c", *c);
10636
12.7M
    }
10637
17.8M
      }
10638
10639
1.25M
    if (value_in_comment > 32 || value_in_comment < -16)
10640
186k
      func (stream, dis_style_comment_start, "\t@ 0x%lx",
10641
186k
      (value_in_comment & 0xffffffffUL));
10642
10643
1.25M
    if (is_unpredictable)
10644
41.5k
      func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
10645
10646
1.25M
    return;
10647
1.25M
  }
10648
1.36M
    }
10649
1.23k
  func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
10650
1.23k
  (unsigned) given);
10651
1.23k
  return;
10652
1.25M
}
10653
10654
/* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
10655
10656
static void
10657
print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
10658
2.00M
{
10659
2.00M
  const struct opcode16 *insn;
10660
2.00M
  void *stream = info->stream;
10661
2.00M
  fprintf_styled_ftype func = info->fprintf_styled_func;
10662
2.00M
  enum disassembler_style base_style = dis_style_mnemonic;
10663
2.00M
  enum disassembler_style old_base_style = base_style;
10664
10665
134M
  for (insn = thumb_opcodes; insn->assembler; insn++)
10666
134M
    if ((given & insn->mask) == insn->value)
10667
2.00M
      {
10668
2.00M
  signed long value_in_comment = 0;
10669
2.00M
  const char *c = insn->assembler;
10670
10671
29.8M
  for (; *c; c++)
10672
27.8M
    {
10673
27.8M
      int domaskpc = 0;
10674
27.8M
      int domasklr = 0;
10675
10676
27.8M
      if (*c != '%')
10677
18.1M
        {
10678
18.1M
    if (*c == '@')
10679
109k
      base_style = dis_style_comment_start;
10680
10681
18.1M
    if (*c == '\t')
10682
2.08M
      base_style = dis_style_text;
10683
10684
18.1M
    func (stream, base_style, "%c", *c);
10685
10686
18.1M
    continue;
10687
18.1M
        }
10688
10689
9.64M
      switch (*++c)
10690
9.64M
        {
10691
1.30M
    case '{':
10692
1.30M
      ++c;
10693
1.30M
      if (*c == '\0')
10694
0
        abort ();
10695
1.30M
      old_base_style = base_style;
10696
1.30M
      base_style = decode_base_style (*c);
10697
1.30M
      ++c;
10698
1.30M
      if (*c != ':')
10699
0
        abort ();
10700
1.30M
      break;
10701
10702
1.30M
    case '}':
10703
1.30M
      base_style = old_base_style;
10704
1.30M
      break;
10705
10706
0
        case '%':
10707
0
    func (stream, base_style, "%%");
10708
0
    break;
10709
10710
967k
        case 'c':
10711
967k
    if (ifthen_state)
10712
22.8k
      func (stream, dis_style_mnemonic, "%s",
10713
22.8k
      arm_conditional[IFTHEN_COND]);
10714
967k
    break;
10715
10716
916k
        case 'C':
10717
916k
    if (ifthen_state)
10718
23.2k
      func (stream, dis_style_mnemonic, "%s",
10719
23.2k
      arm_conditional[IFTHEN_COND]);
10720
893k
    else
10721
893k
      func (stream, dis_style_mnemonic, "s");
10722
916k
    break;
10723
10724
31.1k
        case 'I':
10725
31.1k
    {
10726
31.1k
      unsigned int tmp;
10727
10728
31.1k
      ifthen_next_state = given & 0xff;
10729
118k
      for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10730
87.2k
        func (stream, dis_style_mnemonic,
10731
87.2k
        ((given ^ tmp) & 0x10) ? "e" : "t");
10732
31.1k
      func (stream, dis_style_text, "\t");
10733
31.1k
      func (stream, dis_style_sub_mnemonic, "%s",
10734
31.1k
      arm_conditional[(given >> 4) & 0xf]);
10735
31.1k
    }
10736
31.1k
    break;
10737
10738
66.1k
        case 'x':
10739
66.1k
    if (ifthen_next_state)
10740
1.80k
      func (stream, dis_style_comment_start,
10741
1.80k
      "\t@ unpredictable branch in IT block\n");
10742
66.1k
    break;
10743
10744
101k
        case 'X':
10745
101k
    if (ifthen_state)
10746
16.9k
      func (stream, dis_style_comment_start,
10747
16.9k
      "\t@ unpredictable <IT:%s>",
10748
16.9k
      arm_conditional[IFTHEN_COND]);
10749
101k
    break;
10750
10751
18.8k
        case 'S':
10752
18.8k
    {
10753
18.8k
      long reg;
10754
10755
18.8k
      reg = (given >> 3) & 0x7;
10756
18.8k
      if (given & (1 << 6))
10757
13.8k
        reg += 8;
10758
10759
18.8k
      func (stream, dis_style_register, "%s", arm_regnames[reg]);
10760
18.8k
    }
10761
18.8k
    break;
10762
10763
15.1k
        case 'D':
10764
15.1k
    {
10765
15.1k
      long reg;
10766
10767
15.1k
      reg = given & 0x7;
10768
15.1k
      if (given & (1 << 7))
10769
5.58k
        reg += 8;
10770
10771
15.1k
      func (stream, dis_style_register, "%s", arm_regnames[reg]);
10772
15.1k
    }
10773
15.1k
    break;
10774
10775
7.12k
        case 'N':
10776
7.12k
    if (given & (1 << 8))
10777
4.90k
      domasklr = 1;
10778
    /* Fall through.  */
10779
12.9k
        case 'O':
10780
12.9k
    if (*c == 'O' && (given & (1 << 8)))
10781
3.56k
      domaskpc = 1;
10782
    /* Fall through.  */
10783
117k
        case 'M':
10784
117k
    {
10785
117k
      int started = 0;
10786
117k
      int reg;
10787
10788
117k
      func (stream, dis_style_text, "{");
10789
10790
      /* It would be nice if we could spot
10791
         ranges, and generate the rS-rE format: */
10792
1.05M
      for (reg = 0; (reg < 8); reg++)
10793
939k
        if ((given & (1 << reg)) != 0)
10794
488k
          {
10795
488k
      if (started)
10796
381k
        func (stream, dis_style_text, ", ");
10797
488k
      started = 1;
10798
488k
      func (stream, dis_style_register, "%s",
10799
488k
            arm_regnames[reg]);
10800
488k
          }
10801
10802
117k
      if (domasklr)
10803
4.90k
        {
10804
4.90k
          if (started)
10805
4.22k
      func (stream, dis_style_text, ", ");
10806
4.90k
          started = 1;
10807
4.90k
          func (stream, dis_style_register, "%s",
10808
4.90k
          arm_regnames[14] /* "lr" */);
10809
4.90k
        }
10810
10811
117k
      if (domaskpc)
10812
3.56k
        {
10813
3.56k
          if (started)
10814
3.12k
      func (stream, dis_style_text, ", ");
10815
3.56k
          func (stream, dis_style_register, "%s",
10816
3.56k
          arm_regnames[15] /* "pc" */);
10817
3.56k
        }
10818
10819
117k
      func (stream, dis_style_text, "}");
10820
117k
    }
10821
117k
    break;
10822
10823
57.6k
        case 'W':
10824
    /* Print writeback indicator for a LDMIA.  We are doing a
10825
       writeback if the base register is not in the register
10826
       mask.  */
10827
57.6k
    if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10828
28.4k
      func (stream, dis_style_text, "!");
10829
57.6k
    break;
10830
10831
19.3k
        case 'b':
10832
    /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
10833
19.3k
    {
10834
19.3k
      bfd_vma address = (pc + 4
10835
19.3k
             + ((given & 0x00f8) >> 2)
10836
19.3k
             + ((given & 0x0200) >> 3));
10837
19.3k
      info->print_address_func (address, info);
10838
10839
      /* Fill in instruction information.  */
10840
19.3k
      info->insn_info_valid = 1;
10841
19.3k
      info->insn_type = dis_branch;
10842
19.3k
      info->target = address;
10843
19.3k
    }
10844
19.3k
    break;
10845
10846
118k
        case 's':
10847
    /* Right shift immediate -- bits 6..10; 1-31 print
10848
       as themselves, 0 prints as 32.  */
10849
118k
    {
10850
118k
      long imm = (given & 0x07c0) >> 6;
10851
118k
      if (imm == 0)
10852
12.1k
        imm = 32;
10853
118k
      func (stream, dis_style_immediate, "#%ld", imm);
10854
118k
    }
10855
118k
    break;
10856
10857
3.20M
        case '0': case '1': case '2': case '3': case '4':
10858
4.61M
        case '5': case '6': case '7': case '8': case '9':
10859
4.61M
    {
10860
4.61M
      int bitstart = *c++ - '0';
10861
4.61M
      int bitend = 0;
10862
10863
4.67M
      while (*c >= '0' && *c <= '9')
10864
59.5k
        bitstart = (bitstart * 10) + *c++ - '0';
10865
10866
4.61M
      switch (*c)
10867
4.61M
        {
10868
4.55M
        case '-':
10869
4.55M
          {
10870
4.55M
      bfd_vma reg;
10871
10872
4.55M
      c++;
10873
10.4M
      while (*c >= '0' && *c <= '9')
10874
5.89M
        bitend = (bitend * 10) + *c++ - '0';
10875
4.55M
      if (!bitend)
10876
0
        abort ();
10877
4.55M
      reg = given >> bitstart;
10878
4.55M
      reg &= ((bfd_vma) 2 << (bitend - bitstart)) - 1;
10879
10880
4.55M
      switch (*c)
10881
4.55M
        {
10882
3.18M
        case 'r':
10883
3.18M
          func (stream, dis_style_register, "%s",
10884
3.18M
          arm_regnames[reg]);
10885
3.18M
          break;
10886
10887
603k
        case 'd':
10888
603k
          func (stream, dis_style_immediate, "%ld",
10889
603k
          (long) reg);
10890
603k
          value_in_comment = reg;
10891
603k
          break;
10892
10893
122k
        case 'H':
10894
122k
          func (stream, dis_style_immediate, "%ld",
10895
122k
          (long) (reg << 1));
10896
122k
          value_in_comment = reg << 1;
10897
122k
          break;
10898
10899
363k
        case 'W':
10900
363k
          func (stream, dis_style_immediate, "%ld",
10901
363k
          (long) (reg << 2));
10902
363k
          value_in_comment = reg << 2;
10903
363k
          break;
10904
10905
96.9k
        case 'a':
10906
          /* PC-relative address -- the bottom two
10907
             bits of the address are dropped
10908
             before the calculation.  */
10909
96.9k
          info->print_address_func
10910
96.9k
            (((pc + 4) & ~3) + (reg << 2), info);
10911
96.9k
          value_in_comment = 0;
10912
96.9k
          break;
10913
10914
19.7k
        case 'x':
10915
19.7k
          func (stream, dis_style_immediate, "0x%04lx",
10916
19.7k
          (long) reg);
10917
19.7k
          break;
10918
10919
113k
        case 'B':
10920
113k
          reg = ((reg ^ (1 << bitend)) - (1 << bitend));
10921
113k
          bfd_vma target = reg * 2 + pc + 4;
10922
113k
          info->print_address_func (target, info);
10923
113k
          value_in_comment = 0;
10924
10925
          /* Fill in instruction information.  */
10926
113k
          info->insn_info_valid = 1;
10927
113k
          info->insn_type = dis_branch;
10928
113k
          info->target = target;
10929
113k
          break;
10930
10931
50.7k
        case 'c':
10932
50.7k
          func (stream, dis_style_mnemonic, "%s",
10933
50.7k
          arm_conditional [reg]);
10934
50.7k
          break;
10935
10936
0
        default:
10937
0
          abort ();
10938
4.55M
        }
10939
4.55M
          }
10940
4.55M
          break;
10941
10942
4.55M
        case '\'':
10943
41.1k
          c++;
10944
41.1k
          if ((given & (1 << bitstart)) != 0)
10945
20.5k
      func (stream, base_style, "%c", *c);
10946
41.1k
          break;
10947
10948
19.5k
        case '?':
10949
19.5k
          ++c;
10950
19.5k
          if ((given & (1 << bitstart)) != 0)
10951
14.5k
      func (stream, base_style, "%c", *c++);
10952
5.01k
          else
10953
5.01k
      func (stream, base_style, "%c", *++c);
10954
19.5k
          break;
10955
10956
0
        default:
10957
0
          abort ();
10958
4.61M
        }
10959
4.61M
    }
10960
4.61M
    break;
10961
10962
4.61M
        default:
10963
0
    abort ();
10964
9.64M
        }
10965
9.64M
    }
10966
10967
2.00M
  if (value_in_comment > 32 || value_in_comment < -16)
10968
476k
    func (stream, dis_style_comment_start,
10969
476k
    "\t@ 0x%lx", value_in_comment);
10970
2.00M
  return;
10971
2.00M
      }
10972
10973
  /* No match.  */
10974
0
  func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_16BIT,
10975
0
  (unsigned) given);
10976
0
  return;
10977
2.00M
}
10978
10979
/* Return the name of an V7M special register.  */
10980
10981
static const char *
10982
psr_name (int regno)
10983
15.9k
{
10984
15.9k
  switch (regno)
10985
15.9k
    {
10986
360
    case 0x0: return "APSR";
10987
335
    case 0x1: return "IAPSR";
10988
494
    case 0x2: return "EAPSR";
10989
230
    case 0x3: return "PSR";
10990
303
    case 0x5: return "IPSR";
10991
298
    case 0x6: return "EPSR";
10992
226
    case 0x7: return "IEPSR";
10993
707
    case 0x8: return "MSP";
10994
305
    case 0x9: return "PSP";
10995
588
    case 0xa: return "MSPLIM";
10996
440
    case 0xb: return "PSPLIM";
10997
368
    case 0x10: return "PRIMASK";
10998
293
    case 0x11: return "BASEPRI";
10999
197
    case 0x12: return "BASEPRI_MAX";
11000
395
    case 0x13: return "FAULTMASK";
11001
381
    case 0x14: return "CONTROL";
11002
232
    case 0x20: return "PAC_KEY_P_0";
11003
258
    case 0x21: return "PAC_KEY_P_1";
11004
234
    case 0x22: return "PAC_KEY_P_2";
11005
201
    case 0x23: return "PAC_KEY_P_3";
11006
216
    case 0x24: return "PAC_KEY_U_0";
11007
218
    case 0x25: return "PAC_KEY_U_1";
11008
288
    case 0x26: return "PAC_KEY_U_2";
11009
202
    case 0x27: return "PAC_KEY_U_3";
11010
224
    case 0x88: return "MSP_NS";
11011
362
    case 0x89: return "PSP_NS";
11012
356
    case 0x8a: return "MSPLIM_NS";
11013
550
    case 0x8b: return "PSPLIM_NS";
11014
304
    case 0x90: return "PRIMASK_NS";
11015
318
    case 0x91: return "BASEPRI_NS";
11016
212
    case 0x93: return "FAULTMASK_NS";
11017
391
    case 0x94: return "CONTROL_NS";
11018
226
    case 0x98: return "SP_NS";
11019
1.15k
    case 0xa0: return "PAC_KEY_P_0_NS";
11020
251
    case 0xa1: return "PAC_KEY_P_1_NS";
11021
388
    case 0xa2: return "PAC_KEY_P_2_NS";
11022
222
    case 0xa3: return "PAC_KEY_P_3_NS";
11023
238
    case 0xa4: return "PAC_KEY_U_0_NS";
11024
260
    case 0xa5: return "PAC_KEY_U_1_NS";
11025
236
    case 0xa6: return "PAC_KEY_U_2_NS";
11026
270
    case 0xa7: return "PAC_KEY_U_3_NS";
11027
2.24k
    default: return "<unknown>";
11028
15.9k
    }
11029
15.9k
}
11030
11031
/* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
11032
11033
static void
11034
print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
11035
623k
{
11036
623k
  const struct opcode32 *insn;
11037
623k
  void *stream = info->stream;
11038
623k
  fprintf_styled_ftype func = info->fprintf_styled_func;
11039
623k
  bool is_mve = is_v81m_architecture (info);
11040
623k
  enum disassembler_style base_style = dis_style_mnemonic;
11041
623k
  enum disassembler_style old_base_style = base_style;
11042
11043
623k
  if (print_insn_coprocessor (pc, info, given, true))
11044
22.6k
    return;
11045
11046
600k
  if (!is_mve && print_insn_neon (info, given, true))
11047
35.7k
    return;
11048
11049
564k
  if (is_mve && print_insn_mve (info, given))
11050
139k
    return;
11051
11052
424k
  if (print_insn_cde (info, given, true))
11053
5.79k
    return;
11054
11055
419k
  if (print_insn_generic_coprocessor (pc, info, given, true))
11056
51.1k
    return;
11057
11058
84.6M
  for (insn = thumb32_opcodes; insn->assembler; insn++)
11059
84.6M
    if ((given & insn->mask) == insn->value)
11060
367k
      {
11061
367k
  bool is_clrm = false;
11062
367k
  bool is_unpredictable = false;
11063
367k
  signed long value_in_comment = 0;
11064
367k
  const char *c = insn->assembler;
11065
11066
9.24M
  for (; *c; c++)
11067
8.87M
    {
11068
8.87M
      if (*c != '%')
11069
8.17M
        {
11070
8.17M
    if (*c == '@')
11071
253k
      base_style = dis_style_comment_start;
11072
8.17M
    if (*c == '\t')
11073
619k
      base_style = dis_style_text;
11074
8.17M
    func (stream, base_style, "%c", *c);
11075
8.17M
    continue;
11076
8.17M
        }
11077
11078
697k
      switch (*++c)
11079
697k
        {
11080
11.6k
        case '{':
11081
11.6k
    ++c;
11082
11.6k
    if (*c == '\0')
11083
0
      abort ();
11084
11.6k
    old_base_style = base_style;
11085
11.6k
    base_style = decode_base_style (*c);
11086
11.6k
    ++c;
11087
11.6k
    if (*c != ':')
11088
0
      abort ();
11089
11.6k
    break;
11090
11091
11.6k
        case '}':
11092
11.6k
    base_style = old_base_style;
11093
11.6k
    break;
11094
11095
0
        case '%':
11096
0
    func (stream, base_style, "%%");
11097
0
    break;
11098
11099
103k
        case 'c':
11100
103k
    if (ifthen_state)
11101
2.99k
      func (stream, dis_style_mnemonic, "%s",
11102
2.99k
      arm_conditional[IFTHEN_COND]);
11103
103k
    break;
11104
11105
22.9k
        case 'x':
11106
22.9k
    if (ifthen_next_state)
11107
914
      func (stream, dis_style_comment_start,
11108
914
      "\t@ unpredictable branch in IT block\n");
11109
22.9k
    break;
11110
11111
6.23k
        case 'X':
11112
6.23k
    if (ifthen_state)
11113
412
      func (stream, dis_style_comment_start,
11114
412
      "\t@ unpredictable <IT:%s>",
11115
412
      arm_conditional[IFTHEN_COND]);
11116
6.23k
    break;
11117
11118
1.34k
        case 'I':
11119
1.34k
    {
11120
1.34k
      unsigned int imm12 = 0;
11121
11122
1.34k
      imm12 |= (given & 0x000000ffu);
11123
1.34k
      imm12 |= (given & 0x00007000u) >> 4;
11124
1.34k
      imm12 |= (given & 0x04000000u) >> 15;
11125
1.34k
      func (stream, dis_style_immediate, "#%u", imm12);
11126
1.34k
      value_in_comment = imm12;
11127
1.34k
    }
11128
1.34k
    break;
11129
11130
9.07k
        case 'M':
11131
9.07k
    {
11132
9.07k
      unsigned int bits = 0, imm, imm8, mod;
11133
11134
9.07k
      bits |= (given & 0x000000ffu);
11135
9.07k
      bits |= (given & 0x00007000u) >> 4;
11136
9.07k
      bits |= (given & 0x04000000u) >> 15;
11137
9.07k
      imm8 = (bits & 0x0ff);
11138
9.07k
      mod = (bits & 0xf00) >> 8;
11139
9.07k
      switch (mod)
11140
9.07k
        {
11141
1.37k
        case 0: imm = imm8; break;
11142
330
        case 1: imm = ((imm8 << 16) | imm8); break;
11143
381
        case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
11144
951
        case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
11145
6.04k
        default:
11146
6.04k
          mod  = (bits & 0xf80) >> 7;
11147
6.04k
          imm8 = (bits & 0x07f) | 0x80;
11148
6.04k
          imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
11149
9.07k
        }
11150
9.07k
      func (stream, dis_style_immediate, "#%u", imm);
11151
9.07k
      value_in_comment = imm;
11152
9.07k
    }
11153
0
    break;
11154
11155
477
        case 'J':
11156
477
    {
11157
477
      unsigned int imm = 0;
11158
11159
477
      imm |= (given & 0x000000ffu);
11160
477
      imm |= (given & 0x00007000u) >> 4;
11161
477
      imm |= (given & 0x04000000u) >> 15;
11162
477
      imm |= (given & 0x000f0000u) >> 4;
11163
477
      func (stream, dis_style_immediate, "#%u", imm);
11164
477
      value_in_comment = imm;
11165
477
    }
11166
477
    break;
11167
11168
289
        case 'K':
11169
289
    {
11170
289
      unsigned int imm = 0;
11171
11172
289
      imm |= (given & 0x000f0000u) >> 16;
11173
289
      imm |= (given & 0x00000ff0u) >> 0;
11174
289
      imm |= (given & 0x0000000fu) << 12;
11175
289
      func (stream, dis_style_immediate, "#%u", imm);
11176
289
      value_in_comment = imm;
11177
289
    }
11178
289
    break;
11179
11180
291
        case 'H':
11181
291
    {
11182
291
      unsigned int imm = 0;
11183
11184
291
      imm |= (given & 0x000f0000u) >> 4;
11185
291
      imm |= (given & 0x00000fffu) >> 0;
11186
291
      func (stream, dis_style_immediate, "#%u", imm);
11187
291
      value_in_comment = imm;
11188
291
    }
11189
291
    break;
11190
11191
255
        case 'V':
11192
255
    {
11193
255
      unsigned int imm = 0;
11194
11195
255
      imm |= (given & 0x00000fffu);
11196
255
      imm |= (given & 0x000f0000u) >> 4;
11197
255
      func (stream, dis_style_immediate, "#%u", imm);
11198
255
      value_in_comment = imm;
11199
255
    }
11200
255
    break;
11201
11202
5.51k
        case 'S':
11203
5.51k
    {
11204
5.51k
      unsigned int reg = (given & 0x0000000fu);
11205
5.51k
      unsigned int stp = (given & 0x00000030u) >> 4;
11206
5.51k
      unsigned int imm = 0;
11207
5.51k
      imm |= (given & 0x000000c0u) >> 6;
11208
5.51k
      imm |= (given & 0x00007000u) >> 10;
11209
11210
5.51k
      func (stream, dis_style_register, "%s", arm_regnames[reg]);
11211
5.51k
      switch (stp)
11212
5.51k
        {
11213
1.01k
        case 0:
11214
1.01k
          if (imm > 0)
11215
468
      {
11216
468
        func (stream, dis_style_text, ", ");
11217
468
        func (stream, dis_style_sub_mnemonic, "lsl ");
11218
468
        func (stream, dis_style_immediate, "#%u", imm);
11219
468
      }
11220
1.01k
          break;
11221
11222
1.18k
        case 1:
11223
1.18k
          if (imm == 0)
11224
422
      imm = 32;
11225
1.18k
          func (stream, dis_style_text, ", ");
11226
1.18k
          func (stream, dis_style_sub_mnemonic, "lsr ");
11227
1.18k
          func (stream, dis_style_immediate, "#%u", imm);
11228
1.18k
          break;
11229
11230
1.87k
        case 2:
11231
1.87k
          if (imm == 0)
11232
324
      imm = 32;
11233
1.87k
          func (stream, dis_style_text, ", ");
11234
1.87k
          func (stream, dis_style_sub_mnemonic, "asr ");
11235
1.87k
          func (stream, dis_style_immediate, "#%u", imm);
11236
1.87k
          break;
11237
11238
1.42k
        case 3:
11239
1.42k
          if (imm == 0)
11240
246
      {
11241
246
        func (stream, dis_style_text, ", ");
11242
246
        func (stream, dis_style_sub_mnemonic, "rrx");
11243
246
      }
11244
1.18k
          else
11245
1.18k
      {
11246
1.18k
        func (stream, dis_style_text, ", ");
11247
1.18k
        func (stream, dis_style_sub_mnemonic, "ror ");
11248
1.18k
        func (stream, dis_style_immediate, "#%u", imm);
11249
1.18k
      }
11250
5.51k
        }
11251
5.51k
    }
11252
5.51k
    break;
11253
11254
17.7k
        case 'a':
11255
17.7k
    {
11256
17.7k
      unsigned int Rn  = (given & 0x000f0000) >> 16;
11257
17.7k
      unsigned int U   = ! NEGATIVE_BIT_SET;
11258
17.7k
      unsigned int op  = (given & 0x00000f00) >> 8;
11259
17.7k
      unsigned int i12 = (given & 0x00000fff);
11260
17.7k
      unsigned int i8  = (given & 0x000000ff);
11261
17.7k
      bool writeback = false, postind = false;
11262
17.7k
      bfd_vma offset = 0;
11263
11264
17.7k
      func (stream, dis_style_text, "[");
11265
17.7k
      func (stream, dis_style_register, "%s", arm_regnames[Rn]);
11266
17.7k
      if (U) /* 12-bit positive immediate offset.  */
11267
10.4k
        {
11268
10.4k
          offset = i12;
11269
10.4k
          if (Rn != 15)
11270
8.10k
      value_in_comment = offset;
11271
10.4k
        }
11272
7.33k
      else if (Rn == 15) /* 12-bit negative immediate offset.  */
11273
822
        offset = - (int) i12;
11274
6.51k
      else if (op == 0x0) /* Shifted register offset.  */
11275
727
        {
11276
727
          unsigned int Rm = (i8 & 0x0f);
11277
727
          unsigned int sh = (i8 & 0x30) >> 4;
11278
11279
727
          func (stream, dis_style_text, ", ");
11280
727
          func (stream, dis_style_register, "%s",
11281
727
          arm_regnames[Rm]);
11282
727
          if (sh)
11283
354
      {
11284
354
        func (stream, dis_style_text, ", ");
11285
354
        func (stream, dis_style_sub_mnemonic, "lsl ");
11286
354
        func (stream, dis_style_immediate, "#%u", sh);
11287
354
      }
11288
727
          func (stream, dis_style_text, "]");
11289
727
          break;
11290
727
        }
11291
5.78k
      else switch (op)
11292
5.78k
        {
11293
391
        case 0xE:  /* 8-bit positive immediate offset.  */
11294
391
          offset = i8;
11295
391
          break;
11296
11297
708
        case 0xC:  /* 8-bit negative immediate offset.  */
11298
708
          offset = -i8;
11299
708
          break;
11300
11301
688
        case 0xF:  /* 8-bit + preindex with wb.  */
11302
688
          offset = i8;
11303
688
          writeback = true;
11304
688
          break;
11305
11306
568
        case 0xD:  /* 8-bit - preindex with wb.  */
11307
568
          offset = -i8;
11308
568
          writeback = true;
11309
568
          break;
11310
11311
834
        case 0xB:  /* 8-bit + postindex.  */
11312
834
          offset = i8;
11313
834
          postind = true;
11314
834
          break;
11315
11316
415
        case 0x9:  /* 8-bit - postindex.  */
11317
415
          offset = -i8;
11318
415
          postind = true;
11319
415
          break;
11320
11321
2.17k
        default:
11322
2.17k
          func (stream, dis_style_text, ", <undefined>]");
11323
2.17k
          goto skip;
11324
5.78k
        }
11325
11326
14.8k
      if (postind)
11327
1.24k
        {
11328
1.24k
          func (stream, dis_style_text, "], ");
11329
1.24k
          func (stream, dis_style_immediate, "#%d", (int) offset);
11330
1.24k
        }
11331
13.6k
      else
11332
13.6k
        {
11333
13.6k
          if (offset)
11334
12.4k
      {
11335
12.4k
        func (stream, dis_style_text, ", ");
11336
12.4k
        func (stream, dis_style_immediate, "#%d",
11337
12.4k
        (int) offset);
11338
12.4k
      }
11339
13.6k
          func (stream, dis_style_text, writeback ? "]!" : "]");
11340
13.6k
        }
11341
11342
14.8k
      if (Rn == 15)
11343
3.15k
        {
11344
3.15k
          func (stream, dis_style_comment_start, "\t@ ");
11345
3.15k
          info->print_address_func (((pc + 4) & ~3) + offset, info);
11346
3.15k
        }
11347
14.8k
    }
11348
17.0k
        skip:
11349
17.0k
    break;
11350
11351
0
        case 'A':
11352
0
    {
11353
0
      unsigned int U   = ! NEGATIVE_BIT_SET;
11354
0
      unsigned int W   = WRITEBACK_BIT_SET;
11355
0
      unsigned int Rn  = (given & 0x000f0000) >> 16;
11356
0
      unsigned int off = (given & 0x000000ff);
11357
11358
0
      func (stream, dis_style_text, "[");
11359
0
      func (stream, dis_style_register, "%s", arm_regnames[Rn]);
11360
11361
0
      if (PRE_BIT_SET)
11362
0
        {
11363
0
          if (off || !U)
11364
0
      {
11365
0
        func (stream, dis_style_text, ", ");
11366
0
        func (stream, dis_style_immediate, "#%c%u",
11367
0
        U ? '+' : '-', off * 4);
11368
0
        value_in_comment = off * 4 * (U ? 1 : -1);
11369
0
      }
11370
0
          func (stream, dis_style_text, "]");
11371
0
          if (W)
11372
0
      func (stream, dis_style_text, "!");
11373
0
        }
11374
0
      else
11375
0
        {
11376
0
          func (stream, dis_style_text, "], ");
11377
0
          if (W)
11378
0
      {
11379
0
        func (stream, dis_style_immediate, "#%c%u",
11380
0
        U ? '+' : '-', off * 4);
11381
0
        value_in_comment = off * 4 * (U ? 1 : -1);
11382
0
      }
11383
0
          else
11384
0
      {
11385
0
        func (stream, dis_style_text, "{");
11386
0
        func (stream, dis_style_immediate, "%u", off);
11387
0
        func (stream, dis_style_text, "}");
11388
0
        value_in_comment = off;
11389
0
      }
11390
0
        }
11391
0
    }
11392
0
    break;
11393
11394
17.2k
        case 'w':
11395
17.2k
    {
11396
17.2k
      unsigned int Sbit = (given & 0x01000000) >> 24;
11397
17.2k
      unsigned int type = (given & 0x00600000) >> 21;
11398
11399
17.2k
      switch (type)
11400
17.2k
        {
11401
3.60k
        case 0:
11402
3.60k
          func (stream, dis_style_mnemonic, Sbit ? "sb" : "b");
11403
3.60k
          break;
11404
1.85k
        case 1:
11405
1.85k
          func (stream, dis_style_mnemonic, Sbit ? "sh" : "h");
11406
1.85k
          break;
11407
2.53k
        case 2:
11408
2.53k
          if (Sbit)
11409
826
      func (stream, dis_style_text, "??");
11410
2.53k
          break;
11411
9.23k
        case 3:
11412
9.23k
          func (stream, dis_style_text, "??");
11413
9.23k
          break;
11414
17.2k
        }
11415
17.2k
    }
11416
17.2k
    break;
11417
11418
17.2k
        case 'n':
11419
394
    is_clrm = true;
11420
    /* Fall through.  */
11421
3.09k
        case 'm':
11422
3.09k
    {
11423
3.09k
      int started = 0;
11424
3.09k
      int reg;
11425
11426
3.09k
      func (stream, dis_style_text, "{");
11427
52.6k
      for (reg = 0; reg < 16; reg++)
11428
49.5k
        if ((given & (1 << reg)) != 0)
11429
23.3k
          {
11430
23.3k
      if (started)
11431
20.3k
        func (stream, dis_style_text, ", ");
11432
23.3k
      started = 1;
11433
23.3k
      if (is_clrm && reg == 13)
11434
0
        func (stream, dis_style_text, "(invalid: %s)",
11435
0
        arm_regnames[reg]);
11436
23.3k
      else if (is_clrm && reg == 15)
11437
333
        func (stream, dis_style_register, "%s", "APSR");
11438
23.0k
      else
11439
23.0k
        func (stream, dis_style_register, "%s",
11440
23.0k
        arm_regnames[reg]);
11441
23.3k
          }
11442
3.09k
      func (stream, dis_style_text, "}");
11443
3.09k
    }
11444
3.09k
    break;
11445
11446
496
        case 'E':
11447
496
    {
11448
496
      unsigned int msb = (given & 0x0000001f);
11449
496
      unsigned int lsb = 0;
11450
11451
496
      lsb |= (given & 0x000000c0u) >> 6;
11452
496
      lsb |= (given & 0x00007000u) >> 10;
11453
496
      func (stream, dis_style_immediate, "#%u", lsb);
11454
496
      func (stream, dis_style_text, ", ");
11455
496
      func (stream, dis_style_immediate, "#%u", msb - lsb + 1);
11456
496
    }
11457
496
    break;
11458
11459
336
        case 'F':
11460
336
    {
11461
336
      unsigned int width = (given & 0x0000001f) + 1;
11462
336
      unsigned int lsb = 0;
11463
11464
336
      lsb |= (given & 0x000000c0u) >> 6;
11465
336
      lsb |= (given & 0x00007000u) >> 10;
11466
336
      func (stream, dis_style_immediate, "#%u", lsb);
11467
336
      func (stream, dis_style_text, ", ");
11468
336
      func (stream, dis_style_immediate, "#%u", width);
11469
336
    }
11470
336
    break;
11471
11472
4.37k
        case 'G':
11473
4.37k
    {
11474
4.37k
      unsigned int boff = (((given & 0x07800000) >> 23) << 1);
11475
4.37k
      func (stream, dis_style_immediate, "%x", boff);
11476
4.37k
    }
11477
4.37k
    break;
11478
11479
685
        case 'W':
11480
685
    {
11481
685
      unsigned int immA = (given & 0x001f0000u) >> 16;
11482
685
      unsigned int immB = (given & 0x000007feu) >> 1;
11483
685
      unsigned int immC = (given & 0x00000800u) >> 11;
11484
685
      bfd_vma offset = 0;
11485
11486
685
      offset |= immA << 12;
11487
685
      offset |= immB << 2;
11488
685
      offset |= immC << 1;
11489
      /* Sign extend.  */
11490
685
      offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11491
11492
685
      info->print_address_func (pc + 4 + offset, info);
11493
685
    }
11494
685
    break;
11495
11496
1.93k
        case 'Y':
11497
1.93k
    {
11498
1.93k
      unsigned int immA = (given & 0x007f0000u) >> 16;
11499
1.93k
      unsigned int immB = (given & 0x000007feu) >> 1;
11500
1.93k
      unsigned int immC = (given & 0x00000800u) >> 11;
11501
1.93k
      bfd_vma offset = 0;
11502
11503
1.93k
      offset |= immA << 12;
11504
1.93k
      offset |= immB << 2;
11505
1.93k
      offset |= immC << 1;
11506
      /* Sign extend.  */
11507
1.93k
      offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11508
11509
1.93k
      info->print_address_func (pc + 4 + offset, info);
11510
1.93k
    }
11511
1.93k
    break;
11512
11513
1.65k
        case 'Z':
11514
1.65k
    {
11515
1.65k
      unsigned int immA = (given & 0x00010000u) >> 16;
11516
1.65k
      unsigned int immB = (given & 0x000007feu) >> 1;
11517
1.65k
      unsigned int immC = (given & 0x00000800u) >> 11;
11518
1.65k
      bfd_vma offset = 0;
11519
11520
1.65k
      offset |= immA << 12;
11521
1.65k
      offset |= immB << 2;
11522
1.65k
      offset |= immC << 1;
11523
      /* Sign extend.  */
11524
1.65k
      offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11525
11526
1.65k
      info->print_address_func (pc + 4 + offset, info);
11527
11528
1.65k
      unsigned int T    = (given & 0x00020000u) >> 17;
11529
1.65k
      unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11530
1.65k
      unsigned int boffset   = (T == 1) ? 4 : 2;
11531
1.65k
      func (stream, dis_style_text, ", ");
11532
1.65k
      func (stream, dis_style_immediate, "%x",
11533
1.65k
      endoffset + boffset);
11534
1.65k
    }
11535
1.65k
    break;
11536
11537
839
        case 'Q':
11538
839
    {
11539
839
      unsigned int immh = (given & 0x000007feu) >> 1;
11540
839
      unsigned int imml = (given & 0x00000800u) >> 11;
11541
839
      bfd_vma imm32 = 0;
11542
11543
839
      imm32 |= immh << 2;
11544
839
      imm32 |= imml << 1;
11545
11546
839
      info->print_address_func (pc + 4 + imm32, info);
11547
839
    }
11548
839
    break;
11549
11550
218
        case 'P':
11551
218
    {
11552
218
      unsigned int immh = (given & 0x000007feu) >> 1;
11553
218
      unsigned int imml = (given & 0x00000800u) >> 11;
11554
218
      bfd_vma imm32 = 0;
11555
11556
218
      imm32 |= immh << 2;
11557
218
      imm32 |= imml << 1;
11558
11559
218
      info->print_address_func (pc + 4 - imm32, info);
11560
218
    }
11561
218
    break;
11562
11563
5.97k
        case 'b':
11564
5.97k
    {
11565
5.97k
      unsigned int S = (given & 0x04000000u) >> 26;
11566
5.97k
      unsigned int J1 = (given & 0x00002000u) >> 13;
11567
5.97k
      unsigned int J2 = (given & 0x00000800u) >> 11;
11568
5.97k
      bfd_vma offset = 0;
11569
11570
5.97k
      offset |= !S << 20;
11571
5.97k
      offset |= J2 << 19;
11572
5.97k
      offset |= J1 << 18;
11573
5.97k
      offset |= (given & 0x003f0000) >> 4;
11574
5.97k
      offset |= (given & 0x000007ff) << 1;
11575
5.97k
      offset -= (1 << 20);
11576
11577
5.97k
      bfd_vma target = pc + 4 + offset;
11578
5.97k
      info->print_address_func (target, info);
11579
11580
      /* Fill in instruction information.  */
11581
5.97k
      info->insn_info_valid = 1;
11582
5.97k
      info->insn_type = dis_branch;
11583
5.97k
      info->target = target;
11584
5.97k
    }
11585
5.97k
    break;
11586
11587
22.9k
        case 'B':
11588
22.9k
    {
11589
22.9k
      unsigned int S = (given & 0x04000000u) >> 26;
11590
22.9k
      unsigned int I1 = (given & 0x00002000u) >> 13;
11591
22.9k
      unsigned int I2 = (given & 0x00000800u) >> 11;
11592
22.9k
      bfd_vma offset = 0;
11593
11594
22.9k
      offset |= !S << 24;
11595
22.9k
      offset |= !(I1 ^ S) << 23;
11596
22.9k
      offset |= !(I2 ^ S) << 22;
11597
22.9k
      offset |= (given & 0x03ff0000u) >> 4;
11598
22.9k
      offset |= (given & 0x000007ffu) << 1;
11599
22.9k
      offset -= (1 << 24);
11600
22.9k
      offset += pc + 4;
11601
11602
      /* BLX target addresses are always word aligned.  */
11603
22.9k
      if ((given & 0x00001000u) == 0)
11604
3.39k
          offset &= ~2u;
11605
11606
22.9k
      info->print_address_func (offset, info);
11607
11608
      /* Fill in instruction information.  */
11609
22.9k
      info->insn_info_valid = 1;
11610
22.9k
      info->insn_type = dis_branch;
11611
22.9k
      info->target = offset;
11612
22.9k
    }
11613
22.9k
    break;
11614
11615
1.94k
        case 's':
11616
1.94k
    {
11617
1.94k
      unsigned int shift = 0;
11618
11619
1.94k
      shift |= (given & 0x000000c0u) >> 6;
11620
1.94k
      shift |= (given & 0x00007000u) >> 10;
11621
1.94k
      if (WRITEBACK_BIT_SET)
11622
315
        {
11623
315
          func (stream, dis_style_text, ", ");
11624
315
          func (stream, dis_style_sub_mnemonic, "asr ");
11625
315
          func (stream, dis_style_immediate, "#%u", shift);
11626
315
        }
11627
1.63k
      else if (shift)
11628
901
        {
11629
901
          func (stream, dis_style_text, ", ");
11630
901
          func (stream, dis_style_sub_mnemonic, "lsl ");
11631
901
          func (stream, dis_style_immediate, "#%u", shift);
11632
901
        }
11633
      /* else print nothing - lsl #0 */
11634
1.94k
    }
11635
1.94k
    break;
11636
11637
540
        case 'R':
11638
540
    {
11639
540
      unsigned int rot = (given & 0x00000030) >> 4;
11640
11641
540
      if (rot)
11642
309
        {
11643
309
          func (stream, dis_style_text, ", ");
11644
309
          func (stream, dis_style_sub_mnemonic, "ror ");
11645
309
          func (stream, dis_style_immediate, "#%u", rot * 8);
11646
309
        }
11647
540
    }
11648
540
    break;
11649
11650
1.15k
        case 'U':
11651
1.15k
    if ((given & 0xf0) == 0x60)
11652
456
      {
11653
456
        switch (given & 0xf)
11654
456
          {
11655
235
          case 0xf:
11656
235
      func (stream, dis_style_sub_mnemonic, "sy");
11657
235
      break;
11658
221
          default:
11659
221
      func (stream, dis_style_immediate, "#%d",
11660
221
            (int) given & 0xf);
11661
221
      break;
11662
456
          }
11663
456
      }
11664
703
    else
11665
703
      {
11666
703
        const char * opt = data_barrier_option (given & 0xf);
11667
703
        if (opt != NULL)
11668
318
          func (stream, dis_style_sub_mnemonic, "%s", opt);
11669
385
        else
11670
385
          func (stream, dis_style_immediate, "#%d",
11671
385
          (int) given & 0xf);
11672
703
       }
11673
1.15k
    break;
11674
11675
11.2k
        case 'C':
11676
11.2k
    if ((given & 0xff) == 0)
11677
857
      {
11678
857
        func (stream, dis_style_register, "%cPSR_",
11679
857
        (given & 0x100000) ? 'S' : 'C');
11680
11681
857
        if (given & 0x800)
11682
367
          func (stream, dis_style_register, "f");
11683
857
        if (given & 0x400)
11684
332
          func (stream, dis_style_register, "s");
11685
857
        if (given & 0x200)
11686
388
          func (stream, dis_style_register, "x");
11687
857
        if (given & 0x100)
11688
422
          func (stream, dis_style_register, "c");
11689
857
      }
11690
10.4k
    else if (is_v81m_architecture (info))
11691
3.92k
      func (stream, dis_style_register, "%s",
11692
3.92k
      psr_name (given & 0xff));
11693
11694
6.48k
    else if ((given & 0x20) == 0x20)
11695
5.13k
      {
11696
5.13k
        char const* name;
11697
5.13k
        unsigned sysm = (given & 0xf00) >> 8;
11698
11699
5.13k
        sysm |= (given & 0x30);
11700
5.13k
        sysm |= (given & 0x00100000) >> 14;
11701
5.13k
        name = banked_regname (sysm);
11702
11703
5.13k
        if (name != NULL)
11704
4.36k
          func (stream, dis_style_register, "%s", name);
11705
764
        else
11706
764
          func (stream, dis_style_text,
11707
764
          "(UNDEF: %lu)", (unsigned long) sysm);
11708
5.13k
      }
11709
1.35k
    else
11710
1.35k
      {
11711
1.35k
        func (stream, dis_style_register, "%s",
11712
1.35k
        psr_name (given & 0xff));
11713
1.35k
      }
11714
11.2k
    break;
11715
11716
15.8k
        case 'D':
11717
15.8k
    if (is_v81m_architecture (info))
11718
6.21k
      func (stream, dis_style_register, "%s",
11719
6.21k
      psr_name (given & 0xff));
11720
9.59k
    else if (((given & 0xff) == 0)
11721
9.10k
       || ((given & 0x20) == 0x20))
11722
5.11k
      {
11723
5.11k
        char const* name;
11724
5.11k
        unsigned sm = (given & 0xf0000) >> 16;
11725
11726
5.11k
        sm |= (given & 0x30);
11727
5.11k
        sm |= (given & 0x00100000) >> 14;
11728
5.11k
        name = banked_regname (sm);
11729
11730
5.11k
        if (name != NULL)
11731
4.44k
          func (stream, dis_style_register, "%s", name);
11732
674
        else
11733
674
          func (stream, dis_style_text,
11734
674
          "(UNDEF: %lu)", (unsigned long) sm);
11735
5.11k
      }
11736
4.48k
    else
11737
4.48k
      func (stream, dis_style_register, "%s",
11738
4.48k
      psr_name (given & 0xff));
11739
15.8k
    break;
11740
11741
365k
        case '0': case '1': case '2': case '3': case '4':
11742
410k
        case '5': case '6': case '7': case '8': case '9':
11743
410k
    {
11744
410k
      int width;
11745
410k
      unsigned long val;
11746
11747
410k
      c = arm_decode_bitfield (c, given, &val, &width);
11748
11749
410k
      switch (*c)
11750
410k
        {
11751
834
        case 's':
11752
834
          if (val <= 3)
11753
834
      func (stream, dis_style_mnemonic, "%s",
11754
834
            mve_vec_sizename[val]);
11755
0
          else
11756
0
      func (stream, dis_style_text, "<undef size>");
11757
834
          break;
11758
11759
597
        case 'd':
11760
597
          func (stream, base_style, "%lu", val);
11761
597
          value_in_comment = val;
11762
597
          break;
11763
11764
1.46k
        case 'D':
11765
1.46k
          func (stream, dis_style_immediate, "%lu", val + 1);
11766
1.46k
          value_in_comment = val + 1;
11767
1.46k
          break;
11768
11769
6.00k
        case 'W':
11770
6.00k
          func (stream, dis_style_immediate, "%lu", val * 4);
11771
6.00k
          value_in_comment = val * 4;
11772
6.00k
          break;
11773
11774
940
        case 'S':
11775
940
          if (val == 13)
11776
432
      is_unpredictable = true;
11777
          /* Fall through.  */
11778
4.99k
        case 'R':
11779
4.99k
          if (val == 15)
11780
996
      is_unpredictable = true;
11781
          /* Fall through.  */
11782
111k
        case 'r':
11783
111k
          func (stream, dis_style_register, "%s",
11784
111k
          arm_regnames[val]);
11785
111k
          break;
11786
11787
7.63k
        case 'c':
11788
7.63k
          func (stream, base_style, "%s", arm_conditional[val]);
11789
7.63k
          break;
11790
11791
21.8k
        case '\'':
11792
21.8k
          c++;
11793
21.8k
          if (val == ((1ul << width) - 1))
11794
9.55k
      func (stream, base_style, "%c", *c);
11795
21.8k
          break;
11796
11797
5.93k
        case '`':
11798
5.93k
          c++;
11799
5.93k
          if (val == 0)
11800
1.17k
      func (stream, dis_style_immediate, "%c", *c);
11801
5.93k
          break;
11802
11803
1.10k
        case '?':
11804
1.10k
          func (stream, dis_style_mnemonic, "%c",
11805
1.10k
          c[(1 << width) - (int) val]);
11806
1.10k
          c += 1 << width;
11807
1.10k
          break;
11808
11809
253k
        case 'x':
11810
253k
          func (stream, dis_style_immediate, "0x%lx",
11811
253k
          val & 0xffffffffUL);
11812
253k
          break;
11813
11814
0
        default:
11815
0
          abort ();
11816
410k
        }
11817
410k
    }
11818
410k
    break;
11819
11820
410k
        case 'L':
11821
    /* PR binutils/12534
11822
       If we have a PC relative offset in an LDRD or STRD
11823
       instructions then display the decoded address.  */
11824
5.93k
    if (((given >> 16) & 0xf) == 0xf)
11825
1.51k
      {
11826
1.51k
        bfd_vma offset = (given & 0xff) * 4;
11827
11828
1.51k
        if ((given & (1 << 23)) == 0)
11829
419
          offset = - offset;
11830
1.51k
        func (stream, dis_style_comment_start, "\t@ ");
11831
1.51k
        info->print_address_func ((pc & ~3) + 4 + offset, info);
11832
1.51k
      }
11833
5.93k
    break;
11834
11835
0
        default:
11836
0
    abort ();
11837
697k
        }
11838
697k
    }
11839
11840
367k
  if (value_in_comment > 32 || value_in_comment < -16)
11841
23.8k
    func (stream, dis_style_comment_start, "\t@ 0x%lx",
11842
23.8k
    value_in_comment);
11843
11844
367k
  if (is_unpredictable)
11845
1.17k
    func (stream, dis_style_comment_start, UNPREDICTABLE_INSTRUCTION);
11846
11847
367k
  return;
11848
367k
      }
11849
11850
  /* No match.  */
11851
0
  func (stream, dis_style_comment_start, UNKNOWN_INSTRUCTION_32BIT,
11852
0
  (unsigned) given);
11853
0
  return;
11854
367k
}
11855
11856
/* Print data bytes on INFO->STREAM.  */
11857
11858
static void
11859
print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11860
     struct disassemble_info *info,
11861
     long given)
11862
0
{
11863
0
  fprintf_styled_ftype func = info->fprintf_styled_func;
11864
11865
0
  switch (info->bytes_per_chunk)
11866
0
    {
11867
0
    case 1:
11868
0
      func (info->stream, dis_style_assembler_directive, ".byte");
11869
0
      func (info->stream, dis_style_text, "\t");
11870
0
      func (info->stream, dis_style_immediate, "0x%02lx", given);
11871
0
      break;
11872
0
    case 2:
11873
0
      func (info->stream, dis_style_assembler_directive, ".short");
11874
0
      func (info->stream, dis_style_text, "\t");
11875
0
      func (info->stream, dis_style_immediate, "0x%04lx", given);
11876
0
      break;
11877
0
    case 4:
11878
0
      func (info->stream, dis_style_assembler_directive, ".word");
11879
0
      func (info->stream, dis_style_text, "\t");
11880
0
      func (info->stream, dis_style_immediate, "0x%08lx", given);
11881
0
      break;
11882
0
    default:
11883
0
      abort ();
11884
0
    }
11885
0
}
11886
11887
/* Disallow mapping symbols ($a, $b, $d, $t etc) from
11888
   being displayed in symbol relative addresses.
11889
11890
   Also disallow private symbol, with __tagsym$$ prefix,
11891
   from ARM RVCT toolchain being displayed.  */
11892
11893
bool
11894
arm_symbol_is_valid (asymbol * sym,
11895
         struct disassemble_info * info ATTRIBUTE_UNUSED)
11896
0
{
11897
0
  const char * name;
11898
11899
0
  if (sym == NULL)
11900
0
    return false;
11901
11902
0
  name = bfd_asymbol_name (sym);
11903
11904
0
  return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
11905
0
}
11906
11907
/* Parse a disassembler option.  */
11908
11909
static bool
11910
arm_parse_option (const char *opt, void *data ATTRIBUTE_UNUSED)
11911
20.1k
{
11912
20.1k
  if (startswith (opt, "reg-names-"))
11913
430
    {
11914
430
      unsigned int i;
11915
4.04k
      for (i = 0; i < NUM_ARM_OPTIONS; i++)
11916
3.65k
  if (strcmp (opt, regnames[i].name) == 0)
11917
38
    {
11918
38
      regname_selected = i;
11919
38
      break;
11920
38
    }
11921
11922
430
      if (i >= NUM_ARM_OPTIONS)
11923
  /* xgettext: c-format */
11924
392
  opcodes_error_handler (_("unrecognised register name set: %s"),
11925
392
             opt);
11926
430
    }
11927
19.6k
  else if (startswith (opt, "force-thumb"))
11928
3.13k
    force_thumb = 1;
11929
16.5k
  else if (startswith (opt, "no-force-thumb"))
11930
56
    force_thumb = 0;
11931
16.4k
  else if (startswith (opt, "coproc"))
11932
570
    {
11933
570
      const char *procptr = opt + sizeof ("coproc") - 1;
11934
570
      char *endptr;
11935
570
      uint8_t coproc_number = strtol (procptr, &endptr, 10);
11936
570
      if (endptr != procptr + 1 || coproc_number > 7)
11937
184
  opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
11938
184
             opt);
11939
386
      else if (*endptr != '=')
11940
90
  opcodes_error_handler (_("coproc must have an argument: %s"),
11941
90
             opt);
11942
296
      else
11943
296
  {
11944
296
    endptr += 1;
11945
296
    if (startswith (endptr, "generic"))
11946
28
      cde_coprocs &= ~(1 << coproc_number);
11947
268
    else if (startswith (endptr, "cde")
11948
246
       || startswith (endptr, "CDE"))
11949
70
      cde_coprocs |= (1 << coproc_number);
11950
198
    else
11951
198
      opcodes_error_handler
11952
198
        (_("coprocN argument takes options \"generic\","
11953
198
     " \"cde\", or \"CDE\": %s"), opt);
11954
296
  }
11955
570
    }
11956
15.9k
  else
11957
    /* xgettext: c-format */
11958
15.9k
    opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
11959
20.1k
  return true;
11960
20.1k
}
11961
11962
static bool
11963
mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11964
       enum map_type *map_symbol);
11965
11966
/* Search back through the insn stream to determine if this instruction is
11967
   conditionally executed.  */
11968
11969
static void
11970
find_ifthen_state (bfd_vma pc,
11971
       struct disassemble_info *info,
11972
       bool little)
11973
13.0k
{
11974
13.0k
  unsigned char b[2];
11975
13.0k
  unsigned int insn;
11976
13.0k
  int status;
11977
  /* COUNT is twice the number of instructions seen.  It will be odd if we
11978
     just crossed an instruction boundary.  */
11979
13.0k
  int count;
11980
13.0k
  int it_count;
11981
13.0k
  unsigned int seen_it;
11982
13.0k
  bfd_vma addr;
11983
11984
13.0k
  ifthen_address = pc;
11985
13.0k
  ifthen_state = 0;
11986
11987
13.0k
  addr = pc;
11988
13.0k
  count = 1;
11989
13.0k
  it_count = 0;
11990
13.0k
  seen_it = 0;
11991
  /* Scan backwards looking for IT instructions, keeping track of where
11992
     instruction boundaries are.  We don't know if something is actually an
11993
     IT instruction until we find a definite instruction boundary.  */
11994
13.0k
  for (;;)
11995
13.0k
    {
11996
13.0k
      if (addr == 0 || info->symbol_at_address_func (addr, info))
11997
0
  {
11998
    /* A symbol must be on an instruction boundary, and will not
11999
       be within an IT block.  */
12000
0
    if (seen_it && (count & 1))
12001
0
      break;
12002
12003
0
    return;
12004
0
  }
12005
13.0k
      addr -= 2;
12006
13.0k
      status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
12007
13.0k
      if (status)
12008
13.0k
  return;
12009
12010
0
      if (little)
12011
0
  insn = (b[0]) | (b[1] << 8);
12012
0
      else
12013
0
  insn = (b[1]) | (b[0] << 8);
12014
0
      if (seen_it)
12015
0
  {
12016
0
    if ((insn & 0xf800) < 0xe800)
12017
0
      {
12018
        /* Addr + 2 is an instruction boundary.  See if this matches
12019
           the expected boundary based on the position of the last
12020
     IT candidate.  */
12021
0
        if (count & 1)
12022
0
    break;
12023
0
        seen_it = 0;
12024
0
      }
12025
0
  }
12026
0
      if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
12027
0
  {
12028
0
    enum map_type type = MAP_ARM;
12029
0
    bool found = mapping_symbol_for_insn (addr, info, &type);
12030
12031
0
    if (!found || (found && type == MAP_THUMB))
12032
0
      {
12033
        /* This could be an IT instruction.  */
12034
0
        seen_it = insn;
12035
0
        it_count = count >> 1;
12036
0
      }
12037
0
  }
12038
0
      if ((insn & 0xf800) >= 0xe800)
12039
0
  count++;
12040
0
      else
12041
0
  count = (count + 2) | 1;
12042
      /* IT blocks contain at most 4 instructions.  */
12043
0
      if (count >= 8 && !seen_it)
12044
0
  return;
12045
0
    }
12046
  /* We found an IT instruction.  */
12047
0
  ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
12048
0
  if ((ifthen_state & 0xf) == 0)
12049
0
    ifthen_state = 0;
12050
0
}
12051
12052
/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
12053
   mapping symbol.  */
12054
12055
static int
12056
is_mapping_symbol (struct disassemble_info *info,
12057
       int n,
12058
       enum map_type *map_type)
12059
0
{
12060
0
  const char *name = bfd_asymbol_name (info->symtab[n]);
12061
12062
0
  if (name[0] == '$'
12063
0
      && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
12064
0
      && (name[2] == 0 || name[2] == '.'))
12065
0
    {
12066
0
      *map_type = ((name[1] == 'a') ? MAP_ARM
12067
0
       : (name[1] == 't') ? MAP_THUMB
12068
0
       : MAP_DATA);
12069
0
      return true;
12070
0
    }
12071
12072
0
  return false;
12073
0
}
12074
12075
/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
12076
   Returns nonzero if *MAP_TYPE was set.  */
12077
12078
static int
12079
get_map_sym_type (struct disassemble_info *info,
12080
      int n,
12081
      enum map_type *map_type)
12082
0
{
12083
  /* If the symbol is in a different section, ignore it.  */
12084
0
  if (info->section != NULL && info->section != info->symtab[n]->section)
12085
0
    return false;
12086
12087
0
  return is_mapping_symbol (info, n, map_type);
12088
0
}
12089
12090
/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
12091
   Returns nonzero if *MAP_TYPE was set.  */
12092
12093
static int
12094
get_sym_code_type (struct disassemble_info *info,
12095
       int n,
12096
       enum map_type *map_type)
12097
0
{
12098
0
  elf_symbol_type *es;
12099
0
  unsigned int type;
12100
0
  asymbol * sym;
12101
12102
  /* If the symbol is in a different section, ignore it.  */
12103
0
  if (info->section != NULL && info->section != info->symtab[n]->section)
12104
0
    return false;
12105
12106
  /* PR 30230: Reject non-ELF symbols, eg synthetic ones.  */
12107
0
  sym = info->symtab[n];
12108
0
  if (bfd_asymbol_flavour (sym) != bfd_target_elf_flavour)
12109
0
    return false;
12110
12111
0
  es = (elf_symbol_type *) sym;
12112
0
  type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12113
12114
  /* If the symbol has function type then use that.  */
12115
0
  if (type == STT_FUNC || type == STT_GNU_IFUNC)
12116
0
    {
12117
0
      if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12118
0
    == ST_BRANCH_TO_THUMB)
12119
0
  *map_type = MAP_THUMB;
12120
0
      else
12121
0
  *map_type = MAP_ARM;
12122
0
      return true;
12123
0
    }
12124
12125
0
  return false;
12126
0
}
12127
12128
/* Search the mapping symbol state for instruction at pc.  This is only
12129
   applicable for elf target.
12130
12131
   There is an assumption Here, info->private_data contains the correct AND
12132
   up-to-date information about current scan process.  The information will be
12133
   used to speed this search process.
12134
12135
   Return TRUE if the mapping state can be determined, and map_symbol
12136
   will be updated accordingly.  Otherwise, return FALSE.  */
12137
12138
static bool
12139
mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
12140
       enum map_type *map_symbol)
12141
0
{
12142
0
  bfd_vma addr, section_vma = 0;
12143
0
  int n, last_sym = -1;
12144
0
  bool found = false;
12145
0
  bool can_use_search_opt_p = false;
12146
12147
  /* Sanity check.  */
12148
0
  if (info == NULL)
12149
0
    return false;
12150
12151
  /* Default to DATA.  A text section is required by the ABI to contain an
12152
     INSN mapping symbol at the start.  A data section has no such
12153
     requirement, hence if no mapping symbol is found the section must
12154
     contain only data.  This however isn't very useful if the user has
12155
     fully stripped the binaries.  If this is the case use the section
12156
     attributes to determine the default.  If we have no section default to
12157
     INSN as well, as we may be disassembling some raw bytes on a baremetal
12158
     HEX file or similar.  */
12159
0
  enum map_type type = MAP_DATA;
12160
0
  if ((info->section && info->section->flags & SEC_CODE) || !info->section)
12161
0
    type = MAP_ARM;
12162
0
  struct arm_private_data *private_data;
12163
12164
0
  if (info->private_data == NULL || info->symtab == NULL
12165
0
      || info->symtab_size == 0
12166
0
      || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
12167
0
    return false;
12168
12169
0
  private_data = info->private_data;
12170
12171
  /* First, look for mapping symbols.  */
12172
0
  if (pc <= private_data->last_mapping_addr)
12173
0
    private_data->last_mapping_sym = -1;
12174
12175
  /* Start scanning at the start of the function, or wherever
12176
     we finished last time.  */
12177
0
  n = info->symtab_pos + 1;
12178
12179
  /* If the last stop offset is different from the current one it means we
12180
     are disassembling a different glob of bytes.  As such the optimization
12181
     would not be safe and we should start over.  */
12182
0
  can_use_search_opt_p
12183
0
    = (private_data->last_mapping_sym >= 0
12184
0
       && info->stop_offset == private_data->last_stop_offset);
12185
12186
0
  if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12187
0
    n = private_data->last_mapping_sym;
12188
12189
  /* Look down while we haven't passed the location being disassembled.
12190
     The reason for this is that there's no defined order between a symbol
12191
     and an mapping symbol that may be at the same address.  We may have to
12192
     look at least one position ahead.  */
12193
0
  for (; n < info->symtab_size; n++)
12194
0
    {
12195
0
      addr = bfd_asymbol_value (info->symtab[n]);
12196
0
      if (addr > pc)
12197
0
  break;
12198
0
      if (get_map_sym_type (info, n, &type))
12199
0
  {
12200
0
    last_sym = n;
12201
0
    found = true;
12202
0
  }
12203
0
    }
12204
12205
0
  if (!found)
12206
0
    {
12207
0
      n = info->symtab_pos;
12208
0
      if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
12209
0
  n = private_data->last_mapping_sym;
12210
12211
      /* No mapping symbol found at this address.  Look backwards
12212
   for a preceeding one, but don't go pass the section start
12213
   otherwise a data section with no mapping symbol can pick up
12214
   a text mapping symbol of a preceeding section.  The documentation
12215
   says section can be NULL, in which case we will seek up all the
12216
   way to the top.  */
12217
0
      if (info->section)
12218
0
  section_vma = info->section->vma;
12219
12220
0
      for (; n >= 0; n--)
12221
0
  {
12222
0
    addr = bfd_asymbol_value (info->symtab[n]);
12223
0
    if (addr < section_vma)
12224
0
      break;
12225
12226
0
    if (get_map_sym_type (info, n, &type))
12227
0
      {
12228
0
        last_sym = n;
12229
0
        found = true;
12230
0
        break;
12231
0
      }
12232
0
  }
12233
0
    }
12234
12235
  /* If no mapping symbol was found, try looking up without a mapping
12236
     symbol.  This is done by walking up from the current PC to the nearest
12237
     symbol.  We don't actually have to loop here since symtab_pos will
12238
     contain the nearest symbol already.  */
12239
0
  if (!found)
12240
0
    {
12241
0
      n = info->symtab_pos;
12242
0
      if (n >= 0 && get_sym_code_type (info, n, &type))
12243
0
  {
12244
0
    last_sym = n;
12245
0
    found = true;
12246
0
  }
12247
0
    }
12248
12249
0
  private_data->last_mapping_sym = last_sym;
12250
0
  private_data->last_type = type;
12251
0
  private_data->last_stop_offset = info->stop_offset;
12252
12253
0
  *map_symbol = type;
12254
0
  return found;
12255
0
}
12256
12257
/* Given a bfd_mach_arm_XXX value, this function fills in the fields
12258
   of the supplied arm_feature_set structure with bitmasks indicating
12259
   the supported base architectures and coprocessor extensions.
12260
12261
   FIXME: This could more efficiently implemented as a constant array,
12262
   although it would also be less robust.  */
12263
12264
static void
12265
select_arm_features (unsigned long mach,
12266
         arm_feature_set * features)
12267
17.0k
{
12268
17.0k
  arm_feature_set arch_fset;
12269
17.0k
  const arm_feature_set fpu_any = FPU_ANY;
12270
12271
17.0k
#undef ARM_SET_FEATURES
12272
17.0k
#define ARM_SET_FEATURES(FSET) \
12273
17.0k
  {             \
12274
17.0k
    const arm_feature_set fset = FSET;      \
12275
17.0k
    arch_fset = fset;         \
12276
17.0k
  }
12277
12278
  /* When several architecture versions share the same bfd_mach_arm_XXX value
12279
     the most featureful is chosen.  */
12280
17.0k
  switch (mach)
12281
17.0k
    {
12282
285
    case bfd_mach_arm_2:  ARM_SET_FEATURES (ARM_ARCH_V2); break;
12283
116
    case bfd_mach_arm_2a:  ARM_SET_FEATURES (ARM_ARCH_V2S); break;
12284
191
    case bfd_mach_arm_3:  ARM_SET_FEATURES (ARM_ARCH_V3); break;
12285
466
    case bfd_mach_arm_3M:  ARM_SET_FEATURES (ARM_ARCH_V3M); break;
12286
172
    case bfd_mach_arm_4:  ARM_SET_FEATURES (ARM_ARCH_V4); break;
12287
0
    case bfd_mach_arm_ep9312:
12288
38
    case bfd_mach_arm_4T:  ARM_SET_FEATURES (ARM_ARCH_V4T); break;
12289
227
    case bfd_mach_arm_5:  ARM_SET_FEATURES (ARM_ARCH_V5); break;
12290
189
    case bfd_mach_arm_5T:  ARM_SET_FEATURES (ARM_ARCH_V5T); break;
12291
193
    case bfd_mach_arm_5TE:  ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
12292
235
    case bfd_mach_arm_XScale:  ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
12293
362
    case bfd_mach_arm_iWMMXt:  ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
12294
595
    case bfd_mach_arm_iWMMXt2:  ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
12295
52
    case bfd_mach_arm_5TEJ:  ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
12296
89
    case bfd_mach_arm_6:  ARM_SET_FEATURES (ARM_ARCH_V6); break;
12297
146
    case bfd_mach_arm_6KZ:  ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
12298
76
    case bfd_mach_arm_6T2:  ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
12299
59
    case bfd_mach_arm_6K:  ARM_SET_FEATURES (ARM_ARCH_V6K); break;
12300
129
    case bfd_mach_arm_7:  ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
12301
78
    case bfd_mach_arm_6M:  ARM_SET_FEATURES (ARM_ARCH_V6M); break;
12302
76
    case bfd_mach_arm_6SM:  ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
12303
129
    case bfd_mach_arm_7EM:  ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
12304
33
    case bfd_mach_arm_8:
12305
33
  {
12306
    /* Add bits for extensions that Armv8.6-A recognizes.  */
12307
33
    arm_feature_set armv8_6_ext_fset
12308
33
      = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
12309
33
    ARM_SET_FEATURES (ARM_ARCH_V8_6A);
12310
33
    ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
12311
33
    break;
12312
0
  }
12313
41
    case bfd_mach_arm_8R:  ARM_SET_FEATURES (ARM_ARCH_V8R_CRC); break;
12314
64
    case bfd_mach_arm_8M_BASE:  ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
12315
40
    case bfd_mach_arm_8M_MAIN:  ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
12316
9.45k
    case bfd_mach_arm_8_1M_MAIN:
12317
9.45k
      ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
12318
9.45k
      arm_feature_set mve_all
12319
9.45k
  = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
12320
9.45k
      ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
12321
9.45k
      force_thumb = 1;
12322
9.45k
      break;
12323
66
    case bfd_mach_arm_9:         ARM_SET_FEATURES (ARM_ARCH_V9A); break;
12324
      /* If the machine type is unknown allow all architecture types and all
12325
   extensions, with the exception of MVE as that clashes with NEON.  */
12326
3.46k
    case bfd_mach_arm_unknown:
12327
3.46k
      ARM_SET_FEATURES (ARM_ARCH_UNKNOWN);
12328
3.46k
      break;
12329
0
    default:
12330
0
      abort ();
12331
17.0k
    }
12332
17.0k
#undef ARM_SET_FEATURES
12333
12334
  /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12335
     and thus on bfd_mach_arm_XXX value.  Therefore for a given
12336
     bfd_mach_arm_XXX value all coprocessor feature bits should be allowed.  */
12337
17.0k
  ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
12338
17.0k
}
12339
12340
12341
/* NOTE: There are no checks in these routines that
12342
   the relevant number of data bytes exist.  */
12343
12344
static int
12345
print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
12346
4.05M
{
12347
4.05M
  unsigned char b[4];
12348
4.05M
  unsigned long given;
12349
4.05M
  int status;
12350
4.05M
  int is_thumb = false;
12351
4.05M
  int is_data = false;
12352
4.05M
  int little_code;
12353
4.05M
  unsigned int  size = 4;
12354
4.05M
  void (*printer) (bfd_vma, struct disassemble_info *, long);
12355
4.05M
  bool found = false;
12356
4.05M
  struct arm_private_data *private_data;
12357
12358
  /* Clear instruction information field.  */
12359
4.05M
  info->insn_info_valid = 0;
12360
4.05M
  info->branch_delay_insns = 0;
12361
4.05M
  info->data_size = 0;
12362
4.05M
  info->insn_type = dis_noninsn;
12363
4.05M
  info->target = 0;
12364
4.05M
  info->target2 = 0;
12365
12366
4.05M
  if (info->disassembler_options)
12367
14.5k
    {
12368
14.5k
      force_thumb = false;
12369
14.5k
      for_each_disassembler_option (info, arm_parse_option, NULL);
12370
12371
      /* To avoid repeated parsing of these options, we remove them here.  */
12372
14.5k
      info->disassembler_options = NULL;
12373
14.5k
    }
12374
12375
  /* PR 10288: Control which instructions will be disassembled.  */
12376
4.05M
  if (info->private_data == NULL)
12377
17.0k
    {
12378
17.0k
      static struct arm_private_data private;
12379
12380
17.0k
      if (info->flavour != bfd_target_elf_flavour
12381
16.5k
    && (info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
12382
  /* If the user did not use the -m command line switch then default to
12383
     disassembling all types of ARM instruction.
12384
12385
     If this is an arm elf target, build attributes will be used to
12386
     determine info->mach, which enable us to be more accurate when
12387
     disassembling since we know what the target architecture version is.
12388
     For any other target see the comment below:
12389
12390
     The info->mach value has to be ignored as this will be based on
12391
     the default archictecture for the target and/or hints in the notes
12392
     section, but it will never be greater than the current largest arm
12393
     machine value (iWMMXt2), which is only equivalent to the V5TE
12394
     architecture.  ARM architectures have advanced beyond the machine
12395
     value encoding, and these newer architectures would be ignored if
12396
     the machine value was used.
12397
12398
     Ie the -m switch is used to restrict which instructions will be
12399
     disassembled.  If it is necessary to use the -m switch to tell
12400
     objdump that an ARM binary is being disassembled, eg because the
12401
     input is a raw binary file, but it is also desired to disassemble
12402
     all ARM instructions then use "-marm".  This will select the
12403
     "unknown" arm architecture which is compatible with any ARM
12404
     instruction.  */
12405
92
    info->mach = bfd_mach_arm_unknown;
12406
12407
      /* Compute the architecture bitmask from the machine number.
12408
   Note: This assumes that the machine number will not change
12409
   during disassembly....  */
12410
17.0k
      select_arm_features (info->mach, & private.features);
12411
12412
17.0k
      private.last_mapping_sym = -1;
12413
17.0k
      private.last_mapping_addr = 0;
12414
17.0k
      private.last_stop_offset = 0;
12415
12416
17.0k
      info->private_data = & private;
12417
17.0k
    }
12418
12419
4.05M
  private_data = info->private_data;
12420
12421
  /* Decide if our code is going to be little-endian, despite what the
12422
     function argument might say.  */
12423
4.05M
  little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12424
12425
  /* For ELF, consult the symbol table to determine what kind of code
12426
     or data we have.  */
12427
4.05M
  if (info->symtab_size != 0
12428
0
      && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12429
0
    {
12430
0
      bfd_vma addr;
12431
0
      int n;
12432
0
      int last_sym = -1;
12433
0
      enum map_type type = MAP_ARM;
12434
12435
0
      found = mapping_symbol_for_insn (pc, info, &type);
12436
0
      last_sym = private_data->last_mapping_sym;
12437
12438
0
      is_thumb = (private_data->last_type == MAP_THUMB);
12439
0
      is_data = (private_data->last_type == MAP_DATA);
12440
12441
      /* Look a little bit ahead to see if we should print out
12442
   two or four bytes of data.  If there's a symbol,
12443
   mapping or otherwise, after two bytes then don't
12444
   print more.  */
12445
0
      if (is_data)
12446
0
  {
12447
0
    size = 4 - (pc & 3);
12448
0
    for (n = last_sym + 1; n < info->symtab_size; n++)
12449
0
      {
12450
0
        addr = bfd_asymbol_value (info->symtab[n]);
12451
0
        if (addr > pc
12452
0
      && (info->section == NULL
12453
0
          || info->section == info->symtab[n]->section))
12454
0
    {
12455
0
      if (addr - pc < size)
12456
0
        size = addr - pc;
12457
0
      break;
12458
0
    }
12459
0
      }
12460
    /* If the next symbol is after three bytes, we need to
12461
       print only part of the data, so that we can use either
12462
       .byte or .short.  */
12463
0
    if (size == 3)
12464
0
      size = (pc & 1) ? 1 : 2;
12465
0
  }
12466
0
    }
12467
12468
4.05M
  if (info->symbols != NULL)
12469
0
    {
12470
0
      if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12471
0
  {
12472
0
    coff_symbol_type * cs;
12473
12474
0
    cs = coffsymbol (*info->symbols);
12475
0
    is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
12476
0
          || cs->native->u.syment.n_sclass == C_THUMBSTAT
12477
0
          || cs->native->u.syment.n_sclass == C_THUMBLABEL
12478
0
          || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12479
0
          || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12480
0
  }
12481
0
      else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12482
0
         && !found)
12483
0
  {
12484
    /* If no mapping symbol has been found then fall back to the type
12485
       of the function symbol.  */
12486
0
    elf_symbol_type *  es;
12487
0
    unsigned int       type;
12488
12489
0
    es = *(elf_symbol_type **)(info->symbols);
12490
0
    type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12491
12492
0
    is_thumb =
12493
0
      ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12494
0
        == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
12495
0
  }
12496
0
      else if (bfd_asymbol_flavour (*info->symbols)
12497
0
         == bfd_target_mach_o_flavour)
12498
0
  {
12499
0
    bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12500
12501
0
    is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12502
0
  }
12503
0
    }
12504
12505
4.05M
  if (force_thumb)
12506
2.63M
    is_thumb = true;
12507
12508
4.05M
  if (is_data)
12509
0
    info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12510
4.05M
  else
12511
4.05M
    info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12512
12513
4.05M
  info->bytes_per_line = 4;
12514
12515
  /* PR 10263: Disassemble data if requested to do so by the user.  */
12516
4.05M
  if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
12517
0
    {
12518
0
      int i;
12519
12520
      /* Size was already set above.  */
12521
0
      info->bytes_per_chunk = size;
12522
0
      printer = print_insn_data;
12523
12524
0
      status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
12525
0
      given = 0;
12526
0
      if (little)
12527
0
  for (i = size - 1; i >= 0; i--)
12528
0
    given = b[i] | (given << 8);
12529
0
      else
12530
0
  for (i = 0; i < (int) size; i++)
12531
0
    given = b[i] | (given << 8);
12532
0
    }
12533
4.05M
  else if (!is_thumb)
12534
1.42M
    {
12535
      /* In ARM mode endianness is a straightforward issue: the instruction
12536
   is four bytes long and is either ordered 0123 or 3210.  */
12537
1.42M
      printer = print_insn_arm;
12538
1.42M
      info->bytes_per_chunk = 4;
12539
1.42M
      size = 4;
12540
12541
1.42M
      status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
12542
1.42M
      if (little_code)
12543
424k
  given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
12544
996k
      else
12545
996k
  given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
12546
1.42M
    }
12547
2.63M
  else
12548
2.63M
    {
12549
      /* In Thumb mode we have the additional wrinkle of two
12550
   instruction lengths.  Fortunately, the bits that determine
12551
   the length of the current instruction are always to be found
12552
   in the first two bytes.  */
12553
2.63M
      printer = print_insn_thumb16;
12554
2.63M
      info->bytes_per_chunk = 2;
12555
2.63M
      size = 2;
12556
12557
2.63M
      status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
12558
2.63M
      if (little_code)
12559
2.35M
  given = (b[0]) | (b[1] << 8);
12560
281k
      else
12561
281k
  given = (b[1]) | (b[0] << 8);
12562
12563
2.63M
      if (!status)
12564
2.63M
  {
12565
    /* These bit patterns signal a four-byte Thumb
12566
       instruction.  */
12567
2.63M
    if ((given & 0xF800) == 0xF800
12568
2.27M
        || (given & 0xF800) == 0xF000
12569
2.17M
        || (given & 0xF800) == 0xE800)
12570
624k
      {
12571
624k
        status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
12572
624k
        if (little_code)
12573
503k
    given = (b[0]) | (b[1] << 8) | (given << 16);
12574
120k
        else
12575
120k
    given = (b[1]) | (b[0] << 8) | (given << 16);
12576
12577
624k
        printer = print_insn_thumb32;
12578
624k
        size = 4;
12579
624k
      }
12580
2.63M
  }
12581
12582
2.63M
      if (ifthen_address != pc)
12583
13.0k
  find_ifthen_state (pc, info, little_code);
12584
12585
2.63M
      if (ifthen_state)
12586
83.8k
  {
12587
83.8k
    if ((ifthen_state & 0xf) == 0x8)
12588
17.9k
      ifthen_next_state = 0;
12589
65.8k
    else
12590
65.8k
      ifthen_next_state = (ifthen_state & 0xe0)
12591
65.8k
        | ((ifthen_state & 0xf) << 1);
12592
83.8k
  }
12593
2.63M
    }
12594
12595
4.05M
  if (status)
12596
5.64k
    {
12597
5.64k
      info->memory_error_func (status, pc, info);
12598
5.64k
      return -1;
12599
5.64k
    }
12600
4.04M
  if (info->flags & INSN_HAS_RELOC)
12601
    /* If the instruction has a reloc associated with it, then
12602
       the offset field in the instruction will actually be the
12603
       addend for the reloc.  (We are using REL type relocs).
12604
       In such cases, we can ignore the pc when computing
12605
       addresses, since the addend is not currently pc-relative.  */
12606
0
    pc = 0;
12607
12608
4.04M
  printer (pc, info, given);
12609
12610
4.04M
  if (is_thumb)
12611
2.62M
    {
12612
2.62M
      ifthen_state = ifthen_next_state;
12613
2.62M
      ifthen_address += size;
12614
2.62M
    }
12615
4.04M
  return size;
12616
4.05M
}
12617
12618
int
12619
print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
12620
1.31M
{
12621
  /* Detect BE8-ness and record it in the disassembler info.  */
12622
1.31M
  if (info->flavour == bfd_target_elf_flavour
12623
994k
      && info->section != NULL
12624
993k
      && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12625
36.7k
    info->endian_code = BFD_ENDIAN_LITTLE;
12626
12627
1.31M
  return print_insn (pc, info, false);
12628
1.31M
}
12629
12630
int
12631
print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
12632
2.73M
{
12633
2.73M
  return print_insn (pc, info, true);
12634
2.73M
}
12635
12636
const disasm_options_and_args_t *
12637
disassembler_options_arm (void)
12638
0
{
12639
0
  static disasm_options_and_args_t *opts_and_args;
12640
12641
0
  if (opts_and_args == NULL)
12642
0
    {
12643
0
      disasm_options_t *opts;
12644
0
      unsigned int i;
12645
12646
0
      opts_and_args = XNEW (disasm_options_and_args_t);
12647
0
      opts_and_args->args = NULL;
12648
12649
0
      opts = &opts_and_args->options;
12650
0
      opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12651
0
      opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12652
0
      opts->arg = NULL;
12653
0
      for (i = 0; i < NUM_ARM_OPTIONS; i++)
12654
0
  {
12655
0
    opts->name[i] = regnames[i].name;
12656
0
    if (regnames[i].description != NULL)
12657
0
      opts->description[i] = _(regnames[i].description);
12658
0
    else
12659
0
      opts->description[i] = NULL;
12660
0
  }
12661
      /* The array we return must be NULL terminated.  */
12662
0
      opts->name[i] = NULL;
12663
0
      opts->description[i] = NULL;
12664
0
    }
12665
12666
0
  return opts_and_args;
12667
0
}
12668
12669
void
12670
print_arm_disassembler_options (FILE *stream)
12671
0
{
12672
0
  unsigned int i, max_len = 0;
12673
0
  fprintf (stream, _("\n\
12674
0
The following ARM specific disassembler options are supported for use with\n\
12675
0
the -M switch:\n"));
12676
12677
0
  for (i = 0; i < NUM_ARM_OPTIONS; i++)
12678
0
    {
12679
0
      unsigned int len = strlen (regnames[i].name);
12680
0
      if (max_len < len)
12681
0
  max_len = len;
12682
0
    }
12683
12684
0
  for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
12685
0
    fprintf (stream, "  %s%*c %s\n",
12686
0
       regnames[i].name,
12687
0
       (int)(max_len - strlen (regnames[i].name)), ' ',
12688
       _(regnames[i].description));
12689
0
}