Coverage Report

Created: 2026-04-04 08:16

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/binutils-gdb/opcodes/microblaze-dis.c
Line
Count
Source
1
/* Disassemble Xilinx microblaze instructions.
2
3
   Copyright (C) 2009-2026 Free Software Foundation, Inc.
4
5
   This file is part of the GNU opcodes library.
6
7
   This library is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
12
   It is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
17
   You should have received a copy of the GNU General Public License
18
   along with this file; see the file COPYING.  If not, write to the
19
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20
   MA 02110-1301, USA.  */
21
22
23
#include "sysdep.h"
24
#define STATIC_TABLE
25
#define DEFINE_TABLE
26
27
#include "disassemble.h"
28
#include <strings.h>
29
#include "microblaze-opc.h"
30
#include "microblaze-dis.h"
31
32
22.9k
#define get_field_rd(buf, instr)   get_field (buf, instr, RD_MASK, RD_LOW)
33
24.4k
#define get_field_r1(buf, instr)   get_field (buf, instr, RA_MASK, RA_LOW)
34
3.58k
#define get_field_r2(buf, instr)   get_field (buf, instr, RB_MASK, RB_LOW)
35
6.63k
#define get_int_field_imm(instr)   ((instr & IMM_MASK) >> IMM_LOW)
36
17.2k
#define get_int_field_r1(instr)    ((instr & RA_MASK) >> RA_LOW)
37
38
75.7k
#define NUM_STRBUFS 4
39
#define STRBUF_SIZE 25
40
41
struct string_buf
42
{
43
  unsigned int which;
44
  char str[NUM_STRBUFS][STRBUF_SIZE];
45
};
46
47
static inline char *
48
strbuf (struct string_buf *buf)
49
75.7k
{
50
75.7k
#ifdef ENABLE_CHECKING
51
75.7k
  if (buf->which >= NUM_STRBUFS)
52
0
    abort ();
53
75.7k
#endif
54
75.7k
  return buf->str[buf->which++];
55
75.7k
}
56
57
static char *
58
get_field (struct string_buf *buf, long instr, long mask, unsigned short low)
59
50.9k
{
60
50.9k
  char *p = strbuf (buf);
61
62
50.9k
  sprintf (p, "%s%d", register_prefix, (int)((instr & mask) >> low));
63
50.9k
  return p;
64
50.9k
}
65
66
static char *
67
get_field_imm (struct string_buf *buf, long instr)
68
21.2k
{
69
21.2k
  char *p = strbuf (buf);
70
71
21.2k
  sprintf (p, "%d", (short)((instr & IMM_MASK) >> IMM_LOW));
72
21.2k
  return p;
73
21.2k
}
74
75
static char *
76
get_field_imm5 (struct string_buf *buf, long instr)
77
176
{
78
176
  char *p = strbuf (buf);
79
80
176
  sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
81
176
  return p;
82
176
}
83
84
static char *
85
get_field_imm5_mbar (struct string_buf *buf, long instr)
86
116
{
87
116
  char *p = strbuf (buf);
88
89
116
  sprintf (p, "%d", (short)((instr & IMM5_MBAR_MASK) >> IMM_MBAR));
90
116
  return p;
91
116
}
92
93
static char *
94
get_field_immw (struct string_buf *buf, long instr)
95
149
{
96
149
  char *p = strbuf (buf);
97
98
149
  if (instr & 0x00004000)
99
18
    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK)
100
18
        >> IMM_WIDTH_LOW))); /* bsefi */
101
131
  else
102
131
    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >>
103
131
        IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >>
104
131
        IMM_LOW) + 1)); /* bsifi */
105
149
  return p;
106
149
}
107
108
static char *
109
get_field_rfsl (struct string_buf *buf, long instr)
110
2.38k
{
111
2.38k
  char *p = strbuf (buf);
112
113
2.38k
  sprintf (p, "%s%d", fsl_register_prefix,
114
2.38k
     (short)((instr & RFSL_MASK) >> IMM_LOW));
115
2.38k
  return p;
116
2.38k
}
117
118
static char *
119
get_field_imm15 (struct string_buf *buf, long instr)
120
20
{
121
20
  char *p = strbuf (buf);
122
123
20
  sprintf (p, "%d", (short)((instr & IMM15_MASK) >> IMM_LOW));
124
20
  return p;
125
20
}
126
127
static char *
128
get_field_special (struct string_buf *buf, long instr,
129
       const struct op_code_struct *op)
130
653
{
131
653
  char *p = strbuf (buf);
132
653
  char *spr;
133
134
653
  switch ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask))
135
653
    {
136
0
    case REG_MSR_MASK :
137
0
      spr = "msr";
138
0
      break;
139
35
    case REG_PC_MASK :
140
35
      spr = "pc";
141
35
      break;
142
9
    case REG_EAR_MASK :
143
9
      spr = "ear";
144
9
      break;
145
4
    case REG_ESR_MASK :
146
4
      spr = "esr";
147
4
      break;
148
19
    case REG_FSR_MASK :
149
19
      spr = "fsr";
150
19
      break;
151
62
    case REG_BTR_MASK :
152
62
      spr = "btr";
153
62
      break;
154
25
    case REG_EDR_MASK :
155
25
      spr = "edr";
156
25
      break;
157
11
    case REG_PID_MASK :
158
11
      spr = "pid";
159
11
      break;
160
36
    case REG_ZPR_MASK :
161
36
      spr = "zpr";
162
36
      break;
163
26
    case REG_TLBX_MASK :
164
26
      spr = "tlbx";
165
26
      break;
166
101
    case REG_TLBLO_MASK :
167
101
      spr = "tlblo";
168
101
      break;
169
0
    case REG_TLBHI_MASK :
170
0
      spr = "tlbhi";
171
0
      break;
172
7
    case REG_TLBSX_MASK :
173
7
      spr = "tlbsx";
174
7
      break;
175
0
    case REG_SHR_MASK :
176
0
      spr = "shr";
177
0
      break;
178
40
    case REG_SLR_MASK :
179
40
      spr = "slr";
180
40
      break;
181
278
    default :
182
278
      if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000)
183
278
    == REG_PVR_MASK)
184
117
  {
185
117
    sprintf (p, "%spvr%d", register_prefix,
186
117
       (unsigned short)(((instr & IMM_MASK) >> IMM_LOW)
187
117
            ^ op->immval_mask) ^ REG_PVR_MASK);
188
117
    return p;
189
117
  }
190
161
      else
191
161
  spr = "pc";
192
161
      break;
193
653
    }
194
195
536
   sprintf (p, "%s%s", register_prefix, spr);
196
536
   return p;
197
653
}
198
199
static unsigned long
200
read_insn_microblaze (bfd_vma memaddr,
201
          struct disassemble_info *info,
202
          const struct op_code_struct **opr)
203
66.7k
{
204
66.7k
  unsigned char       ibytes[4];
205
66.7k
  int                 status;
206
66.7k
  const struct op_code_struct *op;
207
66.7k
  unsigned long inst;
208
209
66.7k
  status = info->read_memory_func (memaddr, ibytes, 4, info);
210
211
66.7k
  if (status != 0)
212
55
    {
213
55
      info->memory_error_func (status, memaddr, info);
214
55
      return 0;
215
55
    }
216
217
66.7k
  if (info->endian == BFD_ENDIAN_BIG)
218
5.19k
    inst = (((unsigned) ibytes[0] << 24) | (ibytes[1] << 16)
219
5.19k
      | (ibytes[2] << 8) | ibytes[3]);
220
61.5k
  else if (info->endian == BFD_ENDIAN_LITTLE)
221
61.5k
    inst = (((unsigned) ibytes[3] << 24) | (ibytes[2] << 16)
222
61.5k
      | (ibytes[1] << 8) | ibytes[0]);
223
0
  else
224
0
    abort ();
225
226
  /* Just a linear search of the table.  */
227
13.3M
  for (op = microblaze_opcodes; op->name != 0; op ++)
228
13.3M
    if (op->bit_sequence == (inst & op->opcode_mask))
229
30.0k
      break;
230
231
66.7k
  *opr = op;
232
66.7k
  return inst;
233
66.7k
}
234
235
236
int
237
print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
238
64.2k
{
239
64.2k
  fprintf_ftype print_func = info->fprintf_func;
240
64.2k
  void *stream = info->stream;
241
64.2k
  unsigned long inst, prev_inst;
242
64.2k
  const struct op_code_struct *op, *pop;
243
64.2k
  int immval = 0;
244
64.2k
  bool immfound = false;
245
64.2k
  static bfd_vma prev_insn_addr = -1; /* Init the prev insn addr.  */
246
64.2k
  static int prev_insn_vma = -1;  /* Init the prev insn vma.  */
247
64.2k
  int curr_insn_vma = info->buffer_vma;
248
64.2k
  struct string_buf buf;
249
250
64.2k
  buf.which = 0;
251
64.2k
  info->bytes_per_chunk = 4;
252
253
64.2k
  inst = read_insn_microblaze (memaddr, info, &op);
254
64.2k
  if (inst == 0)
255
125
    return -1;
256
257
64.1k
  if (prev_insn_vma == curr_insn_vma)
258
2.63k
    {
259
2.63k
      if (memaddr-(info->bytes_per_chunk) == prev_insn_addr)
260
2.53k
  {
261
2.53k
    prev_inst = read_insn_microblaze (prev_insn_addr, info, &pop);
262
2.53k
    if (prev_inst == 0)
263
0
      return -1;
264
2.53k
    if (pop->instr == imm)
265
1
      {
266
1
        immval = (get_int_field_imm (prev_inst) << 16) & 0xffff0000;
267
1
        immfound = true;
268
1
      }
269
2.53k
    else
270
2.53k
      {
271
2.53k
        immval = 0;
272
2.53k
        immfound = false;
273
2.53k
      }
274
2.53k
  }
275
2.63k
    }
276
277
  /* Make curr insn as prev insn.  */
278
64.1k
  prev_insn_addr = memaddr;
279
64.1k
  prev_insn_vma = curr_insn_vma;
280
281
64.1k
  if (op->name == NULL)
282
34.9k
    print_func (stream, ".long 0x%04x", (unsigned int) inst);
283
29.1k
  else
284
29.1k
    {
285
29.1k
      print_func (stream, "%s", op->name);
286
287
29.1k
      switch (op->inst_type)
288
29.1k
  {
289
1.61k
  case INST_TYPE_RD_R1_R2:
290
1.61k
    print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
291
1.61k
          get_field_r1 (&buf, inst), get_field_r2 (&buf, inst));
292
1.61k
    break;
293
17.2k
  case INST_TYPE_RD_R1_IMM:
294
17.2k
    print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
295
17.2k
          get_field_r1 (&buf, inst), get_field_imm (&buf, inst));
296
17.2k
    if (info->print_address_func && get_int_field_r1 (inst) == 0
297
2.79k
        && info->symbol_at_address_func)
298
2.79k
      {
299
2.79k
        if (immfound)
300
0
    immval |= (get_int_field_imm (inst) & 0x0000ffff);
301
2.79k
        else
302
2.79k
    {
303
2.79k
      immval = get_int_field_imm (inst);
304
2.79k
      if (immval & 0x8000)
305
1.77k
        immval |= (~0xFFFF);
306
2.79k
    }
307
2.79k
        if (immval > 0 && info->symbol_at_address_func (immval, info))
308
0
    {
309
0
      print_func (stream, "\t// ");
310
0
      info->print_address_func (immval, info);
311
0
    }
312
2.79k
      }
313
17.2k
    break;
314
27
  case INST_TYPE_RD_R1_IMM5:
315
27
    print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
316
27
          get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst));
317
27
    break;
318
1.91k
  case INST_TYPE_RD_RFSL:
319
1.91k
    print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
320
1.91k
          get_field_rfsl (&buf, inst));
321
1.91k
    break;
322
273
  case INST_TYPE_R1_RFSL:
323
273
    print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
324
273
          get_field_rfsl (&buf, inst));
325
273
    break;
326
653
  case INST_TYPE_RD_SPECIAL:
327
653
    print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
328
653
          get_field_special (&buf, inst, op));
329
653
    break;
330
0
  case INST_TYPE_SPECIAL_R1:
331
0
    print_func (stream, "\t%s, %s", get_field_special (&buf, inst, op),
332
0
          get_field_r1 (&buf, inst));
333
0
    break;
334
811
  case INST_TYPE_RD_R1:
335
811
    print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
336
811
          get_field_r1 (&buf, inst));
337
811
    break;
338
1.33k
  case INST_TYPE_R1_R2:
339
1.33k
    print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
340
1.33k
          get_field_r2 (&buf, inst));
341
1.33k
    break;
342
2.73k
  case INST_TYPE_R1_IMM:
343
2.73k
    print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
344
2.73k
          get_field_imm (&buf, inst));
345
    /* The non-pc relative instructions are returns, which shouldn't
346
       have a label printed.  */
347
2.73k
    if (info->print_address_func && op->inst_offset_type == INST_PC_OFFSET
348
2.63k
        && info->symbol_at_address_func)
349
2.63k
      {
350
2.63k
        if (immfound)
351
0
    immval |= (get_int_field_imm (inst) & 0x0000ffff);
352
2.63k
        else
353
2.63k
    {
354
2.63k
      immval = get_int_field_imm (inst);
355
2.63k
      if (immval & 0x8000)
356
2.33k
        immval |= (~0xFFFF);
357
2.63k
    }
358
2.63k
        immval += memaddr;
359
2.63k
        if (immval > 0 && info->symbol_at_address_func (immval, info))
360
0
    {
361
0
      print_func (stream, "\t// ");
362
0
      info->print_address_func (immval, info);
363
0
    }
364
2.63k
        else
365
2.63k
    {
366
2.63k
      print_func (stream, "\t\t// ");
367
2.63k
      print_func (stream, "%x", immval);
368
2.63k
    }
369
2.63k
      }
370
2.73k
    break;
371
127
  case INST_TYPE_RD_IMM:
372
127
    print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
373
127
          get_field_imm (&buf, inst));
374
127
    if (info->print_address_func && info->symbol_at_address_func)
375
127
      {
376
127
        if (immfound)
377
0
    immval |= (get_int_field_imm (inst) & 0x0000ffff);
378
127
        else
379
127
    {
380
127
      immval = get_int_field_imm (inst);
381
127
      if (immval & 0x8000)
382
38
        immval |= (~0xFFFF);
383
127
    }
384
127
        if (op->inst_offset_type == INST_PC_OFFSET)
385
98
    immval += (int) memaddr;
386
127
        if (info->symbol_at_address_func (immval, info))
387
0
    {
388
0
      print_func (stream, "\t// ");
389
0
      info->print_address_func (immval, info);
390
0
    }
391
127
      }
392
127
    break;
393
1.11k
  case INST_TYPE_IMM:
394
1.11k
    print_func (stream, "\t%s", get_field_imm (&buf, inst));
395
1.11k
    if (info->print_address_func && info->symbol_at_address_func
396
1.11k
        && op->instr != imm)
397
1.08k
      {
398
1.08k
        if (immfound)
399
0
    immval |= (get_int_field_imm (inst) & 0x0000ffff);
400
1.08k
        else
401
1.08k
    {
402
1.08k
      immval = get_int_field_imm (inst);
403
1.08k
      if (immval & 0x8000)
404
288
        immval |= (~0xFFFF);
405
1.08k
    }
406
1.08k
        if (op->inst_offset_type == INST_PC_OFFSET)
407
605
    immval += (int) memaddr;
408
1.08k
        if (immval > 0 && info->symbol_at_address_func (immval, info))
409
0
    {
410
0
      print_func (stream, "\t// ");
411
0
      info->print_address_func (immval, info);
412
0
    }
413
1.08k
        else if (op->inst_offset_type == INST_PC_OFFSET)
414
605
    {
415
605
      print_func (stream, "\t\t// ");
416
605
      print_func (stream, "%x", immval);
417
605
    }
418
1.08k
      }
419
1.11k
    break;
420
341
  case INST_TYPE_RD_R2:
421
341
    print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
422
341
          get_field_r2 (&buf, inst));
423
341
    break;
424
124
  case INST_TYPE_R2:
425
124
    print_func (stream, "\t%s", get_field_r2 (&buf, inst));
426
124
    break;
427
0
  case INST_TYPE_R1:
428
0
    print_func (stream, "\t%s", get_field_r1 (&buf, inst));
429
0
    break;
430
175
  case INST_TYPE_R1_R2_SPECIAL:
431
175
    print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst),
432
175
          get_field_r2 (&buf, inst));
433
175
    break;
434
20
  case INST_TYPE_RD_IMM15:
435
20
    print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
436
20
          get_field_imm15 (&buf, inst));
437
20
    break;
438
    /* For mbar insn.  */
439
116
  case INST_TYPE_IMM5:
440
116
    print_func (stream, "\t%s", get_field_imm5_mbar (&buf, inst));
441
116
    break;
442
    /* For mbar 16 or sleep insn.  */
443
132
  case INST_TYPE_NONE:
444
132
    break;
445
    /* For bit field insns.  */
446
149
  case INST_TYPE_RD_R1_IMMW_IMMS:
447
149
    print_func (stream, "\t%s, %s, %s, %s",
448
149
          get_field_rd (&buf, inst),
449
149
          get_field_r1 (&buf, inst),
450
149
          get_field_immw (&buf, inst),
451
149
          get_field_imm5 (&buf, inst));
452
149
    break;
453
    /* For tuqula instruction */
454
0
  case INST_TYPE_RD:
455
0
    print_func (stream, "\t%s", get_field_rd (&buf, inst));
456
0
    break;
457
204
  case INST_TYPE_RFSL:
458
204
    print_func (stream, "\t%s", get_field_rfsl (&buf, inst));
459
204
    break;
460
0
  default:
461
    /* If the disassembler lags the instruction set.  */
462
0
    print_func (stream, "\tundecoded operands, inst is 0x%04x",
463
0
          (unsigned int) inst);
464
0
    break;
465
29.1k
  }
466
29.1k
    }
467
468
  /* Say how many bytes we consumed.  */
469
64.1k
  return 4;
470
64.1k
}
471
472
enum microblaze_instr
473
get_insn_microblaze (long inst,
474
           bool *isunsignedimm,
475
           enum microblaze_instr_type *insn_type,
476
           short *delay_slots)
477
0
{
478
0
  const struct op_code_struct *op;
479
0
  *isunsignedimm = false;
480
481
  /* Just a linear search of the table.  */
482
0
  for (op = microblaze_opcodes; op->name != 0; op ++)
483
0
    if (op->bit_sequence == (inst & op->opcode_mask))
484
0
      break;
485
486
0
  if (op->name == 0)
487
0
    return invalid_inst;
488
0
  else
489
0
    {
490
0
      *isunsignedimm = (op->inst_type == INST_TYPE_RD_R1_UNSIGNED_IMM);
491
0
      *insn_type = op->instr_type;
492
0
      *delay_slots = op->delay_slots;
493
0
      return op->instr;
494
0
    }
495
0
}
496
497
enum microblaze_instr
498
microblaze_decode_insn (long insn, int *rd, int *ra, int *rb, int *immed)
499
0
{
500
0
  enum microblaze_instr op;
501
0
  bool t1;
502
0
  enum microblaze_instr_type t2;
503
0
  short t3;
504
505
0
  op = get_insn_microblaze (insn, &t1, &t2, &t3);
506
0
  *rd = (insn & RD_MASK) >> RD_LOW;
507
0
  *ra = (insn & RA_MASK) >> RA_LOW;
508
0
  *rb = (insn & RB_MASK) >> RB_LOW;
509
0
  t3 = (insn & IMM_MASK) >> IMM_LOW;
510
0
  *immed = (int) t3;
511
0
  return (op);
512
0
}
513
514
unsigned long
515
microblaze_get_target_address (long inst, bool immfound, int immval,
516
             long pcval, long r1val, long r2val,
517
             bool *targetvalid,
518
             bool *unconditionalbranch)
519
0
{
520
0
  const struct op_code_struct *op;
521
0
  long targetaddr = 0;
522
523
0
  *unconditionalbranch = false;
524
  /* Just a linear search of the table.  */
525
0
  for (op = microblaze_opcodes; op->name != 0; op ++)
526
0
    if (op->bit_sequence == (inst & op->opcode_mask))
527
0
      break;
528
529
0
  if (op->name == 0)
530
0
    {
531
0
      *targetvalid = false;
532
0
    }
533
0
  else if (op->instr_type == branch_inst)
534
0
    {
535
0
      switch (op->inst_type)
536
0
  {
537
0
        case INST_TYPE_R2:
538
0
          *unconditionalbranch = true;
539
        /* Fall through.  */
540
0
        case INST_TYPE_RD_R2:
541
0
        case INST_TYPE_R1_R2:
542
0
          targetaddr = r2val;
543
0
          *targetvalid = true;
544
0
          if (op->inst_offset_type == INST_PC_OFFSET)
545
0
      targetaddr += pcval;
546
0
          break;
547
0
        case INST_TYPE_IMM:
548
0
          *unconditionalbranch = true;
549
        /* Fall through.  */
550
0
        case INST_TYPE_RD_IMM:
551
0
        case INST_TYPE_R1_IMM:
552
0
          if (immfound)
553
0
      {
554
0
        targetaddr = (immval << 16) & (~0xffff);
555
0
        targetaddr |= (get_int_field_imm (inst) & 0x0000ffff);
556
0
      }
557
0
    else
558
0
      {
559
0
        targetaddr = get_int_field_imm (inst);
560
0
        if (targetaddr & 0x8000)
561
0
    targetaddr |= (~0xFFFF);
562
0
            }
563
0
          if (op->inst_offset_type == INST_PC_OFFSET)
564
0
      targetaddr += pcval;
565
0
          *targetvalid = true;
566
0
          break;
567
0
  default:
568
0
    *targetvalid = false;
569
0
    break;
570
0
        }
571
0
    }
572
0
  else if (op->instr_type == return_inst)
573
0
    {
574
0
      if (immfound)
575
0
  {
576
0
    targetaddr = (immval << 16) & (~0xffff);
577
0
    targetaddr |= (get_int_field_imm (inst) & 0x0000ffff);
578
0
  }
579
0
      else
580
0
  {
581
0
    targetaddr = get_int_field_imm (inst);
582
0
    if (targetaddr & 0x8000)
583
0
      targetaddr |= (~0xFFFF);
584
0
  }
585
0
      targetaddr += r1val;
586
0
      *targetvalid = true;
587
0
    }
588
0
  else
589
0
    *targetvalid = false;
590
0
  return targetaddr;
591
0
}