/src/binutils-gdb/include/opcode/riscv.h
Line | Count | Source |
1 | | /* riscv.h. RISC-V opcode list for GDB, the GNU debugger. |
2 | | Copyright (C) 2011-2026 Free Software Foundation, Inc. |
3 | | Contributed by Andrew Waterman |
4 | | |
5 | | This file is part of GDB, GAS, and the GNU binutils. |
6 | | |
7 | | GDB, GAS, and the GNU binutils are free software; you can redistribute |
8 | | them and/or modify them under the terms of the GNU General Public |
9 | | License as published by the Free Software Foundation; either version |
10 | | 3, or (at your option) any later version. |
11 | | |
12 | | GDB, GAS, and the GNU binutils are distributed in the hope that they |
13 | | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
14 | | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
15 | | the GNU General Public License for more details. |
16 | | |
17 | | You should have received a copy of the GNU General Public License |
18 | | along with this program; see the file COPYING3. If not, |
19 | | see <http://www.gnu.org/licenses/>. */ |
20 | | |
21 | | #ifndef _RISCV_H_ |
22 | | #define _RISCV_H_ |
23 | | |
24 | | #include "riscv-opc.h" |
25 | | #include <stdlib.h> |
26 | | #include <stdint.h> |
27 | | |
28 | | typedef uint64_t insn_t; |
29 | | |
30 | | static inline unsigned int riscv_insn_length (insn_t insn) |
31 | 5.37M | { |
32 | 5.37M | if ((insn & 0x3) != 0x3) /* RVC instructions. */ |
33 | 4.16M | return 2; |
34 | 1.21M | if ((insn & 0x1f) != 0x1f) /* 32-bit instructions. */ |
35 | 735k | return 4; |
36 | 478k | if ((insn & 0x3f) == 0x1f) /* 48-bit instructions. */ |
37 | 34.6k | return 6; |
38 | 444k | if ((insn & 0x7f) == 0x3f) /* 64-bit instructions. */ |
39 | 21.6k | return 8; |
40 | | /* 80- ... 176-bit instructions. */ |
41 | 422k | if ((insn & 0x7f) == 0x7f && (insn & 0x7000) != 0x7000) |
42 | 84.3k | return 10 + ((insn >> 11) & 0xe); |
43 | | /* Maximum value returned by this function. */ |
44 | 338k | #define RISCV_MAX_INSN_LEN 22 |
45 | | /* Longer instructions not supported at the moment. */ |
46 | 338k | return 2; |
47 | 422k | } Unexecuted instantiation: elf32-riscv.c:riscv_insn_length Unexecuted instantiation: elf64-riscv.c:riscv_insn_length Unexecuted instantiation: elfxx-riscv.c:riscv_insn_length riscv-dis.c:riscv_insn_length Line | Count | Source | 31 | 5.37M | { | 32 | 5.37M | if ((insn & 0x3) != 0x3) /* RVC instructions. */ | 33 | 4.16M | return 2; | 34 | 1.21M | if ((insn & 0x1f) != 0x1f) /* 32-bit instructions. */ | 35 | 735k | return 4; | 36 | 478k | if ((insn & 0x3f) == 0x1f) /* 48-bit instructions. */ | 37 | 34.6k | return 6; | 38 | 444k | if ((insn & 0x7f) == 0x3f) /* 64-bit instructions. */ | 39 | 21.6k | return 8; | 40 | | /* 80- ... 176-bit instructions. */ | 41 | 422k | if ((insn & 0x7f) == 0x7f && (insn & 0x7000) != 0x7000) | 42 | 84.3k | return 10 + ((insn >> 11) & 0xe); | 43 | | /* Maximum value returned by this function. */ | 44 | 338k | #define RISCV_MAX_INSN_LEN 22 | 45 | | /* Longer instructions not supported at the moment. */ | 46 | 338k | return 2; | 47 | 422k | } |
Unexecuted instantiation: riscv-opc.c:riscv_insn_length |
48 | | |
49 | | #define RVC_JUMP_BITS 11 |
50 | | #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN) |
51 | | |
52 | | #define RVC_BRANCH_BITS 8 |
53 | | #define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN) |
54 | | |
55 | 4.32M | #define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) |
56 | 112k | #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) |
57 | 0 | #define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n))) |
58 | 0 | #define RV_IMM_SIGN_N(x, s, n) (-(((x) >> ((s) + (n) - 1)) & 1)) |
59 | | |
60 | | #define EXTRACT_ITYPE_IMM(x) \ |
61 | 45.5k | (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) |
62 | | #define EXTRACT_STYPE_IMM(x) \ |
63 | 19.3k | (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12)) |
64 | | #define EXTRACT_BTYPE_IMM(x) \ |
65 | 7.57k | ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12)) |
66 | | #define EXTRACT_UTYPE_IMM(x) \ |
67 | 30.4k | ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32)) |
68 | | #define EXTRACT_JTYPE_IMM(x) \ |
69 | 9.71k | ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20)) |
70 | | #define EXTRACT_CITYPE_IMM(x) \ |
71 | 546k | (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5)) |
72 | | #define EXTRACT_CITYPE_LUI_IMM(x) \ |
73 | 83.9k | (EXTRACT_CITYPE_IMM (x) << RISCV_IMM_BITS) |
74 | | #define EXTRACT_CITYPE_ADDI16SP_IMM(x) \ |
75 | 7.44k | ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9)) |
76 | | #define EXTRACT_CITYPE_LWSP_IMM(x) \ |
77 | 31.6k | ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6)) |
78 | | #define EXTRACT_CITYPE_LDSP_IMM(x) \ |
79 | 70.5k | ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6)) |
80 | | #define EXTRACT_CSSTYPE_IMM(x) \ |
81 | | (RV_X(x, 7, 6) << 0) |
82 | | #define EXTRACT_CSSTYPE_SWSP_IMM(x) \ |
83 | 31.1k | ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6)) |
84 | | #define EXTRACT_CSSTYPE_SDSP_IMM(x) \ |
85 | 49.8k | ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6)) |
86 | | #define EXTRACT_CIWTYPE_IMM(x) \ |
87 | | (RV_X(x, 5, 8)) |
88 | | #define EXTRACT_CIWTYPE_ADDI4SPN_IMM(x) \ |
89 | 370k | ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6)) |
90 | | #define EXTRACT_CLTYPE_IMM(x) \ |
91 | | ((RV_X(x, 5, 2) << 0) | (RV_X(x, 10, 3) << 2)) |
92 | | #define EXTRACT_CLTYPE_LW_IMM(x) \ |
93 | 76.4k | ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6)) |
94 | | #define EXTRACT_CLTYPE_LD_IMM(x) \ |
95 | 210k | ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6)) |
96 | | #define EXTRACT_CBTYPE_IMM(x) \ |
97 | 52.9k | ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8)) |
98 | | #define EXTRACT_CJTYPE_IMM(x) \ |
99 | 20.1k | ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11)) |
100 | | #define EXTRACT_RVV_VI_IMM(x) \ |
101 | 0 | (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5)) |
102 | | #define EXTRACT_RVV_VI_UIMM(x) \ |
103 | 0 | (RV_X(x, 15, 5)) |
104 | | #define EXTRACT_RVV_VI_UIMM6(x) \ |
105 | 0 | (RV_X(x, 15, 5) | (RV_X(x, 26, 1) << 5)) |
106 | | #define EXTRACT_RVV_OFFSET(x) \ |
107 | 0 | (RV_X(x, 29, 3)) |
108 | | #define EXTRACT_RVV_VB_IMM(x) \ |
109 | 0 | (RV_X(x, 20, 10)) |
110 | | #define EXTRACT_RVV_VC_IMM(x) \ |
111 | 0 | (RV_X(x, 20, 11)) |
112 | | #define EXTRACT_ZCB_BYTE_UIMM(x) \ |
113 | 0 | (RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1)) |
114 | | #define EXTRACT_ZCB_HALFWORD_UIMM(x) \ |
115 | 0 | (RV_X(x, 5, 1) << 1) |
116 | | #define EXTRACT_ZCMP_SPIMM(x) \ |
117 | 0 | (RV_X(x, 2, 2) << 4) |
118 | | #define EXTRACT_ZCMT_INDEX(x) \ |
119 | 0 | (RV_X(x, 2, 8)) |
120 | | /* Vendor-specific (CORE-V) extract macros. */ |
121 | | #define EXTRACT_CV_IS2_UIMM5(x) \ |
122 | 0 | (RV_X(x, 20, 5)) |
123 | | #define EXTRACT_CV_IS3_UIMM5(x) \ |
124 | 0 | (RV_X(x, 25, 5)) |
125 | | #define EXTRACT_CV_BI_IMM5(x) \ |
126 | 0 | (RV_X(x, 20, 5) | (RV_IMM_SIGN_N(x, 20, 5) << 5)) |
127 | | #define EXTRACT_CV_BITMANIP_UIMM5(x) \ |
128 | 0 | (RV_X(x, 25, 5)) |
129 | | #define EXTRACT_CV_BITMANIP_UIMM2(x) \ |
130 | 0 | (RV_X(x, 25, 2)) |
131 | | #define EXTRACT_CV_SIMD_IMM6(x) \ |
132 | 0 | ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1) | (RV_IMM_SIGN_N(x, 20, 5) << 5)) |
133 | | #define EXTRACT_CV_SIMD_UIMM6(x) \ |
134 | 0 | ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1)) |
135 | | /* Vendor-specific (MIPS) extract macros. */ |
136 | | #define EXTRACT_MIPS_LWP_IMM(x) \ |
137 | 0 | (RV_X(x, 22, 5) << 2) |
138 | | #define EXTRACT_MIPS_LDP_IMM(x) \ |
139 | 0 | (RV_X(x, 23, 4) << 3) |
140 | | #define EXTRACT_MIPS_SWP_IMM(x) \ |
141 | 0 | ((RV_X(x, 25, 2) << 5) | (RV_X(x, 9, 3) << 2)) |
142 | | #define EXTRACT_MIPS_SDP_IMM(x) \ |
143 | 0 | ((RV_X(x, 25, 2) << 5) | (RV_X(x, 10, 2) << 3)) |
144 | | /* Vendor-specific (SPACEMIT) encode macros. */ |
145 | | #define ENCODE_SPACEMIT_IME_UIMM2_SP(x) \ |
146 | | ((RV_X (x, 0, 1) << 7) | (RV_X (x, 1, 1) << 15)) |
147 | | |
148 | | #define ENCODE_ITYPE_IMM(x) \ |
149 | 0 | (RV_X(x, 0, 12) << 20) |
150 | | #define ENCODE_STYPE_IMM(x) \ |
151 | 0 | ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25)) |
152 | | #define ENCODE_BTYPE_IMM(x) \ |
153 | 0 | ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31)) |
154 | | #define ENCODE_UTYPE_IMM(x) \ |
155 | 0 | (RV_X(x, 12, 20) << 12) |
156 | | #define ENCODE_JTYPE_IMM(x) \ |
157 | 0 | ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31)) |
158 | | #define ENCODE_CITYPE_IMM(x) \ |
159 | 0 | ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12)) |
160 | | #define ENCODE_CITYPE_LUI_IMM(x) \ |
161 | 0 | ENCODE_CITYPE_IMM ((x) >> RISCV_IMM_BITS) |
162 | | #define ENCODE_CITYPE_ADDI16SP_IMM(x) \ |
163 | | ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12)) |
164 | | #define ENCODE_CITYPE_LWSP_IMM(x) \ |
165 | | ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2)) |
166 | | #define ENCODE_CITYPE_LDSP_IMM(x) \ |
167 | | ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2)) |
168 | | #define ENCODE_CSSTYPE_IMM(x) \ |
169 | | (RV_X(x, 0, 6) << 7) |
170 | | #define ENCODE_CSSTYPE_SWSP_IMM(x) \ |
171 | | ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7)) |
172 | | #define ENCODE_CSSTYPE_SDSP_IMM(x) \ |
173 | | ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7)) |
174 | | #define ENCODE_CIWTYPE_IMM(x) \ |
175 | | (RV_X(x, 0, 8) << 5) |
176 | | #define ENCODE_CIWTYPE_ADDI4SPN_IMM(x) \ |
177 | | ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7)) |
178 | | #define ENCODE_CLTYPE_IMM(x) \ |
179 | | ((RV_X(x, 0, 2) << 5) | (RV_X(x, 2, 3) << 10)) |
180 | | #define ENCODE_CLTYPE_LW_IMM(x) \ |
181 | | ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5)) |
182 | | #define ENCODE_CLTYPE_LD_IMM(x) \ |
183 | | ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5)) |
184 | | #define ENCODE_CBTYPE_IMM(x) \ |
185 | 0 | ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12)) |
186 | | #define ENCODE_CJTYPE_IMM(x) \ |
187 | 0 | ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12)) |
188 | | #define ENCODE_RVV_VB_IMM(x) \ |
189 | | (RV_X(x, 0, 10) << 20) |
190 | | #define ENCODE_RVV_VC_IMM(x) \ |
191 | | (RV_X(x, 0, 11) << 20) |
192 | | #define ENCODE_RVV_VI_UIMM6(x) \ |
193 | | (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26) |
194 | | #define ENCODE_ZCB_BYTE_UIMM(x) \ |
195 | | ((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5)) |
196 | | #define ENCODE_ZCB_HALFWORD_UIMM(x) \ |
197 | | (RV_X(x, 1, 1) << 5) |
198 | | #define ENCODE_ZCMP_SPIMM(x) \ |
199 | | (RV_X(x, 4, 2) << 2) |
200 | | #define ENCODE_ZCMT_INDEX(x) \ |
201 | | (RV_X(x, 0, 8) << 2) |
202 | | /* Vendor-specific (CORE-V) encode macros. */ |
203 | | #define ENCODE_CV_IS2_UIMM5(x) \ |
204 | | (RV_X(x, 0, 5) << 20) |
205 | | #define ENCODE_CV_IS3_UIMM5(x) \ |
206 | | (RV_X(x, 0, 5) << 25) |
207 | | #define ENCODE_CV_BITMANIP_UIMM5(x) \ |
208 | | (RV_X(x, 0, 5) << 25) |
209 | | #define ENCODE_CV_BITMANIP_UIMM2(x) \ |
210 | | (RV_X(x, 0, 2) << 25) |
211 | | #define ENCODE_CV_SIMD_IMM6(x) \ |
212 | | ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20)) |
213 | | #define ENCODE_CV_SIMD_UIMM6(x) \ |
214 | | ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20)) |
215 | | /* Vendor-specific (MIPS) encode macros. */ |
216 | | #define ENCODE_MIPS_LWP_IMM(x) \ |
217 | | (RV_X(x, 2, 5) << 22) |
218 | | #define ENCODE_MIPS_LDP_IMM(x) \ |
219 | | (RV_X(x, 3, 4) << 23) |
220 | | #define ENCODE_MIPS_SWP_IMM(x) \ |
221 | | ((RV_X(x, 5, 2) << 25) | (RV_X(x, 2, 3) << 9)) |
222 | | #define ENCODE_MIPS_SDP_IMM(x) \ |
223 | | ((RV_X(x, 5, 2) << 25) | (RV_X(x, 3, 2) << 10)) |
224 | | |
225 | 0 | #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) |
226 | | #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) |
227 | 0 | #define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x)) |
228 | 0 | #define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x)) |
229 | 0 | #define VALID_JTYPE_IMM(x) (EXTRACT_JTYPE_IMM(ENCODE_JTYPE_IMM(x)) == (x)) |
230 | | #define VALID_CITYPE_IMM(x) (EXTRACT_CITYPE_IMM(ENCODE_CITYPE_IMM(x)) == (x)) |
231 | 0 | #define VALID_CITYPE_LUI_IMM(x) (ENCODE_CITYPE_LUI_IMM(x) != 0 \ |
232 | 0 | && EXTRACT_CITYPE_LUI_IMM(ENCODE_CITYPE_LUI_IMM(x)) == (x)) |
233 | | #define VALID_CITYPE_ADDI16SP_IMM(x) (ENCODE_CITYPE_ADDI16SP_IMM(x) != 0 \ |
234 | | && EXTRACT_CITYPE_ADDI16SP_IMM(ENCODE_CITYPE_ADDI16SP_IMM(x)) == (x)) |
235 | | #define VALID_CITYPE_LWSP_IMM(x) (EXTRACT_CITYPE_LWSP_IMM(ENCODE_CITYPE_LWSP_IMM(x)) == (x)) |
236 | | #define VALID_CITYPE_LDSP_IMM(x) (EXTRACT_CITYPE_LDSP_IMM(ENCODE_CITYPE_LDSP_IMM(x)) == (x)) |
237 | | #define VALID_CSSTYPE_IMM(x) (EXTRACT_CSSTYPE_IMM(ENCODE_CSSTYPE_IMM(x)) == (x)) |
238 | | #define VALID_CSSTYPE_SWSP_IMM(x) (EXTRACT_CSSTYPE_SWSP_IMM(ENCODE_CSSTYPE_SWSP_IMM(x)) == (x)) |
239 | | #define VALID_CSSTYPE_SDSP_IMM(x) (EXTRACT_CSSTYPE_SDSP_IMM(ENCODE_CSSTYPE_SDSP_IMM(x)) == (x)) |
240 | | #define VALID_CIWTYPE_IMM(x) (EXTRACT_CIWTYPE_IMM(ENCODE_CIWTYPE_IMM(x)) == (x)) |
241 | | #define VALID_CIWTYPE_ADDI4SPN_IMM(x) (EXTRACT_CIWTYPE_ADDI4SPN_IMM(ENCODE_CIWTYPE_ADDI4SPN_IMM(x)) == (x)) |
242 | | #define VALID_CLTYPE_IMM(x) (EXTRACT_CLTYPE_IMM(ENCODE_CLTYPE_IMM(x)) == (x)) |
243 | | #define VALID_CLTYPE_LW_IMM(x) (EXTRACT_CLTYPE_LW_IMM(ENCODE_CLTYPE_LW_IMM(x)) == (x)) |
244 | | #define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x)) |
245 | 0 | #define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x)) |
246 | 0 | #define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x)) |
247 | | #define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x)) |
248 | | #define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x)) |
249 | | #define VALID_ZCB_BYTE_UIMM(x) (EXTRACT_ZCB_BYTE_UIMM(ENCODE_ZCB_BYTE_UIMM(x)) == (x)) |
250 | | #define VALID_ZCB_HALFWORD_UIMM(x) (EXTRACT_ZCB_HALFWORD_UIMM(ENCODE_ZCB_HALFWORD_UIMM(x)) == (x)) |
251 | | #define VALID_ZCMP_SPIMM(x) (EXTRACT_ZCMP_SPIMM(ENCODE_ZCMP_SPIMM(x)) == (x)) |
252 | | |
253 | | #define RISCV_RTYPE(insn, rd, rs1, rs2) \ |
254 | 0 | ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2)) |
255 | | #define RISCV_ITYPE(insn, rd, rs1, imm) \ |
256 | 0 | ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm)) |
257 | | #define RISCV_STYPE(insn, rs1, rs2, imm) \ |
258 | | ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm)) |
259 | | #define RISCV_BTYPE(insn, rs1, rs2, target) \ |
260 | | ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_BTYPE_IMM(target)) |
261 | | #define RISCV_UTYPE(insn, rd, bigimm) \ |
262 | 0 | ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm)) |
263 | | #define RISCV_JTYPE(insn, rd, target) \ |
264 | | ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_JTYPE_IMM(target)) |
265 | | |
266 | 0 | #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0) |
267 | 0 | #define RVC_NOP MATCH_C_ADDI |
268 | | |
269 | | #define RISCV_CONST_HIGH_PART(VALUE) \ |
270 | 0 | (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1)) |
271 | 0 | #define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE)) |
272 | 0 | #define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC)) |
273 | 0 | #define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC)) |
274 | | |
275 | | #define RISCV_JUMP_BITS RISCV_BIGIMM_BITS |
276 | | #define RISCV_JUMP_ALIGN_BITS 1 |
277 | | #define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS) |
278 | | #define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN) |
279 | | |
280 | 140k | #define RISCV_IMM_BITS 12 |
281 | 40.8k | #define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS) |
282 | 0 | #define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS) |
283 | 40.8k | #define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS) |
284 | | #define RISCV_RVC_IMM_REACH (1LL << 6) |
285 | | #define RISCV_BRANCH_BITS RISCV_IMM_BITS |
286 | | #define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS |
287 | | #define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS) |
288 | | #define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN) |
289 | | |
290 | | /* RV fields. */ |
291 | | |
292 | 295k | #define OP_MASK_OP 0x7f |
293 | | #define OP_SH_OP 0 |
294 | 10.3M | #define OP_MASK_RS2 0x1f |
295 | 20.7M | #define OP_SH_RS2 20 |
296 | 12.1M | #define OP_MASK_RS1 0x1f |
297 | 22.9M | #define OP_SH_RS1 15 |
298 | | #define OP_MASK_RS3 0x1fU |
299 | | #define OP_SH_RS3 27 |
300 | 12.7M | #define OP_MASK_RD 0x1f |
301 | 23.6M | #define OP_SH_RD 7 |
302 | | #define OP_MASK_SHAMT 0x3f |
303 | | #define OP_SH_SHAMT 20 |
304 | | #define OP_MASK_SHAMTW 0x1f |
305 | | #define OP_SH_SHAMTW 20 |
306 | | #define OP_MASK_RM 0x7 |
307 | | #define OP_SH_RM 12 |
308 | | #define OP_MASK_PRED 0xf |
309 | | #define OP_SH_PRED 24 |
310 | | #define OP_MASK_SUCC 0xf |
311 | | #define OP_SH_SUCC 20 |
312 | | #define OP_MASK_AQ 0x1 |
313 | | #define OP_SH_AQ 26 |
314 | | #define OP_MASK_RL 0x1 |
315 | | #define OP_SH_RL 25 |
316 | | |
317 | | #define OP_MASK_CSR 0xfffU |
318 | | #define OP_SH_CSR 20 |
319 | | |
320 | | #define OP_MASK_FUNCT3 0x7 |
321 | | #define OP_SH_FUNCT3 12 |
322 | | #define OP_MASK_FUNCT7 0x7fU |
323 | | #define OP_SH_FUNCT7 25 |
324 | | #define OP_MASK_FUNCT2 0x3 |
325 | | #define OP_SH_FUNCT2 25 |
326 | | |
327 | | /* RVC fields. */ |
328 | | |
329 | | #define OP_MASK_OP2 0x3 |
330 | | #define OP_SH_OP2 0 |
331 | | |
332 | 778k | #define OP_MASK_CRS2 0x1f |
333 | 1.53M | #define OP_SH_CRS2 2 |
334 | | #define OP_MASK_CRS1S 0x7 |
335 | | #define OP_SH_CRS1S 7 |
336 | 1.59M | #define OP_MASK_CRS2S 0x7 |
337 | 3.19M | #define OP_SH_CRS2S 2 |
338 | | |
339 | | #define OP_MASK_CFUNCT6 0x3f |
340 | | #define OP_SH_CFUNCT6 10 |
341 | | #define OP_MASK_CFUNCT4 0xf |
342 | | #define OP_SH_CFUNCT4 12 |
343 | | #define OP_MASK_CFUNCT3 0x7 |
344 | | #define OP_SH_CFUNCT3 13 |
345 | | #define OP_MASK_CFUNCT2 0x3 |
346 | | #define OP_SH_CFUNCT2 5 |
347 | | |
348 | | /* Scalar crypto fields. */ |
349 | | |
350 | | #define OP_SH_BS 30 |
351 | | #define OP_MASK_BS 3 |
352 | | #define OP_SH_RNUM 20 |
353 | | #define OP_MASK_RNUM 0xf |
354 | | |
355 | | /* RVV fields. */ |
356 | | |
357 | | #define OP_MASK_FUNCT6 0x3fU |
358 | | #define OP_SH_FUNCT6 26 |
359 | | |
360 | 1.21M | #define OP_MASK_VD 0x1f |
361 | 2.42M | #define OP_SH_VD 7 |
362 | 4.82M | #define OP_MASK_VS1 0x1f |
363 | 9.64M | #define OP_SH_VS1 15 |
364 | 4.82M | #define OP_MASK_VS2 0x1f |
365 | 9.64M | #define OP_SH_VS2 20 |
366 | | #define OP_MASK_VIMM 0x1f |
367 | | #define OP_SH_VIMM 15 |
368 | | #define OP_MASK_VMASK 0x1 |
369 | | #define OP_SH_VMASK 25 |
370 | | #define OP_MASK_VFUNCT6 0x3f |
371 | | #define OP_SH_VFUNCT6 26 |
372 | | #define OP_MASK_VLMUL 0x7 |
373 | | #define OP_SH_VLMUL 0 |
374 | | #define OP_MASK_VSEW 0x7 |
375 | | #define OP_SH_VSEW 3 |
376 | | #define OP_MASK_VTA 0x1 |
377 | | #define OP_SH_VTA 6 |
378 | | #define OP_MASK_VMA 0x1 |
379 | | #define OP_SH_VMA 7 |
380 | | #define OP_MASK_VTYPE_ALTFMT 0x1 |
381 | | #define OP_SH_VTYPE_ALTFMT 8 |
382 | | #define OP_MASK_VWD 0x1 |
383 | | #define OP_SH_VWD 26 |
384 | | |
385 | | #define OP_MASK_XTHEADVLMUL 0x3 |
386 | | #define OP_SH_XTHEADVLMUL 0 |
387 | | #define OP_MASK_XTHEADVSEW 0x7 |
388 | | #define OP_SH_XTHEADVSEW 2 |
389 | | #define OP_MASK_XTHEADVEDIV 0x3 |
390 | | #define OP_SH_XTHEADVEDIV 5 |
391 | | #define OP_MASK_XTHEADVTYPE_RES 0xf |
392 | | #define OP_SH_XTHEADVTYPE_RES 7 |
393 | | |
394 | | /* Zc fields. */ |
395 | | #define OP_MASK_REG_LIST 0xf |
396 | | #define OP_SH_REG_LIST 4 |
397 | 0 | #define ZCMP_SP_ALIGNMENT 16 |
398 | | #define OP_MASK_SREG1 0x7 |
399 | | #define OP_SH_SREG1 7 |
400 | | #define OP_MASK_SREG2 0x7 |
401 | | #define OP_SH_SREG2 2 |
402 | | |
403 | | #define NVECR 32 |
404 | | #define NVECM 1 |
405 | | |
406 | | /* SiFive fields. */ |
407 | | #define OP_MASK_XSO2 0x3 |
408 | | #define OP_SH_XSO2 26 |
409 | | #define OP_MASK_XSO1 0x1 |
410 | | #define OP_SH_XSO1 26 |
411 | | |
412 | | /* MIPS fields. */ |
413 | | #define OP_MASK_MIPS_IMM9 0x1ff |
414 | | #define OP_SH_MIPS_IMM9 20 |
415 | | #define OP_MASK_MIPS_HINT 0x1f |
416 | | #define OP_SH_MIPS_HINT 7 |
417 | | #define OP_MASK_MIPS_LWP_OFFSET 0x1f |
418 | | #define OP_SH_MIPS_LWP_OFFSET 22 |
419 | | #define OP_MASK_MIPS_LDP_OFFSET 0xf |
420 | | #define OP_SH_MIPS_LDP_OFFSET 23 |
421 | | #define OP_MASK_MIPS_SWP_OFFSET9 0x7 |
422 | | #define OP_SH_MIPS_SWP_OFFSET9 9 |
423 | | #define OP_MASK_MIPS_SWP_OFFSET25 0x3 |
424 | | #define OP_SH_MIPS_SWP_OFFSET25 25 |
425 | | #define OP_MASK_MIPS_SDP_OFFSET10 0x3 |
426 | | #define OP_SH_MIPS_SDP_OFFSET10 10 |
427 | | #define OP_MASK_MIPS_SDP_OFFSET25 0x3 |
428 | | #define OP_SH_MIPS_SDP_OFFSET25 25 |
429 | | |
430 | | /* SpacemiT fields. */ |
431 | | #define OP_MASK_SPACEMIT_IME_VD 0xf |
432 | | #define OP_SH_SPACEMIT_IME_VD 8 |
433 | | #define OP_MASK_SPACEMIT_IME_VS1 0xf |
434 | | #define OP_SH_SPACEMIT_IME_VS1 16 |
435 | | #define OP_MASK_SPACEMIT_IME_WI 0x3 |
436 | | #define OP_SH_SPACEMIT_IME_WI 29 |
437 | | #define OP_MASK_SPACEMIT_IME_VMASK 0x1 |
438 | | #define OP_SH_SPACEMIT_IME_VMASK 25 |
439 | | |
440 | | /* ABI names for selected x-registers. */ |
441 | | |
442 | | #define X_ZERO 0 |
443 | 0 | #define X_RA 1 |
444 | 353k | #define X_SP 2 |
445 | 217k | #define X_GP 3 |
446 | 217k | #define X_TP 4 |
447 | | #define X_T0 5 |
448 | | #define X_T1 6 |
449 | | #define X_T2 7 |
450 | 0 | #define X_S0 8 |
451 | 0 | #define X_S1 9 |
452 | | #define X_A0 10 |
453 | | #define X_A1 11 |
454 | 0 | #define X_S2 18 |
455 | | #define X_S7 23 |
456 | | #define X_S10 26 |
457 | 0 | #define X_S11 27 |
458 | | #define X_T3 28 |
459 | | |
460 | | #define NGPR 32 |
461 | | #define NFPR 32 |
462 | | |
463 | | /* These fake label defines are use by both the assembler, and |
464 | | libopcodes. The assembler uses this when it needs to generate a fake |
465 | | label, and libopcodes uses it to hide the fake labels in its output. */ |
466 | 91 | #define RISCV_FAKE_LABEL_NAME ".L0 " |
467 | | #define RISCV_FAKE_LABEL_CHAR ' ' |
468 | | |
469 | | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
470 | | VALUE << SHIFT. VALUE is evaluated exactly once. */ |
471 | | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ |
472 | | (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \ |
473 | | | ((insn_t)((VALUE) & (MASK)) << (SHIFT))) |
474 | | |
475 | | /* Extract bits MASK << SHIFT from STRUCT and shift them right |
476 | | SHIFT places. */ |
477 | | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ |
478 | 1.03M | (((STRUCT) >> (SHIFT)) & (MASK)) |
479 | | |
480 | | /* Extract the operand given by FIELD from integer INSN. */ |
481 | | #define EXTRACT_OPERAND(FIELD, INSN) \ |
482 | 1.03M | ((unsigned int) EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)) |
483 | | |
484 | | /* Extract an unsigned immediate operand on position s with n bits. */ |
485 | | #define EXTRACT_U_IMM(n, s, l) \ |
486 | 0 | RV_X (l, s, n) |
487 | | |
488 | | /* Extract an signed immediate operand on position s with n bits. */ |
489 | | #define EXTRACT_S_IMM(n, s, l) \ |
490 | 0 | RV_X_SIGNED (l, s, n) |
491 | | |
492 | | /* Validate that unsigned n-bit immediate is within bounds. */ |
493 | | #define VALIDATE_U_IMM(v, n) \ |
494 | | ((unsigned long) v < (1UL << n)) |
495 | | |
496 | | /* Validate that signed n-bit immediate is within bounds. */ |
497 | | #define VALIDATE_S_IMM(v, n) \ |
498 | | (v < (long) (1UL << (n-1)) && v >= -(offsetT) (1UL << (n-1))) |
499 | | |
500 | | /* The maximal number of subset can be required. */ |
501 | | #define MAX_SUBSET_NUM 4 |
502 | | |
503 | | /* The range of sregs. */ |
504 | | #define RISCV_SREG_0_7(REGNO) \ |
505 | | ((REGNO == X_S0 || REGNO == X_S1) \ |
506 | | || (REGNO >= X_S2 && REGNO <= X_S7)) |
507 | | |
508 | | /* All RISC-V instructions belong to at least one of these classes. */ |
509 | | enum riscv_insn_class |
510 | | { |
511 | | INSN_CLASS_NONE, |
512 | | |
513 | | INSN_CLASS_I, |
514 | | INSN_CLASS_ZCA, |
515 | | INSN_CLASS_M, |
516 | | INSN_CLASS_F, |
517 | | INSN_CLASS_D, |
518 | | INSN_CLASS_Q, |
519 | | INSN_CLASS_ZCF, |
520 | | INSN_CLASS_ZCD, |
521 | | INSN_CLASS_ZICOND, |
522 | | INSN_CLASS_ZICSR, |
523 | | INSN_CLASS_ZIFENCEI, |
524 | | INSN_CLASS_ZIHINTNTL, |
525 | | INSN_CLASS_ZIHINTNTL_AND_ZCA, |
526 | | INSN_CLASS_ZIHINTPAUSE, |
527 | | INSN_CLASS_ZIMOP, |
528 | | INSN_CLASS_ZMMUL, |
529 | | INSN_CLASS_ZAAMO, |
530 | | INSN_CLASS_ZALASR, |
531 | | INSN_CLASS_ZALRSC, |
532 | | INSN_CLASS_ZAWRS, |
533 | | INSN_CLASS_F_INX, |
534 | | INSN_CLASS_D_INX, |
535 | | INSN_CLASS_Q_INX, |
536 | | INSN_CLASS_ZFH_INX, |
537 | | INSN_CLASS_ZFHMIN, |
538 | | INSN_CLASS_ZFHMIN_INX, |
539 | | INSN_CLASS_ZFHMIN_AND_D_INX, |
540 | | INSN_CLASS_ZFHMIN_AND_Q_INX, |
541 | | INSN_CLASS_ZFBFMIN, |
542 | | INSN_CLASS_ZFA, |
543 | | INSN_CLASS_D_AND_ZFA, |
544 | | INSN_CLASS_Q_AND_ZFA, |
545 | | INSN_CLASS_ZFH_AND_ZFA, |
546 | | INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA, |
547 | | INSN_CLASS_ZBA, |
548 | | INSN_CLASS_ZBB, |
549 | | INSN_CLASS_ZBC, |
550 | | INSN_CLASS_ZBS, |
551 | | INSN_CLASS_ZBKB, |
552 | | INSN_CLASS_ZBKC, |
553 | | INSN_CLASS_ZBKX, |
554 | | INSN_CLASS_ZKND, |
555 | | INSN_CLASS_ZKNE, |
556 | | INSN_CLASS_ZKNH, |
557 | | INSN_CLASS_ZKSED, |
558 | | INSN_CLASS_ZKSH, |
559 | | INSN_CLASS_ZBB_OR_ZBKB, |
560 | | INSN_CLASS_ZBC_OR_ZBKC, |
561 | | INSN_CLASS_ZKND_OR_ZKNE, |
562 | | INSN_CLASS_V, |
563 | | INSN_CLASS_ZVEF, |
564 | | INSN_CLASS_ZVBB, |
565 | | INSN_CLASS_ZVBC, |
566 | | INSN_CLASS_ZVFBFMIN, |
567 | | INSN_CLASS_ZVFBFWMA, |
568 | | INSN_CLASS_ZVFBDOTA32F, |
569 | | INSN_CLASS_ZVFQWBDOTA8F, |
570 | | INSN_CLASS_ZVFQWDOTA8F, |
571 | | INSN_CLASS_ZVFWBDOTA16BF, |
572 | | INSN_CLASS_ZVFWDOTA16BF, |
573 | | INSN_CLASS_ZVKB, |
574 | | INSN_CLASS_ZVKG, |
575 | | INSN_CLASS_ZVKNED, |
576 | | INSN_CLASS_ZVKNHA_OR_ZVKNHB, |
577 | | INSN_CLASS_ZVKSED, |
578 | | INSN_CLASS_ZVKSH, |
579 | | INSN_CLASS_ZVABD, |
580 | | INSN_CLASS_ZVQWBDOTA8I, |
581 | | INSN_CLASS_ZVQWBDOTA16I, |
582 | | INSN_CLASS_ZVQWBDOTA8I_OR_ZVQWBDOTA16I, |
583 | | INSN_CLASS_ZVQWDOTA8I, |
584 | | INSN_CLASS_ZVQWDOTA16I, |
585 | | INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I, |
586 | | INSN_CLASS_ZICFISS, |
587 | | INSN_CLASS_ZICFISS_AND_ZCMOP, |
588 | | INSN_CLASS_ZICFILP, |
589 | | INSN_CLASS_ZCB, |
590 | | INSN_CLASS_ZCB_AND_ZBA, |
591 | | INSN_CLASS_ZCB_AND_ZBB, |
592 | | INSN_CLASS_ZCB_AND_ZMMUL, |
593 | | INSN_CLASS_ZCMOP, |
594 | | INSN_CLASS_ZCMP, |
595 | | INSN_CLASS_ZCMT, |
596 | | INSN_CLASS_SMCTR_OR_SSCTR, |
597 | | INSN_CLASS_ZILSD, |
598 | | INSN_CLASS_ZCLSD, |
599 | | INSN_CLASS_SMRNMI, |
600 | | INSN_CLASS_SVINVAL, |
601 | | INSN_CLASS_ZICBOM, |
602 | | INSN_CLASS_ZICBOP, |
603 | | INSN_CLASS_ZICBOZ, |
604 | | INSN_CLASS_ZABHA, |
605 | | INSN_CLASS_ZACAS, |
606 | | INSN_CLASS_ZABHA_AND_ZACAS, |
607 | | INSN_CLASS_H, |
608 | | INSN_CLASS_XCVALU, |
609 | | INSN_CLASS_XCVBI, |
610 | | INSN_CLASS_XCVBITMANIP, |
611 | | INSN_CLASS_XCVELW, |
612 | | INSN_CLASS_XCVMAC, |
613 | | INSN_CLASS_XCVMEM, |
614 | | INSN_CLASS_XCVSIMD, |
615 | | INSN_CLASS_XTHEADBA, |
616 | | INSN_CLASS_XTHEADBB, |
617 | | INSN_CLASS_XTHEADBS, |
618 | | INSN_CLASS_XTHEADCMO, |
619 | | INSN_CLASS_XTHEADCONDMOV, |
620 | | INSN_CLASS_XTHEADFMEMIDX, |
621 | | INSN_CLASS_XTHEADFMV, |
622 | | INSN_CLASS_XTHEADINT, |
623 | | INSN_CLASS_XTHEADMAC, |
624 | | INSN_CLASS_XTHEADMEMIDX, |
625 | | INSN_CLASS_XTHEADMEMPAIR, |
626 | | INSN_CLASS_XTHEADSYNC, |
627 | | INSN_CLASS_XTHEADVECTOR, |
628 | | INSN_CLASS_XTHEADVDOT, |
629 | | INSN_CLASS_XTHEADZVAMO, |
630 | | INSN_CLASS_XVENTANACONDOPS, |
631 | | INSN_CLASS_XSFVCP, |
632 | | INSN_CLASS_XSFCEASE, |
633 | | INSN_CLASS_XSFVQMACCQOQ, |
634 | | INSN_CLASS_XSFVQMACCDOD, |
635 | | INSN_CLASS_XSFVFNRCLIPXFQF, |
636 | | INSN_CLASS_XMIPSCBOP, |
637 | | INSN_CLASS_XMIPSCMOV, |
638 | | INSN_CLASS_XMIPSEXECTL, |
639 | | INSN_CLASS_XMIPSLSP, |
640 | | INSN_CLASS_XSMTVDOT, |
641 | | INSN_CLASS_XSMTVDOTII, |
642 | | INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII, |
643 | | }; |
644 | | |
645 | | /* This structure holds information for a particular instruction. */ |
646 | | struct riscv_opcode |
647 | | { |
648 | | /* The name of the instruction. */ |
649 | | const char *name; |
650 | | |
651 | | /* The requirement of xlen for the instruction, 0 if no requirement. */ |
652 | | unsigned xlen_requirement; |
653 | | |
654 | | /* Class to which this instruction belongs. Used to decide whether or |
655 | | not this instruction is legal in the current -march context. */ |
656 | | enum riscv_insn_class insn_class; |
657 | | |
658 | | /* A string describing the arguments for this instruction. */ |
659 | | const char *args; |
660 | | |
661 | | /* The basic opcode for the instruction. When assembling, this |
662 | | opcode is modified by the arguments to produce the actual opcode |
663 | | that is used. If pinfo is INSN_MACRO, then this is 0. */ |
664 | | insn_t match; |
665 | | |
666 | | /* If pinfo is not INSN_MACRO, then this is a bit mask for the |
667 | | relevant portions of the opcode when disassembling. If the |
668 | | actual opcode anded with the match field equals the opcode field, |
669 | | then we have found the correct instruction. If pinfo is |
670 | | INSN_MACRO, then this field is the macro identifier. */ |
671 | | insn_t mask; |
672 | | |
673 | | /* A function to determine if a word corresponds to this instruction. |
674 | | Usually, this computes ((word & mask) == match). */ |
675 | | int (*match_func) (const struct riscv_opcode *op, insn_t word); |
676 | | |
677 | | /* For a macro, this is INSN_MACRO. Otherwise, it is a collection |
678 | | of bits describing the instruction, notably any relevant hazard |
679 | | information. */ |
680 | | unsigned long pinfo; |
681 | | }; |
682 | | |
683 | | /* Instruction is a simple alias (e.g. "mv" for "addi"). */ |
684 | 0 | #define INSN_ALIAS 0x00000001 |
685 | | |
686 | | /* These are for setting insn_info fields. |
687 | | |
688 | | Nonbranch is the default. Noninsn is used only if there is no match. |
689 | | There are no condjsr or dref2 instructions. So that leaves condbranch, |
690 | | branch, jsr, and dref that we need to handle here, encoded in 3 bits. */ |
691 | 1.41M | #define INSN_TYPE 0x0000000e |
692 | | |
693 | | /* Instruction is an unconditional branch. */ |
694 | 24.7k | #define INSN_BRANCH 0x00000002 |
695 | | /* Instruction is a conditional branch. */ |
696 | 60.5k | #define INSN_CONDBRANCH 0x00000004 |
697 | | /* Instruction is a jump to subroutine. */ |
698 | 10.4k | #define INSN_JSR 0x00000006 |
699 | | /* Instruction is a data reference. */ |
700 | 494k | #define INSN_DREF 0x00000008 |
701 | | /* Instruction is allowed when eew >= 64. */ |
702 | 1.41M | #define INSN_V_EEW64 0x10000000 |
703 | | |
704 | | /* We have 5 data reference sizes, which we can encode in 3 bits. */ |
705 | 1.91M | #define INSN_DATA_SIZE 0x00000070 |
706 | 494k | #define INSN_DATA_SIZE_SHIFT 4 |
707 | | #define INSN_1_BYTE 0x00000010 |
708 | | #define INSN_2_BYTE 0x00000020 |
709 | | #define INSN_4_BYTE 0x00000030 |
710 | | #define INSN_8_BYTE 0x00000040 |
711 | | #define INSN_16_BYTE 0x00000050 |
712 | | |
713 | | /* Instruction is actually a macro. It should be ignored by the |
714 | | disassembler, and requires special treatment by the assembler. */ |
715 | 1.10G | #define INSN_MACRO 0xffffffff |
716 | | |
717 | | /* This is a list of macro expanded instructions. */ |
718 | | enum |
719 | | { |
720 | | M_LA, |
721 | | M_LLA, |
722 | | M_LGA, |
723 | | M_LA_TLS_GD, |
724 | | M_LA_TLS_IE, |
725 | | M_Lx, |
726 | | M_FLx, |
727 | | M_Sx_FSx, |
728 | | M_CALL, |
729 | | M_LI, |
730 | | M_EXTH, |
731 | | M_ZEXTW, |
732 | | M_SEXTB, |
733 | | M_VMSGE, |
734 | | M_NUM_MACROS |
735 | | }; |
736 | | |
737 | | /* The mapping symbol states. */ |
738 | | enum riscv_seg_mstate |
739 | | { |
740 | | MAP_NONE = 0, /* Must be zero, for seginfo in new sections. */ |
741 | | MAP_DATA, /* Data. */ |
742 | | MAP_INSN, /* Instructions. */ |
743 | | }; |
744 | | |
745 | | #define NRC (4 + 1) /* Max characters in register names, incl nul. */ |
746 | | |
747 | | extern const char riscv_gpr_names_numeric[NGPR][NRC]; |
748 | | extern const char riscv_gpr_names_abi[NGPR][NRC]; |
749 | | extern const char riscv_fpr_names_numeric[NFPR][NRC]; |
750 | | extern const char riscv_fpr_names_abi[NFPR][NRC]; |
751 | | extern const char * const riscv_rm[8]; |
752 | | extern const char * const riscv_pred_succ[16]; |
753 | | extern const char riscv_vecr_names_numeric[NVECR][NRC]; |
754 | | extern const char riscv_vecm_names_numeric[NVECM][NRC]; |
755 | | extern const char * const riscv_vsew[8]; |
756 | | extern const char * const riscv_vsew_altfmt[2]; |
757 | | extern const char * const riscv_vlmul[8]; |
758 | | extern const char * const riscv_vta[2]; |
759 | | extern const char * const riscv_vma[2]; |
760 | | extern const char * const riscv_th_vlen[4]; |
761 | | extern const char * const riscv_th_vediv[4]; |
762 | | extern const char * const riscv_fli_symval[32]; |
763 | | extern const float riscv_fli_numval[32]; |
764 | | |
765 | | extern const struct riscv_opcode riscv_opcodes[]; |
766 | | extern const struct riscv_opcode riscv_insn_types[]; |
767 | | |
768 | | extern unsigned int riscv_get_sp_base (insn_t, unsigned int); |
769 | | |
770 | | #endif /* _RISCV_H_ */ |