/* tc-i386.c -- Assemble code for the Intel 80386

   Copyright (C) 1989-2026 Free Software Foundation, Inc.

   This file is part of GAS, the GNU Assembler.

   GAS is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3, or (at your option)

   any later version.

   GAS is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with GAS; see the file COPYING.  If not, write to the Free

   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA

   02110-1301, USA.  */

/* Intel 80386 machine specific gas.

   Written by Eliot Dresselhaus (eliot@mgm.mit.edu).

   x86_64 support by Jan Hubicka (jh@suse.cz)

   VIA PadLock support by Michal Ludvig (mludvig@suse.cz)

   Bugs & suggestions are completely welcome.  This is free software.

   Please help us make it better.  */

#include "as.h"

#include "safe-ctype.h"

#include "subsegs.h"

#include "dwarf2dbg.h"

#include "dw2gencfi.h"

#include "scfi.h"

#include "gen-sframe.h"

#include "sframe.h"

#include "elf/x86-64.h"

#include "opcodes/i386-init.h"

#include "opcodes/i386-mnem.h"

#include <limits.h>

#ifndef INFER_ADDR_PREFIX

#define INFER_ADDR_PREFIX 1

#endif

#ifndef DEFAULT_ARCH

#define DEFAULT_ARCH "i386"

#endif

#ifndef INLINE

#if __GNUC__ >= 2

#define INLINE __inline__

#else

#define INLINE

#endif

#endif

/* Prefixes will be emitted in the order defined below.

   WAIT_PREFIX must be the first prefix since FWAIT is really is an

   instruction, and so must come before any prefixes.

   The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,

   REP_PREFIX/HLE_PREFIX, LOCK_PREFIX.  */

#define WAIT_PREFIX 0

#define SEG_PREFIX  1

#define ADDR_PREFIX 2

#define DATA_PREFIX 3

#define REP_PREFIX  4

#define HLE_PREFIX  REP_PREFIX

#define BND_PREFIX  REP_PREFIX

#define LOCK_PREFIX 5

#define REX_PREFIX  6       /* must come last.  */

#define MAX_PREFIXES  7 /* max prefixes per opcode */

/* we define the syntax here (modulo base,index,scale syntax) */

#define REGISTER_PREFIX '%'

#define IMMEDIATE_PREFIX '$'

#define ABSOLUTE_PREFIX '*'

/* these are the instruction mnemonic suffixes in AT&T syntax or

   memory operand size in Intel syntax.  */

#define WORD_MNEM_SUFFIX  'w'

#define BYTE_MNEM_SUFFIX  'b'

#define SHORT_MNEM_SUFFIX 's'

#define LONG_MNEM_SUFFIX  'l'

#define QWORD_MNEM_SUFFIX  'q'

#define END_OF_INSN '\0'

#define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }

/* This matches the C -> StaticRounding alias in the opcode table.  */

#define commutative staticrounding

/*

  'templates' is for grouping together 'template' structures for opcodes

  of the same name.  This is only used for storing the insns in the grand

  ole hash table of insns.

  The templates themselves start at START and range up to (but not including)

  END.

  */

typedef struct

{

  const insn_template *start;

  const insn_template *end;

}

templates;

/* 386 operand encoding bytes:  see 386 book for details of this.  */

typedef struct

{

  unsigned int regmem;  /* codes register or memory operand */

  unsigned int reg; /* codes register operand (or extended opcode) */

  unsigned int mode;  /* how to interpret regmem & reg */

}

modrm_byte;

/* x86-64 extension prefix.  */

typedef int rex_byte;

/* 386 opcode byte to code indirect addressing.  */

typedef struct

{

  unsigned base;

  unsigned index;

  unsigned scale;

}

sib_byte;

/* x86 arch names, types and features */

typedef struct

{

  const char *name;   /* arch name */

  unsigned int len:8;   /* arch string length */

  bool skip:1;      /* show_arch should skip this. */

  enum processor_type type; /* arch type */

  enum { vsz_none, vsz_set, vsz_reset } vsz; /* vector size control */

  i386_cpu_flags enable;    /* cpu feature enable flags */

  i386_cpu_flags disable; /* cpu feature disable flags */

}

arch_entry;

/* Modes for parse_insn() to operate in.  */

enum parse_mode {

  parse_all,

  parse_prefix,

  parse_pseudo_prefix,

};

static void update_code_flag (int, int);

static void s_insn (int);

static void s_noopt (int);

static void set_code_flag (int);

static void set_16bit_gcc_code_flag (int);

static void set_intel_syntax (int);

static void set_intel_mnemonic (int);

static void set_allow_index_reg (int);

static void set_check (int);

static void set_cpu_arch (int);

#ifdef TE_PE

static void pe_directive_secrel (int);

static void pe_directive_secidx (int);

#endif

static void signed_cons (int);

static char *output_invalid (int c);

static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,

            const char *);

static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,

               const char *);

static int i386_att_operand (char *);

static int i386_intel_operand (char *, int);

static int i386_intel_simplify (expressionS *);

static int i386_intel_parse_name (const char *, expressionS *, enum expr_mode);

static const reg_entry *parse_register (const char *, char **);

static const char *parse_insn (const char *, char *, enum parse_mode);

static char *parse_operands (char *, const char *);

static void copy_operand (unsigned int, unsigned int);

static void swap_operands (void);

static void swap_2_operands (unsigned int, unsigned int);

static enum i386_flag_code i386_addressing_mode (void);

static void optimize_imm (void);

static bool optimize_disp (const insn_template *t);

static const insn_template *match_template (char);

static int check_string (void);

static int process_suffix (const insn_template *);

static int check_byte_reg (void);

static int check_long_reg (void);

static int check_qword_reg (void);

static int check_word_reg (void);

static int finalize_imm (void);

static int process_operands (void);

static const reg_entry *build_modrm_byte (void);

static void output_insn (const struct last_insn *);

static void output_imm (fragS *, offsetT);

static void output_disp (fragS *, offsetT);

#ifdef OBJ_AOUT

static void s_bss (int);

#endif

#ifdef OBJ_ELF

static void handle_large_common (int small ATTRIBUTE_UNUSED);

/* GNU_PROPERTY_X86_ISA_1_USED.  */

static unsigned int x86_isa_1_used;

/* GNU_PROPERTY_X86_FEATURE_2_USED.  */

static unsigned int x86_feature_2_used;

/* Generate x86 used ISA and feature properties.  */

static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE;

#endif

static const char *default_arch = DEFAULT_ARCH;

/* parse_register() returns this when a register alias cannot be used.  */

static const reg_entry bad_reg = { "<bad>", OPERAND_TYPE_NONE, 0, 0,

           { Dw2Inval, Dw2Inval } };

static const reg_entry *reg_eax;

static const reg_entry *reg_ds;

static const reg_entry *reg_es;

static const reg_entry *reg_ss;

static const reg_entry *reg_st0;

static const reg_entry *reg_k0;

/* VEX prefix.  */

typedef struct

{

  /* VEX prefix is either 2 byte or 3 byte.  EVEX is 4 byte.  */

  unsigned char bytes[4];

  unsigned int length;

  /* Destination or source register specifier.  */

  const reg_entry *register_specifier;

} vex_prefix;

/* 'md_assemble ()' gathers together information and puts it into a

   i386_insn.  */

union i386_op

  {

    expressionS *disps;

    expressionS *imms;

    const reg_entry *regs;

  };

enum i386_error

  {

    no_error, /* Must be first.  */

    operand_size_mismatch,

    operand_type_mismatch,

    register_type_mismatch,

    number_of_operands_mismatch,

    invalid_instruction_suffix,

    bad_imm4,

    unsupported_with_intel_mnemonic,

    unsupported_syntax,

    unsupported_EGPR_for_addressing,

    unsupported_nf,

    unsupported,

    unsupported_on_arch,

    unsupported_64bit,

    no_vex_encoding,

    no_evex_encoding,

    invalid_sib_address,

    invalid_vsib_address,

    invalid_vector_register_set,

    invalid_tmm_register_set,

    invalid_dest_and_src_register_set,

    invalid_dest_register_set,

    invalid_pseudo_prefix,

    unsupported_vector_index_register,

    unsupported_broadcast,

    broadcast_needed,

    unsupported_masking,

    mask_not_on_destination,

    no_default_mask,

    unsupported_rc_sae,

    unsupported_vector_size,

    unsupported_rsp_register,

    internal_error,

  };

#ifdef OBJ_ELF

enum x86_tls_error_type

{

  x86_tls_error_continue,

  x86_tls_error_none,

  x86_tls_error_insn,

  x86_tls_error_opcode,

  x86_tls_error_sib,

  x86_tls_error_no_base_reg,

  x86_tls_error_require_no_base_index_reg,

  x86_tls_error_base_reg,

  x86_tls_error_index_ebx,

  x86_tls_error_eax,

  x86_tls_error_RegA,

  x86_tls_error_ebx,

  x86_tls_error_rip,

  x86_tls_error_dest_eax,

  x86_tls_error_dest_rdi,

  x86_tls_error_scale_factor,

  x86_tls_error_base_reg_size,

  x86_tls_error_dest_32bit_reg_size,

  x86_tls_error_dest_64bit_reg_size,

  x86_tls_error_dest_32bit_or_64bit_reg_size

};

#endif

struct _i386_insn

  {

    /* TM holds the template for the insn were currently assembling.  */

    insn_template tm;

    /* TM_TYPES are the operand types as referenced by TM.  */

    i386_operand_type tm_types[MAX_OPERANDS];

    /* SUFFIX holds the instruction size suffix for byte, word, dword

       or qword, if given.  */

    char suffix;

    /* OPCODE_LENGTH holds the number of base opcode bytes.  */

    unsigned char opcode_length;

    /* OPERANDS gives the number of given operands.  */

    unsigned int operands;

    /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number

       of given register, displacement, memory operands and immediate

       operands.  */

    unsigned int reg_operands, disp_operands, mem_operands, imm_operands;

    /* TYPES [i] is the type (see above #defines) which tells us how to

       use OP[i] for the corresponding operand.  */

    i386_operand_type types[MAX_OPERANDS];

    /* Displacement expression, immediate expression, or register for each

       operand.  */

    union i386_op op[MAX_OPERANDS];

    /* Flags for operands.  */

    unsigned int flags[MAX_OPERANDS];

#define Operand_PCrel 1

#define Operand_Mem   2

#define Operand_Signed 4 /* .insn only */

    /* Relocation type for operand */

    enum bfd_reloc_code_real reloc[MAX_OPERANDS];

    /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode

       the base index byte below.  */

    const reg_entry *base_reg;

    const reg_entry *index_reg;

    unsigned int log2_scale_factor;

    /* SEG gives the seg_entries of this insn.  They are zero unless

       explicit segment overrides are given.  */

    const reg_entry *seg[2];

    /* PREFIX holds all the given prefix opcodes (usually null).

       PREFIXES is the number of prefix opcodes.  */

    unsigned int prefixes;

    unsigned char prefix[MAX_PREFIXES];

    /* .insn allows for reserved opcode spaces.  */

    unsigned char insn_opcode_space;

    /* .insn also allows (requires) specifying immediate size.  */

    unsigned char imm_bits[MAX_OPERANDS];

    /* Register is in low 3 bits of opcode.  */

    bool short_form;

    /* The operand to a branch insn indicates an absolute branch.  */

    bool jumpabsolute;

    /* The operand to a branch insn indicates a far branch.  */

    bool far_branch;

    /* There is a memory operand of (%dx) which should be only used

       with input/output instructions.  */

    bool input_output_operand;

    /* Extended states.  */

    enum

      {

  /* Use MMX state.  */

  xstate_mmx = 1 << 0,

  /* Use XMM state.  */

  xstate_xmm = 1 << 1,

  /* Use YMM state.  */

  xstate_ymm = 1 << 2 | xstate_xmm,

  /* Use ZMM state.  */

  xstate_zmm = 1 << 3 | xstate_ymm,

  /* Use TMM state.  */

  xstate_tmm = 1 << 4,

  /* Use MASK state.  */

  xstate_mask = 1 << 5

      } xstate;

    /* Has GOTPC or TLS relocation.  */

    bool has_gotpc_tls_reloc;

    /* Has relocation entry from the gotrel array.  */

    bool has_gotrel;

    /* RM and SIB are the modrm byte and the sib byte where the

       addressing modes of this insn are encoded.  */

    modrm_byte rm;

    rex_byte rex;

    rex_byte vrex;

    rex_byte rex2;

    sib_byte sib;

    vex_prefix vex;

    /* Masking attributes.

       The struct describes masking, applied to OPERAND in the instruction.

       REG is a pointer to the corresponding mask register.  ZEROING tells

       whether merging or zeroing mask is used.  */

    struct Mask_Operation

    {

      const reg_entry *reg;

      unsigned int zeroing;

      /* The operand where this operation is associated.  */

      unsigned int operand;

    } mask;

    /* Rounding control and SAE attributes.  */

    struct RC_Operation

    {

      enum rc_type

  {

    rc_none = -1,

    rne,

    rd,

    ru,

    rz,

    saeonly

  } type;

      /* In Intel syntax the operand modifier form is supposed to be used, but

   we continue to accept the immediate forms as well.  */

      bool modifier;

    } rounding;

    /* Broadcasting attributes.

       The struct describes broadcasting, applied to OPERAND.  TYPE is

       expresses the broadcast factor.  */

    struct Broadcast_Operation

    {

      /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}.  */

      unsigned int type;

      /* Index of broadcasted operand.  */

      unsigned int operand;

      /* Number of bytes to broadcast.  */

      unsigned int bytes;

    } broadcast;

    /* Compressed disp8*N attribute.  */

    unsigned int memshift;

    /* SCC = EVEX.[SC3,SC2,SC1,SC0].  */

    unsigned int scc;

    /* Store 4 bits of EVEX.[OF,SF,ZF,CF].  */

#define OSZC_CF 1

#define OSZC_ZF 2

#define OSZC_SF 4

#define OSZC_OF 8

    unsigned int oszc_flags;

    /* Invert the condition encoded in a base opcode.  */

    bool invert_cond;

    /* REP prefix.  */

    const char *rep_prefix;

    /* HLE prefix.  */

    const char *hle_prefix;

    /* Have BND prefix.  */

    const char *bnd_prefix;

    /* Have NOTRACK prefix.  */

    const char *notrack_prefix;

    /* Error message.  */

    enum i386_error error;

  };

typedef struct _i386_insn i386_insn;

/* Pseudo-prefix recording state, separate from i386_insn.  */

static struct pseudo_prefixes {

  /* How to encode instructions.  */

  enum {

    encoding_default = 0,

    encoding_vex,

    encoding_vex3,

    encoding_egpr, /* REX2 or EVEX.  */

    encoding_evex,

    encoding_evex512,

    encoding_error

  } encoding;

  /* Prefer load or store in encoding.  */

  enum {

    dir_encoding_default = 0,

    dir_encoding_load,

    dir_encoding_store,

    dir_encoding_swap

  } dir_encoding;

  /* Prefer 8bit, 16bit, 32bit displacement in encoding.  */

  enum {

    disp_encoding_default = 0,

    disp_encoding_8bit,

    disp_encoding_16bit,

    disp_encoding_32bit

  } disp_encoding;

  /* Exclude sign-extended 8bit immediate in encoding.  */

  bool no_imm8s;

  /* Prefer the REX byte in encoding.  */

  bool rex_encoding;

  /* Prefer the REX2 prefix in encoding.  */

  bool rex2_encoding;

  /* No CSPAZO flags update.  */

  bool has_nf;

  /* Disable instruction size optimization.  */

  bool no_optimize;

} pp;

/* Link RC type with corresponding string, that'll be looked for in

   asm.  */

struct RC_name

{

  enum rc_type type;

  const char *name;

  unsigned int len;

};

static const struct RC_name RC_NamesTable[] =

{

  {  rne, STRING_COMMA_LEN ("rn-sae") },

  {  rd,  STRING_COMMA_LEN ("rd-sae") },

  {  ru,  STRING_COMMA_LEN ("ru-sae") },

  {  rz,  STRING_COMMA_LEN ("rz-sae") },

  {  saeonly,  STRING_COMMA_LEN ("sae") },

};

/* To be indexed by segment register number.  */

static const unsigned char i386_seg_prefixes[] = {

  ES_PREFIX_OPCODE,

  CS_PREFIX_OPCODE,

  SS_PREFIX_OPCODE,

  DS_PREFIX_OPCODE,

  FS_PREFIX_OPCODE,

  GS_PREFIX_OPCODE

};

/* List of chars besides those in app.c:symbol_chars that can start an

   operand.  Used to prevent the scrubber eating vital white-space.  */

const char extra_symbol_chars[] = "*%-(["

#ifdef LEX_AT

  "@"

#endif

#ifdef LEX_QM

  "?"

#endif

  ;

#if (defined (OBJ_ELF)          \

     && !defined (TE_GNU)       \

     && !defined (TE_LINUX)       \

     && !defined (TE_Haiku)       \

     && !defined (TE_FreeBSD)       \

     && !defined (TE_DragonFly)       \

     && !defined (TE_NetBSD))

/* This array holds the chars that always start a comment.  If the

   pre-processor is disabled, these aren't very useful.  The option

   --divide will remove '/' from this list.  */

const char *i386_comment_chars = "#/";

#define SVR4_COMMENT_CHARS 1

#define PREFIX_SEPARATOR '\\'

#else

const char *i386_comment_chars = "#";

#define PREFIX_SEPARATOR '/'

#endif

/* This array holds the chars that only start a comment at the beginning of

   a line.  If the line seems to have the form '# 123 filename'

   .line and .file directives will appear in the pre-processed output.

   Note that input_file.c hand checks for '#' at the beginning of the

   first line of the input file.  This is because the compiler outputs

   #NO_APP at the beginning of its output.

   Also note that comments started like this one will always work if

   '/' isn't otherwise defined.  */

const char line_comment_chars[] = "#/";

const char line_separator_chars[] = ";";

/* Chars that can be used to separate mant from exp in floating point

   nums.  */

const char EXP_CHARS[] = "eE";

/* Chars that mean this number is a floating point constant

   As in 0f12.456

   or    0d1.2345e12.  */

const char FLT_CHARS[] = "fFdDxXhHbB";

/* Tables for lexical analysis.  */

static char mnemonic_chars[256];

static char register_chars[256];

static char operand_chars[256];

/* Lexical macros.  */

#define is_operand_char(x) (operand_chars[(unsigned char) x])

#define is_register_char(x) (register_chars[(unsigned char) x])

/* All non-digit non-letter characters that may occur in an operand and

   which aren't already in extra_symbol_chars[].  */

static const char operand_special_chars[] = "$+,)._~/<>|&^!=:@]{}";

/* md_assemble() always leaves the strings it's passed unaltered.  To

   effect this we maintain a stack of saved characters that we've smashed

   with '\0's (indicating end of strings for various sub-fields of the

   assembler instruction).  */

static char save_stack[32];

static char *save_stack_p;

#define END_STRING_AND_SAVE(s) \

  do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)

#define RESTORE_END_STRING(s) \

  do { *(s) = *--save_stack_p; } while (0)

/* The instruction we're assembling.  */

static i386_insn i;

/* Possible templates for current insn.  */

static templates current_templates;

/* Per instruction expressionS buffers: max displacements & immediates.  */

static expressionS disp_expressions[MAX_MEMORY_OPERANDS];

static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];

/* Current operand we are working on.  */

static int this_operand = -1;

/* Are we processing a .insn directive?  */

#define dot_insn() (i.tm.mnem_off == MN__insn)

static enum i386_flag_code i386_flag_code;

#define flag_code i386_flag_code /* Permit to continue using original name.  */

static unsigned int object_64bit;

static unsigned int disallow_64bit_reloc;

static int use_rela_relocations = 0;

/* __tls_get_addr/___tls_get_addr symbol for TLS.  */

static const char *tls_get_addr;

#ifdef OBJ_ELF

/* The ELF ABI to use.  */

enum x86_elf_abi

{

  I386_ABI,

  X86_64_ABI,

  X86_64_X32_ABI

};

static enum x86_elf_abi x86_elf_abi = I386_ABI;

#endif

#if defined (TE_PE) || defined (TE_PEP)

/* Use big object file format.  */

static int use_big_obj = 0;

#endif

#ifdef OBJ_ELF

/* 1 if generating code for a shared library.  */

static int shared = 0;

const unsigned int x86_sframe_cfa_sp_reg = REG_SP;

/* The other CFA base register for SFrame stack trace info.  */

const unsigned int x86_sframe_cfa_fp_reg = REG_FP;

/* The return address register for SFrame stack trace info.  For AMD64, RA

   tracking is not needed, but some directives like .cfi_undefined may use

   RA to indicate the outermost frame.  */

const unsigned int x86_sframe_cfa_ra_reg = REG_RA;

static ginsnS *x86_ginsn_new (const symbolS *, enum ginsn_gen_mode);

#endif

/* 1 for intel syntax,

   0 if att syntax.  */

static int intel_syntax = 0;

static enum x86_64_isa

{

  amd64 = 1,  /* AMD64 ISA.  */

  intel64 /* Intel64 ISA.  */

} isa64;

/* 1 for intel mnemonic,

   0 if att mnemonic.  */

static int intel_mnemonic = !SYSV386_COMPAT;

/* 1 if pseudo registers are permitted.  */

static int allow_pseudo_reg = 0;

/* 1 if register prefix % not required.  */

static int allow_naked_reg = 0;

/* 1 if the assembler should add BND prefix for all control-transferring

   instructions supporting it, even if this prefix wasn't specified

   explicitly.  */

static int add_bnd_prefix = 0;

/* 1 if pseudo index register, eiz/riz, is allowed .  */

static int allow_index_reg = 0;

/* 1 if the assembler should ignore LOCK prefix, even if it was

   specified explicitly.  */

static int omit_lock_prefix = 0;

/* 1 if the assembler should encode lfence, mfence, and sfence as

   "lock addl $0, (%{re}sp)".  */

static int avoid_fence = 0;

/* 1 if lfence should be inserted after every load.  */

static int lfence_after_load = 0;

/* Non-zero if lfence should be inserted before indirect branch.  */

static enum lfence_before_indirect_branch_kind

  {

    lfence_branch_none = 0,

    lfence_branch_register,

    lfence_branch_memory,

    lfence_branch_all

  }

lfence_before_indirect_branch;

/* Non-zero if lfence should be inserted before ret.  */

static enum lfence_before_ret_kind

  {

    lfence_before_ret_none = 0,

    lfence_before_ret_not,

    lfence_before_ret_or,

    lfence_before_ret_shl

  }

lfence_before_ret;

/* 1 if the assembler should generate relax relocations.  */

#ifdef TE_SOLARIS

/* PR gas/19520: The Solaris/x86 linker cannot handle relax relocations

   before Solaris 11.4 which cannot easily be detected in cross

   configurations.  */

#define DEFAULT_GENERATE_X86_RELAX_RELOCATIONS 0

#else

#define DEFAULT_GENERATE_X86_RELAX_RELOCATIONS 1

#endif

static int generate_relax_relocations

  = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;

/* 1 if the assembler should check tls relocation.  */

static bool tls_check = DEFAULT_X86_TLS_CHECK;

static enum check_kind

  {

    check_none = 0,

    check_warning,

    check_error

  }

sse_check, operand_check = check_warning;

/* Non-zero if branches should be aligned within power of 2 boundary.  */

static int align_branch_power = 0;

/* Types of branches to align.  */

enum align_branch_kind

  {

    align_branch_none = 0,

    align_branch_jcc = 1,

    align_branch_fused = 2,

    align_branch_jmp = 3,

    align_branch_call = 4,

    align_branch_indirect = 5,

    align_branch_ret = 6

  };

/* Type bits of branches to align.  */

enum align_branch_bit

  {

    align_branch_jcc_bit = 1 << align_branch_jcc,

    align_branch_fused_bit = 1 << align_branch_fused,

    align_branch_jmp_bit = 1 << align_branch_jmp,

    align_branch_call_bit = 1 << align_branch_call,

    align_branch_indirect_bit = 1 << align_branch_indirect,

    align_branch_ret_bit = 1 << align_branch_ret

  };

static unsigned int align_branch = (align_branch_jcc_bit

            | align_branch_fused_bit

            | align_branch_jmp_bit);

/* Types of condition jump used by macro-fusion.  */

enum mf_jcc_kind

  {

    mf_jcc_jo = 0,  /* base opcode 0x70  */

    mf_jcc_jc,      /* base opcode 0x72  */

    mf_jcc_je,      /* base opcode 0x74  */

    mf_jcc_jna,     /* base opcode 0x76  */

    mf_jcc_js,      /* base opcode 0x78  */

    mf_jcc_jp,      /* base opcode 0x7a  */

    mf_jcc_jl,      /* base opcode 0x7c  */

    mf_jcc_jle,     /* base opcode 0x7e  */

  };

/* Types of compare flag-modifying insntructions used by macro-fusion.  */

enum mf_cmp_kind

  {

    mf_cmp_test_and,  /* test/cmp */

    mf_cmp_alu_cmp,  /* add/sub/cmp */

    mf_cmp_incdec  /* inc/dec */

  };

/* The maximum padding size for fused jcc.  CMP like instruction can

   be 9 bytes and jcc can be 6 bytes.  Leave room just in case for

   prefixes.   */

#define MAX_FUSED_JCC_PADDING_SIZE 20

/* The maximum number of prefixes added for an instruction.  */

static unsigned int align_branch_prefix_size = 5;

/* Optimization:

   1. Clear the REX_W bit with register operand if possible.

   2. Above plus use 128bit vector instruction to clear the full vector

      register.

 */

static int optimize = 0;

/* Optimization:

   1. Clear the REX_W bit with register operand if possible.

   2. Above plus use 128bit vector instruction to clear the full vector

      register.

   3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to

      "testb $imm7,%r8".

 */

static int optimize_for_space = 0;

/* Disabled optimizations.  */

static int optimize_for_disabled_optimizations = 0;

/* Register prefix used for error message.  */

static const char *register_prefix = "%";

/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,

   leave, push, and pop instructions so that gcc has the same stack

   frame as in 32 bit mode.  */

static char stackop_size = '\0';

/* Non-zero to optimize code alignment.  */

int optimize_align_code = 1;

/* Non-zero to quieten some warnings.  */

static int quiet_warnings = 0;

/* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs.  */

static bool pre_386_16bit_warned;

/* CPU name.  */

static const char *cpu_arch_name = NULL;

static char *cpu_sub_arch_name = NULL;

/* CPU feature flags.  */

static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;

/* ISA extensions available in 64-bit mode only.  */

static const i386_cpu_flags cpu_64_flags = CPU_ANY_64_FLAGS;

/* If we have selected a cpu we are generating instructions for.  */

static int cpu_arch_tune_set = 0;

/* Cpu we are generating instructions for.  */

static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;

/* CPU instruction set architecture used.  */

static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;

/* CPU feature flags of instruction set architecture used.  */

static i386_cpu_flags cpu_arch_isa_flags;

/* If set, conditional jumps are not automatically promoted to handle

   larger than a byte offset.  */

static bool no_cond_jump_promotion = false;

/* This will be set from an expression parser hook if there's any

   applicable operator involved in an expression.  */

static enum {

  expr_operator_none,

  expr_operator_present,

  expr_large_value,

} expr_mode;

/* Encode SSE instructions with VEX prefix.  */

static unsigned int sse2avx;

/* Encode aligned vector move as unaligned vector move.  */

static unsigned int use_unaligned_vector_move;

/* Maximum permitted vector size. */

#define VSZ128 0

#define VSZ256 1

#define VSZ512 2

#define VSZ_DEFAULT VSZ512

static unsigned int vector_size = VSZ_DEFAULT;

/* Encode scalar AVX instructions with specific vector length.  */

static enum

  {

    vex128 = 0,

    vex256

  } avxscalar;

/* Encode VEX WIG instructions with specific vex.w.  */

static enum

  {

    vexw0 = 0,

    vexw1

  } vexwig;

/* Encode scalar EVEX LIG instructions with specific vector length.  */

static enum

  {

    evexl128 = 0,

    evexl256,

    evexl512

  } evexlig;

/* Encode EVEX WIG instructions with specific evex.w.  */

static enum

  {

    evexw0 = 0,

    evexw1

  } evexwig;

/* Value to encode in EVEX RC bits, for SAE-only instructions.  */

static enum rc_type evexrcig = rne;

/* Pre-defined "_GLOBAL_OFFSET_TABLE_".  */

static symbolS *GOT_symbol;

/* The dwarf2 return column, adjusted for 32 or 64 bit.  */

unsigned int x86_dwarf2_return_column;

/* The dwarf2 data alignment, adjusted for 32 or 64 bit.  */

int x86_cie_data_alignment;

/* Interface to relax_segment.

   There are 3 major relax states for 386 jump insns because the

   different types of jumps add different sizes to frags when we're

   figuring out what sort of jump to choose to reach a given label.

   BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align

   branches which are handled by md_estimate_size_before_relax() and

   i386_generic_table_relax_frag().  */

/* Types.  */

#define UNCOND_JUMP 0

#define COND_JUMP 1

#define COND_JUMP86 2

#define BRANCH_PADDING 3

#define BRANCH_PREFIX 4

#define FUSED_JCC_PADDING 5

/* Sizes.  */

#define CODE16  1

#define SMALL 0

#define SMALL16 (SMALL | CODE16)

#define BIG 2

#define BIG16 (BIG | CODE16)

#ifndef INLINE

#ifdef __GNUC__

#define INLINE __inline__

#else

#define INLINE

#endif

#endif

#define ENCODE_RELAX_STATE(type, size) \

  ((relax_substateT) (((type) << 2) | (size)))

#define TYPE_FROM_RELAX_STATE(s) \

  ((s) >> 2)

#define DISP_SIZE_FROM_RELAX_STATE(s) \

    ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))

/* This table is used by relax_frag to promote short jumps to long

   ones where necessary.  SMALL (short) jumps may be promoted to BIG

   (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long).  We

   don't allow a short jump in a 32 bit code segment to be promoted to

   a 16 bit offset jump because it's slower (requires data size

   prefix), and doesn't work, unless the destination is in the bottom

   64k of the code segment (The top 16 bits of eip are zeroed).  */

const relax_typeS md_relax_table[] =

{

  /* The fields are:

     1) most positive reach of this state,

     2) most negative reach of this state,

     3) how many bytes this mode will have in the variable part of the frag

     4) which index into the table to try if we can't fit into this one.  */

  /* UNCOND_JUMP states.  */

  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},

  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},

  /* dword jmp adds 4 bytes to frag:

     0 extra opcode bytes, 4 displacement bytes.  */

  {0, 0, 4, 0},

  /* word jmp adds 2 byte2 to frag:

     0 extra opcode bytes, 2 displacement bytes.  */

  {0, 0, 2, 0},

  /* COND_JUMP states.  */

  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},

  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},

  /* dword conditionals adds 5 bytes to frag:

     1 extra opcode byte, 4 displacement bytes.  */

  {0, 0, 5, 0},

  /* word conditionals add 3 bytes to frag:

     1 extra opcode byte, 2 displacement bytes.  */

  {0, 0, 3, 0},

  /* COND_JUMP86 states.  */

  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},

  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},

  /* dword conditionals adds 5 bytes to frag:

     1 extra opcode byte, 4 displacement bytes.  */

  {0, 0, 5, 0},

  /* word conditionals add 4 bytes to frag:

     1 displacement byte and a 3 byte long branch insn.  */

  {0, 0, 4, 0}

};

#define ARCH(n, t, f, s) \

  { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \

    CPU_NONE_FLAGS }

#define SUBARCH(n, e, d, s) \

  { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \

    CPU_ ## d ## _FLAGS }

#define VECARCH(n, e, d, v) \

  { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \

    CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }

#define CPU_ANY_APX_NCI_NDD_NF_FLAGS \

  { .bitfield = \

    { .cpuapx_nci = true, \

      .cpuapx_ndd = true, \

      .cpuapx_nf = true } }

static const arch_entry cpu_arch[] =

{

  /* Do not replace the first two entries - i386_target_format() and

     set_cpu_arch() rely on them being there in this order.  */

  ARCH (generic32, GENERIC32, GENERIC32, false),

  ARCH (generic64, GENERIC64, GENERIC64, false),

  ARCH (i8086, UNKNOWN, NONE, false),

  ARCH (i186, UNKNOWN, 186, false),

  ARCH (i286, UNKNOWN, 286, false),

  ARCH (i386, I386, 386, false),

  ARCH (i486, I486, 486, false),

  ARCH (i586, PENTIUM, 586, false),

  ARCH (pentium, PENTIUM, 586, false),

  ARCH (i686, I686, 686, false),

  ARCH (pentiumpro, PENTIUMPRO, PENTIUMPRO, false),

  ARCH (pentiumii, PENTIUMPRO, P2, false),

  ARCH (pentiumiii, PENTIUMPRO, P3, false),

  ARCH (pentium4, PENTIUM4, P4, false),

  ARCH (prescott, NOCONA, CORE, false),

  ARCH (nocona, NOCONA, NOCONA, false),

  ARCH (yonah, CORE, CORE, true),

  ARCH (core, CORE, CORE, false),

  ARCH (merom, CORE2, CORE2, true),

  ARCH (core2, CORE2, CORE2, false),

  ARCH (corei7, COREI7, COREI7, false),

  ARCH (iamcu, IAMCU, IAMCU, false),

  ARCH (k6, K6, K6, false),

  ARCH (k6_2, K6, K6_2, false),

  ARCH (athlon, ATHLON, ATHLON, false),

  ARCH (sledgehammer, K8, K8, true),

  ARCH (opteron, K8, K8, false),

  ARCH (k8, K8, K8, false),

  ARCH (amdfam10, AMDFAM10, AMDFAM10, false),

  ARCH (bdver1, BD, BDVER1, false),

  ARCH (bdver2, BD, BDVER2, false),

  ARCH (bdver3, BD, BDVER3, false),

  ARCH (bdver4, BD, BDVER4, false),

  ARCH (znver1, ZNVER, ZNVER1, false),

  ARCH (znver2, ZNVER, ZNVER2, false),

  ARCH (znver3, ZNVER, ZNVER3, false),

  ARCH (znver4, ZNVER, ZNVER4, false),

  ARCH (znver5, ZNVER, ZNVER5, false),

  ARCH (znver6, ZNVER, ZNVER6, false),

  ARCH (btver1, BT, BTVER1, false),

  ARCH (btver2, BT, BTVER2, false),

  SUBARCH (8087, 8087, ANY_8087, false),

  SUBARCH (87, NONE, ANY_8087, false), /* Disable only!  */

  SUBARCH (287, 287, ANY_287, false),

  SUBARCH (387, 387, ANY_387, false),

  SUBARCH (687, 687, ANY_687, false),

  SUBARCH (cmov, CMOV, CMOV, false),

  SUBARCH (fxsr, FXSR, ANY_FXSR, false),

  SUBARCH (mmx, MMX, ANY_MMX, false),

  SUBARCH (sse, SSE, ANY_SSE, false),

  SUBARCH (sse2, SSE2, ANY_SSE2, false),

  SUBARCH (sse3, SSE3, ANY_SSE3, false),

  SUBARCH (sse4a, SSE4A, ANY_SSE4A, false),

  SUBARCH (ssse3, SSSE3, ANY_SSSE3, false),

  SUBARCH (sse4.1, SSE4_1, ANY_SSE4_1, false),

  SUBARCH (sse4.2, SSE4_2, ANY_SSE4_2, false),

  SUBARCH (sse4, SSE4_2, ANY_SSE4_1, false),

  VECARCH (avx, AVX, ANY_AVX, reset),

  VECARCH (avx2, AVX2, ANY_AVX2, reset),

  VECARCH (avx512f, AVX512F, ANY_AVX512F, reset),