/src/binutils-gdb/opcodes/microblaze-dis.c
Line | Count | Source |
1 | | /* Disassemble Xilinx microblaze instructions. |
2 | | |
3 | | Copyright (C) 2009-2026 Free Software Foundation, Inc. |
4 | | |
5 | | This file is part of the GNU opcodes library. |
6 | | |
7 | | This library is free software; you can redistribute it and/or modify |
8 | | it under the terms of the GNU General Public License as published by |
9 | | the Free Software Foundation; either version 3, or (at your option) |
10 | | any later version. |
11 | | |
12 | | It is distributed in the hope that it will be useful, but WITHOUT |
13 | | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
14 | | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
15 | | License for more details. |
16 | | |
17 | | You should have received a copy of the GNU General Public License |
18 | | along with this file; see the file COPYING. If not, write to the |
19 | | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
20 | | MA 02110-1301, USA. */ |
21 | | |
22 | | |
23 | | #include "sysdep.h" |
24 | | #define STATIC_TABLE |
25 | | #define DEFINE_TABLE |
26 | | |
27 | | #include "disassemble.h" |
28 | | #include <strings.h> |
29 | | #include "microblaze-opc.h" |
30 | | #include "microblaze-dis.h" |
31 | | |
32 | 43.3k | #define get_field_rd(buf, instr) get_field (buf, instr, RD_MASK, RD_LOW) |
33 | 39.1k | #define get_field_r1(buf, instr) get_field (buf, instr, RA_MASK, RA_LOW) |
34 | 9.00k | #define get_field_r2(buf, instr) get_field (buf, instr, RB_MASK, RB_LOW) |
35 | 8.22k | #define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW) |
36 | 25.2k | #define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW) |
37 | | |
38 | 135k | #define NUM_STRBUFS 4 |
39 | | #define STRBUF_SIZE 25 |
40 | | |
41 | | struct string_buf |
42 | | { |
43 | | unsigned int which; |
44 | | char str[NUM_STRBUFS][STRBUF_SIZE]; |
45 | | }; |
46 | | |
47 | | static inline char * |
48 | | strbuf (struct string_buf *buf) |
49 | 135k | { |
50 | 135k | #ifdef ENABLE_CHECKING |
51 | 135k | if (buf->which >= NUM_STRBUFS) |
52 | 0 | abort (); |
53 | 135k | #endif |
54 | 135k | return buf->str[buf->which++]; |
55 | 135k | } |
56 | | |
57 | | static char * |
58 | | get_field (struct string_buf *buf, long instr, long mask, unsigned short low) |
59 | 91.4k | { |
60 | 91.4k | char *p = strbuf (buf); |
61 | | |
62 | 91.4k | sprintf (p, "%s%d", register_prefix, (int)((instr & mask) >> low)); |
63 | 91.4k | return p; |
64 | 91.4k | } |
65 | | |
66 | | static char * |
67 | | get_field_imm (struct string_buf *buf, long instr) |
68 | 30.8k | { |
69 | 30.8k | char *p = strbuf (buf); |
70 | | |
71 | 30.8k | sprintf (p, "%d", (short)((instr & IMM_MASK) >> IMM_LOW)); |
72 | 30.8k | return p; |
73 | 30.8k | } |
74 | | |
75 | | static char * |
76 | | get_field_imm5 (struct string_buf *buf, long instr) |
77 | 300 | { |
78 | 300 | char *p = strbuf (buf); |
79 | | |
80 | 300 | sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW)); |
81 | 300 | return p; |
82 | 300 | } |
83 | | |
84 | | static char * |
85 | | get_field_imm5_mbar (struct string_buf *buf, long instr) |
86 | 180 | { |
87 | 180 | char *p = strbuf (buf); |
88 | | |
89 | 180 | sprintf (p, "%d", (short)((instr & IMM5_MBAR_MASK) >> IMM_MBAR)); |
90 | 180 | return p; |
91 | 180 | } |
92 | | |
93 | | static char * |
94 | | get_field_immw (struct string_buf *buf, long instr) |
95 | 186 | { |
96 | 186 | char *p = strbuf (buf); |
97 | | |
98 | 186 | if (instr & 0x00004000) |
99 | 70 | sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) |
100 | 70 | >> IMM_WIDTH_LOW))); /* bsefi */ |
101 | 116 | else |
102 | 116 | sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> |
103 | 116 | IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> |
104 | 116 | IMM_LOW) + 1)); /* bsifi */ |
105 | 186 | return p; |
106 | 186 | } |
107 | | |
108 | | static char * |
109 | | get_field_rfsl (struct string_buf *buf, long instr) |
110 | 10.2k | { |
111 | 10.2k | char *p = strbuf (buf); |
112 | | |
113 | 10.2k | sprintf (p, "%s%d", fsl_register_prefix, |
114 | 10.2k | (short)((instr & RFSL_MASK) >> IMM_LOW)); |
115 | 10.2k | return p; |
116 | 10.2k | } |
117 | | |
118 | | static char * |
119 | | get_field_imm15 (struct string_buf *buf, long instr) |
120 | 17 | { |
121 | 17 | char *p = strbuf (buf); |
122 | | |
123 | 17 | sprintf (p, "%d", (short)((instr & IMM15_MASK) >> IMM_LOW)); |
124 | 17 | return p; |
125 | 17 | } |
126 | | |
127 | | static char * |
128 | | get_field_special (struct string_buf *buf, long instr, |
129 | | const struct op_code_struct *op) |
130 | 2.67k | { |
131 | 2.67k | char *p = strbuf (buf); |
132 | 2.67k | char *spr; |
133 | | |
134 | 2.67k | switch ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask)) |
135 | 2.67k | { |
136 | 13 | case MICROBLAZE_REG_MSR_MASK: |
137 | 13 | spr = "msr"; |
138 | 13 | break; |
139 | 141 | case MICROBLAZE_REG_PC_MASK: |
140 | 141 | spr = "pc"; |
141 | 141 | break; |
142 | 25 | case MICROBLAZE_REG_EAR_MASK: |
143 | 25 | spr = "ear"; |
144 | 25 | break; |
145 | 602 | case MICROBLAZE_REG_ESR_MASK: |
146 | 602 | spr = "esr"; |
147 | 602 | break; |
148 | 36 | case MICROBLAZE_REG_FSR_MASK: |
149 | 36 | spr = "fsr"; |
150 | 36 | break; |
151 | 201 | case MICROBLAZE_REG_BTR_MASK: |
152 | 201 | spr = "btr"; |
153 | 201 | break; |
154 | 181 | case MICROBLAZE_REG_EDR_MASK: |
155 | 181 | spr = "edr"; |
156 | 181 | break; |
157 | 34 | case MICROBLAZE_REG_PID_MASK: |
158 | 34 | spr = "pid"; |
159 | 34 | break; |
160 | 79 | case MICROBLAZE_REG_ZPR_MASK: |
161 | 79 | spr = "zpr"; |
162 | 79 | break; |
163 | 36 | case MICROBLAZE_REG_TLBX_MASK: |
164 | 36 | spr = "tlbx"; |
165 | 36 | break; |
166 | 218 | case MICROBLAZE_REG_TLBLO_MASK: |
167 | 218 | spr = "tlblo"; |
168 | 218 | break; |
169 | 94 | case MICROBLAZE_REG_TLBHI_MASK: |
170 | 94 | spr = "tlbhi"; |
171 | 94 | break; |
172 | 13 | case MICROBLAZE_REG_TLBSX_MASK: |
173 | 13 | spr = "tlbsx"; |
174 | 13 | break; |
175 | 3 | case MICROBLAZE_REG_SHR_MASK: |
176 | 3 | spr = "shr"; |
177 | 3 | break; |
178 | 161 | case MICROBLAZE_REG_SLR_MASK: |
179 | 161 | spr = "slr"; |
180 | 161 | break; |
181 | 833 | default: |
182 | 833 | if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000) |
183 | 833 | == MICROBLAZE_REG_PVR_MASK) |
184 | 538 | { |
185 | 538 | sprintf (p, "%spvr%d", register_prefix, |
186 | 538 | ((unsigned short)(((instr & IMM_MASK) >> IMM_LOW) |
187 | 538 | ^ op->immval_mask) |
188 | 538 | ^ MICROBLAZE_REG_PVR_MASK)); |
189 | 538 | return p; |
190 | 538 | } |
191 | 295 | else |
192 | 295 | spr = "pc"; |
193 | 295 | break; |
194 | 2.67k | } |
195 | | |
196 | 2.13k | sprintf (p, "%s%s", register_prefix, spr); |
197 | 2.13k | return p; |
198 | 2.67k | } |
199 | | |
200 | | static unsigned long |
201 | | read_insn_microblaze (bfd_vma memaddr, |
202 | | struct disassemble_info *info, |
203 | | const struct op_code_struct **opr) |
204 | 131k | { |
205 | 131k | unsigned char ibytes[4]; |
206 | 131k | int status; |
207 | 131k | const struct op_code_struct *op; |
208 | 131k | unsigned long inst; |
209 | | |
210 | 131k | status = info->read_memory_func (memaddr, ibytes, 4, info); |
211 | | |
212 | 131k | if (status != 0) |
213 | 105 | { |
214 | 105 | info->memory_error_func (status, memaddr, info); |
215 | 105 | return 0; |
216 | 105 | } |
217 | | |
218 | 131k | if (info->endian == BFD_ENDIAN_BIG) |
219 | 13.7k | inst = (((unsigned) ibytes[0] << 24) | (ibytes[1] << 16) |
220 | 13.7k | | (ibytes[2] << 8) | ibytes[3]); |
221 | 117k | else if (info->endian == BFD_ENDIAN_LITTLE) |
222 | 117k | inst = (((unsigned) ibytes[3] << 24) | (ibytes[2] << 16) |
223 | 117k | | (ibytes[1] << 8) | ibytes[0]); |
224 | 0 | else |
225 | 0 | abort (); |
226 | | |
227 | | /* Just a linear search of the table. */ |
228 | 27.5M | for (op = microblaze_opcodes; op->name != 0; op ++) |
229 | 27.4M | if (op->bit_sequence == (inst & op->opcode_mask)) |
230 | 58.1k | break; |
231 | | |
232 | 131k | *opr = op; |
233 | 131k | return inst; |
234 | 131k | } |
235 | | |
236 | | |
237 | | int |
238 | | print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) |
239 | 124k | { |
240 | 124k | fprintf_ftype print_func = info->fprintf_func; |
241 | 124k | void *stream = info->stream; |
242 | 124k | unsigned long inst, prev_inst; |
243 | 124k | const struct op_code_struct *op, *pop; |
244 | 124k | int immval = 0; |
245 | 124k | bool immfound = false; |
246 | 124k | static bfd_vma prev_insn_addr = -1; /* Init the prev insn addr. */ |
247 | 124k | static int prev_insn_vma = -1; /* Init the prev insn vma. */ |
248 | 124k | int curr_insn_vma = info->buffer_vma; |
249 | 124k | struct string_buf buf; |
250 | | |
251 | 124k | buf.which = 0; |
252 | 124k | info->bytes_per_chunk = 4; |
253 | | |
254 | 124k | inst = read_insn_microblaze (memaddr, info, &op); |
255 | 124k | if (inst == 0) |
256 | 267 | return -1; |
257 | | |
258 | 124k | if (prev_insn_vma == curr_insn_vma) |
259 | 6.96k | { |
260 | 6.96k | if (memaddr-(info->bytes_per_chunk) == prev_insn_addr) |
261 | 6.65k | { |
262 | 6.65k | prev_inst = read_insn_microblaze (prev_insn_addr, info, &pop); |
263 | 6.65k | if (prev_inst == 0) |
264 | 1 | return -1; |
265 | 6.65k | if (pop->instr == imm) |
266 | 0 | { |
267 | 0 | immval = (get_int_field_imm (prev_inst) << 16) & 0xffff0000; |
268 | 0 | immfound = true; |
269 | 0 | } |
270 | 6.65k | else |
271 | 6.65k | { |
272 | 6.65k | immval = 0; |
273 | 6.65k | immfound = false; |
274 | 6.65k | } |
275 | 6.65k | } |
276 | 6.96k | } |
277 | | |
278 | | /* Make curr insn as prev insn. */ |
279 | 124k | prev_insn_addr = memaddr; |
280 | 124k | prev_insn_vma = curr_insn_vma; |
281 | | |
282 | 124k | if (op->name == NULL) |
283 | 68.9k | print_func (stream, ".long 0x%04x", (unsigned int) inst); |
284 | 55.4k | else |
285 | 55.4k | { |
286 | 55.4k | print_func (stream, "%s", op->name); |
287 | | |
288 | 55.4k | switch (op->inst_type) |
289 | 55.4k | { |
290 | 3.64k | case INST_TYPE_RD_R1_R2: |
291 | 3.64k | print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst), |
292 | 3.64k | get_field_r1 (&buf, inst), get_field_r2 (&buf, inst)); |
293 | 3.64k | break; |
294 | 25.2k | case INST_TYPE_RD_R1_IMM: |
295 | 25.2k | print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst), |
296 | 25.2k | get_field_r1 (&buf, inst), get_field_imm (&buf, inst)); |
297 | 25.2k | if (info->print_address_func && get_int_field_r1 (inst) == 0 |
298 | 3.92k | && info->symbol_at_address_func) |
299 | 3.92k | { |
300 | 3.92k | if (immfound) |
301 | 0 | immval |= (get_int_field_imm (inst) & 0x0000ffff); |
302 | 3.92k | else |
303 | 3.92k | { |
304 | 3.92k | immval = get_int_field_imm (inst); |
305 | 3.92k | if (immval & 0x8000) |
306 | 1.94k | immval |= (~0xFFFF); |
307 | 3.92k | } |
308 | 3.92k | if (immval > 0 && info->symbol_at_address_func (immval, info)) |
309 | 0 | { |
310 | 0 | print_func (stream, "\t// "); |
311 | 0 | info->print_address_func (immval, info); |
312 | 0 | } |
313 | 3.92k | } |
314 | 25.2k | break; |
315 | 114 | case INST_TYPE_RD_R1_IMM5: |
316 | 114 | print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst), |
317 | 114 | get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst)); |
318 | 114 | break; |
319 | 8.57k | case INST_TYPE_RD_RFSL: |
320 | 8.57k | print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), |
321 | 8.57k | get_field_rfsl (&buf, inst)); |
322 | 8.57k | break; |
323 | 912 | case INST_TYPE_R1_RFSL: |
324 | 912 | print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst), |
325 | 912 | get_field_rfsl (&buf, inst)); |
326 | 912 | break; |
327 | 2.66k | case INST_TYPE_RD_SPECIAL: |
328 | 2.66k | print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), |
329 | 2.66k | get_field_special (&buf, inst, op)); |
330 | 2.66k | break; |
331 | 10 | case INST_TYPE_SPECIAL_R1: |
332 | 10 | print_func (stream, "\t%s, %s", get_field_special (&buf, inst, op), |
333 | 10 | get_field_r1 (&buf, inst)); |
334 | 10 | break; |
335 | 1.79k | case INST_TYPE_RD_R1: |
336 | 1.79k | print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), |
337 | 1.79k | get_field_r1 (&buf, inst)); |
338 | 1.79k | break; |
339 | 3.61k | case INST_TYPE_R1_R2: |
340 | 3.61k | print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst), |
341 | 3.61k | get_field_r2 (&buf, inst)); |
342 | 3.61k | break; |
343 | 3.22k | case INST_TYPE_R1_IMM: |
344 | 3.22k | print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst), |
345 | 3.22k | get_field_imm (&buf, inst)); |
346 | | /* The non-pc relative instructions are returns, which shouldn't |
347 | | have a label printed. */ |
348 | 3.22k | if (info->print_address_func && op->inst_offset_type == INST_PC_OFFSET |
349 | 2.93k | && info->symbol_at_address_func) |
350 | 2.93k | { |
351 | 2.93k | if (immfound) |
352 | 0 | immval |= (get_int_field_imm (inst) & 0x0000ffff); |
353 | 2.93k | else |
354 | 2.93k | { |
355 | 2.93k | immval = get_int_field_imm (inst); |
356 | 2.93k | if (immval & 0x8000) |
357 | 2.10k | immval |= (~0xFFFF); |
358 | 2.93k | } |
359 | 2.93k | immval += memaddr; |
360 | 2.93k | if (immval > 0 && info->symbol_at_address_func (immval, info)) |
361 | 0 | { |
362 | 0 | print_func (stream, "\t// "); |
363 | 0 | info->print_address_func (immval, info); |
364 | 0 | } |
365 | 2.93k | else |
366 | 2.93k | { |
367 | 2.93k | print_func (stream, "\t\t// "); |
368 | 2.93k | print_func (stream, "%x", immval); |
369 | 2.93k | } |
370 | 2.93k | } |
371 | 3.22k | break; |
372 | 229 | case INST_TYPE_RD_IMM: |
373 | 229 | print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), |
374 | 229 | get_field_imm (&buf, inst)); |
375 | 229 | if (info->print_address_func && info->symbol_at_address_func) |
376 | 229 | { |
377 | 229 | if (immfound) |
378 | 0 | immval |= (get_int_field_imm (inst) & 0x0000ffff); |
379 | 229 | else |
380 | 229 | { |
381 | 229 | immval = get_int_field_imm (inst); |
382 | 229 | if (immval & 0x8000) |
383 | 79 | immval |= (~0xFFFF); |
384 | 229 | } |
385 | 229 | if (op->inst_offset_type == INST_PC_OFFSET) |
386 | 167 | immval += (int) memaddr; |
387 | 229 | if (info->symbol_at_address_func (immval, info)) |
388 | 0 | { |
389 | 0 | print_func (stream, "\t// "); |
390 | 0 | info->print_address_func (immval, info); |
391 | 0 | } |
392 | 229 | } |
393 | 229 | break; |
394 | 2.13k | case INST_TYPE_IMM: |
395 | 2.13k | print_func (stream, "\t%s", get_field_imm (&buf, inst)); |
396 | 2.13k | if (info->print_address_func && info->symbol_at_address_func |
397 | 2.13k | && op->instr != imm) |
398 | 1.13k | { |
399 | 1.13k | if (immfound) |
400 | 0 | immval |= (get_int_field_imm (inst) & 0x0000ffff); |
401 | 1.13k | else |
402 | 1.13k | { |
403 | 1.13k | immval = get_int_field_imm (inst); |
404 | 1.13k | if (immval & 0x8000) |
405 | 291 | immval |= (~0xFFFF); |
406 | 1.13k | } |
407 | 1.13k | if (op->inst_offset_type == INST_PC_OFFSET) |
408 | 622 | immval += (int) memaddr; |
409 | 1.13k | if (immval > 0 && info->symbol_at_address_func (immval, info)) |
410 | 0 | { |
411 | 0 | print_func (stream, "\t// "); |
412 | 0 | info->print_address_func (immval, info); |
413 | 0 | } |
414 | 1.13k | else if (op->inst_offset_type == INST_PC_OFFSET) |
415 | 622 | { |
416 | 622 | print_func (stream, "\t\t// "); |
417 | 622 | print_func (stream, "%x", immval); |
418 | 622 | } |
419 | 1.13k | } |
420 | 2.13k | break; |
421 | 825 | case INST_TYPE_RD_R2: |
422 | 825 | print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), |
423 | 825 | get_field_r2 (&buf, inst)); |
424 | 825 | break; |
425 | 572 | case INST_TYPE_R2: |
426 | 572 | print_func (stream, "\t%s", get_field_r2 (&buf, inst)); |
427 | 572 | break; |
428 | 0 | case INST_TYPE_R1: |
429 | 0 | print_func (stream, "\t%s", get_field_r1 (&buf, inst)); |
430 | 0 | break; |
431 | 351 | case INST_TYPE_R1_R2_SPECIAL: |
432 | 351 | print_func (stream, "\t%s, %s", get_field_r1 (&buf, inst), |
433 | 351 | get_field_r2 (&buf, inst)); |
434 | 351 | break; |
435 | 17 | case INST_TYPE_RD_IMM15: |
436 | 17 | print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), |
437 | 17 | get_field_imm15 (&buf, inst)); |
438 | 17 | break; |
439 | | /* For mbar insn. */ |
440 | 180 | case INST_TYPE_IMM5: |
441 | 180 | print_func (stream, "\t%s", get_field_imm5_mbar (&buf, inst)); |
442 | 180 | break; |
443 | | /* For mbar 16 or sleep insn. */ |
444 | 339 | case INST_TYPE_NONE: |
445 | 339 | break; |
446 | | /* For bit field insns. */ |
447 | 186 | case INST_TYPE_RD_R1_IMMW_IMMS: |
448 | 186 | print_func (stream, "\t%s, %s, %s, %s", |
449 | 186 | get_field_rd (&buf, inst), |
450 | 186 | get_field_r1 (&buf, inst), |
451 | 186 | get_field_immw (&buf, inst), |
452 | 186 | get_field_imm5 (&buf, inst)); |
453 | 186 | break; |
454 | | /* For tuqula instruction */ |
455 | 0 | case INST_TYPE_RD: |
456 | 0 | print_func (stream, "\t%s", get_field_rd (&buf, inst)); |
457 | 0 | break; |
458 | 798 | case INST_TYPE_RFSL: |
459 | 798 | print_func (stream, "\t%s", get_field_rfsl (&buf, inst)); |
460 | 798 | break; |
461 | 0 | default: |
462 | | /* If the disassembler lags the instruction set. */ |
463 | 0 | print_func (stream, "\tundecoded operands, inst is 0x%04x", |
464 | 0 | (unsigned int) inst); |
465 | 0 | break; |
466 | 55.4k | } |
467 | 55.4k | } |
468 | | |
469 | | /* Say how many bytes we consumed. */ |
470 | 124k | return 4; |
471 | 124k | } |
472 | | |
473 | | enum microblaze_instr |
474 | | get_insn_microblaze (long inst, |
475 | | bool *isunsignedimm, |
476 | | enum microblaze_instr_type *insn_type, |
477 | | short *delay_slots) |
478 | 0 | { |
479 | 0 | const struct op_code_struct *op; |
480 | 0 | *isunsignedimm = false; |
481 | | |
482 | | /* Just a linear search of the table. */ |
483 | 0 | for (op = microblaze_opcodes; op->name != 0; op ++) |
484 | 0 | if (op->bit_sequence == (inst & op->opcode_mask)) |
485 | 0 | break; |
486 | |
|
487 | 0 | if (op->name == 0) |
488 | 0 | return invalid_inst; |
489 | 0 | else |
490 | 0 | { |
491 | 0 | *isunsignedimm = (op->inst_type == INST_TYPE_RD_R1_UNSIGNED_IMM); |
492 | 0 | *insn_type = op->instr_type; |
493 | 0 | *delay_slots = op->delay_slots; |
494 | 0 | return op->instr; |
495 | 0 | } |
496 | 0 | } |
497 | | |
498 | | enum microblaze_instr |
499 | | microblaze_decode_insn (long insn, int *rd, int *ra, int *rb, int *immed) |
500 | 0 | { |
501 | 0 | enum microblaze_instr op; |
502 | 0 | bool t1; |
503 | 0 | enum microblaze_instr_type t2; |
504 | 0 | short t3; |
505 | |
|
506 | 0 | op = get_insn_microblaze (insn, &t1, &t2, &t3); |
507 | 0 | *rd = (insn & RD_MASK) >> RD_LOW; |
508 | 0 | *ra = (insn & RA_MASK) >> RA_LOW; |
509 | 0 | *rb = (insn & RB_MASK) >> RB_LOW; |
510 | 0 | t3 = (insn & IMM_MASK) >> IMM_LOW; |
511 | 0 | *immed = (int) t3; |
512 | 0 | return (op); |
513 | 0 | } |
514 | | |
515 | | unsigned long |
516 | | microblaze_get_target_address (long inst, bool immfound, int immval, |
517 | | long pcval, long r1val, long r2val, |
518 | | bool *targetvalid, |
519 | | bool *unconditionalbranch) |
520 | 0 | { |
521 | 0 | const struct op_code_struct *op; |
522 | 0 | long targetaddr = 0; |
523 | |
|
524 | 0 | *unconditionalbranch = false; |
525 | | /* Just a linear search of the table. */ |
526 | 0 | for (op = microblaze_opcodes; op->name != 0; op ++) |
527 | 0 | if (op->bit_sequence == (inst & op->opcode_mask)) |
528 | 0 | break; |
529 | |
|
530 | 0 | if (op->name == 0) |
531 | 0 | { |
532 | 0 | *targetvalid = false; |
533 | 0 | } |
534 | 0 | else if (op->instr_type == branch_inst) |
535 | 0 | { |
536 | 0 | switch (op->inst_type) |
537 | 0 | { |
538 | 0 | case INST_TYPE_R2: |
539 | 0 | *unconditionalbranch = true; |
540 | | /* Fall through. */ |
541 | 0 | case INST_TYPE_RD_R2: |
542 | 0 | case INST_TYPE_R1_R2: |
543 | 0 | targetaddr = r2val; |
544 | 0 | *targetvalid = true; |
545 | 0 | if (op->inst_offset_type == INST_PC_OFFSET) |
546 | 0 | targetaddr += pcval; |
547 | 0 | break; |
548 | 0 | case INST_TYPE_IMM: |
549 | 0 | *unconditionalbranch = true; |
550 | | /* Fall through. */ |
551 | 0 | case INST_TYPE_RD_IMM: |
552 | 0 | case INST_TYPE_R1_IMM: |
553 | 0 | if (immfound) |
554 | 0 | { |
555 | 0 | targetaddr = (immval << 16) & (~0xffff); |
556 | 0 | targetaddr |= (get_int_field_imm (inst) & 0x0000ffff); |
557 | 0 | } |
558 | 0 | else |
559 | 0 | { |
560 | 0 | targetaddr = get_int_field_imm (inst); |
561 | 0 | if (targetaddr & 0x8000) |
562 | 0 | targetaddr |= (~0xFFFF); |
563 | 0 | } |
564 | 0 | if (op->inst_offset_type == INST_PC_OFFSET) |
565 | 0 | targetaddr += pcval; |
566 | 0 | *targetvalid = true; |
567 | 0 | break; |
568 | 0 | default: |
569 | 0 | *targetvalid = false; |
570 | 0 | break; |
571 | 0 | } |
572 | 0 | } |
573 | 0 | else if (op->instr_type == return_inst) |
574 | 0 | { |
575 | 0 | if (immfound) |
576 | 0 | { |
577 | 0 | targetaddr = (immval << 16) & (~0xffff); |
578 | 0 | targetaddr |= (get_int_field_imm (inst) & 0x0000ffff); |
579 | 0 | } |
580 | 0 | else |
581 | 0 | { |
582 | 0 | targetaddr = get_int_field_imm (inst); |
583 | 0 | if (targetaddr & 0x8000) |
584 | 0 | targetaddr |= (~0xFFFF); |
585 | 0 | } |
586 | 0 | targetaddr += r1val; |
587 | 0 | *targetvalid = true; |
588 | 0 | } |
589 | 0 | else |
590 | 0 | *targetvalid = false; |
591 | 0 | return targetaddr; |
592 | 0 | } |