/src/binutils-gdb/opcodes/ia64-dis.c

Source
/* ia64-dis.c -- Disassemble ia64 instructions
   Copyright (C) 1998-2026 Free Software Foundation, Inc.
   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this file; see the file COPYING.  If not, write to the
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
   02110-1301, USA.  */

#include "sysdep.h"
#include <assert.h>

#include "disassemble.h"
#include "opcode/ia64.h"

#define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0])))

/* Disassemble ia64 instruction.  */

/* Return the instruction type for OPCODE found in unit UNIT. */

static enum ia64_insn_type
unit_to_type (ia64_insn opcode, enum ia64_unit unit)
{
  enum ia64_insn_type type;
  int op;

  op = IA64_OP (opcode);

  if (op >= 8 && (unit == IA64_UNIT_I || unit == IA64_UNIT_M))
    {
      type = IA64_TYPE_A;
    }
  else
    {
      switch (unit)
  {
  case IA64_UNIT_I:
    type = IA64_TYPE_I; break;
  case IA64_UNIT_M:
    type = IA64_TYPE_M; break;
  case IA64_UNIT_B:
    type = IA64_TYPE_B; break;
  case IA64_UNIT_F:
    type = IA64_TYPE_F; break;
        case IA64_UNIT_L:
  case IA64_UNIT_X:
    type = IA64_TYPE_X; break;
  default:
    type = -1;
  }
    }
  return type;
}

int
print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
{
  ia64_insn t0, t1, slot[3], template_val, s_bit, insn;
  int slotnum, j, status, need_comma, retval, slot_multiplier;
  const struct ia64_operand *odesc;
  const struct ia64_opcode *idesc;
  const char *err, *str, *tname;
  uint64_t value;
  bfd_byte bundle[16];
  enum ia64_unit unit;
  char regname[16];

  if (info->bytes_per_line == 0)
    info->bytes_per_line = 6;
  info->display_endian = info->endian;

  slot_multiplier = info->bytes_per_line;
  retval = slot_multiplier;

  slotnum = (((long) memaddr) & 0xf) / slot_multiplier;
  if (slotnum > 2)
    return -1;

  memaddr -= (memaddr & 0xf);
  status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }
  /* bundles are always in little-endian byte order */
  t0 = bfd_getl64 (bundle);
  t1 = bfd_getl64 (bundle + 8);
  s_bit = t0 & 1;
  template_val = (t0 >> 1) & 0xf;
  slot[0] = (t0 >>  5) & 0x1ffffffffffLL;
  slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
  slot[2] = (t1 >> 23) & 0x1ffffffffffLL;

  tname = ia64_templ_desc[template_val].name;
  if (slotnum == 0)
    (*info->fprintf_func) (info->stream, "[%s] ", tname);
  else
    (*info->fprintf_func) (info->stream, "      ");

  unit = ia64_templ_desc[template_val].exec_unit[slotnum];

  if (template_val == 2 && slotnum == 1)
    {
      /* skip L slot in MLI template: */
      slotnum = 2;
      retval += slot_multiplier;
    }

  insn = slot[slotnum];

  if (unit == IA64_UNIT_NIL)
    goto decoding_failed;

  idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit));
  if (idesc == NULL)
    goto decoding_failed;

  /* print predicate, if any: */

  if ((idesc->flags & IA64_OPCODE_NO_PRED)
      || (insn & 0x3f) == 0)
    (*info->fprintf_func) (info->stream, "      ");
  else
    (*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f));

  /* now the actual instruction: */

  (*info->fprintf_func) (info->stream, "%s", idesc->name);
  if (idesc->operands[0])
    (*info->fprintf_func) (info->stream, " ");

  need_comma = 0;
  for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j)
    {
      odesc = elf64_ia64_operands + idesc->operands[j];

      if (need_comma)
  (*info->fprintf_func) (info->stream, ",");

      if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
  {
    /* special case of 64 bit immediate load: */
    value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7)
      | (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21)
      | (slot[1] << 22) | (((insn >> 36) & 0x1) << 63);
  }
      else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
        {
          /* 62-bit immediate for nop.x/break.x */
          value = ((slot[1] & 0x1ffffffffffLL) << 21)
            | (((insn >> 36) & 0x1) << 20)
            | ((insn >> 6) & 0xfffff);
        }
      else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
  {
    /* 60-bit immediate for long branches. */
    value = (((insn >> 13) & 0xfffff)
       | (((insn >> 36) & 1) << 59)
       | (((slot[1] >> 2) & 0x7fffffffffLL) << 20)) << 4;
  }
      else
  {
    err = (*odesc->extract) (odesc, insn, &value);
    if (err)
      {
        (*info->fprintf_func) (info->stream, "%s", err);
        goto done;
      }
  }

  switch (odesc->op_class)
    {
    case IA64_OPND_CLASS_CST:
      (*info->fprintf_func) (info->stream, "%s", odesc->str);
      break;

    case IA64_OPND_CLASS_REG:
      if (odesc->str[0] == 'a' && odesc->str[1] == 'r')
        {
    switch (value)
      {
      case 0: case 1: case 2: case 3:
      case 4: case 5: case 6: case 7:
        sprintf (regname, "ar.k%u", (unsigned int) value);
        break;
      case 16:  strcpy (regname, "ar.rsc"); break;
      case 17:  strcpy (regname, "ar.bsp"); break;
      case 18:  strcpy (regname, "ar.bspstore"); break;
      case 19:  strcpy (regname, "ar.rnat"); break;
      case 21:  strcpy (regname, "ar.fcr"); break;
      case 24:  strcpy (regname, "ar.eflag"); break;
      case 25:  strcpy (regname, "ar.csd"); break;
      case 26:  strcpy (regname, "ar.ssd"); break;
      case 27:  strcpy (regname, "ar.cflg"); break;
      case 28:  strcpy (regname, "ar.fsr"); break;
      case 29:  strcpy (regname, "ar.fir"); break;
      case 30:  strcpy (regname, "ar.fdr"); break;
      case 32:  strcpy (regname, "ar.ccv"); break;
      case 36:  strcpy (regname, "ar.unat"); break;
      case 40:  strcpy (regname, "ar.fpsr"); break;
      case 44:  strcpy (regname, "ar.itc"); break;
      case 45:  strcpy (regname, "ar.ruc"); break;
      case 64:  strcpy (regname, "ar.pfs"); break;
      case 65:  strcpy (regname, "ar.lc"); break;
      case 66:  strcpy (regname, "ar.ec"); break;
      default:
        sprintf (regname, "ar%u", (unsigned int) value);
        break;
      }
    (*info->fprintf_func) (info->stream, "%s", regname);
        }
      else if (odesc->str[0] == 'c' && odesc->str[1] == 'r')
        {
    switch (value)
      {
      case 0:       strcpy (regname, "cr.dcr"); break;
      case 1:       strcpy (regname, "cr.itm"); break;
      case 2:       strcpy (regname, "cr.iva"); break;
      case 8:       strcpy (regname, "cr.pta"); break;
      case 16:      strcpy (regname, "cr.ipsr"); break;
      case 17:      strcpy (regname, "cr.isr"); break;
      case 19:      strcpy (regname, "cr.iip"); break;
      case 20:      strcpy (regname, "cr.ifa"); break;
      case 21:      strcpy (regname, "cr.itir"); break;
      case 22:      strcpy (regname, "cr.iipa"); break;
      case 23:      strcpy (regname, "cr.ifs"); break;
      case 24:      strcpy (regname, "cr.iim"); break;
      case 25:      strcpy (regname, "cr.iha"); break;
      case 26:      strcpy (regname, "cr.iib0"); break;
      case 27:      strcpy (regname, "cr.iib1"); break;
      case 64:      strcpy (regname, "cr.lid"); break;
      case 65:      strcpy (regname, "cr.ivr"); break;
      case 66:      strcpy (regname, "cr.tpr"); break;
      case 67:      strcpy (regname, "cr.eoi"); break;
      case 68:      strcpy (regname, "cr.irr0"); break;
      case 69:      strcpy (regname, "cr.irr1"); break;
      case 70:      strcpy (regname, "cr.irr2"); break;
      case 71:      strcpy (regname, "cr.irr3"); break;
      case 72:      strcpy (regname, "cr.itv"); break;
      case 73:      strcpy (regname, "cr.pmv"); break;
      case 74:      strcpy (regname, "cr.cmcv"); break;
      case 80:      strcpy (regname, "cr.lrr0"); break;
      case 81:      strcpy (regname, "cr.lrr1"); break;
      default:
        sprintf (regname, "cr%u", (unsigned int) value);
        break;
      }
    (*info->fprintf_func) (info->stream, "%s", regname);
        }
      else
        (*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value);
      break;

    case IA64_OPND_CLASS_IND:
      (*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value);
      break;

    case IA64_OPND_CLASS_ABS:
      str = 0;
      if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4)
        switch (value)
    {
    case 0x0: str = "@brcst"; break;
    case 0x8: str = "@mix"; break;
    case 0x9: str = "@shuf"; break;
    case 0xa: str = "@alt"; break;
    case 0xb: str = "@rev"; break;
    }

      if (str)
        (*info->fprintf_func) (info->stream, "%s", str);
      else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED)
        (*info->fprintf_func) (info->stream, "%lld", (long long) value);
      else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED)
        (*info->fprintf_func) (info->stream, "%llu", (long long) value);
      else
        (*info->fprintf_func) (info->stream, "0x%llx", (long long) value);
      break;

    case IA64_OPND_CLASS_REL:
      (*info->print_address_func) (memaddr + value, info);
      break;
    }

      need_comma = 1;
      if (j + 1 == idesc->num_outputs)
  {
    (*info->fprintf_func) (info->stream, "=");
    need_comma = 0;
  }
    }
  if (slotnum + 1 == ia64_templ_desc[template_val].group_boundary
      || ((slotnum == 2) && s_bit))
    (*info->fprintf_func) (info->stream, ";;");

 done:
  ia64_free_opcode ((struct ia64_opcode *)idesc);
 failed:
  if (slotnum == 2)
    retval += 16 - 3*slot_multiplier;
  return retval;

 decoding_failed:
  (*info->fprintf_func) (info->stream, "      data8 %#011llx", (long long) insn);
  goto failed;
}

Coverage Report

Created: 2026-10-02 09:53

Line	Count	Source
1		/* ia64-dis.c -- Disassemble ia64 instructions
2		Copyright (C) 1998-2026 Free Software Foundation, Inc.
3		Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4
5		This file is part of the GNU opcodes library.
6
7		This library is free software; you can redistribute it and/or modify
8		it under the terms of the GNU General Public License as published by
9		the Free Software Foundation; either version 3, or (at your option)
10		any later version.
11
12		It is distributed in the hope that it will be useful, but WITHOUT
13		ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14		or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15		License for more details.
16
17		You should have received a copy of the GNU General Public License
18		along with this file; see the file COPYING. If not, write to the
19		Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20		02110-1301, USA. */
21
22		#include "sysdep.h"
23		#include <assert.h>
24
25		#include "disassemble.h"
26		#include "opcode/ia64.h"
27
28	468k	#define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0])))
29
30		/* Disassemble ia64 instruction. */
31
32		/* Return the instruction type for OPCODE found in unit UNIT. */
33
34		static enum ia64_insn_type
35		unit_to_type (ia64_insn opcode, enum ia64_unit unit)
36	115k	{
37	115k	enum ia64_insn_type type;
38	115k	int op;
39
40	115k	op = IA64_OP (opcode);
41
42	115k	if (op >= 8 && (unit == IA64_UNIT_I \|\| unit == IA64_UNIT_M))
43	30.5k	{
44	30.5k	type = IA64_TYPE_A;
45	30.5k	}
46	85.4k	else
47	85.4k	{
48	85.4k	switch (unit)
49	85.4k	{
50	36.4k	case IA64_UNIT_I:
51	36.4k	type = IA64_TYPE_I; break;
52	29.1k	case IA64_UNIT_M:
53	29.1k	type = IA64_TYPE_M; break;
54	12.8k	case IA64_UNIT_B:
55	12.8k	type = IA64_TYPE_B; break;
56	4.61k	case IA64_UNIT_F:
57	4.61k	type = IA64_TYPE_F; break;
58	2.34k	case IA64_UNIT_L:
59	2.34k	case IA64_UNIT_X:
60	2.34k	type = IA64_TYPE_X; break;
61	0	default:
62	0	type = -1;
63	85.4k	}
64	85.4k	}
65	115k	return type;
66	115k	}
67
68		int
69		print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
70	138k	{
71	138k	ia64_insn t0, t1, slot[3], template_val, s_bit, insn;
72	138k	int slotnum, j, status, need_comma, retval, slot_multiplier;
73	138k	const struct ia64_operand *odesc;
74	138k	const struct ia64_opcode *idesc;
75	138k	const char err, str, *tname;
76	138k	uint64_t value;
77	138k	bfd_byte bundle[16];
78	138k	enum ia64_unit unit;
79	138k	char regname[16];
80
81	138k	if (info->bytes_per_line == 0)
82	138k	info->bytes_per_line = 6;
83	138k	info->display_endian = info->endian;
84
85	138k	slot_multiplier = info->bytes_per_line;
86	138k	retval = slot_multiplier;
87
88	138k	slotnum = (((long) memaddr) & 0xf) / slot_multiplier;
89	138k	if (slotnum > 2)
90	0	return -1;
91
92	138k	memaddr -= (memaddr & 0xf);
93	138k	status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info);
94	138k	if (status != 0)
95	457	{
96	457	(*info->memory_error_func) (status, memaddr, info);
97	457	return -1;
98	457	}
99		/* bundles are always in little-endian byte order */
100	138k	t0 = bfd_getl64 (bundle);
101	138k	t1 = bfd_getl64 (bundle + 8);
102	138k	s_bit = t0 & 1;
103	138k	template_val = (t0 >> 1) & 0xf;
104	138k	slot[0] = (t0 >> 5) & 0x1ffffffffffLL;
105	138k	slot[1] = ((t0 >> 46) & 0x3ffff) \| ((t1 & 0x7fffff) << 18);
106	138k	slot[2] = (t1 >> 23) & 0x1ffffffffffLL;
107
108	138k	tname = ia64_templ_desc[template_val].name;
109	138k	if (slotnum == 0)
110	47.1k	(*info->fprintf_func) (info->stream, "[%s] ", tname);
111	91.2k	else
112	91.2k	(*info->fprintf_func) (info->stream, " ");
113
114	138k	unit = ia64_templ_desc[template_val].exec_unit[slotnum];
115
116	138k	if (template_val == 2 && slotnum == 1)
117	2.34k	{
118		/* skip L slot in MLI template: */
119	2.34k	slotnum = 2;
120	2.34k	retval += slot_multiplier;
121	2.34k	}
122
123	138k	insn = slot[slotnum];
124
125	138k	if (unit == IA64_UNIT_NIL)
126	22.3k	goto decoding_failed;
127
128	115k	idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit));
129	115k	if (idesc == NULL)
130	43.1k	goto decoding_failed;
131
132		/* print predicate, if any: */
133
134	72.8k	if ((idesc->flags & IA64_OPCODE_NO_PRED)
135	68.5k	\|\| (insn & 0x3f) == 0)
136	32.4k	(*info->fprintf_func) (info->stream, " ");
137	40.4k	else
138	40.4k	(*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f));
139
140		/* now the actual instruction: */
141
142	72.8k	(*info->fprintf_func) (info->stream, "%s", idesc->name);
143	72.8k	if (idesc->operands[0])
144	71.8k	(*info->fprintf_func) (info->stream, " ");
145
146	72.8k	need_comma = 0;
147	234k	for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j)
148	161k	{
149	161k	odesc = elf64_ia64_operands + idesc->operands[j];
150
151	161k	if (need_comma)
152	56.8k	(*info->fprintf_func) (info->stream, ",");
153
154	161k	if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
155	189	{
156		/* special case of 64 bit immediate load: */
157	189	value = ((insn >> 13) & 0x7f) \| (((insn >> 27) & 0x1ff) << 7)
158	189	\| (((insn >> 22) & 0x1f) << 16) \| (((insn >> 21) & 0x1) << 21)
159	189	\| (slot[1] << 22) \| (((insn >> 36) & 0x1) << 63);
160	189	}
161	161k	else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
162	497	{
163		/* 62-bit immediate for nop.x/break.x */
164	497	value = ((slot[1] & 0x1ffffffffffLL) << 21)
165	497	\| (((insn >> 36) & 0x1) << 20)
166	497	\| ((insn >> 6) & 0xfffff);
167	497	}
168	160k	else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
169	55	{
170		/* 60-bit immediate for long branches. */
171	55	value = (((insn >> 13) & 0xfffff)
172	55	\| (((insn >> 36) & 1) << 59)
173	55	\| (((slot[1] >> 2) & 0x7fffffffffLL) << 20)) << 4;
174	55	}
175	160k	else
176	160k	{
177	160k	err = (*odesc->extract) (odesc, insn, &value);
178	160k	if (err)
179	0	{
180	0	(*info->fprintf_func) (info->stream, "%s", err);
181	0	goto done;
182	0	}
183	160k	}
184
185	161k	switch (odesc->op_class)
186	161k	{
187	4.05k	case IA64_OPND_CLASS_CST:
188	4.05k	(*info->fprintf_func) (info->stream, "%s", odesc->str);
189	4.05k	break;
190
191	91.8k	case IA64_OPND_CLASS_REG:
192	91.8k	if (odesc->str[0] == 'a' && odesc->str[1] == 'r')
193	553	{
194	553	switch (value)
195	553	{
196	167	case 0: case 1: case 2: case 3:
197	194	case 4: case 5: case 6: case 7:
198	194	sprintf (regname, "ar.k%u", (unsigned int) value);
199	194	break;
200	3	case 16: strcpy (regname, "ar.rsc"); break;
201	2	case 17: strcpy (regname, "ar.bsp"); break;
202	2	case 18: strcpy (regname, "ar.bspstore"); break;
203	15	case 19: strcpy (regname, "ar.rnat"); break;
204	8	case 21: strcpy (regname, "ar.fcr"); break;
205	1	case 24: strcpy (regname, "ar.eflag"); break;
206	4	case 25: strcpy (regname, "ar.csd"); break;
207	146	case 26: strcpy (regname, "ar.ssd"); break;
208	15	case 27: strcpy (regname, "ar.cflg"); break;
209	5	case 28: strcpy (regname, "ar.fsr"); break;
210	13	case 29: strcpy (regname, "ar.fir"); break;
211	7	case 30: strcpy (regname, "ar.fdr"); break;
212	19	case 32: strcpy (regname, "ar.ccv"); break;
213	3	case 36: strcpy (regname, "ar.unat"); break;
214	8	case 40: strcpy (regname, "ar.fpsr"); break;
215	6	case 44: strcpy (regname, "ar.itc"); break;
216	7	case 45: strcpy (regname, "ar.ruc"); break;
217	14	case 64: strcpy (regname, "ar.pfs"); break;
218	2	case 65: strcpy (regname, "ar.lc"); break;
219	1	case 66: strcpy (regname, "ar.ec"); break;
220	78	default:
221	78	sprintf (regname, "ar%u", (unsigned int) value);
222	78	break;
223	553	}
224	553	(*info->fprintf_func) (info->stream, "%s", regname);
225	553	}
226	91.2k	else if (odesc->str[0] == 'c' && odesc->str[1] == 'r')
227	56	{
228	56	switch (value)
229	56	{
230	4	case 0: strcpy (regname, "cr.dcr"); break;
231	1	case 1: strcpy (regname, "cr.itm"); break;
232	1	case 2: strcpy (regname, "cr.iva"); break;
233	1	case 8: strcpy (regname, "cr.pta"); break;
234	1	case 16: strcpy (regname, "cr.ipsr"); break;
235	1	case 17: strcpy (regname, "cr.isr"); break;
236	1	case 19: strcpy (regname, "cr.iip"); break;
237	1	case 20: strcpy (regname, "cr.ifa"); break;
238	1	case 21: strcpy (regname, "cr.itir"); break;
239	1	case 22: strcpy (regname, "cr.iipa"); break;
240	1	case 23: strcpy (regname, "cr.ifs"); break;
241	1	case 24: strcpy (regname, "cr.iim"); break;
242	1	case 25: strcpy (regname, "cr.iha"); break;
243	1	case 26: strcpy (regname, "cr.iib0"); break;
244	1	case 27: strcpy (regname, "cr.iib1"); break;
245	1	case 64: strcpy (regname, "cr.lid"); break;
246	1	case 65: strcpy (regname, "cr.ivr"); break;
247	1	case 66: strcpy (regname, "cr.tpr"); break;
248	1	case 67: strcpy (regname, "cr.eoi"); break;
249	1	case 68: strcpy (regname, "cr.irr0"); break;
250	1	case 69: strcpy (regname, "cr.irr1"); break;
251	2	case 70: strcpy (regname, "cr.irr2"); break;
252	1	case 71: strcpy (regname, "cr.irr3"); break;
253	1	case 72: strcpy (regname, "cr.itv"); break;
254	1	case 73: strcpy (regname, "cr.pmv"); break;
255	1	case 74: strcpy (regname, "cr.cmcv"); break;
256	1	case 80: strcpy (regname, "cr.lrr0"); break;
257	1	case 81: strcpy (regname, "cr.lrr1"); break;
258	24	default:
259	24	sprintf (regname, "cr%u", (unsigned int) value);
260	24	break;
261	56	}
262	56	(*info->fprintf_func) (info->stream, "%s", regname);
263	56	}
264	91.2k	else
265	91.2k	(*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value);
266	91.8k	break;
267
268	91.8k	case IA64_OPND_CLASS_IND:
269	3.03k	(*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value);
270	3.03k	break;
271
272	50.4k	case IA64_OPND_CLASS_ABS:
273	50.4k	str = 0;
274	50.4k	if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4)
275	4	switch (value)
276	4	{
277	0	case 0x0: str = "@brcst"; break;
278	1	case 0x8: str = "@mix"; break;
279	0	case 0x9: str = "@shuf"; break;
280	1	case 0xa: str = "@alt"; break;
281	0	case 0xb: str = "@rev"; break;
282	4	}
283
284	50.4k	if (str)
285	2	(*info->fprintf_func) (info->stream, "%s", str);
286	50.4k	else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED)
287	9.74k	(*info->fprintf_func) (info->stream, "%lld", (long long) value);
288	40.6k	else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED)
289	7.69k	(*info->fprintf_func) (info->stream, "%llu", (long long) value);
290	32.9k	else
291	32.9k	(*info->fprintf_func) (info->stream, "0x%llx", (long long) value);
292	50.4k	break;
293
294	12.0k	case IA64_OPND_CLASS_REL:
295	12.0k	(*info->print_address_func) (memaddr + value, info);
296	12.0k	break;
297	161k	}
298
299	161k	need_comma = 1;
300	161k	if (j + 1 == idesc->num_outputs)
301	32.7k	{
302	32.7k	(*info->fprintf_func) (info->stream, "=");
303	32.7k	need_comma = 0;
304	32.7k	}
305	161k	}
306	72.8k	if (slotnum + 1 == ia64_templ_desc[template_val].group_boundary
307	70.6k	\|\| ((slotnum == 2) && s_bit))
308	6.92k	(*info->fprintf_func) (info->stream, ";;");
309
310	72.8k	done:
311	72.8k	ia64_free_opcode ((struct ia64_opcode *)idesc);
312	138k	failed:
313	138k	if (slotnum == 2)
314	46.5k	retval += 16 - 3*slot_multiplier;
315	138k	return retval;
316
317	65.5k	decoding_failed:
318	65.5k	(*info->fprintf_func) (info->stream, " data8 %#011llx", (long long) insn);
319	65.5k	goto failed;
320	72.8k	}