/src/binutils-gdb/opcodes/rl78-dis.c

Source
/* Disassembler code for Renesas RL78.
   Copyright (C) 2011-2026 Free Software Foundation, Inc.
   Contributed by Red Hat.
   Written by DJ Delorie.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#include "sysdep.h"
#include <stdio.h>

#include "bfd.h"
#include "elf-bfd.h"
#include "disassemble.h"
#include "opcode/rl78.h"
#include "elf/rl78.h"

#include <setjmp.h>

#define DEBUG_SEMANTICS 0

typedef struct
{
  bfd_vma pc;
  disassemble_info * dis;
} RL78_Data;

struct private
{
  OPCODES_SIGJMP_BUF bailout;
};

static int
rl78_get_byte (void * vdata)
{
  bfd_byte buf[1];
  RL78_Data *rl78_data = (RL78_Data *) vdata;
  int status;

  status = rl78_data->dis->read_memory_func (rl78_data->pc,
               buf,
               1,
               rl78_data->dis);
  if (status != 0)
    {
      struct private *priv = (struct private *) rl78_data->dis->private_data;

      rl78_data->dis->memory_error_func (status, rl78_data->pc,
           rl78_data->dis);
      OPCODES_SIGLONGJMP (priv->bailout, 1);
    }

  rl78_data->pc ++;
  return buf[0];
}

static char const *
register_names[] =
{
  "",
  "x", "a", "c", "b", "e", "d", "l", "h",
  "ax", "bc", "de", "hl",
  "sp", "psw", "cs", "es", "pmc", "mem"
};

static char const *
condition_names[] =
{
  "t", "f", "c", "nc", "h", "nh", "z", "nz"
};

static int
indirect_type (int t)
{
  switch (t)
    {
    case RL78_Operand_Indirect:
    case RL78_Operand_BitIndirect:
    case RL78_Operand_PostInc:
    case RL78_Operand_PreDec:
      return 1;
    default:
      return 0;
    }
}

static int
print_insn_rl78_common (bfd_vma addr, disassemble_info * dis, RL78_Dis_Isa isa)
{
  int rv;
  RL78_Data rl78_data;
  RL78_Opcode_Decoded opcode;
  const char * s;
#if DEBUG_SEMANTICS
  static char buf[200];
#endif
  struct private priv;

  dis->private_data = &priv;
  rl78_data.pc = addr;
  rl78_data.dis = dis;

  if (OPCODES_SIGSETJMP (priv.bailout) != 0)
    {
      /* Error return.  */
      return -1;
    }

  rv = rl78_decode_opcode (addr, &opcode, rl78_get_byte, &rl78_data, isa);

  dis->bytes_per_line = 10;

#define PR (dis->fprintf_func)
#define PS (dis->stream)
#define PC(c) PR (PS, "%c", c)

  s = opcode.syntax;

#if DEBUG_SEMANTICS

  switch (opcode.id)
    {
    case RLO_unknown: s = "uknown"; break;
    case RLO_add: s = "add: %e0%0 += %e1%1"; break;
    case RLO_addc: s = "addc: %e0%0 += %e1%1 + CY"; break;
    case RLO_and: s = "and: %e0%0 &= %e1%1"; break;
    case RLO_branch: s = "branch: pc = %e0%0"; break;
    case RLO_branch_cond: s = "branch_cond: pc = %e0%0 if %c1 / %e1%1"; break;
    case RLO_branch_cond_clear: s = "branch_cond_clear: pc = %e0%0 if %c1 / %e1%1, %e1%1 = 0"; break;
    case RLO_call: s = "call: pc = %e1%0"; break;
    case RLO_cmp: s = "cmp: %e0%0 - %e1%1"; break;
    case RLO_mov: s = "mov: %e0%0 = %e1%1"; break;
    case RLO_or: s = "or: %e0%0 |= %e1%1"; break;
    case RLO_rol: s = "rol: %e0%0 <<= %e1%1"; break;
    case RLO_rolc: s = "rol: %e0%0 <<= %e1%1,CY"; break;
    case RLO_ror: s = "ror: %e0%0 >>= %e1%1"; break;
    case RLO_rorc: s = "ror: %e0%0 >>= %e1%1,CY"; break;
    case RLO_sar: s = "sar: %e0%0 >>= %e1%1 signed"; break;
    case RLO_sel: s = "sel: rb = %1"; break;
    case RLO_shr: s = "shr: %e0%0 >>= %e1%1 unsigned"; break;
    case RLO_shl: s = "shl: %e0%0 <<= %e1%1"; break;
    case RLO_skip: s = "skip: if %c1"; break;
    case RLO_sub: s = "sub: %e0%0 -= %e1%1"; break;
    case RLO_subc: s = "subc: %e0%0 -= %e1%1 - CY"; break;
    case RLO_xch: s = "xch: %e0%0 <-> %e1%1"; break;
    case RLO_xor: s = "xor: %e0%0 ^= %e1%1"; break;
    }

  sprintf(buf, "%s%%W%%f\t\033[32m%s\033[0m", s, opcode.syntax);
  s = buf;

#endif

  for (; *s; s++)
    {
      if (*s != '%')
  {
    PC (*s);
  }
      else
  {
    RL78_Opcode_Operand * oper;
    int do_hex = 0;
    int do_addr = 0;
    int do_es = 0;
    int do_sfr = 0;
    int do_cond = 0;
    int do_bang = 0;

    while (1)
      {
        s ++;
        switch (*s)
    {
    case 'x':
      do_hex = 1;
      break;
    case '!':
      do_bang = 1;
      break;
    case 'e':
      do_es = 1;
      break;
    case 'a':
      do_addr = 1;
      break;
    case 's':
      do_sfr = 1;
      break;
    case 'c':
      do_cond = 1;
      break;
    default:
      goto no_more_modifiers;
    }
      }
  no_more_modifiers:;

    switch (*s)
      {
      case '%':
        PC ('%');
        break;

#if DEBUG_SEMANTICS

      case 'W':
        if (opcode.size == RL78_Word)
    PR (PS, " \033[33mW\033[0m");
        break;

      case 'f':
        if (opcode.flags)
    {
      char *comma = "";
      PR (PS, "  \033[35m");

      if (opcode.flags & RL78_PSW_Z)
        { PR (PS, "Z"); comma = ","; }
      if (opcode.flags & RL78_PSW_AC)
        { PR (PS, "%sAC", comma); comma = ","; }
      if (opcode.flags & RL78_PSW_CY)
        { PR (PS, "%sCY", comma); comma = ","; }
      PR (PS, "\033[0m");
    }
        break;

#endif

      case '0':
      case '1':
        oper = *s == '0' ? &opcode.op[0] : &opcode.op[1];
      if (do_es)
        {
    if (oper->use_es && indirect_type (oper->type))
      PR (PS, "es:");
        }

      if (do_bang)
        {
    /* If we are going to display SP by name, we must omit the bang.  */
    if ((oper->type == RL78_Operand_Indirect
         || oper->type == RL78_Operand_BitIndirect)
        && oper->reg == RL78_Reg_None
        && do_sfr
        && ((oper->addend == 0xffff8 && opcode.size == RL78_Word)
      || (oper->addend == 0x0fff8 && do_es && opcode.size == RL78_Word)))
      ;
    else
      PC ('!');
        }

      if (do_cond)
        {
    PR (PS, "%s", condition_names[oper->condition]);
    break;
        }

      switch (oper->type)
        {
        case RL78_Operand_Immediate:
    if (do_addr)
      dis->print_address_func (oper->addend, dis);
    else if (do_hex
       || oper->addend > 999
       || oper->addend < -999)
      PR (PS, "%#x", oper->addend);
    else
      PR (PS, "%d", oper->addend);
    break;

        case RL78_Operand_Register:
    PR (PS, "%s", register_names[oper->reg]);
    break;

        case RL78_Operand_Bit:
    PR (PS, "%s.%d", register_names[oper->reg], oper->bit_number);
    break;

        case RL78_Operand_Indirect:
        case RL78_Operand_BitIndirect:
    switch (oper->reg)
      {
      case RL78_Reg_None:
        if (oper->addend == 0xffffa && do_sfr && opcode.size == RL78_Byte)
          PR (PS, "psw");
        else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Word)
          PR (PS, "sp");
        else if (oper->addend == 0x0fff8 && do_sfr && do_es && opcode.size == RL78_Word)
          PR (PS, "sp");
                    else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Byte)
                      PR (PS, "spl");
                    else if (oper->addend == 0xffff9 && do_sfr && opcode.size == RL78_Byte)
                      PR (PS, "sph");
                    else if (oper->addend == 0xffffc && do_sfr && opcode.size == RL78_Byte)
                      PR (PS, "cs");
                    else if (oper->addend == 0xffffd && do_sfr && opcode.size == RL78_Byte)
                      PR (PS, "es");
                    else if (oper->addend == 0xffffe && do_sfr && opcode.size == RL78_Byte)
                      PR (PS, "pmc");
                    else if (oper->addend == 0xfffff && do_sfr && opcode.size == RL78_Byte)
                      PR (PS, "mem");
        else if (oper->addend >= 0xffe20)
          PR (PS, "%#x", oper->addend);
        else
          {
      int faddr = oper->addend;
      if (do_es && ! oper->use_es)
        faddr += 0xf0000;
      dis->print_address_func (faddr, dis);
          }
        break;

      case RL78_Reg_B:
      case RL78_Reg_C:
      case RL78_Reg_BC:
        PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
        break;

      default:
        PR (PS, "[%s", register_names[oper->reg]);
        if (oper->reg2 != RL78_Reg_None)
          PR (PS, "+%s", register_names[oper->reg2]);
        if (oper->addend || do_addr)
          PR (PS, "+%d", oper->addend);
        PC (']');
        break;

      }
    if (oper->type == RL78_Operand_BitIndirect)
      PR (PS, ".%d", oper->bit_number);
    break;

#if DEBUG_SEMANTICS
    /* Shouldn't happen - push and pop don't print
       [SP] directly.  But we *do* use them for
       semantic debugging.  */
        case RL78_Operand_PostInc:
    PR (PS, "[%s++]", register_names[oper->reg]);
    break;
        case RL78_Operand_PreDec:
    PR (PS, "[--%s]", register_names[oper->reg]);
    break;
#endif

        default:
    /* If we ever print this, that means the
       programmer tried to print an operand with a
       type we don't expect.  Print the line and
       operand number from rl78-decode.opc for
       them.  */
    PR (PS, "???%d.%d", opcode.lineno, *s - '0');
    break;
        }
      }
  }
    }

#if DEBUG_SEMANTICS

  PR (PS, "\t\033[34m(line %d)\033[0m", opcode.lineno);

#endif

  return rv;
}

int
print_insn_rl78 (bfd_vma addr, disassemble_info * dis)
{
  return print_insn_rl78_common (addr, dis, RL78_ISA_DEFAULT);
}

int
print_insn_rl78_g10 (bfd_vma addr, disassemble_info * dis)
{
  return print_insn_rl78_common (addr, dis, RL78_ISA_G10);
}

int
print_insn_rl78_g13 (bfd_vma addr, disassemble_info * dis)
{
  return print_insn_rl78_common (addr, dis, RL78_ISA_G13);
}

int
print_insn_rl78_g14 (bfd_vma addr, disassemble_info * dis)
{
  return print_insn_rl78_common (addr, dis, RL78_ISA_G14);
}

disassembler_ftype
rl78_get_disassembler (bfd *abfd)
{
  int cpu = E_FLAG_RL78_ANY_CPU;

  if (abfd != NULL && bfd_get_flavour (abfd) == bfd_target_elf_flavour)
    cpu = abfd->tdata.elf_obj_data->elf_header->e_flags & E_FLAG_RL78_CPU_MASK;

  switch (cpu)
    {
    case E_FLAG_RL78_G10:
      return print_insn_rl78_g10;
    case E_FLAG_RL78_G13:
      return print_insn_rl78_g13;
    case E_FLAG_RL78_G14:
      return print_insn_rl78_g14;
    default:
      return print_insn_rl78;
    }
}

Coverage Report

Created: 2026-10-02 09:53

Line	Count	Source
1		/* Disassembler code for Renesas RL78.
2		Copyright (C) 2011-2026 Free Software Foundation, Inc.
3		Contributed by Red Hat.
4		Written by DJ Delorie.
5
6		This file is part of the GNU opcodes library.
7
8		This library is free software; you can redistribute it and/or modify
9		it under the terms of the GNU General Public License as published by
10		the Free Software Foundation; either version 3, or (at your option)
11		any later version.
12
13		It is distributed in the hope that it will be useful, but WITHOUT
14		ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15		or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16		License for more details.
17
18		You should have received a copy of the GNU General Public License
19		along with this program; if not, write to the Free Software
20		Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21		MA 02110-1301, USA. */
22
23		#include "sysdep.h"
24		#include <stdio.h>
25
26		#include "bfd.h"
27		#include "elf-bfd.h"
28		#include "disassemble.h"
29		#include "opcode/rl78.h"
30		#include "elf/rl78.h"
31
32		#include <setjmp.h>
33
34		#define DEBUG_SEMANTICS 0
35
36		typedef struct
37		{
38		bfd_vma pc;
39		disassemble_info * dis;
40		} RL78_Data;
41
42		struct private
43		{
44		OPCODES_SIGJMP_BUF bailout;
45		};
46
47		static int
48		rl78_get_byte (void * vdata)
49	10.3M	{
50	10.3M	bfd_byte buf[1];
51	10.3M	RL78_Data rl78_data = (RL78_Data ) vdata;
52	10.3M	int status;
53
54	10.3M	status = rl78_data->dis->read_memory_func (rl78_data->pc,
55	10.3M	buf,
56	10.3M	1,
57	10.3M	rl78_data->dis);
58	10.3M	if (status != 0)
59	1.78k	{
60	1.78k	struct private priv = (struct private ) rl78_data->dis->private_data;
61
62	1.78k	rl78_data->dis->memory_error_func (status, rl78_data->pc,
63	1.78k	rl78_data->dis);
64	1.78k	OPCODES_SIGLONGJMP (priv->bailout, 1);
65	1.78k	}
66
67	10.3M	rl78_data->pc ++;
68	10.3M	return buf[0];
69	10.3M	}
70
71		static char const *
72		register_names[] =
73		{
74		"",
75		"x", "a", "c", "b", "e", "d", "l", "h",
76		"ax", "bc", "de", "hl",
77		"sp", "psw", "cs", "es", "pmc", "mem"
78		};
79
80		static char const *
81		condition_names[] =
82		{
83		"t", "f", "c", "nc", "h", "nh", "z", "nz"
84		};
85
86		static int
87		indirect_type (int t)
88	24.0k	{
89	24.0k	switch (t)
90	24.0k	{
91	22.2k	case RL78_Operand_Indirect:
92	23.5k	case RL78_Operand_BitIndirect:
93	23.5k	case RL78_Operand_PostInc:
94	23.5k	case RL78_Operand_PreDec:
95	23.5k	return 1;
96	451	default:
97	451	return 0;
98	24.0k	}
99	24.0k	}
100
101		static int
102		print_insn_rl78_common (bfd_vma addr, disassemble_info * dis, RL78_Dis_Isa isa)
103	5.98M	{
104	5.98M	int rv;
105	5.98M	RL78_Data rl78_data;
106	5.98M	RL78_Opcode_Decoded opcode;
107	5.98M	const char * s;
108		#if DEBUG_SEMANTICS
109		static char buf[200];
110		#endif
111	5.98M	struct private priv;
112
113	5.98M	dis->private_data = &priv;
114	5.98M	rl78_data.pc = addr;
115	5.98M	rl78_data.dis = dis;
116
117	5.98M	if (OPCODES_SIGSETJMP (priv.bailout) != 0)
118	1.78k	{
119		/* Error return. */
120	1.78k	return -1;
121	1.78k	}
122
123	5.97M	rv = rl78_decode_opcode (addr, &opcode, rl78_get_byte, &rl78_data, isa);
124
125	5.97M	dis->bytes_per_line = 10;
126
127	39.4M	#define PR (dis->fprintf_func)
128	39.4M	#define PS (dis->stream)
129	32.6M	#define PC(c) PR (PS, "%c", c)
130
131	5.97M	s = opcode.syntax;
132
133		#if DEBUG_SEMANTICS
134
135		switch (opcode.id)
136		{
137		case RLO_unknown: s = "uknown"; break;
138		case RLO_add: s = "add: %e0%0 += %e1%1"; break;
139		case RLO_addc: s = "addc: %e0%0 += %e1%1 + CY"; break;
140		case RLO_and: s = "and: %e0%0 &= %e1%1"; break;
141		case RLO_branch: s = "branch: pc = %e0%0"; break;
142		case RLO_branch_cond: s = "branch_cond: pc = %e0%0 if %c1 / %e1%1"; break;
143		case RLO_branch_cond_clear: s = "branch_cond_clear: pc = %e0%0 if %c1 / %e1%1, %e1%1 = 0"; break;
144		case RLO_call: s = "call: pc = %e1%0"; break;
145		case RLO_cmp: s = "cmp: %e0%0 - %e1%1"; break;
146		case RLO_mov: s = "mov: %e0%0 = %e1%1"; break;
147		case RLO_or: s = "or: %e0%0 \|= %e1%1"; break;
148		case RLO_rol: s = "rol: %e0%0 <<= %e1%1"; break;
149		case RLO_rolc: s = "rol: %e0%0 <<= %e1%1,CY"; break;
150		case RLO_ror: s = "ror: %e0%0 >>= %e1%1"; break;
151		case RLO_rorc: s = "ror: %e0%0 >>= %e1%1,CY"; break;
152		case RLO_sar: s = "sar: %e0%0 >>= %e1%1 signed"; break;
153		case RLO_sel: s = "sel: rb = %1"; break;
154		case RLO_shr: s = "shr: %e0%0 >>= %e1%1 unsigned"; break;
155		case RLO_shl: s = "shl: %e0%0 <<= %e1%1"; break;
156		case RLO_skip: s = "skip: if %c1"; break;
157		case RLO_sub: s = "sub: %e0%0 -= %e1%1"; break;
158		case RLO_subc: s = "subc: %e0%0 -= %e1%1 - CY"; break;
159		case RLO_xch: s = "xch: %e0%0 <-> %e1%1"; break;
160		case RLO_xor: s = "xor: %e0%0 ^= %e1%1"; break;
161		}
162
163		sprintf(buf, "%s%%W%%f\t\033[32m%s\033[0m", s, opcode.syntax);
164		s = buf;
165
166		#endif
167
168	44.4M	for (; *s; s++)
169	38.5M	{
170	38.5M	if (*s != '%')
171	31.6M	{
172	31.6M	PC (*s);
173	31.6M	}
174	6.87M	else
175	6.87M	{
176	6.87M	RL78_Opcode_Operand * oper;
177	6.87M	int do_hex = 0;
178	6.87M	int do_addr = 0;
179	6.87M	int do_es = 0;
180	6.87M	int do_sfr = 0;
181	6.87M	int do_cond = 0;
182	6.87M	int do_bang = 0;
183
184	9.12M	while (1)
185	9.12M	{
186	9.12M	s ++;
187	9.12M	switch (*s)
188	9.12M	{
189	19.4k	case 'x':
190	19.4k	do_hex = 1;
191	19.4k	break;
192	485k	case '!':
193	485k	do_bang = 1;
194	485k	break;
195	1.13M	case 'e':
196	1.13M	do_es = 1;
197	1.13M	break;
198	440k	case 'a':
199	440k	do_addr = 1;
200	440k	break;
201	164k	case 's':
202	164k	do_sfr = 1;
203	164k	break;
204	2.74k	case 'c':
205	2.74k	do_cond = 1;
206	2.74k	break;
207	6.87M	default:
208	6.87M	goto no_more_modifiers;
209	9.12M	}
210	9.12M	}
211	6.87M	no_more_modifiers:;
212
213	6.87M	switch (*s)
214	6.87M	{
215	0	case '%':
216	0	PC ('%');
217	0	break;
218
219		#if DEBUG_SEMANTICS
220
221		case 'W':
222		if (opcode.size == RL78_Word)
223		PR (PS, " \033[33mW\033[0m");
224		break;
225
226		case 'f':
227		if (opcode.flags)
228		{
229		char *comma = "";
230		PR (PS, " \033[35m");
231
232		if (opcode.flags & RL78_PSW_Z)
233		{ PR (PS, "Z"); comma = ","; }
234		if (opcode.flags & RL78_PSW_AC)
235		{ PR (PS, "%sAC", comma); comma = ","; }
236		if (opcode.flags & RL78_PSW_CY)
237		{ PR (PS, "%sCY", comma); comma = ","; }
238		PR (PS, "\033[0m");
239		}
240		break;
241
242		#endif
243
244	3.87M	case '0':
245	6.87M	case '1':
246	6.87M	oper = *s == '0' ? &opcode.op[0] : &opcode.op[1];
247	6.87M	if (do_es)
248	1.13M	{
249	1.13M	if (oper->use_es && indirect_type (oper->type))
250	23.5k	PR (PS, "es:");
251	1.13M	}
252
253	6.87M	if (do_bang)
254	485k	{
255		/* If we are going to display SP by name, we must omit the bang. */
256	485k	if ((oper->type == RL78_Operand_Indirect
257	101k	\|\| oper->type == RL78_Operand_BitIndirect)
258	400k	&& oper->reg == RL78_Reg_None
259	400k	&& do_sfr
260	25.4k	&& ((oper->addend == 0xffff8 && opcode.size == RL78_Word)
261	25.4k	\|\| (oper->addend == 0x0fff8 && do_es && opcode.size == RL78_Word)))
262	262	;
263	484k	else
264	485k	PC ('!');
265	485k	}
266
267	6.87M	if (do_cond)
268	2.74k	{
269	2.74k	PR (PS, "%s", condition_names[oper->condition]);
270	2.74k	break;
271	2.74k	}
272
273	6.87M	switch (oper->type)
274	6.87M	{
275	826k	case RL78_Operand_Immediate:
276	826k	if (do_addr)
277	157k	dis->print_address_func (oper->addend, dis);
278	668k	else if (do_hex
279	668k	\|\| oper->addend > 999
280	542k	\|\| oper->addend < -999)
281	126k	PR (PS, "%#x", oper->addend);
282	542k	else
283	542k	PR (PS, "%d", oper->addend);
284	826k	break;
285
286	4.14M	case RL78_Operand_Register:
287	4.14M	PR (PS, "%s", register_names[oper->reg]);
288	4.14M	break;
289
290	35.6k	case RL78_Operand_Bit:
291	35.6k	PR (PS, "%s.%d", register_names[oper->reg], oper->bit_number);
292	35.6k	break;
293
294	1.67M	case RL78_Operand_Indirect:
295	1.86M	case RL78_Operand_BitIndirect:
296	1.86M	switch (oper->reg)
297	1.86M	{
298	1.09M	case RL78_Reg_None:
299	1.09M	if (oper->addend == 0xffffa && do_sfr && opcode.size == RL78_Byte)
300	293	PR (PS, "psw");
301	1.09M	else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Word)
302	746	PR (PS, "sp");
303	1.09M	else if (oper->addend == 0x0fff8 && do_sfr && do_es && opcode.size == RL78_Word)
304	262	PR (PS, "sp");
305	1.09M	else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Byte)
306	1.06k	PR (PS, "spl");
307	1.09M	else if (oper->addend == 0xffff9 && do_sfr && opcode.size == RL78_Byte)
308	477	PR (PS, "sph");
309	1.09M	else if (oper->addend == 0xffffc && do_sfr && opcode.size == RL78_Byte)
310	1.13k	PR (PS, "cs");
311	1.08M	else if (oper->addend == 0xffffd && do_sfr && opcode.size == RL78_Byte)
312	447	PR (PS, "es");
313	1.08M	else if (oper->addend == 0xffffe && do_sfr && opcode.size == RL78_Byte)
314	1.12k	PR (PS, "pmc");
315	1.08M	else if (oper->addend == 0xfffff && do_sfr && opcode.size == RL78_Byte)
316	1.73k	PR (PS, "mem");
317	1.08M	else if (oper->addend >= 0xffe20)
318	666k	PR (PS, "%#x", oper->addend);
319	419k	else
320	419k	{
321	419k	int faddr = oper->addend;
322	419k	if (do_es && ! oper->use_es)
323	392k	faddr += 0xf0000;
324	419k	dis->print_address_func (faddr, dis);
325	419k	}
326	1.09M	break;
327
328	53.4k	case RL78_Reg_B:
329	139k	case RL78_Reg_C:
330	196k	case RL78_Reg_BC:
331	196k	PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
332	196k	break;
333
334	570k	default:
335	570k	PR (PS, "[%s", register_names[oper->reg]);
336	570k	if (oper->reg2 != RL78_Reg_None)
337	15.5k	PR (PS, "+%s", register_names[oper->reg2]);
338	570k	if (oper->addend \|\| do_addr)
339	282k	PR (PS, "+%d", oper->addend);
340	570k	PC (']');
341	570k	break;
342
343	1.86M	}
344	1.86M	if (oper->type == RL78_Operand_BitIndirect)
345	189k	PR (PS, ".%d", oper->bit_number);
346	1.86M	break;
347
348		#if DEBUG_SEMANTICS
349		/* Shouldn't happen - push and pop don't print
350		[SP] directly. But we do use them for
351		semantic debugging. */
352		case RL78_Operand_PostInc:
353		PR (PS, "[%s++]", register_names[oper->reg]);
354		break;
355		case RL78_Operand_PreDec:
356		PR (PS, "[--%s]", register_names[oper->reg]);
357		break;
358		#endif
359
360	0	default:
361		/* If we ever print this, that means the
362		programmer tried to print an operand with a
363		type we don't expect. Print the line and
364		operand number from rl78-decode.opc for
365		them. */
366	0	PR (PS, "???%d.%d", opcode.lineno, *s - '0');
367	0	break;
368	6.87M	}
369	6.87M	}
370	6.87M	}
371	38.5M	}
372
373		#if DEBUG_SEMANTICS
374
375		PR (PS, "\t\033[34m(line %d)\033[0m", opcode.lineno);
376
377		#endif
378
379	5.97M	return rv;
380	5.97M	}
381
382		int
383		print_insn_rl78 (bfd_vma addr, disassemble_info * dis)
384	5.88M	{
385	5.88M	return print_insn_rl78_common (addr, dis, RL78_ISA_DEFAULT);
386	5.88M	}
387
388		int
389		print_insn_rl78_g10 (bfd_vma addr, disassemble_info * dis)
390	18.8k	{
391	18.8k	return print_insn_rl78_common (addr, dis, RL78_ISA_G10);
392	18.8k	}
393
394		int
395		print_insn_rl78_g13 (bfd_vma addr, disassemble_info * dis)
396	21.6k	{
397	21.6k	return print_insn_rl78_common (addr, dis, RL78_ISA_G13);
398	21.6k	}
399
400		int
401		print_insn_rl78_g14 (bfd_vma addr, disassemble_info * dis)
402	52.7k	{
403	52.7k	return print_insn_rl78_common (addr, dis, RL78_ISA_G14);
404	52.7k	}
405
406		disassembler_ftype
407		rl78_get_disassembler (bfd *abfd)
408	5.08k	{
409	5.08k	int cpu = E_FLAG_RL78_ANY_CPU;
410
411	5.08k	if (abfd != NULL && bfd_get_flavour (abfd) == bfd_target_elf_flavour)
412	1.18k	cpu = abfd->tdata.elf_obj_data->elf_header->e_flags & E_FLAG_RL78_CPU_MASK;
413
414	5.08k	switch (cpu)
415	5.08k	{
416	12	case E_FLAG_RL78_G10:
417	12	return print_insn_rl78_g10;
418	16	case E_FLAG_RL78_G13:
419	16	return print_insn_rl78_g13;
420	35	case E_FLAG_RL78_G14:
421	35	return print_insn_rl78_g14;
422	5.02k	default:
423	5.02k	return print_insn_rl78;
424	5.08k	}
425	5.08k	}