/src/bloaty/third_party/capstone/arch/RISCV/RISCVGenAsmWriter.inc
Line | Count | Source |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Assembly Writer Source Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | /* Capstone Disassembly Engine */ |
10 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ |
11 | | |
12 | | #include <stdio.h> // debug |
13 | | #include <capstone/platform.h> |
14 | | #include <assert.h> |
15 | | |
16 | | |
17 | | /// printInstruction - This method is automatically generated by tablegen |
18 | | /// from the instruction set description. |
19 | | static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) |
20 | 0 | { |
21 | 0 | #ifndef CAPSTONE_DIET |
22 | 0 | static const char AsmStrs[] = { |
23 | 0 | /* 0 */ 'l', 'l', 'a', 9, 0, |
24 | 0 | /* 5 */ 's', 'f', 'e', 'n', 'c', 'e', '.', 'v', 'm', 'a', 9, 0, |
25 | 0 | /* 17 */ 's', 'r', 'a', 9, 0, |
26 | 0 | /* 22 */ 'l', 'b', 9, 0, |
27 | 0 | /* 26 */ 's', 'b', 9, 0, |
28 | 0 | /* 30 */ 'c', '.', 's', 'u', 'b', 9, 0, |
29 | 0 | /* 37 */ 'a', 'u', 'i', 'p', 'c', 9, 0, |
30 | 0 | /* 44 */ 'c', 's', 'r', 'r', 'c', 9, 0, |
31 | 0 | /* 51 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0, |
32 | 0 | /* 59 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0, |
33 | 0 | /* 68 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0, |
34 | 0 | /* 78 */ 's', 'c', '.', 'd', 9, 0, |
35 | 0 | /* 84 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0, |
36 | 0 | /* 92 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, |
37 | 0 | /* 101 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, |
38 | 0 | /* 111 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', 9, 0, |
39 | 0 | /* 121 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', 9, 0, |
40 | 0 | /* 131 */ 'f', 'l', 'e', '.', 'd', 9, 0, |
41 | 0 | /* 138 */ 'f', 's', 'g', 'n', 'j', '.', 'd', 9, 0, |
42 | 0 | /* 147 */ 'f', 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0, |
43 | 0 | /* 157 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0, |
44 | 0 | /* 165 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0, |
45 | 0 | /* 173 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', 9, 0, |
46 | 0 | /* 183 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 'd', 9, 0, |
47 | 0 | /* 193 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', 9, 0, |
48 | 0 | /* 204 */ 'f', 'e', 'q', '.', 'd', 9, 0, |
49 | 0 | /* 211 */ 'l', 'r', '.', 'd', 9, 0, |
50 | 0 | /* 217 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', 9, 0, |
51 | 0 | /* 226 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', 9, 0, |
52 | 0 | /* 236 */ 'f', 'c', 'v', 't', '.', 's', '.', 'd', 9, 0, |
53 | 0 | /* 246 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'd', 9, 0, |
54 | 0 | /* 256 */ 'f', 'l', 't', '.', 'd', 9, 0, |
55 | 0 | /* 263 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0, |
56 | 0 | /* 272 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 'd', 9, 0, |
57 | 0 | /* 283 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', 9, 0, |
58 | 0 | /* 294 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 'd', 9, 0, |
59 | 0 | /* 305 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', 9, 0, |
60 | 0 | /* 316 */ 'f', 'd', 'i', 'v', '.', 'd', 9, 0, |
61 | 0 | /* 324 */ 'f', 'c', 'v', 't', '.', 'w', '.', 'd', 9, 0, |
62 | 0 | /* 334 */ 'f', 'm', 'v', '.', 'x', '.', 'd', 9, 0, |
63 | 0 | /* 343 */ 'f', 'm', 'a', 'x', '.', 'd', 9, 0, |
64 | 0 | /* 351 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', 9, 0, |
65 | 0 | /* 361 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 'd', 9, 0, |
66 | 0 | /* 371 */ 'c', '.', 'a', 'd', 'd', 9, 0, |
67 | 0 | /* 378 */ 'c', '.', 'l', 'd', 9, 0, |
68 | 0 | /* 384 */ 'c', '.', 'f', 'l', 'd', 9, 0, |
69 | 0 | /* 391 */ 'c', '.', 'a', 'n', 'd', 9, 0, |
70 | 0 | /* 398 */ 'c', '.', 's', 'd', 9, 0, |
71 | 0 | /* 404 */ 'c', '.', 'f', 's', 'd', 9, 0, |
72 | 0 | /* 411 */ 'f', 'e', 'n', 'c', 'e', 9, 0, |
73 | 0 | /* 418 */ 'b', 'g', 'e', 9, 0, |
74 | 0 | /* 423 */ 'b', 'n', 'e', 9, 0, |
75 | 0 | /* 428 */ 'm', 'u', 'l', 'h', 9, 0, |
76 | 0 | /* 434 */ 's', 'h', 9, 0, |
77 | 0 | /* 438 */ 'f', 'e', 'n', 'c', 'e', '.', 'i', 9, 0, |
78 | 0 | /* 447 */ 'c', '.', 's', 'r', 'a', 'i', 9, 0, |
79 | 0 | /* 455 */ 'c', 's', 'r', 'r', 'c', 'i', 9, 0, |
80 | 0 | /* 463 */ 'c', '.', 'a', 'd', 'd', 'i', 9, 0, |
81 | 0 | /* 471 */ 'c', '.', 'a', 'n', 'd', 'i', 9, 0, |
82 | 0 | /* 479 */ 'w', 'f', 'i', 9, 0, |
83 | 0 | /* 484 */ 'c', '.', 'l', 'i', 9, 0, |
84 | 0 | /* 490 */ 'c', '.', 's', 'l', 'l', 'i', 9, 0, |
85 | 0 | /* 498 */ 'c', '.', 's', 'r', 'l', 'i', 9, 0, |
86 | 0 | /* 506 */ 'x', 'o', 'r', 'i', 9, 0, |
87 | 0 | /* 512 */ 'c', 's', 'r', 'r', 's', 'i', 9, 0, |
88 | 0 | /* 520 */ 's', 'l', 't', 'i', 9, 0, |
89 | 0 | /* 526 */ 'c', '.', 'l', 'u', 'i', 9, 0, |
90 | 0 | /* 533 */ 'c', 's', 'r', 'r', 'w', 'i', 9, 0, |
91 | 0 | /* 541 */ 'c', '.', 'j', 9, 0, |
92 | 0 | /* 546 */ 'c', '.', 'e', 'b', 'r', 'e', 'a', 'k', 9, 0, |
93 | 0 | /* 556 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0, |
94 | 0 | /* 566 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 9, 0, |
95 | 0 | /* 576 */ 'c', '.', 'j', 'a', 'l', 9, 0, |
96 | 0 | /* 583 */ 't', 'a', 'i', 'l', 9, 0, |
97 | 0 | /* 589 */ 'e', 'c', 'a', 'l', 'l', 9, 0, |
98 | 0 | /* 596 */ 's', 'l', 'l', 9, 0, |
99 | 0 | /* 601 */ 's', 'c', '.', 'd', '.', 'r', 'l', 9, 0, |
100 | 0 | /* 610 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'r', 'l', 9, 0, |
101 | 0 | /* 623 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'r', 'l', 9, 0, |
102 | 0 | /* 636 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'r', 'l', 9, 0, |
103 | 0 | /* 649 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'r', 'l', 9, 0, |
104 | 0 | /* 663 */ 'l', 'r', '.', 'd', '.', 'r', 'l', 9, 0, |
105 | 0 | /* 672 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0, |
106 | 0 | /* 684 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0, |
107 | 0 | /* 697 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'r', 'l', 9, 0, |
108 | 0 | /* 711 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'r', 'l', 9, 0, |
109 | 0 | /* 725 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'r', 'l', 9, 0, |
110 | 0 | /* 738 */ 's', 'c', '.', 'w', '.', 'r', 'l', 9, 0, |
111 | 0 | /* 747 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'r', 'l', 9, 0, |
112 | 0 | /* 760 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'r', 'l', 9, 0, |
113 | 0 | /* 773 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'r', 'l', 9, 0, |
114 | 0 | /* 786 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'r', 'l', 9, 0, |
115 | 0 | /* 800 */ 'l', 'r', '.', 'w', '.', 'r', 'l', 9, 0, |
116 | 0 | /* 809 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0, |
117 | 0 | /* 821 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0, |
118 | 0 | /* 834 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'r', 'l', 9, 0, |
119 | 0 | /* 848 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'r', 'l', 9, 0, |
120 | 0 | /* 862 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'r', 'l', 9, 0, |
121 | 0 | /* 875 */ 's', 'c', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
122 | 0 | /* 886 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
123 | 0 | /* 901 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
124 | 0 | /* 916 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
125 | 0 | /* 931 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
126 | 0 | /* 947 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
127 | 0 | /* 958 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
128 | 0 | /* 972 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
129 | 0 | /* 987 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
130 | 0 | /* 1003 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
131 | 0 | /* 1019 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
132 | 0 | /* 1034 */ 's', 'c', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
133 | 0 | /* 1045 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
134 | 0 | /* 1060 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
135 | 0 | /* 1075 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
136 | 0 | /* 1090 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
137 | 0 | /* 1106 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
138 | 0 | /* 1117 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
139 | 0 | /* 1131 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
140 | 0 | /* 1146 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
141 | 0 | /* 1162 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
142 | 0 | /* 1178 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
143 | 0 | /* 1193 */ 's', 'r', 'l', 9, 0, |
144 | 0 | /* 1198 */ 'm', 'u', 'l', 9, 0, |
145 | 0 | /* 1203 */ 'r', 'e', 'm', 9, 0, |
146 | 0 | /* 1208 */ 'c', '.', 'a', 'd', 'd', 'i', '4', 's', 'p', 'n', 9, 0, |
147 | 0 | /* 1220 */ 'f', 'e', 'n', 'c', 'e', '.', 't', 's', 'o', 9, 0, |
148 | 0 | /* 1231 */ 'c', '.', 'u', 'n', 'i', 'm', 'p', 9, 0, |
149 | 0 | /* 1240 */ 'c', '.', 'n', 'o', 'p', 9, 0, |
150 | 0 | /* 1247 */ 'c', '.', 'a', 'd', 'd', 'i', '1', '6', 's', 'p', 9, 0, |
151 | 0 | /* 1259 */ 'c', '.', 'l', 'd', 's', 'p', 9, 0, |
152 | 0 | /* 1267 */ 'c', '.', 'f', 'l', 'd', 's', 'p', 9, 0, |
153 | 0 | /* 1276 */ 'c', '.', 's', 'd', 's', 'p', 9, 0, |
154 | 0 | /* 1284 */ 'c', '.', 'f', 's', 'd', 's', 'p', 9, 0, |
155 | 0 | /* 1293 */ 'c', '.', 'l', 'w', 's', 'p', 9, 0, |
156 | 0 | /* 1301 */ 'c', '.', 'f', 'l', 'w', 's', 'p', 9, 0, |
157 | 0 | /* 1310 */ 'c', '.', 's', 'w', 's', 'p', 9, 0, |
158 | 0 | /* 1318 */ 'c', '.', 'f', 's', 'w', 's', 'p', 9, 0, |
159 | 0 | /* 1327 */ 's', 'c', '.', 'd', '.', 'a', 'q', 9, 0, |
160 | 0 | /* 1336 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 9, 0, |
161 | 0 | /* 1349 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 9, 0, |
162 | 0 | /* 1362 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 9, 0, |
163 | 0 | /* 1375 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 9, 0, |
164 | 0 | /* 1389 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 9, 0, |
165 | 0 | /* 1398 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0, |
166 | 0 | /* 1410 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0, |
167 | 0 | /* 1423 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 9, 0, |
168 | 0 | /* 1437 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 9, 0, |
169 | 0 | /* 1451 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 9, 0, |
170 | 0 | /* 1464 */ 's', 'c', '.', 'w', '.', 'a', 'q', 9, 0, |
171 | 0 | /* 1473 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 9, 0, |
172 | 0 | /* 1486 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 9, 0, |
173 | 0 | /* 1499 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 9, 0, |
174 | 0 | /* 1512 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 9, 0, |
175 | 0 | /* 1526 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 9, 0, |
176 | 0 | /* 1535 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0, |
177 | 0 | /* 1547 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0, |
178 | 0 | /* 1560 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 9, 0, |
179 | 0 | /* 1574 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 9, 0, |
180 | 0 | /* 1588 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 9, 0, |
181 | 0 | /* 1601 */ 'b', 'e', 'q', 9, 0, |
182 | 0 | /* 1606 */ 'c', '.', 'j', 'r', 9, 0, |
183 | 0 | /* 1612 */ 'c', '.', 'j', 'a', 'l', 'r', 9, 0, |
184 | 0 | /* 1620 */ 'c', '.', 'o', 'r', 9, 0, |
185 | 0 | /* 1626 */ 'c', '.', 'x', 'o', 'r', 9, 0, |
186 | 0 | /* 1633 */ 'f', 's', 'u', 'b', '.', 's', 9, 0, |
187 | 0 | /* 1641 */ 'f', 'm', 's', 'u', 'b', '.', 's', 9, 0, |
188 | 0 | /* 1650 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 's', 9, 0, |
189 | 0 | /* 1660 */ 'f', 'c', 'v', 't', '.', 'd', '.', 's', 9, 0, |
190 | 0 | /* 1670 */ 'f', 'a', 'd', 'd', '.', 's', 9, 0, |
191 | 0 | /* 1678 */ 'f', 'm', 'a', 'd', 'd', '.', 's', 9, 0, |
192 | 0 | /* 1687 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 's', 9, 0, |
193 | 0 | /* 1697 */ 'f', 'l', 'e', '.', 's', 9, 0, |
194 | 0 | /* 1704 */ 'f', 's', 'g', 'n', 'j', '.', 's', 9, 0, |
195 | 0 | /* 1713 */ 'f', 'c', 'v', 't', '.', 'l', '.', 's', 9, 0, |
196 | 0 | /* 1723 */ 'f', 'm', 'u', 'l', '.', 's', 9, 0, |
197 | 0 | /* 1731 */ 'f', 'm', 'i', 'n', '.', 's', 9, 0, |
198 | 0 | /* 1739 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 's', 9, 0, |
199 | 0 | /* 1749 */ 'f', 'e', 'q', '.', 's', 9, 0, |
200 | 0 | /* 1756 */ 'f', 'c', 'l', 'a', 's', 's', '.', 's', 9, 0, |
201 | 0 | /* 1766 */ 'f', 'l', 't', '.', 's', 9, 0, |
202 | 0 | /* 1773 */ 'f', 's', 'q', 'r', 't', '.', 's', 9, 0, |
203 | 0 | /* 1782 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 's', 9, 0, |
204 | 0 | /* 1793 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 's', 9, 0, |
205 | 0 | /* 1804 */ 'f', 'd', 'i', 'v', '.', 's', 9, 0, |
206 | 0 | /* 1812 */ 'f', 'c', 'v', 't', '.', 'w', '.', 's', 9, 0, |
207 | 0 | /* 1822 */ 'f', 'm', 'a', 'x', '.', 's', 9, 0, |
208 | 0 | /* 1830 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 's', 9, 0, |
209 | 0 | /* 1840 */ 'c', 's', 'r', 'r', 's', 9, 0, |
210 | 0 | /* 1847 */ 'm', 'r', 'e', 't', 9, 0, |
211 | 0 | /* 1853 */ 's', 'r', 'e', 't', 9, 0, |
212 | 0 | /* 1859 */ 'u', 'r', 'e', 't', 9, 0, |
213 | 0 | /* 1865 */ 'b', 'l', 't', 9, 0, |
214 | 0 | /* 1870 */ 's', 'l', 't', 9, 0, |
215 | 0 | /* 1875 */ 'l', 'b', 'u', 9, 0, |
216 | 0 | /* 1880 */ 'b', 'g', 'e', 'u', 9, 0, |
217 | 0 | /* 1886 */ 'm', 'u', 'l', 'h', 'u', 9, 0, |
218 | 0 | /* 1893 */ 's', 'l', 't', 'i', 'u', 9, 0, |
219 | 0 | /* 1900 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 'u', 9, 0, |
220 | 0 | /* 1911 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 'u', 9, 0, |
221 | 0 | /* 1922 */ 'r', 'e', 'm', 'u', 9, 0, |
222 | 0 | /* 1928 */ 'm', 'u', 'l', 'h', 's', 'u', 9, 0, |
223 | 0 | /* 1936 */ 'b', 'l', 't', 'u', 9, 0, |
224 | 0 | /* 1942 */ 's', 'l', 't', 'u', 9, 0, |
225 | 0 | /* 1948 */ 'd', 'i', 'v', 'u', 9, 0, |
226 | 0 | /* 1954 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 'u', 9, 0, |
227 | 0 | /* 1965 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 'u', 9, 0, |
228 | 0 | /* 1976 */ 'l', 'w', 'u', 9, 0, |
229 | 0 | /* 1981 */ 'd', 'i', 'v', 9, 0, |
230 | 0 | /* 1986 */ 'c', '.', 'm', 'v', 9, 0, |
231 | 0 | /* 1992 */ 's', 'c', '.', 'w', 9, 0, |
232 | 0 | /* 1998 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0, |
233 | 0 | /* 2008 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', 9, 0, |
234 | 0 | /* 2018 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', 9, 0, |
235 | 0 | /* 2028 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', 9, 0, |
236 | 0 | /* 2038 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', 9, 0, |
237 | 0 | /* 2049 */ 'l', 'r', '.', 'w', 9, 0, |
238 | 0 | /* 2055 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', 9, 0, |
239 | 0 | /* 2064 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', 9, 0, |
240 | 0 | /* 2074 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 9, 0, |
241 | 0 | /* 2084 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', 9, 0, |
242 | 0 | /* 2095 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', 9, 0, |
243 | 0 | /* 2106 */ 'f', 'm', 'v', '.', 'x', '.', 'w', 9, 0, |
244 | 0 | /* 2115 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', 9, 0, |
245 | 0 | /* 2125 */ 's', 'r', 'a', 'w', 9, 0, |
246 | 0 | /* 2131 */ 'c', '.', 's', 'u', 'b', 'w', 9, 0, |
247 | 0 | /* 2139 */ 'c', '.', 'a', 'd', 'd', 'w', 9, 0, |
248 | 0 | /* 2147 */ 's', 'r', 'a', 'i', 'w', 9, 0, |
249 | 0 | /* 2154 */ 'c', '.', 'a', 'd', 'd', 'i', 'w', 9, 0, |
250 | 0 | /* 2163 */ 's', 'l', 'l', 'i', 'w', 9, 0, |
251 | 0 | /* 2170 */ 's', 'r', 'l', 'i', 'w', 9, 0, |
252 | 0 | /* 2177 */ 'c', '.', 'l', 'w', 9, 0, |
253 | 0 | /* 2183 */ 'c', '.', 'f', 'l', 'w', 9, 0, |
254 | 0 | /* 2190 */ 's', 'l', 'l', 'w', 9, 0, |
255 | 0 | /* 2196 */ 's', 'r', 'l', 'w', 9, 0, |
256 | 0 | /* 2202 */ 'm', 'u', 'l', 'w', 9, 0, |
257 | 0 | /* 2208 */ 'r', 'e', 'm', 'w', 9, 0, |
258 | 0 | /* 2214 */ 'c', 's', 'r', 'r', 'w', 9, 0, |
259 | 0 | /* 2221 */ 'c', '.', 's', 'w', 9, 0, |
260 | 0 | /* 2227 */ 'c', '.', 'f', 's', 'w', 9, 0, |
261 | 0 | /* 2234 */ 'r', 'e', 'm', 'u', 'w', 9, 0, |
262 | 0 | /* 2241 */ 'd', 'i', 'v', 'u', 'w', 9, 0, |
263 | 0 | /* 2248 */ 'd', 'i', 'v', 'w', 9, 0, |
264 | 0 | /* 2254 */ 'f', 'm', 'v', '.', 'd', '.', 'x', 9, 0, |
265 | 0 | /* 2263 */ 'f', 'm', 'v', '.', 'w', '.', 'x', 9, 0, |
266 | 0 | /* 2272 */ 'c', '.', 'b', 'n', 'e', 'z', 9, 0, |
267 | 0 | /* 2280 */ 'c', '.', 'b', 'e', 'q', 'z', 9, 0, |
268 | 0 | /* 2288 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, |
269 | 0 | /* 2319 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, |
270 | 0 | /* 2343 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, |
271 | 0 | /* 2368 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, |
272 | 0 | /* 2391 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, |
273 | 0 | /* 2414 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, |
274 | 0 | /* 2436 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, |
275 | 0 | /* 2449 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, |
276 | 0 | /* 2456 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, |
277 | 0 | /* 2466 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, |
278 | 0 | /* 2476 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, |
279 | 0 | /* 2491 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, |
280 | 0 | }; |
281 | 0 | #endif |
282 | |
|
283 | 0 | static const uint16_t OpInfo0[] = { |
284 | 0 | 0U, // PHI |
285 | 0 | 0U, // INLINEASM |
286 | 0 | 0U, // INLINEASM_BR |
287 | 0 | 0U, // CFI_INSTRUCTION |
288 | 0 | 0U, // EH_LABEL |
289 | 0 | 0U, // GC_LABEL |
290 | 0 | 0U, // ANNOTATION_LABEL |
291 | 0 | 0U, // KILL |
292 | 0 | 0U, // EXTRACT_SUBREG |
293 | 0 | 0U, // INSERT_SUBREG |
294 | 0 | 0U, // IMPLICIT_DEF |
295 | 0 | 0U, // SUBREG_TO_REG |
296 | 0 | 0U, // COPY_TO_REGCLASS |
297 | 0 | 2457U, // DBG_VALUE |
298 | 0 | 2467U, // DBG_LABEL |
299 | 0 | 0U, // REG_SEQUENCE |
300 | 0 | 0U, // COPY |
301 | 0 | 2450U, // BUNDLE |
302 | 0 | 2477U, // LIFETIME_START |
303 | 0 | 2437U, // LIFETIME_END |
304 | 0 | 0U, // STACKMAP |
305 | 0 | 2492U, // FENTRY_CALL |
306 | 0 | 0U, // PATCHPOINT |
307 | 0 | 0U, // LOAD_STACK_GUARD |
308 | 0 | 0U, // STATEPOINT |
309 | 0 | 0U, // LOCAL_ESCAPE |
310 | 0 | 0U, // FAULTING_OP |
311 | 0 | 0U, // PATCHABLE_OP |
312 | 0 | 2369U, // PATCHABLE_FUNCTION_ENTER |
313 | 0 | 2289U, // PATCHABLE_RET |
314 | 0 | 2415U, // PATCHABLE_FUNCTION_EXIT |
315 | 0 | 2392U, // PATCHABLE_TAIL_CALL |
316 | 0 | 2344U, // PATCHABLE_EVENT_CALL |
317 | 0 | 2320U, // PATCHABLE_TYPED_EVENT_CALL |
318 | 0 | 0U, // ICALL_BRANCH_FUNNEL |
319 | 0 | 0U, // G_ADD |
320 | 0 | 0U, // G_SUB |
321 | 0 | 0U, // G_MUL |
322 | 0 | 0U, // G_SDIV |
323 | 0 | 0U, // G_UDIV |
324 | 0 | 0U, // G_SREM |
325 | 0 | 0U, // G_UREM |
326 | 0 | 0U, // G_AND |
327 | 0 | 0U, // G_OR |
328 | 0 | 0U, // G_XOR |
329 | 0 | 0U, // G_IMPLICIT_DEF |
330 | 0 | 0U, // G_PHI |
331 | 0 | 0U, // G_FRAME_INDEX |
332 | 0 | 0U, // G_GLOBAL_VALUE |
333 | 0 | 0U, // G_EXTRACT |
334 | 0 | 0U, // G_UNMERGE_VALUES |
335 | 0 | 0U, // G_INSERT |
336 | 0 | 0U, // G_MERGE_VALUES |
337 | 0 | 0U, // G_BUILD_VECTOR |
338 | 0 | 0U, // G_BUILD_VECTOR_TRUNC |
339 | 0 | 0U, // G_CONCAT_VECTORS |
340 | 0 | 0U, // G_PTRTOINT |
341 | 0 | 0U, // G_INTTOPTR |
342 | 0 | 0U, // G_BITCAST |
343 | 0 | 0U, // G_INTRINSIC_TRUNC |
344 | 0 | 0U, // G_INTRINSIC_ROUND |
345 | 0 | 0U, // G_LOAD |
346 | 0 | 0U, // G_SEXTLOAD |
347 | 0 | 0U, // G_ZEXTLOAD |
348 | 0 | 0U, // G_STORE |
349 | 0 | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
350 | 0 | 0U, // G_ATOMIC_CMPXCHG |
351 | 0 | 0U, // G_ATOMICRMW_XCHG |
352 | 0 | 0U, // G_ATOMICRMW_ADD |
353 | 0 | 0U, // G_ATOMICRMW_SUB |
354 | 0 | 0U, // G_ATOMICRMW_AND |
355 | 0 | 0U, // G_ATOMICRMW_NAND |
356 | 0 | 0U, // G_ATOMICRMW_OR |
357 | 0 | 0U, // G_ATOMICRMW_XOR |
358 | 0 | 0U, // G_ATOMICRMW_MAX |
359 | 0 | 0U, // G_ATOMICRMW_MIN |
360 | 0 | 0U, // G_ATOMICRMW_UMAX |
361 | 0 | 0U, // G_ATOMICRMW_UMIN |
362 | 0 | 0U, // G_BRCOND |
363 | 0 | 0U, // G_BRINDIRECT |
364 | 0 | 0U, // G_INTRINSIC |
365 | 0 | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
366 | 0 | 0U, // G_ANYEXT |
367 | 0 | 0U, // G_TRUNC |
368 | 0 | 0U, // G_CONSTANT |
369 | 0 | 0U, // G_FCONSTANT |
370 | 0 | 0U, // G_VASTART |
371 | 0 | 0U, // G_VAARG |
372 | 0 | 0U, // G_SEXT |
373 | 0 | 0U, // G_ZEXT |
374 | 0 | 0U, // G_SHL |
375 | 0 | 0U, // G_LSHR |
376 | 0 | 0U, // G_ASHR |
377 | 0 | 0U, // G_ICMP |
378 | 0 | 0U, // G_FCMP |
379 | 0 | 0U, // G_SELECT |
380 | 0 | 0U, // G_UADDO |
381 | 0 | 0U, // G_UADDE |
382 | 0 | 0U, // G_USUBO |
383 | 0 | 0U, // G_USUBE |
384 | 0 | 0U, // G_SADDO |
385 | 0 | 0U, // G_SADDE |
386 | 0 | 0U, // G_SSUBO |
387 | 0 | 0U, // G_SSUBE |
388 | 0 | 0U, // G_UMULO |
389 | 0 | 0U, // G_SMULO |
390 | 0 | 0U, // G_UMULH |
391 | 0 | 0U, // G_SMULH |
392 | 0 | 0U, // G_FADD |
393 | 0 | 0U, // G_FSUB |
394 | 0 | 0U, // G_FMUL |
395 | 0 | 0U, // G_FMA |
396 | 0 | 0U, // G_FDIV |
397 | 0 | 0U, // G_FREM |
398 | 0 | 0U, // G_FPOW |
399 | 0 | 0U, // G_FEXP |
400 | 0 | 0U, // G_FEXP2 |
401 | 0 | 0U, // G_FLOG |
402 | 0 | 0U, // G_FLOG2 |
403 | 0 | 0U, // G_FLOG10 |
404 | 0 | 0U, // G_FNEG |
405 | 0 | 0U, // G_FPEXT |
406 | 0 | 0U, // G_FPTRUNC |
407 | 0 | 0U, // G_FPTOSI |
408 | 0 | 0U, // G_FPTOUI |
409 | 0 | 0U, // G_SITOFP |
410 | 0 | 0U, // G_UITOFP |
411 | 0 | 0U, // G_FABS |
412 | 0 | 0U, // G_FCANONICALIZE |
413 | 0 | 0U, // G_GEP |
414 | 0 | 0U, // G_PTR_MASK |
415 | 0 | 0U, // G_BR |
416 | 0 | 0U, // G_INSERT_VECTOR_ELT |
417 | 0 | 0U, // G_EXTRACT_VECTOR_ELT |
418 | 0 | 0U, // G_SHUFFLE_VECTOR |
419 | 0 | 0U, // G_CTTZ |
420 | 0 | 0U, // G_CTTZ_ZERO_UNDEF |
421 | 0 | 0U, // G_CTLZ |
422 | 0 | 0U, // G_CTLZ_ZERO_UNDEF |
423 | 0 | 0U, // G_CTPOP |
424 | 0 | 0U, // G_BSWAP |
425 | 0 | 0U, // G_FCEIL |
426 | 0 | 0U, // G_FCOS |
427 | 0 | 0U, // G_FSIN |
428 | 0 | 0U, // G_FSQRT |
429 | 0 | 0U, // G_FFLOOR |
430 | 0 | 0U, // G_ADDRSPACE_CAST |
431 | 0 | 0U, // G_BLOCK_ADDR |
432 | 0 | 4U, // ADJCALLSTACKDOWN |
433 | 0 | 4U, // ADJCALLSTACKUP |
434 | 0 | 4U, // BuildPairF64Pseudo |
435 | 0 | 4U, // PseudoAtomicLoadNand32 |
436 | 0 | 4U, // PseudoAtomicLoadNand64 |
437 | 0 | 4U, // PseudoBR |
438 | 0 | 4U, // PseudoBRIND |
439 | 0 | 4687U, // PseudoCALL |
440 | 0 | 4U, // PseudoCALLIndirect |
441 | 0 | 4U, // PseudoCmpXchg32 |
442 | 0 | 4U, // PseudoCmpXchg64 |
443 | 0 | 20482U, // PseudoLA |
444 | 0 | 20967U, // PseudoLI |
445 | 0 | 20481U, // PseudoLLA |
446 | 0 | 4U, // PseudoMaskedAtomicLoadAdd32 |
447 | 0 | 4U, // PseudoMaskedAtomicLoadMax32 |
448 | 0 | 4U, // PseudoMaskedAtomicLoadMin32 |
449 | 0 | 4U, // PseudoMaskedAtomicLoadNand32 |
450 | 0 | 4U, // PseudoMaskedAtomicLoadSub32 |
451 | 0 | 4U, // PseudoMaskedAtomicLoadUMax32 |
452 | 0 | 4U, // PseudoMaskedAtomicLoadUMin32 |
453 | 0 | 4U, // PseudoMaskedAtomicSwap32 |
454 | 0 | 4U, // PseudoMaskedCmpXchg32 |
455 | 0 | 4U, // PseudoRET |
456 | 0 | 4680U, // PseudoTAIL |
457 | 0 | 4U, // PseudoTAILIndirect |
458 | 0 | 4U, // Select_FPR32_Using_CC_GPR |
459 | 0 | 4U, // Select_FPR64_Using_CC_GPR |
460 | 0 | 4U, // Select_GPR_Using_CC_GPR |
461 | 0 | 4U, // SplitF64Pseudo |
462 | 0 | 20854U, // ADD |
463 | 0 | 20946U, // ADDI |
464 | 0 | 22637U, // ADDIW |
465 | 0 | 22622U, // ADDW |
466 | 0 | 20592U, // AMOADD_D |
467 | 0 | 21817U, // AMOADD_D_AQ |
468 | 0 | 21367U, // AMOADD_D_AQ_RL |
469 | 0 | 21091U, // AMOADD_D_RL |
470 | 0 | 22489U, // AMOADD_W |
471 | 0 | 21954U, // AMOADD_W_AQ |
472 | 0 | 21526U, // AMOADD_W_AQ_RL |
473 | 0 | 21228U, // AMOADD_W_RL |
474 | 0 | 20602U, // AMOAND_D |
475 | 0 | 21830U, // AMOAND_D_AQ |
476 | 0 | 21382U, // AMOAND_D_AQ_RL |
477 | 0 | 21104U, // AMOAND_D_RL |
478 | 0 | 22499U, // AMOAND_W |
479 | 0 | 21967U, // AMOAND_W_AQ |
480 | 0 | 21541U, // AMOAND_W_AQ_RL |
481 | 0 | 21241U, // AMOAND_W_RL |
482 | 0 | 20786U, // AMOMAXU_D |
483 | 0 | 21918U, // AMOMAXU_D_AQ |
484 | 0 | 21484U, // AMOMAXU_D_AQ_RL |
485 | 0 | 21192U, // AMOMAXU_D_RL |
486 | 0 | 22576U, // AMOMAXU_W |
487 | 0 | 22055U, // AMOMAXU_W_AQ |
488 | 0 | 21643U, // AMOMAXU_W_AQ_RL |
489 | 0 | 21329U, // AMOMAXU_W_RL |
490 | 0 | 20832U, // AMOMAX_D |
491 | 0 | 21932U, // AMOMAX_D_AQ |
492 | 0 | 21500U, // AMOMAX_D_AQ_RL |
493 | 0 | 21206U, // AMOMAX_D_RL |
494 | 0 | 22596U, // AMOMAX_W |
495 | 0 | 22069U, // AMOMAX_W_AQ |
496 | 0 | 21659U, // AMOMAX_W_AQ_RL |
497 | 0 | 21343U, // AMOMAX_W_RL |
498 | 0 | 20764U, // AMOMINU_D |
499 | 0 | 21904U, // AMOMINU_D_AQ |
500 | 0 | 21468U, // AMOMINU_D_AQ_RL |
501 | 0 | 21178U, // AMOMINU_D_RL |
502 | 0 | 22565U, // AMOMINU_W |
503 | 0 | 22041U, // AMOMINU_W_AQ |
504 | 0 | 21627U, // AMOMINU_W_AQ_RL |
505 | 0 | 21315U, // AMOMINU_W_RL |
506 | 0 | 20654U, // AMOMIN_D |
507 | 0 | 21843U, // AMOMIN_D_AQ |
508 | 0 | 21397U, // AMOMIN_D_AQ_RL |
509 | 0 | 21117U, // AMOMIN_D_RL |
510 | 0 | 22509U, // AMOMIN_W |
511 | 0 | 21980U, // AMOMIN_W_AQ |
512 | 0 | 21556U, // AMOMIN_W_AQ_RL |
513 | 0 | 21254U, // AMOMIN_W_RL |
514 | 0 | 20698U, // AMOOR_D |
515 | 0 | 21879U, // AMOOR_D_AQ |
516 | 0 | 21439U, // AMOOR_D_AQ_RL |
517 | 0 | 21153U, // AMOOR_D_RL |
518 | 0 | 22536U, // AMOOR_W |
519 | 0 | 22016U, // AMOOR_W_AQ |
520 | 0 | 21598U, // AMOOR_W_AQ_RL |
521 | 0 | 21290U, // AMOOR_W_RL |
522 | 0 | 20674U, // AMOSWAP_D |
523 | 0 | 21856U, // AMOSWAP_D_AQ |
524 | 0 | 21412U, // AMOSWAP_D_AQ_RL |
525 | 0 | 21130U, // AMOSWAP_D_RL |
526 | 0 | 22519U, // AMOSWAP_W |
527 | 0 | 21993U, // AMOSWAP_W_AQ |
528 | 0 | 21571U, // AMOSWAP_W_AQ_RL |
529 | 0 | 21267U, // AMOSWAP_W_RL |
530 | 0 | 20707U, // AMOXOR_D |
531 | 0 | 21891U, // AMOXOR_D_AQ |
532 | 0 | 21453U, // AMOXOR_D_AQ_RL |
533 | 0 | 21165U, // AMOXOR_D_RL |
534 | 0 | 22545U, // AMOXOR_W |
535 | 0 | 22028U, // AMOXOR_W_AQ |
536 | 0 | 21612U, // AMOXOR_W_AQ_RL |
537 | 0 | 21302U, // AMOXOR_W_RL |
538 | 0 | 20874U, // AND |
539 | 0 | 20954U, // ANDI |
540 | 0 | 20518U, // AUIPC |
541 | 0 | 22082U, // BEQ |
542 | 0 | 20899U, // BGE |
543 | 0 | 22361U, // BGEU |
544 | 0 | 22346U, // BLT |
545 | 0 | 22417U, // BLTU |
546 | 0 | 20904U, // BNE |
547 | 0 | 20525U, // CSRRC |
548 | 0 | 20936U, // CSRRCI |
549 | 0 | 22321U, // CSRRS |
550 | 0 | 20993U, // CSRRSI |
551 | 0 | 22695U, // CSRRW |
552 | 0 | 21014U, // CSRRWI |
553 | 0 | 8564U, // C_ADD |
554 | 0 | 8656U, // C_ADDI |
555 | 0 | 9440U, // C_ADDI16SP |
556 | 0 | 21689U, // C_ADDI4SPN |
557 | 0 | 10347U, // C_ADDIW |
558 | 0 | 10332U, // C_ADDW |
559 | 0 | 8584U, // C_AND |
560 | 0 | 8664U, // C_ANDI |
561 | 0 | 22761U, // C_BEQZ |
562 | 0 | 22753U, // C_BNEZ |
563 | 0 | 547U, // C_EBREAK |
564 | 0 | 20865U, // C_FLD |
565 | 0 | 21748U, // C_FLDSP |
566 | 0 | 22664U, // C_FLW |
567 | 0 | 21782U, // C_FLWSP |
568 | 0 | 20885U, // C_FSD |
569 | 0 | 21765U, // C_FSDSP |
570 | 0 | 22708U, // C_FSW |
571 | 0 | 21799U, // C_FSWSP |
572 | 0 | 4638U, // C_J |
573 | 0 | 4673U, // C_JAL |
574 | 0 | 5709U, // C_JALR |
575 | 0 | 5703U, // C_JR |
576 | 0 | 20859U, // C_LD |
577 | 0 | 21740U, // C_LDSP |
578 | 0 | 20965U, // C_LI |
579 | 0 | 21007U, // C_LUI |
580 | 0 | 22658U, // C_LW |
581 | 0 | 21774U, // C_LWSP |
582 | 0 | 22467U, // C_MV |
583 | 0 | 1241U, // C_NOP |
584 | 0 | 9813U, // C_OR |
585 | 0 | 20879U, // C_SD |
586 | 0 | 21757U, // C_SDSP |
587 | 0 | 8683U, // C_SLLI |
588 | 0 | 8640U, // C_SRAI |
589 | 0 | 8691U, // C_SRLI |
590 | 0 | 8223U, // C_SUB |
591 | 0 | 10324U, // C_SUBW |
592 | 0 | 22702U, // C_SW |
593 | 0 | 21791U, // C_SWSP |
594 | 0 | 1232U, // C_UNIMP |
595 | 0 | 9819U, // C_XOR |
596 | 0 | 22462U, // DIV |
597 | 0 | 22429U, // DIVU |
598 | 0 | 22722U, // DIVUW |
599 | 0 | 22729U, // DIVW |
600 | 0 | 549U, // EBREAK |
601 | 0 | 590U, // ECALL |
602 | 0 | 20565U, // FADD_D |
603 | 0 | 22151U, // FADD_S |
604 | 0 | 20727U, // FCLASS_D |
605 | 0 | 22237U, // FCLASS_S |
606 | 0 | 21037U, // FCVT_D_L |
607 | 0 | 22381U, // FCVT_D_LU |
608 | 0 | 22141U, // FCVT_D_S |
609 | 0 | 22479U, // FCVT_D_W |
610 | 0 | 22435U, // FCVT_D_WU |
611 | 0 | 20753U, // FCVT_LU_D |
612 | 0 | 22263U, // FCVT_LU_S |
613 | 0 | 20628U, // FCVT_L_D |
614 | 0 | 22194U, // FCVT_L_S |
615 | 0 | 20717U, // FCVT_S_D |
616 | 0 | 21047U, // FCVT_S_L |
617 | 0 | 22392U, // FCVT_S_LU |
618 | 0 | 22555U, // FCVT_S_W |
619 | 0 | 22446U, // FCVT_S_WU |
620 | 0 | 20775U, // FCVT_WU_D |
621 | 0 | 22274U, // FCVT_WU_S |
622 | 0 | 20805U, // FCVT_W_D |
623 | 0 | 22293U, // FCVT_W_S |
624 | 0 | 20797U, // FDIV_D |
625 | 0 | 22285U, // FDIV_S |
626 | 0 | 12700U, // FENCE |
627 | 0 | 439U, // FENCE_I |
628 | 0 | 1221U, // FENCE_TSO |
629 | 0 | 20685U, // FEQ_D |
630 | 0 | 22230U, // FEQ_S |
631 | 0 | 20867U, // FLD |
632 | 0 | 20612U, // FLE_D |
633 | 0 | 22178U, // FLE_S |
634 | 0 | 20737U, // FLT_D |
635 | 0 | 22247U, // FLT_S |
636 | 0 | 22666U, // FLW |
637 | 0 | 20573U, // FMADD_D |
638 | 0 | 22159U, // FMADD_S |
639 | 0 | 20824U, // FMAX_D |
640 | 0 | 22303U, // FMAX_S |
641 | 0 | 20646U, // FMIN_D |
642 | 0 | 22212U, // FMIN_S |
643 | 0 | 20540U, // FMSUB_D |
644 | 0 | 22122U, // FMSUB_S |
645 | 0 | 20638U, // FMUL_D |
646 | 0 | 22204U, // FMUL_S |
647 | 0 | 22735U, // FMV_D_X |
648 | 0 | 22744U, // FMV_W_X |
649 | 0 | 20815U, // FMV_X_D |
650 | 0 | 22587U, // FMV_X_W |
651 | 0 | 20582U, // FNMADD_D |
652 | 0 | 22168U, // FNMADD_S |
653 | 0 | 20549U, // FNMSUB_D |
654 | 0 | 22131U, // FNMSUB_S |
655 | 0 | 20887U, // FSD |
656 | 0 | 20664U, // FSGNJN_D |
657 | 0 | 22220U, // FSGNJN_S |
658 | 0 | 20842U, // FSGNJX_D |
659 | 0 | 22311U, // FSGNJX_S |
660 | 0 | 20619U, // FSGNJ_D |
661 | 0 | 22185U, // FSGNJ_S |
662 | 0 | 20744U, // FSQRT_D |
663 | 0 | 22254U, // FSQRT_S |
664 | 0 | 20532U, // FSUB_D |
665 | 0 | 22114U, // FSUB_S |
666 | 0 | 22710U, // FSW |
667 | 0 | 21059U, // JAL |
668 | 0 | 22095U, // JALR |
669 | 0 | 20503U, // LB |
670 | 0 | 22356U, // LBU |
671 | 0 | 20861U, // LD |
672 | 0 | 20911U, // LH |
673 | 0 | 22369U, // LHU |
674 | 0 | 37076U, // LR_D |
675 | 0 | 38254U, // LR_D_AQ |
676 | 0 | 37812U, // LR_D_AQ_RL |
677 | 0 | 37528U, // LR_D_RL |
678 | 0 | 38914U, // LR_W |
679 | 0 | 38391U, // LR_W_AQ |
680 | 0 | 37971U, // LR_W_AQ_RL |
681 | 0 | 37665U, // LR_W_RL |
682 | 0 | 21009U, // LUI |
683 | 0 | 22660U, // LW |
684 | 0 | 22457U, // LWU |
685 | 0 | 1848U, // MRET |
686 | 0 | 21679U, // MUL |
687 | 0 | 20909U, // MULH |
688 | 0 | 22409U, // MULHSU |
689 | 0 | 22367U, // MULHU |
690 | 0 | 22683U, // MULW |
691 | 0 | 22103U, // OR |
692 | 0 | 20988U, // ORI |
693 | 0 | 21684U, // REM |
694 | 0 | 22403U, // REMU |
695 | 0 | 22715U, // REMUW |
696 | 0 | 22689U, // REMW |
697 | 0 | 20507U, // SB |
698 | 0 | 20559U, // SC_D |
699 | 0 | 21808U, // SC_D_AQ |
700 | 0 | 21356U, // SC_D_AQ_RL |
701 | 0 | 21082U, // SC_D_RL |
702 | 0 | 22473U, // SC_W |
703 | 0 | 21945U, // SC_W_AQ |
704 | 0 | 21515U, // SC_W_AQ_RL |
705 | 0 | 21219U, // SC_W_RL |
706 | 0 | 20881U, // SD |
707 | 0 | 20486U, // SFENCE_VMA |
708 | 0 | 20915U, // SH |
709 | 0 | 21077U, // SLL |
710 | 0 | 20973U, // SLLI |
711 | 0 | 22644U, // SLLIW |
712 | 0 | 22671U, // SLLW |
713 | 0 | 22351U, // SLT |
714 | 0 | 21001U, // SLTI |
715 | 0 | 22374U, // SLTIU |
716 | 0 | 22423U, // SLTU |
717 | 0 | 20498U, // SRA |
718 | 0 | 20930U, // SRAI |
719 | 0 | 22628U, // SRAIW |
720 | 0 | 22606U, // SRAW |
721 | 0 | 1854U, // SRET |
722 | 0 | 21674U, // SRL |
723 | 0 | 20981U, // SRLI |
724 | 0 | 22651U, // SRLIW |
725 | 0 | 22677U, // SRLW |
726 | 0 | 20513U, // SUB |
727 | 0 | 22614U, // SUBW |
728 | 0 | 22704U, // SW |
729 | 0 | 1234U, // UNIMP |
730 | 0 | 1860U, // URET |
731 | 0 | 480U, // WFI |
732 | 0 | 22109U, // XOR |
733 | 0 | 20987U, // XORI |
734 | 0 | }; |
735 | |
|
736 | 0 | static const uint8_t OpInfo1[] = { |
737 | 0 | 0U, // PHI |
738 | 0 | 0U, // INLINEASM |
739 | 0 | 0U, // INLINEASM_BR |
740 | 0 | 0U, // CFI_INSTRUCTION |
741 | 0 | 0U, // EH_LABEL |
742 | 0 | 0U, // GC_LABEL |
743 | 0 | 0U, // ANNOTATION_LABEL |
744 | 0 | 0U, // KILL |
745 | 0 | 0U, // EXTRACT_SUBREG |
746 | 0 | 0U, // INSERT_SUBREG |
747 | 0 | 0U, // IMPLICIT_DEF |
748 | 0 | 0U, // SUBREG_TO_REG |
749 | 0 | 0U, // COPY_TO_REGCLASS |
750 | 0 | 0U, // DBG_VALUE |
751 | 0 | 0U, // DBG_LABEL |
752 | 0 | 0U, // REG_SEQUENCE |
753 | 0 | 0U, // COPY |
754 | 0 | 0U, // BUNDLE |
755 | 0 | 0U, // LIFETIME_START |
756 | 0 | 0U, // LIFETIME_END |
757 | 0 | 0U, // STACKMAP |
758 | 0 | 0U, // FENTRY_CALL |
759 | 0 | 0U, // PATCHPOINT |
760 | 0 | 0U, // LOAD_STACK_GUARD |
761 | 0 | 0U, // STATEPOINT |
762 | 0 | 0U, // LOCAL_ESCAPE |
763 | 0 | 0U, // FAULTING_OP |
764 | 0 | 0U, // PATCHABLE_OP |
765 | 0 | 0U, // PATCHABLE_FUNCTION_ENTER |
766 | 0 | 0U, // PATCHABLE_RET |
767 | 0 | 0U, // PATCHABLE_FUNCTION_EXIT |
768 | 0 | 0U, // PATCHABLE_TAIL_CALL |
769 | 0 | 0U, // PATCHABLE_EVENT_CALL |
770 | 0 | 0U, // PATCHABLE_TYPED_EVENT_CALL |
771 | 0 | 0U, // ICALL_BRANCH_FUNNEL |
772 | 0 | 0U, // G_ADD |
773 | 0 | 0U, // G_SUB |
774 | 0 | 0U, // G_MUL |
775 | 0 | 0U, // G_SDIV |
776 | 0 | 0U, // G_UDIV |
777 | 0 | 0U, // G_SREM |
778 | 0 | 0U, // G_UREM |
779 | 0 | 0U, // G_AND |
780 | 0 | 0U, // G_OR |
781 | 0 | 0U, // G_XOR |
782 | 0 | 0U, // G_IMPLICIT_DEF |
783 | 0 | 0U, // G_PHI |
784 | 0 | 0U, // G_FRAME_INDEX |
785 | 0 | 0U, // G_GLOBAL_VALUE |
786 | 0 | 0U, // G_EXTRACT |
787 | 0 | 0U, // G_UNMERGE_VALUES |
788 | 0 | 0U, // G_INSERT |
789 | 0 | 0U, // G_MERGE_VALUES |
790 | 0 | 0U, // G_BUILD_VECTOR |
791 | 0 | 0U, // G_BUILD_VECTOR_TRUNC |
792 | 0 | 0U, // G_CONCAT_VECTORS |
793 | 0 | 0U, // G_PTRTOINT |
794 | 0 | 0U, // G_INTTOPTR |
795 | 0 | 0U, // G_BITCAST |
796 | 0 | 0U, // G_INTRINSIC_TRUNC |
797 | 0 | 0U, // G_INTRINSIC_ROUND |
798 | 0 | 0U, // G_LOAD |
799 | 0 | 0U, // G_SEXTLOAD |
800 | 0 | 0U, // G_ZEXTLOAD |
801 | 0 | 0U, // G_STORE |
802 | 0 | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
803 | 0 | 0U, // G_ATOMIC_CMPXCHG |
804 | 0 | 0U, // G_ATOMICRMW_XCHG |
805 | 0 | 0U, // G_ATOMICRMW_ADD |
806 | 0 | 0U, // G_ATOMICRMW_SUB |
807 | 0 | 0U, // G_ATOMICRMW_AND |
808 | 0 | 0U, // G_ATOMICRMW_NAND |
809 | 0 | 0U, // G_ATOMICRMW_OR |
810 | 0 | 0U, // G_ATOMICRMW_XOR |
811 | 0 | 0U, // G_ATOMICRMW_MAX |
812 | 0 | 0U, // G_ATOMICRMW_MIN |
813 | 0 | 0U, // G_ATOMICRMW_UMAX |
814 | 0 | 0U, // G_ATOMICRMW_UMIN |
815 | 0 | 0U, // G_BRCOND |
816 | 0 | 0U, // G_BRINDIRECT |
817 | 0 | 0U, // G_INTRINSIC |
818 | 0 | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
819 | 0 | 0U, // G_ANYEXT |
820 | 0 | 0U, // G_TRUNC |
821 | 0 | 0U, // G_CONSTANT |
822 | 0 | 0U, // G_FCONSTANT |
823 | 0 | 0U, // G_VASTART |
824 | 0 | 0U, // G_VAARG |
825 | 0 | 0U, // G_SEXT |
826 | 0 | 0U, // G_ZEXT |
827 | 0 | 0U, // G_SHL |
828 | 0 | 0U, // G_LSHR |
829 | 0 | 0U, // G_ASHR |
830 | 0 | 0U, // G_ICMP |
831 | 0 | 0U, // G_FCMP |
832 | 0 | 0U, // G_SELECT |
833 | 0 | 0U, // G_UADDO |
834 | 0 | 0U, // G_UADDE |
835 | 0 | 0U, // G_USUBO |
836 | 0 | 0U, // G_USUBE |
837 | 0 | 0U, // G_SADDO |
838 | 0 | 0U, // G_SADDE |
839 | 0 | 0U, // G_SSUBO |
840 | 0 | 0U, // G_SSUBE |
841 | 0 | 0U, // G_UMULO |
842 | 0 | 0U, // G_SMULO |
843 | 0 | 0U, // G_UMULH |
844 | 0 | 0U, // G_SMULH |
845 | 0 | 0U, // G_FADD |
846 | 0 | 0U, // G_FSUB |
847 | 0 | 0U, // G_FMUL |
848 | 0 | 0U, // G_FMA |
849 | 0 | 0U, // G_FDIV |
850 | 0 | 0U, // G_FREM |
851 | 0 | 0U, // G_FPOW |
852 | 0 | 0U, // G_FEXP |
853 | 0 | 0U, // G_FEXP2 |
854 | 0 | 0U, // G_FLOG |
855 | 0 | 0U, // G_FLOG2 |
856 | 0 | 0U, // G_FLOG10 |
857 | 0 | 0U, // G_FNEG |
858 | 0 | 0U, // G_FPEXT |
859 | 0 | 0U, // G_FPTRUNC |
860 | 0 | 0U, // G_FPTOSI |
861 | 0 | 0U, // G_FPTOUI |
862 | 0 | 0U, // G_SITOFP |
863 | 0 | 0U, // G_UITOFP |
864 | 0 | 0U, // G_FABS |
865 | 0 | 0U, // G_FCANONICALIZE |
866 | 0 | 0U, // G_GEP |
867 | 0 | 0U, // G_PTR_MASK |
868 | 0 | 0U, // G_BR |
869 | 0 | 0U, // G_INSERT_VECTOR_ELT |
870 | 0 | 0U, // G_EXTRACT_VECTOR_ELT |
871 | 0 | 0U, // G_SHUFFLE_VECTOR |
872 | 0 | 0U, // G_CTTZ |
873 | 0 | 0U, // G_CTTZ_ZERO_UNDEF |
874 | 0 | 0U, // G_CTLZ |
875 | 0 | 0U, // G_CTLZ_ZERO_UNDEF |
876 | 0 | 0U, // G_CTPOP |
877 | 0 | 0U, // G_BSWAP |
878 | 0 | 0U, // G_FCEIL |
879 | 0 | 0U, // G_FCOS |
880 | 0 | 0U, // G_FSIN |
881 | 0 | 0U, // G_FSQRT |
882 | 0 | 0U, // G_FFLOOR |
883 | 0 | 0U, // G_ADDRSPACE_CAST |
884 | 0 | 0U, // G_BLOCK_ADDR |
885 | 0 | 0U, // ADJCALLSTACKDOWN |
886 | 0 | 0U, // ADJCALLSTACKUP |
887 | 0 | 0U, // BuildPairF64Pseudo |
888 | 0 | 0U, // PseudoAtomicLoadNand32 |
889 | 0 | 0U, // PseudoAtomicLoadNand64 |
890 | 0 | 0U, // PseudoBR |
891 | 0 | 0U, // PseudoBRIND |
892 | 0 | 0U, // PseudoCALL |
893 | 0 | 0U, // PseudoCALLIndirect |
894 | 0 | 0U, // PseudoCmpXchg32 |
895 | 0 | 0U, // PseudoCmpXchg64 |
896 | 0 | 0U, // PseudoLA |
897 | 0 | 0U, // PseudoLI |
898 | 0 | 0U, // PseudoLLA |
899 | 0 | 0U, // PseudoMaskedAtomicLoadAdd32 |
900 | 0 | 0U, // PseudoMaskedAtomicLoadMax32 |
901 | 0 | 0U, // PseudoMaskedAtomicLoadMin32 |
902 | 0 | 0U, // PseudoMaskedAtomicLoadNand32 |
903 | 0 | 0U, // PseudoMaskedAtomicLoadSub32 |
904 | 0 | 0U, // PseudoMaskedAtomicLoadUMax32 |
905 | 0 | 0U, // PseudoMaskedAtomicLoadUMin32 |
906 | 0 | 0U, // PseudoMaskedAtomicSwap32 |
907 | 0 | 0U, // PseudoMaskedCmpXchg32 |
908 | 0 | 0U, // PseudoRET |
909 | 0 | 0U, // PseudoTAIL |
910 | 0 | 0U, // PseudoTAILIndirect |
911 | 0 | 0U, // Select_FPR32_Using_CC_GPR |
912 | 0 | 0U, // Select_FPR64_Using_CC_GPR |
913 | 0 | 0U, // Select_GPR_Using_CC_GPR |
914 | 0 | 0U, // SplitF64Pseudo |
915 | 0 | 4U, // ADD |
916 | 0 | 4U, // ADDI |
917 | 0 | 4U, // ADDIW |
918 | 0 | 4U, // ADDW |
919 | 0 | 9U, // AMOADD_D |
920 | 0 | 9U, // AMOADD_D_AQ |
921 | 0 | 9U, // AMOADD_D_AQ_RL |
922 | 0 | 9U, // AMOADD_D_RL |
923 | 0 | 9U, // AMOADD_W |
924 | 0 | 9U, // AMOADD_W_AQ |
925 | 0 | 9U, // AMOADD_W_AQ_RL |
926 | 0 | 9U, // AMOADD_W_RL |
927 | 0 | 9U, // AMOAND_D |
928 | 0 | 9U, // AMOAND_D_AQ |
929 | 0 | 9U, // AMOAND_D_AQ_RL |
930 | 0 | 9U, // AMOAND_D_RL |
931 | 0 | 9U, // AMOAND_W |
932 | 0 | 9U, // AMOAND_W_AQ |
933 | 0 | 9U, // AMOAND_W_AQ_RL |
934 | 0 | 9U, // AMOAND_W_RL |
935 | 0 | 9U, // AMOMAXU_D |
936 | 0 | 9U, // AMOMAXU_D_AQ |
937 | 0 | 9U, // AMOMAXU_D_AQ_RL |
938 | 0 | 9U, // AMOMAXU_D_RL |
939 | 0 | 9U, // AMOMAXU_W |
940 | 0 | 9U, // AMOMAXU_W_AQ |
941 | 0 | 9U, // AMOMAXU_W_AQ_RL |
942 | 0 | 9U, // AMOMAXU_W_RL |
943 | 0 | 9U, // AMOMAX_D |
944 | 0 | 9U, // AMOMAX_D_AQ |
945 | 0 | 9U, // AMOMAX_D_AQ_RL |
946 | 0 | 9U, // AMOMAX_D_RL |
947 | 0 | 9U, // AMOMAX_W |
948 | 0 | 9U, // AMOMAX_W_AQ |
949 | 0 | 9U, // AMOMAX_W_AQ_RL |
950 | 0 | 9U, // AMOMAX_W_RL |
951 | 0 | 9U, // AMOMINU_D |
952 | 0 | 9U, // AMOMINU_D_AQ |
953 | 0 | 9U, // AMOMINU_D_AQ_RL |
954 | 0 | 9U, // AMOMINU_D_RL |
955 | 0 | 9U, // AMOMINU_W |
956 | 0 | 9U, // AMOMINU_W_AQ |
957 | 0 | 9U, // AMOMINU_W_AQ_RL |
958 | 0 | 9U, // AMOMINU_W_RL |
959 | 0 | 9U, // AMOMIN_D |
960 | 0 | 9U, // AMOMIN_D_AQ |
961 | 0 | 9U, // AMOMIN_D_AQ_RL |
962 | 0 | 9U, // AMOMIN_D_RL |
963 | 0 | 9U, // AMOMIN_W |
964 | 0 | 9U, // AMOMIN_W_AQ |
965 | 0 | 9U, // AMOMIN_W_AQ_RL |
966 | 0 | 9U, // AMOMIN_W_RL |
967 | 0 | 9U, // AMOOR_D |
968 | 0 | 9U, // AMOOR_D_AQ |
969 | 0 | 9U, // AMOOR_D_AQ_RL |
970 | 0 | 9U, // AMOOR_D_RL |
971 | 0 | 9U, // AMOOR_W |
972 | 0 | 9U, // AMOOR_W_AQ |
973 | 0 | 9U, // AMOOR_W_AQ_RL |
974 | 0 | 9U, // AMOOR_W_RL |
975 | 0 | 9U, // AMOSWAP_D |
976 | 0 | 9U, // AMOSWAP_D_AQ |
977 | 0 | 9U, // AMOSWAP_D_AQ_RL |
978 | 0 | 9U, // AMOSWAP_D_RL |
979 | 0 | 9U, // AMOSWAP_W |
980 | 0 | 9U, // AMOSWAP_W_AQ |
981 | 0 | 9U, // AMOSWAP_W_AQ_RL |
982 | 0 | 9U, // AMOSWAP_W_RL |
983 | 0 | 9U, // AMOXOR_D |
984 | 0 | 9U, // AMOXOR_D_AQ |
985 | 0 | 9U, // AMOXOR_D_AQ_RL |
986 | 0 | 9U, // AMOXOR_D_RL |
987 | 0 | 9U, // AMOXOR_W |
988 | 0 | 9U, // AMOXOR_W_AQ |
989 | 0 | 9U, // AMOXOR_W_AQ_RL |
990 | 0 | 9U, // AMOXOR_W_RL |
991 | 0 | 4U, // AND |
992 | 0 | 4U, // ANDI |
993 | 0 | 0U, // AUIPC |
994 | 0 | 4U, // BEQ |
995 | 0 | 4U, // BGE |
996 | 0 | 4U, // BGEU |
997 | 0 | 4U, // BLT |
998 | 0 | 4U, // BLTU |
999 | 0 | 4U, // BNE |
1000 | 0 | 2U, // CSRRC |
1001 | 0 | 2U, // CSRRCI |
1002 | 0 | 2U, // CSRRS |
1003 | 0 | 2U, // CSRRSI |
1004 | 0 | 2U, // CSRRW |
1005 | 0 | 2U, // CSRRWI |
1006 | 0 | 0U, // C_ADD |
1007 | 0 | 0U, // C_ADDI |
1008 | 0 | 0U, // C_ADDI16SP |
1009 | 0 | 4U, // C_ADDI4SPN |
1010 | 0 | 0U, // C_ADDIW |
1011 | 0 | 0U, // C_ADDW |
1012 | 0 | 0U, // C_AND |
1013 | 0 | 0U, // C_ANDI |
1014 | 0 | 0U, // C_BEQZ |
1015 | 0 | 0U, // C_BNEZ |
1016 | 0 | 0U, // C_EBREAK |
1017 | 0 | 13U, // C_FLD |
1018 | 0 | 13U, // C_FLDSP |
1019 | 0 | 13U, // C_FLW |
1020 | 0 | 13U, // C_FLWSP |
1021 | 0 | 13U, // C_FSD |
1022 | 0 | 13U, // C_FSDSP |
1023 | 0 | 13U, // C_FSW |
1024 | 0 | 13U, // C_FSWSP |
1025 | 0 | 0U, // C_J |
1026 | 0 | 0U, // C_JAL |
1027 | 0 | 0U, // C_JALR |
1028 | 0 | 0U, // C_JR |
1029 | 0 | 13U, // C_LD |
1030 | 0 | 13U, // C_LDSP |
1031 | 0 | 0U, // C_LI |
1032 | 0 | 0U, // C_LUI |
1033 | 0 | 13U, // C_LW |
1034 | 0 | 13U, // C_LWSP |
1035 | 0 | 0U, // C_MV |
1036 | 0 | 0U, // C_NOP |
1037 | 0 | 0U, // C_OR |
1038 | 0 | 13U, // C_SD |
1039 | 0 | 13U, // C_SDSP |
1040 | 0 | 0U, // C_SLLI |
1041 | 0 | 0U, // C_SRAI |
1042 | 0 | 0U, // C_SRLI |
1043 | 0 | 0U, // C_SUB |
1044 | 0 | 0U, // C_SUBW |
1045 | 0 | 13U, // C_SW |
1046 | 0 | 13U, // C_SWSP |
1047 | 0 | 0U, // C_UNIMP |
1048 | 0 | 0U, // C_XOR |
1049 | 0 | 4U, // DIV |
1050 | 0 | 4U, // DIVU |
1051 | 0 | 4U, // DIVUW |
1052 | 0 | 4U, // DIVW |
1053 | 0 | 0U, // EBREAK |
1054 | 0 | 0U, // ECALL |
1055 | 0 | 36U, // FADD_D |
1056 | 0 | 36U, // FADD_S |
1057 | 0 | 0U, // FCLASS_D |
1058 | 0 | 0U, // FCLASS_S |
1059 | 0 | 20U, // FCVT_D_L |
1060 | 0 | 20U, // FCVT_D_LU |
1061 | 0 | 0U, // FCVT_D_S |
1062 | 0 | 0U, // FCVT_D_W |
1063 | 0 | 0U, // FCVT_D_WU |
1064 | 0 | 20U, // FCVT_LU_D |
1065 | 0 | 20U, // FCVT_LU_S |
1066 | 0 | 20U, // FCVT_L_D |
1067 | 0 | 20U, // FCVT_L_S |
1068 | 0 | 20U, // FCVT_S_D |
1069 | 0 | 20U, // FCVT_S_L |
1070 | 0 | 20U, // FCVT_S_LU |
1071 | 0 | 20U, // FCVT_S_W |
1072 | 0 | 20U, // FCVT_S_WU |
1073 | 0 | 20U, // FCVT_WU_D |
1074 | 0 | 20U, // FCVT_WU_S |
1075 | 0 | 20U, // FCVT_W_D |
1076 | 0 | 20U, // FCVT_W_S |
1077 | 0 | 36U, // FDIV_D |
1078 | 0 | 36U, // FDIV_S |
1079 | 0 | 0U, // FENCE |
1080 | 0 | 0U, // FENCE_I |
1081 | 0 | 0U, // FENCE_TSO |
1082 | 0 | 4U, // FEQ_D |
1083 | 0 | 4U, // FEQ_S |
1084 | 0 | 13U, // FLD |
1085 | 0 | 4U, // FLE_D |
1086 | 0 | 4U, // FLE_S |
1087 | 0 | 4U, // FLT_D |
1088 | 0 | 4U, // FLT_S |
1089 | 0 | 13U, // FLW |
1090 | 0 | 100U, // FMADD_D |
1091 | 0 | 100U, // FMADD_S |
1092 | 0 | 4U, // FMAX_D |
1093 | 0 | 4U, // FMAX_S |
1094 | 0 | 4U, // FMIN_D |
1095 | 0 | 4U, // FMIN_S |
1096 | 0 | 100U, // FMSUB_D |
1097 | 0 | 100U, // FMSUB_S |
1098 | 0 | 36U, // FMUL_D |
1099 | 0 | 36U, // FMUL_S |
1100 | 0 | 0U, // FMV_D_X |
1101 | 0 | 0U, // FMV_W_X |
1102 | 0 | 0U, // FMV_X_D |
1103 | 0 | 0U, // FMV_X_W |
1104 | 0 | 100U, // FNMADD_D |
1105 | 0 | 100U, // FNMADD_S |
1106 | 0 | 100U, // FNMSUB_D |
1107 | 0 | 100U, // FNMSUB_S |
1108 | 0 | 13U, // FSD |
1109 | 0 | 4U, // FSGNJN_D |
1110 | 0 | 4U, // FSGNJN_S |
1111 | 0 | 4U, // FSGNJX_D |
1112 | 0 | 4U, // FSGNJX_S |
1113 | 0 | 4U, // FSGNJ_D |
1114 | 0 | 4U, // FSGNJ_S |
1115 | 0 | 20U, // FSQRT_D |
1116 | 0 | 20U, // FSQRT_S |
1117 | 0 | 36U, // FSUB_D |
1118 | 0 | 36U, // FSUB_S |
1119 | 0 | 13U, // FSW |
1120 | 0 | 0U, // JAL |
1121 | 0 | 4U, // JALR |
1122 | 0 | 13U, // LB |
1123 | 0 | 13U, // LBU |
1124 | 0 | 13U, // LD |
1125 | 0 | 13U, // LH |
1126 | 0 | 13U, // LHU |
1127 | 0 | 0U, // LR_D |
1128 | 0 | 0U, // LR_D_AQ |
1129 | 0 | 0U, // LR_D_AQ_RL |
1130 | 0 | 0U, // LR_D_RL |
1131 | 0 | 0U, // LR_W |
1132 | 0 | 0U, // LR_W_AQ |
1133 | 0 | 0U, // LR_W_AQ_RL |
1134 | 0 | 0U, // LR_W_RL |
1135 | 0 | 0U, // LUI |
1136 | 0 | 13U, // LW |
1137 | 0 | 13U, // LWU |
1138 | 0 | 0U, // MRET |
1139 | 0 | 4U, // MUL |
1140 | 0 | 4U, // MULH |
1141 | 0 | 4U, // MULHSU |
1142 | 0 | 4U, // MULHU |
1143 | 0 | 4U, // MULW |
1144 | 0 | 4U, // OR |
1145 | 0 | 4U, // ORI |
1146 | 0 | 4U, // REM |
1147 | 0 | 4U, // REMU |
1148 | 0 | 4U, // REMUW |
1149 | 0 | 4U, // REMW |
1150 | 0 | 13U, // SB |
1151 | 0 | 9U, // SC_D |
1152 | 0 | 9U, // SC_D_AQ |
1153 | 0 | 9U, // SC_D_AQ_RL |
1154 | 0 | 9U, // SC_D_RL |
1155 | 0 | 9U, // SC_W |
1156 | 0 | 9U, // SC_W_AQ |
1157 | 0 | 9U, // SC_W_AQ_RL |
1158 | 0 | 9U, // SC_W_RL |
1159 | 0 | 13U, // SD |
1160 | 0 | 0U, // SFENCE_VMA |
1161 | 0 | 13U, // SH |
1162 | 0 | 4U, // SLL |
1163 | 0 | 4U, // SLLI |
1164 | 0 | 4U, // SLLIW |
1165 | 0 | 4U, // SLLW |
1166 | 0 | 4U, // SLT |
1167 | 0 | 4U, // SLTI |
1168 | 0 | 4U, // SLTIU |
1169 | 0 | 4U, // SLTU |
1170 | 0 | 4U, // SRA |
1171 | 0 | 4U, // SRAI |
1172 | 0 | 4U, // SRAIW |
1173 | 0 | 4U, // SRAW |
1174 | 0 | 0U, // SRET |
1175 | 0 | 4U, // SRL |
1176 | 0 | 4U, // SRLI |
1177 | 0 | 4U, // SRLIW |
1178 | 0 | 4U, // SRLW |
1179 | 0 | 4U, // SUB |
1180 | 0 | 4U, // SUBW |
1181 | 0 | 13U, // SW |
1182 | 0 | 0U, // UNIMP |
1183 | 0 | 0U, // URET |
1184 | 0 | 0U, // WFI |
1185 | 0 | 4U, // XOR |
1186 | 0 | 4U, // XORI |
1187 | 0 | }; |
1188 | | |
1189 | | // Emit the opcode for the instruction. |
1190 | 0 | uint32_t Bits = 0; |
1191 | 0 | Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0; |
1192 | 0 | Bits |= OpInfo1[MCInst_getOpcode(MI)] << 16; |
1193 | 0 | CS_ASSERT(Bits != 0 && "Cannot print this instruction."); |
1194 | 0 | #ifndef CAPSTONE_DIET |
1195 | 0 | SStream_concat0(O, AsmStrs+(Bits & 4095)-1); |
1196 | 0 | #endif |
1197 | | |
1198 | | |
1199 | | // Fragment 0 encoded into 2 bits for 4 unique commands. |
1200 | 0 | switch ((Bits >> 12) & 3) { |
1201 | 0 | default: CS_ASSERT(0 && "Invalid command number."); |
1202 | 0 | case 0: |
1203 | | // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... |
1204 | 0 | return; |
1205 | 0 | break; |
1206 | 0 | case 1: |
1207 | | // PseudoCALL, PseudoLA, PseudoLI, PseudoLLA, PseudoTAIL, ADD, ADDI, ADDI... |
1208 | 0 | printOperand(MI, 0, O); |
1209 | 0 | break; |
1210 | 0 | case 2: |
1211 | | // C_ADD, C_ADDI, C_ADDI16SP, C_ADDIW, C_ADDW, C_AND, C_ANDI, C_OR, C_SLL... |
1212 | 0 | printOperand(MI, 1, O); |
1213 | 0 | SStream_concat0(O, ", "); |
1214 | 0 | printOperand(MI, 2, O); |
1215 | 0 | return; |
1216 | 0 | break; |
1217 | 0 | case 3: |
1218 | | // FENCE |
1219 | 0 | printFenceArg(MI, 0, O); |
1220 | 0 | SStream_concat0(O, ", "); |
1221 | 0 | printFenceArg(MI, 1, O); |
1222 | 0 | return; |
1223 | 0 | break; |
1224 | 0 | } |
1225 | | |
1226 | | |
1227 | | // Fragment 1 encoded into 2 bits for 3 unique commands. |
1228 | 0 | switch ((Bits >> 14) & 3) { |
1229 | 0 | default: CS_ASSERT(0 && "Invalid command number."); |
1230 | 0 | case 0: |
1231 | | // PseudoCALL, PseudoTAIL, C_J, C_JAL, C_JALR, C_JR |
1232 | 0 | return; |
1233 | 0 | break; |
1234 | 0 | case 1: |
1235 | | // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AMOADD_D, AMOAD... |
1236 | 0 | SStream_concat0(O, ", "); |
1237 | 0 | break; |
1238 | 0 | case 2: |
1239 | | // LR_D, LR_D_AQ, LR_D_AQ_RL, LR_D_RL, LR_W, LR_W_AQ, LR_W_AQ_RL, LR_W_RL |
1240 | 0 | SStream_concat0(O, ", ("); |
1241 | 0 | printOperand(MI, 1, O); |
1242 | 0 | SStream_concat0(O, ")"); |
1243 | 0 | return; |
1244 | 0 | break; |
1245 | 0 | } |
1246 | | |
1247 | | |
1248 | | // Fragment 2 encoded into 2 bits for 3 unique commands. |
1249 | 0 | switch ((Bits >> 16) & 3) { |
1250 | 0 | default: CS_ASSERT(0 && "Invalid command number."); |
1251 | 0 | case 0: |
1252 | | // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AND, ANDI, AUIP... |
1253 | 0 | printOperand(MI, 1, O); |
1254 | 0 | break; |
1255 | 0 | case 1: |
1256 | | // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W... |
1257 | 0 | printOperand(MI, 2, O); |
1258 | 0 | break; |
1259 | 0 | case 2: |
1260 | | // CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI |
1261 | 0 | printCSRSystemRegister(MI, 1, O); |
1262 | 0 | SStream_concat0(O, ", "); |
1263 | 0 | printOperand(MI, 2, O); |
1264 | 0 | return; |
1265 | 0 | break; |
1266 | 0 | } |
1267 | | |
1268 | | |
1269 | | // Fragment 3 encoded into 2 bits for 4 unique commands. |
1270 | 0 | switch ((Bits >> 18) & 3) { |
1271 | 0 | default: CS_ASSERT(0 && "Invalid command number."); |
1272 | 0 | case 0: |
1273 | | // PseudoLA, PseudoLI, PseudoLLA, AUIPC, C_BEQZ, C_BNEZ, C_LI, C_LUI, C_M... |
1274 | 0 | return; |
1275 | 0 | break; |
1276 | 0 | case 1: |
1277 | | // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... |
1278 | 0 | SStream_concat0(O, ", "); |
1279 | 0 | break; |
1280 | 0 | case 2: |
1281 | | // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W... |
1282 | 0 | SStream_concat0(O, ", ("); |
1283 | 0 | printOperand(MI, 1, O); |
1284 | 0 | SStream_concat0(O, ")"); |
1285 | 0 | return; |
1286 | 0 | break; |
1287 | 0 | case 3: |
1288 | | // C_FLD, C_FLDSP, C_FLW, C_FLWSP, C_FSD, C_FSDSP, C_FSW, C_FSWSP, C_LD, ... |
1289 | 0 | SStream_concat0(O, "("); |
1290 | 0 | printOperand(MI, 1, O); |
1291 | 0 | SStream_concat0(O, ")"); |
1292 | 0 | return; |
1293 | 0 | break; |
1294 | 0 | } |
1295 | | |
1296 | | |
1297 | | // Fragment 4 encoded into 1 bits for 2 unique commands. |
1298 | 0 | if ((Bits >> 20) & 1) { |
1299 | | // FCVT_D_L, FCVT_D_LU, FCVT_LU_D, FCVT_LU_S, FCVT_L_D, FCVT_L_S, FCVT_S_... |
1300 | 0 | printFRMArg(MI, 2, O); |
1301 | 0 | return; |
1302 | 0 | } else { |
1303 | | // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... |
1304 | 0 | printOperand(MI, 2, O); |
1305 | 0 | } |
1306 | | |
1307 | | |
1308 | | // Fragment 5 encoded into 1 bits for 2 unique commands. |
1309 | 0 | if ((Bits >> 21) & 1) { |
1310 | | // FADD_D, FADD_S, FDIV_D, FDIV_S, FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FM... |
1311 | 0 | SStream_concat0(O, ", "); |
1312 | 0 | } else { |
1313 | | // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... |
1314 | 0 | return; |
1315 | 0 | } |
1316 | | |
1317 | | |
1318 | | // Fragment 6 encoded into 1 bits for 2 unique commands. |
1319 | 0 | if ((Bits >> 22) & 1) { |
1320 | | // FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FNMADD_D, FNMADD_S, FNMSUB_D, FNMS... |
1321 | 0 | printOperand(MI, 3, O); |
1322 | 0 | SStream_concat0(O, ", "); |
1323 | 0 | printFRMArg(MI, 4, O); |
1324 | 0 | return; |
1325 | 0 | } else { |
1326 | | // FADD_D, FADD_S, FDIV_D, FDIV_S, FMUL_D, FMUL_S, FSUB_D, FSUB_S |
1327 | 0 | printFRMArg(MI, 3, O); |
1328 | 0 | return; |
1329 | 0 | } |
1330 | |
|
1331 | 0 | } |
1332 | | |
1333 | | |
1334 | | /// getRegisterName - This method is automatically generated by tblgen |
1335 | | /// from the register set description. This returns the assembler name |
1336 | | /// for the specified register. |
1337 | | static const char * |
1338 | | getRegisterName(unsigned RegNo, unsigned AltIdx) |
1339 | 0 | { |
1340 | 0 | CS_ASSERT(RegNo && RegNo < 97 && "Invalid register number!"); |
1341 | |
|
1342 | 0 | #ifndef CAPSTONE_DIET |
1343 | 0 | static const char AsmStrsABIRegAltName[] = { |
1344 | 0 | /* 0 */ 'f', 's', '1', '0', 0, |
1345 | 0 | /* 5 */ 'f', 't', '1', '0', 0, |
1346 | 0 | /* 10 */ 'f', 'a', '0', 0, |
1347 | 0 | /* 14 */ 'f', 's', '0', 0, |
1348 | 0 | /* 18 */ 'f', 't', '0', 0, |
1349 | 0 | /* 22 */ 'f', 's', '1', '1', 0, |
1350 | 0 | /* 27 */ 'f', 't', '1', '1', 0, |
1351 | 0 | /* 32 */ 'f', 'a', '1', 0, |
1352 | 0 | /* 36 */ 'f', 's', '1', 0, |
1353 | 0 | /* 40 */ 'f', 't', '1', 0, |
1354 | 0 | /* 44 */ 'f', 'a', '2', 0, |
1355 | 0 | /* 48 */ 'f', 's', '2', 0, |
1356 | 0 | /* 52 */ 'f', 't', '2', 0, |
1357 | 0 | /* 56 */ 'f', 'a', '3', 0, |
1358 | 0 | /* 60 */ 'f', 's', '3', 0, |
1359 | 0 | /* 64 */ 'f', 't', '3', 0, |
1360 | 0 | /* 68 */ 'f', 'a', '4', 0, |
1361 | 0 | /* 72 */ 'f', 's', '4', 0, |
1362 | 0 | /* 76 */ 'f', 't', '4', 0, |
1363 | 0 | /* 80 */ 'f', 'a', '5', 0, |
1364 | 0 | /* 84 */ 'f', 's', '5', 0, |
1365 | 0 | /* 88 */ 'f', 't', '5', 0, |
1366 | 0 | /* 92 */ 'f', 'a', '6', 0, |
1367 | 0 | /* 96 */ 'f', 's', '6', 0, |
1368 | 0 | /* 100 */ 'f', 't', '6', 0, |
1369 | 0 | /* 104 */ 'f', 'a', '7', 0, |
1370 | 0 | /* 108 */ 'f', 's', '7', 0, |
1371 | 0 | /* 112 */ 'f', 't', '7', 0, |
1372 | 0 | /* 116 */ 'f', 's', '8', 0, |
1373 | 0 | /* 120 */ 'f', 't', '8', 0, |
1374 | 0 | /* 124 */ 'f', 's', '9', 0, |
1375 | 0 | /* 128 */ 'f', 't', '9', 0, |
1376 | 0 | /* 132 */ 'r', 'a', 0, |
1377 | 0 | /* 135 */ 'z', 'e', 'r', 'o', 0, |
1378 | 0 | /* 140 */ 'g', 'p', 0, |
1379 | 0 | /* 143 */ 's', 'p', 0, |
1380 | 0 | /* 146 */ 't', 'p', 0, |
1381 | 0 | }; |
1382 | |
|
1383 | 0 | static const uint8_t RegAsmOffsetABIRegAltName[] = { |
1384 | 0 | 135, 132, 143, 140, 146, 19, 41, 53, 15, 37, 11, 33, 45, 57, |
1385 | 0 | 69, 81, 93, 105, 49, 61, 73, 85, 97, 109, 117, 125, 1, 23, |
1386 | 0 | 65, 77, 89, 101, 18, 18, 40, 40, 52, 52, 64, 64, 76, 76, |
1387 | 0 | 88, 88, 100, 100, 112, 112, 14, 14, 36, 36, 10, 10, 32, 32, |
1388 | 0 | 44, 44, 56, 56, 68, 68, 80, 80, 92, 92, 104, 104, 48, 48, |
1389 | 0 | 60, 60, 72, 72, 84, 84, 96, 96, 108, 108, 116, 116, 124, 124, |
1390 | 0 | 0, 0, 22, 22, 120, 120, 128, 128, 5, 5, 27, 27, |
1391 | 0 | }; |
1392 | |
|
1393 | 0 | static const char AsmStrsNoRegAltName[] = { |
1394 | 0 | /* 0 */ 'f', '1', '0', 0, |
1395 | 0 | /* 4 */ 'x', '1', '0', 0, |
1396 | 0 | /* 8 */ 'f', '2', '0', 0, |
1397 | 0 | /* 12 */ 'x', '2', '0', 0, |
1398 | 0 | /* 16 */ 'f', '3', '0', 0, |
1399 | 0 | /* 20 */ 'x', '3', '0', 0, |
1400 | 0 | /* 24 */ 'f', '0', 0, |
1401 | 0 | /* 27 */ 'x', '0', 0, |
1402 | 0 | /* 30 */ 'f', '1', '1', 0, |
1403 | 0 | /* 34 */ 'x', '1', '1', 0, |
1404 | 0 | /* 38 */ 'f', '2', '1', 0, |
1405 | 0 | /* 42 */ 'x', '2', '1', 0, |
1406 | 0 | /* 46 */ 'f', '3', '1', 0, |
1407 | 0 | /* 50 */ 'x', '3', '1', 0, |
1408 | 0 | /* 54 */ 'f', '1', 0, |
1409 | 0 | /* 57 */ 'x', '1', 0, |
1410 | 0 | /* 60 */ 'f', '1', '2', 0, |
1411 | 0 | /* 64 */ 'x', '1', '2', 0, |
1412 | 0 | /* 68 */ 'f', '2', '2', 0, |
1413 | 0 | /* 72 */ 'x', '2', '2', 0, |
1414 | 0 | /* 76 */ 'f', '2', 0, |
1415 | 0 | /* 79 */ 'x', '2', 0, |
1416 | 0 | /* 82 */ 'f', '1', '3', 0, |
1417 | 0 | /* 86 */ 'x', '1', '3', 0, |
1418 | 0 | /* 90 */ 'f', '2', '3', 0, |
1419 | 0 | /* 94 */ 'x', '2', '3', 0, |
1420 | 0 | /* 98 */ 'f', '3', 0, |
1421 | 0 | /* 101 */ 'x', '3', 0, |
1422 | 0 | /* 104 */ 'f', '1', '4', 0, |
1423 | 0 | /* 108 */ 'x', '1', '4', 0, |
1424 | 0 | /* 112 */ 'f', '2', '4', 0, |
1425 | 0 | /* 116 */ 'x', '2', '4', 0, |
1426 | 0 | /* 120 */ 'f', '4', 0, |
1427 | 0 | /* 123 */ 'x', '4', 0, |
1428 | 0 | /* 126 */ 'f', '1', '5', 0, |
1429 | 0 | /* 130 */ 'x', '1', '5', 0, |
1430 | 0 | /* 134 */ 'f', '2', '5', 0, |
1431 | 0 | /* 138 */ 'x', '2', '5', 0, |
1432 | 0 | /* 142 */ 'f', '5', 0, |
1433 | 0 | /* 145 */ 'x', '5', 0, |
1434 | 0 | /* 148 */ 'f', '1', '6', 0, |
1435 | 0 | /* 152 */ 'x', '1', '6', 0, |
1436 | 0 | /* 156 */ 'f', '2', '6', 0, |
1437 | 0 | /* 160 */ 'x', '2', '6', 0, |
1438 | 0 | /* 164 */ 'f', '6', 0, |
1439 | 0 | /* 167 */ 'x', '6', 0, |
1440 | 0 | /* 170 */ 'f', '1', '7', 0, |
1441 | 0 | /* 174 */ 'x', '1', '7', 0, |
1442 | 0 | /* 178 */ 'f', '2', '7', 0, |
1443 | 0 | /* 182 */ 'x', '2', '7', 0, |
1444 | 0 | /* 186 */ 'f', '7', 0, |
1445 | 0 | /* 189 */ 'x', '7', 0, |
1446 | 0 | /* 192 */ 'f', '1', '8', 0, |
1447 | 0 | /* 196 */ 'x', '1', '8', 0, |
1448 | 0 | /* 200 */ 'f', '2', '8', 0, |
1449 | 0 | /* 204 */ 'x', '2', '8', 0, |
1450 | 0 | /* 208 */ 'f', '8', 0, |
1451 | 0 | /* 211 */ 'x', '8', 0, |
1452 | 0 | /* 214 */ 'f', '1', '9', 0, |
1453 | 0 | /* 218 */ 'x', '1', '9', 0, |
1454 | 0 | /* 222 */ 'f', '2', '9', 0, |
1455 | 0 | /* 226 */ 'x', '2', '9', 0, |
1456 | 0 | /* 230 */ 'f', '9', 0, |
1457 | 0 | /* 233 */ 'x', '9', 0, |
1458 | 0 | }; |
1459 | |
|
1460 | 0 | static const uint8_t RegAsmOffsetNoRegAltName[] = { |
1461 | 0 | 27, 57, 79, 101, 123, 145, 167, 189, 211, 233, 4, 34, 64, 86, |
1462 | 0 | 108, 130, 152, 174, 196, 218, 12, 42, 72, 94, 116, 138, 160, 182, |
1463 | 0 | 204, 226, 20, 50, 24, 24, 54, 54, 76, 76, 98, 98, 120, 120, |
1464 | 0 | 142, 142, 164, 164, 186, 186, 208, 208, 230, 230, 0, 0, 30, 30, |
1465 | 0 | 60, 60, 82, 82, 104, 104, 126, 126, 148, 148, 170, 170, 192, 192, |
1466 | 0 | 214, 214, 8, 8, 38, 38, 68, 68, 90, 90, 112, 112, 134, 134, |
1467 | 0 | 156, 156, 178, 178, 200, 200, 222, 222, 16, 16, 46, 46, |
1468 | 0 | }; |
1469 | |
|
1470 | 0 | switch(AltIdx) { |
1471 | 0 | default: CS_ASSERT(0 && "Invalid register alt name index!"); |
1472 | 0 | case RISCV_ABIRegAltName: |
1473 | 0 | CS_ASSERT(*(AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]) && |
1474 | 0 | "Invalid alt name index for register!"); |
1475 | 0 | return AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]; |
1476 | 0 | case RISCV_NoRegAltName: |
1477 | 0 | CS_ASSERT(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && |
1478 | 0 | "Invalid alt name index for register!"); |
1479 | 0 | return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; |
1480 | 0 | } |
1481 | | #else |
1482 | | return NULL; |
1483 | | #endif |
1484 | 0 | } |
1485 | | |
1486 | | #ifdef PRINT_ALIAS_INSTR |
1487 | | #undef PRINT_ALIAS_INSTR |
1488 | | |
1489 | | static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp, |
1490 | | unsigned PredicateIndex); |
1491 | | |
1492 | | static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) |
1493 | 0 | { |
1494 | 0 | MCRegisterInfo *MRI = (MCRegisterInfo *) info; |
1495 | 0 | const char *AsmString; |
1496 | 0 | unsigned I = 0; |
1497 | 0 | #define ASMSTRING_CONTAIN_SIZE 64 |
1498 | 0 | unsigned AsmStringLen = 0; |
1499 | 0 | char tmpString_[ASMSTRING_CONTAIN_SIZE]; |
1500 | 0 | char *tmpString = tmpString_; |
1501 | 0 | switch (MCInst_getOpcode(MI)) { |
1502 | 0 | default: return false; |
1503 | 0 | case RISCV_ADDI: |
1504 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1505 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && |
1506 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && |
1507 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
1508 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
1509 | | // (ADDI X0, X0, 0) |
1510 | 0 | AsmString = "nop"; |
1511 | 0 | break; |
1512 | 0 | } |
1513 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1514 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1515 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1516 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
1517 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
1518 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
1519 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
1520 | | // (ADDI GPR:$rd, GPR:$rs, 0) |
1521 | 0 | AsmString = "mv $\x01, $\x02"; |
1522 | 0 | break; |
1523 | 0 | } |
1524 | 0 | return false; |
1525 | 0 | case RISCV_ADDIW: |
1526 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1527 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1528 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1529 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
1530 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
1531 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
1532 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
1533 | | // (ADDIW GPR:$rd, GPR:$rs, 0) |
1534 | 0 | AsmString = "sext.w $\x01, $\x02"; |
1535 | 0 | break; |
1536 | 0 | } |
1537 | 0 | return false; |
1538 | 0 | case RISCV_BEQ: |
1539 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1540 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1541 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1542 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && |
1543 | 0 | RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { |
1544 | | // (BEQ GPR:$rs, X0, simm13_lsb0:$offset) |
1545 | 0 | AsmString = "beqz $\x01, $\x03"; |
1546 | 0 | break; |
1547 | 0 | } |
1548 | 0 | return false; |
1549 | 0 | case RISCV_BGE: |
1550 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1551 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && |
1552 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
1553 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
1554 | 0 | RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { |
1555 | | // (BGE X0, GPR:$rs, simm13_lsb0:$offset) |
1556 | 0 | AsmString = "blez $\x02, $\x03"; |
1557 | 0 | break; |
1558 | 0 | } |
1559 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1560 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1561 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1562 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && |
1563 | 0 | RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { |
1564 | | // (BGE GPR:$rs, X0, simm13_lsb0:$offset) |
1565 | 0 | AsmString = "bgez $\x01, $\x03"; |
1566 | 0 | break; |
1567 | 0 | } |
1568 | 0 | return false; |
1569 | 0 | case RISCV_BLT: |
1570 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1571 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1572 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1573 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && |
1574 | 0 | RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { |
1575 | | // (BLT GPR:$rs, X0, simm13_lsb0:$offset) |
1576 | 0 | AsmString = "bltz $\x01, $\x03"; |
1577 | 0 | break; |
1578 | 0 | } |
1579 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1580 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && |
1581 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
1582 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
1583 | 0 | RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { |
1584 | | // (BLT X0, GPR:$rs, simm13_lsb0:$offset) |
1585 | 0 | AsmString = "bgtz $\x02, $\x03"; |
1586 | 0 | break; |
1587 | 0 | } |
1588 | 0 | return false; |
1589 | 0 | case RISCV_BNE: |
1590 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1591 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1592 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1593 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && |
1594 | 0 | RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { |
1595 | | // (BNE GPR:$rs, X0, simm13_lsb0:$offset) |
1596 | 0 | AsmString = "bnez $\x01, $\x03"; |
1597 | 0 | break; |
1598 | 0 | } |
1599 | 0 | return false; |
1600 | 0 | case RISCV_CSRRC: |
1601 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1602 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && |
1603 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
1604 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { |
1605 | | // (CSRRC X0, csr_sysreg:$csr, GPR:$rs) |
1606 | 0 | AsmString = "csrc $\xFF\x02\x01, $\x03"; |
1607 | 0 | break; |
1608 | 0 | } |
1609 | 0 | return false; |
1610 | 0 | case RISCV_CSRRCI: |
1611 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1612 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) { |
1613 | | // (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm) |
1614 | 0 | AsmString = "csrci $\xFF\x02\x01, $\x03"; |
1615 | 0 | break; |
1616 | 0 | } |
1617 | 0 | return false; |
1618 | 0 | case RISCV_CSRRS: |
1619 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1620 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1621 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1622 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1623 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && |
1624 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { |
1625 | | // (CSRRS GPR:$rd, 3, X0) |
1626 | 0 | AsmString = "frcsr $\x01"; |
1627 | 0 | break; |
1628 | 0 | } |
1629 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1630 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1631 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1632 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1633 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && |
1634 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { |
1635 | | // (CSRRS GPR:$rd, 2, X0) |
1636 | 0 | AsmString = "frrm $\x01"; |
1637 | 0 | break; |
1638 | 0 | } |
1639 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1640 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1641 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1642 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1643 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && |
1644 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { |
1645 | | // (CSRRS GPR:$rd, 1, X0) |
1646 | 0 | AsmString = "frflags $\x01"; |
1647 | 0 | break; |
1648 | 0 | } |
1649 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1650 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1651 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1652 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1653 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3074 && |
1654 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { |
1655 | | // (CSRRS GPR:$rd, 3074, X0) |
1656 | 0 | AsmString = "rdinstret $\x01"; |
1657 | 0 | break; |
1658 | 0 | } |
1659 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1660 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1661 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1662 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1663 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3072 && |
1664 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { |
1665 | | // (CSRRS GPR:$rd, 3072, X0) |
1666 | 0 | AsmString = "rdcycle $\x01"; |
1667 | 0 | break; |
1668 | 0 | } |
1669 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1670 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1671 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1672 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1673 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3073 && |
1674 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { |
1675 | | // (CSRRS GPR:$rd, 3073, X0) |
1676 | 0 | AsmString = "rdtime $\x01"; |
1677 | 0 | break; |
1678 | 0 | } |
1679 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1680 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1681 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1682 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1683 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3202 && |
1684 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { |
1685 | | // (CSRRS GPR:$rd, 3202, X0) |
1686 | 0 | AsmString = "rdinstreth $\x01"; |
1687 | 0 | break; |
1688 | 0 | } |
1689 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1690 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1691 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1692 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1693 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3200 && |
1694 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { |
1695 | | // (CSRRS GPR:$rd, 3200, X0) |
1696 | 0 | AsmString = "rdcycleh $\x01"; |
1697 | 0 | break; |
1698 | 0 | } |
1699 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1700 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1701 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1702 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1703 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3201 && |
1704 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { |
1705 | | // (CSRRS GPR:$rd, 3201, X0) |
1706 | 0 | AsmString = "rdtimeh $\x01"; |
1707 | 0 | break; |
1708 | 0 | } |
1709 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1710 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1711 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1712 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { |
1713 | | // (CSRRS GPR:$rd, csr_sysreg:$csr, X0) |
1714 | 0 | AsmString = "csrr $\x01, $\xFF\x02\x01"; |
1715 | 0 | break; |
1716 | 0 | } |
1717 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1718 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && |
1719 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
1720 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { |
1721 | | // (CSRRS X0, csr_sysreg:$csr, GPR:$rs) |
1722 | 0 | AsmString = "csrs $\xFF\x02\x01, $\x03"; |
1723 | 0 | break; |
1724 | 0 | } |
1725 | 0 | return false; |
1726 | 0 | case RISCV_CSRRSI: |
1727 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1728 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) { |
1729 | | // (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm) |
1730 | 0 | AsmString = "csrsi $\xFF\x02\x01, $\x03"; |
1731 | 0 | break; |
1732 | 0 | } |
1733 | 0 | return false; |
1734 | 0 | case RISCV_CSRRW: |
1735 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1736 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && |
1737 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1738 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && |
1739 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
1740 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { |
1741 | | // (CSRRW X0, 3, GPR:$rs) |
1742 | 0 | AsmString = "fscsr $\x03"; |
1743 | 0 | break; |
1744 | 0 | } |
1745 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1746 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && |
1747 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1748 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && |
1749 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
1750 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { |
1751 | | // (CSRRW X0, 2, GPR:$rs) |
1752 | 0 | AsmString = "fsrm $\x03"; |
1753 | 0 | break; |
1754 | 0 | } |
1755 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1756 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && |
1757 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1758 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && |
1759 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
1760 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { |
1761 | | // (CSRRW X0, 1, GPR:$rs) |
1762 | 0 | AsmString = "fsflags $\x03"; |
1763 | 0 | break; |
1764 | 0 | } |
1765 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1766 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && |
1767 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
1768 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { |
1769 | | // (CSRRW X0, csr_sysreg:$csr, GPR:$rs) |
1770 | 0 | AsmString = "csrw $\xFF\x02\x01, $\x03"; |
1771 | 0 | break; |
1772 | 0 | } |
1773 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1774 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1775 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1776 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1777 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && |
1778 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
1779 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { |
1780 | | // (CSRRW GPR:$rd, 3, GPR:$rs) |
1781 | 0 | AsmString = "fscsr $\x01, $\x03"; |
1782 | 0 | break; |
1783 | 0 | } |
1784 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1785 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1786 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1787 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1788 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && |
1789 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
1790 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { |
1791 | | // (CSRRW GPR:$rd, 2, GPR:$rs) |
1792 | 0 | AsmString = "fsrm $\x01, $\x03"; |
1793 | 0 | break; |
1794 | 0 | } |
1795 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1796 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1797 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1798 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1799 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && |
1800 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
1801 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { |
1802 | | // (CSRRW GPR:$rd, 1, GPR:$rs) |
1803 | 0 | AsmString = "fsflags $\x01, $\x03"; |
1804 | 0 | break; |
1805 | 0 | } |
1806 | 0 | return false; |
1807 | 0 | case RISCV_CSRRWI: |
1808 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1809 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && |
1810 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1811 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { |
1812 | | // (CSRRWI X0, 2, uimm5:$imm) |
1813 | 0 | AsmString = "fsrmi $\x03"; |
1814 | 0 | break; |
1815 | 0 | } |
1816 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1817 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && |
1818 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1819 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { |
1820 | | // (CSRRWI X0, 1, uimm5:$imm) |
1821 | 0 | AsmString = "fsflagsi $\x03"; |
1822 | 0 | break; |
1823 | 0 | } |
1824 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1825 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) { |
1826 | | // (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm) |
1827 | 0 | AsmString = "csrwi $\xFF\x02\x01, $\x03"; |
1828 | 0 | break; |
1829 | 0 | } |
1830 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1831 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1832 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1833 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1834 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { |
1835 | | // (CSRRWI GPR:$rd, 2, uimm5:$imm) |
1836 | 0 | AsmString = "fsrmi $\x01, $\x03"; |
1837 | 0 | break; |
1838 | 0 | } |
1839 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1840 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1841 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1842 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
1843 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { |
1844 | | // (CSRRWI GPR:$rd, 1, uimm5:$imm) |
1845 | 0 | AsmString = "fsflagsi $\x01, $\x03"; |
1846 | 0 | break; |
1847 | 0 | } |
1848 | 0 | return false; |
1849 | 0 | case RISCV_FADD_D: |
1850 | 0 | if (MCInst_getNumOperands(MI) == 4 && |
1851 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1852 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1853 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
1854 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
1855 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
1856 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
1857 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
1858 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { |
1859 | | // (FADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) |
1860 | 0 | AsmString = "fadd.d $\x01, $\x02, $\x03"; |
1861 | 0 | break; |
1862 | 0 | } |
1863 | 0 | return false; |
1864 | 0 | case RISCV_FADD_S: |
1865 | 0 | if (MCInst_getNumOperands(MI) == 4 && |
1866 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1867 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1868 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
1869 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
1870 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
1871 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
1872 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
1873 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { |
1874 | | // (FADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) |
1875 | 0 | AsmString = "fadd.s $\x01, $\x02, $\x03"; |
1876 | 0 | break; |
1877 | 0 | } |
1878 | 0 | return false; |
1879 | 0 | case RISCV_FCVT_D_L: |
1880 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1881 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1882 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1883 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
1884 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
1885 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
1886 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
1887 | | // (FCVT_D_L FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) |
1888 | 0 | AsmString = "fcvt.d.l $\x01, $\x02"; |
1889 | 0 | break; |
1890 | 0 | } |
1891 | 0 | return false; |
1892 | 0 | case RISCV_FCVT_D_LU: |
1893 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1894 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1895 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1896 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
1897 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
1898 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
1899 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
1900 | | // (FCVT_D_LU FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) |
1901 | 0 | AsmString = "fcvt.d.lu $\x01, $\x02"; |
1902 | 0 | break; |
1903 | 0 | } |
1904 | 0 | return false; |
1905 | 0 | case RISCV_FCVT_LU_D: |
1906 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1907 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1908 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1909 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
1910 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
1911 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
1912 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
1913 | | // (FCVT_LU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) |
1914 | 0 | AsmString = "fcvt.lu.d $\x01, $\x02"; |
1915 | 0 | break; |
1916 | 0 | } |
1917 | 0 | return false; |
1918 | 0 | case RISCV_FCVT_LU_S: |
1919 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1920 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1921 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1922 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
1923 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
1924 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
1925 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
1926 | | // (FCVT_LU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) |
1927 | 0 | AsmString = "fcvt.lu.s $\x01, $\x02"; |
1928 | 0 | break; |
1929 | 0 | } |
1930 | 0 | return false; |
1931 | 0 | case RISCV_FCVT_L_D: |
1932 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1933 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1934 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1935 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
1936 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
1937 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
1938 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
1939 | | // (FCVT_L_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) |
1940 | 0 | AsmString = "fcvt.l.d $\x01, $\x02"; |
1941 | 0 | break; |
1942 | 0 | } |
1943 | 0 | return false; |
1944 | 0 | case RISCV_FCVT_L_S: |
1945 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1946 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1947 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1948 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
1949 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
1950 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
1951 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
1952 | | // (FCVT_L_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) |
1953 | 0 | AsmString = "fcvt.l.s $\x01, $\x02"; |
1954 | 0 | break; |
1955 | 0 | } |
1956 | 0 | return false; |
1957 | 0 | case RISCV_FCVT_S_D: |
1958 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1959 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1960 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1961 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
1962 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
1963 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
1964 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
1965 | | // (FCVT_S_D FPR32:$rd, FPR64:$rs1, { 1, 1, 1 }) |
1966 | 0 | AsmString = "fcvt.s.d $\x01, $\x02"; |
1967 | 0 | break; |
1968 | 0 | } |
1969 | 0 | return false; |
1970 | 0 | case RISCV_FCVT_S_L: |
1971 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1972 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1973 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1974 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
1975 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
1976 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
1977 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
1978 | | // (FCVT_S_L FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) |
1979 | 0 | AsmString = "fcvt.s.l $\x01, $\x02"; |
1980 | 0 | break; |
1981 | 0 | } |
1982 | 0 | return false; |
1983 | 0 | case RISCV_FCVT_S_LU: |
1984 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1985 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1986 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
1987 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
1988 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
1989 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
1990 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
1991 | | // (FCVT_S_LU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) |
1992 | 0 | AsmString = "fcvt.s.lu $\x01, $\x02"; |
1993 | 0 | break; |
1994 | 0 | } |
1995 | 0 | return false; |
1996 | 0 | case RISCV_FCVT_S_W: |
1997 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
1998 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
1999 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2000 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2001 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2002 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
2003 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
2004 | | // (FCVT_S_W FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) |
2005 | 0 | AsmString = "fcvt.s.w $\x01, $\x02"; |
2006 | 0 | break; |
2007 | 0 | } |
2008 | 0 | return false; |
2009 | 0 | case RISCV_FCVT_S_WU: |
2010 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2011 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2012 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2013 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2014 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2015 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
2016 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
2017 | | // (FCVT_S_WU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) |
2018 | 0 | AsmString = "fcvt.s.wu $\x01, $\x02"; |
2019 | 0 | break; |
2020 | 0 | } |
2021 | 0 | return false; |
2022 | 0 | case RISCV_FCVT_WU_D: |
2023 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2024 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2025 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2026 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2027 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2028 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
2029 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
2030 | | // (FCVT_WU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) |
2031 | 0 | AsmString = "fcvt.wu.d $\x01, $\x02"; |
2032 | 0 | break; |
2033 | 0 | } |
2034 | 0 | return false; |
2035 | 0 | case RISCV_FCVT_WU_S: |
2036 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2037 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2038 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2039 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2040 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2041 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
2042 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
2043 | | // (FCVT_WU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) |
2044 | 0 | AsmString = "fcvt.wu.s $\x01, $\x02"; |
2045 | 0 | break; |
2046 | 0 | } |
2047 | 0 | return false; |
2048 | 0 | case RISCV_FCVT_W_D: |
2049 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2050 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2051 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2052 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2053 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2054 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
2055 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
2056 | | // (FCVT_W_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) |
2057 | 0 | AsmString = "fcvt.w.d $\x01, $\x02"; |
2058 | 0 | break; |
2059 | 0 | } |
2060 | 0 | return false; |
2061 | 0 | case RISCV_FCVT_W_S: |
2062 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2063 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2064 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2065 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2066 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2067 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
2068 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
2069 | | // (FCVT_W_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) |
2070 | 0 | AsmString = "fcvt.w.s $\x01, $\x02"; |
2071 | 0 | break; |
2072 | 0 | } |
2073 | 0 | return false; |
2074 | 0 | case RISCV_FDIV_D: |
2075 | 0 | if (MCInst_getNumOperands(MI) == 4 && |
2076 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2077 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2078 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2079 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2080 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2081 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
2082 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
2083 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { |
2084 | | // (FDIV_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) |
2085 | 0 | AsmString = "fdiv.d $\x01, $\x02, $\x03"; |
2086 | 0 | break; |
2087 | 0 | } |
2088 | 0 | return false; |
2089 | 0 | case RISCV_FDIV_S: |
2090 | 0 | if (MCInst_getNumOperands(MI) == 4 && |
2091 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2092 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2093 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2094 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2095 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2096 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
2097 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
2098 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { |
2099 | | // (FDIV_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) |
2100 | 0 | AsmString = "fdiv.s $\x01, $\x02, $\x03"; |
2101 | 0 | break; |
2102 | 0 | } |
2103 | 0 | return false; |
2104 | 0 | case RISCV_FENCE: |
2105 | 0 | if (MCInst_getNumOperands(MI) == 2 && |
2106 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
2107 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && |
2108 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
2109 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { |
2110 | | // (FENCE 15, 15) |
2111 | 0 | AsmString = "fence"; |
2112 | 0 | break; |
2113 | 0 | } |
2114 | 0 | return false; |
2115 | 0 | case RISCV_FMADD_D: |
2116 | 0 | if (MCInst_getNumOperands(MI) == 5 && |
2117 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2118 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2119 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2120 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2121 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2122 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
2123 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 3)) && |
2124 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && |
2125 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 4)) && |
2126 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { |
2127 | | // (FMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) |
2128 | 0 | AsmString = "fmadd.d $\x01, $\x02, $\x03, $\x04"; |
2129 | 0 | break; |
2130 | 0 | } |
2131 | 0 | return false; |
2132 | 0 | case RISCV_FMADD_S: |
2133 | 0 | if (MCInst_getNumOperands(MI) == 5 && |
2134 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2135 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2136 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2137 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2138 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2139 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
2140 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 3)) && |
2141 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && |
2142 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 4)) && |
2143 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { |
2144 | | // (FMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) |
2145 | 0 | AsmString = "fmadd.s $\x01, $\x02, $\x03, $\x04"; |
2146 | 0 | break; |
2147 | 0 | } |
2148 | 0 | return false; |
2149 | 0 | case RISCV_FMSUB_D: |
2150 | 0 | if (MCInst_getNumOperands(MI) == 5 && |
2151 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2152 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2153 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2154 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2155 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2156 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
2157 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 3)) && |
2158 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && |
2159 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 4)) && |
2160 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { |
2161 | | // (FMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) |
2162 | 0 | AsmString = "fmsub.d $\x01, $\x02, $\x03, $\x04"; |
2163 | 0 | break; |
2164 | 0 | } |
2165 | 0 | return false; |
2166 | 0 | case RISCV_FMSUB_S: |
2167 | 0 | if (MCInst_getNumOperands(MI) == 5 && |
2168 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2169 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2170 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2171 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2172 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2173 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
2174 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 3)) && |
2175 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && |
2176 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 4)) && |
2177 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { |
2178 | | // (FMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) |
2179 | 0 | AsmString = "fmsub.s $\x01, $\x02, $\x03, $\x04"; |
2180 | 0 | break; |
2181 | 0 | } |
2182 | 0 | return false; |
2183 | 0 | case RISCV_FMUL_D: |
2184 | 0 | if (MCInst_getNumOperands(MI) == 4 && |
2185 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2186 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2187 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2188 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2189 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2190 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
2191 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
2192 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { |
2193 | | // (FMUL_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) |
2194 | 0 | AsmString = "fmul.d $\x01, $\x02, $\x03"; |
2195 | 0 | break; |
2196 | 0 | } |
2197 | 0 | return false; |
2198 | 0 | case RISCV_FMUL_S: |
2199 | 0 | if (MCInst_getNumOperands(MI) == 4 && |
2200 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2201 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2202 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2203 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2204 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2205 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
2206 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
2207 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { |
2208 | | // (FMUL_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) |
2209 | 0 | AsmString = "fmul.s $\x01, $\x02, $\x03"; |
2210 | 0 | break; |
2211 | 0 | } |
2212 | 0 | return false; |
2213 | 0 | case RISCV_FNMADD_D: |
2214 | 0 | if (MCInst_getNumOperands(MI) == 5 && |
2215 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2216 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2217 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2218 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2219 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2220 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
2221 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 3)) && |
2222 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && |
2223 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 4)) && |
2224 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { |
2225 | | // (FNMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) |
2226 | 0 | AsmString = "fnmadd.d $\x01, $\x02, $\x03, $\x04"; |
2227 | 0 | break; |
2228 | 0 | } |
2229 | 0 | return false; |
2230 | 0 | case RISCV_FNMADD_S: |
2231 | 0 | if (MCInst_getNumOperands(MI) == 5 && |
2232 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2233 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2234 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2235 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2236 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2237 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
2238 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 3)) && |
2239 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && |
2240 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 4)) && |
2241 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { |
2242 | | // (FNMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) |
2243 | 0 | AsmString = "fnmadd.s $\x01, $\x02, $\x03, $\x04"; |
2244 | 0 | break; |
2245 | 0 | } |
2246 | 0 | return false; |
2247 | 0 | case RISCV_FNMSUB_D: |
2248 | 0 | if (MCInst_getNumOperands(MI) == 5 && |
2249 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2250 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2251 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2252 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2253 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2254 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
2255 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 3)) && |
2256 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && |
2257 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 4)) && |
2258 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { |
2259 | | // (FNMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) |
2260 | 0 | AsmString = "fnmsub.d $\x01, $\x02, $\x03, $\x04"; |
2261 | 0 | break; |
2262 | 0 | } |
2263 | 0 | return false; |
2264 | 0 | case RISCV_FNMSUB_S: |
2265 | 0 | if (MCInst_getNumOperands(MI) == 5 && |
2266 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2267 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2268 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2269 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2270 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2271 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
2272 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 3)) && |
2273 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && |
2274 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 4)) && |
2275 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { |
2276 | | // (FNMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) |
2277 | 0 | AsmString = "fnmsub.s $\x01, $\x02, $\x03, $\x04"; |
2278 | 0 | break; |
2279 | 0 | } |
2280 | 0 | return false; |
2281 | 0 | case RISCV_FSGNJN_D: |
2282 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2283 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2284 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2285 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2286 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2287 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2288 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { |
2289 | | // (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs) |
2290 | 0 | AsmString = "fneg.d $\x01, $\x02"; |
2291 | 0 | break; |
2292 | 0 | } |
2293 | 0 | return false; |
2294 | 0 | case RISCV_FSGNJN_S: |
2295 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2296 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2297 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2298 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2299 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2300 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2301 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { |
2302 | | // (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs) |
2303 | 0 | AsmString = "fneg.s $\x01, $\x02"; |
2304 | 0 | break; |
2305 | 0 | } |
2306 | 0 | return false; |
2307 | 0 | case RISCV_FSGNJX_D: |
2308 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2309 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2310 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2311 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2312 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2313 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2314 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { |
2315 | | // (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs) |
2316 | 0 | AsmString = "fabs.d $\x01, $\x02"; |
2317 | 0 | break; |
2318 | 0 | } |
2319 | 0 | return false; |
2320 | 0 | case RISCV_FSGNJX_S: |
2321 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2322 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2323 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2324 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2325 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2326 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2327 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { |
2328 | | // (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs) |
2329 | 0 | AsmString = "fabs.s $\x01, $\x02"; |
2330 | 0 | break; |
2331 | 0 | } |
2332 | 0 | return false; |
2333 | 0 | case RISCV_FSGNJ_D: |
2334 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2335 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2336 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2337 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2338 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2339 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2340 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { |
2341 | | // (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs) |
2342 | 0 | AsmString = "fmv.d $\x01, $\x02"; |
2343 | 0 | break; |
2344 | 0 | } |
2345 | 0 | return false; |
2346 | 0 | case RISCV_FSGNJ_S: |
2347 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2348 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2349 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2350 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2351 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2352 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2353 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { |
2354 | | // (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs) |
2355 | 0 | AsmString = "fmv.s $\x01, $\x02"; |
2356 | 0 | break; |
2357 | 0 | } |
2358 | 0 | return false; |
2359 | 0 | case RISCV_FSQRT_D: |
2360 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2361 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2362 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2363 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2364 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2365 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
2366 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
2367 | | // (FSQRT_D FPR64:$rd, FPR64:$rs1, { 1, 1, 1 }) |
2368 | 0 | AsmString = "fsqrt.d $\x01, $\x02"; |
2369 | 0 | break; |
2370 | 0 | } |
2371 | 0 | return false; |
2372 | 0 | case RISCV_FSQRT_S: |
2373 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2374 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2375 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2376 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2377 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2378 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
2379 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { |
2380 | | // (FSQRT_S FPR32:$rd, FPR32:$rs1, { 1, 1, 1 }) |
2381 | 0 | AsmString = "fsqrt.s $\x01, $\x02"; |
2382 | 0 | break; |
2383 | 0 | } |
2384 | 0 | return false; |
2385 | 0 | case RISCV_FSUB_D: |
2386 | 0 | if (MCInst_getNumOperands(MI) == 4 && |
2387 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2388 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2389 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2390 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2391 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2392 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
2393 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
2394 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { |
2395 | | // (FSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) |
2396 | 0 | AsmString = "fsub.d $\x01, $\x02, $\x03"; |
2397 | 0 | break; |
2398 | 0 | } |
2399 | 0 | return false; |
2400 | 0 | case RISCV_FSUB_S: |
2401 | 0 | if (MCInst_getNumOperands(MI) == 4 && |
2402 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2403 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2404 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2405 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2406 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2407 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && |
2408 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 3)) && |
2409 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { |
2410 | | // (FSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) |
2411 | 0 | AsmString = "fsub.s $\x01, $\x02, $\x03"; |
2412 | 0 | break; |
2413 | 0 | } |
2414 | 0 | return false; |
2415 | 0 | case RISCV_JAL: |
2416 | 0 | if (MCInst_getNumOperands(MI) == 2 && |
2417 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && |
2418 | 0 | RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2)) { |
2419 | | // (JAL X0, simm21_lsb0_jal:$offset) |
2420 | 0 | AsmString = "j $\x02"; |
2421 | 0 | break; |
2422 | 0 | } |
2423 | 0 | if (MCInst_getNumOperands(MI) == 2 && |
2424 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1 && |
2425 | 0 | RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2)) { |
2426 | | // (JAL X1, simm21_lsb0_jal:$offset) |
2427 | 0 | AsmString = "jal $\x02"; |
2428 | 0 | break; |
2429 | 0 | } |
2430 | 0 | return false; |
2431 | 0 | case RISCV_JALR: |
2432 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2433 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && |
2434 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X1 && |
2435 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
2436 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
2437 | | // (JALR X0, X1, 0) |
2438 | 0 | AsmString = "ret"; |
2439 | 0 | break; |
2440 | 0 | } |
2441 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2442 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && |
2443 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2444 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2445 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
2446 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
2447 | | // (JALR X0, GPR:$rs, 0) |
2448 | 0 | AsmString = "jr $\x02"; |
2449 | 0 | break; |
2450 | 0 | } |
2451 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2452 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1 && |
2453 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2454 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2455 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
2456 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { |
2457 | | // (JALR X1, GPR:$rs, 0) |
2458 | 0 | AsmString = "jalr $\x02"; |
2459 | 0 | break; |
2460 | 0 | } |
2461 | 0 | return false; |
2462 | 0 | case RISCV_SFENCE_VMA: |
2463 | 0 | if (MCInst_getNumOperands(MI) == 2 && |
2464 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && |
2465 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) { |
2466 | | // (SFENCE_VMA X0, X0) |
2467 | 0 | AsmString = "sfence.vma"; |
2468 | 0 | break; |
2469 | 0 | } |
2470 | 0 | if (MCInst_getNumOperands(MI) == 2 && |
2471 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2472 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2473 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) { |
2474 | | // (SFENCE_VMA GPR:$rs, X0) |
2475 | 0 | AsmString = "sfence.vma $\x01"; |
2476 | 0 | break; |
2477 | 0 | } |
2478 | 0 | return false; |
2479 | 0 | case RISCV_SLT: |
2480 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2481 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2482 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2483 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2484 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2485 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { |
2486 | | // (SLT GPR:$rd, GPR:$rs, X0) |
2487 | 0 | AsmString = "sltz $\x01, $\x02"; |
2488 | 0 | break; |
2489 | 0 | } |
2490 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2491 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2492 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2493 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && |
2494 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2495 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { |
2496 | | // (SLT GPR:$rd, X0, GPR:$rs) |
2497 | 0 | AsmString = "sgtz $\x01, $\x03"; |
2498 | 0 | break; |
2499 | 0 | } |
2500 | 0 | return false; |
2501 | 0 | case RISCV_SLTIU: |
2502 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2503 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2504 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2505 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2506 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2507 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
2508 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { |
2509 | | // (SLTIU GPR:$rd, GPR:$rs, 1) |
2510 | 0 | AsmString = "seqz $\x01, $\x02"; |
2511 | 0 | break; |
2512 | 0 | } |
2513 | 0 | return false; |
2514 | 0 | case RISCV_SLTU: |
2515 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2516 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2517 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2518 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && |
2519 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2520 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { |
2521 | | // (SLTU GPR:$rd, X0, GPR:$rs) |
2522 | 0 | AsmString = "snez $\x01, $\x03"; |
2523 | 0 | break; |
2524 | 0 | } |
2525 | 0 | return false; |
2526 | 0 | case RISCV_SUB: |
2527 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2528 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2529 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2530 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && |
2531 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2532 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { |
2533 | | // (SUB GPR:$rd, X0, GPR:$rs) |
2534 | 0 | AsmString = "neg $\x01, $\x03"; |
2535 | 0 | break; |
2536 | 0 | } |
2537 | 0 | return false; |
2538 | 0 | case RISCV_SUBW: |
2539 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2540 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2541 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2542 | 0 | MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && |
2543 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
2544 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { |
2545 | | // (SUBW GPR:$rd, X0, GPR:$rs) |
2546 | 0 | AsmString = "negw $\x01, $\x03"; |
2547 | 0 | break; |
2548 | 0 | } |
2549 | 0 | return false; |
2550 | 0 | case RISCV_XORI: |
2551 | 0 | if (MCInst_getNumOperands(MI) == 3 && |
2552 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
2553 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && |
2554 | 0 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
2555 | 0 | MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && |
2556 | 0 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
2557 | 0 | MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1) { |
2558 | | // (XORI GPR:$rd, GPR:$rs, -1) |
2559 | 0 | AsmString = "not $\x01, $\x02"; |
2560 | 0 | break; |
2561 | 0 | } |
2562 | 0 | return false; |
2563 | 0 | } |
2564 | | |
2565 | 0 | AsmStringLen = strlen(AsmString); |
2566 | 0 | if (ASMSTRING_CONTAIN_SIZE - 1 < AsmStringLen) |
2567 | 0 | tmpString = cs_strdup(AsmString); |
2568 | 0 | else |
2569 | 0 | tmpString = memcpy(tmpString, AsmString, 1 + AsmStringLen); |
2570 | |
|
2571 | 0 | while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
2572 | 0 | AsmString[I] != '$' && AsmString[I] != '\0') |
2573 | 0 | ++I; |
2574 | 0 | tmpString[I] = 0; |
2575 | 0 | SStream_concat0(OS, tmpString); |
2576 | 0 | if (ASMSTRING_CONTAIN_SIZE - 1 < AsmStringLen) |
2577 | | /* Free the possible cs_strdup() memory. PR#1424. */ |
2578 | 0 | cs_mem_free(tmpString); |
2579 | 0 | #undef ASMSTRING_CONTAIN_SIZE |
2580 | |
|
2581 | 0 | if (AsmString[I] != '\0') { |
2582 | 0 | if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
2583 | 0 | SStream_concat0(OS, " "); |
2584 | 0 | ++I; |
2585 | 0 | } |
2586 | 0 | do { |
2587 | 0 | if (AsmString[I] == '$') { |
2588 | 0 | ++I; |
2589 | 0 | if (AsmString[I] == (char)0xff) { |
2590 | 0 | ++I; |
2591 | 0 | int OpIdx = AsmString[I++] - 1; |
2592 | 0 | int PrintMethodIdx = AsmString[I++] - 1; |
2593 | 0 | printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); |
2594 | 0 | } else |
2595 | 0 | printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); |
2596 | 0 | } else { |
2597 | 0 | SStream_concat1(OS, AsmString[I++]); |
2598 | 0 | } |
2599 | 0 | } while (AsmString[I] != '\0'); |
2600 | 0 | } |
2601 | |
|
2602 | 0 | return true; |
2603 | 0 | } |
2604 | | |
2605 | | static void printCustomAliasOperand( |
2606 | | MCInst *MI, unsigned OpIdx, |
2607 | | unsigned PrintMethodIdx, |
2608 | 0 | SStream *OS) { |
2609 | 0 | switch (PrintMethodIdx) { |
2610 | 0 | default: |
2611 | 0 | CS_ASSERT(0 && "Unknown PrintMethod kind"); |
2612 | 0 | break; |
2613 | 0 | case 0: |
2614 | 0 | printCSRSystemRegister(MI, OpIdx, OS); |
2615 | 0 | break; |
2616 | 0 | } |
2617 | 0 | } |
2618 | | |
2619 | | static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp, |
2620 | 0 | unsigned PredicateIndex) { |
2621 | | // TODO: need some constant untils operate the MCOperand, |
2622 | | // but current CAPSTONE does't have. |
2623 | | // So, We just return true |
2624 | 0 | return true; |
2625 | |
|
2626 | | #if 0 |
2627 | | switch (PredicateIndex) { |
2628 | | default: |
2629 | | llvm_unreachable("Unknown MCOperandPredicate kind"); |
2630 | | break; |
2631 | | case 1: { |
2632 | | |
2633 | | int64_t Imm; |
2634 | | if (MCOp.evaluateAsConstantImm(Imm)) |
2635 | | return isShiftedInt<12, 1>(Imm); |
2636 | | return MCOp.isBareSymbolRef(); |
2637 | | |
2638 | | } |
2639 | | case 2: { |
2640 | | |
2641 | | int64_t Imm; |
2642 | | if (MCOp.evaluateAsConstantImm(Imm)) |
2643 | | return isShiftedInt<20, 1>(Imm); |
2644 | | return MCOp.isBareSymbolRef(); |
2645 | | |
2646 | | } |
2647 | | } |
2648 | | #endif |
2649 | 0 | } |
2650 | | |
2651 | | #endif // PRINT_ALIAS_INSTR |