/* Capstone Disassembly Engine */

/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */

/*    Rot127 <unisono@quyllur.org>, 2022-2023 */

#ifdef CAPSTONE_HAS_ARM

#include <stdio.h>

#include <string.h>

#include "capstone/arm.h"

#include "capstone/capstone.h"

#include "../../Mapping.h"

#include "../../MCDisassembler.h"

#include "../../cs_priv.h"

#include "../../cs_simple_types.h"

#include "ARMAddressingModes.h"

#include "ARMDisassemblerExtension.h"

#include "ARMBaseInfo.h"

#include "ARMLinkage.h"

#include "ARMInstPrinter.h"

#include "ARMMapping.h"

static const char *get_custom_reg_alias(unsigned reg)

{

  switch (reg) {

  case ARM_REG_R9:

    return "sb";

  case ARM_REG_R10:

    return "sl";

  case ARM_REG_R11:

    return "fp";

  case ARM_REG_R12:

    return "ip";

  case ARM_REG_R13:

    return "sp";

  case ARM_REG_R14:

    return "lr";

  case ARM_REG_R15:

    return "pc";

  }

  return NULL;

}

const char *ARM_reg_name(csh handle, unsigned int reg)

{

  int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax;

  const char *alias = get_custom_reg_alias(reg);

  if ((syntax_opt & CS_OPT_SYNTAX_CS_REG_ALIAS) && alias)

    return alias;

  if (reg == ARM_REG_INVALID || reg >= ARM_REG_ENDING) {

    // This might be a system register or banked register encoding.

    // Note: The system and banked register encodings can overlap.

    // So this might return a system register name although a

    // banked register name is expected.

    const ARMSysReg_MClassSysReg *sys_reg =

      ARMSysReg_lookupMClassSysRegByEncoding(reg);

    if (sys_reg)

      return sys_reg->Name;

    const ARMBankedReg_BankedReg *banked_reg =

      ARMBankedReg_lookupBankedRegByEncoding(reg);

    if (banked_reg)

      return banked_reg->Name;

  }

  if (syntax_opt & CS_OPT_SYNTAX_NOREGNAME) {

    return ARM_LLVM_getRegisterName(reg, ARM_NoRegAltName);

  }

  return ARM_LLVM_getRegisterName(reg, ARM_RegNamesRaw);

}

const insn_map arm_insns[] = {

#include "ARMGenCSMappingInsn.inc"

};

void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)

{

  // Not used by ARM. Information is set after disassembly.

}

/// Patches the register names with Capstone specific alias.

/// Those are common alias for registers (e.g. r15 = pc)

/// which are not set in LLVM.

static void patch_cs_reg_alias(char *asm_str)

{

  char *r9 = strstr(asm_str, "r9");

  while (r9) {

    r9[0] = 's';

    r9[1] = 'b';

    r9 = strstr(asm_str, "r9");

  }

  char *r10 = strstr(asm_str, "r10");

  while (r10) {

    r10[0] = 's';

    r10[1] = 'l';

    memmove(r10 + 2, r10 + 3, strlen(r10 + 3));

    asm_str[strlen(asm_str) - 1] = '\0';

    r10 = strstr(asm_str, "r10");

  }

  char *r11 = strstr(asm_str, "r11");

  while (r11) {

    r11[0] = 'f';

    r11[1] = 'p';

    memmove(r11 + 2, r11 + 3, strlen(r11 + 3));

    asm_str[strlen(asm_str) - 1] = '\0';

    r11 = strstr(asm_str, "r11");

  }

  char *r12 = strstr(asm_str, "r12");

  while (r12) {

    r12[0] = 'i';

    r12[1] = 'p';

    memmove(r12 + 2, r12 + 3, strlen(r12 + 3));

    asm_str[strlen(asm_str) - 1] = '\0';

    r12 = strstr(asm_str, "r12");

  }

  char *r13 = strstr(asm_str, "r13");

  while (r13) {

    r13[0] = 's';

    r13[1] = 'p';

    memmove(r13 + 2, r13 + 3, strlen(r13 + 3));

    asm_str[strlen(asm_str) - 1] = '\0';

    r13 = strstr(asm_str, "r13");

  }

  char *r14 = strstr(asm_str, "r14");

  while (r14) {

    r14[0] = 'l';

    r14[1] = 'r';

    memmove(r14 + 2, r14 + 3, strlen(r14 + 3));

    asm_str[strlen(asm_str) - 1] = '\0';

    r14 = strstr(asm_str, "r14");

  }

  char *r15 = strstr(asm_str, "r15");

  while (r15) {

    r15[0] = 'p';

    r15[1] = 'c';

    memmove(r15 + 2, r15 + 3, strlen(r15 + 3));

    asm_str[strlen(asm_str) - 1] = '\0';

    r15 = strstr(asm_str, "r15");

  }

}

/// Adds group to the instruction which are not defined in LLVM.

static void ARM_add_cs_groups(MCInst *MI)

{

  unsigned Opcode = MI->flat_insn->id;

  switch (Opcode) {

  default:

    return;

  case ARM_INS_SVC:

    add_group(MI, ARM_GRP_INT);

    break;

  case ARM_INS_CDP:

  case ARM_INS_CDP2:

  case ARM_INS_MCR:

  case ARM_INS_MCR2:

  case ARM_INS_MCRR:

  case ARM_INS_MCRR2:

  case ARM_INS_MRC:

  case ARM_INS_MRC2:

  case ARM_INS_SMC:

    add_group(MI, ARM_GRP_PRIVILEGE);

    break;

  }

}

/// Some instructions have their operands not defined but

/// hardcoded as string.

/// Here we add those oprands to detail.

static void ARM_add_not_defined_ops(MCInst *MI)

{

  if (!detail_is_set(MI))

    return;

  unsigned Opcode = MCInst_getOpcode(MI);

  switch (Opcode) {

  default:

    return;

  case ARM_t2MOVsra_flag:

  case ARM_t2MOVsrl_flag:

    ARM_insert_detail_op_imm_at(MI, 2, 1, CS_AC_READ);

    break;

  case ARM_VCMPEZD:

  case ARM_VCMPZD:

  case ARM_tRSB:

  case ARM_VCMPEZH:

  case ARM_VCMPEZS:

  case ARM_VCMPZH:

  case ARM_VCMPZS:

    ARM_insert_detail_op_imm_at(MI, 1, 0, CS_AC_READ);

    break;

  case ARM_MVE_VSHLL_lws16bh:

  case ARM_MVE_VSHLL_lws16th:

  case ARM_MVE_VSHLL_lwu16bh:

  case ARM_MVE_VSHLL_lwu16th:

    ARM_insert_detail_op_imm_at(MI, 2, 16, CS_AC_READ);

    break;

  case ARM_MVE_VSHLL_lws8bh:

  case ARM_MVE_VSHLL_lws8th:

  case ARM_MVE_VSHLL_lwu8bh:

  case ARM_MVE_VSHLL_lwu8th:

    ARM_insert_detail_op_imm_at(MI, 2, 8, CS_AC_READ);

    break;

  case ARM_VCEQzv16i8:

  case ARM_VCEQzv2f32:

  case ARM_VCEQzv2i32:

  case ARM_VCEQzv4f16:

  case ARM_VCEQzv4f32:

  case ARM_VCEQzv4i16:

  case ARM_VCEQzv4i32:

  case ARM_VCEQzv8f16:

  case ARM_VCEQzv8i16:

  case ARM_VCEQzv8i8:

  case ARM_VCGEzv16i8:

  case ARM_VCGEzv2f32:

  case ARM_VCGEzv2i32:

  case ARM_VCGEzv4f16:

  case ARM_VCGEzv4f32:

  case ARM_VCGEzv4i16:

  case ARM_VCGEzv4i32:

  case ARM_VCGEzv8f16:

  case ARM_VCGEzv8i16:

  case ARM_VCGEzv8i8:

  case ARM_VCLEzv16i8:

  case ARM_VCLEzv2f32:

  case ARM_VCLEzv2i32:

  case ARM_VCLEzv4f16:

  case ARM_VCLEzv4f32:

  case ARM_VCLEzv4i16:

  case ARM_VCLEzv4i32:

  case ARM_VCLEzv8f16:

  case ARM_VCLEzv8i16:

  case ARM_VCLEzv8i8:

  case ARM_VCLTzv16i8:

  case ARM_VCLTzv2f32:

  case ARM_VCLTzv2i32:

  case ARM_VCLTzv4f16:

  case ARM_VCLTzv4f32:

  case ARM_VCLTzv4i16:

  case ARM_VCLTzv4i32:

  case ARM_VCLTzv8f16:

  case ARM_VCLTzv8i16:

  case ARM_VCLTzv8i8:

  case ARM_VCGTzv16i8:

  case ARM_VCGTzv2f32:

  case ARM_VCGTzv2i32:

  case ARM_VCGTzv4f16:

  case ARM_VCGTzv4f32:

  case ARM_VCGTzv4i16:

  case ARM_VCGTzv4i32:

  case ARM_VCGTzv8f16:

  case ARM_VCGTzv8i16:

  case ARM_VCGTzv8i8:

    ARM_insert_detail_op_imm_at(MI, 2, 0, CS_AC_READ);

    break;

  case ARM_BX_RET:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_LR, CS_AC_READ);

    break;

  case ARM_MOVPCLR:

  case ARM_t2SUBS_PC_LR:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_PC, CS_AC_WRITE);

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_LR, CS_AC_READ);

    break;

  case ARM_FMSTAT:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_APSR_NZCV,

              CS_AC_WRITE);

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPSCR, CS_AC_READ);

    break;

  case ARM_VLDR_FPCXTNS_off:

  case ARM_VLDR_FPCXTNS_post:

  case ARM_VLDR_FPCXTNS_pre:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPCXTNS,

              CS_AC_WRITE);

    break;

  case ARM_VSTR_FPCXTNS_off:

  case ARM_VSTR_FPCXTNS_post:

  case ARM_VSTR_FPCXTNS_pre:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPCXTNS, CS_AC_READ);

    break;

  case ARM_VLDR_FPCXTS_off:

  case ARM_VLDR_FPCXTS_post:

  case ARM_VLDR_FPCXTS_pre:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPCXTS, CS_AC_WRITE);

    break;

  case ARM_VSTR_FPCXTS_off:

  case ARM_VSTR_FPCXTS_post:

  case ARM_VSTR_FPCXTS_pre:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPCXTS, CS_AC_READ);

    break;

  case ARM_VLDR_FPSCR_NZCVQC_off:

  case ARM_VLDR_FPSCR_NZCVQC_post:

  case ARM_VLDR_FPSCR_NZCVQC_pre:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPSCR_NZCVQC,

              CS_AC_WRITE);

    break;

  case ARM_VSTR_FPSCR_NZCVQC_off:

  case ARM_VSTR_FPSCR_NZCVQC_post:

  case ARM_VSTR_FPSCR_NZCVQC_pre:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPSCR_NZCVQC,

              CS_AC_READ);

    break;

  case ARM_VMSR:

  case ARM_VLDR_FPSCR_off:

  case ARM_VLDR_FPSCR_post:

  case ARM_VLDR_FPSCR_pre:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPSCR, CS_AC_WRITE);

    break;

  case ARM_VSTR_FPSCR_off:

  case ARM_VSTR_FPSCR_post:

  case ARM_VSTR_FPSCR_pre:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPSCR, CS_AC_READ);

    break;

  case ARM_VLDR_P0_off:

  case ARM_VLDR_P0_post:

  case ARM_VLDR_P0_pre:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_P0, CS_AC_WRITE);

    break;

  case ARM_VSTR_P0_off:

  case ARM_VSTR_P0_post:

  case ARM_VSTR_P0_pre:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_P0, CS_AC_READ);

    break;

  case ARM_VLDR_VPR_off:

  case ARM_VLDR_VPR_post:

  case ARM_VLDR_VPR_pre:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_VPR, CS_AC_WRITE);

    break;

  case ARM_VSTR_VPR_off:

  case ARM_VSTR_VPR_post:

  case ARM_VSTR_VPR_pre:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_VPR, CS_AC_READ);

    break;

  case ARM_VMSR_FPEXC:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPEXC, CS_AC_WRITE);

    break;

  case ARM_VMSR_FPINST:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPINST, CS_AC_WRITE);

    break;

  case ARM_VMSR_FPINST2:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPINST2,

              CS_AC_WRITE);

    break;

  case ARM_VMSR_FPSID:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPSID, CS_AC_WRITE);

    break;

  case ARM_t2SRSDB:

  case ARM_t2SRSIA:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_SP, CS_AC_WRITE);

    break;

  case ARM_t2SRSDB_UPD:

  case ARM_t2SRSIA_UPD:

    ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_SP,

              CS_AC_READ | CS_AC_WRITE);

    break;

  case ARM_MRSsys:

  case ARM_t2MRSsys_AR:

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_SPSR, CS_AC_READ);

    break;

  case ARM_MRS:

  case ARM_t2MRS_AR:

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_APSR, CS_AC_READ);

    break;

  case ARM_VMRS:

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPSCR, CS_AC_READ);

    break;

  case ARM_VMRS_FPCXTNS:

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPCXTNS, CS_AC_READ);

    break;

  case ARM_VMRS_FPCXTS:

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPCXTS, CS_AC_READ);

    break;

  case ARM_VMRS_FPEXC:

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPEXC, CS_AC_READ);

    break;

  case ARM_VMRS_FPINST:

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPINST, CS_AC_READ);

    break;

  case ARM_VMRS_FPINST2:

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPINST2, CS_AC_READ);

    break;

  case ARM_VMRS_FPSCR_NZCVQC:

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPSCR_NZCVQC,

              CS_AC_READ);

    break;

  case ARM_VMRS_FPSID:

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPSID, CS_AC_READ);

    break;

  case ARM_VMRS_MVFR0:

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_MVFR0, CS_AC_READ);

    break;

  case ARM_VMRS_MVFR1:

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_MVFR1, CS_AC_READ);

    break;

  case ARM_VMRS_MVFR2:

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_MVFR2, CS_AC_READ);

    break;

  case ARM_VMRS_P0:

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_P0, CS_AC_READ);

    break;

  case ARM_VMRS_VPR:

    ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_VPR, CS_AC_READ);

    break;

  case ARM_MOVsr:

    // Add shift information

    ARM_get_detail(MI)->operands[1].shift.type =

      (arm_shifter)ARM_AM_getSORegShOp(

        MCInst_getOpVal(MI, 3)) +

      ARM_SFT_ASR_REG - 1;

    ARM_get_detail(MI)->operands[1].shift.value =

      MCInst_getOpVal(MI, 2);

    break;

  case ARM_MOVsi:

    if (ARM_AM_getSORegShOp(MCInst_getOpVal(MI, 2)) == ARM_AM_rrx) {

      ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_RRX;

      ARM_get_detail_op(MI, -1)->shift.value =

        translateShiftImm(ARM_AM_getSORegOffset(

          MCInst_getOpVal(MI, 2)));

      return;

    }

    ARM_get_detail_op(MI, -1)->shift.type =

      (arm_shifter)ARM_AM_getSORegShOp(

        MCInst_getOpVal(MI, 2));

    ARM_get_detail_op(MI, -1)->shift.value = translateShiftImm(

      ARM_AM_getSORegOffset(MCInst_getOpVal(MI, 2)));

    break;

  case ARM_STMDB_UPD:

  case ARM_t2STMDB_UPD:

    if (MCInst_getOpVal(MI, 0) == ARM_SP &&

        MCInst_getNumOperands(MI) > 5)

      MI->flat_insn->id = ARM_INS_PUSH;

    break;

  case ARM_STR_PRE_IMM:

    if (MCOperand_getReg(MCInst_getOperand(MI, (2))) == ARM_SP &&

        MCOperand_getImm(MCInst_getOperand(MI, (3))) == -4)

      MI->flat_insn->id = ARM_INS_PUSH;

    break;

  case ARM_LDMIA_UPD:

  case ARM_t2LDMIA_UPD:

    if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP &&

        MCInst_getNumOperands(MI) > 5)

      MI->flat_insn->id = ARM_INS_POP;

    break;

  case ARM_LDR_POST_IMM:

    if (MCOperand_getReg(MCInst_getOperand(MI, (2))) == ARM_SP &&

        ARM_AM_getAM2Offset(

          MCOperand_getImm(MCInst_getOperand(MI, (4)))) == 4)

      MI->flat_insn->id = ARM_INS_POP;

    break;

  case ARM_t2LDR_POST:

    if ((MCOperand_getReg(MCInst_getOperand(MI, (2))) == ARM_SP) &&

        (Opcode == ARM_t2LDR_POST &&

         (MCOperand_getImm(MCInst_getOperand(MI, (3))) == 4)))

      MI->flat_insn->id = ARM_INS_POP;

    break;

  case ARM_VSTMSDB_UPD:

  case ARM_VSTMDDB_UPD:

    if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP)

      MI->flat_insn->id = ARM_INS_VPUSH;

    break;

  case ARM_VLDMSIA_UPD:

  case ARM_VLDMDIA_UPD:

    if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP)

      MI->flat_insn->id = ARM_INS_VPOP;

    break;

  case ARM_tLDMIA: {

    bool Writeback = true;

    unsigned BaseReg = MCInst_getOpVal(MI, 0);

    for (unsigned i = 3; i < MCInst_getNumOperands(MI); ++i) {

      if (MCInst_getOpVal(MI, i) == BaseReg)

        Writeback = false;

    }

    if (Writeback && detail_is_set(MI)) {

      ARM_get_detail(MI)->operands[0].access |= CS_AC_WRITE;

      MI->flat_insn->detail->writeback = true;

    }

    break;

  }

  }

  if (MI->flat_insn->id == ARM_INS_PUSH ||

      MI->flat_insn->id == ARM_INS_POP ||

      MI->flat_insn->id == ARM_INS_VPUSH ||

      MI->flat_insn->id == ARM_INS_VPOP) {

    map_add_implicit_read(MI, ARM_REG_SP);

    map_add_implicit_write(MI, ARM_REG_SP);

  }

}

/// Unfortunately there is currently no way to easily extract

/// informaion about the vector data usage (sign and width used).

/// See: https://github.com/capstone-engine/capstone/issues/2152

void ARM_add_vector_data(MCInst *MI, arm_vectordata_type data_type)

{

  if (!detail_is_set(MI))

    return;

  ARM_get_detail(MI)->vector_data = data_type;

}

/// Unfortunately there is currently no way to easily extract

/// informaion about the vector size.

/// See: https://github.com/capstone-engine/capstone/issues/2152

void ARM_add_vector_size(MCInst *MI, unsigned size)

{

  if (!detail_is_set(MI))

    return;

  ARM_get_detail(MI)->vector_size = size;

}

/// For ARM the attributation of post-indexed instructions is poor.

/// Disponents or index register are sometimes not defined as such.

/// Here we try to detect such cases. We check if the base register

/// is a writeback register, but no other memory operand

/// was disassembled.

/// Because there must be a second memory operand (disponent/index)

/// We assume that the following operand is actually

/// the disponent/index reg.

static void ARM_post_index_detection(MCInst *MI)

{

  if (!detail_is_set(MI) || ARM_get_detail(MI)->post_index)

    return;

  int i = 0;

  for (; i < ARM_get_detail(MI)->op_count; ++i) {

    if (ARM_get_detail(MI)->operands[i].type & ARM_OP_MEM)

      break;

  }

  if (i >= ARM_get_detail(MI)->op_count) {

    // Last operand

    return;

  }

  cs_arm_op *op = &ARM_get_detail(MI)->operands[i];

  cs_arm_op op_next = ARM_get_detail(MI)->operands[i + 1];

  if (op_next.type == ARM_OP_INVALID || op->mem.disp != 0 || op->mem.index != ARM_REG_INVALID)

    return;

  if (op_next.type & CS_OP_IMM)

    op->mem.disp = op_next.imm;

  else if (op_next.type & CS_OP_REG)

    op->mem.index = op_next.reg;

  op->subtracted = op_next.subtracted;

  ARM_get_detail(MI)->post_index = true;

  MI->flat_insn->detail->writeback = true;

  ARM_dec_op_count(MI);

}

/// Decodes the asm string for a given instruction

/// and fills the detail information about the instruction and its operands.

void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)

{

  ARM_LLVM_printInstruction(MI, O, info);

  ARM_add_not_defined_ops(MI);

  ARM_post_index_detection(MI);

  ARM_add_cs_groups(MI);

  int syntax_opt = MI->csh->syntax;

  if (syntax_opt & CS_OPT_SYNTAX_CS_REG_ALIAS)

    patch_cs_reg_alias(O->buffer);

}

#ifndef CAPSTONE_DIET

static const char *const insn_name_maps[] = {

#include "ARMGenCSMappingInsnName.inc"

  // Hard coded alias in LLVM, not defined as alias or instruction.

  // We give them a unique ID for convenience.

  "vpop",

  "vpush",

};

#endif

#ifndef CAPSTONE_DIET

static arm_reg arm_flag_regs[] = {

  ARM_REG_APSR,       ARM_REG_APSR_NZCV, ARM_REG_CPSR,

  ARM_REG_FPCXTNS,      ARM_REG_FPCXTS,  ARM_REG_FPEXC,

  ARM_REG_FPINST,       ARM_REG_FPSCR,   ARM_REG_FPSCR_NZCV,

  ARM_REG_FPSCR_NZCVQC,

};

#endif // CAPSTONE_DIET

const char *ARM_insn_name(csh handle, unsigned int id)

{

#ifndef CAPSTONE_DIET

  if (id >= ARM_INS_ENDING)

    return NULL;

  return insn_name_maps[id];

#else

  return NULL;

#endif

}

#ifndef CAPSTONE_DIET

static const name_map group_name_maps[] = {

  // generic groups

  { ARM_GRP_INVALID, NULL },

  { ARM_GRP_JUMP, "jump" },

  { ARM_GRP_CALL, "call" },

  { ARM_GRP_INT, "int" },

  { ARM_GRP_PRIVILEGE, "privilege" },

  { ARM_GRP_BRANCH_RELATIVE, "branch_relative" },

// architecture-specific groups

#include "ARMGenCSFeatureName.inc"

};

#endif

const char *ARM_group_name(csh handle, unsigned int id)

{

#ifndef CAPSTONE_DIET

  return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);

#else

  return NULL;

#endif

}

// list all relative branch instructions

// ie: insns[i].branch && !insns[i].indirect_branch

static const unsigned int insn_rel[] = {

  ARM_BL,   ARM_BLX_pred, ARM_Bcc,   ARM_t2B,  ARM_t2Bcc,

  ARM_tB,   ARM_tBcc, ARM_tCBNZ, ARM_tCBZ, ARM_BL_pred,

  ARM_BLXi, ARM_tBL,  ARM_tBLXi, 0

};

static const unsigned int insn_blx_rel_to_arm[] = { ARM_tBLXi, 0 };

// check if this insn is relative branch

bool ARM_rel_branch(cs_struct *h, unsigned int id)

{

  int i;

  for (i = 0; insn_rel[i]; i++) {

    if (id == insn_rel[i]) {

      return true;

    }

  }

  // not found

  return false;

}

bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id)

{

  int i;

  for (i = 0; insn_blx_rel_to_arm[i]; i++)

    if (id == insn_blx_rel_to_arm[i])

      return true;

  // not found

  return false;

}

void ARM_check_updates_flags(MCInst *MI)

{

#ifndef CAPSTONE_DIET

  if (!detail_is_set(MI))

    return;

  cs_detail *detail = get_detail(MI);

  for (int i = 0; i < detail->regs_write_count; ++i) {

    if (detail->regs_write[i] == 0)

      return;

    for (int j = 0; j < ARR_SIZE(arm_flag_regs); ++j) {

      if (detail->regs_write[i] == arm_flag_regs[j]) {

        detail->arm.update_flags = true;

        return;

      }

    }

  }

#endif // CAPSTONE_DIET

}

void ARM_set_instr_map_data(MCInst *MI)

{

  map_cs_id(MI, arm_insns, ARR_SIZE(arm_insns));

  map_implicit_reads(MI, arm_insns);

  map_implicit_writes(MI, arm_insns);

  ARM_check_updates_flags(MI);

  map_groups(MI, arm_insns);

}

bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len,

      MCInst *instr, uint16_t *size, uint64_t address,

      void *info)

{

  ARM_init_cs_detail(instr);

  bool Result = ARM_LLVM_getInstruction(handle, code, code_len, instr,

                size, address,

                info) != MCDisassembler_Fail;

  ARM_set_instr_map_data(instr);

  return Result;

}

#define GET_REGINFO_MC_DESC

#include "ARMGenRegisterInfo.inc"

void ARM_init_mri(MCRegisterInfo *MRI)

{

  MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, ARM_REG_ENDING, 0, 0,

            ARMMCRegisterClasses,

            ARR_SIZE(ARMMCRegisterClasses), 0, 0,

            ARMRegDiffLists, 0, ARMSubRegIdxLists,

            ARR_SIZE(ARMSubRegIdxLists), 0);

}

static const map_insn_ops insn_operands[] = {

#include "ARMGenCSMappingInsnOp.inc"

};

#ifndef CAPSTONE_DIET

void ARM_reg_access(const cs_insn *insn, cs_regs regs_read,

        uint8_t *regs_read_count, cs_regs regs_write,

        uint8_t *regs_write_count)

{

  uint8_t i;

  uint8_t read_count, write_count;

  cs_arm *arm = &(insn->detail->arm);

  read_count = insn->detail->regs_read_count;

  write_count = insn->detail->regs_write_count;

  // implicit registers

  memcpy(regs_read, insn->detail->regs_read,

         read_count * sizeof(insn->detail->regs_read[0]));

  memcpy(regs_write, insn->detail->regs_write,

         write_count * sizeof(insn->detail->regs_write[0]));

  // explicit registers

  for (i = 0; i < arm->op_count; i++) {

    cs_arm_op *op = &(arm->operands[i]);

    switch ((int)op->type) {

    case ARM_OP_REG:

      if ((op->access & CS_AC_READ) &&

          !arr_exist(regs_read, read_count, op->reg)) {

        regs_read[read_count] = (uint16_t)op->reg;

        read_count++;

      }

      if ((op->access & CS_AC_WRITE) &&

          !arr_exist(regs_write, write_count, op->reg)) {

        regs_write[write_count] = (uint16_t)op->reg;

        write_count++;

      }

      break;

    case ARM_OP_MEM:

      // registers appeared in memory references always being read

      if ((op->mem.base != ARM_REG_INVALID) &&

          !arr_exist(regs_read, read_count, op->mem.base)) {

        regs_read[read_count] = (uint16_t)op->mem.base;

        read_count++;

      }

      if ((op->mem.index != ARM_REG_INVALID) &&

          !arr_exist(regs_read, read_count, op->mem.index)) {

        regs_read[read_count] = (uint16_t)op->mem.index;

        read_count++;

      }

      if ((insn->detail->writeback) &&

          (op->mem.base != ARM_REG_INVALID) &&

          !arr_exist(regs_write, write_count, op->mem.base)) {

        regs_write[write_count] =

          (uint16_t)op->mem.base;

        write_count++;

      }

    default:

      break;

    }

  }

  *regs_read_count = read_count;

  *regs_write_count = write_count;

}

#endif

void ARM_setup_op(cs_arm_op *op)

{

  memset(op, 0, sizeof(cs_arm_op));

  op->type = ARM_OP_INVALID;

  op->vector_index = -1;

  op->neon_lane = -1;

}

void ARM_init_cs_detail(MCInst *MI)

{

  if (detail_is_set(MI)) {

    unsigned int i;

    memset(get_detail(MI), 0,

           offsetof(cs_detail, arm) + sizeof(cs_arm));

    for (i = 0; i < ARR_SIZE(ARM_get_detail(MI)->operands); i++)

      ARM_setup_op(&ARM_get_detail(MI)->operands[i]);

    ARM_get_detail(MI)->cc = ARMCC_UNDEF;

    ARM_get_detail(MI)->vcc = ARMVCC_None;

  }

}

static uint64_t t_add_pc(MCInst *MI, uint64_t v)

{

  int32_t imm = (int32_t)v;

  if (ARM_rel_branch(MI->csh, MI->Opcode)) {

    uint32_t address;

    // only do this for relative branch

    if (MI->csh->mode & CS_MODE_THUMB) {

      address = (uint32_t)MI->address + 4;

      if (ARM_blx_to_arm_mode(MI->csh, MI->Opcode)) {

        // here need to align down to the nearest 4-byte address

#define _ALIGN_DOWN(v, align_width) ((v / align_width) * align_width)

        address = _ALIGN_DOWN(address, 4);

#undef _ALIGN_DOWN

      }

    } else {

      address = (uint32_t)MI->address + 8;

    }

    imm += address;

    return imm;

  }

  return v;

}

/// Transform a Qs register to its corresponding Ds + Offset register.

static uint64_t t_qpr_to_dpr_list(MCInst *MI, unsigned OpNum, uint8_t offset)

{

  uint64_t v = MCOperand_getReg(MCInst_getOperand(MI, OpNum));

  if (v >= ARM_REG_Q0 && v <= ARM_REG_Q15)

    return ARM_REG_D0 + offset + (v - ARM_REG_Q0) * 2;

  return v + offset;

}

static uint64_t t_mod_imm_rotate(uint64_t v)

{

  unsigned Bits = v & 0xFF;

  unsigned Rot = (v & 0xF00) >> 7;

  int32_t Rotated = ARM_AM_rotr32(Bits, Rot);

  return Rotated;

}

inline static uint64_t t_mod_imm_bits(uint64_t v)

{

  unsigned Bits = v & 0xFF;

  return Bits;

}

inline static uint64_t t_mod_imm_rot(uint64_t v)

{

  unsigned Rot = (v & 0xF00) >> 7;

  return Rot;

}

static uint64_t t_vmov_mod_imm(uint64_t v)

{

  unsigned EltBits;

  uint64_t Val = ARM_AM_decodeVMOVModImm(v, &EltBits);

  return Val;

}

/// Initializes or finishes a memory operand of Capstone (depending on \p

/// status). A memory operand in Capstone can be assembled by two LLVM operands.

/// E.g. the base register and the immediate disponent.

static void ARM_set_mem_access(MCInst *MI, bool status)

{

  if (!detail_is_set(MI))

    return;

  set_doing_mem(MI, status);

  if (status) {

    ARM_get_detail_op(MI, 0)->type = ARM_OP_MEM;

    ARM_get_detail_op(MI, 0)->mem.base = ARM_REG_INVALID;

    ARM_get_detail_op(MI, 0)->mem.index = ARM_REG_INVALID;

    ARM_get_detail_op(MI, 0)->mem.scale = 1;

    ARM_get_detail_op(MI, 0)->mem.disp = 0;

#ifndef CAPSTONE_DIET

    uint8_t access =

      map_get_op_access(MI, ARM_get_detail(MI)->op_count);

    ARM_get_detail_op(MI, 0)->access = access;

#endif

  } else {

    // done, select the next operand slot

    ARM_inc_op_count(MI);

  }

}

/// Fills cs_detail with operand shift information for the last added operand.

static void add_cs_detail_RegImmShift(MCInst *MI, ARM_AM_ShiftOpc ShOpc,

              unsigned ShImm)

{

  if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm))

    return;

  if (!detail_is_set(MI))

    return;

  if (doing_mem(MI))

    ARM_get_detail_op(MI, 0)->shift.type = (arm_shifter)ShOpc;

  else

    ARM_get_detail_op(MI, -1)->shift.type = (arm_shifter)ShOpc;

  if (ShOpc != ARM_AM_rrx) {

    if (doing_mem(MI))

      ARM_get_detail_op(MI, 0)->shift.value =

        translateShiftImm(ShImm);

    else

      ARM_get_detail_op(MI, -1)->shift.value =

        translateShiftImm(ShImm);

  }

}

/// Fills cs_detail with the data of the operand.

/// This function handles operands which's original printer function has no

/// specialities.

static void add_cs_detail_general(MCInst *MI, arm_op_group op_group,

          unsigned OpNum)

{

  if (!detail_is_set(MI))

    return;

  cs_op_type op_type = map_get_op_type(MI, OpNum);

  // Fill cs_detail

  switch (op_group) {

  default:

    printf("ERROR: Operand group %d not handled!\n", op_group);

    assert(0);

  case ARM_OP_GROUP_PredicateOperand:

  case ARM_OP_GROUP_MandatoryPredicateOperand:

  case ARM_OP_GROUP_MandatoryInvertedPredicateOperand:

  case ARM_OP_GROUP_MandatoryRestrictedPredicateOperand: {

    ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(

      MCInst_getOperand(MI, OpNum));

    if ((unsigned)CC == 15 &&

        op_group == ARM_OP_GROUP_PredicateOperand) {

      ARM_get_detail(MI)->cc = ARMCC_UNDEF;

      return;

    }

    if (CC == ARMCC_HS &&

        op_group ==

          ARM_OP_GROUP_MandatoryRestrictedPredicateOperand) {

      ARM_get_detail(MI)->cc = ARMCC_HS;

      return;

    }

    ARM_get_detail(MI)->cc = CC;

    if (CC != ARMCC_AL)

      map_add_implicit_read(MI, ARM_REG_CPSR);

    break;

  }

  case ARM_OP_GROUP_VPTPredicateOperand: {

    ARMVCC_VPTCodes VCC = (ARMVCC_VPTCodes)MCOperand_getImm(

      MCInst_getOperand(MI, OpNum));

    assert(VCC <= ARMVCC_Else);

    if (VCC != ARMVCC_None)

      ARM_get_detail(MI)->vcc = VCC;

    break;

  }

  case ARM_OP_GROUP_Operand:

    if (op_type == CS_OP_IMM) {

      if (doing_mem(MI)) {

        ARM_set_detail_op_mem(MI, OpNum, false, 0, 0,

                  MCInst_getOpVal(MI,

                      OpNum));

      } else {

        ARM_set_detail_op_imm(

          MI, OpNum, ARM_OP_IMM,

          t_add_pc(MI,

             MCInst_getOpVal(MI, OpNum)));

      }

    } else if (op_type == CS_OP_REG)

      if (doing_mem(MI)) {

        bool is_index_reg = map_get_op_type(MI, OpNum) &

                CS_OP_MEM;

        ARM_set_detail_op_mem(

          MI, OpNum, is_index_reg, 0, 0,

          MCInst_getOpVal(MI, OpNum));

      } else {

        ARM_set_detail_op_reg(

          MI, OpNum, MCInst_getOpVal(MI, OpNum));

      }

    else

      assert(0 && "Op type not handled.");

    break;

  case ARM_OP_GROUP_PImmediate:

    ARM_set_detail_op_imm(MI, OpNum, ARM_OP_PIMM,

              MCInst_getOpVal(MI, OpNum));

    break;

  case ARM_OP_GROUP_CImmediate:

    ARM_set_detail_op_imm(MI, OpNum, ARM_OP_CIMM,