/src/capstonenext/arch/PowerPC/PPCMCTargetDesc.h

Source (jump to first uncovered line)
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/*    Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */

/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */

/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */

/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */

//===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file provides PowerPC specific target descriptions.
//
//===----------------------------------------------------------------------===//

#ifndef CS_PPC_MCTARGETDESC_H
#define CS_PPC_MCTARGETDESC_H

// GCC #defines PPC on Linux but we use it as our namespace name
#undef PPC

#include <capstone/platform.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "../../LEB128.h"
#include "../../MathExtras.h"
#include "../../MCInst.h"
#include "../../MCInstrDesc.h"
#include "../../MCRegisterInfo.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b

/// Returns true iff Val consists of one contiguous run of 1s with any number of
/// 0s on either side.  The 1s are allowed to wrap from LSB to MSB, so
/// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.  0x0F0F0000 is not,
/// since all 1s are not contiguous.
static inline bool isRunOfOnes(unsigned Val, unsigned *MB, unsigned *ME)
{
  if (!Val)
    return false;

  if (isShiftedMask_32(Val)) {
    // look for the first non-zero bit
    *MB = countLeadingZeros(Val);
    // look for the first zero bit after the run of ones
    *ME = countLeadingZeros((Val - 1) ^ Val);
    return true;
  } else {
    Val = ~Val; // invert mask
    if (isShiftedMask_32(Val)) {
      // effectively look for the first zero bit
      *ME = countLeadingZeros(Val) - 1;
      // effectively look for the first one bit after the run of zeros
      *MB = countLeadingZeros((Val - 1) ^ Val) + 1;
      return true;
    }
  }
  // no run present
  return false;
}

static inline bool isRunOfOnes64(uint64_t Val, unsigned *MB, unsigned *ME)
{
  if (!Val)
    return false;

  if (isShiftedMask_64(Val)) {
    // look for the first non-zero bit
    *MB = countLeadingZeros(Val);
    // look for the first zero bit after the run of ones
    *ME = countLeadingZeros((Val - 1) ^ Val);
    return true;
  } else {
    Val = ~Val; // invert mask
    if (isShiftedMask_64(Val)) {
      // effectively look for the first zero bit
      *ME = countLeadingZeros(Val) - 1;
      // effectively look for the first one bit after the run of zeros
      *MB = countLeadingZeros((Val - 1) ^ Val) + 1;
      return true;
    }
  }
  // no run present
  return false;
}

// end namespace llvm

// Generated files will use "namespace PPC". To avoid symbol clash,
// undefine PPC here. PPC may be predefined on some hosts.
#undef PPC

// Defines symbolic names for PowerPC registers.  This defines a mapping from
// register name to register number.
//
#define GET_REGINFO_ENUM
#include "PPCGenRegisterInfo.inc"

// Defines symbolic names for the PowerPC instructions.
//
#define GET_INSTRINFO_ENUM
#define GET_INSTRINFO_SCHED_ENUM
#define GET_INSTRINFO_MC_HELPER_DECLS
#define GET_INSTRINFO_MC_DESC
#include "PPCGenInstrInfo.inc"

#define GET_SUBTARGETINFO_ENUM
#include "PPCGenSubtargetInfo.inc"

#define PPC_REGS0_7(X) \
  { \
    X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
  }

#define PPC_REGS0_31(X) \
  { \
    X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
      X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
      X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
      X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
  }

#define PPC_REGS0_63(X) \
  { \
    X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
      X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
      X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
      X##24, X##25, X##26, X##27, X##28, X##29, X##30, \
      X##31, X##32, X##33, X##34, X##35, X##36, X##37, \
      X##38, X##39, X##40, X##41, X##42, X##43, X##44, \
      X##45, X##46, X##47, X##48, X##49, X##50, X##51, \
      X##52, X##53, X##54, X##55, X##56, X##57, X##58, \
      X##59, X##60, X##61, X##62, X##63 \
  }

#define PPC_REGS_NO0_31(Z, X) \
  { \
    Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
      X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
      X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
      X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
  }

#define PPC_REGS_LO_HI(LO, HI) \
  { \
    LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, \
      LO##9, LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, \
      LO##16, LO##17, LO##18, LO##19, LO##20, LO##21, \
      LO##22, LO##23, LO##24, LO##25, LO##26, LO##27, \
      LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
      HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, \
      HI##10, HI##11, HI##12, HI##13, HI##14, HI##15, \
      HI##16, HI##17, HI##18, HI##19, HI##20, HI##21, \
      HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
      HI##28, HI##29, HI##30, HI##31 \
  }

#define PPC_REGS0_7(X) \
  { \
    X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
  }

#define PPC_REGS0_3(X) \
  { \
    X##0, X##1, X##2, X##3 \
  }

#define DEFINE_PPC_REGCLASSES \
  static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC_R); \
  static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC_X); \
  static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC_F); \
  static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC_VSRp); \
  static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC_S); \
  static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC_VF); \
  static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC_V); \
  static const MCPhysReg RRegsNoR0[32] = \
    PPC_REGS_NO0_31(PPC_ZERO, PPC_R); \
  static const MCPhysReg XRegsNoX0[32] = \
    PPC_REGS_NO0_31(PPC_ZERO8, PPC_X); \
  static const MCPhysReg VSRegs[64] = PPC_REGS_LO_HI(PPC_VSL, PPC_V); \
  static const MCPhysReg VSFRegs[64] = PPC_REGS_LO_HI(PPC_F, PPC_VF); \
  static const MCPhysReg VSSRegs[64] = PPC_REGS_LO_HI(PPC_F, PPC_VF); \
  static const MCPhysReg CRBITRegs[32] = { \
    PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN, PPC_CR1LT, \
    PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, PPC_CR2LT, PPC_CR2GT, \
    PPC_CR2EQ, PPC_CR2UN, PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, \
    PPC_CR3UN, PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, \
    PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, PPC_CR6LT, \
    PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, PPC_CR7LT, PPC_CR7GT, \
    PPC_CR7EQ, PPC_CR7UN \
  }; \
  static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC_CR); \
  static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC_ACC); \
  static const MCPhysReg WACCRegs[8] = PPC_REGS0_7(PPC_WACC); \
  static const MCPhysReg WACC_HIRegs[8] = PPC_REGS0_7(PPC_WACC_HI); \
  static const MCPhysReg DMRROWpRegs[32] = PPC_REGS0_31(PPC_DMRROWp); \
  static const MCPhysReg DMRROWRegs[64] = PPC_REGS0_63(PPC_DMRROW); \
  static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC_DMR); \
  static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC_DMRp);

static const MCPhysReg QFRegs[] = {
  PPC_QF0,  PPC_QF1,  PPC_QF2,  PPC_QF3,  PPC_QF4,  PPC_QF5,  PPC_QF6,
  PPC_QF7,  PPC_QF8,  PPC_QF9,  PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13,
  PPC_QF14, PPC_QF15, PPC_QF16, PPC_QF17, PPC_QF18, PPC_QF19, PPC_QF20,
  PPC_QF21, PPC_QF22, PPC_QF23, PPC_QF24, PPC_QF25, PPC_QF26, PPC_QF27,
  PPC_QF28, PPC_QF29, PPC_QF30, PPC_QF31
};

#endif // CS_PPC_MCTARGETDESC_H

Coverage Report

Created: 2023-09-25 06:24

Line	Count	Source (jump to first uncovered line)
1		/* Capstone Disassembly Engine, http://www.capstone-engine.org */
2		/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
3		/* Rot127 <unisono@quyllur.org> 2022-2023 */
4		/* Automatically translated source file from LLVM. */
5
6		/* LLVM-commit: <commit> */
7		/* LLVM-tag: <tag> */
8
9		/* Only small edits allowed. */
10		/* For multiple similar edits, please create a Patch for the translator. */
11
12		/* Capstone's C++ file translator: */
13		/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
14
15		//===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------- C++ --===//
16		//
17		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
18		// See https://llvm.org/LICENSE.txt for license information.
19		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
20		//
21		//===----------------------------------------------------------------------===//
22		//
23		// This file provides PowerPC specific target descriptions.
24		//
25		//===----------------------------------------------------------------------===//
26
27		#ifndef CS_PPC_MCTARGETDESC_H
28		#define CS_PPC_MCTARGETDESC_H
29
30		// GCC #defines PPC on Linux but we use it as our namespace name
31		#undef PPC
32
33		#include <capstone/platform.h>
34		#include <stdio.h>
35		#include <stdlib.h>
36		#include <string.h>
37
38		#include "../../LEB128.h"
39		#include "../../MathExtras.h"
40		#include "../../MCInst.h"
41		#include "../../MCInstrDesc.h"
42		#include "../../MCRegisterInfo.h"
43		#define CONCAT(a, b) CONCAT_(a, b)
44		#define CONCAT_(a, b) a##_##b
45
46		/// Returns true iff Val consists of one contiguous run of 1s with any number of
47		/// 0s on either side. The 1s are allowed to wrap from LSB to MSB, so
48		/// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is not,
49		/// since all 1s are not contiguous.
50		static inline bool isRunOfOnes(unsigned Val, unsigned MB, unsigned ME)
51	0	{
52	0	if (!Val)
53	0	return false;
54	0
55	0	if (isShiftedMask_32(Val)) {
56	0	// look for the first non-zero bit
57	0	*MB = countLeadingZeros(Val);
58	0	// look for the first zero bit after the run of ones
59	0	*ME = countLeadingZeros((Val - 1) ^ Val);
60	0	return true;
61	0	} else {
62	0	Val = ~Val; // invert mask
63	0	if (isShiftedMask_32(Val)) {
64	0	// effectively look for the first zero bit
65	0	*ME = countLeadingZeros(Val) - 1;
66	0	// effectively look for the first one bit after the run of zeros
67	0	*MB = countLeadingZeros((Val - 1) ^ Val) + 1;
68	0	return true;
69	0	}
70	0	}
71	0	// no run present
72	0	return false;
73	0	} Unexecuted instantiation: PPCModule.c:isRunOfOnes Unexecuted instantiation: PPCMapping.c:isRunOfOnes Unexecuted instantiation: PPCDisassembler.c:isRunOfOnes Unexecuted instantiation: PPCInstPrinter.c:isRunOfOnes
74
75		static inline bool isRunOfOnes64(uint64_t Val, unsigned MB, unsigned ME)
76	0	{
77	0	if (!Val)
78	0	return false;
79	0
80	0	if (isShiftedMask_64(Val)) {
81	0	// look for the first non-zero bit
82	0	*MB = countLeadingZeros(Val);
83	0	// look for the first zero bit after the run of ones
84	0	*ME = countLeadingZeros((Val - 1) ^ Val);
85	0	return true;
86	0	} else {
87	0	Val = ~Val; // invert mask
88	0	if (isShiftedMask_64(Val)) {
89	0	// effectively look for the first zero bit
90	0	*ME = countLeadingZeros(Val) - 1;
91	0	// effectively look for the first one bit after the run of zeros
92	0	*MB = countLeadingZeros((Val - 1) ^ Val) + 1;
93	0	return true;
94	0	}
95	0	}
96	0	// no run present
97	0	return false;
98	0	} Unexecuted instantiation: PPCModule.c:isRunOfOnes64 Unexecuted instantiation: PPCMapping.c:isRunOfOnes64 Unexecuted instantiation: PPCDisassembler.c:isRunOfOnes64 Unexecuted instantiation: PPCInstPrinter.c:isRunOfOnes64
99
100		// end namespace llvm
101
102		// Generated files will use "namespace PPC". To avoid symbol clash,
103		// undefine PPC here. PPC may be predefined on some hosts.
104		#undef PPC
105
106		// Defines symbolic names for PowerPC registers. This defines a mapping from
107		// register name to register number.
108		//
109		#define GET_REGINFO_ENUM
110		#include "PPCGenRegisterInfo.inc"
111
112		// Defines symbolic names for the PowerPC instructions.
113		//
114		#define GET_INSTRINFO_ENUM
115		#define GET_INSTRINFO_SCHED_ENUM
116		#define GET_INSTRINFO_MC_HELPER_DECLS
117		#define GET_INSTRINFO_MC_DESC
118		#include "PPCGenInstrInfo.inc"
119
120		#define GET_SUBTARGETINFO_ENUM
121		#include "PPCGenSubtargetInfo.inc"
122
123		#define PPC_REGS0_7(X) \
124		{ \
125		X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
126		}
127
128		#define PPC_REGS0_31(X) \
129		{ \
130		X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
131		X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
132		X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
133		X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
134		}
135
136		#define PPC_REGS0_63(X) \
137		{ \
138		X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
139		X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
140		X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
141		X##24, X##25, X##26, X##27, X##28, X##29, X##30, \
142		X##31, X##32, X##33, X##34, X##35, X##36, X##37, \
143		X##38, X##39, X##40, X##41, X##42, X##43, X##44, \
144		X##45, X##46, X##47, X##48, X##49, X##50, X##51, \
145		X##52, X##53, X##54, X##55, X##56, X##57, X##58, \
146		X##59, X##60, X##61, X##62, X##63 \
147		}
148
149		#define PPC_REGS_NO0_31(Z, X) \
150		{ \
151		Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, \
152		X##10, X##11, X##12, X##13, X##14, X##15, X##16, \
153		X##17, X##18, X##19, X##20, X##21, X##22, X##23, \
154		X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
155		}
156
157		#define PPC_REGS_LO_HI(LO, HI) \
158		{ \
159		LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, \
160		LO##9, LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, \
161		LO##16, LO##17, LO##18, LO##19, LO##20, LO##21, \
162		LO##22, LO##23, LO##24, LO##25, LO##26, LO##27, \
163		LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
164		HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, \
165		HI##10, HI##11, HI##12, HI##13, HI##14, HI##15, \
166		HI##16, HI##17, HI##18, HI##19, HI##20, HI##21, \
167		HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
168		HI##28, HI##29, HI##30, HI##31 \
169		}
170
171		#define PPC_REGS0_7(X) \
172		{ \
173		X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
174		}
175
176		#define PPC_REGS0_3(X) \
177		{ \
178		X##0, X##1, X##2, X##3 \
179		}
180
181		#define DEFINE_PPC_REGCLASSES \
182		static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC_R); \
183		static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC_X); \
184		static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC_F); \
185		static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC_VSRp); \
186		static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC_S); \
187		static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC_VF); \
188		static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC_V); \
189		static const MCPhysReg RRegsNoR0[32] = \
190		PPC_REGS_NO0_31(PPC_ZERO, PPC_R); \
191		static const MCPhysReg XRegsNoX0[32] = \
192		PPC_REGS_NO0_31(PPC_ZERO8, PPC_X); \
193		static const MCPhysReg VSRegs[64] = PPC_REGS_LO_HI(PPC_VSL, PPC_V); \
194		static const MCPhysReg VSFRegs[64] = PPC_REGS_LO_HI(PPC_F, PPC_VF); \
195		static const MCPhysReg VSSRegs[64] = PPC_REGS_LO_HI(PPC_F, PPC_VF); \
196		static const MCPhysReg CRBITRegs[32] = { \
197		PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN, PPC_CR1LT, \
198		PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, PPC_CR2LT, PPC_CR2GT, \
199		PPC_CR2EQ, PPC_CR2UN, PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, \
200		PPC_CR3UN, PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, \
201		PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, PPC_CR6LT, \
202		PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, PPC_CR7LT, PPC_CR7GT, \
203		PPC_CR7EQ, PPC_CR7UN \
204		}; \
205		static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC_CR); \
206		static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC_ACC); \
207		static const MCPhysReg WACCRegs[8] = PPC_REGS0_7(PPC_WACC); \
208		static const MCPhysReg WACC_HIRegs[8] = PPC_REGS0_7(PPC_WACC_HI); \
209		static const MCPhysReg DMRROWpRegs[32] = PPC_REGS0_31(PPC_DMRROWp); \
210		static const MCPhysReg DMRROWRegs[64] = PPC_REGS0_63(PPC_DMRROW); \
211		static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC_DMR); \
212		static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC_DMRp);
213
214		static const MCPhysReg QFRegs[] = {
215		PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6,
216		PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13,
217		PPC_QF14, PPC_QF15, PPC_QF16, PPC_QF17, PPC_QF18, PPC_QF19, PPC_QF20,
218		PPC_QF21, PPC_QF22, PPC_QF23, PPC_QF24, PPC_QF25, PPC_QF26, PPC_QF27,
219		PPC_QF28, PPC_QF29, PPC_QF30, PPC_QF31
220		};
221
222		#endif // CS_PPC_MCTARGETDESC_H