Coverage Report

Created: 2023-09-25 06:24

/src/capstonenext/arch/RISCV/RISCVBaseInfo.h
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//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone enum definitions for the RISCV target
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// useful for the compiler back-end and the MC libraries.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CS_RISCVBASEINFO_H
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#define CS_RISCVBASEINFO_H
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#include "../../cs_priv.h"
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//#include "RISCVMCTargetDesc.h"
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// RISCVII - This namespace holds all of the target specific flags that
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// instruction info tracks. All definitions must match RISCVInstrFormats.td.
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enum {
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  IRISCVII_InstFormatPseudo = 0,
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    IRISCVII_InstFormatR = 1,
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    IRISCVII_InstFormatR4 = 2,
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    IRISCVII_InstFormatI = 3,
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    IRISCVII_InstFormatS = 4,
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    IRISCVII_InstFormatB = 5,
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    IRISCVII_InstFormatU = 6,
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    IRISCVII_InstFormatJ = 7,
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    IRISCVII_InstFormatCR = 8,
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    IRISCVII_InstFormatCI = 9,
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    IRISCVII_InstFormatCSS = 10,
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    IRISCVII_InstFormatCIW = 11,
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  IRISCVII_InstFormatCL = 12,
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    IRISCVII_InstFormatCS = 13,
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    IRISCVII_InstFormatCA = 14,
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    IRISCVII_InstFormatCB = 15,
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    IRISCVII_InstFormatCJ = 16,
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    IRISCVII_InstFormatOther = 17,
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    IRISCVII_InstFormatMask = 31  
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};
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enum {
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  RISCVII_MO_None,
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  RISCVII_MO_LO,
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  RISCVII_MO_HI,
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  RISCVII_MO_PCREL_HI,
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};
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// Describes the predecessor/successor bits used in the FENCE instruction.
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enum FenceField {
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    RISCVFenceField_I = 8,
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    RISCVFenceField_O = 4,
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  RISCVFenceField_R = 2,
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    RISCVFenceField_W = 1
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};
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// Describes the supported floating point rounding mode encodings.
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enum RoundingMode {
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    RISCVFPRndMode_RNE = 0,
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    RISCVFPRndMode_RTZ = 1,
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    RISCVFPRndMode_RDN = 2,
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    RISCVFPRndMode_RUP = 3,
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    RISCVFPRndMode_RMM = 4,
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    RISCVFPRndMode_DYN = 7,
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    RISCVFPRndMode_Invalid
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};
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inline static const char *roundingModeToString(enum RoundingMode RndMode) 
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{
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    switch (RndMode) {
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    default:
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        CS_ASSERT(0 && "Unknown floating point rounding mode");
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    case RISCVFPRndMode_RNE:
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        return "rne";
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    case RISCVFPRndMode_RTZ:
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        return "rtz";
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    case RISCVFPRndMode_RDN:
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        return "rdn";
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    case RISCVFPRndMode_RUP:
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        return "rup";
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    case RISCVFPRndMode_RMM:
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        return "rmm";
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0
    case RISCVFPRndMode_DYN:
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        return "dyn";
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    }
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}
Unexecuted instantiation: RISCVDisassembler.c:roundingModeToString
RISCVInstPrinter.c:roundingModeToString
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{
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    switch (RndMode) {
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    default:
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        CS_ASSERT(0 && "Unknown floating point rounding mode");
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    case RISCVFPRndMode_RNE:
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        return "rne";
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    case RISCVFPRndMode_RTZ:
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        return "rtz";
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    case RISCVFPRndMode_RDN:
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        return "rdn";
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    case RISCVFPRndMode_RUP:
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        return "rup";
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    case RISCVFPRndMode_RMM:
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        return "rmm";
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    case RISCVFPRndMode_DYN:
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        return "dyn";
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    }
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}
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inline static bool RISCVFPRndMode_isValidRoundingMode(unsigned Mode) 
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{
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    switch (Mode) {
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    default:
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        return false;
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    case RISCVFPRndMode_RNE:
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    case RISCVFPRndMode_RTZ:
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    case RISCVFPRndMode_RDN:
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    case RISCVFPRndMode_RUP:
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    case RISCVFPRndMode_RMM:
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    case RISCVFPRndMode_DYN:
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        return true;
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    }
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}
RISCVDisassembler.c:RISCVFPRndMode_isValidRoundingMode
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{
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    switch (Mode) {
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    default:
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        return false;
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    case RISCVFPRndMode_RNE:
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    case RISCVFPRndMode_RTZ:
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    case RISCVFPRndMode_RDN:
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    case RISCVFPRndMode_RUP:
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    case RISCVFPRndMode_RMM:
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    case RISCVFPRndMode_DYN:
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        return true;
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    }
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}
Unexecuted instantiation: RISCVInstPrinter.c:RISCVFPRndMode_isValidRoundingMode
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#endif