Coverage Report

Created: 2023-09-25 06:24

/src/capstonenext/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|*Assembly Writer Source Fragment                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
15
16
/// printInstruction - This method is automatically generated by tablegen
17
/// from the instruction set description.
18
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19
45.1k
{
20
45.1k
  static const uint32_t OpInfo[] = {
21
45.1k
    0U, // PHI
22
45.1k
    0U, // INLINEASM
23
45.1k
    0U, // CFI_INSTRUCTION
24
45.1k
    0U, // EH_LABEL
25
45.1k
    0U, // GC_LABEL
26
45.1k
    0U, // KILL
27
45.1k
    0U, // EXTRACT_SUBREG
28
45.1k
    0U, // INSERT_SUBREG
29
45.1k
    0U, // IMPLICIT_DEF
30
45.1k
    0U, // SUBREG_TO_REG
31
45.1k
    0U, // COPY_TO_REGCLASS
32
45.1k
    2452U,  // DBG_VALUE
33
45.1k
    0U, // REG_SEQUENCE
34
45.1k
    0U, // COPY
35
45.1k
    2445U,  // BUNDLE
36
45.1k
    2462U,  // LIFETIME_START
37
45.1k
    2432U,  // LIFETIME_END
38
45.1k
    0U, // STACKMAP
39
45.1k
    0U, // PATCHPOINT
40
45.1k
    0U, // LOAD_STACK_GUARD
41
45.1k
    0U, // STATEPOINT
42
45.1k
    0U, // FRAME_ALLOC
43
45.1k
    4688U,  // ADDCCri
44
45.1k
    4688U,  // ADDCCrr
45
45.1k
    5925U,  // ADDCri
46
45.1k
    5925U,  // ADDCrr
47
45.1k
    4772U,  // ADDEri
48
45.1k
    4772U,  // ADDErr
49
45.1k
    4786U,  // ADDXC
50
45.1k
    4678U,  // ADDXCCC
51
45.1k
    4808U,  // ADDXri
52
45.1k
    4808U,  // ADDXrr
53
45.1k
    4808U,  // ADDri
54
45.1k
    4808U,  // ADDrr
55
45.1k
    74166U, // ADJCALLSTACKDOWN
56
45.1k
    74185U, // ADJCALLSTACKUP
57
45.1k
    5497U,  // ALIGNADDR
58
45.1k
    5127U,  // ALIGNADDRL
59
45.1k
    4695U,  // ANDCCri
60
45.1k
    4695U,  // ANDCCrr
61
45.1k
    4718U,  // ANDNCCri
62
45.1k
    4718U,  // ANDNCCrr
63
45.1k
    5182U,  // ANDNri
64
45.1k
    5182U,  // ANDNrr
65
45.1k
    5182U,  // ANDXNrr
66
45.1k
    4876U,  // ANDXri
67
45.1k
    4876U,  // ANDXrr
68
45.1k
    4876U,  // ANDri
69
45.1k
    4876U,  // ANDrr
70
45.1k
    4502U,  // ARRAY16
71
45.1k
    4255U,  // ARRAY32
72
45.1k
    4526U,  // ARRAY8
73
45.1k
    0U, // ATOMIC_LOAD_ADD_32
74
45.1k
    0U, // ATOMIC_LOAD_ADD_64
75
45.1k
    0U, // ATOMIC_LOAD_AND_32
76
45.1k
    0U, // ATOMIC_LOAD_AND_64
77
45.1k
    0U, // ATOMIC_LOAD_MAX_32
78
45.1k
    0U, // ATOMIC_LOAD_MAX_64
79
45.1k
    0U, // ATOMIC_LOAD_MIN_32
80
45.1k
    0U, // ATOMIC_LOAD_MIN_64
81
45.1k
    0U, // ATOMIC_LOAD_NAND_32
82
45.1k
    0U, // ATOMIC_LOAD_NAND_64
83
45.1k
    0U, // ATOMIC_LOAD_OR_32
84
45.1k
    0U, // ATOMIC_LOAD_OR_64
85
45.1k
    0U, // ATOMIC_LOAD_SUB_32
86
45.1k
    0U, // ATOMIC_LOAD_SUB_64
87
45.1k
    0U, // ATOMIC_LOAD_UMAX_32
88
45.1k
    0U, // ATOMIC_LOAD_UMAX_64
89
45.1k
    0U, // ATOMIC_LOAD_UMIN_32
90
45.1k
    0U, // ATOMIC_LOAD_UMIN_64
91
45.1k
    0U, // ATOMIC_LOAD_XOR_32
92
45.1k
    0U, // ATOMIC_LOAD_XOR_64
93
45.1k
    0U, // ATOMIC_SWAP_64
94
45.1k
    74271U, // BA
95
45.1k
    1194492U, // BCOND
96
45.1k
    1260028U, // BCONDA
97
45.1k
    17659U, // BINDri
98
45.1k
    17659U, // BINDrr
99
45.1k
    5065U,  // BMASK
100
45.1k
    145915U,  // BPFCC
101
45.1k
    211451U,  // BPFCCA
102
45.1k
    276987U,  // BPFCCANT
103
45.1k
    342523U,  // BPFCCNT
104
45.1k
    2106465U, // BPGEZapn
105
45.1k
    2105838U, // BPGEZapt
106
45.1k
    2106532U, // BPGEZnapn
107
45.1k
    2107288U, // BPGEZnapt
108
45.1k
    2106489U, // BPGZapn
109
45.1k
    2105856U, // BPGZapt
110
45.1k
    2106552U, // BPGZnapn
111
45.1k
    2107384U, // BPGZnapt
112
45.1k
    1456636U, // BPICC
113
45.1k
    473596U,  // BPICCA
114
45.1k
    539132U,  // BPICCANT
115
45.1k
    604668U,  // BPICCNT
116
45.1k
    2106477U, // BPLEZapn
117
45.1k
    2105847U, // BPLEZapt
118
45.1k
    2106542U, // BPLEZnapn
119
45.1k
    2107337U, // BPLEZnapt
120
45.1k
    2106500U, // BPLZapn
121
45.1k
    2105864U, // BPLZapt
122
45.1k
    2106561U, // BPLZnapn
123
45.1k
    2107428U, // BPLZnapt
124
45.1k
    2106511U, // BPNZapn
125
45.1k
    2105872U, // BPNZapt
126
45.1k
    2106570U, // BPNZnapn
127
45.1k
    2107472U, // BPNZnapt
128
45.1k
    1718780U, // BPXCC
129
45.1k
    735740U,  // BPXCCA
130
45.1k
    801276U,  // BPXCCANT
131
45.1k
    866812U,  // BPXCCNT
132
45.1k
    2106522U, // BPZapn
133
45.1k
    2105880U, // BPZapt
134
45.1k
    2106579U, // BPZnapn
135
45.1k
    2107505U, // BPZnapt
136
45.1k
    4983U,  // BSHUFFLE
137
45.1k
    74742U, // CALL
138
45.1k
    17398U, // CALLri
139
45.1k
    17398U, // CALLrr
140
45.1k
    924148U,  // CASXrr
141
45.1k
    924129U,  // CASrr
142
45.1k
    74001U, // CMASK16
143
45.1k
    73833U, // CMASK32
144
45.1k
    74150U, // CMASK8
145
45.1k
    2106607U, // CMPri
146
45.1k
    2106607U, // CMPrr
147
45.1k
    4332U,  // EDGE16
148
45.1k
    5081U,  // EDGE16L
149
45.1k
    5198U,  // EDGE16LN
150
45.1k
    5165U,  // EDGE16N
151
45.1k
    4164U,  // EDGE32
152
45.1k
    5072U,  // EDGE32L
153
45.1k
    5188U,  // EDGE32LN
154
45.1k
    5156U,  // EDGE32N
155
45.1k
    4511U,  // EDGE8
156
45.1k
    5090U,  // EDGE8L
157
45.1k
    5208U,  // EDGE8LN
158
45.1k
    5174U,  // EDGE8N
159
45.1k
    1053516U, // FABSD
160
45.1k
    1054031U, // FABSQ
161
45.1k
    1054376U, // FABSS
162
45.1k
    4813U,  // FADDD
163
45.1k
    5383U,  // FADDQ
164
45.1k
    5645U,  // FADDS
165
45.1k
    4648U,  // FALIGNADATA
166
45.1k
    4875U,  // FAND
167
45.1k
    4112U,  // FANDNOT1
168
45.1k
    5544U,  // FANDNOT1S
169
45.1k
    4271U,  // FANDNOT2
170
45.1k
    5591U,  // FANDNOT2S
171
45.1k
    5677U,  // FANDS
172
45.1k
    1194491U, // FBCOND
173
45.1k
    1260027U, // FBCONDA
174
45.1k
    4394U,  // FCHKSM16
175
45.1k
    2106173U, // FCMPD
176
45.1k
    4413U,  // FCMPEQ16
177
45.1k
    4226U,  // FCMPEQ32
178
45.1k
    4432U,  // FCMPGT16
179
45.1k
    4245U,  // FCMPGT32
180
45.1k
    4340U,  // FCMPLE16
181
45.1k
    4172U,  // FCMPLE32
182
45.1k
    4350U,  // FCMPNE16
183
45.1k
    4182U,  // FCMPNE32
184
45.1k
    2106696U, // FCMPQ
185
45.1k
    2107005U, // FCMPS
186
45.1k
    4960U,  // FDIVD
187
45.1k
    5475U,  // FDIVQ
188
45.1k
    5815U,  // FDIVS
189
45.1k
    5405U,  // FDMULQ
190
45.1k
    1053620U, // FDTOI
191
45.1k
    1053996U, // FDTOQ
192
45.1k
    1054305U, // FDTOS
193
45.1k
    1054536U, // FDTOX
194
45.1k
    1053464U, // FEXPAND
195
45.1k
    4820U,  // FHADDD
196
45.1k
    5652U,  // FHADDS
197
45.1k
    4800U,  // FHSUBD
198
45.1k
    5637U,  // FHSUBS
199
45.1k
    1053473U, // FITOD
200
45.1k
    1054003U, // FITOQ
201
45.1k
    1054312U, // FITOS
202
45.1k
    6300484U, // FLCMPD
203
45.1k
    6301316U, // FLCMPS
204
45.1k
    2606U,  // FLUSHW
205
45.1k
    4404U,  // FMEAN16
206
45.1k
    1053543U, // FMOVD
207
45.1k
    1006078U, // FMOVD_FCC
208
45.1k
    23484926U,  // FMOVD_ICC
209
45.1k
    23747070U,  // FMOVD_XCC
210
45.1k
    1054058U, // FMOVQ
211
45.1k
    1006102U, // FMOVQ_FCC
212
45.1k
    23484950U,  // FMOVQ_ICC
213
45.1k
    23747094U,  // FMOVQ_XCC
214
45.1k
    6018U,  // FMOVRGEZD
215
45.1k
    6029U,  // FMOVRGEZQ
216
45.1k
    6056U,  // FMOVRGEZS
217
45.1k
    6116U,  // FMOVRGZD
218
45.1k
    6126U,  // FMOVRGZQ
219
45.1k
    6150U,  // FMOVRGZS
220
45.1k
    6067U,  // FMOVRLEZD
221
45.1k
    6078U,  // FMOVRLEZQ
222
45.1k
    6105U,  // FMOVRLEZS
223
45.1k
    6160U,  // FMOVRLZD
224
45.1k
    6170U,  // FMOVRLZQ
225
45.1k
    6194U,  // FMOVRLZS
226
45.1k
    6204U,  // FMOVRNZD
227
45.1k
    6214U,  // FMOVRNZQ
228
45.1k
    6238U,  // FMOVRNZS
229
45.1k
    6009U,  // FMOVRZD
230
45.1k
    6248U,  // FMOVRZQ
231
45.1k
    6269U,  // FMOVRZS
232
45.1k
    1054398U, // FMOVS
233
45.1k
    1006114U, // FMOVS_FCC
234
45.1k
    23484962U,  // FMOVS_ICC
235
45.1k
    23747106U,  // FMOVS_XCC
236
45.1k
    4490U,  // FMUL8SUX16
237
45.1k
    4465U,  // FMUL8ULX16
238
45.1k
    4442U,  // FMUL8X16
239
45.1k
    5098U,  // FMUL8X16AL
240
45.1k
    5849U,  // FMUL8X16AU
241
45.1k
    4860U,  // FMULD
242
45.1k
    4477U,  // FMULD8SUX16
243
45.1k
    4452U,  // FMULD8ULX16
244
45.1k
    5413U,  // FMULQ
245
45.1k
    5714U,  // FMULS
246
45.1k
    4837U,  // FNADDD
247
45.1k
    5669U,  // FNADDS
248
45.1k
    4881U,  // FNAND
249
45.1k
    5684U,  // FNANDS
250
45.1k
    1053429U, // FNEGD
251
45.1k
    1053974U, // FNEGQ
252
45.1k
    1054283U, // FNEGS
253
45.1k
    4828U,  // FNHADDD
254
45.1k
    5660U,  // FNHADDS
255
45.1k
    4828U,  // FNMULD
256
45.1k
    5660U,  // FNMULS
257
45.1k
    5513U,  // FNOR
258
45.1k
    5778U,  // FNORS
259
45.1k
    1052698U, // FNOT1
260
45.1k
    1054131U, // FNOT1S
261
45.1k
    1052857U, // FNOT2
262
45.1k
    1054178U, // FNOT2S
263
45.1k
    5660U,  // FNSMULD
264
45.1k
    74625U, // FONE
265
45.1k
    75324U, // FONES
266
45.1k
    5508U,  // FOR
267
45.1k
    4129U,  // FORNOT1
268
45.1k
    5563U,  // FORNOT1S
269
45.1k
    4288U,  // FORNOT2
270
45.1k
    5610U,  // FORNOT2S
271
45.1k
    5772U,  // FORS
272
45.1k
    1052936U, // FPACK16
273
45.1k
    4192U,  // FPACK32
274
45.1k
    1054507U, // FPACKFIX
275
45.1k
    4323U,  // FPADD16
276
45.1k
    5620U,  // FPADD16S
277
45.1k
    4155U,  // FPADD32
278
45.1k
    5573U,  // FPADD32S
279
45.1k
    4297U,  // FPADD64
280
45.1k
    4974U,  // FPMERGE
281
45.1k
    4314U,  // FPSUB16
282
45.1k
    4580U,  // FPSUB16S
283
45.1k
    4146U,  // FPSUB32
284
45.1k
    4570U,  // FPSUB32S
285
45.1k
    1053480U, // FQTOD
286
45.1k
    1053627U, // FQTOI
287
45.1k
    1054319U, // FQTOS
288
45.1k
    1054552U, // FQTOX
289
45.1k
    4423U,  // FSLAS16
290
45.1k
    4236U,  // FSLAS32
291
45.1k
    4378U,  // FSLL16
292
45.1k
    4210U,  // FSLL32
293
45.1k
    4867U,  // FSMULD
294
45.1k
    1053523U, // FSQRTD
295
45.1k
    1054038U, // FSQRTQ
296
45.1k
    1054383U, // FSQRTS
297
45.1k
    4306U,  // FSRA16
298
45.1k
    4138U,  // FSRA32
299
45.1k
    1052681U, // FSRC1
300
45.1k
    1054112U, // FSRC1S
301
45.1k
    1052840U, // FSRC2
302
45.1k
    1054159U, // FSRC2S
303
45.1k
    4386U,  // FSRL16
304
45.1k
    4218U,  // FSRL32
305
45.1k
    1053487U, // FSTOD
306
45.1k
    1053634U, // FSTOI
307
45.1k
    1054010U, // FSTOQ
308
45.1k
    1054559U, // FSTOX
309
45.1k
    4793U,  // FSUBD
310
45.1k
    5376U,  // FSUBQ
311
45.1k
    5630U,  // FSUBS
312
45.1k
    5519U,  // FXNOR
313
45.1k
    5785U,  // FXNORS
314
45.1k
    5526U,  // FXOR
315
45.1k
    5793U,  // FXORS
316
45.1k
    1053494U, // FXTOD
317
45.1k
    1054017U, // FXTOQ
318
45.1k
    1054326U, // FXTOS
319
45.1k
    74984U, // FZERO
320
45.1k
    75353U, // FZEROS
321
45.1k
    24584U, // GETPCX
322
45.1k
    1078273U, // JMPLri
323
45.1k
    1078273U, // JMPLrr
324
45.1k
    1997243U, // LDDFri
325
45.1k
    1997243U, // LDDFrr
326
45.1k
    1997249U, // LDFri
327
45.1k
    1997249U, // LDFrr
328
45.1k
    1997275U, // LDQFri
329
45.1k
    1997275U, // LDQFrr
330
45.1k
    1997229U, // LDSBri
331
45.1k
    1997229U, // LDSBrr
332
45.1k
    1997254U, // LDSHri
333
45.1k
    1997254U, // LDSHrr
334
45.1k
    1997287U, // LDSWri
335
45.1k
    1997287U, // LDSWrr
336
45.1k
    1997236U, // LDUBri
337
45.1k
    1997236U, // LDUBrr
338
45.1k
    1997261U, // LDUHri
339
45.1k
    1997261U, // LDUHrr
340
45.1k
    1997294U, // LDXri
341
45.1k
    1997294U, // LDXrr
342
45.1k
    1997249U, // LDri
343
45.1k
    1997249U, // LDrr
344
45.1k
    33480U, // LEAX_ADDri
345
45.1k
    33480U, // LEA_ADDri
346
45.1k
    1054405U, // LZCNT
347
45.1k
    75121U, // MEMBARi
348
45.1k
    1054543U, // MOVDTOX
349
45.1k
    1006122U, // MOVFCCri
350
45.1k
    1006122U, // MOVFCCrr
351
45.1k
    23484970U,  // MOVICCri
352
45.1k
    23484970U,  // MOVICCrr
353
45.1k
    6047U,  // MOVRGEZri
354
45.1k
    6047U,  // MOVRGEZrr
355
45.1k
    6142U,  // MOVRGZri
356
45.1k
    6142U,  // MOVRGZrr
357
45.1k
    6096U,  // MOVRLEZri
358
45.1k
    6096U,  // MOVRLEZrr
359
45.1k
    6186U,  // MOVRLZri
360
45.1k
    6186U,  // MOVRLZrr
361
45.1k
    6230U,  // MOVRNZri
362
45.1k
    6230U,  // MOVRNZrr
363
45.1k
    6262U,  // MOVRRZri
364
45.1k
    6262U,  // MOVRRZrr
365
45.1k
    1054469U, // MOVSTOSW
366
45.1k
    1054479U, // MOVSTOUW
367
45.1k
    1054543U, // MOVWTOS
368
45.1k
    23747114U,  // MOVXCCri
369
45.1k
    23747114U,  // MOVXCCrr
370
45.1k
    1054543U, // MOVXTOD
371
45.1k
    5954U,  // MULXri
372
45.1k
    5954U,  // MULXrr
373
45.1k
    2578U,  // NOP
374
45.1k
    4735U,  // ORCCri
375
45.1k
    4735U,  // ORCCrr
376
45.1k
    4726U,  // ORNCCri
377
45.1k
    4726U,  // ORNCCrr
378
45.1k
    5339U,  // ORNri
379
45.1k
    5339U,  // ORNrr
380
45.1k
    5339U,  // ORXNrr
381
45.1k
    5509U,  // ORXri
382
45.1k
    5509U,  // ORXrr
383
45.1k
    5509U,  // ORri
384
45.1k
    5509U,  // ORrr
385
45.1k
    5836U,  // PDIST
386
45.1k
    5344U,  // PDISTN
387
45.1k
    1053356U, // POPCrr
388
45.1k
    73729U, // RDY
389
45.1k
    4999U,  // RESTOREri
390
45.1k
    4999U,  // RESTORErr
391
45.1k
    76132U, // RET
392
45.1k
    76141U, // RETL
393
45.1k
    18131U, // RETTri
394
45.1k
    18131U, // RETTrr
395
45.1k
    5008U,  // SAVEri
396
45.1k
    5008U,  // SAVErr
397
45.1k
    4748U,  // SDIVCCri
398
45.1k
    4748U,  // SDIVCCrr
399
45.1k
    5995U,  // SDIVXri
400
45.1k
    5995U,  // SDIVXrr
401
45.1k
    5861U,  // SDIVri
402
45.1k
    5861U,  // SDIVrr
403
45.1k
    2182U,  // SELECT_CC_DFP_FCC
404
45.1k
    2293U,  // SELECT_CC_DFP_ICC
405
45.1k
    2238U,  // SELECT_CC_FP_FCC
406
45.1k
    2349U,  // SELECT_CC_FP_ICC
407
45.1k
    2265U,  // SELECT_CC_Int_FCC
408
45.1k
    2376U,  // SELECT_CC_Int_ICC
409
45.1k
    2210U,  // SELECT_CC_QFP_FCC
410
45.1k
    2321U,  // SELECT_CC_QFP_ICC
411
45.1k
    1053595U, // SETHIXi
412
45.1k
    1053595U, // SETHIi
413
45.1k
    2569U,  // SHUTDOWN
414
45.1k
    2564U,  // SIAM
415
45.1k
    5941U,  // SLLXri
416
45.1k
    5941U,  // SLLXrr
417
45.1k
    5116U,  // SLLri
418
45.1k
    5116U,  // SLLrr
419
45.1k
    4702U,  // SMULCCri
420
45.1k
    4702U,  // SMULCCrr
421
45.1k
    5144U,  // SMULri
422
45.1k
    5144U,  // SMULrr
423
45.1k
    5913U,  // SRAXri
424
45.1k
    5913U,  // SRAXrr
425
45.1k
    4643U,  // SRAri
426
45.1k
    4643U,  // SRArr
427
45.1k
    5947U,  // SRLXri
428
45.1k
    5947U,  // SRLXrr
429
45.1k
    5139U,  // SRLri
430
45.1k
    5139U,  // SRLrr
431
45.1k
    2588U,  // STBAR
432
45.1k
    37428U, // STBri
433
45.1k
    37428U, // STBrr
434
45.1k
    37723U, // STDFri
435
45.1k
    37723U, // STDFrr
436
45.1k
    38607U, // STFri
437
45.1k
    38607U, // STFrr
438
45.1k
    37782U, // STHri
439
45.1k
    37782U, // STHrr
440
45.1k
    38238U, // STQFri
441
45.1k
    38238U, // STQFrr
442
45.1k
    38758U, // STXri
443
45.1k
    38758U, // STXrr
444
45.1k
    38607U, // STri
445
45.1k
    38607U, // STrr
446
45.1k
    4671U,  // SUBCCri
447
45.1k
    4671U,  // SUBCCrr
448
45.1k
    5919U,  // SUBCri
449
45.1k
    5919U,  // SUBCrr
450
45.1k
    4764U,  // SUBEri
451
45.1k
    4764U,  // SUBErr
452
45.1k
    4665U,  // SUBXri
453
45.1k
    4665U,  // SUBXrr
454
45.1k
    4665U,  // SUBri
455
45.1k
    4665U,  // SUBrr
456
45.1k
    1997268U, // SWAPri
457
45.1k
    1997268U, // SWAPrr
458
45.1k
    2422U,  // TA3
459
45.1k
    2427U,  // TA5
460
45.1k
    5883U,  // TADDCCTVri
461
45.1k
    5883U,  // TADDCCTVrr
462
45.1k
    4687U,  // TADDCCri
463
45.1k
    4687U,  // TADDCCrr
464
45.1k
    9873960U, // TICCri
465
45.1k
    9873960U, // TICCrr
466
45.1k
    37753544U,  // TLS_ADDXrr
467
45.1k
    37753544U,  // TLS_ADDrr
468
45.1k
    2106358U, // TLS_CALL
469
45.1k
    39746030U,  // TLS_LDXrr
470
45.1k
    39745985U,  // TLS_LDrr
471
45.1k
    5873U,  // TSUBCCTVri
472
45.1k
    5873U,  // TSUBCCTVrr
473
45.1k
    4670U,  // TSUBCCri
474
45.1k
    4670U,  // TSUBCCrr
475
45.1k
    10136104U,  // TXCCri
476
45.1k
    10136104U,  // TXCCrr
477
45.1k
    4756U,  // UDIVCCri
478
45.1k
    4756U,  // UDIVCCrr
479
45.1k
    6002U,  // UDIVXri
480
45.1k
    6002U,  // UDIVXrr
481
45.1k
    5867U,  // UDIVri
482
45.1k
    5867U,  // UDIVrr
483
45.1k
    4710U,  // UMULCCri
484
45.1k
    4710U,  // UMULCCrr
485
45.1k
    5026U,  // UMULXHI
486
45.1k
    5150U,  // UMULri
487
45.1k
    5150U,  // UMULrr
488
45.1k
    74996U, // UNIMP
489
45.1k
    6300477U, // V9FCMPD
490
45.1k
    6300397U, // V9FCMPED
491
45.1k
    6300942U, // V9FCMPEQ
492
45.1k
    6301251U, // V9FCMPES
493
45.1k
    6301000U, // V9FCMPQ
494
45.1k
    6301309U, // V9FCMPS
495
45.1k
    47614U, // V9FMOVD_FCC
496
45.1k
    47638U, // V9FMOVQ_FCC
497
45.1k
    47650U, // V9FMOVS_FCC
498
45.1k
    47658U, // V9MOVFCCri
499
45.1k
    47658U, // V9MOVFCCrr
500
45.1k
    14689692U,  // WRYri
501
45.1k
    14689692U,  // WRYrr
502
45.1k
    5953U,  // XMULX
503
45.1k
    5035U,  // XMULXHI
504
45.1k
    4733U,  // XNORCCri
505
45.1k
    4733U,  // XNORCCrr
506
45.1k
    5520U,  // XNORXrr
507
45.1k
    5520U,  // XNORri
508
45.1k
    5520U,  // XNORrr
509
45.1k
    4741U,  // XORCCri
510
45.1k
    4741U,  // XORCCrr
511
45.1k
    5527U,  // XORXri
512
45.1k
    5527U,  // XORXrr
513
45.1k
    5527U,  // XORri
514
45.1k
    5527U,  // XORrr
515
45.1k
    0U
516
45.1k
  };
517
518
45.1k
#ifndef CAPSTONE_DIET
519
45.1k
  static const char AsmStrs[] = {
520
45.1k
  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521
45.1k
  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522
45.1k
  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523
45.1k
  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524
45.1k
  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525
45.1k
  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526
45.1k
  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527
45.1k
  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528
45.1k
  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529
45.1k
  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530
45.1k
  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531
45.1k
  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532
45.1k
  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533
45.1k
  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534
45.1k
  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535
45.1k
  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536
45.1k
  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537
45.1k
  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538
45.1k
  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539
45.1k
  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540
45.1k
  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541
45.1k
  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542
45.1k
  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543
45.1k
  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544
45.1k
  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545
45.1k
  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546
45.1k
  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547
45.1k
  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548
45.1k
  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549
45.1k
  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550
45.1k
  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551
45.1k
  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552
45.1k
  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553
45.1k
  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554
45.1k
  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555
45.1k
  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556
45.1k
  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557
45.1k
  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558
45.1k
  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559
45.1k
  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560
45.1k
  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561
45.1k
  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562
45.1k
  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563
45.1k
  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564
45.1k
  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565
45.1k
  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566
45.1k
  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567
45.1k
  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568
45.1k
  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569
45.1k
  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570
45.1k
  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571
45.1k
  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572
45.1k
  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573
45.1k
  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574
45.1k
  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575
45.1k
  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576
45.1k
  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577
45.1k
  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578
45.1k
  /* 542 */ 'b', 'a', 32, 0,
579
45.1k
  /* 546 */ 's', 'r', 'a', 32, 0,
580
45.1k
  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581
45.1k
  /* 563 */ 's', 't', 'b', 32, 0,
582
45.1k
  /* 568 */ 's', 'u', 'b', 32, 0,
583
45.1k
  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584
45.1k
  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585
45.1k
  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586
45.1k
  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587
45.1k
  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588
45.1k
  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589
45.1k
  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590
45.1k
  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591
45.1k
  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592
45.1k
  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593
45.1k
  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594
45.1k
  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595
45.1k
  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596
45.1k
  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597
45.1k
  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598
45.1k
  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599
45.1k
  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600
45.1k
  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601
45.1k
  /* 711 */ 'a', 'd', 'd', 32, 0,
602
45.1k
  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603
45.1k
  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604
45.1k
  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605
45.1k
  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606
45.1k
  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607
45.1k
  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608
45.1k
  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609
45.1k
  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610
45.1k
  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611
45.1k
  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612
45.1k
  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613
45.1k
  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614
45.1k
  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615
45.1k
  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616
45.1k
  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617
45.1k
  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618
45.1k
  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619
45.1k
  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620
45.1k
  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621
45.1k
  /* 858 */ 's', 't', 'd', 32, 0,
622
45.1k
  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623
45.1k
  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624
45.1k
  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625
45.1k
  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626
45.1k
  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627
45.1k
  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628
45.1k
  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629
45.1k
  /* 917 */ 's', 't', 'h', 32, 0,
630
45.1k
  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631
45.1k
  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632
45.1k
  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633
45.1k
  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634
45.1k
  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635
45.1k
  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636
45.1k
  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637
45.1k
  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638
45.1k
  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639
45.1k
  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640
45.1k
  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641
45.1k
  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642
45.1k
  /* 1019 */ 's', 'l', 'l', 32, 0,
643
45.1k
  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644
45.1k
  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645
45.1k
  /* 1042 */ 's', 'r', 'l', 32, 0,
646
45.1k
  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647
45.1k
  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648
45.1k
  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649
45.1k
  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650
45.1k
  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651
45.1k
  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652
45.1k
  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653
45.1k
  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654
45.1k
  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655
45.1k
  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656
45.1k
  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657
45.1k
  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658
45.1k
  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659
45.1k
  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660
45.1k
  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661
45.1k
  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662
45.1k
  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663
45.1k
  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664
45.1k
  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665
45.1k
  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666
45.1k
  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667
45.1k
  /* 1242 */ 'o', 'r', 'n', 32, 0,
668
45.1k
  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669
45.1k
  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670
45.1k
  /* 1262 */ 'c', 'm', 'p', 32, 0,
671
45.1k
  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672
45.1k
  /* 1274 */ 'j', 'm', 'p', 32, 0,
673
45.1k
  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674
45.1k
  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675
45.1k
  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676
45.1k
  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677
45.1k
  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678
45.1k
  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679
45.1k
  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680
45.1k
  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681
45.1k
  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682
45.1k
  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683
45.1k
  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684
45.1k
  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685
45.1k
  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686
45.1k
  /* 1373 */ 's', 't', 'q', 32, 0,
687
45.1k
  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688
45.1k
  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689
45.1k
  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690
45.1k
  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691
45.1k
  /* 1411 */ 'f', 'o', 'r', 32, 0,
692
45.1k
  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693
45.1k
  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694
45.1k
  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695
45.1k
  /* 1435 */ 'w', 'r', 32, 0,
696
45.1k
  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697
45.1k
  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698
45.1k
  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699
45.1k
  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700
45.1k
  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701
45.1k
  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702
45.1k
  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703
45.1k
  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704
45.1k
  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705
45.1k
  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706
45.1k
  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707
45.1k
  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708
45.1k
  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709
45.1k
  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710
45.1k
  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711
45.1k
  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712
45.1k
  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713
45.1k
  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714
45.1k
  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715
45.1k
  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716
45.1k
  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717
45.1k
  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718
45.1k
  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719
45.1k
  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720
45.1k
  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721
45.1k
  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722
45.1k
  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723
45.1k
  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724
45.1k
  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725
45.1k
  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726
45.1k
  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727
45.1k
  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728
45.1k
  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729
45.1k
  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730
45.1k
  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731
45.1k
  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732
45.1k
  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733
45.1k
  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734
45.1k
  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735
45.1k
  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736
45.1k
  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737
45.1k
  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738
45.1k
  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739
45.1k
  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740
45.1k
  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741
45.1k
  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742
45.1k
  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743
45.1k
  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744
45.1k
  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745
45.1k
  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746
45.1k
  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747
45.1k
  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748
45.1k
  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749
45.1k
  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750
45.1k
  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751
45.1k
  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752
45.1k
  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753
45.1k
  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754
45.1k
  /* 1893 */ 's', 't', 'x', 32, 0,
755
45.1k
  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756
45.1k
  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757
45.1k
  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758
45.1k
  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759
45.1k
  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760
45.1k
  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761
45.1k
  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762
45.1k
  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763
45.1k
  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764
45.1k
  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765
45.1k
  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766
45.1k
  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767
45.1k
  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768
45.1k
  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769
45.1k
  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770
45.1k
  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771
45.1k
  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772
45.1k
  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773
45.1k
  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774
45.1k
  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775
45.1k
  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776
45.1k
  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777
45.1k
  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778
45.1k
  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779
45.1k
  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780
45.1k
  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781
45.1k
  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782
45.1k
  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783
45.1k
  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784
45.1k
  /* 2160 */ 'b', 'r', 'z', 32, 0,
785
45.1k
  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786
45.1k
  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787
45.1k
  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788
45.1k
  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789
45.1k
  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790
45.1k
  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791
45.1k
  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792
45.1k
  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793
45.1k
  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794
45.1k
  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795
45.1k
  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796
45.1k
  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797
45.1k
  /* 2421 */ 't', 'a', 32, '3', 0,
798
45.1k
  /* 2426 */ 't', 'a', 32, '5', 0,
799
45.1k
  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800
45.1k
  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801
45.1k
  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802
45.1k
  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803
45.1k
  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804
45.1k
  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805
45.1k
  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806
45.1k
  /* 2496 */ 'l', 'd', 32, '[', 0,
807
45.1k
  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808
45.1k
  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809
45.1k
  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810
45.1k
  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811
45.1k
  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812
45.1k
  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813
45.1k
  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814
45.1k
  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815
45.1k
  /* 2554 */ 'f', 'b', 0,
816
45.1k
  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817
45.1k
  /* 2563 */ 's', 'i', 'a', 'm', 0,
818
45.1k
  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819
45.1k
  /* 2577 */ 'n', 'o', 'p', 0,
820
45.1k
  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821
45.1k
  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822
45.1k
  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823
45.1k
  /* 2599 */ 't', 0,
824
45.1k
  /* 2601 */ 'm', 'o', 'v', 0,
825
45.1k
  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826
45.1k
  };
827
45.1k
#endif
828
829
  // Emit the opcode for the instruction.
830
45.1k
  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831
45.1k
#ifndef CAPSTONE_DIET
832
  // assert(Bits != 0 && "Cannot print this instruction.");
833
45.1k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834
45.1k
#endif
835
836
837
  // Fragment 0 encoded into 4 bits for 12 unique commands.
838
  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839
45.1k
  switch ((Bits >> 12) & 15) {
840
0
  default:   // unreachable.
841
216
  case 0:
842
    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843
216
    return;
844
0
    break;
845
8.41k
  case 1:
846
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847
8.41k
    printOperand(MI, 1, O); 
848
8.41k
    break;
849
26.6k
  case 2:
850
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851
26.6k
    printOperand(MI, 0, O); 
852
26.6k
    break;
853
4.82k
  case 3:
854
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855
4.82k
    printCCOperand(MI, 1, O); 
856
4.82k
    break;
857
127
  case 4:
858
    // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859
127
    printMemOperand(MI, 0, O, NULL); 
860
127
    return;
861
0
    break;
862
945
  case 5:
863
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864
945
    printCCOperand(MI, 3, O); 
865
945
    break;
866
0
  case 6:
867
    // GETPCX
868
0
    printGetPCX(MI, 0, O); 
869
0
    return;
870
0
    break;
871
2.21k
  case 7:
872
    // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873
2.21k
    printMemOperand(MI, 1, O, NULL); 
874
2.21k
    break;
875
0
  case 8:
876
    // LEAX_ADDri, LEA_ADDri
877
0
    printMemOperand(MI, 1, O, "arith"); 
878
0
    SStream_concat0(O, ", "); 
879
0
    printOperand(MI, 0, O); 
880
0
    return;
881
0
    break;
882
616
  case 9:
883
    // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884
616
    printOperand(MI, 2, O); 
885
616
    SStream_concat0(O, ", ["); 
886
616
    printMemOperand(MI, 0, O, NULL); 
887
616
    SStream_concat0(O, "]"); 
888
616
    return;
889
0
    break;
890
162
  case 10:
891
    // TICCri, TICCrr, TXCCri, TXCCrr
892
162
    printCCOperand(MI, 2, O); 
893
162
    break;
894
987
  case 11:
895
    // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896
987
    printCCOperand(MI, 4, O); 
897
987
    SStream_concat0(O, " "); 
898
987
    printOperand(MI, 1, O); 
899
987
    SStream_concat0(O, ", "); 
900
987
    printOperand(MI, 2, O); 
901
987
    SStream_concat0(O, ", "); 
902
987
    printOperand(MI, 0, O); 
903
987
    return;
904
0
    break;
905
45.1k
  }
906
907
908
  // Fragment 1 encoded into 4 bits for 16 unique commands.
909
  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910
43.2k
  switch ((Bits >> 16) & 15) {
911
0
  default:   // unreachable.
912
14.9k
  case 0:
913
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914
14.9k
    SStream_concat0(O, ", "); 
915
14.9k
    break;
916
20.4k
  case 1:
917
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918
20.4k
    return;
919
0
    break;
920
1.80k
  case 2:
921
    // BCOND, BPFCC, FBCOND
922
1.80k
    SStream_concat0(O, " "); 
923
1.80k
    break;
924
1.61k
  case 3:
925
    // BCONDA, BPFCCA, FBCONDA
926
1.61k
    SStream_concat0(O, ",a ");
927
1.61k
  Sparc_add_hint(MI, SPARC_HINT_A);
928
1.61k
    break;
929
0
  case 4:
930
    // BPFCCANT
931
0
    SStream_concat0(O, ",a,pn ");
932
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933
0
    printOperand(MI, 2, O); 
934
0
    SStream_concat0(O, ", "); 
935
0
    printOperand(MI, 0, O); 
936
0
    return;
937
0
    break;
938
0
  case 5:
939
    // BPFCCNT
940
0
    SStream_concat0(O, ",pn ");
941
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
942
0
    printOperand(MI, 2, O); 
943
0
    SStream_concat0(O, ", "); 
944
0
    printOperand(MI, 0, O); 
945
0
    return;
946
0
    break;
947
1.03k
  case 6:
948
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949
1.03k
    SStream_concat0(O, " %icc, ");
950
1.03k
  Sparc_add_reg(MI, SPARC_REG_ICC);
951
1.03k
    break;
952
240
  case 7:
953
    // BPICCA
954
240
    SStream_concat0(O, ",a %icc, ");
955
240
  Sparc_add_hint(MI, SPARC_HINT_A);
956
240
  Sparc_add_reg(MI, SPARC_REG_ICC);
957
240
    printOperand(MI, 0, O); 
958
240
    return;
959
0
    break;
960
0
  case 8:
961
    // BPICCANT
962
0
    SStream_concat0(O, ",a,pn %icc, ");
963
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
965
0
    printOperand(MI, 0, O); 
966
0
    return;
967
0
    break;
968
0
  case 9:
969
    // BPICCNT
970
0
    SStream_concat0(O, ",pn %icc, ");
971
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
972
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
973
0
    printOperand(MI, 0, O); 
974
0
    return;
975
0
    break;
976
663
  case 10:
977
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978
663
    SStream_concat0(O, " %xcc, ");
979
663
  Sparc_add_reg(MI, SPARC_REG_XCC);
980
663
    break;
981
223
  case 11:
982
    // BPXCCA
983
223
    SStream_concat0(O, ",a %xcc, ");
984
223
  Sparc_add_hint(MI, SPARC_HINT_A);
985
223
  Sparc_add_reg(MI, SPARC_REG_XCC);
986
223
    printOperand(MI, 0, O); 
987
223
    return;
988
0
    break;
989
0
  case 12:
990
    // BPXCCANT
991
0
    SStream_concat0(O, ",a,pn %xcc, ");
992
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
994
0
    printOperand(MI, 0, O); 
995
0
    return;
996
0
    break;
997
0
  case 13:
998
    // BPXCCNT
999
0
    SStream_concat0(O, ",pn %xcc, ");
1000
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
1001
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
1002
0
    printOperand(MI, 0, O); 
1003
0
    return;
1004
0
    break;
1005
1.88k
  case 14:
1006
    // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007
1.88k
    SStream_concat0(O, "], "); 
1008
1.88k
    break;
1009
364
  case 15:
1010
    // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011
364
    SStream_concat0(O, " %fcc0, ");
1012
364
  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013
364
    printOperand(MI, 1, O); 
1014
364
    SStream_concat0(O, ", "); 
1015
364
    printOperand(MI, 0, O); 
1016
364
    return;
1017
0
    break;
1018
43.2k
  }
1019
1020
1021
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022
  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023
21.9k
  switch ((Bits >> 20) & 3) {
1024
0
  default:   // unreachable.
1025
5.78k
  case 0:
1026
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027
5.78k
    printOperand(MI, 2, O); 
1028
5.78k
    SStream_concat0(O, ", "); 
1029
5.78k
    printOperand(MI, 0, O); 
1030
5.78k
    break;
1031
9.37k
  case 1:
1032
    // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033
9.37k
    printOperand(MI, 0, O); 
1034
9.37k
    break;
1035
6.80k
  case 2:
1036
    // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037
6.80k
    printOperand(MI, 1, O); 
1038
6.80k
    break;
1039
21.9k
  }
1040
1041
1042
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043
  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044
21.9k
  switch ((Bits >> 22) & 3) {
1045
0
  default:   // unreachable.
1046
19.0k
  case 0:
1047
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048
19.0k
    return;
1049
0
    break;
1050
2.51k
  case 1:
1051
    // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052
2.51k
    SStream_concat0(O, ", "); 
1053
2.51k
    break;
1054
162
  case 2:
1055
    // TICCri, TICCrr, TXCCri, TXCCrr
1056
162
    SStream_concat0(O, " + ");  // qq
1057
162
    printOperand(MI, 1, O); 
1058
162
    return;
1059
0
    break;
1060
258
  case 3:
1061
    // WRYri, WRYrr
1062
258
    SStream_concat0(O, ", %y");
1063
258
  Sparc_add_reg(MI, SPARC_REG_Y);
1064
258
    return;
1065
0
    break;
1066
21.9k
  }
1067
1068
1069
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070
  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071
2.51k
  switch ((Bits >> 24) & 3) {
1072
0
  default:   // unreachable.
1073
1.93k
  case 0:
1074
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075
1.93k
    printOperand(MI, 2, O); 
1076
1.93k
    return;
1077
0
    break;
1078
581
  case 1:
1079
    // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080
581
    printOperand(MI, 0, O); 
1081
581
    return;
1082
0
    break;
1083
0
  case 2:
1084
    // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085
0
    printOperand(MI, 3, O); 
1086
0
    return;
1087
0
    break;
1088
2.51k
  }
1089
2.51k
}
1090
1091
1092
/// getRegisterName - This method is automatically generated by tblgen
1093
/// from the register set description.  This returns the assembler name
1094
/// for the specified register.
1095
static const char *getRegisterName(unsigned RegNo)
1096
59.7k
{
1097
  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098
1099
59.7k
#ifndef CAPSTONE_DIET
1100
59.7k
  static const char AsmStrs[] = {
1101
59.7k
  /* 0 */ 'f', '1', '0', 0,
1102
59.7k
  /* 4 */ 'f', '2', '0', 0,
1103
59.7k
  /* 8 */ 'f', '3', '0', 0,
1104
59.7k
  /* 12 */ 'f', '4', '0', 0,
1105
59.7k
  /* 16 */ 'f', '5', '0', 0,
1106
59.7k
  /* 20 */ 'f', '6', '0', 0,
1107
59.7k
  /* 24 */ 'f', 'c', 'c', '0', 0,
1108
59.7k
  /* 29 */ 'f', '0', 0,
1109
59.7k
  /* 32 */ 'g', '0', 0,
1110
59.7k
  /* 35 */ 'i', '0', 0,
1111
59.7k
  /* 38 */ 'l', '0', 0,
1112
59.7k
  /* 41 */ 'o', '0', 0,
1113
59.7k
  /* 44 */ 'f', '1', '1', 0,
1114
59.7k
  /* 48 */ 'f', '2', '1', 0,
1115
59.7k
  /* 52 */ 'f', '3', '1', 0,
1116
59.7k
  /* 56 */ 'f', 'c', 'c', '1', 0,
1117
59.7k
  /* 61 */ 'f', '1', 0,
1118
59.7k
  /* 64 */ 'g', '1', 0,
1119
59.7k
  /* 67 */ 'i', '1', 0,
1120
59.7k
  /* 70 */ 'l', '1', 0,
1121
59.7k
  /* 73 */ 'o', '1', 0,
1122
59.7k
  /* 76 */ 'f', '1', '2', 0,
1123
59.7k
  /* 80 */ 'f', '2', '2', 0,
1124
59.7k
  /* 84 */ 'f', '3', '2', 0,
1125
59.7k
  /* 88 */ 'f', '4', '2', 0,
1126
59.7k
  /* 92 */ 'f', '5', '2', 0,
1127
59.7k
  /* 96 */ 'f', '6', '2', 0,
1128
59.7k
  /* 100 */ 'f', 'c', 'c', '2', 0,
1129
59.7k
  /* 105 */ 'f', '2', 0,
1130
59.7k
  /* 108 */ 'g', '2', 0,
1131
59.7k
  /* 111 */ 'i', '2', 0,
1132
59.7k
  /* 114 */ 'l', '2', 0,
1133
59.7k
  /* 117 */ 'o', '2', 0,
1134
59.7k
  /* 120 */ 'f', '1', '3', 0,
1135
59.7k
  /* 124 */ 'f', '2', '3', 0,
1136
59.7k
  /* 128 */ 'f', 'c', 'c', '3', 0,
1137
59.7k
  /* 133 */ 'f', '3', 0,
1138
59.7k
  /* 136 */ 'g', '3', 0,
1139
59.7k
  /* 139 */ 'i', '3', 0,
1140
59.7k
  /* 142 */ 'l', '3', 0,
1141
59.7k
  /* 145 */ 'o', '3', 0,
1142
59.7k
  /* 148 */ 'f', '1', '4', 0,
1143
59.7k
  /* 152 */ 'f', '2', '4', 0,
1144
59.7k
  /* 156 */ 'f', '3', '4', 0,
1145
59.7k
  /* 160 */ 'f', '4', '4', 0,
1146
59.7k
  /* 164 */ 'f', '5', '4', 0,
1147
59.7k
  /* 168 */ 'f', '4', 0,
1148
59.7k
  /* 171 */ 'g', '4', 0,
1149
59.7k
  /* 174 */ 'i', '4', 0,
1150
59.7k
  /* 177 */ 'l', '4', 0,
1151
59.7k
  /* 180 */ 'o', '4', 0,
1152
59.7k
  /* 183 */ 'f', '1', '5', 0,
1153
59.7k
  /* 187 */ 'f', '2', '5', 0,
1154
59.7k
  /* 191 */ 'f', '5', 0,
1155
59.7k
  /* 194 */ 'g', '5', 0,
1156
59.7k
  /* 197 */ 'i', '5', 0,
1157
59.7k
  /* 200 */ 'l', '5', 0,
1158
59.7k
  /* 203 */ 'o', '5', 0,
1159
59.7k
  /* 206 */ 'f', '1', '6', 0,
1160
59.7k
  /* 210 */ 'f', '2', '6', 0,
1161
59.7k
  /* 214 */ 'f', '3', '6', 0,
1162
59.7k
  /* 218 */ 'f', '4', '6', 0,
1163
59.7k
  /* 222 */ 'f', '5', '6', 0,
1164
59.7k
  /* 226 */ 'f', '6', 0,
1165
59.7k
  /* 229 */ 'g', '6', 0,
1166
59.7k
  /* 232 */ 'l', '6', 0,
1167
59.7k
  /* 235 */ 'f', '1', '7', 0,
1168
59.7k
  /* 239 */ 'f', '2', '7', 0,
1169
59.7k
  /* 243 */ 'f', '7', 0,
1170
59.7k
  /* 246 */ 'g', '7', 0,
1171
59.7k
  /* 249 */ 'i', '7', 0,
1172
59.7k
  /* 252 */ 'l', '7', 0,
1173
59.7k
  /* 255 */ 'o', '7', 0,
1174
59.7k
  /* 258 */ 'f', '1', '8', 0,
1175
59.7k
  /* 262 */ 'f', '2', '8', 0,
1176
59.7k
  /* 266 */ 'f', '3', '8', 0,
1177
59.7k
  /* 270 */ 'f', '4', '8', 0,
1178
59.7k
  /* 274 */ 'f', '5', '8', 0,
1179
59.7k
  /* 278 */ 'f', '8', 0,
1180
59.7k
  /* 281 */ 'f', '1', '9', 0,
1181
59.7k
  /* 285 */ 'f', '2', '9', 0,
1182
59.7k
  /* 289 */ 'f', '9', 0,
1183
59.7k
  /* 292 */ 'i', 'c', 'c', 0,
1184
59.7k
  /* 296 */ 'f', 'p', 0,
1185
59.7k
  /* 299 */ 's', 'p', 0,
1186
59.7k
  /* 302 */ 'y', 0,
1187
59.7k
  };
1188
1189
59.7k
  static const uint16_t RegAsmOffset[] = {
1190
59.7k
    292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 
1191
59.7k
    152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 
1192
59.7k
    92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 
1193
59.7k
    278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 
1194
59.7k
    80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 
1195
59.7k
    32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 
1196
59.7k
    296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 
1197
59.7k
    180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 
1198
59.7k
    12, 160, 270, 92, 222, 20, 
1199
59.7k
  };
1200
1201
  //int i;
1202
  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203
  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204
  //printf("*************************\n");
1205
59.7k
  return AsmStrs+RegAsmOffset[RegNo-1];
1206
#else
1207
  return NULL;
1208
#endif
1209
59.7k
}
1210
1211
#ifdef PRINT_ALIAS_INSTR
1212
#undef PRINT_ALIAS_INSTR
1213
1214
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1215
  unsigned PrintMethodIdx, SStream *OS)
1216
0
{
1217
0
}
1218
1219
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1220
77.6k
{
1221
319k
  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1222
77.6k
  const char *AsmString;
1223
77.6k
  char *tmp, *AsmMnem, *AsmOps, *c;
1224
77.6k
  int OpIdx, PrintMethodIdx;
1225
77.6k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1226
77.6k
  switch (MCInst_getOpcode(MI)) {
1227
43.1k
  default: return NULL;
1228
2.37k
  case SP_BCOND:
1229
2.37k
    if (MCInst_getNumOperands(MI) == 2 &&
1230
2.37k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1231
2.37k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1232
      // (BCOND brtarget:$imm, 8)
1233
0
      AsmString = "ba $\x01";
1234
0
      break;
1235
0
    }
1236
2.37k
    if (MCInst_getNumOperands(MI) == 2 &&
1237
2.37k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1238
2.37k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1239
      // (BCOND brtarget:$imm, 0)
1240
624
      AsmString = "bn $\x01";
1241
624
      break;
1242
624
    }
1243
1.74k
    if (MCInst_getNumOperands(MI) == 2 &&
1244
1.74k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1245
1.74k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1246
      // (BCOND brtarget:$imm, 9)
1247
102
      AsmString = "bne $\x01";
1248
102
      break;
1249
102
    }
1250
1.64k
    if (MCInst_getNumOperands(MI) == 2 &&
1251
1.64k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1252
1.64k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1253
      // (BCOND brtarget:$imm, 1)
1254
88
      AsmString = "be $\x01";
1255
88
      break;
1256
88
    }
1257
1.55k
    if (MCInst_getNumOperands(MI) == 2 &&
1258
1.55k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1259
1.55k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1260
      // (BCOND brtarget:$imm, 10)
1261
61
      AsmString = "bg $\x01";
1262
61
      break;
1263
61
    }
1264
1.49k
    if (MCInst_getNumOperands(MI) == 2 &&
1265
1.49k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1266
1.49k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1267
      // (BCOND brtarget:$imm, 2)
1268
207
      AsmString = "ble $\x01";
1269
207
      break;
1270
207
    }
1271
1.28k
    if (MCInst_getNumOperands(MI) == 2 &&
1272
1.28k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1273
1.28k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1274
      // (BCOND brtarget:$imm, 11)
1275
196
      AsmString = "bge $\x01";
1276
196
      break;
1277
196
    }
1278
1.09k
    if (MCInst_getNumOperands(MI) == 2 &&
1279
1.09k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1280
1.09k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1281
      // (BCOND brtarget:$imm, 3)
1282
96
      AsmString = "bl $\x01";
1283
96
      break;
1284
96
    }
1285
997
    if (MCInst_getNumOperands(MI) == 2 &&
1286
997
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1287
997
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1288
      // (BCOND brtarget:$imm, 12)
1289
111
      AsmString = "bgu $\x01";
1290
111
      break;
1291
111
    }
1292
886
    if (MCInst_getNumOperands(MI) == 2 &&
1293
886
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1294
886
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1295
      // (BCOND brtarget:$imm, 4)
1296
107
      AsmString = "bleu $\x01";
1297
107
      break;
1298
107
    }
1299
779
    if (MCInst_getNumOperands(MI) == 2 &&
1300
779
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1301
779
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1302
      // (BCOND brtarget:$imm, 13)
1303
70
      AsmString = "bcc $\x01";
1304
70
      break;
1305
70
    }
1306
709
    if (MCInst_getNumOperands(MI) == 2 &&
1307
709
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1308
709
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1309
      // (BCOND brtarget:$imm, 5)
1310
197
      AsmString = "bcs $\x01";
1311
197
      break;
1312
197
    }
1313
512
    if (MCInst_getNumOperands(MI) == 2 &&
1314
512
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1315
512
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1316
      // (BCOND brtarget:$imm, 14)
1317
69
      AsmString = "bpos $\x01";
1318
69
      break;
1319
69
    }
1320
443
    if (MCInst_getNumOperands(MI) == 2 &&
1321
443
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1322
443
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1323
      // (BCOND brtarget:$imm, 6)
1324
115
      AsmString = "bneg $\x01";
1325
115
      break;
1326
115
    }
1327
328
    if (MCInst_getNumOperands(MI) == 2 &&
1328
328
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1329
328
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1330
      // (BCOND brtarget:$imm, 15)
1331
213
      AsmString = "bvc $\x01";
1332
213
      break;
1333
213
    }
1334
115
    if (MCInst_getNumOperands(MI) == 2 &&
1335
115
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1336
115
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1337
      // (BCOND brtarget:$imm, 7)
1338
115
      AsmString = "bvs $\x01";
1339
115
      break;
1340
115
    }
1341
0
    return NULL;
1342
2.20k
  case SP_BCONDA:
1343
2.20k
    if (MCInst_getNumOperands(MI) == 2 &&
1344
2.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1345
2.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1346
      // (BCONDA brtarget:$imm, 8)
1347
349
      AsmString = "ba,a $\x01";
1348
349
      break;
1349
349
    }
1350
1.85k
    if (MCInst_getNumOperands(MI) == 2 &&
1351
1.85k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1352
1.85k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1353
      // (BCONDA brtarget:$imm, 0)
1354
219
      AsmString = "bn,a $\x01";
1355
219
      break;
1356
219
    }
1357
1.63k
    if (MCInst_getNumOperands(MI) == 2 &&
1358
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1359
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1360
      // (BCONDA brtarget:$imm, 9)
1361
97
      AsmString = "bne,a $\x01";
1362
97
      break;
1363
97
    }
1364
1.53k
    if (MCInst_getNumOperands(MI) == 2 &&
1365
1.53k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1366
1.53k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1367
      // (BCONDA brtarget:$imm, 1)
1368
140
      AsmString = "be,a $\x01";
1369
140
      break;
1370
140
    }
1371
1.39k
    if (MCInst_getNumOperands(MI) == 2 &&
1372
1.39k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1373
1.39k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1374
      // (BCONDA brtarget:$imm, 10)
1375
148
      AsmString = "bg,a $\x01";
1376
148
      break;
1377
148
    }
1378
1.24k
    if (MCInst_getNumOperands(MI) == 2 &&
1379
1.24k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1380
1.24k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1381
      // (BCONDA brtarget:$imm, 2)
1382
111
      AsmString = "ble,a $\x01";
1383
111
      break;
1384
111
    }
1385
1.13k
    if (MCInst_getNumOperands(MI) == 2 &&
1386
1.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1387
1.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1388
      // (BCONDA brtarget:$imm, 11)
1389
82
      AsmString = "bge,a $\x01";
1390
82
      break;
1391
82
    }
1392
1.05k
    if (MCInst_getNumOperands(MI) == 2 &&
1393
1.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1394
1.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1395
      // (BCONDA brtarget:$imm, 3)
1396
211
      AsmString = "bl,a $\x01";
1397
211
      break;
1398
211
    }
1399
844
    if (MCInst_getNumOperands(MI) == 2 &&
1400
844
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1401
844
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1402
      // (BCONDA brtarget:$imm, 12)
1403
54
      AsmString = "bgu,a $\x01";
1404
54
      break;
1405
54
    }
1406
790
    if (MCInst_getNumOperands(MI) == 2 &&
1407
790
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1408
790
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1409
      // (BCONDA brtarget:$imm, 4)
1410
112
      AsmString = "bleu,a $\x01";
1411
112
      break;
1412
112
    }
1413
678
    if (MCInst_getNumOperands(MI) == 2 &&
1414
678
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1415
678
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1416
      // (BCONDA brtarget:$imm, 13)
1417
69
      AsmString = "bcc,a $\x01";
1418
69
      break;
1419
69
    }
1420
609
    if (MCInst_getNumOperands(MI) == 2 &&
1421
609
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1422
609
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1423
      // (BCONDA brtarget:$imm, 5)
1424
125
      AsmString = "bcs,a $\x01";
1425
125
      break;
1426
125
    }
1427
484
    if (MCInst_getNumOperands(MI) == 2 &&
1428
484
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1429
484
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1430
      // (BCONDA brtarget:$imm, 14)
1431
216
      AsmString = "bpos,a $\x01";
1432
216
      break;
1433
216
    }
1434
268
    if (MCInst_getNumOperands(MI) == 2 &&
1435
268
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1436
268
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1437
      // (BCONDA brtarget:$imm, 6)
1438
111
      AsmString = "bneg,a $\x01";
1439
111
      break;
1440
111
    }
1441
157
    if (MCInst_getNumOperands(MI) == 2 &&
1442
157
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1443
157
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1444
      // (BCONDA brtarget:$imm, 15)
1445
76
      AsmString = "bvc,a $\x01";
1446
76
      break;
1447
76
    }
1448
81
    if (MCInst_getNumOperands(MI) == 2 &&
1449
81
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1450
81
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1451
      // (BCONDA brtarget:$imm, 7)
1452
81
      AsmString = "bvs,a $\x01";
1453
81
      break;
1454
81
    }
1455
0
    return NULL;
1456
4.05k
  case SP_BPFCCANT:
1457
4.05k
    if (MCInst_getNumOperands(MI) == 3 &&
1458
4.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1459
4.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1460
4.05k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1461
4.05k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1462
      // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1463
287
      AsmString = "fba,a,pn $\x03, $\x01";
1464
287
      break;
1465
287
    }
1466
3.76k
    if (MCInst_getNumOperands(MI) == 3 &&
1467
3.76k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1468
3.76k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1469
3.76k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1470
3.76k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1471
      // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1472
347
      AsmString = "fbn,a,pn $\x03, $\x01";
1473
347
      break;
1474
347
    }
1475
3.41k
    if (MCInst_getNumOperands(MI) == 3 &&
1476
3.41k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1477
3.41k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1478
3.41k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1479
3.41k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1480
      // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1481
119
      AsmString = "fbu,a,pn $\x03, $\x01";
1482
119
      break;
1483
119
    }
1484
3.29k
    if (MCInst_getNumOperands(MI) == 3 &&
1485
3.29k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1486
3.29k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1487
3.29k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1488
3.29k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1489
      // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1490
288
      AsmString = "fbg,a,pn $\x03, $\x01";
1491
288
      break;
1492
288
    }
1493
3.01k
    if (MCInst_getNumOperands(MI) == 3 &&
1494
3.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1495
3.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1496
3.01k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1497
3.01k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1498
      // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1499
375
      AsmString = "fbug,a,pn $\x03, $\x01";
1500
375
      break;
1501
375
    }
1502
2.63k
    if (MCInst_getNumOperands(MI) == 3 &&
1503
2.63k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1504
2.63k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1505
2.63k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1506
2.63k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1507
      // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1508
78
      AsmString = "fbl,a,pn $\x03, $\x01";
1509
78
      break;
1510
78
    }
1511
2.55k
    if (MCInst_getNumOperands(MI) == 3 &&
1512
2.55k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1513
2.55k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1514
2.55k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1515
2.55k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1516
      // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1517
205
      AsmString = "fbul,a,pn $\x03, $\x01";
1518
205
      break;
1519
205
    }
1520
2.35k
    if (MCInst_getNumOperands(MI) == 3 &&
1521
2.35k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1522
2.35k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1523
2.35k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1524
2.35k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1525
      // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1526
254
      AsmString = "fblg,a,pn $\x03, $\x01";
1527
254
      break;
1528
254
    }
1529
2.09k
    if (MCInst_getNumOperands(MI) == 3 &&
1530
2.09k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1531
2.09k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1532
2.09k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1533
2.09k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1534
      // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1535
1.12k
      AsmString = "fbne,a,pn $\x03, $\x01";
1536
1.12k
      break;
1537
1.12k
    }
1538
978
    if (MCInst_getNumOperands(MI) == 3 &&
1539
978
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1540
978
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1541
978
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1542
978
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1543
      // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1544
76
      AsmString = "fbe,a,pn $\x03, $\x01";
1545
76
      break;
1546
76
    }
1547
902
    if (MCInst_getNumOperands(MI) == 3 &&
1548
902
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1549
902
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1550
902
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1551
902
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1552
      // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1553
68
      AsmString = "fbue,a,pn $\x03, $\x01";
1554
68
      break;
1555
68
    }
1556
834
    if (MCInst_getNumOperands(MI) == 3 &&
1557
834
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1558
834
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1559
834
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1560
834
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1561
      // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1562
87
      AsmString = "fbge,a,pn $\x03, $\x01";
1563
87
      break;
1564
87
    }
1565
747
    if (MCInst_getNumOperands(MI) == 3 &&
1566
747
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1567
747
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1568
747
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1569
747
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1570
      // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1571
42
      AsmString = "fbuge,a,pn $\x03, $\x01";
1572
42
      break;
1573
42
    }
1574
705
    if (MCInst_getNumOperands(MI) == 3 &&
1575
705
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1576
705
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1577
705
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1578
705
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1579
      // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1580
256
      AsmString = "fble,a,pn $\x03, $\x01";
1581
256
      break;
1582
256
    }
1583
449
    if (MCInst_getNumOperands(MI) == 3 &&
1584
449
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1585
449
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1586
449
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1587
449
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1588
      // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1589
341
      AsmString = "fbule,a,pn $\x03, $\x01";
1590
341
      break;
1591
341
    }
1592
108
    if (MCInst_getNumOperands(MI) == 3 &&
1593
108
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1594
108
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1595
108
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1596
108
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1597
      // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1598
108
      AsmString = "fbo,a,pn $\x03, $\x01";
1599
108
      break;
1600
108
    }
1601
0
    return NULL;
1602
4.38k
  case SP_BPFCCNT:
1603
4.38k
    if (MCInst_getNumOperands(MI) == 3 &&
1604
4.38k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1605
4.38k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1606
4.38k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1607
4.38k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1608
      // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1609
342
      AsmString = "fba,pn $\x03, $\x01";
1610
342
      break;
1611
342
    }
1612
4.04k
    if (MCInst_getNumOperands(MI) == 3 &&
1613
4.04k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1614
4.04k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1615
4.04k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1616
4.04k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1617
      // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1618
82
      AsmString = "fbn,pn $\x03, $\x01";
1619
82
      break;
1620
82
    }
1621
3.95k
    if (MCInst_getNumOperands(MI) == 3 &&
1622
3.95k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
3.95k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1624
3.95k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1625
3.95k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1626
      // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1627
292
      AsmString = "fbu,pn $\x03, $\x01";
1628
292
      break;
1629
292
    }
1630
3.66k
    if (MCInst_getNumOperands(MI) == 3 &&
1631
3.66k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1632
3.66k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1633
3.66k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1634
3.66k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1635
      // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1636
270
      AsmString = "fbg,pn $\x03, $\x01";
1637
270
      break;
1638
270
    }
1639
3.39k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
3.39k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1641
3.39k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1642
3.39k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1643
3.39k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1644
      // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1645
224
      AsmString = "fbug,pn $\x03, $\x01";
1646
224
      break;
1647
224
    }
1648
3.17k
    if (MCInst_getNumOperands(MI) == 3 &&
1649
3.17k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1650
3.17k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1651
3.17k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1652
3.17k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1653
      // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1654
72
      AsmString = "fbl,pn $\x03, $\x01";
1655
72
      break;
1656
72
    }
1657
3.10k
    if (MCInst_getNumOperands(MI) == 3 &&
1658
3.10k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1659
3.10k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1660
3.10k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1661
3.10k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1662
      // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1663
93
      AsmString = "fbul,pn $\x03, $\x01";
1664
93
      break;
1665
93
    }
1666
3.00k
    if (MCInst_getNumOperands(MI) == 3 &&
1667
3.00k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1668
3.00k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1669
3.00k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1670
3.00k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1671
      // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1672
417
      AsmString = "fblg,pn $\x03, $\x01";
1673
417
      break;
1674
417
    }
1675
2.59k
    if (MCInst_getNumOperands(MI) == 3 &&
1676
2.59k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1677
2.59k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1678
2.59k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1679
2.59k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1680
      // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1681
132
      AsmString = "fbne,pn $\x03, $\x01";
1682
132
      break;
1683
132
    }
1684
2.45k
    if (MCInst_getNumOperands(MI) == 3 &&
1685
2.45k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1686
2.45k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1687
2.45k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1688
2.45k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1689
      // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1690
879
      AsmString = "fbe,pn $\x03, $\x01";
1691
879
      break;
1692
879
    }
1693
1.57k
    if (MCInst_getNumOperands(MI) == 3 &&
1694
1.57k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1695
1.57k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1696
1.57k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1697
1.57k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1698
      // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1699
523
      AsmString = "fbue,pn $\x03, $\x01";
1700
523
      break;
1701
523
    }
1702
1.05k
    if (MCInst_getNumOperands(MI) == 3 &&
1703
1.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1704
1.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1705
1.05k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1706
1.05k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1707
      // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1708
397
      AsmString = "fbge,pn $\x03, $\x01";
1709
397
      break;
1710
397
    }
1711
659
    if (MCInst_getNumOperands(MI) == 3 &&
1712
659
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1713
659
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1714
659
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1715
659
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1716
      // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1717
145
      AsmString = "fbuge,pn $\x03, $\x01";
1718
145
      break;
1719
145
    }
1720
514
    if (MCInst_getNumOperands(MI) == 3 &&
1721
514
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1722
514
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1723
514
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1724
514
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1725
      // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1726
99
      AsmString = "fble,pn $\x03, $\x01";
1727
99
      break;
1728
99
    }
1729
415
    if (MCInst_getNumOperands(MI) == 3 &&
1730
415
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1731
415
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1732
415
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1733
415
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1734
      // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1735
290
      AsmString = "fbule,pn $\x03, $\x01";
1736
290
      break;
1737
290
    }
1738
125
    if (MCInst_getNumOperands(MI) == 3 &&
1739
125
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1740
125
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1741
125
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1742
125
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1743
      // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1744
125
      AsmString = "fbo,pn $\x03, $\x01";
1745
125
      break;
1746
125
    }
1747
0
    return NULL;
1748
2.43k
  case SP_BPICCANT:
1749
2.43k
    if (MCInst_getNumOperands(MI) == 2 &&
1750
2.43k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1751
2.43k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1752
      // (BPICCANT brtarget:$imm, 8)
1753
245
      AsmString = "ba,a,pn %icc, $\x01";
1754
245
      break;
1755
245
    }
1756
2.19k
    if (MCInst_getNumOperands(MI) == 2 &&
1757
2.19k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
2.19k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1759
      // (BPICCANT brtarget:$imm, 0)
1760
211
      AsmString = "bn,a,pn %icc, $\x01";
1761
211
      break;
1762
211
    }
1763
1.98k
    if (MCInst_getNumOperands(MI) == 2 &&
1764
1.98k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1765
1.98k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1766
      // (BPICCANT brtarget:$imm, 9)
1767
20
      AsmString = "bne,a,pn %icc, $\x01";
1768
20
      break;
1769
20
    }
1770
1.96k
    if (MCInst_getNumOperands(MI) == 2 &&
1771
1.96k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1772
1.96k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1773
      // (BPICCANT brtarget:$imm, 1)
1774
69
      AsmString = "be,a,pn %icc, $\x01";
1775
69
      break;
1776
69
    }
1777
1.89k
    if (MCInst_getNumOperands(MI) == 2 &&
1778
1.89k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1779
1.89k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1780
      // (BPICCANT brtarget:$imm, 10)
1781
36
      AsmString = "bg,a,pn %icc, $\x01";
1782
36
      break;
1783
36
    }
1784
1.85k
    if (MCInst_getNumOperands(MI) == 2 &&
1785
1.85k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1786
1.85k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1787
      // (BPICCANT brtarget:$imm, 2)
1788
591
      AsmString = "ble,a,pn %icc, $\x01";
1789
591
      break;
1790
591
    }
1791
1.26k
    if (MCInst_getNumOperands(MI) == 2 &&
1792
1.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1793
1.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1794
      // (BPICCANT brtarget:$imm, 11)
1795
276
      AsmString = "bge,a,pn %icc, $\x01";
1796
276
      break;
1797
276
    }
1798
990
    if (MCInst_getNumOperands(MI) == 2 &&
1799
990
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1800
990
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1801
      // (BPICCANT brtarget:$imm, 3)
1802
80
      AsmString = "bl,a,pn %icc, $\x01";
1803
80
      break;
1804
80
    }
1805
910
    if (MCInst_getNumOperands(MI) == 2 &&
1806
910
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1807
910
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1808
      // (BPICCANT brtarget:$imm, 12)
1809
89
      AsmString = "bgu,a,pn %icc, $\x01";
1810
89
      break;
1811
89
    }
1812
821
    if (MCInst_getNumOperands(MI) == 2 &&
1813
821
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1814
821
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1815
      // (BPICCANT brtarget:$imm, 4)
1816
67
      AsmString = "bleu,a,pn %icc, $\x01";
1817
67
      break;
1818
67
    }
1819
754
    if (MCInst_getNumOperands(MI) == 2 &&
1820
754
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1821
754
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1822
      // (BPICCANT brtarget:$imm, 13)
1823
133
      AsmString = "bcc,a,pn %icc, $\x01";
1824
133
      break;
1825
133
    }
1826
621
    if (MCInst_getNumOperands(MI) == 2 &&
1827
621
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1828
621
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1829
      // (BPICCANT brtarget:$imm, 5)
1830
49
      AsmString = "bcs,a,pn %icc, $\x01";
1831
49
      break;
1832
49
    }
1833
572
    if (MCInst_getNumOperands(MI) == 2 &&
1834
572
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1835
572
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1836
      // (BPICCANT brtarget:$imm, 14)
1837
78
      AsmString = "bpos,a,pn %icc, $\x01";
1838
78
      break;
1839
78
    }
1840
494
    if (MCInst_getNumOperands(MI) == 2 &&
1841
494
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1842
494
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1843
      // (BPICCANT brtarget:$imm, 6)
1844
245
      AsmString = "bneg,a,pn %icc, $\x01";
1845
245
      break;
1846
245
    }
1847
249
    if (MCInst_getNumOperands(MI) == 2 &&
1848
249
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1849
249
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1850
      // (BPICCANT brtarget:$imm, 15)
1851
79
      AsmString = "bvc,a,pn %icc, $\x01";
1852
79
      break;
1853
79
    }
1854
170
    if (MCInst_getNumOperands(MI) == 2 &&
1855
170
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1856
170
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1857
      // (BPICCANT brtarget:$imm, 7)
1858
170
      AsmString = "bvs,a,pn %icc, $\x01";
1859
170
      break;
1860
170
    }
1861
0
    return NULL;
1862
4.22k
  case SP_BPICCNT:
1863
4.22k
    if (MCInst_getNumOperands(MI) == 2 &&
1864
4.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1865
4.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1866
      // (BPICCNT brtarget:$imm, 8)
1867
72
      AsmString = "ba,pn %icc, $\x01";
1868
72
      break;
1869
72
    }
1870
4.15k
    if (MCInst_getNumOperands(MI) == 2 &&
1871
4.15k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1872
4.15k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1873
      // (BPICCNT brtarget:$imm, 0)
1874
386
      AsmString = "bn,pn %icc, $\x01";
1875
386
      break;
1876
386
    }
1877
3.76k
    if (MCInst_getNumOperands(MI) == 2 &&
1878
3.76k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1879
3.76k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1880
      // (BPICCNT brtarget:$imm, 9)
1881
123
      AsmString = "bne,pn %icc, $\x01";
1882
123
      break;
1883
123
    }
1884
3.64k
    if (MCInst_getNumOperands(MI) == 2 &&
1885
3.64k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1886
3.64k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1887
      // (BPICCNT brtarget:$imm, 1)
1888
234
      AsmString = "be,pn %icc, $\x01";
1889
234
      break;
1890
234
    }
1891
3.40k
    if (MCInst_getNumOperands(MI) == 2 &&
1892
3.40k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1893
3.40k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1894
      // (BPICCNT brtarget:$imm, 10)
1895
451
      AsmString = "bg,pn %icc, $\x01";
1896
451
      break;
1897
451
    }
1898
2.95k
    if (MCInst_getNumOperands(MI) == 2 &&
1899
2.95k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1900
2.95k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1901
      // (BPICCNT brtarget:$imm, 2)
1902
115
      AsmString = "ble,pn %icc, $\x01";
1903
115
      break;
1904
115
    }
1905
2.84k
    if (MCInst_getNumOperands(MI) == 2 &&
1906
2.84k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1907
2.84k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1908
      // (BPICCNT brtarget:$imm, 11)
1909
734
      AsmString = "bge,pn %icc, $\x01";
1910
734
      break;
1911
734
    }
1912
2.10k
    if (MCInst_getNumOperands(MI) == 2 &&
1913
2.10k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1914
2.10k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1915
      // (BPICCNT brtarget:$imm, 3)
1916
67
      AsmString = "bl,pn %icc, $\x01";
1917
67
      break;
1918
67
    }
1919
2.04k
    if (MCInst_getNumOperands(MI) == 2 &&
1920
2.04k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1921
2.04k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1922
      // (BPICCNT brtarget:$imm, 12)
1923
530
      AsmString = "bgu,pn %icc, $\x01";
1924
530
      break;
1925
530
    }
1926
1.51k
    if (MCInst_getNumOperands(MI) == 2 &&
1927
1.51k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1928
1.51k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1929
      // (BPICCNT brtarget:$imm, 4)
1930
202
      AsmString = "bleu,pn %icc, $\x01";
1931
202
      break;
1932
202
    }
1933
1.30k
    if (MCInst_getNumOperands(MI) == 2 &&
1934
1.30k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1935
1.30k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1936
      // (BPICCNT brtarget:$imm, 13)
1937
446
      AsmString = "bcc,pn %icc, $\x01";
1938
446
      break;
1939
446
    }
1940
863
    if (MCInst_getNumOperands(MI) == 2 &&
1941
863
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1942
863
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1943
      // (BPICCNT brtarget:$imm, 5)
1944
82
      AsmString = "bcs,pn %icc, $\x01";
1945
82
      break;
1946
82
    }
1947
781
    if (MCInst_getNumOperands(MI) == 2 &&
1948
781
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1949
781
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1950
      // (BPICCNT brtarget:$imm, 14)
1951
68
      AsmString = "bpos,pn %icc, $\x01";
1952
68
      break;
1953
68
    }
1954
713
    if (MCInst_getNumOperands(MI) == 2 &&
1955
713
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1956
713
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1957
      // (BPICCNT brtarget:$imm, 6)
1958
68
      AsmString = "bneg,pn %icc, $\x01";
1959
68
      break;
1960
68
    }
1961
645
    if (MCInst_getNumOperands(MI) == 2 &&
1962
645
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1963
645
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1964
      // (BPICCNT brtarget:$imm, 15)
1965
439
      AsmString = "bvc,pn %icc, $\x01";
1966
439
      break;
1967
439
    }
1968
206
    if (MCInst_getNumOperands(MI) == 2 &&
1969
206
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1970
206
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1971
      // (BPICCNT brtarget:$imm, 7)
1972
206
      AsmString = "bvs,pn %icc, $\x01";
1973
206
      break;
1974
206
    }
1975
0
    return NULL;
1976
1.69k
  case SP_BPXCCANT:
1977
1.69k
    if (MCInst_getNumOperands(MI) == 2 &&
1978
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1979
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1980
      // (BPXCCANT brtarget:$imm, 8)
1981
71
      AsmString = "ba,a,pn %xcc, $\x01";
1982
71
      break;
1983
71
    }
1984
1.62k
    if (MCInst_getNumOperands(MI) == 2 &&
1985
1.62k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1986
1.62k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1987
      // (BPXCCANT brtarget:$imm, 0)
1988
205
      AsmString = "bn,a,pn %xcc, $\x01";
1989
205
      break;
1990
205
    }
1991
1.41k
    if (MCInst_getNumOperands(MI) == 2 &&
1992
1.41k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1993
1.41k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1994
      // (BPXCCANT brtarget:$imm, 9)
1995
26
      AsmString = "bne,a,pn %xcc, $\x01";
1996
26
      break;
1997
26
    }
1998
1.39k
    if (MCInst_getNumOperands(MI) == 2 &&
1999
1.39k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2000
1.39k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2001
      // (BPXCCANT brtarget:$imm, 1)
2002
89
      AsmString = "be,a,pn %xcc, $\x01";
2003
89
      break;
2004
89
    }
2005
1.30k
    if (MCInst_getNumOperands(MI) == 2 &&
2006
1.30k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2007
1.30k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2008
      // (BPXCCANT brtarget:$imm, 10)
2009
148
      AsmString = "bg,a,pn %xcc, $\x01";
2010
148
      break;
2011
148
    }
2012
1.15k
    if (MCInst_getNumOperands(MI) == 2 &&
2013
1.15k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2014
1.15k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2015
      // (BPXCCANT brtarget:$imm, 2)
2016
204
      AsmString = "ble,a,pn %xcc, $\x01";
2017
204
      break;
2018
204
    }
2019
951
    if (MCInst_getNumOperands(MI) == 2 &&
2020
951
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2021
951
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2022
      // (BPXCCANT brtarget:$imm, 11)
2023
90
      AsmString = "bge,a,pn %xcc, $\x01";
2024
90
      break;
2025
90
    }
2026
861
    if (MCInst_getNumOperands(MI) == 2 &&
2027
861
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2028
861
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2029
      // (BPXCCANT brtarget:$imm, 3)
2030
42
      AsmString = "bl,a,pn %xcc, $\x01";
2031
42
      break;
2032
42
    }
2033
819
    if (MCInst_getNumOperands(MI) == 2 &&
2034
819
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2035
819
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2036
      // (BPXCCANT brtarget:$imm, 12)
2037
21
      AsmString = "bgu,a,pn %xcc, $\x01";
2038
21
      break;
2039
21
    }
2040
798
    if (MCInst_getNumOperands(MI) == 2 &&
2041
798
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2042
798
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2043
      // (BPXCCANT brtarget:$imm, 4)
2044
74
      AsmString = "bleu,a,pn %xcc, $\x01";
2045
74
      break;
2046
74
    }
2047
724
    if (MCInst_getNumOperands(MI) == 2 &&
2048
724
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2049
724
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2050
      // (BPXCCANT brtarget:$imm, 13)
2051
88
      AsmString = "bcc,a,pn %xcc, $\x01";
2052
88
      break;
2053
88
    }
2054
636
    if (MCInst_getNumOperands(MI) == 2 &&
2055
636
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2056
636
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2057
      // (BPXCCANT brtarget:$imm, 5)
2058
67
      AsmString = "bcs,a,pn %xcc, $\x01";
2059
67
      break;
2060
67
    }
2061
569
    if (MCInst_getNumOperands(MI) == 2 &&
2062
569
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2063
569
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2064
      // (BPXCCANT brtarget:$imm, 14)
2065
110
      AsmString = "bpos,a,pn %xcc, $\x01";
2066
110
      break;
2067
110
    }
2068
459
    if (MCInst_getNumOperands(MI) == 2 &&
2069
459
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2070
459
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2071
      // (BPXCCANT brtarget:$imm, 6)
2072
175
      AsmString = "bneg,a,pn %xcc, $\x01";
2073
175
      break;
2074
175
    }
2075
284
    if (MCInst_getNumOperands(MI) == 2 &&
2076
284
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2077
284
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2078
      // (BPXCCANT brtarget:$imm, 15)
2079
73
      AsmString = "bvc,a,pn %xcc, $\x01";
2080
73
      break;
2081
73
    }
2082
211
    if (MCInst_getNumOperands(MI) == 2 &&
2083
211
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2084
211
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2085
      // (BPXCCANT brtarget:$imm, 7)
2086
211
      AsmString = "bvs,a,pn %xcc, $\x01";
2087
211
      break;
2088
211
    }
2089
0
    return NULL;
2090
1.76k
  case SP_BPXCCNT:
2091
1.76k
    if (MCInst_getNumOperands(MI) == 2 &&
2092
1.76k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2093
1.76k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2094
      // (BPXCCNT brtarget:$imm, 8)
2095
119
      AsmString = "ba,pn %xcc, $\x01";
2096
119
      break;
2097
119
    }
2098
1.64k
    if (MCInst_getNumOperands(MI) == 2 &&
2099
1.64k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2100
1.64k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2101
      // (BPXCCNT brtarget:$imm, 0)
2102
268
      AsmString = "bn,pn %xcc, $\x01";
2103
268
      break;
2104
268
    }
2105
1.37k
    if (MCInst_getNumOperands(MI) == 2 &&
2106
1.37k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2107
1.37k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2108
      // (BPXCCNT brtarget:$imm, 9)
2109
72
      AsmString = "bne,pn %xcc, $\x01";
2110
72
      break;
2111
72
    }
2112
1.30k
    if (MCInst_getNumOperands(MI) == 2 &&
2113
1.30k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2114
1.30k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2115
      // (BPXCCNT brtarget:$imm, 1)
2116
76
      AsmString = "be,pn %xcc, $\x01";
2117
76
      break;
2118
76
    }
2119
1.23k
    if (MCInst_getNumOperands(MI) == 2 &&
2120
1.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2121
1.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2122
      // (BPXCCNT brtarget:$imm, 10)
2123
111
      AsmString = "bg,pn %xcc, $\x01";
2124
111
      break;
2125
111
    }
2126
1.11k
    if (MCInst_getNumOperands(MI) == 2 &&
2127
1.11k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2128
1.11k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2129
      // (BPXCCNT brtarget:$imm, 2)
2130
107
      AsmString = "ble,pn %xcc, $\x01";
2131
107
      break;
2132
107
    }
2133
1.01k
    if (MCInst_getNumOperands(MI) == 2 &&
2134
1.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2135
1.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2136
      // (BPXCCNT brtarget:$imm, 11)
2137
90
      AsmString = "bge,pn %xcc, $\x01";
2138
90
      break;
2139
90
    }
2140
922
    if (MCInst_getNumOperands(MI) == 2 &&
2141
922
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2142
922
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2143
      // (BPXCCNT brtarget:$imm, 3)
2144
69
      AsmString = "bl,pn %xcc, $\x01";
2145
69
      break;
2146
69
    }
2147
853
    if (MCInst_getNumOperands(MI) == 2 &&
2148
853
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2149
853
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2150
      // (BPXCCNT brtarget:$imm, 12)
2151
67
      AsmString = "bgu,pn %xcc, $\x01";
2152
67
      break;
2153
67
    }
2154
786
    if (MCInst_getNumOperands(MI) == 2 &&
2155
786
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2156
786
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2157
      // (BPXCCNT brtarget:$imm, 4)
2158
68
      AsmString = "bleu,pn %xcc, $\x01";
2159
68
      break;
2160
68
    }
2161
718
    if (MCInst_getNumOperands(MI) == 2 &&
2162
718
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2163
718
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2164
      // (BPXCCNT brtarget:$imm, 13)
2165
70
      AsmString = "bcc,pn %xcc, $\x01";
2166
70
      break;
2167
70
    }
2168
648
    if (MCInst_getNumOperands(MI) == 2 &&
2169
648
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2170
648
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2171
      // (BPXCCNT brtarget:$imm, 5)
2172
208
      AsmString = "bcs,pn %xcc, $\x01";
2173
208
      break;
2174
208
    }
2175
440
    if (MCInst_getNumOperands(MI) == 2 &&
2176
440
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2177
440
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2178
      // (BPXCCNT brtarget:$imm, 14)
2179
34
      AsmString = "bpos,pn %xcc, $\x01";
2180
34
      break;
2181
34
    }
2182
406
    if (MCInst_getNumOperands(MI) == 2 &&
2183
406
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2184
406
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2185
      // (BPXCCNT brtarget:$imm, 6)
2186
71
      AsmString = "bneg,pn %xcc, $\x01";
2187
71
      break;
2188
71
    }
2189
335
    if (MCInst_getNumOperands(MI) == 2 &&
2190
335
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2191
335
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2192
      // (BPXCCNT brtarget:$imm, 15)
2193
258
      AsmString = "bvc,pn %xcc, $\x01";
2194
258
      break;
2195
258
    }
2196
77
    if (MCInst_getNumOperands(MI) == 2 &&
2197
77
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2198
77
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2199
      // (BPXCCNT brtarget:$imm, 7)
2200
77
      AsmString = "bvs,pn %xcc, $\x01";
2201
77
      break;
2202
77
    }
2203
0
    return NULL;
2204
95
  case SP_FMOVD_ICC:
2205
95
    if (MCInst_getNumOperands(MI) == 3 &&
2206
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2207
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2208
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2209
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2210
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2211
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2212
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2213
0
      AsmString = "fmovda %icc, $\x02, $\x01";
2214
0
      break;
2215
0
    }
2216
95
    if (MCInst_getNumOperands(MI) == 3 &&
2217
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2218
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2219
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2220
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2221
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2222
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2223
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2224
0
      AsmString = "fmovdn %icc, $\x02, $\x01";
2225
0
      break;
2226
0
    }
2227
95
    if (MCInst_getNumOperands(MI) == 3 &&
2228
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2229
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2230
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2231
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2232
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2233
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2234
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2235
0
      AsmString = "fmovdne %icc, $\x02, $\x01";
2236
0
      break;
2237
0
    }
2238
95
    if (MCInst_getNumOperands(MI) == 3 &&
2239
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2240
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2241
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2242
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2243
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2244
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2245
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2246
0
      AsmString = "fmovde %icc, $\x02, $\x01";
2247
0
      break;
2248
0
    }
2249
95
    if (MCInst_getNumOperands(MI) == 3 &&
2250
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2251
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2252
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2253
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2254
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2255
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2256
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2257
0
      AsmString = "fmovdg %icc, $\x02, $\x01";
2258
0
      break;
2259
0
    }
2260
95
    if (MCInst_getNumOperands(MI) == 3 &&
2261
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2262
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2263
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2264
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2265
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2266
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2267
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2268
0
      AsmString = "fmovdle %icc, $\x02, $\x01";
2269
0
      break;
2270
0
    }
2271
95
    if (MCInst_getNumOperands(MI) == 3 &&
2272
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2273
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2274
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2275
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2276
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2277
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2278
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2279
0
      AsmString = "fmovdge %icc, $\x02, $\x01";
2280
0
      break;
2281
0
    }
2282
95
    if (MCInst_getNumOperands(MI) == 3 &&
2283
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2285
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2287
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2288
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2289
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2290
0
      AsmString = "fmovdl %icc, $\x02, $\x01";
2291
0
      break;
2292
0
    }
2293
95
    if (MCInst_getNumOperands(MI) == 3 &&
2294
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2295
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2296
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2297
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2298
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2299
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2300
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2301
0
      AsmString = "fmovdgu %icc, $\x02, $\x01";
2302
0
      break;
2303
0
    }
2304
95
    if (MCInst_getNumOperands(MI) == 3 &&
2305
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2306
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2307
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2308
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2309
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2310
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2311
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2312
0
      AsmString = "fmovdleu %icc, $\x02, $\x01";
2313
0
      break;
2314
0
    }
2315
95
    if (MCInst_getNumOperands(MI) == 3 &&
2316
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2317
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2318
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2319
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2320
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2321
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2322
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2323
0
      AsmString = "fmovdcc %icc, $\x02, $\x01";
2324
0
      break;
2325
0
    }
2326
95
    if (MCInst_getNumOperands(MI) == 3 &&
2327
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2328
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2329
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2330
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2331
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2332
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2333
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2334
0
      AsmString = "fmovdcs %icc, $\x02, $\x01";
2335
0
      break;
2336
0
    }
2337
95
    if (MCInst_getNumOperands(MI) == 3 &&
2338
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2339
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2340
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2341
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2342
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2343
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2344
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2345
0
      AsmString = "fmovdpos %icc, $\x02, $\x01";
2346
0
      break;
2347
0
    }
2348
95
    if (MCInst_getNumOperands(MI) == 3 &&
2349
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2350
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2351
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2352
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2353
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2354
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2355
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2356
0
      AsmString = "fmovdneg %icc, $\x02, $\x01";
2357
0
      break;
2358
0
    }
2359
95
    if (MCInst_getNumOperands(MI) == 3 &&
2360
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2361
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2362
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2363
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2364
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2365
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2366
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2367
0
      AsmString = "fmovdvc %icc, $\x02, $\x01";
2368
0
      break;
2369
0
    }
2370
95
    if (MCInst_getNumOperands(MI) == 3 &&
2371
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2372
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2373
95
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2374
95
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2375
95
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2376
95
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2377
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2378
0
      AsmString = "fmovdvs %icc, $\x02, $\x01";
2379
0
      break;
2380
0
    }
2381
95
    return NULL;
2382
20
  case SP_FMOVD_XCC:
2383
20
    if (MCInst_getNumOperands(MI) == 3 &&
2384
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2385
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2386
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2387
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2388
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2389
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2390
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2391
0
      AsmString = "fmovda %xcc, $\x02, $\x01";
2392
0
      break;
2393
0
    }
2394
20
    if (MCInst_getNumOperands(MI) == 3 &&
2395
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2396
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2397
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2398
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2399
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2400
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2401
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2402
0
      AsmString = "fmovdn %xcc, $\x02, $\x01";
2403
0
      break;
2404
0
    }
2405
20
    if (MCInst_getNumOperands(MI) == 3 &&
2406
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2407
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2408
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2409
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2410
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2411
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2412
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2413
0
      AsmString = "fmovdne %xcc, $\x02, $\x01";
2414
0
      break;
2415
0
    }
2416
20
    if (MCInst_getNumOperands(MI) == 3 &&
2417
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2418
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2419
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2420
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2421
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2422
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2423
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2424
0
      AsmString = "fmovde %xcc, $\x02, $\x01";
2425
0
      break;
2426
0
    }
2427
20
    if (MCInst_getNumOperands(MI) == 3 &&
2428
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2429
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2430
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2431
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2432
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2433
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2434
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2435
0
      AsmString = "fmovdg %xcc, $\x02, $\x01";
2436
0
      break;
2437
0
    }
2438
20
    if (MCInst_getNumOperands(MI) == 3 &&
2439
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2440
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2441
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2442
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2443
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2444
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2445
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2446
0
      AsmString = "fmovdle %xcc, $\x02, $\x01";
2447
0
      break;
2448
0
    }
2449
20
    if (MCInst_getNumOperands(MI) == 3 &&
2450
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2451
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2452
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2453
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2454
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2455
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2456
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2457
0
      AsmString = "fmovdge %xcc, $\x02, $\x01";
2458
0
      break;
2459
0
    }
2460
20
    if (MCInst_getNumOperands(MI) == 3 &&
2461
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2462
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2463
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2464
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2465
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2466
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2467
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2468
0
      AsmString = "fmovdl %xcc, $\x02, $\x01";
2469
0
      break;
2470
0
    }
2471
20
    if (MCInst_getNumOperands(MI) == 3 &&
2472
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2473
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2474
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2475
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2476
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2477
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2478
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2479
0
      AsmString = "fmovdgu %xcc, $\x02, $\x01";
2480
0
      break;
2481
0
    }
2482
20
    if (MCInst_getNumOperands(MI) == 3 &&
2483
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2484
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2485
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2486
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2487
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2488
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2489
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2490
0
      AsmString = "fmovdleu %xcc, $\x02, $\x01";
2491
0
      break;
2492
0
    }
2493
20
    if (MCInst_getNumOperands(MI) == 3 &&
2494
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2495
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2496
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2497
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2498
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2499
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2500
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2501
0
      AsmString = "fmovdcc %xcc, $\x02, $\x01";
2502
0
      break;
2503
0
    }
2504
20
    if (MCInst_getNumOperands(MI) == 3 &&
2505
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2506
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2507
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2508
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2509
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2510
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2511
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2512
0
      AsmString = "fmovdcs %xcc, $\x02, $\x01";
2513
0
      break;
2514
0
    }
2515
20
    if (MCInst_getNumOperands(MI) == 3 &&
2516
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2518
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2519
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2520
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2521
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2522
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2523
0
      AsmString = "fmovdpos %xcc, $\x02, $\x01";
2524
0
      break;
2525
0
    }
2526
20
    if (MCInst_getNumOperands(MI) == 3 &&
2527
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2528
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2529
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2530
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2531
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2532
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2533
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2534
0
      AsmString = "fmovdneg %xcc, $\x02, $\x01";
2535
0
      break;
2536
0
    }
2537
20
    if (MCInst_getNumOperands(MI) == 3 &&
2538
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2539
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2540
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2541
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2542
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2543
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2544
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2545
0
      AsmString = "fmovdvc %xcc, $\x02, $\x01";
2546
0
      break;
2547
0
    }
2548
20
    if (MCInst_getNumOperands(MI) == 3 &&
2549
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2550
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2551
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2552
20
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2553
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2554
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2555
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2556
0
      AsmString = "fmovdvs %xcc, $\x02, $\x01";
2557
0
      break;
2558
0
    }
2559
20
    return NULL;
2560
24
  case SP_FMOVQ_ICC:
2561
24
    if (MCInst_getNumOperands(MI) == 3 &&
2562
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2563
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2564
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2565
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2566
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2567
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2568
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2569
0
      AsmString = "fmovqa %icc, $\x02, $\x01";
2570
0
      break;
2571
0
    }
2572
24
    if (MCInst_getNumOperands(MI) == 3 &&
2573
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2574
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2575
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2576
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2577
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2578
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2579
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2580
0
      AsmString = "fmovqn %icc, $\x02, $\x01";
2581
0
      break;
2582
0
    }
2583
24
    if (MCInst_getNumOperands(MI) == 3 &&
2584
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2585
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2586
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2587
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2588
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2589
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2590
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2591
0
      AsmString = "fmovqne %icc, $\x02, $\x01";
2592
0
      break;
2593
0
    }
2594
24
    if (MCInst_getNumOperands(MI) == 3 &&
2595
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2596
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2597
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2598
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2599
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2600
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2601
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2602
0
      AsmString = "fmovqe %icc, $\x02, $\x01";
2603
0
      break;
2604
0
    }
2605
24
    if (MCInst_getNumOperands(MI) == 3 &&
2606
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2607
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2608
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2609
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2610
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2611
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2612
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2613
0
      AsmString = "fmovqg %icc, $\x02, $\x01";
2614
0
      break;
2615
0
    }
2616
24
    if (MCInst_getNumOperands(MI) == 3 &&
2617
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2618
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2619
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2620
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2621
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2622
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2623
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2624
0
      AsmString = "fmovqle %icc, $\x02, $\x01";
2625
0
      break;
2626
0
    }
2627
24
    if (MCInst_getNumOperands(MI) == 3 &&
2628
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2629
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2630
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2631
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2632
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2633
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2634
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2635
0
      AsmString = "fmovqge %icc, $\x02, $\x01";
2636
0
      break;
2637
0
    }
2638
24
    if (MCInst_getNumOperands(MI) == 3 &&
2639
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2640
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2641
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2642
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2643
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2644
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2645
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2646
0
      AsmString = "fmovql %icc, $\x02, $\x01";
2647
0
      break;
2648
0
    }
2649
24
    if (MCInst_getNumOperands(MI) == 3 &&
2650
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2651
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2652
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2653
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2654
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2655
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2656
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2657
0
      AsmString = "fmovqgu %icc, $\x02, $\x01";
2658
0
      break;
2659
0
    }
2660
24
    if (MCInst_getNumOperands(MI) == 3 &&
2661
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2662
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2663
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2664
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2665
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2666
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2667
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2668
0
      AsmString = "fmovqleu %icc, $\x02, $\x01";
2669
0
      break;
2670
0
    }
2671
24
    if (MCInst_getNumOperands(MI) == 3 &&
2672
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2673
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2674
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2675
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2676
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2677
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2678
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2679
0
      AsmString = "fmovqcc %icc, $\x02, $\x01";
2680
0
      break;
2681
0
    }
2682
24
    if (MCInst_getNumOperands(MI) == 3 &&
2683
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2684
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2685
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2686
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2687
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2688
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2689
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2690
0
      AsmString = "fmovqcs %icc, $\x02, $\x01";
2691
0
      break;
2692
0
    }
2693
24
    if (MCInst_getNumOperands(MI) == 3 &&
2694
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2695
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2696
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2697
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2698
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2699
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2700
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2701
0
      AsmString = "fmovqpos %icc, $\x02, $\x01";
2702
0
      break;
2703
0
    }
2704
24
    if (MCInst_getNumOperands(MI) == 3 &&
2705
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2706
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2707
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2708
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2709
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2710
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2711
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2712
0
      AsmString = "fmovqneg %icc, $\x02, $\x01";
2713
0
      break;
2714
0
    }
2715
24
    if (MCInst_getNumOperands(MI) == 3 &&
2716
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2717
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2718
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2719
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2720
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2721
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2722
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2723
0
      AsmString = "fmovqvc %icc, $\x02, $\x01";
2724
0
      break;
2725
0
    }
2726
24
    if (MCInst_getNumOperands(MI) == 3 &&
2727
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2728
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2729
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2730
24
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2731
24
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2732
24
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2733
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2734
0
      AsmString = "fmovqvs %icc, $\x02, $\x01";
2735
0
      break;
2736
0
    }
2737
24
    return NULL;
2738
58
  case SP_FMOVQ_XCC:
2739
58
    if (MCInst_getNumOperands(MI) == 3 &&
2740
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2741
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2742
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2743
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2744
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2745
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2746
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2747
0
      AsmString = "fmovqa %xcc, $\x02, $\x01";
2748
0
      break;
2749
0
    }
2750
58
    if (MCInst_getNumOperands(MI) == 3 &&
2751
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2752
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2753
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2754
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2755
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2756
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2757
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2758
0
      AsmString = "fmovqn %xcc, $\x02, $\x01";
2759
0
      break;
2760
0
    }
2761
58
    if (MCInst_getNumOperands(MI) == 3 &&
2762
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2763
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2764
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2765
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2766
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2767
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2768
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2769
0
      AsmString = "fmovqne %xcc, $\x02, $\x01";
2770
0
      break;
2771
0
    }
2772
58
    if (MCInst_getNumOperands(MI) == 3 &&
2773
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2774
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2775
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2776
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2777
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2778
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2779
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2780
0
      AsmString = "fmovqe %xcc, $\x02, $\x01";
2781
0
      break;
2782
0
    }
2783
58
    if (MCInst_getNumOperands(MI) == 3 &&
2784
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2785
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2786
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2787
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2788
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2789
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2790
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2791
0
      AsmString = "fmovqg %xcc, $\x02, $\x01";
2792
0
      break;
2793
0
    }
2794
58
    if (MCInst_getNumOperands(MI) == 3 &&
2795
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2796
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2797
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2798
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2799
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2800
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2801
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2802
0
      AsmString = "fmovqle %xcc, $\x02, $\x01";
2803
0
      break;
2804
0
    }
2805
58
    if (MCInst_getNumOperands(MI) == 3 &&
2806
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2807
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2808
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2809
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2810
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2811
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2812
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2813
0
      AsmString = "fmovqge %xcc, $\x02, $\x01";
2814
0
      break;
2815
0
    }
2816
58
    if (MCInst_getNumOperands(MI) == 3 &&
2817
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2818
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2819
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2820
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2821
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2822
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2823
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2824
0
      AsmString = "fmovql %xcc, $\x02, $\x01";
2825
0
      break;
2826
0
    }
2827
58
    if (MCInst_getNumOperands(MI) == 3 &&
2828
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2829
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2830
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2831
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2832
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2834
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2835
0
      AsmString = "fmovqgu %xcc, $\x02, $\x01";
2836
0
      break;
2837
0
    }
2838
58
    if (MCInst_getNumOperands(MI) == 3 &&
2839
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2840
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2841
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2842
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2843
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2844
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2845
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2846
0
      AsmString = "fmovqleu %xcc, $\x02, $\x01";
2847
0
      break;
2848
0
    }
2849
58
    if (MCInst_getNumOperands(MI) == 3 &&
2850
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2851
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2852
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2853
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2854
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2855
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2856
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2857
0
      AsmString = "fmovqcc %xcc, $\x02, $\x01";
2858
0
      break;
2859
0
    }
2860
58
    if (MCInst_getNumOperands(MI) == 3 &&
2861
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2862
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2863
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2864
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2865
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2866
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2867
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2868
0
      AsmString = "fmovqcs %xcc, $\x02, $\x01";
2869
0
      break;
2870
0
    }
2871
58
    if (MCInst_getNumOperands(MI) == 3 &&
2872
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2873
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2874
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2875
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2876
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2877
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2878
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2879
0
      AsmString = "fmovqpos %xcc, $\x02, $\x01";
2880
0
      break;
2881
0
    }
2882
58
    if (MCInst_getNumOperands(MI) == 3 &&
2883
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2884
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2885
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2886
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2887
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2888
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2889
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2890
0
      AsmString = "fmovqneg %xcc, $\x02, $\x01";
2891
0
      break;
2892
0
    }
2893
58
    if (MCInst_getNumOperands(MI) == 3 &&
2894
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2895
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2896
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2897
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2898
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2899
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2900
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2901
0
      AsmString = "fmovqvc %xcc, $\x02, $\x01";
2902
0
      break;
2903
0
    }
2904
58
    if (MCInst_getNumOperands(MI) == 3 &&
2905
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2906
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2907
58
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2908
58
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2909
58
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2910
58
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2911
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2912
0
      AsmString = "fmovqvs %xcc, $\x02, $\x01";
2913
0
      break;
2914
0
    }
2915
58
    return NULL;
2916
48
  case SP_FMOVS_ICC:
2917
48
    if (MCInst_getNumOperands(MI) == 3 &&
2918
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2919
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2920
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2921
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2922
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2923
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2924
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2925
0
      AsmString = "fmovsa %icc, $\x02, $\x01";
2926
0
      break;
2927
0
    }
2928
48
    if (MCInst_getNumOperands(MI) == 3 &&
2929
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2930
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2931
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2932
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2933
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2934
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2935
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2936
0
      AsmString = "fmovsn %icc, $\x02, $\x01";
2937
0
      break;
2938
0
    }
2939
48
    if (MCInst_getNumOperands(MI) == 3 &&
2940
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2941
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2942
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2943
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2944
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2945
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2946
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2947
0
      AsmString = "fmovsne %icc, $\x02, $\x01";
2948
0
      break;
2949
0
    }
2950
48
    if (MCInst_getNumOperands(MI) == 3 &&
2951
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2952
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2953
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2954
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2955
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2956
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2957
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2958
0
      AsmString = "fmovse %icc, $\x02, $\x01";
2959
0
      break;
2960
0
    }
2961
48
    if (MCInst_getNumOperands(MI) == 3 &&
2962
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2963
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2964
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2965
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2966
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2967
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2968
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2969
0
      AsmString = "fmovsg %icc, $\x02, $\x01";
2970
0
      break;
2971
0
    }
2972
48
    if (MCInst_getNumOperands(MI) == 3 &&
2973
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2974
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2975
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2976
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2977
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2978
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2979
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2980
0
      AsmString = "fmovsle %icc, $\x02, $\x01";
2981
0
      break;
2982
0
    }
2983
48
    if (MCInst_getNumOperands(MI) == 3 &&
2984
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2985
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2986
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2987
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2988
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2989
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2990
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2991
0
      AsmString = "fmovsge %icc, $\x02, $\x01";
2992
0
      break;
2993
0
    }
2994
48
    if (MCInst_getNumOperands(MI) == 3 &&
2995
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2996
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2997
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2998
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2999
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3000
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3001
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3002
0
      AsmString = "fmovsl %icc, $\x02, $\x01";
3003
0
      break;
3004
0
    }
3005
48
    if (MCInst_getNumOperands(MI) == 3 &&
3006
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3007
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3008
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3009
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3010
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3011
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3012
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3013
0
      AsmString = "fmovsgu %icc, $\x02, $\x01";
3014
0
      break;
3015
0
    }
3016
48
    if (MCInst_getNumOperands(MI) == 3 &&
3017
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3018
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3019
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3020
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3021
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3022
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3023
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3024
0
      AsmString = "fmovsleu %icc, $\x02, $\x01";
3025
0
      break;
3026
0
    }
3027
48
    if (MCInst_getNumOperands(MI) == 3 &&
3028
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3029
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3030
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3031
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3032
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3033
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3034
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3035
0
      AsmString = "fmovscc %icc, $\x02, $\x01";
3036
0
      break;
3037
0
    }
3038
48
    if (MCInst_getNumOperands(MI) == 3 &&
3039
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3040
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3041
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3042
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3043
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3044
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3045
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3046
0
      AsmString = "fmovscs %icc, $\x02, $\x01";
3047
0
      break;
3048
0
    }
3049
48
    if (MCInst_getNumOperands(MI) == 3 &&
3050
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3051
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3052
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3053
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3054
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3055
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3056
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3057
0
      AsmString = "fmovspos %icc, $\x02, $\x01";
3058
0
      break;
3059
0
    }
3060
48
    if (MCInst_getNumOperands(MI) == 3 &&
3061
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3062
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3063
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3064
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3065
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3066
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3067
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3068
0
      AsmString = "fmovsneg %icc, $\x02, $\x01";
3069
0
      break;
3070
0
    }
3071
48
    if (MCInst_getNumOperands(MI) == 3 &&
3072
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3073
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3074
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3075
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3076
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3077
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3078
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3079
0
      AsmString = "fmovsvc %icc, $\x02, $\x01";
3080
0
      break;
3081
0
    }
3082
48
    if (MCInst_getNumOperands(MI) == 3 &&
3083
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3084
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3085
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3086
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3087
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3088
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3089
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3090
0
      AsmString = "fmovsvs %icc, $\x02, $\x01";
3091
0
      break;
3092
0
    }
3093
48
    return NULL;
3094
22
  case SP_FMOVS_XCC:
3095
22
    if (MCInst_getNumOperands(MI) == 3 &&
3096
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3097
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3098
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3099
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3100
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3101
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3102
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3103
0
      AsmString = "fmovsa %xcc, $\x02, $\x01";
3104
0
      break;
3105
0
    }
3106
22
    if (MCInst_getNumOperands(MI) == 3 &&
3107
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3108
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3109
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3110
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3111
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3112
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3113
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3114
0
      AsmString = "fmovsn %xcc, $\x02, $\x01";
3115
0
      break;
3116
0
    }
3117
22
    if (MCInst_getNumOperands(MI) == 3 &&
3118
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3119
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3120
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3121
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3122
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3123
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3124
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3125
0
      AsmString = "fmovsne %xcc, $\x02, $\x01";
3126
0
      break;
3127
0
    }
3128
22
    if (MCInst_getNumOperands(MI) == 3 &&
3129
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3130
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3131
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3132
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3133
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3134
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3135
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3136
0
      AsmString = "fmovse %xcc, $\x02, $\x01";
3137
0
      break;
3138
0
    }
3139
22
    if (MCInst_getNumOperands(MI) == 3 &&
3140
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3141
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3142
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3143
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3144
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3145
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3146
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3147
0
      AsmString = "fmovsg %xcc, $\x02, $\x01";
3148
0
      break;
3149
0
    }
3150
22
    if (MCInst_getNumOperands(MI) == 3 &&
3151
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3152
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3153
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3154
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3155
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3156
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3157
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3158
0
      AsmString = "fmovsle %xcc, $\x02, $\x01";
3159
0
      break;
3160
0
    }
3161
22
    if (MCInst_getNumOperands(MI) == 3 &&
3162
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3163
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3164
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3165
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3166
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3167
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3168
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3169
0
      AsmString = "fmovsge %xcc, $\x02, $\x01";
3170
0
      break;
3171
0
    }
3172
22
    if (MCInst_getNumOperands(MI) == 3 &&
3173
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3174
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3175
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3176
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3177
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3178
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3179
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3180
0
      AsmString = "fmovsl %xcc, $\x02, $\x01";
3181
0
      break;
3182
0
    }
3183
22
    if (MCInst_getNumOperands(MI) == 3 &&
3184
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3185
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3186
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3187
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3188
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3190
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3191
0
      AsmString = "fmovsgu %xcc, $\x02, $\x01";
3192
0
      break;
3193
0
    }
3194
22
    if (MCInst_getNumOperands(MI) == 3 &&
3195
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3196
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3197
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3198
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3199
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3200
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3201
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3202
0
      AsmString = "fmovsleu %xcc, $\x02, $\x01";
3203
0
      break;
3204
0
    }
3205
22
    if (MCInst_getNumOperands(MI) == 3 &&
3206
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3207
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3208
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3209
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3210
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3211
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3212
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3213
0
      AsmString = "fmovscc %xcc, $\x02, $\x01";
3214
0
      break;
3215
0
    }
3216
22
    if (MCInst_getNumOperands(MI) == 3 &&
3217
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3218
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3219
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3220
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3221
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3222
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3223
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3224
0
      AsmString = "fmovscs %xcc, $\x02, $\x01";
3225
0
      break;
3226
0
    }
3227
22
    if (MCInst_getNumOperands(MI) == 3 &&
3228
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3229
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3230
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3231
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3232
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3233
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3234
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3235
0
      AsmString = "fmovspos %xcc, $\x02, $\x01";
3236
0
      break;
3237
0
    }
3238
22
    if (MCInst_getNumOperands(MI) == 3 &&
3239
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3240
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3241
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3242
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3243
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3244
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3245
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3246
0
      AsmString = "fmovsneg %xcc, $\x02, $\x01";
3247
0
      break;
3248
0
    }
3249
22
    if (MCInst_getNumOperands(MI) == 3 &&
3250
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3251
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3252
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3253
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3254
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3255
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3256
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3257
0
      AsmString = "fmovsvc %xcc, $\x02, $\x01";
3258
0
      break;
3259
0
    }
3260
22
    if (MCInst_getNumOperands(MI) == 3 &&
3261
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3262
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3263
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3264
22
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3265
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3266
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3267
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3268
0
      AsmString = "fmovsvs %xcc, $\x02, $\x01";
3269
0
      break;
3270
0
    }
3271
22
    return NULL;
3272
76
  case SP_MOVICCri:
3273
76
    if (MCInst_getNumOperands(MI) == 3 &&
3274
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3275
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3276
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3277
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3278
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3279
0
      AsmString = "mova %icc, $\x02, $\x01";
3280
0
      break;
3281
0
    }
3282
76
    if (MCInst_getNumOperands(MI) == 3 &&
3283
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3284
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3285
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3286
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3287
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3288
0
      AsmString = "movn %icc, $\x02, $\x01";
3289
0
      break;
3290
0
    }
3291
76
    if (MCInst_getNumOperands(MI) == 3 &&
3292
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3293
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3294
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3295
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3296
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3297
0
      AsmString = "movne %icc, $\x02, $\x01";
3298
0
      break;
3299
0
    }
3300
76
    if (MCInst_getNumOperands(MI) == 3 &&
3301
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3302
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3303
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3304
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3305
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3306
0
      AsmString = "move %icc, $\x02, $\x01";
3307
0
      break;
3308
0
    }
3309
76
    if (MCInst_getNumOperands(MI) == 3 &&
3310
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3311
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3312
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3313
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3314
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3315
0
      AsmString = "movg %icc, $\x02, $\x01";
3316
0
      break;
3317
0
    }
3318
76
    if (MCInst_getNumOperands(MI) == 3 &&
3319
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3320
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3321
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3322
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3323
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3324
0
      AsmString = "movle %icc, $\x02, $\x01";
3325
0
      break;
3326
0
    }
3327
76
    if (MCInst_getNumOperands(MI) == 3 &&
3328
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3329
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3330
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3331
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3332
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3333
0
      AsmString = "movge %icc, $\x02, $\x01";
3334
0
      break;
3335
0
    }
3336
76
    if (MCInst_getNumOperands(MI) == 3 &&
3337
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3338
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3339
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3340
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3341
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3342
0
      AsmString = "movl %icc, $\x02, $\x01";
3343
0
      break;
3344
0
    }
3345
76
    if (MCInst_getNumOperands(MI) == 3 &&
3346
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3347
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3348
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3349
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3350
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3351
0
      AsmString = "movgu %icc, $\x02, $\x01";
3352
0
      break;
3353
0
    }
3354
76
    if (MCInst_getNumOperands(MI) == 3 &&
3355
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3356
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3357
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3358
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3359
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3360
0
      AsmString = "movleu %icc, $\x02, $\x01";
3361
0
      break;
3362
0
    }
3363
76
    if (MCInst_getNumOperands(MI) == 3 &&
3364
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3365
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3366
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3367
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3368
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3369
0
      AsmString = "movcc %icc, $\x02, $\x01";
3370
0
      break;
3371
0
    }
3372
76
    if (MCInst_getNumOperands(MI) == 3 &&
3373
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3374
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3375
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3376
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3377
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3378
0
      AsmString = "movcs %icc, $\x02, $\x01";
3379
0
      break;
3380
0
    }
3381
76
    if (MCInst_getNumOperands(MI) == 3 &&
3382
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3383
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3384
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3385
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3386
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3387
0
      AsmString = "movpos %icc, $\x02, $\x01";
3388
0
      break;
3389
0
    }
3390
76
    if (MCInst_getNumOperands(MI) == 3 &&
3391
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3392
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3393
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3394
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3395
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3396
0
      AsmString = "movneg %icc, $\x02, $\x01";
3397
0
      break;
3398
0
    }
3399
76
    if (MCInst_getNumOperands(MI) == 3 &&
3400
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3401
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3402
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3403
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3404
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3405
0
      AsmString = "movvc %icc, $\x02, $\x01";
3406
0
      break;
3407
0
    }
3408
76
    if (MCInst_getNumOperands(MI) == 3 &&
3409
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3410
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3411
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3412
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3413
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3414
0
      AsmString = "movvs %icc, $\x02, $\x01";
3415
0
      break;
3416
0
    }
3417
76
    return NULL;
3418
132
  case SP_MOVICCrr:
3419
132
    if (MCInst_getNumOperands(MI) == 3 &&
3420
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3421
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3422
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3423
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3424
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3425
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3426
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3427
0
      AsmString = "mova %icc, $\x02, $\x01";
3428
0
      break;
3429
0
    }
3430
132
    if (MCInst_getNumOperands(MI) == 3 &&
3431
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3432
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3433
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3434
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3435
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3436
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3437
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3438
0
      AsmString = "movn %icc, $\x02, $\x01";
3439
0
      break;
3440
0
    }
3441
132
    if (MCInst_getNumOperands(MI) == 3 &&
3442
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3443
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3444
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3445
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3446
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3447
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3448
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3449
0
      AsmString = "movne %icc, $\x02, $\x01";
3450
0
      break;
3451
0
    }
3452
132
    if (MCInst_getNumOperands(MI) == 3 &&
3453
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3454
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3455
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3456
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3457
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3458
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3459
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3460
0
      AsmString = "move %icc, $\x02, $\x01";
3461
0
      break;
3462
0
    }
3463
132
    if (MCInst_getNumOperands(MI) == 3 &&
3464
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3465
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3466
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3467
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3468
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3469
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3470
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3471
0
      AsmString = "movg %icc, $\x02, $\x01";
3472
0
      break;
3473
0
    }
3474
132
    if (MCInst_getNumOperands(MI) == 3 &&
3475
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3476
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3477
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3478
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3479
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3480
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3481
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3482
0
      AsmString = "movle %icc, $\x02, $\x01";
3483
0
      break;
3484
0
    }
3485
132
    if (MCInst_getNumOperands(MI) == 3 &&
3486
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3487
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3488
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3489
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3490
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3491
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3492
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3493
0
      AsmString = "movge %icc, $\x02, $\x01";
3494
0
      break;
3495
0
    }
3496
132
    if (MCInst_getNumOperands(MI) == 3 &&
3497
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3498
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3499
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3500
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3501
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3502
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3503
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3504
0
      AsmString = "movl %icc, $\x02, $\x01";
3505
0
      break;
3506
0
    }
3507
132
    if (MCInst_getNumOperands(MI) == 3 &&
3508
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3509
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3510
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3511
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3512
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3513
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3514
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3515
0
      AsmString = "movgu %icc, $\x02, $\x01";
3516
0
      break;
3517
0
    }
3518
132
    if (MCInst_getNumOperands(MI) == 3 &&
3519
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3520
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3521
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3522
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3523
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3524
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3525
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3526
0
      AsmString = "movleu %icc, $\x02, $\x01";
3527
0
      break;
3528
0
    }
3529
132
    if (MCInst_getNumOperands(MI) == 3 &&
3530
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3531
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3532
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3533
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3534
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3535
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3536
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3537
0
      AsmString = "movcc %icc, $\x02, $\x01";
3538
0
      break;
3539
0
    }
3540
132
    if (MCInst_getNumOperands(MI) == 3 &&
3541
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3542
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3543
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3544
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3545
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3546
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3547
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3548
0
      AsmString = "movcs %icc, $\x02, $\x01";
3549
0
      break;
3550
0
    }
3551
132
    if (MCInst_getNumOperands(MI) == 3 &&
3552
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3553
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3554
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3555
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3556
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3557
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3558
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3559
0
      AsmString = "movpos %icc, $\x02, $\x01";
3560
0
      break;
3561
0
    }
3562
132
    if (MCInst_getNumOperands(MI) == 3 &&
3563
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3564
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3565
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3566
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3567
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3568
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3569
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3570
0
      AsmString = "movneg %icc, $\x02, $\x01";
3571
0
      break;
3572
0
    }
3573
132
    if (MCInst_getNumOperands(MI) == 3 &&
3574
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3575
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3576
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3577
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3578
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3579
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3580
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3581
0
      AsmString = "movvc %icc, $\x02, $\x01";
3582
0
      break;
3583
0
    }
3584
132
    if (MCInst_getNumOperands(MI) == 3 &&
3585
132
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3586
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3587
132
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3588
132
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3589
132
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3590
132
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3591
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3592
0
      AsmString = "movvs %icc, $\x02, $\x01";
3593
0
      break;
3594
0
    }
3595
132
    return NULL;
3596
84
  case SP_MOVXCCri:
3597
84
    if (MCInst_getNumOperands(MI) == 3 &&
3598
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3599
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3600
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3601
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3602
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3603
0
      AsmString = "mova %xcc, $\x02, $\x01";
3604
0
      break;
3605
0
    }
3606
84
    if (MCInst_getNumOperands(MI) == 3 &&
3607
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3608
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3609
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3610
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3611
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3612
0
      AsmString = "movn %xcc, $\x02, $\x01";
3613
0
      break;
3614
0
    }
3615
84
    if (MCInst_getNumOperands(MI) == 3 &&
3616
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3617
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3618
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3619
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3620
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3621
0
      AsmString = "movne %xcc, $\x02, $\x01";
3622
0
      break;
3623
0
    }
3624
84
    if (MCInst_getNumOperands(MI) == 3 &&
3625
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3626
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3627
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3628
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3629
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3630
0
      AsmString = "move %xcc, $\x02, $\x01";
3631
0
      break;
3632
0
    }
3633
84
    if (MCInst_getNumOperands(MI) == 3 &&
3634
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3635
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3636
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3637
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3638
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3639
0
      AsmString = "movg %xcc, $\x02, $\x01";
3640
0
      break;
3641
0
    }
3642
84
    if (MCInst_getNumOperands(MI) == 3 &&
3643
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3644
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3645
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3646
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3647
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3648
0
      AsmString = "movle %xcc, $\x02, $\x01";
3649
0
      break;
3650
0
    }
3651
84
    if (MCInst_getNumOperands(MI) == 3 &&
3652
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3653
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3654
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3655
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3656
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3657
0
      AsmString = "movge %xcc, $\x02, $\x01";
3658
0
      break;
3659
0
    }
3660
84
    if (MCInst_getNumOperands(MI) == 3 &&
3661
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3662
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3663
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3664
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3665
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3666
0
      AsmString = "movl %xcc, $\x02, $\x01";
3667
0
      break;
3668
0
    }
3669
84
    if (MCInst_getNumOperands(MI) == 3 &&
3670
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3671
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3672
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3673
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3674
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3675
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3676
0
      break;
3677
0
    }
3678
84
    if (MCInst_getNumOperands(MI) == 3 &&
3679
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3680
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3681
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3682
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3683
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3684
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3685
0
      break;
3686
0
    }
3687
84
    if (MCInst_getNumOperands(MI) == 3 &&
3688
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3689
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3690
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3691
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3692
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3693
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3694
0
      break;
3695
0
    }
3696
84
    if (MCInst_getNumOperands(MI) == 3 &&
3697
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3698
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3699
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3700
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3701
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3702
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3703
0
      break;
3704
0
    }
3705
84
    if (MCInst_getNumOperands(MI) == 3 &&
3706
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3707
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3708
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3709
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3710
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3711
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3712
0
      break;
3713
0
    }
3714
84
    if (MCInst_getNumOperands(MI) == 3 &&
3715
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3716
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3717
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3718
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3719
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3720
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3721
0
      break;
3722
0
    }
3723
84
    if (MCInst_getNumOperands(MI) == 3 &&
3724
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3725
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3726
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3727
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3728
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3729
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3730
0
      break;
3731
0
    }
3732
84
    if (MCInst_getNumOperands(MI) == 3 &&
3733
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3734
84
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3735
84
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3736
84
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3737
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3738
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3739
0
      break;
3740
0
    }
3741
84
    return NULL;
3742
22
  case SP_MOVXCCrr:
3743
22
    if (MCInst_getNumOperands(MI) == 3 &&
3744
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3745
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3746
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3747
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3748
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3749
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3750
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3751
0
      AsmString = "mova %xcc, $\x02, $\x01";
3752
0
      break;
3753
0
    }
3754
22
    if (MCInst_getNumOperands(MI) == 3 &&
3755
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3756
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3757
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3758
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3759
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3760
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3761
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3762
0
      AsmString = "movn %xcc, $\x02, $\x01";
3763
0
      break;
3764
0
    }
3765
22
    if (MCInst_getNumOperands(MI) == 3 &&
3766
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3767
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3768
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3769
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3770
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3771
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3772
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3773
0
      AsmString = "movne %xcc, $\x02, $\x01";
3774
0
      break;
3775
0
    }
3776
22
    if (MCInst_getNumOperands(MI) == 3 &&
3777
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3778
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3779
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3780
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3781
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3782
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3783
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3784
0
      AsmString = "move %xcc, $\x02, $\x01";
3785
0
      break;
3786
0
    }
3787
22
    if (MCInst_getNumOperands(MI) == 3 &&
3788
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3789
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3790
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3791
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3792
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3793
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3794
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3795
0
      AsmString = "movg %xcc, $\x02, $\x01";
3796
0
      break;
3797
0
    }
3798
22
    if (MCInst_getNumOperands(MI) == 3 &&
3799
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3800
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3801
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3802
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3803
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3804
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3805
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3806
0
      AsmString = "movle %xcc, $\x02, $\x01";
3807
0
      break;
3808
0
    }
3809
22
    if (MCInst_getNumOperands(MI) == 3 &&
3810
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3811
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3812
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3813
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3814
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3815
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3816
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3817
0
      AsmString = "movge %xcc, $\x02, $\x01";
3818
0
      break;
3819
0
    }
3820
22
    if (MCInst_getNumOperands(MI) == 3 &&
3821
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3822
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3823
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3824
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3825
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3826
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3827
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3828
0
      AsmString = "movl %xcc, $\x02, $\x01";
3829
0
      break;
3830
0
    }
3831
22
    if (MCInst_getNumOperands(MI) == 3 &&
3832
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3833
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3834
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3835
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3836
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3837
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3838
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3839
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3840
0
      break;
3841
0
    }
3842
22
    if (MCInst_getNumOperands(MI) == 3 &&
3843
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3844
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3845
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3846
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3847
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3848
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3849
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3850
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3851
0
      break;
3852
0
    }
3853
22
    if (MCInst_getNumOperands(MI) == 3 &&
3854
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3855
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3856
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3857
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3858
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3859
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3860
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3861
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3862
0
      break;
3863
0
    }
3864
22
    if (MCInst_getNumOperands(MI) == 3 &&
3865
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3866
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3867
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3868
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3869
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3870
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3871
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3872
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3873
0
      break;
3874
0
    }
3875
22
    if (MCInst_getNumOperands(MI) == 3 &&
3876
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3877
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3878
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3879
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3880
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3881
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3882
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3883
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3884
0
      break;
3885
0
    }
3886
22
    if (MCInst_getNumOperands(MI) == 3 &&
3887
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3888
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3889
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3890
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3891
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3892
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3893
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3894
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3895
0
      break;
3896
0
    }
3897
22
    if (MCInst_getNumOperands(MI) == 3 &&
3898
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3899
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3900
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3901
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3902
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3903
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3904
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3905
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3906
0
      break;
3907
0
    }
3908
22
    if (MCInst_getNumOperands(MI) == 3 &&
3909
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3910
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3911
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3912
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3913
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3914
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3915
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3916
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3917
0
      break;
3918
0
    }
3919
22
    return NULL;
3920
306
  case SP_ORri:
3921
306
    if (MCInst_getNumOperands(MI) == 3 &&
3922
306
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3923
306
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3924
306
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3925
      // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3926
92
      AsmString = "mov $\x03, $\x01";
3927
92
      break;
3928
92
    }
3929
214
    return NULL;
3930
127
  case SP_ORrr:
3931
127
    if (MCInst_getNumOperands(MI) == 3 &&
3932
127
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3933
127
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3934
127
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3935
127
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3936
127
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3937
      // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3938
50
      AsmString = "mov $\x03, $\x01";
3939
50
      break;
3940
50
    }
3941
77
    return NULL;
3942
546
  case SP_RESTORErr:
3943
546
    if (MCInst_getNumOperands(MI) == 3 &&
3944
546
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3945
546
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3946
546
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3947
      // (RESTORErr G0, G0, G0)
3948
297
      AsmString = "restore";
3949
297
      break;
3950
297
    }
3951
249
    return NULL;
3952
0
  case SP_RET:
3953
0
    if (MCInst_getNumOperands(MI) == 1 &&
3954
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3955
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3956
      // (RET 8)
3957
0
      AsmString = "ret";
3958
0
      break;
3959
0
    }
3960
0
    return NULL;
3961
0
  case SP_RETL:
3962
0
    if (MCInst_getNumOperands(MI) == 1 &&
3963
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3964
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3965
      // (RETL 8)
3966
0
      AsmString = "retl";
3967
0
      break;
3968
0
    }
3969
0
    return NULL;
3970
3.60k
  case SP_TXCCri:
3971
3.60k
    if (MCInst_getNumOperands(MI) == 3 &&
3972
3.60k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3973
3.60k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3974
3.60k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3975
3.60k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3976
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3977
34
      AsmString = "ta %xcc, $\x01 + $\x02";
3978
34
      break;
3979
34
    }
3980
3.57k
    if (MCInst_getNumOperands(MI) == 3 &&
3981
3.57k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3982
3.57k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3983
3.57k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3984
      // (TXCCri G0, i32imm:$imm, 8)
3985
0
      AsmString = "ta %xcc, $\x02";
3986
0
      break;
3987
0
    }
3988
3.57k
    if (MCInst_getNumOperands(MI) == 3 &&
3989
3.57k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3990
3.57k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3991
3.57k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3992
3.57k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3993
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3994
70
      AsmString = "tn %xcc, $\x01 + $\x02";
3995
70
      break;
3996
70
    }
3997
3.50k
    if (MCInst_getNumOperands(MI) == 3 &&
3998
3.50k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3999
3.50k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4000
3.50k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4001
      // (TXCCri G0, i32imm:$imm, 0)
4002
0
      AsmString = "tn %xcc, $\x02";
4003
0
      break;
4004
0
    }
4005
3.50k
    if (MCInst_getNumOperands(MI) == 3 &&
4006
3.50k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4007
3.50k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4008
3.50k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4009
3.50k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4010
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4011
18
      AsmString = "tne %xcc, $\x01 + $\x02";
4012
18
      break;
4013
18
    }
4014
3.48k
    if (MCInst_getNumOperands(MI) == 3 &&
4015
3.48k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4016
3.48k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4017
3.48k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4018
      // (TXCCri G0, i32imm:$imm, 9)
4019
0
      AsmString = "tne %xcc, $\x02";
4020
0
      break;
4021
0
    }
4022
3.48k
    if (MCInst_getNumOperands(MI) == 3 &&
4023
3.48k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4024
3.48k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4025
3.48k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4026
3.48k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4027
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4028
34
      AsmString = "te %xcc, $\x01 + $\x02";
4029
34
      break;
4030
34
    }
4031
3.44k
    if (MCInst_getNumOperands(MI) == 3 &&
4032
3.44k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4033
3.44k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4034
3.44k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4035
      // (TXCCri G0, i32imm:$imm, 1)
4036
0
      AsmString = "te %xcc, $\x02";
4037
0
      break;
4038
0
    }
4039
3.44k
    if (MCInst_getNumOperands(MI) == 3 &&
4040
3.44k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4041
3.44k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4042
3.44k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4043
3.44k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4044
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4045
521
      AsmString = "tg %xcc, $\x01 + $\x02";
4046
521
      break;
4047
521
    }
4048
2.92k
    if (MCInst_getNumOperands(MI) == 3 &&
4049
2.92k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4050
2.92k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4051
2.92k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4052
      // (TXCCri G0, i32imm:$imm, 10)
4053
0
      AsmString = "tg %xcc, $\x02";
4054
0
      break;
4055
0
    }
4056
2.92k
    if (MCInst_getNumOperands(MI) == 3 &&
4057
2.92k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4058
2.92k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4059
2.92k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4060
2.92k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4061
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4062
66
      AsmString = "tle %xcc, $\x01 + $\x02";
4063
66
      break;
4064
66
    }
4065
2.86k
    if (MCInst_getNumOperands(MI) == 3 &&
4066
2.86k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4067
2.86k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4068
2.86k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4069
      // (TXCCri G0, i32imm:$imm, 2)
4070
0
      AsmString = "tle %xcc, $\x02";
4071
0
      break;
4072
0
    }
4073
2.86k
    if (MCInst_getNumOperands(MI) == 3 &&
4074
2.86k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4075
2.86k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4076
2.86k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4077
2.86k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4078
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4079
18
      AsmString = "tge %xcc, $\x01 + $\x02";
4080
18
      break;
4081
18
    }
4082
2.84k
    if (MCInst_getNumOperands(MI) == 3 &&
4083
2.84k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4084
2.84k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4085
2.84k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4086
      // (TXCCri G0, i32imm:$imm, 11)
4087
0
      AsmString = "tge %xcc, $\x02";
4088
0
      break;
4089
0
    }
4090
2.84k
    if (MCInst_getNumOperands(MI) == 3 &&
4091
2.84k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4092
2.84k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4093
2.84k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4094
2.84k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4095
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4096
18
      AsmString = "tl %xcc, $\x01 + $\x02";
4097
18
      break;
4098
18
    }
4099
2.82k
    if (MCInst_getNumOperands(MI) == 3 &&
4100
2.82k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4101
2.82k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4102
2.82k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4103
      // (TXCCri G0, i32imm:$imm, 3)
4104
0
      AsmString = "tl %xcc, $\x02";
4105
0
      break;
4106
0
    }
4107
2.82k
    if (MCInst_getNumOperands(MI) == 3 &&
4108
2.82k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4109
2.82k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4110
2.82k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4111
2.82k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4112
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4113
22
      AsmString = "tgu %xcc, $\x01 + $\x02";
4114
22
      break;
4115
22
    }
4116
2.80k
    if (MCInst_getNumOperands(MI) == 3 &&
4117
2.80k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4118
2.80k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4119
2.80k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4120
      // (TXCCri G0, i32imm:$imm, 12)
4121
0
      AsmString = "tgu %xcc, $\x02";
4122
0
      break;
4123
0
    }
4124
2.80k
    if (MCInst_getNumOperands(MI) == 3 &&
4125
2.80k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4126
2.80k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4127
2.80k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4128
2.80k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4129
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4130
1.23k
      AsmString = "tleu %xcc, $\x01 + $\x02";
4131
1.23k
      break;
4132
1.23k
    }
4133
1.56k
    if (MCInst_getNumOperands(MI) == 3 &&
4134
1.56k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4135
1.56k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4136
1.56k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4137
      // (TXCCri G0, i32imm:$imm, 4)
4138
0
      AsmString = "tleu %xcc, $\x02";
4139
0
      break;
4140
0
    }
4141
1.56k
    if (MCInst_getNumOperands(MI) == 3 &&
4142
1.56k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4143
1.56k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4144
1.56k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4145
1.56k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4146
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4147
146
      AsmString = "tcc %xcc, $\x01 + $\x02";
4148
146
      break;
4149
146
    }
4150
1.42k
    if (MCInst_getNumOperands(MI) == 3 &&
4151
1.42k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4152
1.42k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4153
1.42k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4154
      // (TXCCri G0, i32imm:$imm, 13)
4155
0
      AsmString = "tcc %xcc, $\x02";
4156
0
      break;
4157
0
    }
4158
1.42k
    if (MCInst_getNumOperands(MI) == 3 &&
4159
1.42k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4160
1.42k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4161
1.42k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4162
1.42k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4163
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4164
194
      AsmString = "tcs %xcc, $\x01 + $\x02";
4165
194
      break;
4166
194
    }
4167
1.22k
    if (MCInst_getNumOperands(MI) == 3 &&
4168
1.22k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4169
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4170
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4171
      // (TXCCri G0, i32imm:$imm, 5)
4172
0
      AsmString = "tcs %xcc, $\x02";
4173
0
      break;
4174
0
    }
4175
1.22k
    if (MCInst_getNumOperands(MI) == 3 &&
4176
1.22k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4177
1.22k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4178
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4179
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4180
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4181
751
      AsmString = "tpos %xcc, $\x01 + $\x02";
4182
751
      break;
4183
751
    }
4184
475
    if (MCInst_getNumOperands(MI) == 3 &&
4185
475
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4186
475
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4187
475
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4188
      // (TXCCri G0, i32imm:$imm, 14)
4189
0
      AsmString = "tpos %xcc, $\x02";
4190
0
      break;
4191
0
    }
4192
475
    if (MCInst_getNumOperands(MI) == 3 &&
4193
475
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4194
475
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4195
475
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4196
475
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4197
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4198
150
      AsmString = "tneg %xcc, $\x01 + $\x02";
4199
150
      break;
4200
150
    }
4201
325
    if (MCInst_getNumOperands(MI) == 3 &&
4202
325
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4203
325
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4204
325
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4205
      // (TXCCri G0, i32imm:$imm, 6)
4206
0
      AsmString = "tneg %xcc, $\x02";
4207
0
      break;
4208
0
    }
4209
325
    if (MCInst_getNumOperands(MI) == 3 &&
4210
325
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4211
325
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4212
325
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4213
325
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4214
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4215
136
      AsmString = "tvc %xcc, $\x01 + $\x02";
4216
136
      break;
4217
136
    }
4218
189
    if (MCInst_getNumOperands(MI) == 3 &&
4219
189
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4220
189
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4221
189
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4222
      // (TXCCri G0, i32imm:$imm, 15)
4223
0
      AsmString = "tvc %xcc, $\x02";
4224
0
      break;
4225
0
    }
4226
189
    if (MCInst_getNumOperands(MI) == 3 &&
4227
189
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4228
189
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4229
189
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4230
189
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4231
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4232
189
      AsmString = "tvs %xcc, $\x01 + $\x02";
4233
189
      break;
4234
189
    }
4235
0
    if (MCInst_getNumOperands(MI) == 3 &&
4236
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4237
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4238
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4239
      // (TXCCri G0, i32imm:$imm, 7)
4240
0
      AsmString = "tvs %xcc, $\x02";
4241
0
      break;
4242
0
    }
4243
0
    return NULL;
4244
2.88k
  case SP_TXCCrr:
4245
2.88k
    if (MCInst_getNumOperands(MI) == 3 &&
4246
2.88k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4247
2.88k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4248
2.88k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4249
2.88k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4250
2.88k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4251
2.88k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4252
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4253
17
      AsmString = "ta %xcc, $\x01 + $\x02";
4254
17
      break;
4255
17
    }
4256
2.87k
    if (MCInst_getNumOperands(MI) == 3 &&
4257
2.87k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4258
2.87k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4259
2.87k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4260
2.87k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4261
2.87k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4262
      // (TXCCrr G0, IntRegs:$rs2, 8)
4263
0
      AsmString = "ta %xcc, $\x02";
4264
0
      break;
4265
0
    }
4266
2.87k
    if (MCInst_getNumOperands(MI) == 3 &&
4267
2.87k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4268
2.87k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4269
2.87k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4270
2.87k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4271
2.87k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4272
2.87k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4273
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4274
18
      AsmString = "tn %xcc, $\x01 + $\x02";
4275
18
      break;
4276
18
    }
4277
2.85k
    if (MCInst_getNumOperands(MI) == 3 &&
4278
2.85k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4279
2.85k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4280
2.85k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4281
2.85k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4282
2.85k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4283
      // (TXCCrr G0, IntRegs:$rs2, 0)
4284
0
      AsmString = "tn %xcc, $\x02";
4285
0
      break;
4286
0
    }
4287
2.85k
    if (MCInst_getNumOperands(MI) == 3 &&
4288
2.85k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4289
2.85k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4290
2.85k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4291
2.85k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4292
2.85k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4293
2.85k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4294
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4295
35
      AsmString = "tne %xcc, $\x01 + $\x02";
4296
35
      break;
4297
35
    }
4298
2.81k
    if (MCInst_getNumOperands(MI) == 3 &&
4299
2.81k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4300
2.81k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4301
2.81k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4302
2.81k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4303
2.81k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4304
      // (TXCCrr G0, IntRegs:$rs2, 9)
4305
0
      AsmString = "tne %xcc, $\x02";
4306
0
      break;
4307
0
    }
4308
2.81k
    if (MCInst_getNumOperands(MI) == 3 &&
4309
2.81k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4310
2.81k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4311
2.81k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4312
2.81k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4313
2.81k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4314
2.81k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4315
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4316
34
      AsmString = "te %xcc, $\x01 + $\x02";
4317
34
      break;
4318
34
    }
4319
2.78k
    if (MCInst_getNumOperands(MI) == 3 &&
4320
2.78k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4321
2.78k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4322
2.78k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4323
2.78k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4324
2.78k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4325
      // (TXCCrr G0, IntRegs:$rs2, 1)
4326
0
      AsmString = "te %xcc, $\x02";
4327
0
      break;
4328
0
    }
4329
2.78k
    if (MCInst_getNumOperands(MI) == 3 &&
4330
2.78k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4331
2.78k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4332
2.78k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4333
2.78k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4334
2.78k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4335
2.78k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4336
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4337
69
      AsmString = "tg %xcc, $\x01 + $\x02";
4338
69
      break;
4339
69
    }
4340
2.71k
    if (MCInst_getNumOperands(MI) == 3 &&
4341
2.71k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4342
2.71k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4343
2.71k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4344
2.71k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4345
2.71k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4346
      // (TXCCrr G0, IntRegs:$rs2, 10)
4347
0
      AsmString = "tg %xcc, $\x02";
4348
0
      break;
4349
0
    }
4350
2.71k
    if (MCInst_getNumOperands(MI) == 3 &&
4351
2.71k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4352
2.71k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4353
2.71k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4354
2.71k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4355
2.71k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4356
2.71k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4357
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4358
37
      AsmString = "tle %xcc, $\x01 + $\x02";
4359
37
      break;
4360
37
    }
4361
2.67k
    if (MCInst_getNumOperands(MI) == 3 &&
4362
2.67k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4363
2.67k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4364
2.67k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4365
2.67k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4366
2.67k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4367
      // (TXCCrr G0, IntRegs:$rs2, 2)
4368
0
      AsmString = "tle %xcc, $\x02";
4369
0
      break;
4370
0
    }
4371
2.67k
    if (MCInst_getNumOperands(MI) == 3 &&
4372
2.67k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4373
2.67k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4374
2.67k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4375
2.67k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4376
2.67k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4377
2.67k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4378
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4379
196
      AsmString = "tge %xcc, $\x01 + $\x02";
4380
196
      break;
4381
196
    }
4382
2.48k
    if (MCInst_getNumOperands(MI) == 3 &&
4383
2.48k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4384
2.48k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4385
2.48k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4386
2.48k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4387
2.48k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4388
      // (TXCCrr G0, IntRegs:$rs2, 11)
4389
0
      AsmString = "tge %xcc, $\x02";
4390
0
      break;
4391
0
    }
4392
2.48k
    if (MCInst_getNumOperands(MI) == 3 &&
4393
2.48k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4394
2.48k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4395
2.48k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4396
2.48k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4397
2.48k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4398
2.48k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4399
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4400
42
      AsmString = "tl %xcc, $\x01 + $\x02";
4401
42
      break;
4402
42
    }
4403
2.44k
    if (MCInst_getNumOperands(MI) == 3 &&
4404
2.44k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4405
2.44k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4406
2.44k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4407
2.44k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4408
2.44k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4409
      // (TXCCrr G0, IntRegs:$rs2, 3)
4410
0
      AsmString = "tl %xcc, $\x02";
4411
0
      break;
4412
0
    }
4413
2.44k
    if (MCInst_getNumOperands(MI) == 3 &&
4414
2.44k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4415
2.44k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4416
2.44k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4417
2.44k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4418
2.44k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4419
2.44k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4420
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4421
953
      AsmString = "tgu %xcc, $\x01 + $\x02";
4422
953
      break;
4423
953
    }
4424
1.48k
    if (MCInst_getNumOperands(MI) == 3 &&
4425
1.48k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4426
1.48k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4427
1.48k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4428
1.48k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4429
1.48k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4430
      // (TXCCrr G0, IntRegs:$rs2, 12)
4431
0
      AsmString = "tgu %xcc, $\x02";
4432
0
      break;
4433
0
    }
4434
1.48k
    if (MCInst_getNumOperands(MI) == 3 &&
4435
1.48k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4436
1.48k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4437
1.48k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4438
1.48k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4439
1.48k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4440
1.48k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4441
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4442
398
      AsmString = "tleu %xcc, $\x01 + $\x02";
4443
398
      break;
4444
398
    }
4445
1.08k
    if (MCInst_getNumOperands(MI) == 3 &&
4446
1.08k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4447
1.08k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4448
1.08k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4449
1.08k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4450
1.08k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4451
      // (TXCCrr G0, IntRegs:$rs2, 4)
4452
0
      AsmString = "tleu %xcc, $\x02";
4453
0
      break;
4454
0
    }
4455
1.08k
    if (MCInst_getNumOperands(MI) == 3 &&
4456
1.08k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4457
1.08k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4458
1.08k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4459
1.08k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4460
1.08k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4461
1.08k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4462
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4463
121
      AsmString = "tcc %xcc, $\x01 + $\x02";
4464
121
      break;
4465
121
    }
4466
968
    if (MCInst_getNumOperands(MI) == 3 &&
4467
968
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4468
968
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4469
968
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4470
968
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4471
968
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4472
      // (TXCCrr G0, IntRegs:$rs2, 13)
4473
0
      AsmString = "tcc %xcc, $\x02";
4474
0
      break;
4475
0
    }
4476
968
    if (MCInst_getNumOperands(MI) == 3 &&
4477
968
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4478
968
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4479
968
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4480
968
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4481
968
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4482
968
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4483
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4484
120
      AsmString = "tcs %xcc, $\x01 + $\x02";
4485
120
      break;
4486
120
    }
4487
848
    if (MCInst_getNumOperands(MI) == 3 &&
4488
848
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4489
848
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4490
848
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4491
848
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4492
848
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4493
      // (TXCCrr G0, IntRegs:$rs2, 5)
4494
0
      AsmString = "tcs %xcc, $\x02";
4495
0
      break;
4496
0
    }
4497
848
    if (MCInst_getNumOperands(MI) == 3 &&
4498
848
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4499
848
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4500
848
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4501
848
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4502
848
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4503
848
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4504
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4505
37
      AsmString = "tpos %xcc, $\x01 + $\x02";
4506
37
      break;
4507
37
    }
4508
811
    if (MCInst_getNumOperands(MI) == 3 &&
4509
811
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4510
811
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4511
811
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4512
811
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4513
811
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4514
      // (TXCCrr G0, IntRegs:$rs2, 14)
4515
0
      AsmString = "tpos %xcc, $\x02";
4516
0
      break;
4517
0
    }
4518
811
    if (MCInst_getNumOperands(MI) == 3 &&
4519
811
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4520
811
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4521
811
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4522
811
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4523
811
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4524
811
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4525
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4526
32
      AsmString = "tneg %xcc, $\x01 + $\x02";
4527
32
      break;
4528
32
    }
4529
779
    if (MCInst_getNumOperands(MI) == 3 &&
4530
779
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4531
779
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4532
779
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4533
779
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4534
779
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4535
      // (TXCCrr G0, IntRegs:$rs2, 6)
4536
0
      AsmString = "tneg %xcc, $\x02";
4537
0
      break;
4538
0
    }
4539
779
    if (MCInst_getNumOperands(MI) == 3 &&
4540
779
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4541
779
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4542
779
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4543
779
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4544
779
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4545
779
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4546
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4547
606
      AsmString = "tvc %xcc, $\x01 + $\x02";
4548
606
      break;
4549
606
    }
4550
173
    if (MCInst_getNumOperands(MI) == 3 &&
4551
173
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4552
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4553
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4554
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4555
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4556
      // (TXCCrr G0, IntRegs:$rs2, 15)
4557
0
      AsmString = "tvc %xcc, $\x02";
4558
0
      break;
4559
0
    }
4560
173
    if (MCInst_getNumOperands(MI) == 3 &&
4561
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4562
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4563
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4564
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4565
173
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4566
173
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4567
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4568
173
      AsmString = "tvs %xcc, $\x01 + $\x02";
4569
173
      break;
4570
173
    }
4571
0
    if (MCInst_getNumOperands(MI) == 3 &&
4572
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4573
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4574
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4575
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4576
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4577
      // (TXCCrr G0, IntRegs:$rs2, 7)
4578
0
      AsmString = "tvs %xcc, $\x02";
4579
0
      break;
4580
0
    }
4581
0
    return NULL;
4582
278
  case SP_V9FCMPD:
4583
278
    if (MCInst_getNumOperands(MI) == 3 &&
4584
278
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4585
278
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4586
278
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4587
278
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4588
278
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4589
      // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4590
66
      AsmString = "fcmpd $\x02, $\x03";
4591
66
      break;
4592
66
    }
4593
212
    return NULL;
4594
297
  case SP_V9FCMPED:
4595
297
    if (MCInst_getNumOperands(MI) == 3 &&
4596
297
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4597
297
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4598
297
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4599
297
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4600
297
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4601
      // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4602
35
      AsmString = "fcmped $\x02, $\x03";
4603
35
      break;
4604
35
    }
4605
262
    return NULL;
4606
87
  case SP_V9FCMPEQ:
4607
87
    if (MCInst_getNumOperands(MI) == 3 &&
4608
87
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4609
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4610
87
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4611
87
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4612
87
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4613
      // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4614
18
      AsmString = "fcmpeq $\x02, $\x03";
4615
18
      break;
4616
18
    }
4617
69
    return NULL;
4618
564
  case SP_V9FCMPES:
4619
564
    if (MCInst_getNumOperands(MI) == 3 &&
4620
564
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4621
564
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4622
564
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4623
564
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4624
564
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4625
      // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4626
20
      AsmString = "fcmpes $\x02, $\x03";
4627
20
      break;
4628
20
    }
4629
544
    return NULL;
4630
844
  case SP_V9FCMPQ:
4631
844
    if (MCInst_getNumOperands(MI) == 3 &&
4632
844
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4633
844
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4634
844
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4635
844
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4636
844
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4637
      // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4638
202
      AsmString = "fcmpq $\x02, $\x03";
4639
202
      break;
4640
202
    }
4641
642
    return NULL;
4642
260
  case SP_V9FCMPS:
4643
260
    if (MCInst_getNumOperands(MI) == 3 &&
4644
260
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4645
260
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4646
260
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4647
260
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4648
260
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4649
      // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4650
53
      AsmString = "fcmps $\x02, $\x03";
4651
53
      break;
4652
53
    }
4653
207
    return NULL;
4654
24
  case SP_V9FMOVD_FCC:
4655
24
    if (MCInst_getNumOperands(MI) == 4 &&
4656
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4657
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4658
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4659
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4660
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4661
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4662
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4663
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4664
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4665
0
      AsmString = "fmovda $\x02, $\x03, $\x01";
4666
0
      break;
4667
0
    }
4668
24
    if (MCInst_getNumOperands(MI) == 4 &&
4669
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4670
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4671
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4672
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4673
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4674
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4675
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4676
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4677
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4678
0
      AsmString = "fmovdn $\x02, $\x03, $\x01";
4679
0
      break;
4680
0
    }
4681
24
    if (MCInst_getNumOperands(MI) == 4 &&
4682
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4683
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4684
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4685
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4686
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4687
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4688
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4689
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4690
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4691
0
      AsmString = "fmovdu $\x02, $\x03, $\x01";
4692
0
      break;
4693
0
    }
4694
24
    if (MCInst_getNumOperands(MI) == 4 &&
4695
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4696
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4697
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4698
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4699
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4700
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4701
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4702
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4703
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4704
0
      AsmString = "fmovdg $\x02, $\x03, $\x01";
4705
0
      break;
4706
0
    }
4707
24
    if (MCInst_getNumOperands(MI) == 4 &&
4708
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4709
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4710
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4711
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4712
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4713
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4714
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4715
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4716
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4717
0
      AsmString = "fmovdug $\x02, $\x03, $\x01";
4718
0
      break;
4719
0
    }
4720
24
    if (MCInst_getNumOperands(MI) == 4 &&
4721
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4722
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4723
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4724
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4725
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4726
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4727
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4728
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4729
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4730
0
      AsmString = "fmovdl $\x02, $\x03, $\x01";
4731
0
      break;
4732
0
    }
4733
24
    if (MCInst_getNumOperands(MI) == 4 &&
4734
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4735
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4736
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4737
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4738
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4739
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4740
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4741
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4742
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4743
0
      AsmString = "fmovdul $\x02, $\x03, $\x01";
4744
0
      break;
4745
0
    }
4746
24
    if (MCInst_getNumOperands(MI) == 4 &&
4747
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4748
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4749
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4750
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4751
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4752
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4753
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4754
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4755
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4756
0
      AsmString = "fmovdlg $\x02, $\x03, $\x01";
4757
0
      break;
4758
0
    }
4759
24
    if (MCInst_getNumOperands(MI) == 4 &&
4760
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4761
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4762
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4763
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4764
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4765
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4766
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4767
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4768
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4769
0
      AsmString = "fmovdne $\x02, $\x03, $\x01";
4770
0
      break;
4771
0
    }
4772
24
    if (MCInst_getNumOperands(MI) == 4 &&
4773
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4774
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4775
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4776
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4777
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4778
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4779
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4780
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4781
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4782
0
      AsmString = "fmovde $\x02, $\x03, $\x01";
4783
0
      break;
4784
0
    }
4785
24
    if (MCInst_getNumOperands(MI) == 4 &&
4786
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4787
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4788
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4789
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4790
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4791
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4792
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4793
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4794
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4795
0
      AsmString = "fmovdue $\x02, $\x03, $\x01";
4796
0
      break;
4797
0
    }
4798
24
    if (MCInst_getNumOperands(MI) == 4 &&
4799
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4800
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4801
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4802
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4803
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4804
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4805
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4806
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4807
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4808
0
      AsmString = "fmovdge $\x02, $\x03, $\x01";
4809
0
      break;
4810
0
    }
4811
24
    if (MCInst_getNumOperands(MI) == 4 &&
4812
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4813
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4814
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4815
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4816
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4817
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4818
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4819
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4820
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4821
0
      AsmString = "fmovduge $\x02, $\x03, $\x01";
4822
0
      break;
4823
0
    }
4824
24
    if (MCInst_getNumOperands(MI) == 4 &&
4825
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4826
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4827
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4828
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4829
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4830
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4831
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4832
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4833
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4834
0
      AsmString = "fmovdle $\x02, $\x03, $\x01";
4835
0
      break;
4836
0
    }
4837
24
    if (MCInst_getNumOperands(MI) == 4 &&
4838
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4839
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4840
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4841
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4842
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4843
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4844
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4845
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4846
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4847
0
      AsmString = "fmovdule $\x02, $\x03, $\x01";
4848
0
      break;
4849
0
    }
4850
24
    if (MCInst_getNumOperands(MI) == 4 &&
4851
24
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4852
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4853
24
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4854
24
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4855
24
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4856
24
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4857
24
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4858
24
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4859
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4860
0
      AsmString = "fmovdo $\x02, $\x03, $\x01";
4861
0
      break;
4862
0
    }
4863
24
    return NULL;
4864
46
  case SP_V9FMOVQ_FCC:
4865
46
    if (MCInst_getNumOperands(MI) == 4 &&
4866
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4867
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4868
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4869
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4870
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4871
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4872
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4873
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4874
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4875
0
      AsmString = "fmovqa $\x02, $\x03, $\x01";
4876
0
      break;
4877
0
    }
4878
46
    if (MCInst_getNumOperands(MI) == 4 &&
4879
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4880
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4881
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4882
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4883
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4884
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4885
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4886
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4887
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4888
0
      AsmString = "fmovqn $\x02, $\x03, $\x01";
4889
0
      break;
4890
0
    }
4891
46
    if (MCInst_getNumOperands(MI) == 4 &&
4892
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4893
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4894
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4895
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4896
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4897
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4898
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4899
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4900
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4901
0
      AsmString = "fmovqu $\x02, $\x03, $\x01";
4902
0
      break;
4903
0
    }
4904
46
    if (MCInst_getNumOperands(MI) == 4 &&
4905
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4906
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4907
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4908
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4909
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4910
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4911
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4912
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4913
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4914
0
      AsmString = "fmovqg $\x02, $\x03, $\x01";
4915
0
      break;
4916
0
    }
4917
46
    if (MCInst_getNumOperands(MI) == 4 &&
4918
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4919
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4920
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4921
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4922
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4923
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4924
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4925
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4926
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4927
0
      AsmString = "fmovqug $\x02, $\x03, $\x01";
4928
0
      break;
4929
0
    }
4930
46
    if (MCInst_getNumOperands(MI) == 4 &&
4931
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4932
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4933
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4934
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4935
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4936
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4937
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4938
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4939
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4940
0
      AsmString = "fmovql $\x02, $\x03, $\x01";
4941
0
      break;
4942
0
    }
4943
46
    if (MCInst_getNumOperands(MI) == 4 &&
4944
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4945
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4946
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4947
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4948
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4949
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4950
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4951
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4952
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4953
0
      AsmString = "fmovqul $\x02, $\x03, $\x01";
4954
0
      break;
4955
0
    }
4956
46
    if (MCInst_getNumOperands(MI) == 4 &&
4957
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4958
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4959
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4960
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4961
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4962
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4963
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4964
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4965
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4966
0
      AsmString = "fmovqlg $\x02, $\x03, $\x01";
4967
0
      break;
4968
0
    }
4969
46
    if (MCInst_getNumOperands(MI) == 4 &&
4970
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4971
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4972
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4973
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4974
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4975
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4976
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4977
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4978
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4979
0
      AsmString = "fmovqne $\x02, $\x03, $\x01";
4980
0
      break;
4981
0
    }
4982
46
    if (MCInst_getNumOperands(MI) == 4 &&
4983
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4984
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4985
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4986
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4987
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4988
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4989
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4990
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4991
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4992
0
      AsmString = "fmovqe $\x02, $\x03, $\x01";
4993
0
      break;
4994
0
    }
4995
46
    if (MCInst_getNumOperands(MI) == 4 &&
4996
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4997
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4998
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4999
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5000
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5001
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5002
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5003
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5004
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5005
0
      AsmString = "fmovque $\x02, $\x03, $\x01";
5006
0
      break;
5007
0
    }
5008
46
    if (MCInst_getNumOperands(MI) == 4 &&
5009
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5010
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5011
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5012
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5013
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5014
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5015
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5016
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5017
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5018
0
      AsmString = "fmovqge $\x02, $\x03, $\x01";
5019
0
      break;
5020
0
    }
5021
46
    if (MCInst_getNumOperands(MI) == 4 &&
5022
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5023
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5024
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5025
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5026
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5027
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5028
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5029
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5030
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5031
0
      AsmString = "fmovquge $\x02, $\x03, $\x01";
5032
0
      break;
5033
0
    }
5034
46
    if (MCInst_getNumOperands(MI) == 4 &&
5035
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5036
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5037
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5038
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5039
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5040
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5041
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5042
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5043
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5044
0
      AsmString = "fmovqle $\x02, $\x03, $\x01";
5045
0
      break;
5046
0
    }
5047
46
    if (MCInst_getNumOperands(MI) == 4 &&
5048
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5049
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5050
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5051
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5052
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5053
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5054
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5055
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5056
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5057
0
      AsmString = "fmovqule $\x02, $\x03, $\x01";
5058
0
      break;
5059
0
    }
5060
46
    if (MCInst_getNumOperands(MI) == 4 &&
5061
46
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5062
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5063
46
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5064
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5065
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5066
46
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5067
46
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5068
46
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5069
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5070
0
      AsmString = "fmovqo $\x02, $\x03, $\x01";
5071
0
      break;
5072
0
    }
5073
46
    return NULL;
5074
341
  case SP_V9FMOVS_FCC:
5075
341
    if (MCInst_getNumOperands(MI) == 4 &&
5076
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5077
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5078
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5079
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5080
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5081
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5082
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5083
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5084
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5085
0
      AsmString = "fmovsa $\x02, $\x03, $\x01";
5086
0
      break;
5087
0
    }
5088
341
    if (MCInst_getNumOperands(MI) == 4 &&
5089
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5090
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5091
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5092
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5093
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5094
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5095
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5096
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5097
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5098
0
      AsmString = "fmovsn $\x02, $\x03, $\x01";
5099
0
      break;
5100
0
    }
5101
341
    if (MCInst_getNumOperands(MI) == 4 &&
5102
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5103
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5104
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5105
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5106
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5107
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5108
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5109
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5110
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5111
0
      AsmString = "fmovsu $\x02, $\x03, $\x01";
5112
0
      break;
5113
0
    }
5114
341
    if (MCInst_getNumOperands(MI) == 4 &&
5115
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5116
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5117
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5118
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5119
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5120
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5121
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5122
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5123
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5124
0
      AsmString = "fmovsg $\x02, $\x03, $\x01";
5125
0
      break;
5126
0
    }
5127
341
    if (MCInst_getNumOperands(MI) == 4 &&
5128
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5129
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5130
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5131
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5132
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5133
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5134
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5135
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5136
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5137
0
      AsmString = "fmovsug $\x02, $\x03, $\x01";
5138
0
      break;
5139
0
    }
5140
341
    if (MCInst_getNumOperands(MI) == 4 &&
5141
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5142
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5143
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5144
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5145
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5146
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5147
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5148
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5149
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5150
0
      AsmString = "fmovsl $\x02, $\x03, $\x01";
5151
0
      break;
5152
0
    }
5153
341
    if (MCInst_getNumOperands(MI) == 4 &&
5154
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5155
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5156
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5157
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5158
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5159
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5160
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5161
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5162
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5163
0
      AsmString = "fmovsul $\x02, $\x03, $\x01";
5164
0
      break;
5165
0
    }
5166
341
    if (MCInst_getNumOperands(MI) == 4 &&
5167
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5168
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5169
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5170
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5171
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5172
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5173
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5174
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5175
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5176
0
      AsmString = "fmovslg $\x02, $\x03, $\x01";
5177
0
      break;
5178
0
    }
5179
341
    if (MCInst_getNumOperands(MI) == 4 &&
5180
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5181
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5182
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5183
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5184
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5185
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5186
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5187
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5188
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5189
0
      AsmString = "fmovsne $\x02, $\x03, $\x01";
5190
0
      break;
5191
0
    }
5192
341
    if (MCInst_getNumOperands(MI) == 4 &&
5193
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5194
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5195
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5196
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5197
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5198
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5199
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5200
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5201
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5202
0
      AsmString = "fmovse $\x02, $\x03, $\x01";
5203
0
      break;
5204
0
    }
5205
341
    if (MCInst_getNumOperands(MI) == 4 &&
5206
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5207
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5208
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5209
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5210
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5211
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5212
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5213
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5214
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5215
0
      AsmString = "fmovsue $\x02, $\x03, $\x01";
5216
0
      break;
5217
0
    }
5218
341
    if (MCInst_getNumOperands(MI) == 4 &&
5219
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5220
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5221
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5222
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5223
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5224
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5225
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5226
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5227
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5228
0
      AsmString = "fmovsge $\x02, $\x03, $\x01";
5229
0
      break;
5230
0
    }
5231
341
    if (MCInst_getNumOperands(MI) == 4 &&
5232
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5233
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5234
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5235
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5236
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5237
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5238
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5239
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5240
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5241
0
      AsmString = "fmovsuge $\x02, $\x03, $\x01";
5242
0
      break;
5243
0
    }
5244
341
    if (MCInst_getNumOperands(MI) == 4 &&
5245
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5246
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5247
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5248
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5249
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5250
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5251
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5252
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5253
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5254
0
      AsmString = "fmovsle $\x02, $\x03, $\x01";
5255
0
      break;
5256
0
    }
5257
341
    if (MCInst_getNumOperands(MI) == 4 &&
5258
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5259
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5260
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5261
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5262
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5263
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5264
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5265
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5266
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5267
0
      AsmString = "fmovsule $\x02, $\x03, $\x01";
5268
0
      break;
5269
0
    }
5270
341
    if (MCInst_getNumOperands(MI) == 4 &&
5271
341
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5272
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5273
341
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5274
341
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5275
341
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5276
341
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5277
341
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5278
341
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5279
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5280
0
      AsmString = "fmovso $\x02, $\x03, $\x01";
5281
0
      break;
5282
0
    }
5283
341
    return NULL;
5284
324
  case SP_V9MOVFCCri:
5285
324
    if (MCInst_getNumOperands(MI) == 4 &&
5286
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5287
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5288
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5289
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5290
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5291
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5292
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5293
0
      AsmString = "mova $\x02, $\x03, $\x01";
5294
0
      break;
5295
0
    }
5296
324
    if (MCInst_getNumOperands(MI) == 4 &&
5297
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5298
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5299
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5300
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5301
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5302
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5303
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5304
0
      AsmString = "movn $\x02, $\x03, $\x01";
5305
0
      break;
5306
0
    }
5307
324
    if (MCInst_getNumOperands(MI) == 4 &&
5308
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5309
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5310
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5311
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5312
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5313
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5314
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5315
0
      AsmString = "movu $\x02, $\x03, $\x01";
5316
0
      break;
5317
0
    }
5318
324
    if (MCInst_getNumOperands(MI) == 4 &&
5319
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5320
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5321
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5322
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5323
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5324
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5325
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5326
0
      AsmString = "movg $\x02, $\x03, $\x01";
5327
0
      break;
5328
0
    }
5329
324
    if (MCInst_getNumOperands(MI) == 4 &&
5330
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5331
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5332
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5333
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5334
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5335
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5336
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5337
0
      AsmString = "movug $\x02, $\x03, $\x01";
5338
0
      break;
5339
0
    }
5340
324
    if (MCInst_getNumOperands(MI) == 4 &&
5341
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5342
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5343
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5344
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5345
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5346
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5347
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5348
0
      AsmString = "movl $\x02, $\x03, $\x01";
5349
0
      break;
5350
0
    }
5351
324
    if (MCInst_getNumOperands(MI) == 4 &&
5352
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5353
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5354
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5355
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5356
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5357
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5358
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5359
0
      AsmString = "movul $\x02, $\x03, $\x01";
5360
0
      break;
5361
0
    }
5362
324
    if (MCInst_getNumOperands(MI) == 4 &&
5363
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5364
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5365
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5366
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5367
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5368
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5369
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5370
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5371
0
      break;
5372
0
    }
5373
324
    if (MCInst_getNumOperands(MI) == 4 &&
5374
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5375
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5376
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5377
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5378
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5379
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5380
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5381
0
      AsmString = "movne $\x02, $\x03, $\x01";
5382
0
      break;
5383
0
    }
5384
324
    if (MCInst_getNumOperands(MI) == 4 &&
5385
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5386
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5387
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5388
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5389
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5390
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5391
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5392
0
      AsmString = "move $\x02, $\x03, $\x01";
5393
0
      break;
5394
0
    }
5395
324
    if (MCInst_getNumOperands(MI) == 4 &&
5396
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5397
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5398
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5399
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5400
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5401
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5402
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5403
0
      AsmString = "movue $\x02, $\x03, $\x01";
5404
0
      break;
5405
0
    }
5406
324
    if (MCInst_getNumOperands(MI) == 4 &&
5407
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5408
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5409
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5410
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5411
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5412
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5413
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5414
0
      AsmString = "movge $\x02, $\x03, $\x01";
5415
0
      break;
5416
0
    }
5417
324
    if (MCInst_getNumOperands(MI) == 4 &&
5418
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5419
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5420
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5421
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5422
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5423
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5424
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5425
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5426
0
      break;
5427
0
    }
5428
324
    if (MCInst_getNumOperands(MI) == 4 &&
5429
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5430
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5431
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5432
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5433
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5434
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5435
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5436
0
      AsmString = "movle $\x02, $\x03, $\x01";
5437
0
      break;
5438
0
    }
5439
324
    if (MCInst_getNumOperands(MI) == 4 &&
5440
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5441
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5442
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5443
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5444
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5445
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5446
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5447
0
      AsmString = "movule $\x02, $\x03, $\x01";
5448
0
      break;
5449
0
    }
5450
324
    if (MCInst_getNumOperands(MI) == 4 &&
5451
324
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5452
324
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5453
324
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5454
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5455
324
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5456
324
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5457
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5458
0
      AsmString = "movo $\x02, $\x03, $\x01";
5459
0
      break;
5460
0
    }
5461
324
    return NULL;
5462
252
  case SP_V9MOVFCCrr:
5463
252
    if (MCInst_getNumOperands(MI) == 4 &&
5464
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5465
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5466
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5467
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5468
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5469
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5470
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5471
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5472
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5473
0
      AsmString = "mova $\x02, $\x03, $\x01";
5474
0
      break;
5475
0
    }
5476
252
    if (MCInst_getNumOperands(MI) == 4 &&
5477
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5478
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5479
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5480
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5481
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5482
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5483
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5484
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5485
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5486
0
      AsmString = "movn $\x02, $\x03, $\x01";
5487
0
      break;
5488
0
    }
5489
252
    if (MCInst_getNumOperands(MI) == 4 &&
5490
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5491
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5492
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5493
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5494
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5495
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5496
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5497
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5498
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5499
0
      AsmString = "movu $\x02, $\x03, $\x01";
5500
0
      break;
5501
0
    }
5502
252
    if (MCInst_getNumOperands(MI) == 4 &&
5503
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5504
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5505
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5506
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5507
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5508
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5509
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5510
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5511
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5512
0
      AsmString = "movg $\x02, $\x03, $\x01";
5513
0
      break;
5514
0
    }
5515
252
    if (MCInst_getNumOperands(MI) == 4 &&
5516
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5517
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5518
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5519
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5520
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5521
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5522
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5523
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5524
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5525
0
      AsmString = "movug $\x02, $\x03, $\x01";
5526
0
      break;
5527
0
    }
5528
252
    if (MCInst_getNumOperands(MI) == 4 &&
5529
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5530
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5531
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5532
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5533
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5534
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5535
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5536
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5537
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5538
0
      AsmString = "movl $\x02, $\x03, $\x01";
5539
0
      break;
5540
0
    }
5541
252
    if (MCInst_getNumOperands(MI) == 4 &&
5542
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5543
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5544
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5545
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5546
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5547
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5548
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5549
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5550
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5551
0
      AsmString = "movul $\x02, $\x03, $\x01";
5552
0
      break;
5553
0
    }
5554
252
    if (MCInst_getNumOperands(MI) == 4 &&
5555
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5556
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5557
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5558
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5559
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5560
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5561
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5562
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5563
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5564
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5565
0
      break;
5566
0
    }
5567
252
    if (MCInst_getNumOperands(MI) == 4 &&
5568
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5569
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5570
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5571
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5572
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5573
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5574
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5575
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5576
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5577
0
      AsmString = "movne $\x02, $\x03, $\x01";
5578
0
      break;
5579
0
    }
5580
252
    if (MCInst_getNumOperands(MI) == 4 &&
5581
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5582
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5583
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5584
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5585
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5586
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5587
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5588
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5589
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5590
0
      AsmString = "move $\x02, $\x03, $\x01";
5591
0
      break;
5592
0
    }
5593
252
    if (MCInst_getNumOperands(MI) == 4 &&
5594
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5595
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5596
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5597
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5598
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5599
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5600
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5601
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5602
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5603
0
      AsmString = "movue $\x02, $\x03, $\x01";
5604
0
      break;
5605
0
    }
5606
252
    if (MCInst_getNumOperands(MI) == 4 &&
5607
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5608
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5609
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5610
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5611
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5612
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5613
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5614
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5615
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5616
0
      AsmString = "movge $\x02, $\x03, $\x01";
5617
0
      break;
5618
0
    }
5619
252
    if (MCInst_getNumOperands(MI) == 4 &&
5620
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5621
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5622
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5623
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5624
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5625
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5626
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5627
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5628
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5629
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5630
0
      break;
5631
0
    }
5632
252
    if (MCInst_getNumOperands(MI) == 4 &&
5633
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5634
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5635
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5636
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5637
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5638
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5639
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5640
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5641
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5642
0
      AsmString = "movle $\x02, $\x03, $\x01";
5643
0
      break;
5644
0
    }
5645
252
    if (MCInst_getNumOperands(MI) == 4 &&
5646
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5647
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5648
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5649
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5650
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5651
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5652
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5653
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5654
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5655
0
      AsmString = "movule $\x02, $\x03, $\x01";
5656
0
      break;
5657
0
    }
5658
252
    if (MCInst_getNumOperands(MI) == 4 &&
5659
252
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5660
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5661
252
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5662
252
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5663
252
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5664
252
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5665
252
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5666
252
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5667
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5668
0
      AsmString = "movo $\x02, $\x03, $\x01";
5669
0
      break;
5670
0
    }
5671
252
    return NULL;
5672
77.6k
  }
5673
5674
30.4k
  tmp = cs_strdup(AsmString);
5675
30.4k
  AsmMnem = tmp;
5676
204k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5677
204k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
5678
30.1k
      *AsmOps = '\0';
5679
30.1k
      AsmOps++;
5680
30.1k
      break;
5681
30.1k
    }
5682
204k
  }
5683
30.4k
  SStream_concat0(OS, AsmMnem);
5684
30.4k
  if (*AsmOps) {
5685
30.1k
    SStream_concat0(OS, "\t");
5686
30.1k
    if (strstr(AsmOps, "icc"))
5687
6.66k
      Sparc_addReg(MI, SPARC_REG_ICC);
5688
30.1k
    if (strstr(AsmOps, "xcc"))
5689
9.95k
      Sparc_addReg(MI, SPARC_REG_XCC);
5690
212k
    for (c = AsmOps; *c; c++) {
5691
182k
      if (*c == '$') {
5692
45.6k
        c += 1;
5693
45.6k
        if (*c == (char)0xff) {
5694
0
          c += 1;
5695
0
          OpIdx = *c - 1;
5696
0
          c += 1;
5697
0
          PrintMethodIdx = *c - 1;
5698
0
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5699
0
        } else
5700
45.6k
          printOperand(MI, *c - 1, OS);
5701
137k
      } else {
5702
137k
        SStream_concat(OS, "%c", *c);
5703
137k
      }
5704
182k
    }
5705
30.1k
  }
5706
30.4k
  return tmp;
5707
77.6k
}
5708
5709
#endif // PRINT_ALIAS_INSTR