Coverage Report

Created: 2023-09-25 06:24

/src/capstonev5/arch/AArch64/AArch64InstPrinter.c
Line
Count
Source (jump to first uncovered line)
1
//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This class prints an AArch64 MCInst to a .s file.
11
//
12
//===----------------------------------------------------------------------===//
13
14
/* Capstone Disassembly Engine */
15
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2016 */
16
17
#ifdef CAPSTONE_HAS_ARM64
18
19
#include <capstone/platform.h>
20
#include <stdio.h>
21
#include <stdlib.h>
22
23
#include "AArch64InstPrinter.h"
24
#include "AArch64Disassembler.h"
25
#include "AArch64BaseInfo.h"
26
#include "../../utils.h"
27
#include "../../MCInst.h"
28
#include "../../SStream.h"
29
#include "../../MCRegisterInfo.h"
30
#include "../../MathExtras.h"
31
32
#include "AArch64Mapping.h"
33
#include "AArch64AddressingModes.h"
34
35
#define GET_REGINFO_ENUM
36
#include "AArch64GenRegisterInfo.inc"
37
38
#define GET_INSTRINFO_ENUM
39
#include "AArch64GenInstrInfo.inc"
40
41
#include "AArch64GenSubtargetInfo.inc"
42
43
44
static const char *getRegisterName(unsigned RegNo, unsigned AltIdx);
45
static void printOperand(MCInst *MI, unsigned OpNum, SStream *O);
46
static bool printSysAlias(MCInst *MI, SStream *O);
47
static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI);
48
static void printInstruction(MCInst *MI, SStream *O);
49
static void printShifter(MCInst *MI, unsigned OpNum, SStream *O);
50
static void printCustomAliasOperand(MCInst *MI, uint64_t Address, unsigned OpIdx,
51
    unsigned PrintMethodIdx, SStream *OS);
52
53
54
static cs_ac_type get_op_access(cs_struct *h, unsigned int id, unsigned int index)
55
253k
{
56
253k
#ifndef CAPSTONE_DIET
57
253k
  const uint8_t *arr = AArch64_get_op_access(h, id);
58
59
253k
  if (arr[index] == CS_AC_IGNORE)
60
0
    return 0;
61
62
253k
  return arr[index];
63
#else
64
  return 0;
65
#endif
66
253k
}
67
68
static void op_addImm(MCInst *MI, int v)
69
663
{
70
663
  if (MI->csh->detail) {
71
663
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
72
663
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = v;
73
663
    MI->flat_insn->detail->arm64.op_count++;
74
663
  }
75
663
}
76
77
static void set_sme_index(MCInst *MI, bool status)
78
4.17k
{
79
  // Doing SME Index operand
80
4.17k
  MI->csh->doing_SME_Index = status;
81
82
4.17k
  if (MI->csh->detail != CS_OPT_ON)
83
0
    return;
84
85
4.17k
  if (status) {
86
2.88k
    unsigned prevOpNum = MI->flat_insn->detail->arm64.op_count - 1; 
87
2.88k
    unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, prevOpNum));
88
    // Replace previous SME register operand with an OP_SME_INDEX operand
89
2.88k
    MI->flat_insn->detail->arm64.operands[prevOpNum].type = ARM64_OP_SME_INDEX;
90
2.88k
    MI->flat_insn->detail->arm64.operands[prevOpNum].sme_index.reg = Reg;
91
2.88k
    MI->flat_insn->detail->arm64.operands[prevOpNum].sme_index.base = ARM64_REG_INVALID;
92
2.88k
    MI->flat_insn->detail->arm64.operands[prevOpNum].sme_index.disp = 0;
93
2.88k
  }
94
4.17k
}
95
96
static void set_mem_access(MCInst *MI, bool status)
97
82.7k
{
98
  // If status == false, check if this is meant for SME_index
99
82.7k
  if(!status && MI->csh->doing_SME_Index) {
100
1.60k
    MI->csh->doing_SME_Index = status;
101
1.60k
    return;
102
1.60k
  }
103
104
  // Doing Memory Operation
105
81.1k
  MI->csh->doing_mem = status;
106
107
108
81.1k
  if (MI->csh->detail != CS_OPT_ON)
109
0
    return;
110
111
81.1k
  if (status) {
112
40.5k
#ifndef CAPSTONE_DIET
113
40.5k
    uint8_t access;
114
40.5k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
115
40.5k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
116
40.5k
    MI->ac_idx++;
117
40.5k
#endif
118
40.5k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_MEM;
119
40.5k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = ARM64_REG_INVALID;
120
40.5k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = ARM64_REG_INVALID;
121
40.5k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = 0;
122
40.5k
  } else {
123
    // done, create the next operand slot
124
40.5k
    MI->flat_insn->detail->arm64.op_count++;
125
40.5k
  }
126
81.1k
}
127
128
void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
129
90.4k
{
130
  // Check for special encodings and print the canonical alias instead.
131
90.4k
  unsigned Opcode = MCInst_getOpcode(MI);
132
90.4k
  int LSB, Width;
133
90.4k
  char *mnem;
134
135
  // printf(">>> opcode = %u\n", MCInst_getOpcode(MI));
136
137
90.4k
  if (Opcode == AArch64_SYSxt && printSysAlias(MI, O))
138
189
    return;
139
140
  // SBFM/UBFM should print to a nicer aliased form if possible.
141
90.3k
  if (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri ||
142
90.3k
      Opcode == AArch64_UBFMXri || Opcode == AArch64_UBFMWri) {
143
2.35k
    bool IsSigned = (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri);
144
2.35k
    bool Is64Bit = (Opcode == AArch64_SBFMXri || Opcode == AArch64_UBFMXri);
145
146
2.35k
    MCOperand *Op0 = MCInst_getOperand(MI, 0);
147
2.35k
    MCOperand *Op1 = MCInst_getOperand(MI, 1);
148
2.35k
    MCOperand *Op2 = MCInst_getOperand(MI, 2);
149
2.35k
    MCOperand *Op3 = MCInst_getOperand(MI, 3);
150
151
2.35k
    if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 && MCOperand_isImm(Op3)) {
152
1.99k
      const char *AsmMnemonic = NULL;
153
154
1.99k
      switch (MCOperand_getImm(Op3)) {
155
447
        default:
156
447
          break;
157
158
1.19k
        case 7:
159
1.19k
          if (IsSigned)
160
1.18k
            AsmMnemonic = "sxtb";
161
11
          else if (!Is64Bit)
162
3
            AsmMnemonic = "uxtb";
163
1.19k
          break;
164
165
251
        case 15:
166
251
          if (IsSigned)
167
238
            AsmMnemonic = "sxth";
168
13
          else if (!Is64Bit)
169
5
            AsmMnemonic = "uxth";
170
251
          break;
171
172
102
        case 31:
173
          // *xtw is only valid for signed 64-bit operations.
174
102
          if (Is64Bit && IsSigned)
175
85
            AsmMnemonic = "sxtw";
176
102
          break;
177
1.99k
      }
178
179
1.99k
      if (AsmMnemonic) {
180
1.51k
        SStream_concat(O, "%s\t%s, %s", AsmMnemonic,
181
1.51k
            getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
182
1.51k
            getRegisterName(getWRegFromXReg(MCOperand_getReg(Op1)), AArch64_NoRegAltName));
183
184
1.51k
        if (MI->csh->detail) {
185
1.51k
#ifndef CAPSTONE_DIET
186
1.51k
          uint8_t access;
187
1.51k
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
188
1.51k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
189
1.51k
          MI->ac_idx++;
190
1.51k
#endif
191
1.51k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
192
1.51k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
193
1.51k
          MI->flat_insn->detail->arm64.op_count++;
194
1.51k
#ifndef CAPSTONE_DIET
195
1.51k
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
196
1.51k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
197
1.51k
          MI->ac_idx++;
198
1.51k
#endif
199
1.51k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
200
1.51k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = getWRegFromXReg(MCOperand_getReg(Op1));
201
1.51k
          MI->flat_insn->detail->arm64.op_count++;
202
1.51k
        }
203
204
1.51k
        MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic));
205
206
1.51k
        return;
207
1.51k
      }
208
1.99k
    }
209
210
    // All immediate shifts are aliases, implemented using the Bitfield
211
    // instruction. In all cases the immediate shift amount shift must be in
212
    // the range 0 to (reg.size -1).
213
839
    if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) {
214
839
      const char *AsmMnemonic = NULL;
215
839
      int shift = 0;
216
839
      int immr = (int)MCOperand_getImm(Op2);
217
839
      int imms = (int)MCOperand_getImm(Op3);
218
219
839
      if (Opcode == AArch64_UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
220
12
        AsmMnemonic = "lsl";
221
12
        shift = 31 - imms;
222
827
      } else if (Opcode == AArch64_UBFMXri && imms != 0x3f &&
223
827
          ((imms + 1 == immr))) {
224
4
        AsmMnemonic = "lsl";
225
4
        shift = 63 - imms;
226
823
      } else if (Opcode == AArch64_UBFMWri && imms == 0x1f) {
227
14
        AsmMnemonic = "lsr";
228
14
        shift = immr;
229
809
      } else if (Opcode == AArch64_UBFMXri && imms == 0x3f) {
230
22
        AsmMnemonic = "lsr";
231
22
        shift = immr;
232
787
      } else if (Opcode == AArch64_SBFMWri && imms == 0x1f) {
233
2
        AsmMnemonic = "asr";
234
2
        shift = immr;
235
785
      } else if (Opcode == AArch64_SBFMXri && imms == 0x3f) {
236
6
        AsmMnemonic = "asr";
237
6
        shift = immr;
238
6
      }
239
240
839
      if (AsmMnemonic) {
241
60
        SStream_concat(O, "%s\t%s, %s, ", AsmMnemonic,
242
60
            getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
243
60
            getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName));
244
245
60
        printInt32Bang(O, shift);
246
247
60
        MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic));
248
249
60
        if (MI->csh->detail) {
250
60
#ifndef CAPSTONE_DIET
251
60
          uint8_t access;
252
60
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
253
60
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
254
60
          MI->ac_idx++;
255
60
#endif
256
60
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
257
60
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
258
60
          MI->flat_insn->detail->arm64.op_count++;
259
60
#ifndef CAPSTONE_DIET
260
60
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
261
60
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
262
60
          MI->ac_idx++;
263
60
#endif
264
60
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
265
60
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1);
266
60
          MI->flat_insn->detail->arm64.op_count++;
267
60
#ifndef CAPSTONE_DIET
268
60
          access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
269
60
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
270
60
          MI->ac_idx++;
271
60
#endif
272
60
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
273
60
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = shift;
274
60
          MI->flat_insn->detail->arm64.op_count++;
275
60
        }
276
277
60
        return;
278
60
      }
279
839
    }
280
281
    // SBFIZ/UBFIZ aliases
282
779
    if (MCOperand_getImm(Op2) > MCOperand_getImm(Op3)) {
283
181
      SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfiz" : "ubfiz"),
284
181
          getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
285
181
          getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName));
286
287
181
      printInt32Bang(O, (int)((Is64Bit ? 64 : 32) - MCOperand_getImm(Op2)));
288
289
181
      SStream_concat0(O, ", ");
290
291
181
      printInt32Bang(O, (int)MCOperand_getImm(Op3) + 1);
292
293
181
      MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfiz" : "ubfiz"));
294
295
181
      if (MI->csh->detail) {
296
181
#ifndef CAPSTONE_DIET
297
181
        uint8_t access;
298
181
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
299
181
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
300
181
        MI->ac_idx++;
301
181
#endif
302
181
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
303
181
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
304
181
        MI->flat_insn->detail->arm64.op_count++;
305
181
#ifndef CAPSTONE_DIET
306
181
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
307
181
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
308
181
        MI->ac_idx++;
309
181
#endif
310
181
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
311
181
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1);
312
181
        MI->flat_insn->detail->arm64.op_count++;
313
181
#ifndef CAPSTONE_DIET
314
181
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
315
181
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
316
181
        MI->ac_idx++;
317
181
#endif
318
181
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
319
181
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (Is64Bit ? 64 : 32) - (int)MCOperand_getImm(Op2);
320
181
        MI->flat_insn->detail->arm64.op_count++;
321
181
#ifndef CAPSTONE_DIET
322
181
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
323
181
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
324
181
        MI->ac_idx++;
325
181
#endif
326
181
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
327
181
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) + 1;
328
181
        MI->flat_insn->detail->arm64.op_count++;
329
181
      }
330
331
181
      return;
332
181
    }
333
334
    // Otherwise SBFX/UBFX is the preferred form
335
598
    SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfx" : "ubfx"),
336
598
        getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
337
598
        getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName));
338
339
598
    printInt32Bang(O, (int)MCOperand_getImm(Op2));
340
598
    SStream_concat0(O, ", ");
341
598
    printInt32Bang(O, (int)MCOperand_getImm(Op3) - (int)MCOperand_getImm(Op2) + 1);
342
343
598
    MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfx" : "ubfx"));
344
345
598
    if (MI->csh->detail) {
346
598
#ifndef CAPSTONE_DIET
347
598
      uint8_t access;
348
598
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
349
598
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
350
598
      MI->ac_idx++;
351
598
#endif
352
598
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
353
598
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
354
598
      MI->flat_insn->detail->arm64.op_count++;
355
598
#ifndef CAPSTONE_DIET
356
598
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
357
598
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
358
598
      MI->ac_idx++;
359
598
#endif
360
598
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
361
598
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1);
362
598
      MI->flat_insn->detail->arm64.op_count++;
363
598
#ifndef CAPSTONE_DIET
364
598
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
365
598
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
366
598
      MI->ac_idx++;
367
598
#endif
368
598
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
369
598
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op2);
370
598
      MI->flat_insn->detail->arm64.op_count++;
371
598
#ifndef CAPSTONE_DIET
372
598
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
373
598
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
374
598
      MI->ac_idx++;
375
598
#endif
376
598
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
377
598
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) - MCOperand_getImm(Op2) + 1;
378
598
      MI->flat_insn->detail->arm64.op_count++;
379
598
    }
380
381
598
    return;
382
779
  }
383
384
87.9k
  if (Opcode == AArch64_BFMXri || Opcode == AArch64_BFMWri) {
385
435
    MCOperand *Op0 = MCInst_getOperand(MI, 0); // Op1 == Op0
386
435
    MCOperand *Op2 = MCInst_getOperand(MI, 2);
387
435
    int ImmR = (int)MCOperand_getImm(MCInst_getOperand(MI, 3));
388
435
    int ImmS = (int)MCOperand_getImm(MCInst_getOperand(MI, 4));
389
390
435
    if ((MCOperand_getReg(Op2) == AArch64_WZR || MCOperand_getReg(Op2) == AArch64_XZR) &&
391
435
        (ImmR == 0 || ImmS < ImmR)) {
392
      // BFC takes precedence over its entire range, sligtly differently to BFI.
393
24
      int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32;
394
24
      int LSB = (BitWidth - ImmR) % BitWidth;
395
24
      int Width = ImmS + 1;
396
397
24
      SStream_concat(O, "bfc\t%s, ",
398
24
          getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName));
399
400
24
      printInt32Bang(O, LSB);
401
24
      SStream_concat0(O, ", ");
402
24
      printInt32Bang(O, Width);
403
24
      MCInst_setOpcodePub(MI, AArch64_map_insn("bfc"));
404
405
24
      if (MI->csh->detail) {
406
24
#ifndef CAPSTONE_DIET
407
24
        uint8_t access;
408
24
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
409
24
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
410
24
        MI->ac_idx++;
411
24
#endif
412
24
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
413
24
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
414
24
        MI->flat_insn->detail->arm64.op_count++;
415
416
24
#ifndef CAPSTONE_DIET
417
24
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
418
24
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
419
24
        MI->ac_idx++;
420
24
#endif
421
24
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
422
24
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB;
423
24
        MI->flat_insn->detail->arm64.op_count++;
424
24
#ifndef CAPSTONE_DIET
425
24
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
426
24
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
427
24
        MI->ac_idx++;
428
24
#endif
429
24
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
430
24
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width;
431
24
        MI->flat_insn->detail->arm64.op_count++;
432
24
      }
433
434
24
      return;
435
411
    } else if (ImmS < ImmR) {
436
      // BFI alias
437
162
      int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32;
438
162
      LSB = (BitWidth - ImmR) % BitWidth;
439
162
      Width = ImmS + 1;
440
441
162
      SStream_concat(O, "bfi\t%s, %s, ",
442
162
          getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
443
162
          getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName));
444
445
162
      printInt32Bang(O, LSB);
446
162
      SStream_concat0(O, ", ");
447
162
      printInt32Bang(O, Width);
448
449
162
      MCInst_setOpcodePub(MI, AArch64_map_insn("bfi"));
450
451
162
      if (MI->csh->detail) {
452
162
#ifndef CAPSTONE_DIET
453
162
        uint8_t access;
454
162
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
455
162
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
456
162
        MI->ac_idx++;
457
162
#endif
458
162
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
459
162
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
460
162
        MI->flat_insn->detail->arm64.op_count++;
461
162
#ifndef CAPSTONE_DIET
462
162
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
463
162
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
464
162
        MI->ac_idx++;
465
162
#endif
466
162
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
467
162
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2);
468
162
        MI->flat_insn->detail->arm64.op_count++;
469
162
#ifndef CAPSTONE_DIET
470
162
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
471
162
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
472
162
        MI->ac_idx++;
473
162
#endif
474
162
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
475
162
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB;
476
162
        MI->flat_insn->detail->arm64.op_count++;
477
162
#ifndef CAPSTONE_DIET
478
162
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
479
162
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
480
162
        MI->ac_idx++;
481
162
#endif
482
162
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
483
162
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width;
484
162
        MI->flat_insn->detail->arm64.op_count++;
485
162
      }
486
487
162
      return;
488
162
    }
489
490
249
    LSB = ImmR;
491
249
    Width = ImmS - ImmR + 1;
492
    // Otherwise BFXIL the preferred form
493
249
    SStream_concat(O, "bfxil\t%s, %s, ",
494
249
        getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
495
249
        getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName));
496
497
249
    printInt32Bang(O, LSB);
498
249
    SStream_concat0(O, ", ");
499
249
    printInt32Bang(O, Width);
500
501
249
    MCInst_setOpcodePub(MI, AArch64_map_insn("bfxil"));
502
503
249
    if (MI->csh->detail) {
504
249
#ifndef CAPSTONE_DIET
505
249
      uint8_t access;
506
249
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
507
249
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
508
249
      MI->ac_idx++;
509
249
#endif
510
249
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
511
249
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
512
249
      MI->flat_insn->detail->arm64.op_count++;
513
249
#ifndef CAPSTONE_DIET
514
249
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
515
249
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
516
249
      MI->ac_idx++;
517
249
#endif
518
249
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
519
249
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2);
520
249
      MI->flat_insn->detail->arm64.op_count++;
521
249
#ifndef CAPSTONE_DIET
522
249
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
523
249
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
524
249
      MI->ac_idx++;
525
249
#endif
526
249
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
527
249
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB;
528
249
      MI->flat_insn->detail->arm64.op_count++;
529
249
#ifndef CAPSTONE_DIET
530
249
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
531
249
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
532
249
      MI->ac_idx++;
533
249
#endif
534
249
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
535
249
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width;
536
249
      MI->flat_insn->detail->arm64.op_count++;
537
249
    }
538
539
249
    return;
540
435
  }
541
542
  // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
543
  // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
544
  // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
545
  // that can represent the move is the MOV alias, and the rest get printed
546
  // normally.
547
87.5k
  if ((Opcode == AArch64_MOVZXi || Opcode == AArch64_MOVZWi) &&
548
87.5k
      MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2))) {
549
364
    int RegWidth = Opcode == AArch64_MOVZXi ? 64 : 32;
550
364
    int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2));
551
364
    uint64_t Value = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) << Shift;
552
553
364
    if (isMOVZMovAlias(Value, Shift,
554
364
          Opcode == AArch64_MOVZXi ? 64 : 32)) {
555
329
      SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName));
556
557
329
      printInt64Bang(O, SignExtend64(Value, RegWidth));
558
559
329
      if (MI->csh->detail) {
560
329
#ifndef CAPSTONE_DIET
561
329
        uint8_t access;
562
329
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
563
329
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
564
329
        MI->ac_idx++;
565
329
#endif
566
329
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
567
329
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
568
329
        MI->flat_insn->detail->arm64.op_count++;
569
570
329
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
571
329
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth);
572
329
        MI->flat_insn->detail->arm64.op_count++;
573
329
      }
574
575
329
      MCInst_setOpcodePub(MI, AArch64_map_insn("mov"));
576
577
329
      return;
578
329
    }
579
364
  }
580
581
87.1k
  if ((Opcode == AArch64_MOVNXi || Opcode == AArch64_MOVNWi) &&
582
87.1k
      MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2))) {
583
335
    int RegWidth = Opcode == AArch64_MOVNXi ? 64 : 32;
584
335
    int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2));
585
335
    uint64_t Value = ~((uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) << Shift);
586
587
335
    if (RegWidth == 32)
588
41
      Value = Value & 0xffffffff;
589
590
335
    if (AArch64_AM_isMOVNMovAlias(Value, Shift, RegWidth)) {
591
314
      SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName));
592
593
314
      printInt64Bang(O, SignExtend64(Value, RegWidth));
594
595
314
      if (MI->csh->detail) {
596
314
#ifndef CAPSTONE_DIET
597
314
        uint8_t access;
598
314
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
599
314
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
600
314
        MI->ac_idx++;
601
314
#endif
602
314
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
603
314
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
604
314
        MI->flat_insn->detail->arm64.op_count++;
605
606
314
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
607
314
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth);
608
314
        MI->flat_insn->detail->arm64.op_count++;
609
314
      }
610
611
314
      MCInst_setOpcodePub(MI, AArch64_map_insn("mov"));
612
613
314
      return;
614
314
    }
615
335
  }
616
617
86.8k
  if ((Opcode == AArch64_ORRXri || Opcode == AArch64_ORRWri) &&
618
86.8k
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR ||
619
686
       MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR) &&
620
86.8k
      MCOperand_isImm(MCInst_getOperand(MI, 2))) {
621
113
    int RegWidth = Opcode == AArch64_ORRXri ? 64 : 32;
622
113
    uint64_t Value = AArch64_AM_decodeLogicalImmediate(
623
113
        MCOperand_getImm(MCInst_getOperand(MI, 2)), RegWidth);
624
113
    SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName));
625
626
113
    printInt64Bang(O, SignExtend64(Value, RegWidth));
627
628
113
    if (MI->csh->detail) {
629
113
#ifndef CAPSTONE_DIET
630
113
      uint8_t access;
631
113
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
632
113
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
633
113
      MI->ac_idx++;
634
113
#endif
635
113
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
636
113
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
637
113
      MI->flat_insn->detail->arm64.op_count++;
638
639
113
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
640
113
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth);
641
113
      MI->flat_insn->detail->arm64.op_count++;
642
113
    }
643
644
113
    MCInst_setOpcodePub(MI, AArch64_map_insn("mov"));
645
646
113
    return;
647
113
  }
648
649
  // Instruction TSB is specified as a one operand instruction, but 'csync' is
650
  // not encoded, so for printing it is treated as a special case here:
651
86.7k
  if (Opcode == AArch64_TSB) {
652
6
    SStream_concat0(O, "tsb\tcsync");
653
6
    MCInst_setOpcodePub(MI, AArch64_map_insn("tsb"));
654
6
    return;
655
6
  }
656
657
86.7k
  MI->MRI = Info;
658
659
86.7k
  mnem = printAliasInstr(MI, O, (MCRegisterInfo *)Info);
660
86.7k
  if (mnem) {
661
9.03k
    MCInst_setOpcodePub(MI, AArch64_map_insn(mnem));
662
9.03k
    cs_mem_free(mnem);
663
664
9.03k
    switch(MCInst_getOpcode(MI)) {
665
5.26k
      default: break;
666
5.26k
      case AArch64_LD1i8_POST:
667
23
        arm64_op_addImm(MI, 1);
668
23
        break;
669
35
      case AArch64_LD1i16_POST:
670
35
        arm64_op_addImm(MI, 2);
671
35
        break;
672
193
      case AArch64_LD1i32_POST:
673
193
        arm64_op_addImm(MI, 4);
674
193
        break;
675
2
      case AArch64_LD1Onev1d_POST:
676
4
      case AArch64_LD1Onev2s_POST:
677
10
      case AArch64_LD1Onev4h_POST:
678
19
      case AArch64_LD1Onev8b_POST:
679
27
      case AArch64_LD1i64_POST:
680
27
        arm64_op_addImm(MI, 8);
681
27
        break;
682
0
      case AArch64_LD1Onev16b_POST:
683
230
      case AArch64_LD1Onev2d_POST:
684
307
      case AArch64_LD1Onev4s_POST:
685
453
      case AArch64_LD1Onev8h_POST:
686
462
      case AArch64_LD1Twov1d_POST:
687
501
      case AArch64_LD1Twov2s_POST:
688
504
      case AArch64_LD1Twov4h_POST:
689
527
      case AArch64_LD1Twov8b_POST:
690
527
        arm64_op_addImm(MI, 16);
691
527
        break;
692
6
      case AArch64_LD1Threev1d_POST:
693
463
      case AArch64_LD1Threev2s_POST:
694
519
      case AArch64_LD1Threev4h_POST:
695
524
      case AArch64_LD1Threev8b_POST:
696
524
        arm64_op_addImm(MI, 24);
697
524
        break;
698
2
      case AArch64_LD1Fourv1d_POST:
699
70
      case AArch64_LD1Fourv2s_POST:
700
74
      case AArch64_LD1Fourv4h_POST:
701
74
      case AArch64_LD1Fourv8b_POST:
702
115
      case AArch64_LD1Twov16b_POST:
703
142
      case AArch64_LD1Twov2d_POST:
704
146
      case AArch64_LD1Twov4s_POST:
705
148
      case AArch64_LD1Twov8h_POST:
706
148
        arm64_op_addImm(MI, 32);
707
148
        break;
708
49
      case AArch64_LD1Threev16b_POST:
709
65
      case AArch64_LD1Threev2d_POST:
710
95
      case AArch64_LD1Threev4s_POST:
711
131
      case AArch64_LD1Threev8h_POST:
712
131
         arm64_op_addImm(MI, 48);
713
131
         break;
714
16
      case AArch64_LD1Fourv16b_POST:
715
29
      case AArch64_LD1Fourv2d_POST:
716
33
      case AArch64_LD1Fourv4s_POST:
717
47
      case AArch64_LD1Fourv8h_POST:
718
47
        arm64_op_addImm(MI, 64);
719
47
        break;
720
4
      case AArch64_UMOVvi64:
721
4
        arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D);
722
4
        break;
723
5
      case AArch64_UMOVvi32:
724
5
        arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S);
725
5
        break;
726
14
      case AArch64_INSvi8gpr:
727
17
      case AArch64_DUP_ZI_B:
728
83
      case AArch64_CPY_ZPmI_B:
729
185
      case AArch64_CPY_ZPzI_B:
730
188
      case AArch64_CPY_ZPmV_B:
731
242
      case AArch64_CPY_ZPmR_B:
732
416
      case AArch64_DUP_ZR_B:
733
416
        if (MI->csh->detail) {
734
416
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
735
416
        }
736
416
        break;
737
7
      case AArch64_INSvi16gpr:
738
12
      case AArch64_DUP_ZI_H:
739
40
      case AArch64_CPY_ZPmI_H:
740
145
      case AArch64_CPY_ZPzI_H:
741
163
      case AArch64_CPY_ZPmV_H:
742
215
      case AArch64_CPY_ZPmR_H:
743
228
      case AArch64_DUP_ZR_H:
744
248
      case AArch64_FCPY_ZPmI_H:
745
266
      case AArch64_FDUP_ZI_H:
746
266
        if (MI->csh->detail) {
747
266
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
748
266
        }
749
266
        break;
750
2
      case AArch64_INSvi32gpr:
751
54
      case AArch64_DUP_ZI_S:
752
114
      case AArch64_CPY_ZPmI_S:
753
153
      case AArch64_CPY_ZPzI_S:
754
228
      case AArch64_CPY_ZPmV_S:
755
228
      case AArch64_CPY_ZPmR_S:
756
234
      case AArch64_DUP_ZR_S:
757
238
      case AArch64_FCPY_ZPmI_S:
758
255
      case AArch64_FDUP_ZI_S:
759
255
        if (MI->csh->detail) {
760
255
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
761
255
        }
762
255
        break;
763
25
      case AArch64_INSvi64gpr:
764
45
      case AArch64_DUP_ZI_D:
765
54
      case AArch64_CPY_ZPmI_D:
766
217
      case AArch64_CPY_ZPzI_D:
767
219
      case AArch64_CPY_ZPmV_D:
768
233
      case AArch64_CPY_ZPmR_D:
769
433
      case AArch64_DUP_ZR_D:
770
448
      case AArch64_FCPY_ZPmI_D:
771
452
      case AArch64_FDUP_ZI_D:
772
452
        if (MI->csh->detail) {
773
452
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
774
452
        }
775
452
        break;
776
36
      case AArch64_INSvi8lane:
777
41
      case AArch64_ORR_PPzPP:
778
48
      case AArch64_ORRS_PPzPP:
779
48
        if (MI->csh->detail) {
780
48
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
781
48
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1B;
782
48
        }
783
48
        break;
784
17
      case AArch64_INSvi16lane:
785
17
        if (MI->csh->detail) {
786
17
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
787
17
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1H;
788
17
        }
789
17
         break;
790
24
      case AArch64_INSvi32lane:
791
24
        if (MI->csh->detail) {
792
24
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
793
24
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1S;
794
24
        }
795
24
        break;
796
49
      case AArch64_INSvi64lane:
797
49
      case AArch64_ORR_ZZZ:
798
49
        if (MI->csh->detail) {
799
49
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
800
49
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1D;
801
49
        }
802
49
        break;
803
0
      case AArch64_ORRv16i8:
804
270
      case AArch64_NOTv16i8:
805
270
        if (MI->csh->detail) {
806
270
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_16B;
807
270
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_16B;
808
270
        }
809
270
        break;
810
3
      case AArch64_ORRv8i8:
811
9
      case AArch64_NOTv8i8:
812
9
        if (MI->csh->detail) {
813
9
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_8B;
814
9
          MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_8B;
815
9
        }
816
9
        break;
817
3
      case AArch64_AND_PPzPP:
818
7
      case AArch64_ANDS_PPzPP:
819
19
      case AArch64_EOR_PPzPP:
820
24
      case AArch64_EORS_PPzPP:
821
37
      case AArch64_SEL_PPPP:
822
57
      case AArch64_SEL_ZPZZ_B:
823
57
        if (MI->csh->detail) {
824
57
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
825
57
          MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1B;
826
57
        }
827
57
        break;
828
27
      case AArch64_SEL_ZPZZ_D:
829
27
        if (MI->csh->detail) {
830
27
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
831
27
          MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1D;
832
27
        }
833
27
        break;
834
40
      case AArch64_SEL_ZPZZ_H:
835
40
        if (MI->csh->detail) {
836
40
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
837
40
          MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1H;
838
40
        }
839
40
        break;
840
8
      case AArch64_SEL_ZPZZ_S:
841
8
        if (MI->csh->detail) {
842
8
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
843
8
          MI->flat_insn->detail->arm64.operands[2].vas = ARM64_VAS_1S;
844
8
        }
845
8
        break;
846
43
      case AArch64_DUP_ZZI_B:
847
43
        if (MI->csh->detail) {
848
43
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1B;
849
43
          if (MI->flat_insn->detail->arm64.op_count == 1) {
850
0
            arm64_op_addReg(MI, ARM64_REG_B0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
851
43
          } else {
852
43
            MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1B;
853
43
          }
854
43
        }
855
43
        break;
856
32
      case AArch64_DUP_ZZI_D:
857
32
        if (MI->csh->detail) {
858
32
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1D;
859
32
          if (MI->flat_insn->detail->arm64.op_count == 1) {
860
0
            arm64_op_addReg(MI, ARM64_REG_D0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
861
32
          } else {
862
32
            MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1D;
863
32
          }
864
32
        }
865
32
        break;
866
4
      case AArch64_DUP_ZZI_H:
867
4
        if (MI->csh->detail) {
868
4
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1H;
869
4
          if (MI->flat_insn->detail->arm64.op_count == 1) {
870
0
            arm64_op_addReg(MI, ARM64_REG_H0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
871
4
          } else {
872
4
            MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1H;
873
4
          }
874
4
        }
875
4
        break;
876
75
      case AArch64_DUP_ZZI_Q:
877
75
        if (MI->csh->detail) {
878
75
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1Q;
879
75
          if (MI->flat_insn->detail->arm64.op_count == 1) {
880
0
            arm64_op_addReg(MI, ARM64_REG_Q0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
881
75
          } else {
882
75
            MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1Q;
883
75
          }
884
75
         }
885
75
         break;
886
2
      case AArch64_DUP_ZZI_S:
887
2
        if (MI->csh->detail) {
888
2
          MI->flat_insn->detail->arm64.operands[0].vas = ARM64_VAS_1S;
889
2
          if (MI->flat_insn->detail->arm64.op_count == 1) {
890
0
            arm64_op_addReg(MI, ARM64_REG_S0 + MCOperand_getReg(MCInst_getOperand(MI, 1)) - ARM64_REG_Z0);
891
2
          } else {
892
2
             MI->flat_insn->detail->arm64.operands[1].vas = ARM64_VAS_1S;
893
2
          }
894
2
        }
895
2
        break;
896
      // Hacky detail filling of SMSTART and SMSTOP alias'
897
8
      case AArch64_MSRpstatesvcrImm1:{
898
8
        if(MI->csh->detail){
899
8
          MI->flat_insn->detail->arm64.op_count = 2;
900
8
#ifndef CAPSTONE_DIET
901
8
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
902
8
          MI->ac_idx++;
903
8
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
904
8
          MI->ac_idx++;
905
8
#endif
906
8
          MI->flat_insn->detail->arm64.operands[0].type = ARM64_OP_SVCR;
907
8
          MI->flat_insn->detail->arm64.operands[0].sys = (unsigned)ARM64_SYSREG_SVCR;
908
8
          MI->flat_insn->detail->arm64.operands[0].svcr = lookupSVCRByEncoding(MCOperand_getImm(MCInst_getOperand(MI, 0)))->Encoding;
909
8
          MI->flat_insn->detail->arm64.operands[1].type = ARM64_OP_IMM;
910
8
          MI->flat_insn->detail->arm64.operands[1].imm = MCOperand_getImm(MCInst_getOperand(MI, 1));
911
8
        }
912
8
        break;
913
37
      }
914
9.03k
    }
915
77.7k
  } else {
916
77.7k
    printInstruction(MI, O);
917
77.7k
  }
918
86.7k
}
919
920
static bool printSysAlias(MCInst *MI, SStream *O)
921
397
{
922
  // unsigned Opcode = MCInst_getOpcode(MI);
923
  //assert(Opcode == AArch64_SYSxt && "Invalid opcode for SYS alias!");
924
925
397
  const char *Ins;
926
397
  uint16_t Encoding;
927
397
  bool NeedsReg;
928
397
  char Name[64];
929
397
  MCOperand *Op1 = MCInst_getOperand(MI, 0);
930
397
  MCOperand *Cn = MCInst_getOperand(MI, 1);
931
397
  MCOperand *Cm = MCInst_getOperand(MI, 2);
932
397
  MCOperand *Op2 = MCInst_getOperand(MI, 3);
933
934
397
  unsigned Op1Val = (unsigned)MCOperand_getImm(Op1);
935
397
  unsigned CnVal = (unsigned)MCOperand_getImm(Cn);
936
397
  unsigned CmVal = (unsigned)MCOperand_getImm(Cm);
937
397
  unsigned Op2Val = (unsigned)MCOperand_getImm(Op2);
938
939
397
  Encoding = Op2Val;
940
397
  Encoding |= CmVal << 3;
941
397
  Encoding |= CnVal << 7;
942
397
  Encoding |= Op1Val << 11;
943
944
397
  if (CnVal == 7) {
945
297
    switch (CmVal) {
946
17
      default:
947
17
        return false;
948
949
      // IC aliases
950
59
      case 1: case 5: {
951
59
        const IC *IC = lookupICByEncoding(Encoding);
952
        // if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
953
59
        if (!IC)
954
19
          return false;
955
956
40
        NeedsReg = IC->NeedsReg;
957
40
        Ins = "ic";
958
40
        strncpy(Name, IC->Name, sizeof(Name) - 1);
959
40
      }
960
0
      break;
961
962
      // DC aliases
963
85
      case 4: case 6: case 10: case 11: case 12: case 14: {
964
85
        const DC *DC = lookupDCByEncoding(Encoding);
965
        // if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
966
85
        if (!DC)
967
34
          return false;
968
969
51
        NeedsReg = true;
970
51
        Ins = "dc";
971
51
        strncpy(Name, DC->Name, sizeof(Name) - 1);
972
51
      }
973
0
      break;
974
975
      // AT aliases
976
136
      case 8: case 9: {
977
136
        const AT *AT = lookupATByEncoding(Encoding);
978
        // if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
979
136
        if (!AT)
980
61
          return false;
981
982
75
        NeedsReg = true;
983
75
        Ins = "at";
984
75
        strncpy(Name, AT->Name, sizeof(Name) - 1);
985
75
      }
986
0
      break;
987
297
    }
988
297
  } else if (CnVal == 8) {
989
    // TLBI aliases
990
76
    const TLBI *TLBI = lookupTLBIByEncoding(Encoding);
991
    // if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
992
76
    if (!TLBI)
993
53
      return false;
994
995
23
    NeedsReg = TLBI->NeedsReg;
996
23
    Ins = "tlbi";
997
23
    strncpy(Name, TLBI->Name, sizeof(Name) - 1);
998
23
  } else
999
24
    return false;
1000
1001
189
  SStream_concat(O, "%s\t%s", Ins, Name);
1002
1003
189
  if (NeedsReg) {
1004
134
    SStream_concat(O, ", %s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 4)), AArch64_NoRegAltName));
1005
134
  }
1006
1007
189
  MCInst_setOpcodePub(MI, AArch64_map_insn(Ins));
1008
1009
189
  if (MI->csh->detail) {
1010
#if 0
1011
#ifndef CAPSTONE_DIET
1012
    uint8_t access;
1013
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1014
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1015
    MI->ac_idx++;
1016
#endif
1017
#endif
1018
189
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
1019
189
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = AArch64_map_sys_op(Name);
1020
189
    MI->flat_insn->detail->arm64.op_count++;
1021
1022
189
    if (NeedsReg) {
1023
134
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1024
134
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 4));
1025
134
      MI->flat_insn->detail->arm64.op_count++;
1026
134
    }
1027
189
  }
1028
1029
189
  return true;
1030
397
}
1031
1032
static void printOperand(MCInst *MI, unsigned OpNum, SStream *O)
1033
130k
{
1034
130k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1035
1036
130k
  if (MCOperand_isReg(Op)) {
1037
111k
    unsigned Reg = MCOperand_getReg(Op);
1038
1039
111k
    SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
1040
1041
111k
    if (MI->csh->detail) {
1042
111k
      if (MI->csh->doing_mem) {
1043
47.0k
        if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base == ARM64_REG_INVALID) {
1044
40.2k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = Reg;
1045
40.2k
        }
1046
6.74k
        else if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index == ARM64_REG_INVALID) {
1047
6.74k
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = Reg;
1048
6.74k
        }
1049
64.2k
      } else if (MI->csh->doing_SME_Index) {
1050
        // Access op_count-1 as We want to add info to previous operand, not create a new one
1051
2.88k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count-1].sme_index.base = Reg;
1052
61.4k
      } else {
1053
61.4k
#ifndef CAPSTONE_DIET
1054
61.4k
        uint8_t access;
1055
1056
61.4k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1057
61.4k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1058
61.4k
        MI->ac_idx++;
1059
61.4k
#endif
1060
61.4k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1061
61.4k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
1062
61.4k
        MI->flat_insn->detail->arm64.op_count++;
1063
61.4k
      }
1064
111k
    }
1065
111k
  } else if (MCOperand_isImm(Op)) {
1066
18.7k
    int64_t imm = MCOperand_getImm(Op);
1067
1068
18.7k
    if (MI->Opcode == AArch64_ADR) {
1069
1.25k
      imm += MI->address;
1070
1.25k
      printUInt64Bang(O, imm);
1071
17.4k
    } else {
1072
17.4k
      if (MI->csh->doing_mem) {
1073
5.34k
        if (MI->csh->imm_unsigned) {
1074
0
          printUInt64Bang(O, imm);
1075
5.34k
        } else {
1076
5.34k
          printInt64Bang(O, imm);
1077
5.34k
        }
1078
5.34k
      } else
1079
12.1k
        printUInt64Bang(O, imm);
1080
17.4k
    }
1081
1082
18.7k
    if (MI->csh->detail) {
1083
18.7k
      if (MI->csh->doing_mem) {
1084
5.34k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)imm;
1085
13.3k
      } else if (MI->csh->doing_SME_Index) {
1086
        // Access op_count-1 as We want to add info to previous operand, not create a new one
1087
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count-1].sme_index.disp = (int32_t)imm; 
1088
13.3k
      } else {
1089
13.3k
#ifndef CAPSTONE_DIET
1090
13.3k
        uint8_t access;
1091
1092
13.3k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1093
13.3k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1094
13.3k
#endif
1095
13.3k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1096
13.3k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
1097
13.3k
        MI->flat_insn->detail->arm64.op_count++;
1098
13.3k
      }
1099
18.7k
    }
1100
18.7k
  }
1101
130k
}
1102
1103
static void printImm(MCInst *MI, unsigned OpNum, SStream *O)
1104
1.83k
{
1105
1.83k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1106
1.83k
  printUInt64Bang(O, MCOperand_getImm(Op));
1107
1108
1.83k
  if (MI->csh->detail) {
1109
1.83k
#ifndef CAPSTONE_DIET
1110
1.83k
    uint8_t access;
1111
1.83k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1112
1.83k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1113
1.83k
    MI->ac_idx++;
1114
1.83k
#endif
1115
1.83k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1116
1.83k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
1117
1.83k
    MI->flat_insn->detail->arm64.op_count++;
1118
1.83k
  }
1119
1.83k
}
1120
1121
static void printImmHex(MCInst *MI, unsigned OpNum, SStream *O)
1122
42
{
1123
42
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1124
42
  printUInt64Bang(O, MCOperand_getImm(Op));
1125
1126
42
  if (MI->csh->detail) {
1127
42
#ifndef CAPSTONE_DIET
1128
42
    uint8_t access;
1129
42
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1130
42
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1131
42
    MI->ac_idx++;
1132
42
#endif
1133
42
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1134
42
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
1135
42
    MI->flat_insn->detail->arm64.op_count++;
1136
42
  }
1137
42
}
1138
1139
160
static void printSImm(MCInst *MI, unsigned OpNo, SStream *O, int Size) {
1140
160
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
1141
160
  if (Size == 8)
1142
114
  printInt64Bang(O, (signed char) MCOperand_getImm(Op));
1143
46
  else if (Size == 16)
1144
46
  printInt64Bang(O, (signed short) MCOperand_getImm(Op));
1145
0
  else
1146
0
    printInt64Bang(O, MCOperand_getImm(Op));
1147
1148
160
  if (MI->csh->detail) {
1149
160
#ifndef CAPSTONE_DIET
1150
160
    uint8_t access;
1151
160
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1152
160
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1153
160
    MI->ac_idx++;
1154
160
#endif
1155
160
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1156
160
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
1157
160
    MI->flat_insn->detail->arm64.op_count++;
1158
160
  }
1159
160
}
1160
1161
static void printPostIncOperand(MCInst *MI, unsigned OpNum, SStream *O,
1162
    unsigned Imm)
1163
6.71k
{
1164
6.71k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1165
1166
6.71k
  if (MCOperand_isReg(Op)) {
1167
6.71k
    unsigned Reg = MCOperand_getReg(Op);
1168
6.71k
    if (Reg == AArch64_XZR) {
1169
0
      printInt32Bang(O, Imm);
1170
1171
0
      if (MI->csh->detail) {
1172
0
#ifndef CAPSTONE_DIET
1173
0
        uint8_t access;
1174
1175
0
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1176
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1177
0
        MI->ac_idx++;
1178
0
#endif
1179
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1180
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Imm;
1181
0
        MI->flat_insn->detail->arm64.op_count++;
1182
0
      }
1183
6.71k
    } else {
1184
6.71k
      SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
1185
1186
6.71k
      if (MI->csh->detail) {
1187
6.71k
#ifndef CAPSTONE_DIET
1188
6.71k
        uint8_t access;
1189
1190
6.71k
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1191
6.71k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1192
6.71k
        MI->ac_idx++;
1193
6.71k
#endif
1194
6.71k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1195
6.71k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
1196
6.71k
        MI->flat_insn->detail->arm64.op_count++;
1197
6.71k
      }
1198
6.71k
    }
1199
6.71k
  }
1200
  //llvm_unreachable("unknown operand kind in printPostIncOperand64");
1201
6.71k
}
1202
1203
static void printVRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
1204
15.8k
{
1205
15.8k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1206
  //assert(Op.isReg() && "Non-register vreg operand!");
1207
15.8k
  unsigned Reg = MCOperand_getReg(Op);
1208
1209
15.8k
  SStream_concat0(O, getRegisterName(Reg, AArch64_vreg));
1210
1211
15.8k
  if (MI->csh->detail) {
1212
15.8k
#ifndef CAPSTONE_DIET
1213
15.8k
    uint8_t access;
1214
15.8k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1215
15.8k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1216
15.8k
    MI->ac_idx++;
1217
15.8k
#endif
1218
15.8k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1219
15.8k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg);
1220
15.8k
    MI->flat_insn->detail->arm64.op_count++;
1221
15.8k
  }
1222
15.8k
}
1223
1224
static void printSysCROperand(MCInst *MI, unsigned OpNum, SStream *O)
1225
420
{
1226
420
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1227
  //assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
1228
420
  SStream_concat(O, "c%u", MCOperand_getImm(Op));
1229
1230
420
  if (MI->csh->detail) {
1231
420
#ifndef CAPSTONE_DIET
1232
420
    uint8_t access;
1233
1234
420
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1235
420
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1236
420
    MI->ac_idx++;
1237
420
#endif
1238
420
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_CIMM;
1239
420
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
1240
420
    MI->flat_insn->detail->arm64.op_count++;
1241
420
  }
1242
420
}
1243
1244
static void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O)
1245
663
{
1246
663
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
1247
663
  if (MCOperand_isImm(MO)) {
1248
663
    unsigned Val = (MCOperand_getImm(MO) & 0xfff);
1249
    //assert(Val == MO.getImm() && "Add/sub immediate out of range!");
1250
663
    unsigned Shift = AArch64_AM_getShiftValue((int)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)));
1251
1252
663
    printInt32Bang(O, Val);
1253
1254
663
    if (MI->csh->detail) {
1255
663
#ifndef CAPSTONE_DIET
1256
663
      uint8_t access;
1257
1258
663
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1259
663
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1260
663
      MI->ac_idx++;
1261
663
#endif
1262
663
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1263
663
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
1264
663
      MI->flat_insn->detail->arm64.op_count++;
1265
663
    }
1266
1267
663
    if (Shift != 0)
1268
277
      printShifter(MI, OpNum + 1, O);
1269
663
  }
1270
663
}
1271
1272
static void printLogicalImm32(MCInst *MI, unsigned OpNum, SStream *O)
1273
1.35k
{
1274
1.35k
  int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1275
1276
1.35k
  Val = AArch64_AM_decodeLogicalImmediate(Val, 32);
1277
1.35k
  printUInt32Bang(O, (int)Val);
1278
1279
1.35k
  if (MI->csh->detail) {
1280
1.35k
#ifndef CAPSTONE_DIET
1281
1.35k
    uint8_t access;
1282
1283
1.35k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1284
1.35k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1285
1.35k
    MI->ac_idx++;
1286
1.35k
#endif
1287
1.35k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1288
1.35k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
1289
1.35k
    MI->flat_insn->detail->arm64.op_count++;
1290
1.35k
  }
1291
1.35k
}
1292
1293
static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O)
1294
1.06k
{
1295
1.06k
  int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1296
1.06k
  Val = AArch64_AM_decodeLogicalImmediate(Val, 64);
1297
1298
1.06k
  switch(MI->flat_insn->id) {
1299
463
    default:
1300
463
      printInt64Bang(O, Val);
1301
463
      break;
1302
1303
329
    case ARM64_INS_ORR:
1304
528
    case ARM64_INS_AND:
1305
598
    case ARM64_INS_EOR:
1306
598
    case ARM64_INS_TST:
1307
      // do not print number in negative form
1308
598
      if (Val >= 0 && Val <= HEX_THRESHOLD)
1309
45
        SStream_concat(O, "#%u", (int)Val);
1310
553
      else
1311
553
        SStream_concat(O, "#0x%"PRIx64, Val);
1312
598
      break;
1313
1.06k
  }
1314
1315
1.06k
  if (MI->csh->detail) {
1316
1.06k
#ifndef CAPSTONE_DIET
1317
1.06k
    uint8_t access;
1318
1319
1.06k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1320
1.06k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1321
1.06k
    MI->ac_idx++;
1322
1.06k
#endif
1323
1.06k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1324
1.06k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int64_t)Val;
1325
1.06k
    MI->flat_insn->detail->arm64.op_count++;
1326
1.06k
  }
1327
1.06k
}
1328
1329
static void printShifter(MCInst *MI, unsigned OpNum, SStream *O)
1330
5.13k
{
1331
5.13k
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1332
1333
  // LSL #0 should not be printed.
1334
5.13k
  if (AArch64_AM_getShiftType(Val) == AArch64_AM_LSL &&
1335
5.13k
      AArch64_AM_getShiftValue(Val) == 0)
1336
240
    return;
1337
1338
4.89k
  SStream_concat(O, ", %s ", AArch64_AM_getShiftExtendName(AArch64_AM_getShiftType(Val)));
1339
4.89k
  printInt32BangDec(O, AArch64_AM_getShiftValue(Val));
1340
1341
4.89k
  if (MI->csh->detail) {
1342
4.89k
    arm64_shifter shifter = ARM64_SFT_INVALID;
1343
1344
4.89k
    switch(AArch64_AM_getShiftType(Val)) {
1345
0
      default:  // never reach
1346
3.06k
      case AArch64_AM_LSL:
1347
3.06k
        shifter = ARM64_SFT_LSL;
1348
3.06k
        break;
1349
1350
886
      case AArch64_AM_LSR:
1351
886
        shifter = ARM64_SFT_LSR;
1352
886
        break;
1353
1354
367
      case AArch64_AM_ASR:
1355
367
        shifter = ARM64_SFT_ASR;
1356
367
        break;
1357
1358
542
      case AArch64_AM_ROR:
1359
542
        shifter = ARM64_SFT_ROR;
1360
542
        break;
1361
1362
36
      case AArch64_AM_MSL:
1363
36
        shifter = ARM64_SFT_MSL;
1364
36
        break;
1365
4.89k
    }
1366
1367
4.89k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = shifter;
1368
4.89k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = AArch64_AM_getShiftValue(Val);
1369
4.89k
  }
1370
4.89k
}
1371
1372
static void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O)
1373
3.92k
{
1374
3.92k
  SStream_concat0(O, getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName));
1375
1376
3.92k
  if (MI->csh->detail) {
1377
3.92k
#ifndef CAPSTONE_DIET
1378
3.92k
    uint8_t access;
1379
3.92k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1380
3.92k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1381
3.92k
    MI->ac_idx++;
1382
3.92k
#endif
1383
3.92k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1384
3.92k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
1385
3.92k
    MI->flat_insn->detail->arm64.op_count++;
1386
3.92k
  }
1387
1388
3.92k
  printShifter(MI, OpNum + 1, O);
1389
3.92k
}
1390
1391
static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O)
1392
751
{
1393
751
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1394
751
  AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val);
1395
751
  unsigned ShiftVal = AArch64_AM_getArithShiftValue(Val);
1396
1397
  // If the destination or first source register operand is [W]SP, print
1398
  // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
1399
  // all.
1400
751
  if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) {
1401
287
    unsigned Dest = MCOperand_getReg(MCInst_getOperand(MI, 0));
1402
287
    unsigned Src1 = MCOperand_getReg(MCInst_getOperand(MI, 1));
1403
1404
287
    if (((Dest == AArch64_SP || Src1 == AArch64_SP) &&
1405
287
          ExtType == AArch64_AM_UXTX) ||
1406
287
        ((Dest == AArch64_WSP || Src1 == AArch64_WSP) &&
1407
175
         ExtType == AArch64_AM_UXTW)) {
1408
175
      if (ShiftVal != 0) {
1409
175
        SStream_concat0(O, ", lsl ");
1410
175
        printInt32Bang(O, ShiftVal);
1411
1412
175
        if (MI->csh->detail) {
1413
175
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
1414
175
          MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal;
1415
175
        }
1416
175
      }
1417
1418
175
      return;
1419
175
    }
1420
287
  }
1421
1422
576
  SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType));
1423
1424
576
  if (MI->csh->detail) {
1425
576
    arm64_extender ext = ARM64_EXT_INVALID;
1426
576
    switch(ExtType) {
1427
0
      default:  // never reach
1428
1429
64
      case AArch64_AM_UXTB:
1430
64
        ext = ARM64_EXT_UXTB;
1431
64
        break;
1432
1433
152
      case AArch64_AM_UXTH:
1434
152
        ext = ARM64_EXT_UXTH;
1435
152
        break;
1436
1437
46
      case AArch64_AM_UXTW:
1438
46
        ext = ARM64_EXT_UXTW;
1439
46
        break;
1440
1441
66
      case AArch64_AM_UXTX:
1442
66
        ext = ARM64_EXT_UXTX;
1443
66
        break;
1444
1445
83
      case AArch64_AM_SXTB:
1446
83
        ext = ARM64_EXT_SXTB;
1447
83
        break;
1448
1449
50
      case AArch64_AM_SXTH:
1450
50
        ext = ARM64_EXT_SXTH;
1451
50
        break;
1452
1453
77
      case AArch64_AM_SXTW:
1454
77
        ext = ARM64_EXT_SXTW;
1455
77
        break;
1456
1457
38
      case AArch64_AM_SXTX:
1458
38
        ext = ARM64_EXT_SXTX;
1459
38
        break;
1460
576
    }
1461
1462
576
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].ext = ext;
1463
576
  }
1464
1465
576
  if (ShiftVal != 0) {
1466
450
    SStream_concat0(O, " ");
1467
450
    printInt32Bang(O, ShiftVal);
1468
1469
450
    if (MI->csh->detail) {
1470
450
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
1471
450
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal;
1472
450
    }
1473
450
  }
1474
576
}
1475
1476
static void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O)
1477
532
{
1478
532
  unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
1479
1480
532
  SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
1481
1482
532
  if (MI->csh->detail) {
1483
532
#ifndef CAPSTONE_DIET
1484
532
    uint8_t access;
1485
532
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1486
532
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1487
532
    MI->ac_idx++;
1488
532
#endif
1489
532
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1490
532
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
1491
532
    MI->flat_insn->detail->arm64.op_count++;
1492
532
  }
1493
1494
532
  printArithExtend(MI, OpNum + 1, O);
1495
532
}
1496
1497
static void printMemExtendImpl(MCInst *MI, bool SignExtend, bool DoShift, unsigned Width,
1498
             char SrcRegKind, SStream *O)
1499
6.42k
{
1500
  // sxtw, sxtx, uxtw or lsl (== uxtx)
1501
6.42k
  bool IsLSL = !SignExtend && SrcRegKind == 'x';
1502
6.42k
  if (IsLSL) {
1503
3.18k
    SStream_concat0(O, "lsl");
1504
1505
3.18k
    if (MI->csh->detail) {
1506
3.18k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL;
1507
3.18k
    }
1508
3.23k
  } else {
1509
3.23k
    SStream_concat(O, "%cxt%c", (SignExtend ? 's' : 'u'), SrcRegKind);
1510
1511
3.23k
    if (MI->csh->detail) {
1512
3.23k
      if (!SignExtend) {
1513
2.08k
        switch(SrcRegKind) {
1514
0
          default: break;
1515
0
          case 'b':
1516
0
               MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTB;
1517
0
               break;
1518
0
          case 'h':
1519
0
               MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTH;
1520
0
               break;
1521
2.08k
          case 'w':
1522
2.08k
               MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTW;
1523
2.08k
               break;
1524
2.08k
        }
1525
2.08k
      } else {
1526
1.14k
          switch(SrcRegKind) {
1527
0
            default: break;
1528
0
            case 'b':
1529
0
              MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTB;
1530
0
              break;
1531
0
            case 'h':
1532
0
              MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTH;
1533
0
              break;
1534
813
            case 'w':
1535
813
              MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTW;
1536
813
              break;
1537
335
            case 'x':
1538
335
              MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTX;
1539
335
              break;
1540
1.14k
          }
1541
1.14k
      }
1542
3.23k
    }
1543
3.23k
  }
1544
1545
6.42k
  if (DoShift || IsLSL) {
1546
5.08k
    SStream_concat(O, " #%u", Log2_32(Width / 8));
1547
1548
5.08k
    if (MI->csh->detail) {
1549
5.08k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL;
1550
5.08k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.value = Log2_32(Width / 8);
1551
5.08k
    }
1552
5.08k
  }
1553
6.42k
}
1554
1555
static void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind, unsigned Width)
1556
1.36k
{
1557
1.36k
  unsigned SignExtend = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1558
1.36k
  unsigned DoShift = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
1559
1560
1.36k
  printMemExtendImpl(MI, SignExtend, DoShift, Width, SrcRegKind, O);
1561
1.36k
}
1562
1563
static void printRegWithShiftExtend(MCInst *MI, unsigned OpNum, SStream *O,
1564
            bool SignExtend, int ExtWidth,
1565
            char SrcRegKind, char Suffix)
1566
5.61k
{
1567
5.61k
  bool DoShift;
1568
1569
5.61k
  printOperand(MI, OpNum, O);
1570
1571
5.61k
  if (Suffix == 's' || Suffix == 'd')
1572
2.93k
    SStream_concat(O, ".%c", Suffix);
1573
1574
5.61k
  DoShift = ExtWidth != 8;
1575
5.61k
  if (SignExtend || DoShift || SrcRegKind == 'w') {
1576
5.05k
    SStream_concat0(O, ", ");
1577
5.05k
    printMemExtendImpl(MI, SignExtend, DoShift, ExtWidth, SrcRegKind, O);
1578
5.05k
  }
1579
5.61k
}
1580
1581
static void printCondCode(MCInst *MI, unsigned OpNum, SStream *O)
1582
707
{
1583
707
  AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1584
707
  SStream_concat0(O, getCondCodeName(CC));
1585
1586
707
  if (MI->csh->detail)
1587
707
    MI->flat_insn->detail->arm64.cc = (arm64_cc)(CC + 1);
1588
707
}
1589
1590
static void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O)
1591
14
{
1592
14
  AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1593
14
  SStream_concat0(O, getCondCodeName(getInvertedCondCode(CC)));
1594
1595
14
  if (MI->csh->detail) {
1596
14
    MI->flat_insn->detail->arm64.cc = (arm64_cc)(getInvertedCondCode(CC) + 1);
1597
14
  }
1598
14
}
1599
1600
static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale)
1601
7.57k
{
1602
7.57k
  int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1603
1604
7.57k
  printInt64Bang(O, val);
1605
1606
7.57k
  if (MI->csh->detail) {
1607
7.57k
    if (MI->csh->doing_mem) {
1608
6.12k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val;
1609
6.12k
    } else {
1610
1.44k
#ifndef CAPSTONE_DIET
1611
1.44k
      uint8_t access;
1612
1613
1.44k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1614
1.44k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1615
1.44k
      MI->ac_idx++;
1616
1.44k
#endif
1617
1.44k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1618
1.44k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val;
1619
1.44k
      MI->flat_insn->detail->arm64.op_count++;
1620
1.44k
    }
1621
7.57k
  }
1622
7.57k
}
1623
1624
static void printUImm12Offset(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale)
1625
3.19k
{
1626
3.19k
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
1627
1628
3.19k
  if (MCOperand_isImm(MO)) {
1629
3.19k
    int64_t val = Scale * MCOperand_getImm(MO);
1630
3.19k
    printInt64Bang(O, val);
1631
1632
3.19k
    if (MI->csh->detail) {
1633
3.19k
      if (MI->csh->doing_mem) {
1634
3.19k
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val;
1635
3.19k
      } else {
1636
0
#ifndef CAPSTONE_DIET
1637
0
        uint8_t access;
1638
1639
0
        access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1640
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1641
0
        MI->ac_idx++;
1642
0
#endif
1643
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1644
0
        MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)val;
1645
0
        MI->flat_insn->detail->arm64.op_count++;
1646
0
      }
1647
3.19k
    }
1648
3.19k
  }
1649
3.19k
}
1650
1651
#if 0
1652
static void printAMIndexedWB(MCInst *MI, unsigned OpNum, SStream *O, unsigned int Scale)
1653
{
1654
  MCOperand *MO = MCInst_getOperand(MI, OpNum + 1);
1655
1656
  SStream_concat(O, "[%s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName));
1657
1658
  if (MCOperand_isImm(MO)) {
1659
    int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1660
    printInt64Bang(O, val);
1661
  // } else {
1662
  //   // assert(MO1.isExpr() && "Unexpected operand type!");
1663
  //   SStream_concat0(O, ", ");
1664
  //   MO1.getExpr()->print(O, &MAI);
1665
  }
1666
1667
  SStream_concat0(O, "]");
1668
}
1669
#endif
1670
1671
// IsSVEPrefetch = false
1672
static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O, bool IsSVEPrefetch)
1673
2.14k
{
1674
2.14k
  unsigned prfop = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1675
1676
2.14k
  if (IsSVEPrefetch) {
1677
1.64k
    const SVEPRFM *PRFM = lookupSVEPRFMByEncoding(prfop);
1678
1.64k
    if (PRFM)
1679
1.40k
      SStream_concat0(O, PRFM->Name);
1680
1681
1.64k
    return;
1682
1.64k
  } else {
1683
501
    const PRFM *PRFM = lookupPRFMByEncoding(prfop);
1684
501
    if (PRFM)
1685
169
      SStream_concat0(O, PRFM->Name);
1686
1687
501
    return;
1688
501
  }
1689
1690
  // FIXME: set OpcodePub?
1691
1692
0
  printInt32Bang(O, prfop);
1693
1694
0
  if (MI->csh->detail) {
1695
0
#ifndef CAPSTONE_DIET
1696
0
    uint8_t access;
1697
0
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1698
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1699
0
    MI->ac_idx++;
1700
0
#endif
1701
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
1702
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = prfop;
1703
0
    MI->flat_insn->detail->arm64.op_count++;
1704
0
  }
1705
0
}
1706
1707
static void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O)
1708
282
{
1709
282
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1710
282
  unsigned int psbhintop = MCOperand_getImm(Op);
1711
1712
282
  const PSB *PSB = lookupPSBByEncoding(psbhintop);
1713
282
  if (PSB)
1714
282
    SStream_concat0(O, PSB->Name);
1715
0
  else
1716
0
    printUInt32Bang(O, psbhintop);
1717
282
}
1718
1719
7
static void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O) {
1720
7
  unsigned btihintop = MCOperand_getImm(MCInst_getOperand(MI, OpNum)) ^ 32;
1721
1722
7
  const BTI *BTI = lookupBTIByEncoding(btihintop);
1723
7
  if (BTI)
1724
7
  SStream_concat0(O, BTI->Name);
1725
0
  else
1726
0
  printUInt32Bang(O, btihintop);
1727
7
}
1728
1729
static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
1730
302
{
1731
302
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
1732
302
  float FPImm = MCOperand_isFPImm(MO) ? MCOperand_getFPImm(MO) : AArch64_AM_getFPImmFloat((int)MCOperand_getImm(MO));
1733
1734
  // 8 decimal places are enough to perfectly represent permitted floats.
1735
#if defined(_KERNEL_MODE)
1736
  // Issue #681: Windows kernel does not support formatting float point
1737
  SStream_concat0(O, "#<float_point_unsupported>");
1738
#else
1739
302
  SStream_concat(O, "#%.8f", FPImm);
1740
302
#endif
1741
1742
302
  if (MI->csh->detail) {
1743
302
#ifndef CAPSTONE_DIET
1744
302
    uint8_t access;
1745
1746
302
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1747
302
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1748
302
    MI->ac_idx++;
1749
302
#endif
1750
302
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP;
1751
302
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = FPImm;
1752
302
    MI->flat_insn->detail->arm64.op_count++;
1753
302
  }
1754
302
}
1755
1756
//static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1)
1757
static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride)
1758
41.4k
{
1759
82.8k
  while (Stride--) {
1760
41.4k
    if (Reg >= AArch64_Q0 && Reg <= AArch64_Q30) // AArch64_Q0 .. AArch64_Q30
1761
30.5k
      Reg += 1;
1762
10.8k
    else if (Reg == AArch64_Q31) // Vector lists can wrap around.
1763
1.74k
      Reg = AArch64_Q0;
1764
9.13k
    else if (Reg >= AArch64_Z0 && Reg <= AArch64_Z30) // AArch64_Z0 .. AArch64_Z30
1765
8.61k
      Reg += 1;
1766
520
    else if (Reg == AArch64_Z31) // Vector lists can wrap around.
1767
520
      Reg = AArch64_Z0;
1768
41.4k
  }
1769
1770
41.4k
  return Reg;
1771
41.4k
}
1772
1773
static void printGPRSeqPairsClassOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned int size)
1774
1.25k
{
1775
  // static_assert(size == 64 || size == 32,
1776
  //    "Template parameter must be either 32 or 64");
1777
1.25k
  unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
1778
1.25k
  unsigned Sube = (size == 32) ? AArch64_sube32 : AArch64_sube64;
1779
1.25k
  unsigned Subo = (size == 32) ? AArch64_subo32 : AArch64_subo64;
1780
1.25k
  unsigned Even = MCRegisterInfo_getSubReg(MI->MRI, Reg, Sube);
1781
1.25k
  unsigned Odd = MCRegisterInfo_getSubReg(MI->MRI, Reg, Subo);
1782
1783
1.25k
  SStream_concat(O, "%s, %s", getRegisterName(Even, AArch64_NoRegAltName),
1784
1.25k
      getRegisterName(Odd, AArch64_NoRegAltName));
1785
1786
1.25k
  if (MI->csh->detail) {
1787
1.25k
#ifndef CAPSTONE_DIET
1788
1.25k
    uint8_t access;
1789
1790
1.25k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1791
1.25k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1792
1.25k
    MI->ac_idx++;
1793
1.25k
#endif
1794
1795
1.25k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1796
1.25k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Even;
1797
1.25k
    MI->flat_insn->detail->arm64.op_count++;
1798
1799
1.25k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1800
1.25k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Odd;
1801
1.25k
    MI->flat_insn->detail->arm64.op_count++;
1802
1.25k
  }
1803
1.25k
}
1804
1805
static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O,
1806
    char *LayoutSuffix, MCRegisterInfo *MRI, arm64_vas vas)
1807
17.9k
{
1808
274k
#define GETREGCLASS_CONTAIN0(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), _reg)
1809
17.9k
  unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
1810
17.9k
  unsigned NumRegs = 1, FirstReg, i;
1811
1812
17.9k
  SStream_concat0(O, "{");
1813
1814
  // Work out how many registers there are in the list (if there is an actual
1815
  // list).
1816
17.9k
  if (GETREGCLASS_CONTAIN0(AArch64_DDRegClassID , Reg) ||
1817
17.9k
      GETREGCLASS_CONTAIN0(AArch64_ZPR2RegClassID, Reg) ||
1818
17.9k
      GETREGCLASS_CONTAIN0(AArch64_QQRegClassID, Reg))
1819
2.91k
    NumRegs = 2;
1820
14.9k
  else if (GETREGCLASS_CONTAIN0(AArch64_DDDRegClassID, Reg) ||
1821
14.9k
      GETREGCLASS_CONTAIN0(AArch64_ZPR3RegClassID, Reg) ||
1822
14.9k
      GETREGCLASS_CONTAIN0(AArch64_QQQRegClassID, Reg))
1823
3.73k
    NumRegs = 3;
1824
11.2k
  else if (GETREGCLASS_CONTAIN0(AArch64_DDDDRegClassID, Reg) ||
1825
11.2k
      GETREGCLASS_CONTAIN0(AArch64_ZPR4RegClassID, Reg) ||
1826
11.2k
      GETREGCLASS_CONTAIN0(AArch64_QQQQRegClassID, Reg))
1827
4.37k
    NumRegs = 4;
1828
1829
  // Now forget about the list and find out what the first register is.
1830
17.9k
  if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_dsub0)))
1831
1.91k
    Reg = FirstReg;
1832
15.9k
  else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_qsub0)))
1833
7.47k
    Reg = FirstReg;
1834
8.51k
  else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_zsub0)))
1835
1.62k
    Reg = FirstReg;
1836
1837
  // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1838
  // printing (otherwise getRegisterName fails).
1839
17.9k
  if (GETREGCLASS_CONTAIN0(AArch64_FPR64RegClassID, Reg)) {
1840
2.17k
    const MCRegisterClass *FPR128RC = MCRegisterInfo_getRegClass(MRI, AArch64_FPR128RegClassID);
1841
2.17k
    Reg = MCRegisterInfo_getMatchingSuperReg(MRI, Reg, AArch64_dsub, FPR128RC);
1842
2.17k
  }
1843
1844
59.3k
  for (i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg, 1)) {
1845
41.4k
    bool isZReg = GETREGCLASS_CONTAIN0(AArch64_ZPRRegClassID, Reg);
1846
41.4k
    if (isZReg)
1847
9.13k
      SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_NoRegAltName), LayoutSuffix);
1848
32.2k
    else
1849
32.2k
      SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_vreg), LayoutSuffix);
1850
1851
41.4k
    if (MI->csh->detail) {
1852
41.4k
#ifndef CAPSTONE_DIET
1853
41.4k
      uint8_t access;
1854
1855
41.4k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
1856
41.4k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
1857
41.4k
      MI->ac_idx++;
1858
41.4k
#endif
1859
41.4k
      unsigned regForDetail = isZReg ? Reg : AArch64_map_vregister(Reg);
1860
41.4k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
1861
41.4k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = regForDetail;
1862
41.4k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vas = vas;
1863
41.4k
      MI->flat_insn->detail->arm64.op_count++;
1864
41.4k
    }
1865
1866
41.4k
    if (i + 1 != NumRegs)
1867
23.4k
      SStream_concat0(O, ", ");
1868
41.4k
  }
1869
1870
17.9k
  SStream_concat0(O, "}");
1871
17.9k
}
1872
1873
static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigned NumLanes, char LaneKind)
1874
17.9k
{
1875
17.9k
  char Suffix[32];
1876
17.9k
  arm64_vas vas = 0;
1877
1878
17.9k
  if (NumLanes) {
1879
6.23k
    cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, LaneKind);
1880
1881
6.23k
    switch(LaneKind) {
1882
0
      default: break;
1883
1.70k
      case 'b':
1884
1.70k
        switch(NumLanes) {
1885
0
          default: break;
1886
0
          case 1:
1887
0
               vas = ARM64_VAS_1B;
1888
0
               break;
1889
0
          case 4:
1890
0
               vas = ARM64_VAS_4B;
1891
0
               break;
1892
442
          case 8:
1893
442
               vas = ARM64_VAS_8B;
1894
442
               break;
1895
1.26k
          case 16:
1896
1.26k
               vas = ARM64_VAS_16B;
1897
1.26k
               break;
1898
1.70k
        }
1899
1.70k
        break;
1900
1.70k
      case 'h':
1901
1.60k
        switch(NumLanes) {
1902
0
          default: break;
1903
0
          case 1:
1904
0
               vas = ARM64_VAS_1H;
1905
0
               break;
1906
0
          case 2:
1907
0
               vas = ARM64_VAS_2H;
1908
0
               break;
1909
618
          case 4:
1910
618
               vas = ARM64_VAS_4H;
1911
618
               break;
1912
991
          case 8:
1913
991
               vas = ARM64_VAS_8H;
1914
991
               break;
1915
1.60k
        }
1916
1.60k
        break;
1917
1.97k
      case 's':
1918
1.97k
        switch(NumLanes) {
1919
0
          default: break;
1920
0
          case 1:
1921
0
               vas = ARM64_VAS_1S;
1922
0
               break;
1923
872
          case 2:
1924
872
               vas = ARM64_VAS_2S;
1925
872
               break;
1926
1.09k
          case 4:
1927
1.09k
               vas = ARM64_VAS_4S;
1928
1.09k
               break;
1929
1.97k
        }
1930
1.97k
        break;
1931
1.97k
      case 'd':
1932
945
        switch(NumLanes) {
1933
0
          default: break;
1934
243
          case 1:
1935
243
               vas = ARM64_VAS_1D;
1936
243
               break;
1937
702
          case 2:
1938
702
               vas = ARM64_VAS_2D;
1939
702
               break;
1940
945
        }
1941
945
        break;
1942
945
      case 'q':
1943
0
        switch(NumLanes) {
1944
0
          default: break;
1945
0
          case 1:
1946
0
               vas = ARM64_VAS_1Q;
1947
0
               break;
1948
0
        }
1949
0
        break;
1950
6.23k
    }
1951
11.6k
  } else {
1952
11.6k
    cs_snprintf(Suffix, sizeof(Suffix), ".%c", LaneKind);
1953
1954
11.6k
    switch(LaneKind) {
1955
0
      default: break;
1956
2.33k
      case 'b':
1957
2.33k
           vas = ARM64_VAS_1B;
1958
2.33k
           break;
1959
3.12k
      case 'h':
1960
3.12k
           vas = ARM64_VAS_1H;
1961
3.12k
           break;
1962
2.93k
      case 's':
1963
2.93k
           vas = ARM64_VAS_1S;
1964
2.93k
           break;
1965
3.28k
      case 'd':
1966
3.28k
           vas = ARM64_VAS_1D;
1967
3.28k
           break;
1968
0
      case 'q':
1969
0
           vas = ARM64_VAS_1Q;
1970
0
           break;
1971
11.6k
    }
1972
11.6k
  }
1973
1974
17.9k
  printVectorList(MI, OpNum, O, Suffix, MI->MRI, vas);
1975
17.9k
}
1976
1977
static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O)
1978
8.75k
{
1979
8.75k
  SStream_concat0(O, "[");
1980
8.75k
  printInt32(O, (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
1981
8.75k
  SStream_concat0(O, "]");
1982
1983
8.75k
  if (MI->csh->detail) {
1984
8.75k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vector_index = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1985
8.75k
  }
1986
8.75k
}
1987
1988
static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O)
1989
5.07k
{
1990
5.07k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
1991
1992
  // If the label has already been resolved to an immediate offset (say, when
1993
  // we're running the disassembler), just print the immediate.
1994
5.07k
  if (MCOperand_isImm(Op)) {
1995
5.07k
    uint64_t imm = (MCOperand_getImm(Op) * 4) + MI->address;
1996
5.07k
    printUInt64Bang(O, imm);
1997
1998
5.07k
    if (MI->csh->detail) {
1999
5.07k
#ifndef CAPSTONE_DIET
2000
5.07k
      uint8_t access;
2001
2002
5.07k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2003
5.07k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2004
5.07k
      MI->ac_idx++;
2005
5.07k
#endif
2006
5.07k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2007
5.07k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
2008
5.07k
      MI->flat_insn->detail->arm64.op_count++;
2009
5.07k
    }
2010
5.07k
  }
2011
5.07k
}
2012
2013
static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O)
2014
1.13k
{
2015
1.13k
  MCOperand *Op = MCInst_getOperand(MI, OpNum);
2016
2017
1.13k
  if (MCOperand_isImm(Op)) {
2018
    // ADRP sign extends a 21-bit offset, shifts it left by 12
2019
    // and adds it to the value of the PC with its bottom 12 bits cleared
2020
1.13k
    uint64_t imm = (MCOperand_getImm(Op) * 0x1000) + (MI->address & ~0xfff);
2021
1.13k
    printUInt64Bang(O, imm);
2022
2023
1.13k
    if (MI->csh->detail) {
2024
1.13k
#ifndef CAPSTONE_DIET
2025
1.13k
      uint8_t access;
2026
2027
1.13k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2028
1.13k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2029
1.13k
      MI->ac_idx++;
2030
1.13k
#endif
2031
1.13k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2032
1.13k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
2033
1.13k
      MI->flat_insn->detail->arm64.op_count++;
2034
1.13k
    }
2035
1.13k
  }
2036
1.13k
}
2037
2038
static void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O)
2039
429
{
2040
429
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2041
429
  unsigned Opcode = MCInst_getOpcode(MI);
2042
429
  const char *Name = NULL;
2043
2044
429
  if (Opcode == AArch64_ISB) {
2045
10
    const ISB *ISB = lookupISBByEncoding(Val);
2046
10
    Name = ISB ? ISB->Name : NULL;
2047
419
  } else if (Opcode == AArch64_TSB) {
2048
0
    const TSB *TSB = lookupTSBByEncoding(Val);
2049
0
    Name = TSB ? TSB->Name : NULL;
2050
419
  } else {
2051
419
    const DB *DB = lookupDBByEncoding(Val);
2052
419
    Name = DB ? DB->Name : NULL;
2053
419
  }
2054
2055
429
  if (Name) {
2056
164
    SStream_concat0(O, Name);
2057
2058
164
    if (MI->csh->detail) {
2059
164
#ifndef CAPSTONE_DIET
2060
164
      uint8_t access;
2061
2062
164
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2063
164
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2064
164
      MI->ac_idx++;
2065
164
#endif
2066
164
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_BARRIER;
2067
164
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].barrier = Val;
2068
164
      MI->flat_insn->detail->arm64.op_count++;
2069
164
    }
2070
265
  } else {
2071
265
    printUInt32Bang(O, Val);
2072
2073
265
    if (MI->csh->detail) {
2074
265
#ifndef CAPSTONE_DIET
2075
265
      uint8_t access;
2076
2077
265
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2078
265
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2079
265
      MI->ac_idx++;
2080
265
#endif
2081
265
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2082
265
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
2083
265
      MI->flat_insn->detail->arm64.op_count++;
2084
265
    }
2085
265
  }
2086
429
}
2087
2088
32
static void printBarriernXSOption(MCInst *MI, unsigned OpNo, SStream *O) {
2089
32
  unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNo));
2090
  // assert(MI->getOpcode() == AArch64::DSBnXS);
2091
2092
32
  const char *Name = NULL;
2093
32
  const DBnXS *DB = lookupDBnXSByEncoding(Val);
2094
32
  Name = DB ? DB->Name : NULL;
2095
2096
32
  if (Name) {
2097
32
    SStream_concat0(O, Name);
2098
2099
32
    if (MI->csh->detail) {
2100
32
#ifndef CAPSTONE_DIET
2101
32
      uint8_t access;
2102
2103
32
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2104
32
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2105
32
      MI->ac_idx++;
2106
32
#endif
2107
32
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_BARRIER;
2108
32
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].barrier = Val;
2109
32
      MI->flat_insn->detail->arm64.op_count++;
2110
32
    }
2111
32
  }
2112
0
  else {
2113
0
    printUInt32Bang(O, Val);
2114
2115
0
    if (MI->csh->detail) {
2116
0
#ifndef CAPSTONE_DIET
2117
0
      uint8_t access;
2118
2119
0
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2120
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2121
0
      MI->ac_idx++;
2122
0
#endif
2123
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2124
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
2125
0
      MI->flat_insn->detail->arm64.op_count++;
2126
0
    }
2127
0
  }
2128
32
}
2129
2130
static void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
2131
107
{
2132
107
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2133
107
  const SysReg *Reg = lookupSysRegByEncoding(Val);
2134
2135
  // Horrible hack for the one register that has identical encodings but
2136
  // different names in MSR and MRS. Because of this, one of MRS and MSR is
2137
  // going to get the wrong entry
2138
107
  if (Val == ARM64_SYSREG_DBGDTRRX_EL0) {
2139
14
    SStream_concat0(O, "dbgdtrrx_el0");
2140
2141
14
    if (MI->csh->detail) {
2142
14
#ifndef CAPSTONE_DIET
2143
14
      uint8_t access;
2144
2145
14
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2146
14
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2147
14
      MI->ac_idx++;
2148
14
#endif
2149
2150
14
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2151
14
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val;
2152
14
      MI->flat_insn->detail->arm64.op_count++;
2153
14
    }
2154
2155
14
    return;
2156
14
  }
2157
2158
  // Another hack for a register which has an alternative name which is not an alias,
2159
  // and is not in the Armv9-A documentation.
2160
93
  if( Val == ARM64_SYSREG_VSCTLR_EL2){
2161
3
    SStream_concat0(O, "ttbr0_el2");
2162
2163
3
    if (MI->csh->detail) {
2164
3
#ifndef CAPSTONE_DIET
2165
3
      uint8_t access;
2166
2167
3
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2168
3
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2169
3
      MI->ac_idx++;
2170
3
#endif
2171
2172
3
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2173
3
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val;
2174
3
      MI->flat_insn->detail->arm64.op_count++;
2175
3
    }
2176
2177
3
    return;
2178
3
  }
2179
2180
  // if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits()))
2181
90
  if (Reg && Reg->Readable) {
2182
37
    SStream_concat0(O, Reg->Name);
2183
2184
37
    if (MI->csh->detail) {
2185
37
#ifndef CAPSTONE_DIET
2186
37
      uint8_t access;
2187
2188
37
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2189
37
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2190
37
      MI->ac_idx++;
2191
37
#endif
2192
2193
37
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2194
37
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Reg->Encoding;
2195
37
      MI->flat_insn->detail->arm64.op_count++;
2196
37
    }
2197
53
  } else {
2198
53
    char result[128];
2199
2200
53
    AArch64SysReg_genericRegisterString(Val, result);
2201
53
    SStream_concat0(O, result);
2202
2203
53
    if (MI->csh->detail) {
2204
53
#ifndef CAPSTONE_DIET
2205
53
      uint8_t access;
2206
53
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2207
53
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2208
53
      MI->ac_idx++;
2209
53
#endif
2210
53
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS;
2211
53
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val;
2212
53
      MI->flat_insn->detail->arm64.op_count++;
2213
53
    }
2214
53
  }
2215
90
}
2216
2217
static void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O)
2218
817
{
2219
817
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2220
817
  const SysReg *Reg = lookupSysRegByEncoding(Val);
2221
2222
  // Horrible hack for the one register that has identical encodings but
2223
  // different names in MSR and MRS. Because of this, one of MRS and MSR is
2224
  // going to get the wrong entry
2225
817
  if (Val == ARM64_SYSREG_DBGDTRTX_EL0) {
2226
20
    SStream_concat0(O, "dbgdtrtx_el0");
2227
2228
20
    if (MI->csh->detail) {
2229
20
#ifndef CAPSTONE_DIET
2230
20
      uint8_t access;
2231
2232
20
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2233
20
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2234
20
      MI->ac_idx++;
2235
20
#endif
2236
2237
20
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2238
20
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val;
2239
20
      MI->flat_insn->detail->arm64.op_count++;
2240
20
    }
2241
2242
20
    return;
2243
20
  }
2244
2245
  // Another hack for a register which has an alternative name which is not an alias,
2246
  // and is not in the Armv9-A documentation.
2247
797
  if( Val == ARM64_SYSREG_VSCTLR_EL2){
2248
5
    SStream_concat0(O, "ttbr0_el2");
2249
2250
5
    if (MI->csh->detail) {
2251
5
#ifndef CAPSTONE_DIET
2252
5
      uint8_t access;
2253
2254
5
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2255
5
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2256
5
      MI->ac_idx++;
2257
5
#endif
2258
2259
5
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2260
5
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val;
2261
5
      MI->flat_insn->detail->arm64.op_count++;
2262
5
    }
2263
2264
5
    return;
2265
5
  }
2266
2267
  // if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits()))
2268
792
  if (Reg && Reg->Writeable) {
2269
35
    SStream_concat0(O, Reg->Name);
2270
2271
35
    if (MI->csh->detail) {
2272
35
#ifndef CAPSTONE_DIET
2273
35
      uint8_t access;
2274
2275
35
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2276
35
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2277
35
      MI->ac_idx++;
2278
35
#endif
2279
2280
35
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
2281
35
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Reg->Encoding;
2282
35
      MI->flat_insn->detail->arm64.op_count++;
2283
35
    }
2284
757
  } else {
2285
757
    char result[128];
2286
2287
757
    AArch64SysReg_genericRegisterString(Val, result);
2288
757
    SStream_concat0(O, result);
2289
2290
757
    if (MI->csh->detail) {
2291
757
#ifndef CAPSTONE_DIET
2292
757
      uint8_t access;
2293
757
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2294
757
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2295
757
      MI->ac_idx++;
2296
757
#endif
2297
757
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS;
2298
757
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val;
2299
757
      MI->flat_insn->detail->arm64.op_count++;
2300
757
    }
2301
757
  }
2302
792
}
2303
2304
static void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O)
2305
30
{
2306
30
  unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2307
2308
30
  const PState *PState = lookupPStateByEncoding(Val);
2309
2310
30
  if (PState) {
2311
30
    SStream_concat0(O, PState->Name);
2312
2313
30
    if (MI->csh->detail) {
2314
30
#ifndef CAPSTONE_DIET
2315
30
      uint8_t access;
2316
30
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2317
30
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2318
30
      MI->ac_idx++;
2319
30
#endif
2320
30
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_PSTATE;
2321
30
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].pstate = Val;
2322
30
      MI->flat_insn->detail->arm64.op_count++;
2323
30
    }
2324
30
  } else {
2325
0
    printUInt32Bang(O, Val);
2326
2327
0
    if (MI->csh->detail) {
2328
0
#ifndef CAPSTONE_DIET
2329
0
      unsigned char access;
2330
2331
0
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2332
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2333
0
      MI->ac_idx++;
2334
0
#endif
2335
2336
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2337
0
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
2338
0
      MI->flat_insn->detail->arm64.op_count++;
2339
0
    }
2340
0
  }
2341
30
}
2342
2343
static void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O)
2344
154
{
2345
154
  uint8_t RawVal = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2346
154
  uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal);
2347
2348
154
  SStream_concat(O, "#%#016llx", Val);
2349
2350
154
  if (MI->csh->detail) {
2351
154
#ifndef CAPSTONE_DIET
2352
154
    unsigned char access;
2353
2354
154
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2355
154
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2356
154
    MI->ac_idx++;
2357
154
#endif
2358
154
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
2359
154
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
2360
154
    MI->flat_insn->detail->arm64.op_count++;
2361
154
  }
2362
154
}
2363
2364
static void printComplexRotationOp(MCInst *MI, unsigned OpNum, SStream *O, int64_t Angle, int64_t Remainder)
2365
655
{
2366
655
  unsigned int Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2367
655
  printInt64Bang(O, (Val * Angle) + Remainder);
2368
655
  op_addImm(MI, (Val * Angle) + Remainder);
2369
655
}
2370
2371
static void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O)
2372
0
{
2373
0
  MCOperand *MO = MCInst_getOperand(MI, OpNum);
2374
    // assert(MCOperand_isImm(MO) && "Unexpected operand type!");
2375
0
    unsigned svcrop = MCOperand_getImm(MO);
2376
0
  const SVCR *svcr = lookupSVCRByEncoding(svcrop);
2377
    // assert(svcr && "Unexpected SVCR operand!");
2378
0
  SStream_concat0(O, svcr->Name);
2379
2380
0
  if (MI->csh->detail) {
2381
0
#ifndef CAPSTONE_DIET
2382
0
    uint8_t access;
2383
2384
0
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2385
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2386
0
    MI->ac_idx++;
2387
0
#endif
2388
2389
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SVCR;
2390
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = (unsigned)ARM64_SYSREG_SVCR;
2391
0
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].svcr = svcr->Encoding;
2392
0
    MI->flat_insn->detail->arm64.op_count++;
2393
0
  }
2394
0
}
2395
2396
static void printMatrix(MCInst *MI, unsigned OpNum, SStream *O, int EltSize)
2397
17
{
2398
17
  MCOperand *RegOp = MCInst_getOperand(MI, OpNum);
2399
    // assert(MCOperand_isReg(RegOp) && "Unexpected operand type!");
2400
17
  unsigned Reg = MCOperand_getReg(RegOp);
2401
2402
17
  SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
2403
17
  const char *sizeStr = "";
2404
17
    switch (EltSize) {
2405
17
    case 0:
2406
17
    sizeStr = "";
2407
17
      break;
2408
0
    case 8:
2409
0
      sizeStr = ".b";
2410
0
      break;
2411
0
    case 16:
2412
0
      sizeStr = ".h";
2413
0
      break;
2414
0
    case 32:
2415
0
      sizeStr = ".s";
2416
0
      break;
2417
0
    case 64:
2418
0
      sizeStr = ".d";
2419
0
      break;
2420
0
    case 128:
2421
0
      sizeStr = ".q";
2422
0
      break;
2423
0
    default:
2424
0
    break;
2425
    //   llvm_unreachable("Unsupported element size");
2426
17
    }
2427
17
  SStream_concat0(O, sizeStr);
2428
2429
17
  if (MI->csh->detail) {
2430
17
#ifndef CAPSTONE_DIET
2431
17
    uint8_t access;
2432
2433
17
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2434
17
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2435
17
    MI->ac_idx++;
2436
17
#endif
2437
2438
17
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2439
17
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
2440
17
    MI->flat_insn->detail->arm64.op_count++;
2441
17
  }
2442
17
}
2443
2444
static void printMatrixIndex(MCInst *MI, unsigned OpNum, SStream *O)
2445
2.88k
{
2446
2.88k
  int64_t imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2447
2.88k
  printInt64(O, imm);
2448
2449
2.88k
  if (MI->csh->detail) {
2450
2.88k
    if (MI->csh->doing_SME_Index) {
2451
      // Access op_count-1 as We want to add info to previous operand, not create a new one
2452
2.88k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count-1].sme_index.disp = imm;
2453
2.88k
    }
2454
2.88k
  }
2455
2.88k
}
2456
2457
static void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O)
2458
618
{
2459
618
  MCOperand *RegOp = MCInst_getOperand(MI, OpNum);
2460
    // assert(MCOperand_isReg(RegOp) && "Unexpected operand type!");
2461
618
  unsigned Reg = MCOperand_getReg(RegOp);
2462
618
    SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
2463
2464
618
  if (MI->csh->detail) {
2465
618
#ifndef CAPSTONE_DIET
2466
618
    uint8_t access;
2467
2468
618
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2469
618
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2470
618
    MI->ac_idx++;
2471
618
#endif
2472
2473
618
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2474
618
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
2475
618
    MI->flat_insn->detail->arm64.op_count++;
2476
618
  }
2477
618
}
2478
2479
static void printMatrixTileVector(MCInst *MI, unsigned OpNum, SStream *O, bool IsVertical)
2480
2.78k
{
2481
2.78k
  MCOperand *RegOp = MCInst_getOperand(MI, OpNum);
2482
    // assert(MCOperand_isReg(RegOp) && "Unexpected operand type!");
2483
2.78k
  unsigned Reg = MCOperand_getReg(RegOp);
2484
2.78k
#ifndef CAPSTONE_DIET
2485
2.78k
  const char *RegName = getRegisterName(Reg, AArch64_NoRegAltName);
2486
2487
2.78k
  const size_t strLn = strlen(RegName);
2488
  // +2 for extra chars, + 1 for null char \0
2489
2.78k
  char *RegNameNew = cs_mem_malloc(sizeof(char) * (strLn + 2 + 1));
2490
2.78k
  int index = 0, i;
2491
22.3k
  for (i = 0; i < (strLn + 2); i++){
2492
19.5k
    if(RegName[i] != '.'){
2493
16.7k
      RegNameNew[index] = RegName[i];
2494
16.7k
      index++;
2495
16.7k
    }
2496
2.78k
    else{
2497
2.78k
      RegNameNew[index] = IsVertical ? 'v' : 'h';
2498
2.78k
      RegNameNew[index + 1] = '.';
2499
2.78k
      index += 2;
2500
2.78k
    }
2501
19.5k
  }
2502
2.78k
  SStream_concat0(O, RegNameNew);
2503
2.78k
#endif
2504
2505
2.78k
  if (MI->csh->detail) {
2506
2.78k
#ifndef CAPSTONE_DIET
2507
2.78k
    uint8_t access;
2508
2509
2.78k
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2510
2.78k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2511
2.78k
    MI->ac_idx++;
2512
2.78k
#endif
2513
2514
2.78k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2515
2.78k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
2516
2.78k
    MI->flat_insn->detail->arm64.op_count++;
2517
2.78k
  }
2518
2.78k
#ifndef CAPSTONE_DIET
2519
2.78k
  cs_mem_free(RegNameNew);
2520
2.78k
#endif
2521
2.78k
}
2522
2523
static const unsigned MatrixZADRegisterTable[] = {
2524
  AArch64_ZAD0, AArch64_ZAD1, AArch64_ZAD2, AArch64_ZAD3,
2525
  AArch64_ZAD4, AArch64_ZAD5, AArch64_ZAD6, AArch64_ZAD7
2526
};
2527
2528
168
static void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O){
2529
168
  unsigned MaxRegs = 8;
2530
168
  unsigned RegMask = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2531
2532
168
  unsigned NumRegs = 0, I;
2533
1.51k
  for (I = 0; I < MaxRegs; ++I)
2534
1.34k
    if ((RegMask & (1 << I)) != 0)
2535
408
      ++NumRegs;
2536
2537
168
  SStream_concat0(O, "{");
2538
168
  unsigned Printed = 0, J;
2539
1.51k
  for (J = 0; J < MaxRegs; ++J) {
2540
1.34k
    unsigned Reg = RegMask & (1 << J);
2541
1.34k
    if (Reg == 0)
2542
936
      continue;
2543
408
    SStream_concat0(O, getRegisterName(MatrixZADRegisterTable[J], AArch64_NoRegAltName));
2544
2545
408
    if (MI->csh->detail) {
2546
408
#ifndef CAPSTONE_DIET
2547
408
      uint8_t access;
2548
2549
408
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2550
408
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2551
408
      MI->ac_idx++;
2552
408
#endif
2553
2554
408
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2555
408
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MatrixZADRegisterTable[J];
2556
408
      MI->flat_insn->detail->arm64.op_count++;
2557
408
    }
2558
2559
408
    if (Printed + 1 != NumRegs)
2560
240
      SStream_concat0(O, ", ");
2561
408
    ++Printed;
2562
408
  }
2563
168
  SStream_concat0(O, "}");
2564
168
}
2565
2566
static void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O)
2567
2.19k
{
2568
2.19k
  unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2569
2570
2.19k
  const SVEPREDPAT *Pat = lookupSVEPREDPATByEncoding(Val);
2571
2.19k
  if (Pat)
2572
1.97k
    SStream_concat0(O, Pat->Name);
2573
220
  else
2574
220
    printUInt32Bang(O, Val);
2575
2.19k
}
2576
2577
// default suffix = 0
2578
static void printSVERegOp(MCInst *MI, unsigned OpNum, SStream *O, char suffix)
2579
40.0k
{
2580
40.0k
  unsigned int Reg;
2581
2582
#if 0
2583
  switch (suffix) {
2584
    case 0:
2585
    case 'b':
2586
    case 'h':
2587
    case 's':
2588
    case 'd':
2589
    case 'q':
2590
      break;
2591
    default:
2592
      // llvm_unreachable("Invalid kind specifier.");
2593
  }
2594
#endif
2595
2596
40.0k
  Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2597
2598
40.0k
  if (MI->csh->detail) {
2599
40.0k
#ifndef CAPSTONE_DIET
2600
40.0k
      uint8_t access;
2601
2602
40.0k
      access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2603
40.0k
      MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2604
40.0k
      MI->ac_idx++;
2605
40.0k
#endif
2606
40.0k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2607
40.0k
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
2608
40.0k
    MI->flat_insn->detail->arm64.op_count++;
2609
40.0k
  }
2610
2611
40.0k
  SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
2612
2613
40.0k
  if (suffix != '\0')
2614
24.0k
    SStream_concat(O, ".%c", suffix);
2615
40.0k
}
2616
2617
static void printImmSVE16(int16_t Val, SStream *O)
2618
246
{
2619
246
  printUInt32Bang(O, Val);
2620
246
}
2621
2622
static void printImmSVE32(int32_t Val, SStream *O)
2623
445
{
2624
445
  printUInt32Bang(O, Val);
2625
445
}
2626
2627
static void printImmSVE64(int64_t Val, SStream *O)
2628
335
{
2629
335
  printUInt64Bang(O, Val);
2630
335
}
2631
2632
static void printImm8OptLsl32(MCInst *MI, unsigned OpNum, SStream *O)
2633
487
{
2634
487
  unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2635
487
  unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
2636
487
  uint32_t Val;
2637
2638
  // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
2639
  //  "Unexepected shift type!");
2640
2641
  // #0 lsl #8 is never pretty printed
2642
487
  if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) {
2643
42
    printUInt32Bang(O, UnscaledVal);
2644
42
    printShifter(MI, OpNum + 1, O);
2645
42
    return;
2646
42
  }
2647
2648
445
  Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift));
2649
445
  printImmSVE32(Val, O);
2650
445
}
2651
2652
static void printImm8OptLsl64(MCInst *MI, unsigned OpNum, SStream *O)
2653
193
{
2654
193
  unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2655
193
  unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
2656
193
  uint64_t Val;
2657
2658
  // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
2659
  //  "Unexepected shift type!");
2660
2661
  // #0 lsl #8 is never pretty printed
2662
193
  if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) {
2663
5
    printUInt32Bang(O, UnscaledVal);
2664
5
    printShifter(MI, OpNum + 1, O);
2665
5
    return;
2666
5
  }
2667
2668
188
  Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift));
2669
188
  printImmSVE64(Val, O);
2670
188
}
2671
2672
static void printSVELogicalImm16(MCInst *MI, unsigned OpNum, SStream *O)
2673
243
{
2674
243
  uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2675
243
  uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64);
2676
2677
  // Prefer the default format for 16bit values, hex otherwise.
2678
243
  printImmSVE16(PrintVal, O);
2679
243
}
2680
2681
static void printSVELogicalImm32(MCInst *MI, unsigned OpNum, SStream *O)
2682
196
{
2683
196
  uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2684
196
  uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64);
2685
2686
  // Prefer the default format for 16bit values, hex otherwise.
2687
196
  if ((uint16_t)PrintVal == (uint32_t)PrintVal)
2688
3
    printImmSVE16(PrintVal, O);
2689
193
  else
2690
193
    printUInt64Bang(O, PrintVal);
2691
196
}
2692
2693
static void printSVELogicalImm64(MCInst *MI, unsigned OpNum, SStream *O)
2694
147
{
2695
147
  uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2696
147
  uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64);
2697
2698
147
  printImmSVE64(PrintVal, O);
2699
147
}
2700
2701
static void printZPRasFPR(MCInst *MI, unsigned OpNum, SStream *O, int Width)
2702
466
{
2703
466
  unsigned int Base, Reg;
2704
2705
466
  switch (Width) {
2706
0
    default: // llvm_unreachable("Unsupported width");
2707
44
    case 8:   Base = AArch64_B0; break;
2708
144
    case 16:  Base = AArch64_H0; break;
2709
75
    case 32:  Base = AArch64_S0; break;
2710
196
    case 64:  Base = AArch64_D0; break;
2711
7
    case 128: Base = AArch64_Q0; break;
2712
466
  }
2713
2714
466
  Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) - AArch64_Z0 + Base;
2715
2716
466
  SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
2717
2718
466
  if (MI->csh->detail) {
2719
466
#ifndef CAPSTONE_DIET
2720
466
    uint8_t access;
2721
2722
466
    access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
2723
466
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
2724
466
    MI->ac_idx++;
2725
466
#endif
2726
466
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
2727
466
    MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
2728
466
    MI->flat_insn->detail->arm64.op_count++;
2729
466
  }
2730
466
}
2731
2732
static void printExactFPImm(MCInst *MI, unsigned OpNum, SStream *O, unsigned ImmIs0, unsigned ImmIs1)
2733
152
{
2734
152
  const ExactFPImm *Imm0Desc = lookupExactFPImmByEnum(ImmIs0);
2735
152
  const ExactFPImm *Imm1Desc = lookupExactFPImmByEnum(ImmIs1);
2736
152
  unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2737
2738
152
  SStream_concat0(O, Val ? Imm1Desc->Repr : Imm0Desc->Repr);
2739
152
}
2740
2741
static void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O)
2742
1.99k
{
2743
1.99k
  unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2744
2745
1.99k
  SStream_concat0(O, getRegisterName(getWRegFromXReg(Reg), AArch64_NoRegAltName));
2746
1.99k
}
2747
2748
static void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O) 
2749
39
{
2750
39
    unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2751
2752
39
    SStream_concat0(O, getRegisterName(MCRegisterInfo_getSubReg(MI->MRI, Reg, AArch64_x8sub_0), AArch64_NoRegAltName));
2753
39
}
2754
2755
#define PRINT_ALIAS_INSTR
2756
#include "AArch64GenAsmWriter.inc"
2757
#include "AArch64GenRegisterName.inc"
2758
2759
void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst *mci)
2760
90.4k
{
2761
90.4k
  if (((cs_struct *)handle)->detail != CS_OPT_ON)
2762
0
    return;
2763
2764
90.4k
  if (mci->csh->detail) {
2765
90.4k
    unsigned opcode = MCInst_getOpcode(mci);
2766
2767
90.4k
    switch (opcode) {
2768
75.3k
      default:
2769
75.3k
        break;
2770
75.3k
      case AArch64_LD1Fourv16b_POST:
2771
182
      case AArch64_LD1Fourv1d_POST:
2772
199
      case AArch64_LD1Fourv2d_POST:
2773
269
      case AArch64_LD1Fourv2s_POST:
2774
276
      case AArch64_LD1Fourv4h_POST:
2775
280
      case AArch64_LD1Fourv4s_POST:
2776
290
      case AArch64_LD1Fourv8b_POST:
2777
305
      case AArch64_LD1Fourv8h_POST:
2778
306
      case AArch64_LD1Onev16b_POST:
2779
308
      case AArch64_LD1Onev1d_POST:
2780
599
      case AArch64_LD1Onev2d_POST:
2781
625
      case AArch64_LD1Onev2s_POST:
2782
632
      case AArch64_LD1Onev4h_POST:
2783
709
      case AArch64_LD1Onev4s_POST:
2784
719
      case AArch64_LD1Onev8b_POST:
2785
998
      case AArch64_LD1Onev8h_POST:
2786
1.06k
      case AArch64_LD1Rv16b_POST:
2787
1.07k
      case AArch64_LD1Rv1d_POST:
2788
1.07k
      case AArch64_LD1Rv2d_POST:
2789
1.13k
      case AArch64_LD1Rv2s_POST:
2790
1.14k
      case AArch64_LD1Rv4h_POST:
2791
1.20k
      case AArch64_LD1Rv4s_POST:
2792
1.21k
      case AArch64_LD1Rv8b_POST:
2793
1.22k
      case AArch64_LD1Rv8h_POST:
2794
1.27k
      case AArch64_LD1Threev16b_POST:
2795
1.27k
      case AArch64_LD1Threev1d_POST:
2796
1.31k
      case AArch64_LD1Threev2d_POST:
2797
1.77k
      case AArch64_LD1Threev2s_POST:
2798
1.84k
      case AArch64_LD1Threev4h_POST:
2799
1.87k
      case AArch64_LD1Threev4s_POST:
2800
1.91k
      case AArch64_LD1Threev8b_POST:
2801
2.21k
      case AArch64_LD1Threev8h_POST:
2802
2.25k
      case AArch64_LD1Twov16b_POST:
2803
2.26k
      case AArch64_LD1Twov1d_POST:
2804
2.29k
      case AArch64_LD1Twov2d_POST:
2805
2.33k
      case AArch64_LD1Twov2s_POST:
2806
2.33k
      case AArch64_LD1Twov4h_POST:
2807
2.34k
      case AArch64_LD1Twov4s_POST:
2808
2.36k
      case AArch64_LD1Twov8b_POST:
2809
2.36k
      case AArch64_LD1Twov8h_POST:
2810
2.41k
      case AArch64_LD1i16_POST:
2811
2.64k
      case AArch64_LD1i32_POST:
2812
2.65k
      case AArch64_LD1i64_POST:
2813
2.73k
      case AArch64_LD1i8_POST:
2814
2.76k
      case AArch64_LD2Rv16b_POST:
2815
2.77k
      case AArch64_LD2Rv1d_POST:
2816
2.77k
      case AArch64_LD2Rv2d_POST:
2817
2.77k
      case AArch64_LD2Rv2s_POST:
2818
2.81k
      case AArch64_LD2Rv4h_POST:
2819
2.82k
      case AArch64_LD2Rv4s_POST:
2820
2.86k
      case AArch64_LD2Rv8b_POST:
2821
2.88k
      case AArch64_LD2Rv8h_POST:
2822
2.89k
      case AArch64_LD2Twov16b_POST:
2823
2.89k
      case AArch64_LD2Twov2d_POST:
2824
2.90k
      case AArch64_LD2Twov2s_POST:
2825
2.91k
      case AArch64_LD2Twov4h_POST:
2826
2.92k
      case AArch64_LD2Twov4s_POST:
2827
2.92k
      case AArch64_LD2Twov8b_POST:
2828
2.95k
      case AArch64_LD2Twov8h_POST:
2829
3.06k
      case AArch64_LD2i16_POST:
2830
3.12k
      case AArch64_LD2i32_POST:
2831
3.13k
      case AArch64_LD2i64_POST:
2832
3.18k
      case AArch64_LD2i8_POST:
2833
3.20k
      case AArch64_LD3Rv16b_POST:
2834
3.25k
      case AArch64_LD3Rv1d_POST:
2835
3.26k
      case AArch64_LD3Rv2d_POST:
2836
3.28k
      case AArch64_LD3Rv2s_POST:
2837
3.29k
      case AArch64_LD3Rv4h_POST:
2838
3.32k
      case AArch64_LD3Rv4s_POST:
2839
3.33k
      case AArch64_LD3Rv8b_POST:
2840
3.37k
      case AArch64_LD3Rv8h_POST:
2841
3.38k
      case AArch64_LD3Threev16b_POST:
2842
3.42k
      case AArch64_LD3Threev2d_POST:
2843
3.43k
      case AArch64_LD3Threev2s_POST:
2844
3.44k
      case AArch64_LD3Threev4h_POST:
2845
3.44k
      case AArch64_LD3Threev4s_POST:
2846
3.46k
      case AArch64_LD3Threev8b_POST:
2847
3.46k
      case AArch64_LD3Threev8h_POST:
2848
3.67k
      case AArch64_LD3i16_POST:
2849
3.82k
      case AArch64_LD3i32_POST:
2850
3.89k
      case AArch64_LD3i64_POST:
2851
4.34k
      case AArch64_LD3i8_POST:
2852
4.39k
      case AArch64_LD4Fourv16b_POST:
2853
4.40k
      case AArch64_LD4Fourv2d_POST:
2854
4.43k
      case AArch64_LD4Fourv2s_POST:
2855
4.43k
      case AArch64_LD4Fourv4h_POST:
2856
4.44k
      case AArch64_LD4Fourv4s_POST:
2857
4.49k
      case AArch64_LD4Fourv8b_POST:
2858
4.50k
      case AArch64_LD4Fourv8h_POST:
2859
4.52k
      case AArch64_LD4Rv16b_POST:
2860
4.57k
      case AArch64_LD4Rv1d_POST:
2861
4.58k
      case AArch64_LD4Rv2d_POST:
2862
4.58k
      case AArch64_LD4Rv2s_POST:
2863
4.61k
      case AArch64_LD4Rv4h_POST:
2864
4.61k
      case AArch64_LD4Rv4s_POST:
2865
4.62k
      case AArch64_LD4Rv8b_POST:
2866
4.66k
      case AArch64_LD4Rv8h_POST:
2867
4.76k
      case AArch64_LD4i16_POST:
2868
4.86k
      case AArch64_LD4i32_POST:
2869
4.89k
      case AArch64_LD4i64_POST:
2870
5.01k
      case AArch64_LD4i8_POST:
2871
5.03k
      case AArch64_LDRBBpost:
2872
5.13k
      case AArch64_LDRBpost:
2873
5.14k
      case AArch64_LDRDpost:
2874
5.20k
      case AArch64_LDRHHpost:
2875
5.50k
      case AArch64_LDRHpost:
2876
5.50k
      case AArch64_LDRQpost:
2877
5.62k
      case AArch64_LDPDpost:
2878
5.78k
      case AArch64_LDPQpost:
2879
5.80k
      case AArch64_LDPSWpost:
2880
5.87k
      case AArch64_LDPSpost:
2881
6.14k
      case AArch64_LDPWpost:
2882
6.17k
      case AArch64_LDPXpost:
2883
6.21k
      case AArch64_ST1Fourv16b_POST:
2884
6.23k
      case AArch64_ST1Fourv1d_POST:
2885
6.25k
      case AArch64_ST1Fourv2d_POST:
2886
6.25k
      case AArch64_ST1Fourv2s_POST:
2887
6.26k
      case AArch64_ST1Fourv4h_POST:
2888
6.71k
      case AArch64_ST1Fourv4s_POST:
2889
6.71k
      case AArch64_ST1Fourv8b_POST:
2890
6.72k
      case AArch64_ST1Fourv8h_POST:
2891
6.74k
      case AArch64_ST1Onev16b_POST:
2892
6.75k
      case AArch64_ST1Onev1d_POST:
2893
6.75k
      case AArch64_ST1Onev2d_POST:
2894
6.76k
      case AArch64_ST1Onev2s_POST:
2895
6.76k
      case AArch64_ST1Onev4h_POST:
2896
6.80k
      case AArch64_ST1Onev4s_POST:
2897
6.84k
      case AArch64_ST1Onev8b_POST:
2898
6.84k
      case AArch64_ST1Onev8h_POST:
2899
6.85k
      case AArch64_ST1Threev16b_POST:
2900
6.87k
      case AArch64_ST1Threev1d_POST:
2901
6.88k
      case AArch64_ST1Threev2d_POST:
2902
6.89k
      case AArch64_ST1Threev2s_POST:
2903
6.90k
      case AArch64_ST1Threev4h_POST:
2904
6.91k
      case AArch64_ST1Threev4s_POST:
2905
6.95k
      case AArch64_ST1Threev8b_POST:
2906
6.98k
      case AArch64_ST1Threev8h_POST:
2907
7.02k
      case AArch64_ST1Twov16b_POST:
2908
7.03k
      case AArch64_ST1Twov1d_POST:
2909
7.05k
      case AArch64_ST1Twov2d_POST:
2910
7.08k
      case AArch64_ST1Twov2s_POST:
2911
7.11k
      case AArch64_ST1Twov4h_POST:
2912
7.33k
      case AArch64_ST1Twov4s_POST:
2913
7.34k
      case AArch64_ST1Twov8b_POST:
2914
7.36k
      case AArch64_ST1Twov8h_POST:
2915
7.43k
      case AArch64_ST1i16_POST:
2916
7.90k
      case AArch64_ST1i32_POST:
2917
8.07k
      case AArch64_ST1i64_POST:
2918
8.13k
      case AArch64_ST1i8_POST:
2919
8.19k
      case AArch64_ST2GPostIndex:
2920
8.20k
      case AArch64_ST2Twov16b_POST:
2921
8.24k
      case AArch64_ST2Twov2d_POST:
2922
8.25k
      case AArch64_ST2Twov2s_POST:
2923
8.26k
      case AArch64_ST2Twov4h_POST:
2924
8.30k
      case AArch64_ST2Twov4s_POST:
2925
8.31k
      case AArch64_ST2Twov8b_POST:
2926
8.32k
      case AArch64_ST2Twov8h_POST:
2927
8.45k
      case AArch64_ST2i16_POST:
2928
8.52k
      case AArch64_ST2i32_POST:
2929
8.70k
      case AArch64_ST2i64_POST:
2930
8.73k
      case AArch64_ST2i8_POST:
2931
8.74k
      case AArch64_ST3Threev16b_POST:
2932
8.77k
      case AArch64_ST3Threev2d_POST:
2933
8.78k
      case AArch64_ST3Threev2s_POST:
2934
8.80k
      case AArch64_ST3Threev4h_POST:
2935
8.82k
      case AArch64_ST3Threev4s_POST:
2936
8.84k
      case AArch64_ST3Threev8b_POST:
2937
8.87k
      case AArch64_ST3Threev8h_POST:
2938
8.96k
      case AArch64_ST3i16_POST:
2939
9.01k
      case AArch64_ST3i32_POST:
2940
9.17k
      case AArch64_ST3i64_POST:
2941
9.21k
      case AArch64_ST3i8_POST:
2942
9.23k
      case AArch64_ST4Fourv16b_POST:
2943
9.25k
      case AArch64_ST4Fourv2d_POST:
2944
9.28k
      case AArch64_ST4Fourv2s_POST:
2945
9.31k
      case AArch64_ST4Fourv4h_POST:
2946
9.33k
      case AArch64_ST4Fourv4s_POST:
2947
9.39k
      case AArch64_ST4Fourv8b_POST:
2948
9.47k
      case AArch64_ST4Fourv8h_POST:
2949
9.70k
      case AArch64_ST4i16_POST:
2950
9.74k
      case AArch64_ST4i32_POST:
2951
9.75k
      case AArch64_ST4i64_POST:
2952
9.92k
      case AArch64_ST4i8_POST:
2953
9.98k
      case AArch64_STPDpost:
2954
10.1k
      case AArch64_STPQpost:
2955
10.2k
      case AArch64_STPSpost:
2956
10.3k
      case AArch64_STPWpost:
2957
10.4k
      case AArch64_STPXpost:
2958
10.4k
      case AArch64_STRBBpost:
2959
10.6k
      case AArch64_STRBpost:
2960
10.6k
      case AArch64_STRDpost:
2961
10.7k
      case AArch64_STRHHpost:
2962
10.7k
      case AArch64_STRHpost:
2963
10.7k
      case AArch64_STRQpost:
2964
10.7k
      case AArch64_STRSpost:
2965
10.8k
      case AArch64_STRWpost:
2966
10.9k
      case AArch64_STRXpost:
2967
10.9k
      case AArch64_STZ2GPostIndex:
2968
10.9k
      case AArch64_STZGPostIndex:
2969
11.1k
      case AArch64_STGPostIndex:
2970
11.1k
      case AArch64_STGPpost:
2971
11.1k
      case AArch64_LDRSBWpost:
2972
11.2k
      case AArch64_LDRSBXpost:
2973
11.2k
      case AArch64_LDRSHWpost:
2974
11.3k
      case AArch64_LDRSHXpost:
2975
11.4k
      case AArch64_LDRSWpost:
2976
11.5k
      case AArch64_LDRSpost:
2977
11.6k
      case AArch64_LDRWpost:
2978
11.6k
      case AArch64_LDRXpost:
2979
11.6k
        flat_insn->detail->arm64.writeback = true;
2980
11.6k
          flat_insn->detail->arm64.post_index = true;
2981
11.6k
        break;
2982
126
      case AArch64_LDRAAwriteback:
2983
335
      case AArch64_LDRABwriteback:
2984
588
      case AArch64_ST2GPreIndex:
2985
678
      case AArch64_LDPDpre:
2986
729
      case AArch64_LDPQpre:
2987
788
      case AArch64_LDPSWpre:
2988
875
      case AArch64_LDPSpre:
2989
998
      case AArch64_LDPWpre:
2990
1.14k
      case AArch64_LDPXpre:
2991
1.15k
      case AArch64_LDRBBpre:
2992
1.20k
      case AArch64_LDRBpre:
2993
1.35k
      case AArch64_LDRDpre:
2994
1.39k
      case AArch64_LDRHHpre:
2995
1.41k
      case AArch64_LDRHpre:
2996
1.42k
      case AArch64_LDRQpre:
2997
1.42k
      case AArch64_LDRSBWpre:
2998
1.45k
      case AArch64_LDRSBXpre:
2999
1.83k
      case AArch64_LDRSHWpre:
3000
1.87k
      case AArch64_LDRSHXpre:
3001
1.91k
      case AArch64_LDRSWpre:
3002
1.93k
      case AArch64_LDRSpre:
3003
2.13k
      case AArch64_LDRWpre:
3004
2.18k
      case AArch64_LDRXpre:
3005
2.23k
      case AArch64_STGPreIndex:
3006
2.33k
      case AArch64_STPDpre:
3007
2.70k
      case AArch64_STPQpre:
3008
2.74k
      case AArch64_STPSpre:
3009
2.79k
      case AArch64_STPWpre:
3010
2.93k
      case AArch64_STPXpre:
3011
2.96k
      case AArch64_STRBBpre:
3012
3.05k
      case AArch64_STRBpre:
3013
3.05k
      case AArch64_STRDpre:
3014
3.10k
      case AArch64_STRHHpre:
3015
3.17k
      case AArch64_STRHpre:
3016
3.18k
      case AArch64_STRQpre:
3017
3.19k
      case AArch64_STRSpre:
3018
3.21k
      case AArch64_STRWpre:
3019
3.33k
      case AArch64_STRXpre:
3020
3.35k
      case AArch64_STZ2GPreIndex:
3021
3.46k
      case AArch64_STZGPreIndex:
3022
3.46k
      case AArch64_STGPpre:
3023
3.46k
        flat_insn->detail->arm64.writeback = true;
3024
3.46k
        break;
3025
90.4k
    }
3026
90.4k
  }
3027
90.4k
}
3028
3029
#endif