Coverage Report

Created: 2023-09-25 06:24

/src/capstonev5/arch/RISCV/RISCVGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Assembly Writer Source Fragment                                            *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
#include <assert.h>
15
16
17
/// printInstruction - This method is automatically generated by tablegen
18
/// from the instruction set description.
19
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
20
15.6k
{
21
15.6k
#ifndef CAPSTONE_DIET
22
15.6k
  static const char AsmStrs[] = {
23
15.6k
  /* 0 */ 'l', 'l', 'a', 9, 0,
24
15.6k
  /* 5 */ 's', 'f', 'e', 'n', 'c', 'e', '.', 'v', 'm', 'a', 9, 0,
25
15.6k
  /* 17 */ 's', 'r', 'a', 9, 0,
26
15.6k
  /* 22 */ 'l', 'b', 9, 0,
27
15.6k
  /* 26 */ 's', 'b', 9, 0,
28
15.6k
  /* 30 */ 'c', '.', 's', 'u', 'b', 9, 0,
29
15.6k
  /* 37 */ 'a', 'u', 'i', 'p', 'c', 9, 0,
30
15.6k
  /* 44 */ 'c', 's', 'r', 'r', 'c', 9, 0,
31
15.6k
  /* 51 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0,
32
15.6k
  /* 59 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0,
33
15.6k
  /* 68 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0,
34
15.6k
  /* 78 */ 's', 'c', '.', 'd', 9, 0,
35
15.6k
  /* 84 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0,
36
15.6k
  /* 92 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0,
37
15.6k
  /* 101 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0,
38
15.6k
  /* 111 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', 9, 0,
39
15.6k
  /* 121 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', 9, 0,
40
15.6k
  /* 131 */ 'f', 'l', 'e', '.', 'd', 9, 0,
41
15.6k
  /* 138 */ 'f', 's', 'g', 'n', 'j', '.', 'd', 9, 0,
42
15.6k
  /* 147 */ 'f', 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0,
43
15.6k
  /* 157 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0,
44
15.6k
  /* 165 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0,
45
15.6k
  /* 173 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', 9, 0,
46
15.6k
  /* 183 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 'd', 9, 0,
47
15.6k
  /* 193 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', 9, 0,
48
15.6k
  /* 204 */ 'f', 'e', 'q', '.', 'd', 9, 0,
49
15.6k
  /* 211 */ 'l', 'r', '.', 'd', 9, 0,
50
15.6k
  /* 217 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', 9, 0,
51
15.6k
  /* 226 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', 9, 0,
52
15.6k
  /* 236 */ 'f', 'c', 'v', 't', '.', 's', '.', 'd', 9, 0,
53
15.6k
  /* 246 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'd', 9, 0,
54
15.6k
  /* 256 */ 'f', 'l', 't', '.', 'd', 9, 0,
55
15.6k
  /* 263 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0,
56
15.6k
  /* 272 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 'd', 9, 0,
57
15.6k
  /* 283 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', 9, 0,
58
15.6k
  /* 294 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 'd', 9, 0,
59
15.6k
  /* 305 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', 9, 0,
60
15.6k
  /* 316 */ 'f', 'd', 'i', 'v', '.', 'd', 9, 0,
61
15.6k
  /* 324 */ 'f', 'c', 'v', 't', '.', 'w', '.', 'd', 9, 0,
62
15.6k
  /* 334 */ 'f', 'm', 'v', '.', 'x', '.', 'd', 9, 0,
63
15.6k
  /* 343 */ 'f', 'm', 'a', 'x', '.', 'd', 9, 0,
64
15.6k
  /* 351 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', 9, 0,
65
15.6k
  /* 361 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 'd', 9, 0,
66
15.6k
  /* 371 */ 'c', '.', 'a', 'd', 'd', 9, 0,
67
15.6k
  /* 378 */ 'c', '.', 'l', 'd', 9, 0,
68
15.6k
  /* 384 */ 'c', '.', 'f', 'l', 'd', 9, 0,
69
15.6k
  /* 391 */ 'c', '.', 'a', 'n', 'd', 9, 0,
70
15.6k
  /* 398 */ 'c', '.', 's', 'd', 9, 0,
71
15.6k
  /* 404 */ 'c', '.', 'f', 's', 'd', 9, 0,
72
15.6k
  /* 411 */ 'f', 'e', 'n', 'c', 'e', 9, 0,
73
15.6k
  /* 418 */ 'b', 'g', 'e', 9, 0,
74
15.6k
  /* 423 */ 'b', 'n', 'e', 9, 0,
75
15.6k
  /* 428 */ 'm', 'u', 'l', 'h', 9, 0,
76
15.6k
  /* 434 */ 's', 'h', 9, 0,
77
15.6k
  /* 438 */ 'f', 'e', 'n', 'c', 'e', '.', 'i', 9, 0,
78
15.6k
  /* 447 */ 'c', '.', 's', 'r', 'a', 'i', 9, 0,
79
15.6k
  /* 455 */ 'c', 's', 'r', 'r', 'c', 'i', 9, 0,
80
15.6k
  /* 463 */ 'c', '.', 'a', 'd', 'd', 'i', 9, 0,
81
15.6k
  /* 471 */ 'c', '.', 'a', 'n', 'd', 'i', 9, 0,
82
15.6k
  /* 479 */ 'w', 'f', 'i', 9, 0,
83
15.6k
  /* 484 */ 'c', '.', 'l', 'i', 9, 0,
84
15.6k
  /* 490 */ 'c', '.', 's', 'l', 'l', 'i', 9, 0,
85
15.6k
  /* 498 */ 'c', '.', 's', 'r', 'l', 'i', 9, 0,
86
15.6k
  /* 506 */ 'x', 'o', 'r', 'i', 9, 0,
87
15.6k
  /* 512 */ 'c', 's', 'r', 'r', 's', 'i', 9, 0,
88
15.6k
  /* 520 */ 's', 'l', 't', 'i', 9, 0,
89
15.6k
  /* 526 */ 'c', '.', 'l', 'u', 'i', 9, 0,
90
15.6k
  /* 533 */ 'c', 's', 'r', 'r', 'w', 'i', 9, 0,
91
15.6k
  /* 541 */ 'c', '.', 'j', 9, 0,
92
15.6k
  /* 546 */ 'c', '.', 'e', 'b', 'r', 'e', 'a', 'k', 9, 0,
93
15.6k
  /* 556 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0,
94
15.6k
  /* 566 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 9, 0,
95
15.6k
  /* 576 */ 'c', '.', 'j', 'a', 'l', 9, 0,
96
15.6k
  /* 583 */ 't', 'a', 'i', 'l', 9, 0,
97
15.6k
  /* 589 */ 'e', 'c', 'a', 'l', 'l', 9, 0,
98
15.6k
  /* 596 */ 's', 'l', 'l', 9, 0,
99
15.6k
  /* 601 */ 's', 'c', '.', 'd', '.', 'r', 'l', 9, 0,
100
15.6k
  /* 610 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'r', 'l', 9, 0,
101
15.6k
  /* 623 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'r', 'l', 9, 0,
102
15.6k
  /* 636 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'r', 'l', 9, 0,
103
15.6k
  /* 649 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'r', 'l', 9, 0,
104
15.6k
  /* 663 */ 'l', 'r', '.', 'd', '.', 'r', 'l', 9, 0,
105
15.6k
  /* 672 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0,
106
15.6k
  /* 684 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0,
107
15.6k
  /* 697 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'r', 'l', 9, 0,
108
15.6k
  /* 711 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'r', 'l', 9, 0,
109
15.6k
  /* 725 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'r', 'l', 9, 0,
110
15.6k
  /* 738 */ 's', 'c', '.', 'w', '.', 'r', 'l', 9, 0,
111
15.6k
  /* 747 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'r', 'l', 9, 0,
112
15.6k
  /* 760 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'r', 'l', 9, 0,
113
15.6k
  /* 773 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'r', 'l', 9, 0,
114
15.6k
  /* 786 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'r', 'l', 9, 0,
115
15.6k
  /* 800 */ 'l', 'r', '.', 'w', '.', 'r', 'l', 9, 0,
116
15.6k
  /* 809 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0,
117
15.6k
  /* 821 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0,
118
15.6k
  /* 834 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'r', 'l', 9, 0,
119
15.6k
  /* 848 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'r', 'l', 9, 0,
120
15.6k
  /* 862 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'r', 'l', 9, 0,
121
15.6k
  /* 875 */ 's', 'c', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
122
15.6k
  /* 886 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
123
15.6k
  /* 901 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
124
15.6k
  /* 916 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
125
15.6k
  /* 931 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
126
15.6k
  /* 947 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
127
15.6k
  /* 958 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
128
15.6k
  /* 972 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
129
15.6k
  /* 987 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
130
15.6k
  /* 1003 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
131
15.6k
  /* 1019 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
132
15.6k
  /* 1034 */ 's', 'c', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
133
15.6k
  /* 1045 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
134
15.6k
  /* 1060 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
135
15.6k
  /* 1075 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
136
15.6k
  /* 1090 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
137
15.6k
  /* 1106 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
138
15.6k
  /* 1117 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
139
15.6k
  /* 1131 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
140
15.6k
  /* 1146 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
141
15.6k
  /* 1162 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
142
15.6k
  /* 1178 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
143
15.6k
  /* 1193 */ 's', 'r', 'l', 9, 0,
144
15.6k
  /* 1198 */ 'm', 'u', 'l', 9, 0,
145
15.6k
  /* 1203 */ 'r', 'e', 'm', 9, 0,
146
15.6k
  /* 1208 */ 'c', '.', 'a', 'd', 'd', 'i', '4', 's', 'p', 'n', 9, 0,
147
15.6k
  /* 1220 */ 'f', 'e', 'n', 'c', 'e', '.', 't', 's', 'o', 9, 0,
148
15.6k
  /* 1231 */ 'c', '.', 'u', 'n', 'i', 'm', 'p', 9, 0,
149
15.6k
  /* 1240 */ 'c', '.', 'n', 'o', 'p', 9, 0,
150
15.6k
  /* 1247 */ 'c', '.', 'a', 'd', 'd', 'i', '1', '6', 's', 'p', 9, 0,
151
15.6k
  /* 1259 */ 'c', '.', 'l', 'd', 's', 'p', 9, 0,
152
15.6k
  /* 1267 */ 'c', '.', 'f', 'l', 'd', 's', 'p', 9, 0,
153
15.6k
  /* 1276 */ 'c', '.', 's', 'd', 's', 'p', 9, 0,
154
15.6k
  /* 1284 */ 'c', '.', 'f', 's', 'd', 's', 'p', 9, 0,
155
15.6k
  /* 1293 */ 'c', '.', 'l', 'w', 's', 'p', 9, 0,
156
15.6k
  /* 1301 */ 'c', '.', 'f', 'l', 'w', 's', 'p', 9, 0,
157
15.6k
  /* 1310 */ 'c', '.', 's', 'w', 's', 'p', 9, 0,
158
15.6k
  /* 1318 */ 'c', '.', 'f', 's', 'w', 's', 'p', 9, 0,
159
15.6k
  /* 1327 */ 's', 'c', '.', 'd', '.', 'a', 'q', 9, 0,
160
15.6k
  /* 1336 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 9, 0,
161
15.6k
  /* 1349 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 9, 0,
162
15.6k
  /* 1362 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 9, 0,
163
15.6k
  /* 1375 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 9, 0,
164
15.6k
  /* 1389 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 9, 0,
165
15.6k
  /* 1398 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0,
166
15.6k
  /* 1410 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0,
167
15.6k
  /* 1423 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 9, 0,
168
15.6k
  /* 1437 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 9, 0,
169
15.6k
  /* 1451 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 9, 0,
170
15.6k
  /* 1464 */ 's', 'c', '.', 'w', '.', 'a', 'q', 9, 0,
171
15.6k
  /* 1473 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 9, 0,
172
15.6k
  /* 1486 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 9, 0,
173
15.6k
  /* 1499 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 9, 0,
174
15.6k
  /* 1512 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 9, 0,
175
15.6k
  /* 1526 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 9, 0,
176
15.6k
  /* 1535 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0,
177
15.6k
  /* 1547 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0,
178
15.6k
  /* 1560 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 9, 0,
179
15.6k
  /* 1574 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 9, 0,
180
15.6k
  /* 1588 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 9, 0,
181
15.6k
  /* 1601 */ 'b', 'e', 'q', 9, 0,
182
15.6k
  /* 1606 */ 'c', '.', 'j', 'r', 9, 0,
183
15.6k
  /* 1612 */ 'c', '.', 'j', 'a', 'l', 'r', 9, 0,
184
15.6k
  /* 1620 */ 'c', '.', 'o', 'r', 9, 0,
185
15.6k
  /* 1626 */ 'c', '.', 'x', 'o', 'r', 9, 0,
186
15.6k
  /* 1633 */ 'f', 's', 'u', 'b', '.', 's', 9, 0,
187
15.6k
  /* 1641 */ 'f', 'm', 's', 'u', 'b', '.', 's', 9, 0,
188
15.6k
  /* 1650 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 's', 9, 0,
189
15.6k
  /* 1660 */ 'f', 'c', 'v', 't', '.', 'd', '.', 's', 9, 0,
190
15.6k
  /* 1670 */ 'f', 'a', 'd', 'd', '.', 's', 9, 0,
191
15.6k
  /* 1678 */ 'f', 'm', 'a', 'd', 'd', '.', 's', 9, 0,
192
15.6k
  /* 1687 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 's', 9, 0,
193
15.6k
  /* 1697 */ 'f', 'l', 'e', '.', 's', 9, 0,
194
15.6k
  /* 1704 */ 'f', 's', 'g', 'n', 'j', '.', 's', 9, 0,
195
15.6k
  /* 1713 */ 'f', 'c', 'v', 't', '.', 'l', '.', 's', 9, 0,
196
15.6k
  /* 1723 */ 'f', 'm', 'u', 'l', '.', 's', 9, 0,
197
15.6k
  /* 1731 */ 'f', 'm', 'i', 'n', '.', 's', 9, 0,
198
15.6k
  /* 1739 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 's', 9, 0,
199
15.6k
  /* 1749 */ 'f', 'e', 'q', '.', 's', 9, 0,
200
15.6k
  /* 1756 */ 'f', 'c', 'l', 'a', 's', 's', '.', 's', 9, 0,
201
15.6k
  /* 1766 */ 'f', 'l', 't', '.', 's', 9, 0,
202
15.6k
  /* 1773 */ 'f', 's', 'q', 'r', 't', '.', 's', 9, 0,
203
15.6k
  /* 1782 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 's', 9, 0,
204
15.6k
  /* 1793 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 's', 9, 0,
205
15.6k
  /* 1804 */ 'f', 'd', 'i', 'v', '.', 's', 9, 0,
206
15.6k
  /* 1812 */ 'f', 'c', 'v', 't', '.', 'w', '.', 's', 9, 0,
207
15.6k
  /* 1822 */ 'f', 'm', 'a', 'x', '.', 's', 9, 0,
208
15.6k
  /* 1830 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 's', 9, 0,
209
15.6k
  /* 1840 */ 'c', 's', 'r', 'r', 's', 9, 0,
210
15.6k
  /* 1847 */ 'm', 'r', 'e', 't', 9, 0,
211
15.6k
  /* 1853 */ 's', 'r', 'e', 't', 9, 0,
212
15.6k
  /* 1859 */ 'u', 'r', 'e', 't', 9, 0,
213
15.6k
  /* 1865 */ 'b', 'l', 't', 9, 0,
214
15.6k
  /* 1870 */ 's', 'l', 't', 9, 0,
215
15.6k
  /* 1875 */ 'l', 'b', 'u', 9, 0,
216
15.6k
  /* 1880 */ 'b', 'g', 'e', 'u', 9, 0,
217
15.6k
  /* 1886 */ 'm', 'u', 'l', 'h', 'u', 9, 0,
218
15.6k
  /* 1893 */ 's', 'l', 't', 'i', 'u', 9, 0,
219
15.6k
  /* 1900 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 'u', 9, 0,
220
15.6k
  /* 1911 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 'u', 9, 0,
221
15.6k
  /* 1922 */ 'r', 'e', 'm', 'u', 9, 0,
222
15.6k
  /* 1928 */ 'm', 'u', 'l', 'h', 's', 'u', 9, 0,
223
15.6k
  /* 1936 */ 'b', 'l', 't', 'u', 9, 0,
224
15.6k
  /* 1942 */ 's', 'l', 't', 'u', 9, 0,
225
15.6k
  /* 1948 */ 'd', 'i', 'v', 'u', 9, 0,
226
15.6k
  /* 1954 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 'u', 9, 0,
227
15.6k
  /* 1965 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 'u', 9, 0,
228
15.6k
  /* 1976 */ 'l', 'w', 'u', 9, 0,
229
15.6k
  /* 1981 */ 'd', 'i', 'v', 9, 0,
230
15.6k
  /* 1986 */ 'c', '.', 'm', 'v', 9, 0,
231
15.6k
  /* 1992 */ 's', 'c', '.', 'w', 9, 0,
232
15.6k
  /* 1998 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0,
233
15.6k
  /* 2008 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', 9, 0,
234
15.6k
  /* 2018 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', 9, 0,
235
15.6k
  /* 2028 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', 9, 0,
236
15.6k
  /* 2038 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', 9, 0,
237
15.6k
  /* 2049 */ 'l', 'r', '.', 'w', 9, 0,
238
15.6k
  /* 2055 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', 9, 0,
239
15.6k
  /* 2064 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', 9, 0,
240
15.6k
  /* 2074 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 9, 0,
241
15.6k
  /* 2084 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', 9, 0,
242
15.6k
  /* 2095 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', 9, 0,
243
15.6k
  /* 2106 */ 'f', 'm', 'v', '.', 'x', '.', 'w', 9, 0,
244
15.6k
  /* 2115 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', 9, 0,
245
15.6k
  /* 2125 */ 's', 'r', 'a', 'w', 9, 0,
246
15.6k
  /* 2131 */ 'c', '.', 's', 'u', 'b', 'w', 9, 0,
247
15.6k
  /* 2139 */ 'c', '.', 'a', 'd', 'd', 'w', 9, 0,
248
15.6k
  /* 2147 */ 's', 'r', 'a', 'i', 'w', 9, 0,
249
15.6k
  /* 2154 */ 'c', '.', 'a', 'd', 'd', 'i', 'w', 9, 0,
250
15.6k
  /* 2163 */ 's', 'l', 'l', 'i', 'w', 9, 0,
251
15.6k
  /* 2170 */ 's', 'r', 'l', 'i', 'w', 9, 0,
252
15.6k
  /* 2177 */ 'c', '.', 'l', 'w', 9, 0,
253
15.6k
  /* 2183 */ 'c', '.', 'f', 'l', 'w', 9, 0,
254
15.6k
  /* 2190 */ 's', 'l', 'l', 'w', 9, 0,
255
15.6k
  /* 2196 */ 's', 'r', 'l', 'w', 9, 0,
256
15.6k
  /* 2202 */ 'm', 'u', 'l', 'w', 9, 0,
257
15.6k
  /* 2208 */ 'r', 'e', 'm', 'w', 9, 0,
258
15.6k
  /* 2214 */ 'c', 's', 'r', 'r', 'w', 9, 0,
259
15.6k
  /* 2221 */ 'c', '.', 's', 'w', 9, 0,
260
15.6k
  /* 2227 */ 'c', '.', 'f', 's', 'w', 9, 0,
261
15.6k
  /* 2234 */ 'r', 'e', 'm', 'u', 'w', 9, 0,
262
15.6k
  /* 2241 */ 'd', 'i', 'v', 'u', 'w', 9, 0,
263
15.6k
  /* 2248 */ 'd', 'i', 'v', 'w', 9, 0,
264
15.6k
  /* 2254 */ 'f', 'm', 'v', '.', 'd', '.', 'x', 9, 0,
265
15.6k
  /* 2263 */ 'f', 'm', 'v', '.', 'w', '.', 'x', 9, 0,
266
15.6k
  /* 2272 */ 'c', '.', 'b', 'n', 'e', 'z', 9, 0,
267
15.6k
  /* 2280 */ 'c', '.', 'b', 'e', 'q', 'z', 9, 0,
268
15.6k
  /* 2288 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0,
269
15.6k
  /* 2319 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0,
270
15.6k
  /* 2343 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0,
271
15.6k
  /* 2368 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0,
272
15.6k
  /* 2391 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0,
273
15.6k
  /* 2414 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0,
274
15.6k
  /* 2436 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
275
15.6k
  /* 2449 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
276
15.6k
  /* 2456 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
277
15.6k
  /* 2466 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
278
15.6k
  /* 2476 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
279
15.6k
  /* 2491 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0,
280
15.6k
  };
281
15.6k
#endif
282
283
15.6k
  static const uint16_t OpInfo0[] = {
284
15.6k
    0U, // PHI
285
15.6k
    0U, // INLINEASM
286
15.6k
    0U, // INLINEASM_BR
287
15.6k
    0U, // CFI_INSTRUCTION
288
15.6k
    0U, // EH_LABEL
289
15.6k
    0U, // GC_LABEL
290
15.6k
    0U, // ANNOTATION_LABEL
291
15.6k
    0U, // KILL
292
15.6k
    0U, // EXTRACT_SUBREG
293
15.6k
    0U, // INSERT_SUBREG
294
15.6k
    0U, // IMPLICIT_DEF
295
15.6k
    0U, // SUBREG_TO_REG
296
15.6k
    0U, // COPY_TO_REGCLASS
297
15.6k
    2457U,  // DBG_VALUE
298
15.6k
    2467U,  // DBG_LABEL
299
15.6k
    0U, // REG_SEQUENCE
300
15.6k
    0U, // COPY
301
15.6k
    2450U,  // BUNDLE
302
15.6k
    2477U,  // LIFETIME_START
303
15.6k
    2437U,  // LIFETIME_END
304
15.6k
    0U, // STACKMAP
305
15.6k
    2492U,  // FENTRY_CALL
306
15.6k
    0U, // PATCHPOINT
307
15.6k
    0U, // LOAD_STACK_GUARD
308
15.6k
    0U, // STATEPOINT
309
15.6k
    0U, // LOCAL_ESCAPE
310
15.6k
    0U, // FAULTING_OP
311
15.6k
    0U, // PATCHABLE_OP
312
15.6k
    2369U,  // PATCHABLE_FUNCTION_ENTER
313
15.6k
    2289U,  // PATCHABLE_RET
314
15.6k
    2415U,  // PATCHABLE_FUNCTION_EXIT
315
15.6k
    2392U,  // PATCHABLE_TAIL_CALL
316
15.6k
    2344U,  // PATCHABLE_EVENT_CALL
317
15.6k
    2320U,  // PATCHABLE_TYPED_EVENT_CALL
318
15.6k
    0U, // ICALL_BRANCH_FUNNEL
319
15.6k
    0U, // G_ADD
320
15.6k
    0U, // G_SUB
321
15.6k
    0U, // G_MUL
322
15.6k
    0U, // G_SDIV
323
15.6k
    0U, // G_UDIV
324
15.6k
    0U, // G_SREM
325
15.6k
    0U, // G_UREM
326
15.6k
    0U, // G_AND
327
15.6k
    0U, // G_OR
328
15.6k
    0U, // G_XOR
329
15.6k
    0U, // G_IMPLICIT_DEF
330
15.6k
    0U, // G_PHI
331
15.6k
    0U, // G_FRAME_INDEX
332
15.6k
    0U, // G_GLOBAL_VALUE
333
15.6k
    0U, // G_EXTRACT
334
15.6k
    0U, // G_UNMERGE_VALUES
335
15.6k
    0U, // G_INSERT
336
15.6k
    0U, // G_MERGE_VALUES
337
15.6k
    0U, // G_BUILD_VECTOR
338
15.6k
    0U, // G_BUILD_VECTOR_TRUNC
339
15.6k
    0U, // G_CONCAT_VECTORS
340
15.6k
    0U, // G_PTRTOINT
341
15.6k
    0U, // G_INTTOPTR
342
15.6k
    0U, // G_BITCAST
343
15.6k
    0U, // G_INTRINSIC_TRUNC
344
15.6k
    0U, // G_INTRINSIC_ROUND
345
15.6k
    0U, // G_LOAD
346
15.6k
    0U, // G_SEXTLOAD
347
15.6k
    0U, // G_ZEXTLOAD
348
15.6k
    0U, // G_STORE
349
15.6k
    0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
350
15.6k
    0U, // G_ATOMIC_CMPXCHG
351
15.6k
    0U, // G_ATOMICRMW_XCHG
352
15.6k
    0U, // G_ATOMICRMW_ADD
353
15.6k
    0U, // G_ATOMICRMW_SUB
354
15.6k
    0U, // G_ATOMICRMW_AND
355
15.6k
    0U, // G_ATOMICRMW_NAND
356
15.6k
    0U, // G_ATOMICRMW_OR
357
15.6k
    0U, // G_ATOMICRMW_XOR
358
15.6k
    0U, // G_ATOMICRMW_MAX
359
15.6k
    0U, // G_ATOMICRMW_MIN
360
15.6k
    0U, // G_ATOMICRMW_UMAX
361
15.6k
    0U, // G_ATOMICRMW_UMIN
362
15.6k
    0U, // G_BRCOND
363
15.6k
    0U, // G_BRINDIRECT
364
15.6k
    0U, // G_INTRINSIC
365
15.6k
    0U, // G_INTRINSIC_W_SIDE_EFFECTS
366
15.6k
    0U, // G_ANYEXT
367
15.6k
    0U, // G_TRUNC
368
15.6k
    0U, // G_CONSTANT
369
15.6k
    0U, // G_FCONSTANT
370
15.6k
    0U, // G_VASTART
371
15.6k
    0U, // G_VAARG
372
15.6k
    0U, // G_SEXT
373
15.6k
    0U, // G_ZEXT
374
15.6k
    0U, // G_SHL
375
15.6k
    0U, // G_LSHR
376
15.6k
    0U, // G_ASHR
377
15.6k
    0U, // G_ICMP
378
15.6k
    0U, // G_FCMP
379
15.6k
    0U, // G_SELECT
380
15.6k
    0U, // G_UADDO
381
15.6k
    0U, // G_UADDE
382
15.6k
    0U, // G_USUBO
383
15.6k
    0U, // G_USUBE
384
15.6k
    0U, // G_SADDO
385
15.6k
    0U, // G_SADDE
386
15.6k
    0U, // G_SSUBO
387
15.6k
    0U, // G_SSUBE
388
15.6k
    0U, // G_UMULO
389
15.6k
    0U, // G_SMULO
390
15.6k
    0U, // G_UMULH
391
15.6k
    0U, // G_SMULH
392
15.6k
    0U, // G_FADD
393
15.6k
    0U, // G_FSUB
394
15.6k
    0U, // G_FMUL
395
15.6k
    0U, // G_FMA
396
15.6k
    0U, // G_FDIV
397
15.6k
    0U, // G_FREM
398
15.6k
    0U, // G_FPOW
399
15.6k
    0U, // G_FEXP
400
15.6k
    0U, // G_FEXP2
401
15.6k
    0U, // G_FLOG
402
15.6k
    0U, // G_FLOG2
403
15.6k
    0U, // G_FLOG10
404
15.6k
    0U, // G_FNEG
405
15.6k
    0U, // G_FPEXT
406
15.6k
    0U, // G_FPTRUNC
407
15.6k
    0U, // G_FPTOSI
408
15.6k
    0U, // G_FPTOUI
409
15.6k
    0U, // G_SITOFP
410
15.6k
    0U, // G_UITOFP
411
15.6k
    0U, // G_FABS
412
15.6k
    0U, // G_FCANONICALIZE
413
15.6k
    0U, // G_GEP
414
15.6k
    0U, // G_PTR_MASK
415
15.6k
    0U, // G_BR
416
15.6k
    0U, // G_INSERT_VECTOR_ELT
417
15.6k
    0U, // G_EXTRACT_VECTOR_ELT
418
15.6k
    0U, // G_SHUFFLE_VECTOR
419
15.6k
    0U, // G_CTTZ
420
15.6k
    0U, // G_CTTZ_ZERO_UNDEF
421
15.6k
    0U, // G_CTLZ
422
15.6k
    0U, // G_CTLZ_ZERO_UNDEF
423
15.6k
    0U, // G_CTPOP
424
15.6k
    0U, // G_BSWAP
425
15.6k
    0U, // G_FCEIL
426
15.6k
    0U, // G_FCOS
427
15.6k
    0U, // G_FSIN
428
15.6k
    0U, // G_FSQRT
429
15.6k
    0U, // G_FFLOOR
430
15.6k
    0U, // G_ADDRSPACE_CAST
431
15.6k
    0U, // G_BLOCK_ADDR
432
15.6k
    4U, // ADJCALLSTACKDOWN
433
15.6k
    4U, // ADJCALLSTACKUP
434
15.6k
    4U, // BuildPairF64Pseudo
435
15.6k
    4U, // PseudoAtomicLoadNand32
436
15.6k
    4U, // PseudoAtomicLoadNand64
437
15.6k
    4U, // PseudoBR
438
15.6k
    4U, // PseudoBRIND
439
15.6k
    4687U,  // PseudoCALL
440
15.6k
    4U, // PseudoCALLIndirect
441
15.6k
    4U, // PseudoCmpXchg32
442
15.6k
    4U, // PseudoCmpXchg64
443
15.6k
    20482U, // PseudoLA
444
15.6k
    20967U, // PseudoLI
445
15.6k
    20481U, // PseudoLLA
446
15.6k
    4U, // PseudoMaskedAtomicLoadAdd32
447
15.6k
    4U, // PseudoMaskedAtomicLoadMax32
448
15.6k
    4U, // PseudoMaskedAtomicLoadMin32
449
15.6k
    4U, // PseudoMaskedAtomicLoadNand32
450
15.6k
    4U, // PseudoMaskedAtomicLoadSub32
451
15.6k
    4U, // PseudoMaskedAtomicLoadUMax32
452
15.6k
    4U, // PseudoMaskedAtomicLoadUMin32
453
15.6k
    4U, // PseudoMaskedAtomicSwap32
454
15.6k
    4U, // PseudoMaskedCmpXchg32
455
15.6k
    4U, // PseudoRET
456
15.6k
    4680U,  // PseudoTAIL
457
15.6k
    4U, // PseudoTAILIndirect
458
15.6k
    4U, // Select_FPR32_Using_CC_GPR
459
15.6k
    4U, // Select_FPR64_Using_CC_GPR
460
15.6k
    4U, // Select_GPR_Using_CC_GPR
461
15.6k
    4U, // SplitF64Pseudo
462
15.6k
    20854U, // ADD
463
15.6k
    20946U, // ADDI
464
15.6k
    22637U, // ADDIW
465
15.6k
    22622U, // ADDW
466
15.6k
    20592U, // AMOADD_D
467
15.6k
    21817U, // AMOADD_D_AQ
468
15.6k
    21367U, // AMOADD_D_AQ_RL
469
15.6k
    21091U, // AMOADD_D_RL
470
15.6k
    22489U, // AMOADD_W
471
15.6k
    21954U, // AMOADD_W_AQ
472
15.6k
    21526U, // AMOADD_W_AQ_RL
473
15.6k
    21228U, // AMOADD_W_RL
474
15.6k
    20602U, // AMOAND_D
475
15.6k
    21830U, // AMOAND_D_AQ
476
15.6k
    21382U, // AMOAND_D_AQ_RL
477
15.6k
    21104U, // AMOAND_D_RL
478
15.6k
    22499U, // AMOAND_W
479
15.6k
    21967U, // AMOAND_W_AQ
480
15.6k
    21541U, // AMOAND_W_AQ_RL
481
15.6k
    21241U, // AMOAND_W_RL
482
15.6k
    20786U, // AMOMAXU_D
483
15.6k
    21918U, // AMOMAXU_D_AQ
484
15.6k
    21484U, // AMOMAXU_D_AQ_RL
485
15.6k
    21192U, // AMOMAXU_D_RL
486
15.6k
    22576U, // AMOMAXU_W
487
15.6k
    22055U, // AMOMAXU_W_AQ
488
15.6k
    21643U, // AMOMAXU_W_AQ_RL
489
15.6k
    21329U, // AMOMAXU_W_RL
490
15.6k
    20832U, // AMOMAX_D
491
15.6k
    21932U, // AMOMAX_D_AQ
492
15.6k
    21500U, // AMOMAX_D_AQ_RL
493
15.6k
    21206U, // AMOMAX_D_RL
494
15.6k
    22596U, // AMOMAX_W
495
15.6k
    22069U, // AMOMAX_W_AQ
496
15.6k
    21659U, // AMOMAX_W_AQ_RL
497
15.6k
    21343U, // AMOMAX_W_RL
498
15.6k
    20764U, // AMOMINU_D
499
15.6k
    21904U, // AMOMINU_D_AQ
500
15.6k
    21468U, // AMOMINU_D_AQ_RL
501
15.6k
    21178U, // AMOMINU_D_RL
502
15.6k
    22565U, // AMOMINU_W
503
15.6k
    22041U, // AMOMINU_W_AQ
504
15.6k
    21627U, // AMOMINU_W_AQ_RL
505
15.6k
    21315U, // AMOMINU_W_RL
506
15.6k
    20654U, // AMOMIN_D
507
15.6k
    21843U, // AMOMIN_D_AQ
508
15.6k
    21397U, // AMOMIN_D_AQ_RL
509
15.6k
    21117U, // AMOMIN_D_RL
510
15.6k
    22509U, // AMOMIN_W
511
15.6k
    21980U, // AMOMIN_W_AQ
512
15.6k
    21556U, // AMOMIN_W_AQ_RL
513
15.6k
    21254U, // AMOMIN_W_RL
514
15.6k
    20698U, // AMOOR_D
515
15.6k
    21879U, // AMOOR_D_AQ
516
15.6k
    21439U, // AMOOR_D_AQ_RL
517
15.6k
    21153U, // AMOOR_D_RL
518
15.6k
    22536U, // AMOOR_W
519
15.6k
    22016U, // AMOOR_W_AQ
520
15.6k
    21598U, // AMOOR_W_AQ_RL
521
15.6k
    21290U, // AMOOR_W_RL
522
15.6k
    20674U, // AMOSWAP_D
523
15.6k
    21856U, // AMOSWAP_D_AQ
524
15.6k
    21412U, // AMOSWAP_D_AQ_RL
525
15.6k
    21130U, // AMOSWAP_D_RL
526
15.6k
    22519U, // AMOSWAP_W
527
15.6k
    21993U, // AMOSWAP_W_AQ
528
15.6k
    21571U, // AMOSWAP_W_AQ_RL
529
15.6k
    21267U, // AMOSWAP_W_RL
530
15.6k
    20707U, // AMOXOR_D
531
15.6k
    21891U, // AMOXOR_D_AQ
532
15.6k
    21453U, // AMOXOR_D_AQ_RL
533
15.6k
    21165U, // AMOXOR_D_RL
534
15.6k
    22545U, // AMOXOR_W
535
15.6k
    22028U, // AMOXOR_W_AQ
536
15.6k
    21612U, // AMOXOR_W_AQ_RL
537
15.6k
    21302U, // AMOXOR_W_RL
538
15.6k
    20874U, // AND
539
15.6k
    20954U, // ANDI
540
15.6k
    20518U, // AUIPC
541
15.6k
    22082U, // BEQ
542
15.6k
    20899U, // BGE
543
15.6k
    22361U, // BGEU
544
15.6k
    22346U, // BLT
545
15.6k
    22417U, // BLTU
546
15.6k
    20904U, // BNE
547
15.6k
    20525U, // CSRRC
548
15.6k
    20936U, // CSRRCI
549
15.6k
    22321U, // CSRRS
550
15.6k
    20993U, // CSRRSI
551
15.6k
    22695U, // CSRRW
552
15.6k
    21014U, // CSRRWI
553
15.6k
    8564U,  // C_ADD
554
15.6k
    8656U,  // C_ADDI
555
15.6k
    9440U,  // C_ADDI16SP
556
15.6k
    21689U, // C_ADDI4SPN
557
15.6k
    10347U, // C_ADDIW
558
15.6k
    10332U, // C_ADDW
559
15.6k
    8584U,  // C_AND
560
15.6k
    8664U,  // C_ANDI
561
15.6k
    22761U, // C_BEQZ
562
15.6k
    22753U, // C_BNEZ
563
15.6k
    547U, // C_EBREAK
564
15.6k
    20865U, // C_FLD
565
15.6k
    21748U, // C_FLDSP
566
15.6k
    22664U, // C_FLW
567
15.6k
    21782U, // C_FLWSP
568
15.6k
    20885U, // C_FSD
569
15.6k
    21765U, // C_FSDSP
570
15.6k
    22708U, // C_FSW
571
15.6k
    21799U, // C_FSWSP
572
15.6k
    4638U,  // C_J
573
15.6k
    4673U,  // C_JAL
574
15.6k
    5709U,  // C_JALR
575
15.6k
    5703U,  // C_JR
576
15.6k
    20859U, // C_LD
577
15.6k
    21740U, // C_LDSP
578
15.6k
    20965U, // C_LI
579
15.6k
    21007U, // C_LUI
580
15.6k
    22658U, // C_LW
581
15.6k
    21774U, // C_LWSP
582
15.6k
    22467U, // C_MV
583
15.6k
    1241U,  // C_NOP
584
15.6k
    9813U,  // C_OR
585
15.6k
    20879U, // C_SD
586
15.6k
    21757U, // C_SDSP
587
15.6k
    8683U,  // C_SLLI
588
15.6k
    8640U,  // C_SRAI
589
15.6k
    8691U,  // C_SRLI
590
15.6k
    8223U,  // C_SUB
591
15.6k
    10324U, // C_SUBW
592
15.6k
    22702U, // C_SW
593
15.6k
    21791U, // C_SWSP
594
15.6k
    1232U,  // C_UNIMP
595
15.6k
    9819U,  // C_XOR
596
15.6k
    22462U, // DIV
597
15.6k
    22429U, // DIVU
598
15.6k
    22722U, // DIVUW
599
15.6k
    22729U, // DIVW
600
15.6k
    549U, // EBREAK
601
15.6k
    590U, // ECALL
602
15.6k
    20565U, // FADD_D
603
15.6k
    22151U, // FADD_S
604
15.6k
    20727U, // FCLASS_D
605
15.6k
    22237U, // FCLASS_S
606
15.6k
    21037U, // FCVT_D_L
607
15.6k
    22381U, // FCVT_D_LU
608
15.6k
    22141U, // FCVT_D_S
609
15.6k
    22479U, // FCVT_D_W
610
15.6k
    22435U, // FCVT_D_WU
611
15.6k
    20753U, // FCVT_LU_D
612
15.6k
    22263U, // FCVT_LU_S
613
15.6k
    20628U, // FCVT_L_D
614
15.6k
    22194U, // FCVT_L_S
615
15.6k
    20717U, // FCVT_S_D
616
15.6k
    21047U, // FCVT_S_L
617
15.6k
    22392U, // FCVT_S_LU
618
15.6k
    22555U, // FCVT_S_W
619
15.6k
    22446U, // FCVT_S_WU
620
15.6k
    20775U, // FCVT_WU_D
621
15.6k
    22274U, // FCVT_WU_S
622
15.6k
    20805U, // FCVT_W_D
623
15.6k
    22293U, // FCVT_W_S
624
15.6k
    20797U, // FDIV_D
625
15.6k
    22285U, // FDIV_S
626
15.6k
    12700U, // FENCE
627
15.6k
    439U, // FENCE_I
628
15.6k
    1221U,  // FENCE_TSO
629
15.6k
    20685U, // FEQ_D
630
15.6k
    22230U, // FEQ_S
631
15.6k
    20867U, // FLD
632
15.6k
    20612U, // FLE_D
633
15.6k
    22178U, // FLE_S
634
15.6k
    20737U, // FLT_D
635
15.6k
    22247U, // FLT_S
636
15.6k
    22666U, // FLW
637
15.6k
    20573U, // FMADD_D
638
15.6k
    22159U, // FMADD_S
639
15.6k
    20824U, // FMAX_D
640
15.6k
    22303U, // FMAX_S
641
15.6k
    20646U, // FMIN_D
642
15.6k
    22212U, // FMIN_S
643
15.6k
    20540U, // FMSUB_D
644
15.6k
    22122U, // FMSUB_S
645
15.6k
    20638U, // FMUL_D
646
15.6k
    22204U, // FMUL_S
647
15.6k
    22735U, // FMV_D_X
648
15.6k
    22744U, // FMV_W_X
649
15.6k
    20815U, // FMV_X_D
650
15.6k
    22587U, // FMV_X_W
651
15.6k
    20582U, // FNMADD_D
652
15.6k
    22168U, // FNMADD_S
653
15.6k
    20549U, // FNMSUB_D
654
15.6k
    22131U, // FNMSUB_S
655
15.6k
    20887U, // FSD
656
15.6k
    20664U, // FSGNJN_D
657
15.6k
    22220U, // FSGNJN_S
658
15.6k
    20842U, // FSGNJX_D
659
15.6k
    22311U, // FSGNJX_S
660
15.6k
    20619U, // FSGNJ_D
661
15.6k
    22185U, // FSGNJ_S
662
15.6k
    20744U, // FSQRT_D
663
15.6k
    22254U, // FSQRT_S
664
15.6k
    20532U, // FSUB_D
665
15.6k
    22114U, // FSUB_S
666
15.6k
    22710U, // FSW
667
15.6k
    21059U, // JAL
668
15.6k
    22095U, // JALR
669
15.6k
    20503U, // LB
670
15.6k
    22356U, // LBU
671
15.6k
    20861U, // LD
672
15.6k
    20911U, // LH
673
15.6k
    22369U, // LHU
674
15.6k
    37076U, // LR_D
675
15.6k
    38254U, // LR_D_AQ
676
15.6k
    37812U, // LR_D_AQ_RL
677
15.6k
    37528U, // LR_D_RL
678
15.6k
    38914U, // LR_W
679
15.6k
    38391U, // LR_W_AQ
680
15.6k
    37971U, // LR_W_AQ_RL
681
15.6k
    37665U, // LR_W_RL
682
15.6k
    21009U, // LUI
683
15.6k
    22660U, // LW
684
15.6k
    22457U, // LWU
685
15.6k
    1848U,  // MRET
686
15.6k
    21679U, // MUL
687
15.6k
    20909U, // MULH
688
15.6k
    22409U, // MULHSU
689
15.6k
    22367U, // MULHU
690
15.6k
    22683U, // MULW
691
15.6k
    22103U, // OR
692
15.6k
    20988U, // ORI
693
15.6k
    21684U, // REM
694
15.6k
    22403U, // REMU
695
15.6k
    22715U, // REMUW
696
15.6k
    22689U, // REMW
697
15.6k
    20507U, // SB
698
15.6k
    20559U, // SC_D
699
15.6k
    21808U, // SC_D_AQ
700
15.6k
    21356U, // SC_D_AQ_RL
701
15.6k
    21082U, // SC_D_RL
702
15.6k
    22473U, // SC_W
703
15.6k
    21945U, // SC_W_AQ
704
15.6k
    21515U, // SC_W_AQ_RL
705
15.6k
    21219U, // SC_W_RL
706
15.6k
    20881U, // SD
707
15.6k
    20486U, // SFENCE_VMA
708
15.6k
    20915U, // SH
709
15.6k
    21077U, // SLL
710
15.6k
    20973U, // SLLI
711
15.6k
    22644U, // SLLIW
712
15.6k
    22671U, // SLLW
713
15.6k
    22351U, // SLT
714
15.6k
    21001U, // SLTI
715
15.6k
    22374U, // SLTIU
716
15.6k
    22423U, // SLTU
717
15.6k
    20498U, // SRA
718
15.6k
    20930U, // SRAI
719
15.6k
    22628U, // SRAIW
720
15.6k
    22606U, // SRAW
721
15.6k
    1854U,  // SRET
722
15.6k
    21674U, // SRL
723
15.6k
    20981U, // SRLI
724
15.6k
    22651U, // SRLIW
725
15.6k
    22677U, // SRLW
726
15.6k
    20513U, // SUB
727
15.6k
    22614U, // SUBW
728
15.6k
    22704U, // SW
729
15.6k
    1234U,  // UNIMP
730
15.6k
    1860U,  // URET
731
15.6k
    480U, // WFI
732
15.6k
    22109U, // XOR
733
15.6k
    20987U, // XORI
734
15.6k
  };
735
736
15.6k
  static const uint8_t OpInfo1[] = {
737
15.6k
    0U, // PHI
738
15.6k
    0U, // INLINEASM
739
15.6k
    0U, // INLINEASM_BR
740
15.6k
    0U, // CFI_INSTRUCTION
741
15.6k
    0U, // EH_LABEL
742
15.6k
    0U, // GC_LABEL
743
15.6k
    0U, // ANNOTATION_LABEL
744
15.6k
    0U, // KILL
745
15.6k
    0U, // EXTRACT_SUBREG
746
15.6k
    0U, // INSERT_SUBREG
747
15.6k
    0U, // IMPLICIT_DEF
748
15.6k
    0U, // SUBREG_TO_REG
749
15.6k
    0U, // COPY_TO_REGCLASS
750
15.6k
    0U, // DBG_VALUE
751
15.6k
    0U, // DBG_LABEL
752
15.6k
    0U, // REG_SEQUENCE
753
15.6k
    0U, // COPY
754
15.6k
    0U, // BUNDLE
755
15.6k
    0U, // LIFETIME_START
756
15.6k
    0U, // LIFETIME_END
757
15.6k
    0U, // STACKMAP
758
15.6k
    0U, // FENTRY_CALL
759
15.6k
    0U, // PATCHPOINT
760
15.6k
    0U, // LOAD_STACK_GUARD
761
15.6k
    0U, // STATEPOINT
762
15.6k
    0U, // LOCAL_ESCAPE
763
15.6k
    0U, // FAULTING_OP
764
15.6k
    0U, // PATCHABLE_OP
765
15.6k
    0U, // PATCHABLE_FUNCTION_ENTER
766
15.6k
    0U, // PATCHABLE_RET
767
15.6k
    0U, // PATCHABLE_FUNCTION_EXIT
768
15.6k
    0U, // PATCHABLE_TAIL_CALL
769
15.6k
    0U, // PATCHABLE_EVENT_CALL
770
15.6k
    0U, // PATCHABLE_TYPED_EVENT_CALL
771
15.6k
    0U, // ICALL_BRANCH_FUNNEL
772
15.6k
    0U, // G_ADD
773
15.6k
    0U, // G_SUB
774
15.6k
    0U, // G_MUL
775
15.6k
    0U, // G_SDIV
776
15.6k
    0U, // G_UDIV
777
15.6k
    0U, // G_SREM
778
15.6k
    0U, // G_UREM
779
15.6k
    0U, // G_AND
780
15.6k
    0U, // G_OR
781
15.6k
    0U, // G_XOR
782
15.6k
    0U, // G_IMPLICIT_DEF
783
15.6k
    0U, // G_PHI
784
15.6k
    0U, // G_FRAME_INDEX
785
15.6k
    0U, // G_GLOBAL_VALUE
786
15.6k
    0U, // G_EXTRACT
787
15.6k
    0U, // G_UNMERGE_VALUES
788
15.6k
    0U, // G_INSERT
789
15.6k
    0U, // G_MERGE_VALUES
790
15.6k
    0U, // G_BUILD_VECTOR
791
15.6k
    0U, // G_BUILD_VECTOR_TRUNC
792
15.6k
    0U, // G_CONCAT_VECTORS
793
15.6k
    0U, // G_PTRTOINT
794
15.6k
    0U, // G_INTTOPTR
795
15.6k
    0U, // G_BITCAST
796
15.6k
    0U, // G_INTRINSIC_TRUNC
797
15.6k
    0U, // G_INTRINSIC_ROUND
798
15.6k
    0U, // G_LOAD
799
15.6k
    0U, // G_SEXTLOAD
800
15.6k
    0U, // G_ZEXTLOAD
801
15.6k
    0U, // G_STORE
802
15.6k
    0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
803
15.6k
    0U, // G_ATOMIC_CMPXCHG
804
15.6k
    0U, // G_ATOMICRMW_XCHG
805
15.6k
    0U, // G_ATOMICRMW_ADD
806
15.6k
    0U, // G_ATOMICRMW_SUB
807
15.6k
    0U, // G_ATOMICRMW_AND
808
15.6k
    0U, // G_ATOMICRMW_NAND
809
15.6k
    0U, // G_ATOMICRMW_OR
810
15.6k
    0U, // G_ATOMICRMW_XOR
811
15.6k
    0U, // G_ATOMICRMW_MAX
812
15.6k
    0U, // G_ATOMICRMW_MIN
813
15.6k
    0U, // G_ATOMICRMW_UMAX
814
15.6k
    0U, // G_ATOMICRMW_UMIN
815
15.6k
    0U, // G_BRCOND
816
15.6k
    0U, // G_BRINDIRECT
817
15.6k
    0U, // G_INTRINSIC
818
15.6k
    0U, // G_INTRINSIC_W_SIDE_EFFECTS
819
15.6k
    0U, // G_ANYEXT
820
15.6k
    0U, // G_TRUNC
821
15.6k
    0U, // G_CONSTANT
822
15.6k
    0U, // G_FCONSTANT
823
15.6k
    0U, // G_VASTART
824
15.6k
    0U, // G_VAARG
825
15.6k
    0U, // G_SEXT
826
15.6k
    0U, // G_ZEXT
827
15.6k
    0U, // G_SHL
828
15.6k
    0U, // G_LSHR
829
15.6k
    0U, // G_ASHR
830
15.6k
    0U, // G_ICMP
831
15.6k
    0U, // G_FCMP
832
15.6k
    0U, // G_SELECT
833
15.6k
    0U, // G_UADDO
834
15.6k
    0U, // G_UADDE
835
15.6k
    0U, // G_USUBO
836
15.6k
    0U, // G_USUBE
837
15.6k
    0U, // G_SADDO
838
15.6k
    0U, // G_SADDE
839
15.6k
    0U, // G_SSUBO
840
15.6k
    0U, // G_SSUBE
841
15.6k
    0U, // G_UMULO
842
15.6k
    0U, // G_SMULO
843
15.6k
    0U, // G_UMULH
844
15.6k
    0U, // G_SMULH
845
15.6k
    0U, // G_FADD
846
15.6k
    0U, // G_FSUB
847
15.6k
    0U, // G_FMUL
848
15.6k
    0U, // G_FMA
849
15.6k
    0U, // G_FDIV
850
15.6k
    0U, // G_FREM
851
15.6k
    0U, // G_FPOW
852
15.6k
    0U, // G_FEXP
853
15.6k
    0U, // G_FEXP2
854
15.6k
    0U, // G_FLOG
855
15.6k
    0U, // G_FLOG2
856
15.6k
    0U, // G_FLOG10
857
15.6k
    0U, // G_FNEG
858
15.6k
    0U, // G_FPEXT
859
15.6k
    0U, // G_FPTRUNC
860
15.6k
    0U, // G_FPTOSI
861
15.6k
    0U, // G_FPTOUI
862
15.6k
    0U, // G_SITOFP
863
15.6k
    0U, // G_UITOFP
864
15.6k
    0U, // G_FABS
865
15.6k
    0U, // G_FCANONICALIZE
866
15.6k
    0U, // G_GEP
867
15.6k
    0U, // G_PTR_MASK
868
15.6k
    0U, // G_BR
869
15.6k
    0U, // G_INSERT_VECTOR_ELT
870
15.6k
    0U, // G_EXTRACT_VECTOR_ELT
871
15.6k
    0U, // G_SHUFFLE_VECTOR
872
15.6k
    0U, // G_CTTZ
873
15.6k
    0U, // G_CTTZ_ZERO_UNDEF
874
15.6k
    0U, // G_CTLZ
875
15.6k
    0U, // G_CTLZ_ZERO_UNDEF
876
15.6k
    0U, // G_CTPOP
877
15.6k
    0U, // G_BSWAP
878
15.6k
    0U, // G_FCEIL
879
15.6k
    0U, // G_FCOS
880
15.6k
    0U, // G_FSIN
881
15.6k
    0U, // G_FSQRT
882
15.6k
    0U, // G_FFLOOR
883
15.6k
    0U, // G_ADDRSPACE_CAST
884
15.6k
    0U, // G_BLOCK_ADDR
885
15.6k
    0U, // ADJCALLSTACKDOWN
886
15.6k
    0U, // ADJCALLSTACKUP
887
15.6k
    0U, // BuildPairF64Pseudo
888
15.6k
    0U, // PseudoAtomicLoadNand32
889
15.6k
    0U, // PseudoAtomicLoadNand64
890
15.6k
    0U, // PseudoBR
891
15.6k
    0U, // PseudoBRIND
892
15.6k
    0U, // PseudoCALL
893
15.6k
    0U, // PseudoCALLIndirect
894
15.6k
    0U, // PseudoCmpXchg32
895
15.6k
    0U, // PseudoCmpXchg64
896
15.6k
    0U, // PseudoLA
897
15.6k
    0U, // PseudoLI
898
15.6k
    0U, // PseudoLLA
899
15.6k
    0U, // PseudoMaskedAtomicLoadAdd32
900
15.6k
    0U, // PseudoMaskedAtomicLoadMax32
901
15.6k
    0U, // PseudoMaskedAtomicLoadMin32
902
15.6k
    0U, // PseudoMaskedAtomicLoadNand32
903
15.6k
    0U, // PseudoMaskedAtomicLoadSub32
904
15.6k
    0U, // PseudoMaskedAtomicLoadUMax32
905
15.6k
    0U, // PseudoMaskedAtomicLoadUMin32
906
15.6k
    0U, // PseudoMaskedAtomicSwap32
907
15.6k
    0U, // PseudoMaskedCmpXchg32
908
15.6k
    0U, // PseudoRET
909
15.6k
    0U, // PseudoTAIL
910
15.6k
    0U, // PseudoTAILIndirect
911
15.6k
    0U, // Select_FPR32_Using_CC_GPR
912
15.6k
    0U, // Select_FPR64_Using_CC_GPR
913
15.6k
    0U, // Select_GPR_Using_CC_GPR
914
15.6k
    0U, // SplitF64Pseudo
915
15.6k
    4U, // ADD
916
15.6k
    4U, // ADDI
917
15.6k
    4U, // ADDIW
918
15.6k
    4U, // ADDW
919
15.6k
    9U, // AMOADD_D
920
15.6k
    9U, // AMOADD_D_AQ
921
15.6k
    9U, // AMOADD_D_AQ_RL
922
15.6k
    9U, // AMOADD_D_RL
923
15.6k
    9U, // AMOADD_W
924
15.6k
    9U, // AMOADD_W_AQ
925
15.6k
    9U, // AMOADD_W_AQ_RL
926
15.6k
    9U, // AMOADD_W_RL
927
15.6k
    9U, // AMOAND_D
928
15.6k
    9U, // AMOAND_D_AQ
929
15.6k
    9U, // AMOAND_D_AQ_RL
930
15.6k
    9U, // AMOAND_D_RL
931
15.6k
    9U, // AMOAND_W
932
15.6k
    9U, // AMOAND_W_AQ
933
15.6k
    9U, // AMOAND_W_AQ_RL
934
15.6k
    9U, // AMOAND_W_RL
935
15.6k
    9U, // AMOMAXU_D
936
15.6k
    9U, // AMOMAXU_D_AQ
937
15.6k
    9U, // AMOMAXU_D_AQ_RL
938
15.6k
    9U, // AMOMAXU_D_RL
939
15.6k
    9U, // AMOMAXU_W
940
15.6k
    9U, // AMOMAXU_W_AQ
941
15.6k
    9U, // AMOMAXU_W_AQ_RL
942
15.6k
    9U, // AMOMAXU_W_RL
943
15.6k
    9U, // AMOMAX_D
944
15.6k
    9U, // AMOMAX_D_AQ
945
15.6k
    9U, // AMOMAX_D_AQ_RL
946
15.6k
    9U, // AMOMAX_D_RL
947
15.6k
    9U, // AMOMAX_W
948
15.6k
    9U, // AMOMAX_W_AQ
949
15.6k
    9U, // AMOMAX_W_AQ_RL
950
15.6k
    9U, // AMOMAX_W_RL
951
15.6k
    9U, // AMOMINU_D
952
15.6k
    9U, // AMOMINU_D_AQ
953
15.6k
    9U, // AMOMINU_D_AQ_RL
954
15.6k
    9U, // AMOMINU_D_RL
955
15.6k
    9U, // AMOMINU_W
956
15.6k
    9U, // AMOMINU_W_AQ
957
15.6k
    9U, // AMOMINU_W_AQ_RL
958
15.6k
    9U, // AMOMINU_W_RL
959
15.6k
    9U, // AMOMIN_D
960
15.6k
    9U, // AMOMIN_D_AQ
961
15.6k
    9U, // AMOMIN_D_AQ_RL
962
15.6k
    9U, // AMOMIN_D_RL
963
15.6k
    9U, // AMOMIN_W
964
15.6k
    9U, // AMOMIN_W_AQ
965
15.6k
    9U, // AMOMIN_W_AQ_RL
966
15.6k
    9U, // AMOMIN_W_RL
967
15.6k
    9U, // AMOOR_D
968
15.6k
    9U, // AMOOR_D_AQ
969
15.6k
    9U, // AMOOR_D_AQ_RL
970
15.6k
    9U, // AMOOR_D_RL
971
15.6k
    9U, // AMOOR_W
972
15.6k
    9U, // AMOOR_W_AQ
973
15.6k
    9U, // AMOOR_W_AQ_RL
974
15.6k
    9U, // AMOOR_W_RL
975
15.6k
    9U, // AMOSWAP_D
976
15.6k
    9U, // AMOSWAP_D_AQ
977
15.6k
    9U, // AMOSWAP_D_AQ_RL
978
15.6k
    9U, // AMOSWAP_D_RL
979
15.6k
    9U, // AMOSWAP_W
980
15.6k
    9U, // AMOSWAP_W_AQ
981
15.6k
    9U, // AMOSWAP_W_AQ_RL
982
15.6k
    9U, // AMOSWAP_W_RL
983
15.6k
    9U, // AMOXOR_D
984
15.6k
    9U, // AMOXOR_D_AQ
985
15.6k
    9U, // AMOXOR_D_AQ_RL
986
15.6k
    9U, // AMOXOR_D_RL
987
15.6k
    9U, // AMOXOR_W
988
15.6k
    9U, // AMOXOR_W_AQ
989
15.6k
    9U, // AMOXOR_W_AQ_RL
990
15.6k
    9U, // AMOXOR_W_RL
991
15.6k
    4U, // AND
992
15.6k
    4U, // ANDI
993
15.6k
    0U, // AUIPC
994
15.6k
    4U, // BEQ
995
15.6k
    4U, // BGE
996
15.6k
    4U, // BGEU
997
15.6k
    4U, // BLT
998
15.6k
    4U, // BLTU
999
15.6k
    4U, // BNE
1000
15.6k
    2U, // CSRRC
1001
15.6k
    2U, // CSRRCI
1002
15.6k
    2U, // CSRRS
1003
15.6k
    2U, // CSRRSI
1004
15.6k
    2U, // CSRRW
1005
15.6k
    2U, // CSRRWI
1006
15.6k
    0U, // C_ADD
1007
15.6k
    0U, // C_ADDI
1008
15.6k
    0U, // C_ADDI16SP
1009
15.6k
    4U, // C_ADDI4SPN
1010
15.6k
    0U, // C_ADDIW
1011
15.6k
    0U, // C_ADDW
1012
15.6k
    0U, // C_AND
1013
15.6k
    0U, // C_ANDI
1014
15.6k
    0U, // C_BEQZ
1015
15.6k
    0U, // C_BNEZ
1016
15.6k
    0U, // C_EBREAK
1017
15.6k
    13U,  // C_FLD
1018
15.6k
    13U,  // C_FLDSP
1019
15.6k
    13U,  // C_FLW
1020
15.6k
    13U,  // C_FLWSP
1021
15.6k
    13U,  // C_FSD
1022
15.6k
    13U,  // C_FSDSP
1023
15.6k
    13U,  // C_FSW
1024
15.6k
    13U,  // C_FSWSP
1025
15.6k
    0U, // C_J
1026
15.6k
    0U, // C_JAL
1027
15.6k
    0U, // C_JALR
1028
15.6k
    0U, // C_JR
1029
15.6k
    13U,  // C_LD
1030
15.6k
    13U,  // C_LDSP
1031
15.6k
    0U, // C_LI
1032
15.6k
    0U, // C_LUI
1033
15.6k
    13U,  // C_LW
1034
15.6k
    13U,  // C_LWSP
1035
15.6k
    0U, // C_MV
1036
15.6k
    0U, // C_NOP
1037
15.6k
    0U, // C_OR
1038
15.6k
    13U,  // C_SD
1039
15.6k
    13U,  // C_SDSP
1040
15.6k
    0U, // C_SLLI
1041
15.6k
    0U, // C_SRAI
1042
15.6k
    0U, // C_SRLI
1043
15.6k
    0U, // C_SUB
1044
15.6k
    0U, // C_SUBW
1045
15.6k
    13U,  // C_SW
1046
15.6k
    13U,  // C_SWSP
1047
15.6k
    0U, // C_UNIMP
1048
15.6k
    0U, // C_XOR
1049
15.6k
    4U, // DIV
1050
15.6k
    4U, // DIVU
1051
15.6k
    4U, // DIVUW
1052
15.6k
    4U, // DIVW
1053
15.6k
    0U, // EBREAK
1054
15.6k
    0U, // ECALL
1055
15.6k
    36U,  // FADD_D
1056
15.6k
    36U,  // FADD_S
1057
15.6k
    0U, // FCLASS_D
1058
15.6k
    0U, // FCLASS_S
1059
15.6k
    20U,  // FCVT_D_L
1060
15.6k
    20U,  // FCVT_D_LU
1061
15.6k
    0U, // FCVT_D_S
1062
15.6k
    0U, // FCVT_D_W
1063
15.6k
    0U, // FCVT_D_WU
1064
15.6k
    20U,  // FCVT_LU_D
1065
15.6k
    20U,  // FCVT_LU_S
1066
15.6k
    20U,  // FCVT_L_D
1067
15.6k
    20U,  // FCVT_L_S
1068
15.6k
    20U,  // FCVT_S_D
1069
15.6k
    20U,  // FCVT_S_L
1070
15.6k
    20U,  // FCVT_S_LU
1071
15.6k
    20U,  // FCVT_S_W
1072
15.6k
    20U,  // FCVT_S_WU
1073
15.6k
    20U,  // FCVT_WU_D
1074
15.6k
    20U,  // FCVT_WU_S
1075
15.6k
    20U,  // FCVT_W_D
1076
15.6k
    20U,  // FCVT_W_S
1077
15.6k
    36U,  // FDIV_D
1078
15.6k
    36U,  // FDIV_S
1079
15.6k
    0U, // FENCE
1080
15.6k
    0U, // FENCE_I
1081
15.6k
    0U, // FENCE_TSO
1082
15.6k
    4U, // FEQ_D
1083
15.6k
    4U, // FEQ_S
1084
15.6k
    13U,  // FLD
1085
15.6k
    4U, // FLE_D
1086
15.6k
    4U, // FLE_S
1087
15.6k
    4U, // FLT_D
1088
15.6k
    4U, // FLT_S
1089
15.6k
    13U,  // FLW
1090
15.6k
    100U, // FMADD_D
1091
15.6k
    100U, // FMADD_S
1092
15.6k
    4U, // FMAX_D
1093
15.6k
    4U, // FMAX_S
1094
15.6k
    4U, // FMIN_D
1095
15.6k
    4U, // FMIN_S
1096
15.6k
    100U, // FMSUB_D
1097
15.6k
    100U, // FMSUB_S
1098
15.6k
    36U,  // FMUL_D
1099
15.6k
    36U,  // FMUL_S
1100
15.6k
    0U, // FMV_D_X
1101
15.6k
    0U, // FMV_W_X
1102
15.6k
    0U, // FMV_X_D
1103
15.6k
    0U, // FMV_X_W
1104
15.6k
    100U, // FNMADD_D
1105
15.6k
    100U, // FNMADD_S
1106
15.6k
    100U, // FNMSUB_D
1107
15.6k
    100U, // FNMSUB_S
1108
15.6k
    13U,  // FSD
1109
15.6k
    4U, // FSGNJN_D
1110
15.6k
    4U, // FSGNJN_S
1111
15.6k
    4U, // FSGNJX_D
1112
15.6k
    4U, // FSGNJX_S
1113
15.6k
    4U, // FSGNJ_D
1114
15.6k
    4U, // FSGNJ_S
1115
15.6k
    20U,  // FSQRT_D
1116
15.6k
    20U,  // FSQRT_S
1117
15.6k
    36U,  // FSUB_D
1118
15.6k
    36U,  // FSUB_S
1119
15.6k
    13U,  // FSW
1120
15.6k
    0U, // JAL
1121
15.6k
    4U, // JALR
1122
15.6k
    13U,  // LB
1123
15.6k
    13U,  // LBU
1124
15.6k
    13U,  // LD
1125
15.6k
    13U,  // LH
1126
15.6k
    13U,  // LHU
1127
15.6k
    0U, // LR_D
1128
15.6k
    0U, // LR_D_AQ
1129
15.6k
    0U, // LR_D_AQ_RL
1130
15.6k
    0U, // LR_D_RL
1131
15.6k
    0U, // LR_W
1132
15.6k
    0U, // LR_W_AQ
1133
15.6k
    0U, // LR_W_AQ_RL
1134
15.6k
    0U, // LR_W_RL
1135
15.6k
    0U, // LUI
1136
15.6k
    13U,  // LW
1137
15.6k
    13U,  // LWU
1138
15.6k
    0U, // MRET
1139
15.6k
    4U, // MUL
1140
15.6k
    4U, // MULH
1141
15.6k
    4U, // MULHSU
1142
15.6k
    4U, // MULHU
1143
15.6k
    4U, // MULW
1144
15.6k
    4U, // OR
1145
15.6k
    4U, // ORI
1146
15.6k
    4U, // REM
1147
15.6k
    4U, // REMU
1148
15.6k
    4U, // REMUW
1149
15.6k
    4U, // REMW
1150
15.6k
    13U,  // SB
1151
15.6k
    9U, // SC_D
1152
15.6k
    9U, // SC_D_AQ
1153
15.6k
    9U, // SC_D_AQ_RL
1154
15.6k
    9U, // SC_D_RL
1155
15.6k
    9U, // SC_W
1156
15.6k
    9U, // SC_W_AQ
1157
15.6k
    9U, // SC_W_AQ_RL
1158
15.6k
    9U, // SC_W_RL
1159
15.6k
    13U,  // SD
1160
15.6k
    0U, // SFENCE_VMA
1161
15.6k
    13U,  // SH
1162
15.6k
    4U, // SLL
1163
15.6k
    4U, // SLLI
1164
15.6k
    4U, // SLLIW
1165
15.6k
    4U, // SLLW
1166
15.6k
    4U, // SLT
1167
15.6k
    4U, // SLTI
1168
15.6k
    4U, // SLTIU
1169
15.6k
    4U, // SLTU
1170
15.6k
    4U, // SRA
1171
15.6k
    4U, // SRAI
1172
15.6k
    4U, // SRAIW
1173
15.6k
    4U, // SRAW
1174
15.6k
    0U, // SRET
1175
15.6k
    4U, // SRL
1176
15.6k
    4U, // SRLI
1177
15.6k
    4U, // SRLIW
1178
15.6k
    4U, // SRLW
1179
15.6k
    4U, // SUB
1180
15.6k
    4U, // SUBW
1181
15.6k
    13U,  // SW
1182
15.6k
    0U, // UNIMP
1183
15.6k
    0U, // URET
1184
15.6k
    0U, // WFI
1185
15.6k
    4U, // XOR
1186
15.6k
    4U, // XORI
1187
15.6k
  };
1188
1189
  // Emit the opcode for the instruction.
1190
15.6k
  uint32_t Bits = 0;
1191
15.6k
  Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0;
1192
15.6k
  Bits |= OpInfo1[MCInst_getOpcode(MI)] << 16;
1193
15.6k
  CS_ASSERT(Bits != 0 && "Cannot print this instruction.");
1194
15.6k
#ifndef CAPSTONE_DIET
1195
15.6k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
1196
15.6k
#endif
1197
1198
1199
  // Fragment 0 encoded into 2 bits for 4 unique commands.
1200
15.6k
  switch ((Bits >> 12) & 3) {
1201
0
  default: CS_ASSERT(0 && "Invalid command number.");
1202
2
  case 0:
1203
    // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL...
1204
2
    return;
1205
0
    break;
1206
15.4k
  case 1:
1207
    // PseudoCALL, PseudoLA, PseudoLI, PseudoLLA, PseudoTAIL, ADD, ADDI, ADDI...
1208
15.4k
    printOperand(MI, 0, O);
1209
15.4k
    break;
1210
0
  case 2:
1211
    // C_ADD, C_ADDI, C_ADDI16SP, C_ADDIW, C_ADDW, C_AND, C_ANDI, C_OR, C_SLL...
1212
0
    printOperand(MI, 1, O);
1213
0
    SStream_concat0(O, ", ");
1214
0
    printOperand(MI, 2, O);
1215
0
    return;
1216
0
    break;
1217
185
  case 3:
1218
    // FENCE
1219
185
    printFenceArg(MI, 0, O);
1220
185
    SStream_concat0(O, ", ");
1221
185
    printFenceArg(MI, 1, O);
1222
185
    return;
1223
0
    break;
1224
15.6k
  }
1225
1226
1227
  // Fragment 1 encoded into 2 bits for 3 unique commands.
1228
15.4k
  switch ((Bits >> 14) & 3) {
1229
0
  default: CS_ASSERT(0 && "Invalid command number.");
1230
0
  case 0:
1231
    // PseudoCALL, PseudoTAIL, C_J, C_JAL, C_JALR, C_JR
1232
0
    return;
1233
0
    break;
1234
15.4k
  case 1:
1235
    // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AMOADD_D, AMOAD...
1236
15.4k
    SStream_concat0(O, ", ");
1237
15.4k
    break;
1238
3
  case 2:
1239
    // LR_D, LR_D_AQ, LR_D_AQ_RL, LR_D_RL, LR_W, LR_W_AQ, LR_W_AQ_RL, LR_W_RL
1240
3
    SStream_concat0(O, ", (");
1241
3
    printOperand(MI, 1, O);
1242
3
    SStream_concat0(O, ")");
1243
3
    return;
1244
0
    break;
1245
15.4k
  }
1246
1247
1248
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1249
15.4k
  switch ((Bits >> 16) & 3) {
1250
0
  default: CS_ASSERT(0 && "Invalid command number.");
1251
5.05k
  case 0:
1252
    // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AND, ANDI, AUIP...
1253
5.05k
    printOperand(MI, 1, O);
1254
5.05k
    break;
1255
452
  case 1:
1256
    // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W...
1257
452
    printOperand(MI, 2, O);
1258
452
    break;
1259
9.98k
  case 2:
1260
    // CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI
1261
9.98k
    printCSRSystemRegister(MI, 1, O);
1262
9.98k
    SStream_concat0(O, ", ");
1263
9.98k
    printOperand(MI, 2, O);
1264
9.98k
    return;
1265
0
    break;
1266
15.4k
  }
1267
1268
1269
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1270
5.50k
  switch ((Bits >> 18) & 3) {
1271
0
  default: CS_ASSERT(0 && "Invalid command number.");
1272
1.30k
  case 0:
1273
    // PseudoLA, PseudoLI, PseudoLLA, AUIPC, C_BEQZ, C_BNEZ, C_LI, C_LUI, C_M...
1274
1.30k
    return;
1275
0
    break;
1276
3.74k
  case 1:
1277
    // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A...
1278
3.74k
    SStream_concat0(O, ", ");
1279
3.74k
    break;
1280
7
  case 2:
1281
    // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W...
1282
7
    SStream_concat0(O, ", (");
1283
7
    printOperand(MI, 1, O);
1284
7
    SStream_concat0(O, ")");
1285
7
    return;
1286
0
    break;
1287
445
  case 3:
1288
    // C_FLD, C_FLDSP, C_FLW, C_FLWSP, C_FSD, C_FSDSP, C_FSW, C_FSWSP, C_LD, ...
1289
445
    SStream_concat0(O, "(");
1290
445
    printOperand(MI, 1, O);
1291
445
    SStream_concat0(O, ")");
1292
445
    return;
1293
0
    break;
1294
5.50k
  }
1295
1296
1297
  // Fragment 4 encoded into 1 bits for 2 unique commands.
1298
3.74k
  if ((Bits >> 20) & 1) {
1299
    // FCVT_D_L, FCVT_D_LU, FCVT_LU_D, FCVT_LU_S, FCVT_L_D, FCVT_L_S, FCVT_S_...
1300
410
    printFRMArg(MI, 2, O);
1301
410
    return;
1302
3.33k
  } else {
1303
    // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A...
1304
3.33k
    printOperand(MI, 2, O);
1305
3.33k
  }
1306
1307
1308
  // Fragment 5 encoded into 1 bits for 2 unique commands.
1309
3.33k
  if ((Bits >> 21) & 1) {
1310
    // FADD_D, FADD_S, FDIV_D, FDIV_S, FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FM...
1311
628
    SStream_concat0(O, ", ");
1312
2.70k
  } else {
1313
    // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A...
1314
2.70k
    return;
1315
2.70k
  }
1316
1317
1318
  // Fragment 6 encoded into 1 bits for 2 unique commands.
1319
628
  if ((Bits >> 22) & 1) {
1320
    // FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FNMADD_D, FNMADD_S, FNMSUB_D, FNMS...
1321
272
    printOperand(MI, 3, O);
1322
272
    SStream_concat0(O, ", ");
1323
272
    printFRMArg(MI, 4, O);
1324
272
    return;
1325
356
  } else {
1326
    // FADD_D, FADD_S, FDIV_D, FDIV_S, FMUL_D, FMUL_S, FSUB_D, FSUB_S
1327
356
    printFRMArg(MI, 3, O);
1328
356
    return;
1329
356
  }
1330
1331
628
}
1332
1333
1334
/// getRegisterName - This method is automatically generated by tblgen
1335
/// from the register set description.  This returns the assembler name
1336
/// for the specified register.
1337
static const char *
1338
getRegisterName(unsigned RegNo, unsigned AltIdx)
1339
39.6k
{
1340
39.6k
  CS_ASSERT(RegNo && RegNo < 97 && "Invalid register number!");
1341
1342
39.6k
#ifndef CAPSTONE_DIET
1343
39.6k
  static const char AsmStrsABIRegAltName[] = {
1344
39.6k
  /* 0 */ 'f', 's', '1', '0', 0,
1345
39.6k
  /* 5 */ 'f', 't', '1', '0', 0,
1346
39.6k
  /* 10 */ 'f', 'a', '0', 0,
1347
39.6k
  /* 14 */ 'f', 's', '0', 0,
1348
39.6k
  /* 18 */ 'f', 't', '0', 0,
1349
39.6k
  /* 22 */ 'f', 's', '1', '1', 0,
1350
39.6k
  /* 27 */ 'f', 't', '1', '1', 0,
1351
39.6k
  /* 32 */ 'f', 'a', '1', 0,
1352
39.6k
  /* 36 */ 'f', 's', '1', 0,
1353
39.6k
  /* 40 */ 'f', 't', '1', 0,
1354
39.6k
  /* 44 */ 'f', 'a', '2', 0,
1355
39.6k
  /* 48 */ 'f', 's', '2', 0,
1356
39.6k
  /* 52 */ 'f', 't', '2', 0,
1357
39.6k
  /* 56 */ 'f', 'a', '3', 0,
1358
39.6k
  /* 60 */ 'f', 's', '3', 0,
1359
39.6k
  /* 64 */ 'f', 't', '3', 0,
1360
39.6k
  /* 68 */ 'f', 'a', '4', 0,
1361
39.6k
  /* 72 */ 'f', 's', '4', 0,
1362
39.6k
  /* 76 */ 'f', 't', '4', 0,
1363
39.6k
  /* 80 */ 'f', 'a', '5', 0,
1364
39.6k
  /* 84 */ 'f', 's', '5', 0,
1365
39.6k
  /* 88 */ 'f', 't', '5', 0,
1366
39.6k
  /* 92 */ 'f', 'a', '6', 0,
1367
39.6k
  /* 96 */ 'f', 's', '6', 0,
1368
39.6k
  /* 100 */ 'f', 't', '6', 0,
1369
39.6k
  /* 104 */ 'f', 'a', '7', 0,
1370
39.6k
  /* 108 */ 'f', 's', '7', 0,
1371
39.6k
  /* 112 */ 'f', 't', '7', 0,
1372
39.6k
  /* 116 */ 'f', 's', '8', 0,
1373
39.6k
  /* 120 */ 'f', 't', '8', 0,
1374
39.6k
  /* 124 */ 'f', 's', '9', 0,
1375
39.6k
  /* 128 */ 'f', 't', '9', 0,
1376
39.6k
  /* 132 */ 'r', 'a', 0,
1377
39.6k
  /* 135 */ 'z', 'e', 'r', 'o', 0,
1378
39.6k
  /* 140 */ 'g', 'p', 0,
1379
39.6k
  /* 143 */ 's', 'p', 0,
1380
39.6k
  /* 146 */ 't', 'p', 0,
1381
39.6k
  };
1382
1383
39.6k
  static const uint8_t RegAsmOffsetABIRegAltName[] = {
1384
39.6k
    135, 132, 143, 140, 146, 19, 41, 53, 15, 37, 11, 33, 45, 57, 
1385
39.6k
    69, 81, 93, 105, 49, 61, 73, 85, 97, 109, 117, 125, 1, 23, 
1386
39.6k
    65, 77, 89, 101, 18, 18, 40, 40, 52, 52, 64, 64, 76, 76, 
1387
39.6k
    88, 88, 100, 100, 112, 112, 14, 14, 36, 36, 10, 10, 32, 32, 
1388
39.6k
    44, 44, 56, 56, 68, 68, 80, 80, 92, 92, 104, 104, 48, 48, 
1389
39.6k
    60, 60, 72, 72, 84, 84, 96, 96, 108, 108, 116, 116, 124, 124, 
1390
39.6k
    0, 0, 22, 22, 120, 120, 128, 128, 5, 5, 27, 27, 
1391
39.6k
  };
1392
1393
39.6k
  static const char AsmStrsNoRegAltName[] = {
1394
39.6k
  /* 0 */ 'f', '1', '0', 0,
1395
39.6k
  /* 4 */ 'x', '1', '0', 0,
1396
39.6k
  /* 8 */ 'f', '2', '0', 0,
1397
39.6k
  /* 12 */ 'x', '2', '0', 0,
1398
39.6k
  /* 16 */ 'f', '3', '0', 0,
1399
39.6k
  /* 20 */ 'x', '3', '0', 0,
1400
39.6k
  /* 24 */ 'f', '0', 0,
1401
39.6k
  /* 27 */ 'x', '0', 0,
1402
39.6k
  /* 30 */ 'f', '1', '1', 0,
1403
39.6k
  /* 34 */ 'x', '1', '1', 0,
1404
39.6k
  /* 38 */ 'f', '2', '1', 0,
1405
39.6k
  /* 42 */ 'x', '2', '1', 0,
1406
39.6k
  /* 46 */ 'f', '3', '1', 0,
1407
39.6k
  /* 50 */ 'x', '3', '1', 0,
1408
39.6k
  /* 54 */ 'f', '1', 0,
1409
39.6k
  /* 57 */ 'x', '1', 0,
1410
39.6k
  /* 60 */ 'f', '1', '2', 0,
1411
39.6k
  /* 64 */ 'x', '1', '2', 0,
1412
39.6k
  /* 68 */ 'f', '2', '2', 0,
1413
39.6k
  /* 72 */ 'x', '2', '2', 0,
1414
39.6k
  /* 76 */ 'f', '2', 0,
1415
39.6k
  /* 79 */ 'x', '2', 0,
1416
39.6k
  /* 82 */ 'f', '1', '3', 0,
1417
39.6k
  /* 86 */ 'x', '1', '3', 0,
1418
39.6k
  /* 90 */ 'f', '2', '3', 0,
1419
39.6k
  /* 94 */ 'x', '2', '3', 0,
1420
39.6k
  /* 98 */ 'f', '3', 0,
1421
39.6k
  /* 101 */ 'x', '3', 0,
1422
39.6k
  /* 104 */ 'f', '1', '4', 0,
1423
39.6k
  /* 108 */ 'x', '1', '4', 0,
1424
39.6k
  /* 112 */ 'f', '2', '4', 0,
1425
39.6k
  /* 116 */ 'x', '2', '4', 0,
1426
39.6k
  /* 120 */ 'f', '4', 0,
1427
39.6k
  /* 123 */ 'x', '4', 0,
1428
39.6k
  /* 126 */ 'f', '1', '5', 0,
1429
39.6k
  /* 130 */ 'x', '1', '5', 0,
1430
39.6k
  /* 134 */ 'f', '2', '5', 0,
1431
39.6k
  /* 138 */ 'x', '2', '5', 0,
1432
39.6k
  /* 142 */ 'f', '5', 0,
1433
39.6k
  /* 145 */ 'x', '5', 0,
1434
39.6k
  /* 148 */ 'f', '1', '6', 0,
1435
39.6k
  /* 152 */ 'x', '1', '6', 0,
1436
39.6k
  /* 156 */ 'f', '2', '6', 0,
1437
39.6k
  /* 160 */ 'x', '2', '6', 0,
1438
39.6k
  /* 164 */ 'f', '6', 0,
1439
39.6k
  /* 167 */ 'x', '6', 0,
1440
39.6k
  /* 170 */ 'f', '1', '7', 0,
1441
39.6k
  /* 174 */ 'x', '1', '7', 0,
1442
39.6k
  /* 178 */ 'f', '2', '7', 0,
1443
39.6k
  /* 182 */ 'x', '2', '7', 0,
1444
39.6k
  /* 186 */ 'f', '7', 0,
1445
39.6k
  /* 189 */ 'x', '7', 0,
1446
39.6k
  /* 192 */ 'f', '1', '8', 0,
1447
39.6k
  /* 196 */ 'x', '1', '8', 0,
1448
39.6k
  /* 200 */ 'f', '2', '8', 0,
1449
39.6k
  /* 204 */ 'x', '2', '8', 0,
1450
39.6k
  /* 208 */ 'f', '8', 0,
1451
39.6k
  /* 211 */ 'x', '8', 0,
1452
39.6k
  /* 214 */ 'f', '1', '9', 0,
1453
39.6k
  /* 218 */ 'x', '1', '9', 0,
1454
39.6k
  /* 222 */ 'f', '2', '9', 0,
1455
39.6k
  /* 226 */ 'x', '2', '9', 0,
1456
39.6k
  /* 230 */ 'f', '9', 0,
1457
39.6k
  /* 233 */ 'x', '9', 0,
1458
39.6k
  };
1459
1460
39.6k
  static const uint8_t RegAsmOffsetNoRegAltName[] = {
1461
39.6k
    27, 57, 79, 101, 123, 145, 167, 189, 211, 233, 4, 34, 64, 86, 
1462
39.6k
    108, 130, 152, 174, 196, 218, 12, 42, 72, 94, 116, 138, 160, 182, 
1463
39.6k
    204, 226, 20, 50, 24, 24, 54, 54, 76, 76, 98, 98, 120, 120, 
1464
39.6k
    142, 142, 164, 164, 186, 186, 208, 208, 230, 230, 0, 0, 30, 30, 
1465
39.6k
    60, 60, 82, 82, 104, 104, 126, 126, 148, 148, 170, 170, 192, 192, 
1466
39.6k
    214, 214, 8, 8, 38, 38, 68, 68, 90, 90, 112, 112, 134, 134, 
1467
39.6k
    156, 156, 178, 178, 200, 200, 222, 222, 16, 16, 46, 46, 
1468
39.6k
  };
1469
1470
39.6k
  switch(AltIdx) {
1471
0
  default: CS_ASSERT(0 && "Invalid register alt name index!");
1472
39.6k
  case RISCV_ABIRegAltName:
1473
39.6k
    CS_ASSERT(*(AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]) &&
1474
39.6k
           "Invalid alt name index for register!");
1475
39.6k
    return AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1];
1476
0
  case RISCV_NoRegAltName:
1477
0
    CS_ASSERT(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
1478
0
           "Invalid alt name index for register!");
1479
0
    return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
1480
39.6k
  }
1481
#else
1482
  return NULL;
1483
#endif
1484
39.6k
}
1485
1486
#ifdef PRINT_ALIAS_INSTR
1487
#undef PRINT_ALIAS_INSTR
1488
1489
static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp,
1490
                  unsigned PredicateIndex);
1491
1492
static bool printAliasInstr(MCInst *MI, SStream * OS, void *info)
1493
22.6k
{
1494
22.6k
  MCRegisterInfo *MRI = (MCRegisterInfo *) info;
1495
22.6k
  const char *AsmString;
1496
22.6k
  unsigned I = 0;
1497
22.6k
#define ASMSTRING_CONTAIN_SIZE 64
1498
22.6k
  unsigned AsmStringLen = 0;
1499
22.6k
  char tmpString_[ASMSTRING_CONTAIN_SIZE];
1500
22.6k
  char *tmpString = tmpString_;
1501
22.6k
  switch (MCInst_getOpcode(MI)) {
1502
937
  default: return false;
1503
231
  case RISCV_ADDI:
1504
231
    if (MCInst_getNumOperands(MI) == 3 &&
1505
231
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1506
231
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
1507
231
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1508
231
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
1509
      // (ADDI X0, X0, 0)
1510
26
      AsmString = "nop";
1511
26
      break;
1512
26
    }
1513
205
    if (MCInst_getNumOperands(MI) == 3 &&
1514
205
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1515
205
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1516
205
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1517
205
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1518
205
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1519
205
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
1520
      // (ADDI GPR:$rd, GPR:$rs, 0)
1521
66
      AsmString = "mv $\x01, $\x02";
1522
66
      break;
1523
66
    }
1524
139
    return false;
1525
64
  case RISCV_ADDIW:
1526
64
    if (MCInst_getNumOperands(MI) == 3 &&
1527
64
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1528
64
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1529
64
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1530
64
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1531
64
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1532
64
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
1533
      // (ADDIW GPR:$rd, GPR:$rs, 0)
1534
9
      AsmString = "sext.w $\x01, $\x02";
1535
9
      break;
1536
9
    }
1537
55
    return false;
1538
28
  case RISCV_BEQ:
1539
28
    if (MCInst_getNumOperands(MI) == 3 &&
1540
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1541
28
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1542
28
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
1543
28
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) {
1544
      // (BEQ GPR:$rs, X0, simm13_lsb0:$offset)
1545
0
      AsmString = "beqz $\x01, $\x03";
1546
0
      break;
1547
0
    }
1548
28
    return false;
1549
57
  case RISCV_BGE:
1550
57
    if (MCInst_getNumOperands(MI) == 3 &&
1551
57
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1552
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1553
57
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1554
57
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) {
1555
      // (BGE X0, GPR:$rs, simm13_lsb0:$offset)
1556
17
      AsmString = "blez $\x02, $\x03";
1557
17
      break;
1558
17
    }
1559
40
    if (MCInst_getNumOperands(MI) == 3 &&
1560
40
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1561
40
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1562
40
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
1563
40
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) {
1564
      // (BGE GPR:$rs, X0, simm13_lsb0:$offset)
1565
13
      AsmString = "bgez $\x01, $\x03";
1566
13
      break;
1567
13
    }
1568
27
    return false;
1569
144
  case RISCV_BLT:
1570
144
    if (MCInst_getNumOperands(MI) == 3 &&
1571
144
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1572
144
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1573
144
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
1574
144
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) {
1575
      // (BLT GPR:$rs, X0, simm13_lsb0:$offset)
1576
55
      AsmString = "bltz $\x01, $\x03";
1577
55
      break;
1578
55
    }
1579
89
    if (MCInst_getNumOperands(MI) == 3 &&
1580
89
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1581
89
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1582
89
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1583
89
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) {
1584
      // (BLT X0, GPR:$rs, simm13_lsb0:$offset)
1585
13
      AsmString = "bgtz $\x02, $\x03";
1586
13
      break;
1587
13
    }
1588
76
    return false;
1589
130
  case RISCV_BNE:
1590
130
    if (MCInst_getNumOperands(MI) == 3 &&
1591
130
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1592
130
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1593
130
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
1594
130
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) {
1595
      // (BNE GPR:$rs, X0, simm13_lsb0:$offset)
1596
59
      AsmString = "bnez $\x01, $\x03";
1597
59
      break;
1598
59
    }
1599
71
    return false;
1600
1.99k
  case RISCV_CSRRC:
1601
1.99k
    if (MCInst_getNumOperands(MI) == 3 &&
1602
1.99k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1603
1.99k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1604
1.99k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1605
      // (CSRRC X0, csr_sysreg:$csr, GPR:$rs)
1606
91
      AsmString = "csrc $\xFF\x02\x01, $\x03";
1607
91
      break;
1608
91
    }
1609
1.90k
    return false;
1610
2.76k
  case RISCV_CSRRCI:
1611
2.76k
    if (MCInst_getNumOperands(MI) == 3 &&
1612
2.76k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) {
1613
      // (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)
1614
431
      AsmString = "csrci $\xFF\x02\x01, $\x03";
1615
431
      break;
1616
431
    }
1617
2.32k
    return false;
1618
4.86k
  case RISCV_CSRRS:
1619
4.86k
    if (MCInst_getNumOperands(MI) == 3 &&
1620
4.86k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1621
4.86k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1622
4.86k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
4.86k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1624
4.86k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1625
      // (CSRRS GPR:$rd, 3, X0)
1626
14
      AsmString = "frcsr $\x01";
1627
14
      break;
1628
14
    }
1629
4.85k
    if (MCInst_getNumOperands(MI) == 3 &&
1630
4.85k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1631
4.85k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1632
4.85k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1633
4.85k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1634
4.85k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1635
      // (CSRRS GPR:$rd, 2, X0)
1636
2
      AsmString = "frrm $\x01";
1637
2
      break;
1638
2
    }
1639
4.85k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
4.85k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1641
4.85k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1642
4.85k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1643
4.85k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1644
4.85k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1645
      // (CSRRS GPR:$rd, 1, X0)
1646
14
      AsmString = "frflags $\x01";
1647
14
      break;
1648
14
    }
1649
4.83k
    if (MCInst_getNumOperands(MI) == 3 &&
1650
4.83k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1651
4.83k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1652
4.83k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1653
4.83k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3074 &&
1654
4.83k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1655
      // (CSRRS GPR:$rd, 3074, X0)
1656
11
      AsmString = "rdinstret $\x01";
1657
11
      break;
1658
11
    }
1659
4.82k
    if (MCInst_getNumOperands(MI) == 3 &&
1660
4.82k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1661
4.82k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1662
4.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1663
4.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3072 &&
1664
4.82k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1665
      // (CSRRS GPR:$rd, 3072, X0)
1666
7
      AsmString = "rdcycle $\x01";
1667
7
      break;
1668
7
    }
1669
4.82k
    if (MCInst_getNumOperands(MI) == 3 &&
1670
4.82k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1671
4.82k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1672
4.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1673
4.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3073 &&
1674
4.82k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1675
      // (CSRRS GPR:$rd, 3073, X0)
1676
1
      AsmString = "rdtime $\x01";
1677
1
      break;
1678
1
    }
1679
4.82k
    if (MCInst_getNumOperands(MI) == 3 &&
1680
4.82k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1681
4.82k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1682
4.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1683
4.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3202 &&
1684
4.82k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1685
      // (CSRRS GPR:$rd, 3202, X0)
1686
2
      AsmString = "rdinstreth $\x01";
1687
2
      break;
1688
2
    }
1689
4.81k
    if (MCInst_getNumOperands(MI) == 3 &&
1690
4.81k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1691
4.81k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1692
4.81k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1693
4.81k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3200 &&
1694
4.81k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1695
      // (CSRRS GPR:$rd, 3200, X0)
1696
19
      AsmString = "rdcycleh $\x01";
1697
19
      break;
1698
19
    }
1699
4.79k
    if (MCInst_getNumOperands(MI) == 3 &&
1700
4.79k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1701
4.79k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1702
4.79k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1703
4.79k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3201 &&
1704
4.79k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1705
      // (CSRRS GPR:$rd, 3201, X0)
1706
8
      AsmString = "rdtimeh $\x01";
1707
8
      break;
1708
8
    }
1709
4.79k
    if (MCInst_getNumOperands(MI) == 3 &&
1710
4.79k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1711
4.79k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1712
4.79k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
1713
      // (CSRRS GPR:$rd, csr_sysreg:$csr, X0)
1714
1.35k
      AsmString = "csrr $\x01, $\xFF\x02\x01";
1715
1.35k
      break;
1716
1.35k
    }
1717
3.43k
    if (MCInst_getNumOperands(MI) == 3 &&
1718
3.43k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1719
3.43k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1720
3.43k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1721
      // (CSRRS X0, csr_sysreg:$csr, GPR:$rs)
1722
87
      AsmString = "csrs $\xFF\x02\x01, $\x03";
1723
87
      break;
1724
87
    }
1725
3.34k
    return false;
1726
814
  case RISCV_CSRRSI:
1727
814
    if (MCInst_getNumOperands(MI) == 3 &&
1728
814
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) {
1729
      // (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)
1730
162
      AsmString = "csrsi $\xFF\x02\x01, $\x03";
1731
162
      break;
1732
162
    }
1733
652
    return false;
1734
1.72k
  case RISCV_CSRRW:
1735
1.72k
    if (MCInst_getNumOperands(MI) == 3 &&
1736
1.72k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1737
1.72k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1738
1.72k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1739
1.72k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1740
1.72k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1741
      // (CSRRW X0, 3, GPR:$rs)
1742
7
      AsmString = "fscsr $\x03";
1743
7
      break;
1744
7
    }
1745
1.71k
    if (MCInst_getNumOperands(MI) == 3 &&
1746
1.71k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1747
1.71k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1748
1.71k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1749
1.71k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1750
1.71k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1751
      // (CSRRW X0, 2, GPR:$rs)
1752
173
      AsmString = "fsrm $\x03";
1753
173
      break;
1754
173
    }
1755
1.54k
    if (MCInst_getNumOperands(MI) == 3 &&
1756
1.54k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1757
1.54k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
1.54k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1759
1.54k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1760
1.54k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1761
      // (CSRRW X0, 1, GPR:$rs)
1762
83
      AsmString = "fsflags $\x03";
1763
83
      break;
1764
83
    }
1765
1.45k
    if (MCInst_getNumOperands(MI) == 3 &&
1766
1.45k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1767
1.45k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1768
1.45k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1769
      // (CSRRW X0, csr_sysreg:$csr, GPR:$rs)
1770
467
      AsmString = "csrw $\xFF\x02\x01, $\x03";
1771
467
      break;
1772
467
    }
1773
991
    if (MCInst_getNumOperands(MI) == 3 &&
1774
991
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1775
991
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1776
991
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1777
991
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1778
991
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1779
991
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1780
      // (CSRRW GPR:$rd, 3, GPR:$rs)
1781
14
      AsmString = "fscsr $\x01, $\x03";
1782
14
      break;
1783
14
    }
1784
977
    if (MCInst_getNumOperands(MI) == 3 &&
1785
977
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1786
977
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1787
977
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1788
977
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1789
977
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1790
977
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1791
      // (CSRRW GPR:$rd, 2, GPR:$rs)
1792
49
      AsmString = "fsrm $\x01, $\x03";
1793
49
      break;
1794
49
    }
1795
928
    if (MCInst_getNumOperands(MI) == 3 &&
1796
928
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1797
928
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1798
928
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1799
928
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1800
928
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1801
928
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
1802
      // (CSRRW GPR:$rd, 1, GPR:$rs)
1803
1
      AsmString = "fsflags $\x01, $\x03";
1804
1
      break;
1805
1
    }
1806
927
    return false;
1807
941
  case RISCV_CSRRWI:
1808
941
    if (MCInst_getNumOperands(MI) == 3 &&
1809
941
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1810
941
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1811
941
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1812
      // (CSRRWI X0, 2, uimm5:$imm)
1813
7
      AsmString = "fsrmi $\x03";
1814
7
      break;
1815
7
    }
1816
934
    if (MCInst_getNumOperands(MI) == 3 &&
1817
934
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
1818
934
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1819
934
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1820
      // (CSRRWI X0, 1, uimm5:$imm)
1821
7
      AsmString = "fsflagsi $\x03";
1822
7
      break;
1823
7
    }
1824
927
    if (MCInst_getNumOperands(MI) == 3 &&
1825
927
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) {
1826
      // (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)
1827
23
      AsmString = "csrwi $\xFF\x02\x01, $\x03";
1828
23
      break;
1829
23
    }
1830
904
    if (MCInst_getNumOperands(MI) == 3 &&
1831
904
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1832
904
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1833
904
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1834
904
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1835
      // (CSRRWI GPR:$rd, 2, uimm5:$imm)
1836
74
      AsmString = "fsrmi $\x01, $\x03";
1837
74
      break;
1838
74
    }
1839
830
    if (MCInst_getNumOperands(MI) == 3 &&
1840
830
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1841
830
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1842
830
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1843
830
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1844
      // (CSRRWI GPR:$rd, 1, uimm5:$imm)
1845
8
      AsmString = "fsflagsi $\x01, $\x03";
1846
8
      break;
1847
8
    }
1848
822
    return false;
1849
54
  case RISCV_FADD_D:
1850
54
    if (MCInst_getNumOperands(MI) == 4 &&
1851
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1852
54
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1853
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1854
54
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1855
54
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1856
54
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
1857
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
1858
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
1859
      // (FADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 })
1860
17
      AsmString = "fadd.d $\x01, $\x02, $\x03";
1861
17
      break;
1862
17
    }
1863
37
    return false;
1864
69
  case RISCV_FADD_S:
1865
69
    if (MCInst_getNumOperands(MI) == 4 &&
1866
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1867
69
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1868
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1869
69
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1870
69
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1871
69
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
1872
69
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
1873
69
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
1874
      // (FADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 })
1875
7
      AsmString = "fadd.s $\x01, $\x02, $\x03";
1876
7
      break;
1877
7
    }
1878
62
    return false;
1879
42
  case RISCV_FCVT_D_L:
1880
42
    if (MCInst_getNumOperands(MI) == 3 &&
1881
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1882
42
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1883
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1884
42
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1885
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1886
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1887
      // (FCVT_D_L FPR64:$rd, GPR:$rs1, { 1, 1, 1 })
1888
5
      AsmString = "fcvt.d.l $\x01, $\x02";
1889
5
      break;
1890
5
    }
1891
37
    return false;
1892
60
  case RISCV_FCVT_D_LU:
1893
60
    if (MCInst_getNumOperands(MI) == 3 &&
1894
60
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1895
60
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1896
60
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1897
60
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1898
60
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1899
60
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1900
      // (FCVT_D_LU FPR64:$rd, GPR:$rs1, { 1, 1, 1 })
1901
59
      AsmString = "fcvt.d.lu $\x01, $\x02";
1902
59
      break;
1903
59
    }
1904
1
    return false;
1905
130
  case RISCV_FCVT_LU_D:
1906
130
    if (MCInst_getNumOperands(MI) == 3 &&
1907
130
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1908
130
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1909
130
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1910
130
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1911
130
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1912
130
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1913
      // (FCVT_LU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 })
1914
97
      AsmString = "fcvt.lu.d $\x01, $\x02";
1915
97
      break;
1916
97
    }
1917
33
    return false;
1918
25
  case RISCV_FCVT_LU_S:
1919
25
    if (MCInst_getNumOperands(MI) == 3 &&
1920
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1921
25
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1922
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1923
25
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1924
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1925
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1926
      // (FCVT_LU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 })
1927
11
      AsmString = "fcvt.lu.s $\x01, $\x02";
1928
11
      break;
1929
11
    }
1930
14
    return false;
1931
203
  case RISCV_FCVT_L_D:
1932
203
    if (MCInst_getNumOperands(MI) == 3 &&
1933
203
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1934
203
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1935
203
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1936
203
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1937
203
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1938
203
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1939
      // (FCVT_L_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 })
1940
184
      AsmString = "fcvt.l.d $\x01, $\x02";
1941
184
      break;
1942
184
    }
1943
19
    return false;
1944
22
  case RISCV_FCVT_L_S:
1945
22
    if (MCInst_getNumOperands(MI) == 3 &&
1946
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1947
22
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1948
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1949
22
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1950
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1951
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1952
      // (FCVT_L_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 })
1953
4
      AsmString = "fcvt.l.s $\x01, $\x02";
1954
4
      break;
1955
4
    }
1956
18
    return false;
1957
26
  case RISCV_FCVT_S_D:
1958
26
    if (MCInst_getNumOperands(MI) == 3 &&
1959
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1960
26
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1961
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1962
26
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1963
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1964
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1965
      // (FCVT_S_D FPR32:$rd, FPR64:$rs1, { 1, 1, 1 })
1966
5
      AsmString = "fcvt.s.d $\x01, $\x02";
1967
5
      break;
1968
5
    }
1969
21
    return false;
1970
40
  case RISCV_FCVT_S_L:
1971
40
    if (MCInst_getNumOperands(MI) == 3 &&
1972
40
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1973
40
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1974
40
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1975
40
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1976
40
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1977
40
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1978
      // (FCVT_S_L FPR32:$rd, GPR:$rs1, { 1, 1, 1 })
1979
6
      AsmString = "fcvt.s.l $\x01, $\x02";
1980
6
      break;
1981
6
    }
1982
34
    return false;
1983
17
  case RISCV_FCVT_S_LU:
1984
17
    if (MCInst_getNumOperands(MI) == 3 &&
1985
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1986
17
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1987
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
1988
17
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
1989
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
1990
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
1991
      // (FCVT_S_LU FPR32:$rd, GPR:$rs1, { 1, 1, 1 })
1992
3
      AsmString = "fcvt.s.lu $\x01, $\x02";
1993
3
      break;
1994
3
    }
1995
14
    return false;
1996
22
  case RISCV_FCVT_S_W:
1997
22
    if (MCInst_getNumOperands(MI) == 3 &&
1998
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
1999
22
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2000
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2001
22
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2002
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2003
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2004
      // (FCVT_S_W FPR32:$rd, GPR:$rs1, { 1, 1, 1 })
2005
6
      AsmString = "fcvt.s.w $\x01, $\x02";
2006
6
      break;
2007
6
    }
2008
16
    return false;
2009
21
  case RISCV_FCVT_S_WU:
2010
21
    if (MCInst_getNumOperands(MI) == 3 &&
2011
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2012
21
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2013
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2014
21
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2015
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2016
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2017
      // (FCVT_S_WU FPR32:$rd, GPR:$rs1, { 1, 1, 1 })
2018
12
      AsmString = "fcvt.s.wu $\x01, $\x02";
2019
12
      break;
2020
12
    }
2021
9
    return false;
2022
19
  case RISCV_FCVT_WU_D:
2023
19
    if (MCInst_getNumOperands(MI) == 3 &&
2024
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2025
19
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2026
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2027
19
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2028
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2029
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2030
      // (FCVT_WU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 })
2031
5
      AsmString = "fcvt.wu.d $\x01, $\x02";
2032
5
      break;
2033
5
    }
2034
14
    return false;
2035
93
  case RISCV_FCVT_WU_S:
2036
93
    if (MCInst_getNumOperands(MI) == 3 &&
2037
93
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2038
93
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2039
93
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2040
93
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2041
93
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2042
93
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2043
      // (FCVT_WU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 })
2044
12
      AsmString = "fcvt.wu.s $\x01, $\x02";
2045
12
      break;
2046
12
    }
2047
81
    return false;
2048
21
  case RISCV_FCVT_W_D:
2049
21
    if (MCInst_getNumOperands(MI) == 3 &&
2050
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2051
21
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2052
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2053
21
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2054
21
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2055
21
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2056
      // (FCVT_W_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 })
2057
0
      AsmString = "fcvt.w.d $\x01, $\x02";
2058
0
      break;
2059
0
    }
2060
21
    return false;
2061
157
  case RISCV_FCVT_W_S:
2062
157
    if (MCInst_getNumOperands(MI) == 3 &&
2063
157
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2064
157
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2065
157
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2066
157
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2067
157
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2068
157
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2069
      // (FCVT_W_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 })
2070
143
      AsmString = "fcvt.w.s $\x01, $\x02";
2071
143
      break;
2072
143
    }
2073
14
    return false;
2074
133
  case RISCV_FDIV_D:
2075
133
    if (MCInst_getNumOperands(MI) == 4 &&
2076
133
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2077
133
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2078
133
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2079
133
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2080
133
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2081
133
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2082
133
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
2083
133
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
2084
      // (FDIV_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 })
2085
92
      AsmString = "fdiv.d $\x01, $\x02, $\x03";
2086
92
      break;
2087
92
    }
2088
41
    return false;
2089
19
  case RISCV_FDIV_S:
2090
19
    if (MCInst_getNumOperands(MI) == 4 &&
2091
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2092
19
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2093
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2094
19
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2095
19
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2096
19
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2097
19
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
2098
19
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
2099
      // (FDIV_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 })
2100
10
      AsmString = "fdiv.s $\x01, $\x02, $\x03";
2101
10
      break;
2102
10
    }
2103
9
    return false;
2104
192
  case RISCV_FENCE:
2105
192
    if (MCInst_getNumOperands(MI) == 2 &&
2106
192
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
2107
192
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 &&
2108
192
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2109
192
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2110
      // (FENCE 15, 15)
2111
7
      AsmString = "fence";
2112
7
      break;
2113
7
    }
2114
185
    return false;
2115
141
  case RISCV_FMADD_D:
2116
141
    if (MCInst_getNumOperands(MI) == 5 &&
2117
141
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2118
141
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2119
141
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2120
141
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2121
141
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2122
141
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2123
141
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2124
141
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2125
141
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2126
141
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2127
      // (FMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 })
2128
121
      AsmString = "fmadd.d $\x01, $\x02, $\x03, $\x04";
2129
121
      break;
2130
121
    }
2131
20
    return false;
2132
64
  case RISCV_FMADD_S:
2133
64
    if (MCInst_getNumOperands(MI) == 5 &&
2134
64
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2135
64
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2136
64
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2137
64
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2138
64
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2139
64
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2140
64
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2141
64
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2142
64
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2143
64
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2144
      // (FMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 })
2145
13
      AsmString = "fmadd.s $\x01, $\x02, $\x03, $\x04";
2146
13
      break;
2147
13
    }
2148
51
    return false;
2149
40
  case RISCV_FMSUB_D:
2150
40
    if (MCInst_getNumOperands(MI) == 5 &&
2151
40
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2152
40
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2153
40
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2154
40
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2155
40
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2156
40
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2157
40
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2158
40
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2159
40
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2160
40
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2161
      // (FMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 })
2162
31
      AsmString = "fmsub.d $\x01, $\x02, $\x03, $\x04";
2163
31
      break;
2164
31
    }
2165
9
    return false;
2166
28
  case RISCV_FMSUB_S:
2167
28
    if (MCInst_getNumOperands(MI) == 5 &&
2168
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2169
28
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2170
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2171
28
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2172
28
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2173
28
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2174
28
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2175
28
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2176
28
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2177
28
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2178
      // (FMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 })
2179
21
      AsmString = "fmsub.s $\x01, $\x02, $\x03, $\x04";
2180
21
      break;
2181
21
    }
2182
7
    return false;
2183
20
  case RISCV_FMUL_D:
2184
20
    if (MCInst_getNumOperands(MI) == 4 &&
2185
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2186
20
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2187
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2188
20
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2189
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2190
20
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2191
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
2192
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
2193
      // (FMUL_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 })
2194
5
      AsmString = "fmul.d $\x01, $\x02, $\x03";
2195
5
      break;
2196
5
    }
2197
15
    return false;
2198
64
  case RISCV_FMUL_S:
2199
64
    if (MCInst_getNumOperands(MI) == 4 &&
2200
64
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2201
64
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2202
64
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2203
64
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2204
64
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2205
64
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2206
64
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
2207
64
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
2208
      // (FMUL_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 })
2209
34
      AsmString = "fmul.s $\x01, $\x02, $\x03";
2210
34
      break;
2211
34
    }
2212
30
    return false;
2213
625
  case RISCV_FNMADD_D:
2214
625
    if (MCInst_getNumOperands(MI) == 5 &&
2215
625
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2216
625
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2217
625
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2218
625
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2219
625
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2220
625
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2221
625
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2222
625
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2223
625
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2224
625
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2225
      // (FNMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 })
2226
510
      AsmString = "fnmadd.d $\x01, $\x02, $\x03, $\x04";
2227
510
      break;
2228
510
    }
2229
115
    return false;
2230
64
  case RISCV_FNMADD_S:
2231
64
    if (MCInst_getNumOperands(MI) == 5 &&
2232
64
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2233
64
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2234
64
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2235
64
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2236
64
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2237
64
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2238
64
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2239
64
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2240
64
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2241
64
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2242
      // (FNMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 })
2243
7
      AsmString = "fnmadd.s $\x01, $\x02, $\x03, $\x04";
2244
7
      break;
2245
7
    }
2246
57
    return false;
2247
16
  case RISCV_FNMSUB_D:
2248
16
    if (MCInst_getNumOperands(MI) == 5 &&
2249
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2250
16
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2251
16
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2252
16
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2253
16
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2254
16
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2255
16
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2256
16
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2257
16
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2258
16
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2259
      // (FNMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 })
2260
8
      AsmString = "fnmsub.d $\x01, $\x02, $\x03, $\x04";
2261
8
      break;
2262
8
    }
2263
8
    return false;
2264
7
  case RISCV_FNMSUB_S:
2265
7
    if (MCInst_getNumOperands(MI) == 5 &&
2266
7
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2267
7
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2268
7
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2269
7
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2270
7
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2271
7
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2272
7
        MCOperand_isReg(MCInst_getOperand(MI, 3)) &&
2273
7
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) &&
2274
7
        MCOperand_isImm(MCInst_getOperand(MI, 4)) &&
2275
7
        MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) {
2276
      // (FNMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 })
2277
2
      AsmString = "fnmsub.s $\x01, $\x02, $\x03, $\x04";
2278
2
      break;
2279
2
    }
2280
5
    return false;
2281
425
  case RISCV_FSGNJN_D:
2282
425
    if (MCInst_getNumOperands(MI) == 3 &&
2283
425
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
425
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2285
425
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
425
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2287
425
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2288
425
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
2289
      // (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)
2290
252
      AsmString = "fneg.d $\x01, $\x02";
2291
252
      break;
2292
252
    }
2293
173
    return false;
2294
1.01k
  case RISCV_FSGNJN_S:
2295
1.01k
    if (MCInst_getNumOperands(MI) == 3 &&
2296
1.01k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2297
1.01k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2298
1.01k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2299
1.01k
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2300
1.01k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2301
1.01k
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
2302
      // (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)
2303
175
      AsmString = "fneg.s $\x01, $\x02";
2304
175
      break;
2305
175
    }
2306
839
    return false;
2307
278
  case RISCV_FSGNJX_D:
2308
278
    if (MCInst_getNumOperands(MI) == 3 &&
2309
278
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2310
278
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2311
278
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2312
278
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2313
278
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2314
278
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
2315
      // (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)
2316
233
      AsmString = "fabs.d $\x01, $\x02";
2317
233
      break;
2318
233
    }
2319
45
    return false;
2320
772
  case RISCV_FSGNJX_S:
2321
772
    if (MCInst_getNumOperands(MI) == 3 &&
2322
772
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2323
772
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2324
772
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2325
772
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2326
772
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2327
772
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
2328
      // (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)
2329
569
      AsmString = "fabs.s $\x01, $\x02";
2330
569
      break;
2331
569
    }
2332
203
    return false;
2333
26
  case RISCV_FSGNJ_D:
2334
26
    if (MCInst_getNumOperands(MI) == 3 &&
2335
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2336
26
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2337
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2338
26
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2339
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2340
26
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
2341
      // (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)
2342
21
      AsmString = "fmv.d $\x01, $\x02";
2343
21
      break;
2344
21
    }
2345
5
    return false;
2346
145
  case RISCV_FSGNJ_S:
2347
145
    if (MCInst_getNumOperands(MI) == 3 &&
2348
145
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2349
145
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2350
145
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2351
145
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2352
145
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2353
145
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) {
2354
      // (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)
2355
47
      AsmString = "fmv.s $\x01, $\x02";
2356
47
      break;
2357
47
    }
2358
98
    return false;
2359
25
  case RISCV_FSQRT_D:
2360
25
    if (MCInst_getNumOperands(MI) == 3 &&
2361
25
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2362
25
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2363
25
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2364
25
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2365
25
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2366
25
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2367
      // (FSQRT_D FPR64:$rd, FPR64:$rs1, { 1, 1, 1 })
2368
18
      AsmString = "fsqrt.d $\x01, $\x02";
2369
18
      break;
2370
18
    }
2371
7
    return false;
2372
69
  case RISCV_FSQRT_S:
2373
69
    if (MCInst_getNumOperands(MI) == 3 &&
2374
69
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2375
69
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2376
69
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2377
69
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2378
69
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2379
69
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2380
      // (FSQRT_S FPR32:$rd, FPR32:$rs1, { 1, 1, 1 })
2381
12
      AsmString = "fsqrt.s $\x01, $\x02";
2382
12
      break;
2383
12
    }
2384
57
    return false;
2385
230
  case RISCV_FSUB_D:
2386
230
    if (MCInst_getNumOperands(MI) == 4 &&
2387
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2388
230
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2389
230
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2390
230
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2391
230
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2392
230
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2393
230
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
2394
230
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
2395
      // (FSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 })
2396
75
      AsmString = "fsub.d $\x01, $\x02, $\x03";
2397
75
      break;
2398
75
    }
2399
155
    return false;
2400
49
  case RISCV_FSUB_S:
2401
49
    if (MCInst_getNumOperands(MI) == 4 &&
2402
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2403
49
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2404
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2405
49
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2406
49
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2407
49
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) &&
2408
49
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
2409
49
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
2410
      // (FSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 })
2411
42
      AsmString = "fsub.s $\x01, $\x02, $\x03";
2412
42
      break;
2413
42
    }
2414
7
    return false;
2415
974
  case RISCV_JAL:
2416
974
    if (MCInst_getNumOperands(MI) == 2 &&
2417
974
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
2418
974
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2)) {
2419
      // (JAL X0, simm21_lsb0_jal:$offset)
2420
123
      AsmString = "j $\x02";
2421
123
      break;
2422
123
    }
2423
851
    if (MCInst_getNumOperands(MI) == 2 &&
2424
851
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1 &&
2425
851
        RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2)) {
2426
      // (JAL X1, simm21_lsb0_jal:$offset)
2427
109
      AsmString = "jal $\x02";
2428
109
      break;
2429
109
    }
2430
742
    return false;
2431
546
  case RISCV_JALR:
2432
546
    if (MCInst_getNumOperands(MI) == 3 &&
2433
546
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
2434
546
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X1 &&
2435
546
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2436
546
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2437
      // (JALR X0, X1, 0)
2438
126
      AsmString = "ret";
2439
126
      break;
2440
126
    }
2441
420
    if (MCInst_getNumOperands(MI) == 3 &&
2442
420
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
2443
420
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2444
420
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2445
420
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2446
420
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2447
      // (JALR X0, GPR:$rs, 0)
2448
37
      AsmString = "jr $\x02";
2449
37
      break;
2450
37
    }
2451
383
    if (MCInst_getNumOperands(MI) == 3 &&
2452
383
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1 &&
2453
383
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2454
383
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2455
383
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2456
383
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2457
      // (JALR X1, GPR:$rs, 0)
2458
5
      AsmString = "jalr $\x02";
2459
5
      break;
2460
5
    }
2461
378
    return false;
2462
528
  case RISCV_SFENCE_VMA:
2463
528
    if (MCInst_getNumOperands(MI) == 2 &&
2464
528
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 &&
2465
528
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) {
2466
      // (SFENCE_VMA X0, X0)
2467
5
      AsmString = "sfence.vma";
2468
5
      break;
2469
5
    }
2470
523
    if (MCInst_getNumOperands(MI) == 2 &&
2471
523
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2472
523
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2473
523
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) {
2474
      // (SFENCE_VMA GPR:$rs, X0)
2475
44
      AsmString = "sfence.vma $\x01";
2476
44
      break;
2477
44
    }
2478
479
    return false;
2479
124
  case RISCV_SLT:
2480
124
    if (MCInst_getNumOperands(MI) == 3 &&
2481
124
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2482
124
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2483
124
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2484
124
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2485
124
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) {
2486
      // (SLT GPR:$rd, GPR:$rs, X0)
2487
46
      AsmString = "sltz $\x01, $\x02";
2488
46
      break;
2489
46
    }
2490
78
    if (MCInst_getNumOperands(MI) == 3 &&
2491
78
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2492
78
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2493
78
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
2494
78
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2495
78
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
2496
      // (SLT GPR:$rd, X0, GPR:$rs)
2497
61
      AsmString = "sgtz $\x01, $\x03";
2498
61
      break;
2499
61
    }
2500
17
    return false;
2501
85
  case RISCV_SLTIU:
2502
85
    if (MCInst_getNumOperands(MI) == 3 &&
2503
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2504
85
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2505
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2506
85
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2507
85
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2508
85
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2509
      // (SLTIU GPR:$rd, GPR:$rs, 1)
2510
21
      AsmString = "seqz $\x01, $\x02";
2511
21
      break;
2512
21
    }
2513
64
    return false;
2514
65
  case RISCV_SLTU:
2515
65
    if (MCInst_getNumOperands(MI) == 3 &&
2516
65
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
65
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2518
65
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
2519
65
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2520
65
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
2521
      // (SLTU GPR:$rd, X0, GPR:$rs)
2522
48
      AsmString = "snez $\x01, $\x03";
2523
48
      break;
2524
48
    }
2525
17
    return false;
2526
9
  case RISCV_SUB:
2527
9
    if (MCInst_getNumOperands(MI) == 3 &&
2528
9
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2529
9
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2530
9
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
2531
9
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2532
9
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
2533
      // (SUB GPR:$rd, X0, GPR:$rs)
2534
0
      AsmString = "neg $\x01, $\x03";
2535
0
      break;
2536
0
    }
2537
9
    return false;
2538
11
  case RISCV_SUBW:
2539
11
    if (MCInst_getNumOperands(MI) == 3 &&
2540
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2541
11
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2542
11
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 &&
2543
11
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
2544
11
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
2545
      // (SUBW GPR:$rd, X0, GPR:$rs)
2546
8
      AsmString = "negw $\x01, $\x03";
2547
8
      break;
2548
8
    }
2549
3
    return false;
2550
124
  case RISCV_XORI:
2551
124
    if (MCInst_getNumOperands(MI) == 3 &&
2552
124
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2553
124
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2554
124
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2555
124
        MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) &&
2556
124
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2557
124
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1) {
2558
      // (XORI GPR:$rd, GPR:$rs, -1)
2559
58
      AsmString = "not $\x01, $\x02";
2560
58
      break;
2561
58
    }
2562
66
    return false;
2563
22.6k
  }
2564
2565
6.94k
  AsmStringLen = strlen(AsmString);
2566
6.94k
  if (ASMSTRING_CONTAIN_SIZE - 1 < AsmStringLen)
2567
0
    tmpString = cs_strdup(AsmString);
2568
6.94k
  else
2569
6.94k
    tmpString = memcpy(tmpString, AsmString, 1 + AsmStringLen);
2570
2571
43.6k
  while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
2572
43.6k
         AsmString[I] != '$' && AsmString[I] != '\0')
2573
36.7k
    ++I;
2574
6.94k
  tmpString[I] = 0;
2575
6.94k
  SStream_concat0(OS, tmpString);
2576
6.94k
  if (ASMSTRING_CONTAIN_SIZE - 1 < AsmStringLen)
2577
    /* Free the possible cs_strdup() memory. PR#1424. */
2578
0
    cs_mem_free(tmpString);
2579
6.94k
#undef ASMSTRING_CONTAIN_SIZE
2580
2581
6.94k
  if (AsmString[I] != '\0') {
2582
6.78k
    if (AsmString[I] == ' ' || AsmString[I] == '\t') {
2583
6.78k
      SStream_concat0(OS, " ");
2584
6.78k
      ++I;
2585
6.78k
    }
2586
30.2k
    do {
2587
30.2k
      if (AsmString[I] == '$') {
2588
14.6k
        ++I;
2589
14.6k
        if (AsmString[I] == (char)0xff) {
2590
2.61k
          ++I;
2591
2.61k
          int OpIdx = AsmString[I++] - 1;
2592
2.61k
          int PrintMethodIdx = AsmString[I++] - 1;
2593
2.61k
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
2594
2.61k
        } else
2595
11.9k
          printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS);
2596
15.6k
      } else {
2597
15.6k
        SStream_concat1(OS, AsmString[I++]);
2598
15.6k
      }
2599
30.2k
    } while (AsmString[I] != '\0');
2600
6.78k
  }
2601
2602
6.94k
  return true;
2603
22.6k
}
2604
2605
static void printCustomAliasOperand(
2606
         MCInst *MI, unsigned OpIdx,
2607
         unsigned PrintMethodIdx,
2608
2.61k
         SStream *OS) {
2609
2.61k
  switch (PrintMethodIdx) {
2610
0
  default:
2611
0
    CS_ASSERT(0 && "Unknown PrintMethod kind");
2612
0
    break;
2613
2.61k
  case 0:
2614
2.61k
    printCSRSystemRegister(MI, OpIdx, OS);
2615
2.61k
    break;
2616
2.61k
  }
2617
2.61k
}
2618
2619
static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp,
2620
389
                  unsigned PredicateIndex) {
2621
  // TODO: need some constant untils operate the MCOperand,
2622
  // but current CAPSTONE does't have.
2623
  // So, We just return true
2624
389
  return true;
2625
2626
#if 0
2627
  switch (PredicateIndex) {
2628
  default:
2629
    llvm_unreachable("Unknown MCOperandPredicate kind");
2630
    break;
2631
  case 1: {
2632
2633
    int64_t Imm;
2634
    if (MCOp.evaluateAsConstantImm(Imm))
2635
      return isShiftedInt<12, 1>(Imm);
2636
    return MCOp.isBareSymbolRef();
2637
  
2638
    }
2639
  case 2: {
2640
2641
    int64_t Imm;
2642
    if (MCOp.evaluateAsConstantImm(Imm))
2643
      return isShiftedInt<20, 1>(Imm);
2644
    return MCOp.isBareSymbolRef();
2645
  
2646
    }
2647
  }
2648
#endif
2649
389
}
2650
2651
#endif // PRINT_ALIAS_INSTR