Coverage Report

Created: 2023-09-25 06:24

/src/capstonev5/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|*Assembly Writer Source Fragment                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
15
16
/// printInstruction - This method is automatically generated by tablegen
17
/// from the instruction set description.
18
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19
15.3k
{
20
15.3k
  static const uint32_t OpInfo[] = {
21
15.3k
    0U, // PHI
22
15.3k
    0U, // INLINEASM
23
15.3k
    0U, // CFI_INSTRUCTION
24
15.3k
    0U, // EH_LABEL
25
15.3k
    0U, // GC_LABEL
26
15.3k
    0U, // KILL
27
15.3k
    0U, // EXTRACT_SUBREG
28
15.3k
    0U, // INSERT_SUBREG
29
15.3k
    0U, // IMPLICIT_DEF
30
15.3k
    0U, // SUBREG_TO_REG
31
15.3k
    0U, // COPY_TO_REGCLASS
32
15.3k
    2452U,  // DBG_VALUE
33
15.3k
    0U, // REG_SEQUENCE
34
15.3k
    0U, // COPY
35
15.3k
    2445U,  // BUNDLE
36
15.3k
    2462U,  // LIFETIME_START
37
15.3k
    2432U,  // LIFETIME_END
38
15.3k
    0U, // STACKMAP
39
15.3k
    0U, // PATCHPOINT
40
15.3k
    0U, // LOAD_STACK_GUARD
41
15.3k
    0U, // STATEPOINT
42
15.3k
    0U, // FRAME_ALLOC
43
15.3k
    4688U,  // ADDCCri
44
15.3k
    4688U,  // ADDCCrr
45
15.3k
    5925U,  // ADDCri
46
15.3k
    5925U,  // ADDCrr
47
15.3k
    4772U,  // ADDEri
48
15.3k
    4772U,  // ADDErr
49
15.3k
    4786U,  // ADDXC
50
15.3k
    4678U,  // ADDXCCC
51
15.3k
    4808U,  // ADDXri
52
15.3k
    4808U,  // ADDXrr
53
15.3k
    4808U,  // ADDri
54
15.3k
    4808U,  // ADDrr
55
15.3k
    74166U, // ADJCALLSTACKDOWN
56
15.3k
    74185U, // ADJCALLSTACKUP
57
15.3k
    5497U,  // ALIGNADDR
58
15.3k
    5127U,  // ALIGNADDRL
59
15.3k
    4695U,  // ANDCCri
60
15.3k
    4695U,  // ANDCCrr
61
15.3k
    4718U,  // ANDNCCri
62
15.3k
    4718U,  // ANDNCCrr
63
15.3k
    5182U,  // ANDNri
64
15.3k
    5182U,  // ANDNrr
65
15.3k
    5182U,  // ANDXNrr
66
15.3k
    4876U,  // ANDXri
67
15.3k
    4876U,  // ANDXrr
68
15.3k
    4876U,  // ANDri
69
15.3k
    4876U,  // ANDrr
70
15.3k
    4502U,  // ARRAY16
71
15.3k
    4255U,  // ARRAY32
72
15.3k
    4526U,  // ARRAY8
73
15.3k
    0U, // ATOMIC_LOAD_ADD_32
74
15.3k
    0U, // ATOMIC_LOAD_ADD_64
75
15.3k
    0U, // ATOMIC_LOAD_AND_32
76
15.3k
    0U, // ATOMIC_LOAD_AND_64
77
15.3k
    0U, // ATOMIC_LOAD_MAX_32
78
15.3k
    0U, // ATOMIC_LOAD_MAX_64
79
15.3k
    0U, // ATOMIC_LOAD_MIN_32
80
15.3k
    0U, // ATOMIC_LOAD_MIN_64
81
15.3k
    0U, // ATOMIC_LOAD_NAND_32
82
15.3k
    0U, // ATOMIC_LOAD_NAND_64
83
15.3k
    0U, // ATOMIC_LOAD_OR_32
84
15.3k
    0U, // ATOMIC_LOAD_OR_64
85
15.3k
    0U, // ATOMIC_LOAD_SUB_32
86
15.3k
    0U, // ATOMIC_LOAD_SUB_64
87
15.3k
    0U, // ATOMIC_LOAD_UMAX_32
88
15.3k
    0U, // ATOMIC_LOAD_UMAX_64
89
15.3k
    0U, // ATOMIC_LOAD_UMIN_32
90
15.3k
    0U, // ATOMIC_LOAD_UMIN_64
91
15.3k
    0U, // ATOMIC_LOAD_XOR_32
92
15.3k
    0U, // ATOMIC_LOAD_XOR_64
93
15.3k
    0U, // ATOMIC_SWAP_64
94
15.3k
    74271U, // BA
95
15.3k
    1194492U, // BCOND
96
15.3k
    1260028U, // BCONDA
97
15.3k
    17659U, // BINDri
98
15.3k
    17659U, // BINDrr
99
15.3k
    5065U,  // BMASK
100
15.3k
    145915U,  // BPFCC
101
15.3k
    211451U,  // BPFCCA
102
15.3k
    276987U,  // BPFCCANT
103
15.3k
    342523U,  // BPFCCNT
104
15.3k
    2106465U, // BPGEZapn
105
15.3k
    2105838U, // BPGEZapt
106
15.3k
    2106532U, // BPGEZnapn
107
15.3k
    2107288U, // BPGEZnapt
108
15.3k
    2106489U, // BPGZapn
109
15.3k
    2105856U, // BPGZapt
110
15.3k
    2106552U, // BPGZnapn
111
15.3k
    2107384U, // BPGZnapt
112
15.3k
    1456636U, // BPICC
113
15.3k
    473596U,  // BPICCA
114
15.3k
    539132U,  // BPICCANT
115
15.3k
    604668U,  // BPICCNT
116
15.3k
    2106477U, // BPLEZapn
117
15.3k
    2105847U, // BPLEZapt
118
15.3k
    2106542U, // BPLEZnapn
119
15.3k
    2107337U, // BPLEZnapt
120
15.3k
    2106500U, // BPLZapn
121
15.3k
    2105864U, // BPLZapt
122
15.3k
    2106561U, // BPLZnapn
123
15.3k
    2107428U, // BPLZnapt
124
15.3k
    2106511U, // BPNZapn
125
15.3k
    2105872U, // BPNZapt
126
15.3k
    2106570U, // BPNZnapn
127
15.3k
    2107472U, // BPNZnapt
128
15.3k
    1718780U, // BPXCC
129
15.3k
    735740U,  // BPXCCA
130
15.3k
    801276U,  // BPXCCANT
131
15.3k
    866812U,  // BPXCCNT
132
15.3k
    2106522U, // BPZapn
133
15.3k
    2105880U, // BPZapt
134
15.3k
    2106579U, // BPZnapn
135
15.3k
    2107505U, // BPZnapt
136
15.3k
    4983U,  // BSHUFFLE
137
15.3k
    74742U, // CALL
138
15.3k
    17398U, // CALLri
139
15.3k
    17398U, // CALLrr
140
15.3k
    924148U,  // CASXrr
141
15.3k
    924129U,  // CASrr
142
15.3k
    74001U, // CMASK16
143
15.3k
    73833U, // CMASK32
144
15.3k
    74150U, // CMASK8
145
15.3k
    2106607U, // CMPri
146
15.3k
    2106607U, // CMPrr
147
15.3k
    4332U,  // EDGE16
148
15.3k
    5081U,  // EDGE16L
149
15.3k
    5198U,  // EDGE16LN
150
15.3k
    5165U,  // EDGE16N
151
15.3k
    4164U,  // EDGE32
152
15.3k
    5072U,  // EDGE32L
153
15.3k
    5188U,  // EDGE32LN
154
15.3k
    5156U,  // EDGE32N
155
15.3k
    4511U,  // EDGE8
156
15.3k
    5090U,  // EDGE8L
157
15.3k
    5208U,  // EDGE8LN
158
15.3k
    5174U,  // EDGE8N
159
15.3k
    1053516U, // FABSD
160
15.3k
    1054031U, // FABSQ
161
15.3k
    1054376U, // FABSS
162
15.3k
    4813U,  // FADDD
163
15.3k
    5383U,  // FADDQ
164
15.3k
    5645U,  // FADDS
165
15.3k
    4648U,  // FALIGNADATA
166
15.3k
    4875U,  // FAND
167
15.3k
    4112U,  // FANDNOT1
168
15.3k
    5544U,  // FANDNOT1S
169
15.3k
    4271U,  // FANDNOT2
170
15.3k
    5591U,  // FANDNOT2S
171
15.3k
    5677U,  // FANDS
172
15.3k
    1194491U, // FBCOND
173
15.3k
    1260027U, // FBCONDA
174
15.3k
    4394U,  // FCHKSM16
175
15.3k
    2106173U, // FCMPD
176
15.3k
    4413U,  // FCMPEQ16
177
15.3k
    4226U,  // FCMPEQ32
178
15.3k
    4432U,  // FCMPGT16
179
15.3k
    4245U,  // FCMPGT32
180
15.3k
    4340U,  // FCMPLE16
181
15.3k
    4172U,  // FCMPLE32
182
15.3k
    4350U,  // FCMPNE16
183
15.3k
    4182U,  // FCMPNE32
184
15.3k
    2106696U, // FCMPQ
185
15.3k
    2107005U, // FCMPS
186
15.3k
    4960U,  // FDIVD
187
15.3k
    5475U,  // FDIVQ
188
15.3k
    5815U,  // FDIVS
189
15.3k
    5405U,  // FDMULQ
190
15.3k
    1053620U, // FDTOI
191
15.3k
    1053996U, // FDTOQ
192
15.3k
    1054305U, // FDTOS
193
15.3k
    1054536U, // FDTOX
194
15.3k
    1053464U, // FEXPAND
195
15.3k
    4820U,  // FHADDD
196
15.3k
    5652U,  // FHADDS
197
15.3k
    4800U,  // FHSUBD
198
15.3k
    5637U,  // FHSUBS
199
15.3k
    1053473U, // FITOD
200
15.3k
    1054003U, // FITOQ
201
15.3k
    1054312U, // FITOS
202
15.3k
    6300484U, // FLCMPD
203
15.3k
    6301316U, // FLCMPS
204
15.3k
    2606U,  // FLUSHW
205
15.3k
    4404U,  // FMEAN16
206
15.3k
    1053543U, // FMOVD
207
15.3k
    1006078U, // FMOVD_FCC
208
15.3k
    23484926U,  // FMOVD_ICC
209
15.3k
    23747070U,  // FMOVD_XCC
210
15.3k
    1054058U, // FMOVQ
211
15.3k
    1006102U, // FMOVQ_FCC
212
15.3k
    23484950U,  // FMOVQ_ICC
213
15.3k
    23747094U,  // FMOVQ_XCC
214
15.3k
    6018U,  // FMOVRGEZD
215
15.3k
    6029U,  // FMOVRGEZQ
216
15.3k
    6056U,  // FMOVRGEZS
217
15.3k
    6116U,  // FMOVRGZD
218
15.3k
    6126U,  // FMOVRGZQ
219
15.3k
    6150U,  // FMOVRGZS
220
15.3k
    6067U,  // FMOVRLEZD
221
15.3k
    6078U,  // FMOVRLEZQ
222
15.3k
    6105U,  // FMOVRLEZS
223
15.3k
    6160U,  // FMOVRLZD
224
15.3k
    6170U,  // FMOVRLZQ
225
15.3k
    6194U,  // FMOVRLZS
226
15.3k
    6204U,  // FMOVRNZD
227
15.3k
    6214U,  // FMOVRNZQ
228
15.3k
    6238U,  // FMOVRNZS
229
15.3k
    6009U,  // FMOVRZD
230
15.3k
    6248U,  // FMOVRZQ
231
15.3k
    6269U,  // FMOVRZS
232
15.3k
    1054398U, // FMOVS
233
15.3k
    1006114U, // FMOVS_FCC
234
15.3k
    23484962U,  // FMOVS_ICC
235
15.3k
    23747106U,  // FMOVS_XCC
236
15.3k
    4490U,  // FMUL8SUX16
237
15.3k
    4465U,  // FMUL8ULX16
238
15.3k
    4442U,  // FMUL8X16
239
15.3k
    5098U,  // FMUL8X16AL
240
15.3k
    5849U,  // FMUL8X16AU
241
15.3k
    4860U,  // FMULD
242
15.3k
    4477U,  // FMULD8SUX16
243
15.3k
    4452U,  // FMULD8ULX16
244
15.3k
    5413U,  // FMULQ
245
15.3k
    5714U,  // FMULS
246
15.3k
    4837U,  // FNADDD
247
15.3k
    5669U,  // FNADDS
248
15.3k
    4881U,  // FNAND
249
15.3k
    5684U,  // FNANDS
250
15.3k
    1053429U, // FNEGD
251
15.3k
    1053974U, // FNEGQ
252
15.3k
    1054283U, // FNEGS
253
15.3k
    4828U,  // FNHADDD
254
15.3k
    5660U,  // FNHADDS
255
15.3k
    4828U,  // FNMULD
256
15.3k
    5660U,  // FNMULS
257
15.3k
    5513U,  // FNOR
258
15.3k
    5778U,  // FNORS
259
15.3k
    1052698U, // FNOT1
260
15.3k
    1054131U, // FNOT1S
261
15.3k
    1052857U, // FNOT2
262
15.3k
    1054178U, // FNOT2S
263
15.3k
    5660U,  // FNSMULD
264
15.3k
    74625U, // FONE
265
15.3k
    75324U, // FONES
266
15.3k
    5508U,  // FOR
267
15.3k
    4129U,  // FORNOT1
268
15.3k
    5563U,  // FORNOT1S
269
15.3k
    4288U,  // FORNOT2
270
15.3k
    5610U,  // FORNOT2S
271
15.3k
    5772U,  // FORS
272
15.3k
    1052936U, // FPACK16
273
15.3k
    4192U,  // FPACK32
274
15.3k
    1054507U, // FPACKFIX
275
15.3k
    4323U,  // FPADD16
276
15.3k
    5620U,  // FPADD16S
277
15.3k
    4155U,  // FPADD32
278
15.3k
    5573U,  // FPADD32S
279
15.3k
    4297U,  // FPADD64
280
15.3k
    4974U,  // FPMERGE
281
15.3k
    4314U,  // FPSUB16
282
15.3k
    4580U,  // FPSUB16S
283
15.3k
    4146U,  // FPSUB32
284
15.3k
    4570U,  // FPSUB32S
285
15.3k
    1053480U, // FQTOD
286
15.3k
    1053627U, // FQTOI
287
15.3k
    1054319U, // FQTOS
288
15.3k
    1054552U, // FQTOX
289
15.3k
    4423U,  // FSLAS16
290
15.3k
    4236U,  // FSLAS32
291
15.3k
    4378U,  // FSLL16
292
15.3k
    4210U,  // FSLL32
293
15.3k
    4867U,  // FSMULD
294
15.3k
    1053523U, // FSQRTD
295
15.3k
    1054038U, // FSQRTQ
296
15.3k
    1054383U, // FSQRTS
297
15.3k
    4306U,  // FSRA16
298
15.3k
    4138U,  // FSRA32
299
15.3k
    1052681U, // FSRC1
300
15.3k
    1054112U, // FSRC1S
301
15.3k
    1052840U, // FSRC2
302
15.3k
    1054159U, // FSRC2S
303
15.3k
    4386U,  // FSRL16
304
15.3k
    4218U,  // FSRL32
305
15.3k
    1053487U, // FSTOD
306
15.3k
    1053634U, // FSTOI
307
15.3k
    1054010U, // FSTOQ
308
15.3k
    1054559U, // FSTOX
309
15.3k
    4793U,  // FSUBD
310
15.3k
    5376U,  // FSUBQ
311
15.3k
    5630U,  // FSUBS
312
15.3k
    5519U,  // FXNOR
313
15.3k
    5785U,  // FXNORS
314
15.3k
    5526U,  // FXOR
315
15.3k
    5793U,  // FXORS
316
15.3k
    1053494U, // FXTOD
317
15.3k
    1054017U, // FXTOQ
318
15.3k
    1054326U, // FXTOS
319
15.3k
    74984U, // FZERO
320
15.3k
    75353U, // FZEROS
321
15.3k
    24584U, // GETPCX
322
15.3k
    1078273U, // JMPLri
323
15.3k
    1078273U, // JMPLrr
324
15.3k
    1997243U, // LDDFri
325
15.3k
    1997243U, // LDDFrr
326
15.3k
    1997249U, // LDFri
327
15.3k
    1997249U, // LDFrr
328
15.3k
    1997275U, // LDQFri
329
15.3k
    1997275U, // LDQFrr
330
15.3k
    1997229U, // LDSBri
331
15.3k
    1997229U, // LDSBrr
332
15.3k
    1997254U, // LDSHri
333
15.3k
    1997254U, // LDSHrr
334
15.3k
    1997287U, // LDSWri
335
15.3k
    1997287U, // LDSWrr
336
15.3k
    1997236U, // LDUBri
337
15.3k
    1997236U, // LDUBrr
338
15.3k
    1997261U, // LDUHri
339
15.3k
    1997261U, // LDUHrr
340
15.3k
    1997294U, // LDXri
341
15.3k
    1997294U, // LDXrr
342
15.3k
    1997249U, // LDri
343
15.3k
    1997249U, // LDrr
344
15.3k
    33480U, // LEAX_ADDri
345
15.3k
    33480U, // LEA_ADDri
346
15.3k
    1054405U, // LZCNT
347
15.3k
    75121U, // MEMBARi
348
15.3k
    1054543U, // MOVDTOX
349
15.3k
    1006122U, // MOVFCCri
350
15.3k
    1006122U, // MOVFCCrr
351
15.3k
    23484970U,  // MOVICCri
352
15.3k
    23484970U,  // MOVICCrr
353
15.3k
    6047U,  // MOVRGEZri
354
15.3k
    6047U,  // MOVRGEZrr
355
15.3k
    6142U,  // MOVRGZri
356
15.3k
    6142U,  // MOVRGZrr
357
15.3k
    6096U,  // MOVRLEZri
358
15.3k
    6096U,  // MOVRLEZrr
359
15.3k
    6186U,  // MOVRLZri
360
15.3k
    6186U,  // MOVRLZrr
361
15.3k
    6230U,  // MOVRNZri
362
15.3k
    6230U,  // MOVRNZrr
363
15.3k
    6262U,  // MOVRRZri
364
15.3k
    6262U,  // MOVRRZrr
365
15.3k
    1054469U, // MOVSTOSW
366
15.3k
    1054479U, // MOVSTOUW
367
15.3k
    1054543U, // MOVWTOS
368
15.3k
    23747114U,  // MOVXCCri
369
15.3k
    23747114U,  // MOVXCCrr
370
15.3k
    1054543U, // MOVXTOD
371
15.3k
    5954U,  // MULXri
372
15.3k
    5954U,  // MULXrr
373
15.3k
    2578U,  // NOP
374
15.3k
    4735U,  // ORCCri
375
15.3k
    4735U,  // ORCCrr
376
15.3k
    4726U,  // ORNCCri
377
15.3k
    4726U,  // ORNCCrr
378
15.3k
    5339U,  // ORNri
379
15.3k
    5339U,  // ORNrr
380
15.3k
    5339U,  // ORXNrr
381
15.3k
    5509U,  // ORXri
382
15.3k
    5509U,  // ORXrr
383
15.3k
    5509U,  // ORri
384
15.3k
    5509U,  // ORrr
385
15.3k
    5836U,  // PDIST
386
15.3k
    5344U,  // PDISTN
387
15.3k
    1053356U, // POPCrr
388
15.3k
    73729U, // RDY
389
15.3k
    4999U,  // RESTOREri
390
15.3k
    4999U,  // RESTORErr
391
15.3k
    76132U, // RET
392
15.3k
    76141U, // RETL
393
15.3k
    18131U, // RETTri
394
15.3k
    18131U, // RETTrr
395
15.3k
    5008U,  // SAVEri
396
15.3k
    5008U,  // SAVErr
397
15.3k
    4748U,  // SDIVCCri
398
15.3k
    4748U,  // SDIVCCrr
399
15.3k
    5995U,  // SDIVXri
400
15.3k
    5995U,  // SDIVXrr
401
15.3k
    5861U,  // SDIVri
402
15.3k
    5861U,  // SDIVrr
403
15.3k
    2182U,  // SELECT_CC_DFP_FCC
404
15.3k
    2293U,  // SELECT_CC_DFP_ICC
405
15.3k
    2238U,  // SELECT_CC_FP_FCC
406
15.3k
    2349U,  // SELECT_CC_FP_ICC
407
15.3k
    2265U,  // SELECT_CC_Int_FCC
408
15.3k
    2376U,  // SELECT_CC_Int_ICC
409
15.3k
    2210U,  // SELECT_CC_QFP_FCC
410
15.3k
    2321U,  // SELECT_CC_QFP_ICC
411
15.3k
    1053595U, // SETHIXi
412
15.3k
    1053595U, // SETHIi
413
15.3k
    2569U,  // SHUTDOWN
414
15.3k
    2564U,  // SIAM
415
15.3k
    5941U,  // SLLXri
416
15.3k
    5941U,  // SLLXrr
417
15.3k
    5116U,  // SLLri
418
15.3k
    5116U,  // SLLrr
419
15.3k
    4702U,  // SMULCCri
420
15.3k
    4702U,  // SMULCCrr
421
15.3k
    5144U,  // SMULri
422
15.3k
    5144U,  // SMULrr
423
15.3k
    5913U,  // SRAXri
424
15.3k
    5913U,  // SRAXrr
425
15.3k
    4643U,  // SRAri
426
15.3k
    4643U,  // SRArr
427
15.3k
    5947U,  // SRLXri
428
15.3k
    5947U,  // SRLXrr
429
15.3k
    5139U,  // SRLri
430
15.3k
    5139U,  // SRLrr
431
15.3k
    2588U,  // STBAR
432
15.3k
    37428U, // STBri
433
15.3k
    37428U, // STBrr
434
15.3k
    37723U, // STDFri
435
15.3k
    37723U, // STDFrr
436
15.3k
    38607U, // STFri
437
15.3k
    38607U, // STFrr
438
15.3k
    37782U, // STHri
439
15.3k
    37782U, // STHrr
440
15.3k
    38238U, // STQFri
441
15.3k
    38238U, // STQFrr
442
15.3k
    38758U, // STXri
443
15.3k
    38758U, // STXrr
444
15.3k
    38607U, // STri
445
15.3k
    38607U, // STrr
446
15.3k
    4671U,  // SUBCCri
447
15.3k
    4671U,  // SUBCCrr
448
15.3k
    5919U,  // SUBCri
449
15.3k
    5919U,  // SUBCrr
450
15.3k
    4764U,  // SUBEri
451
15.3k
    4764U,  // SUBErr
452
15.3k
    4665U,  // SUBXri
453
15.3k
    4665U,  // SUBXrr
454
15.3k
    4665U,  // SUBri
455
15.3k
    4665U,  // SUBrr
456
15.3k
    1997268U, // SWAPri
457
15.3k
    1997268U, // SWAPrr
458
15.3k
    2422U,  // TA3
459
15.3k
    2427U,  // TA5
460
15.3k
    5883U,  // TADDCCTVri
461
15.3k
    5883U,  // TADDCCTVrr
462
15.3k
    4687U,  // TADDCCri
463
15.3k
    4687U,  // TADDCCrr
464
15.3k
    9873960U, // TICCri
465
15.3k
    9873960U, // TICCrr
466
15.3k
    37753544U,  // TLS_ADDXrr
467
15.3k
    37753544U,  // TLS_ADDrr
468
15.3k
    2106358U, // TLS_CALL
469
15.3k
    39746030U,  // TLS_LDXrr
470
15.3k
    39745985U,  // TLS_LDrr
471
15.3k
    5873U,  // TSUBCCTVri
472
15.3k
    5873U,  // TSUBCCTVrr
473
15.3k
    4670U,  // TSUBCCri
474
15.3k
    4670U,  // TSUBCCrr
475
15.3k
    10136104U,  // TXCCri
476
15.3k
    10136104U,  // TXCCrr
477
15.3k
    4756U,  // UDIVCCri
478
15.3k
    4756U,  // UDIVCCrr
479
15.3k
    6002U,  // UDIVXri
480
15.3k
    6002U,  // UDIVXrr
481
15.3k
    5867U,  // UDIVri
482
15.3k
    5867U,  // UDIVrr
483
15.3k
    4710U,  // UMULCCri
484
15.3k
    4710U,  // UMULCCrr
485
15.3k
    5026U,  // UMULXHI
486
15.3k
    5150U,  // UMULri
487
15.3k
    5150U,  // UMULrr
488
15.3k
    74996U, // UNIMP
489
15.3k
    6300477U, // V9FCMPD
490
15.3k
    6300397U, // V9FCMPED
491
15.3k
    6300942U, // V9FCMPEQ
492
15.3k
    6301251U, // V9FCMPES
493
15.3k
    6301000U, // V9FCMPQ
494
15.3k
    6301309U, // V9FCMPS
495
15.3k
    47614U, // V9FMOVD_FCC
496
15.3k
    47638U, // V9FMOVQ_FCC
497
15.3k
    47650U, // V9FMOVS_FCC
498
15.3k
    47658U, // V9MOVFCCri
499
15.3k
    47658U, // V9MOVFCCrr
500
15.3k
    14689692U,  // WRYri
501
15.3k
    14689692U,  // WRYrr
502
15.3k
    5953U,  // XMULX
503
15.3k
    5035U,  // XMULXHI
504
15.3k
    4733U,  // XNORCCri
505
15.3k
    4733U,  // XNORCCrr
506
15.3k
    5520U,  // XNORXrr
507
15.3k
    5520U,  // XNORri
508
15.3k
    5520U,  // XNORrr
509
15.3k
    4741U,  // XORCCri
510
15.3k
    4741U,  // XORCCrr
511
15.3k
    5527U,  // XORXri
512
15.3k
    5527U,  // XORXrr
513
15.3k
    5527U,  // XORri
514
15.3k
    5527U,  // XORrr
515
15.3k
    0U
516
15.3k
  };
517
518
15.3k
#ifndef CAPSTONE_DIET
519
15.3k
  static const char AsmStrs[] = {
520
15.3k
  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521
15.3k
  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522
15.3k
  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523
15.3k
  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524
15.3k
  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525
15.3k
  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526
15.3k
  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527
15.3k
  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528
15.3k
  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529
15.3k
  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530
15.3k
  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531
15.3k
  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532
15.3k
  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533
15.3k
  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534
15.3k
  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535
15.3k
  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536
15.3k
  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537
15.3k
  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538
15.3k
  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539
15.3k
  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540
15.3k
  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541
15.3k
  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542
15.3k
  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543
15.3k
  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544
15.3k
  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545
15.3k
  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546
15.3k
  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547
15.3k
  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548
15.3k
  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549
15.3k
  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550
15.3k
  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551
15.3k
  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552
15.3k
  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553
15.3k
  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554
15.3k
  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555
15.3k
  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556
15.3k
  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557
15.3k
  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558
15.3k
  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559
15.3k
  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560
15.3k
  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561
15.3k
  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562
15.3k
  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563
15.3k
  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564
15.3k
  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565
15.3k
  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566
15.3k
  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567
15.3k
  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568
15.3k
  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569
15.3k
  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570
15.3k
  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571
15.3k
  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572
15.3k
  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573
15.3k
  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574
15.3k
  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575
15.3k
  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576
15.3k
  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577
15.3k
  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578
15.3k
  /* 542 */ 'b', 'a', 32, 0,
579
15.3k
  /* 546 */ 's', 'r', 'a', 32, 0,
580
15.3k
  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581
15.3k
  /* 563 */ 's', 't', 'b', 32, 0,
582
15.3k
  /* 568 */ 's', 'u', 'b', 32, 0,
583
15.3k
  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584
15.3k
  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585
15.3k
  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586
15.3k
  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587
15.3k
  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588
15.3k
  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589
15.3k
  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590
15.3k
  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591
15.3k
  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592
15.3k
  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593
15.3k
  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594
15.3k
  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595
15.3k
  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596
15.3k
  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597
15.3k
  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598
15.3k
  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599
15.3k
  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600
15.3k
  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601
15.3k
  /* 711 */ 'a', 'd', 'd', 32, 0,
602
15.3k
  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603
15.3k
  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604
15.3k
  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605
15.3k
  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606
15.3k
  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607
15.3k
  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608
15.3k
  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609
15.3k
  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610
15.3k
  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611
15.3k
  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612
15.3k
  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613
15.3k
  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614
15.3k
  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615
15.3k
  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616
15.3k
  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617
15.3k
  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618
15.3k
  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619
15.3k
  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620
15.3k
  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621
15.3k
  /* 858 */ 's', 't', 'd', 32, 0,
622
15.3k
  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623
15.3k
  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624
15.3k
  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625
15.3k
  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626
15.3k
  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627
15.3k
  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628
15.3k
  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629
15.3k
  /* 917 */ 's', 't', 'h', 32, 0,
630
15.3k
  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631
15.3k
  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632
15.3k
  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633
15.3k
  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634
15.3k
  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635
15.3k
  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636
15.3k
  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637
15.3k
  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638
15.3k
  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639
15.3k
  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640
15.3k
  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641
15.3k
  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642
15.3k
  /* 1019 */ 's', 'l', 'l', 32, 0,
643
15.3k
  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644
15.3k
  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645
15.3k
  /* 1042 */ 's', 'r', 'l', 32, 0,
646
15.3k
  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647
15.3k
  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648
15.3k
  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649
15.3k
  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650
15.3k
  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651
15.3k
  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652
15.3k
  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653
15.3k
  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654
15.3k
  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655
15.3k
  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656
15.3k
  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657
15.3k
  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658
15.3k
  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659
15.3k
  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660
15.3k
  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661
15.3k
  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662
15.3k
  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663
15.3k
  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664
15.3k
  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665
15.3k
  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666
15.3k
  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667
15.3k
  /* 1242 */ 'o', 'r', 'n', 32, 0,
668
15.3k
  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669
15.3k
  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670
15.3k
  /* 1262 */ 'c', 'm', 'p', 32, 0,
671
15.3k
  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672
15.3k
  /* 1274 */ 'j', 'm', 'p', 32, 0,
673
15.3k
  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674
15.3k
  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675
15.3k
  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676
15.3k
  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677
15.3k
  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678
15.3k
  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679
15.3k
  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680
15.3k
  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681
15.3k
  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682
15.3k
  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683
15.3k
  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684
15.3k
  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685
15.3k
  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686
15.3k
  /* 1373 */ 's', 't', 'q', 32, 0,
687
15.3k
  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688
15.3k
  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689
15.3k
  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690
15.3k
  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691
15.3k
  /* 1411 */ 'f', 'o', 'r', 32, 0,
692
15.3k
  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693
15.3k
  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694
15.3k
  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695
15.3k
  /* 1435 */ 'w', 'r', 32, 0,
696
15.3k
  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697
15.3k
  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698
15.3k
  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699
15.3k
  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700
15.3k
  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701
15.3k
  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702
15.3k
  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703
15.3k
  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704
15.3k
  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705
15.3k
  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706
15.3k
  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707
15.3k
  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708
15.3k
  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709
15.3k
  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710
15.3k
  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711
15.3k
  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712
15.3k
  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713
15.3k
  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714
15.3k
  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715
15.3k
  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716
15.3k
  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717
15.3k
  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718
15.3k
  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719
15.3k
  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720
15.3k
  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721
15.3k
  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722
15.3k
  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723
15.3k
  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724
15.3k
  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725
15.3k
  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726
15.3k
  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727
15.3k
  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728
15.3k
  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729
15.3k
  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730
15.3k
  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731
15.3k
  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732
15.3k
  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733
15.3k
  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734
15.3k
  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735
15.3k
  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736
15.3k
  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737
15.3k
  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738
15.3k
  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739
15.3k
  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740
15.3k
  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741
15.3k
  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742
15.3k
  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743
15.3k
  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744
15.3k
  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745
15.3k
  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746
15.3k
  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747
15.3k
  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748
15.3k
  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749
15.3k
  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750
15.3k
  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751
15.3k
  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752
15.3k
  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753
15.3k
  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754
15.3k
  /* 1893 */ 's', 't', 'x', 32, 0,
755
15.3k
  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756
15.3k
  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757
15.3k
  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758
15.3k
  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759
15.3k
  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760
15.3k
  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761
15.3k
  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762
15.3k
  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763
15.3k
  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764
15.3k
  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765
15.3k
  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766
15.3k
  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767
15.3k
  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768
15.3k
  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769
15.3k
  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770
15.3k
  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771
15.3k
  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772
15.3k
  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773
15.3k
  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774
15.3k
  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775
15.3k
  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776
15.3k
  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777
15.3k
  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778
15.3k
  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779
15.3k
  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780
15.3k
  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781
15.3k
  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782
15.3k
  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783
15.3k
  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784
15.3k
  /* 2160 */ 'b', 'r', 'z', 32, 0,
785
15.3k
  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786
15.3k
  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787
15.3k
  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788
15.3k
  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789
15.3k
  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790
15.3k
  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791
15.3k
  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792
15.3k
  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793
15.3k
  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794
15.3k
  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795
15.3k
  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796
15.3k
  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797
15.3k
  /* 2421 */ 't', 'a', 32, '3', 0,
798
15.3k
  /* 2426 */ 't', 'a', 32, '5', 0,
799
15.3k
  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800
15.3k
  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801
15.3k
  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802
15.3k
  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803
15.3k
  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804
15.3k
  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805
15.3k
  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806
15.3k
  /* 2496 */ 'l', 'd', 32, '[', 0,
807
15.3k
  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808
15.3k
  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809
15.3k
  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810
15.3k
  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811
15.3k
  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812
15.3k
  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813
15.3k
  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814
15.3k
  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815
15.3k
  /* 2554 */ 'f', 'b', 0,
816
15.3k
  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817
15.3k
  /* 2563 */ 's', 'i', 'a', 'm', 0,
818
15.3k
  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819
15.3k
  /* 2577 */ 'n', 'o', 'p', 0,
820
15.3k
  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821
15.3k
  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822
15.3k
  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823
15.3k
  /* 2599 */ 't', 0,
824
15.3k
  /* 2601 */ 'm', 'o', 'v', 0,
825
15.3k
  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826
15.3k
  };
827
15.3k
#endif
828
829
  // Emit the opcode for the instruction.
830
15.3k
  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831
15.3k
#ifndef CAPSTONE_DIET
832
  // assert(Bits != 0 && "Cannot print this instruction.");
833
15.3k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834
15.3k
#endif
835
836
837
  // Fragment 0 encoded into 4 bits for 12 unique commands.
838
  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839
15.3k
  switch ((Bits >> 12) & 15) {
840
0
  default:   // unreachable.
841
30
  case 0:
842
    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843
30
    return;
844
0
    break;
845
2.43k
  case 1:
846
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847
2.43k
    printOperand(MI, 1, O); 
848
2.43k
    break;
849
9.47k
  case 2:
850
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851
9.47k
    printOperand(MI, 0, O); 
852
9.47k
    break;
853
1.62k
  case 3:
854
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855
1.62k
    printCCOperand(MI, 1, O); 
856
1.62k
    break;
857
19
  case 4:
858
    // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859
19
    printMemOperand(MI, 0, O, NULL); 
860
19
    return;
861
0
    break;
862
640
  case 5:
863
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864
640
    printCCOperand(MI, 3, O); 
865
640
    break;
866
0
  case 6:
867
    // GETPCX
868
0
    printGetPCX(MI, 0, O); 
869
0
    return;
870
0
    break;
871
642
  case 7:
872
    // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873
642
    printMemOperand(MI, 1, O, NULL); 
874
642
    break;
875
0
  case 8:
876
    // LEAX_ADDri, LEA_ADDri
877
0
    printMemOperand(MI, 1, O, "arith"); 
878
0
    SStream_concat0(O, ", "); 
879
0
    printOperand(MI, 0, O); 
880
0
    return;
881
0
    break;
882
271
  case 9:
883
    // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884
271
    printOperand(MI, 2, O); 
885
271
    SStream_concat0(O, ", ["); 
886
271
    printMemOperand(MI, 0, O, NULL); 
887
271
    SStream_concat0(O, "]"); 
888
271
    return;
889
0
    break;
890
54
  case 10:
891
    // TICCri, TICCrr, TXCCri, TXCCrr
892
54
    printCCOperand(MI, 2, O); 
893
54
    break;
894
191
  case 11:
895
    // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896
191
    printCCOperand(MI, 4, O); 
897
191
    SStream_concat0(O, " "); 
898
191
    printOperand(MI, 1, O); 
899
191
    SStream_concat0(O, ", "); 
900
191
    printOperand(MI, 2, O); 
901
191
    SStream_concat0(O, ", "); 
902
191
    printOperand(MI, 0, O); 
903
191
    return;
904
0
    break;
905
15.3k
  }
906
907
908
  // Fragment 1 encoded into 4 bits for 16 unique commands.
909
  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910
14.8k
  switch ((Bits >> 16) & 15) {
911
0
  default:   // unreachable.
912
3.30k
  case 0:
913
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914
3.30k
    SStream_concat0(O, ", "); 
915
3.30k
    break;
916
8.60k
  case 1:
917
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918
8.60k
    return;
919
0
    break;
920
854
  case 2:
921
    // BCOND, BPFCC, FBCOND
922
854
    SStream_concat0(O, " "); 
923
854
    break;
924
454
  case 3:
925
    // BCONDA, BPFCCA, FBCONDA
926
454
    SStream_concat0(O, ",a ");
927
454
  Sparc_add_hint(MI, SPARC_HINT_A);
928
454
    break;
929
0
  case 4:
930
    // BPFCCANT
931
0
    SStream_concat0(O, ",a,pn ");
932
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933
0
    printOperand(MI, 2, O); 
934
0
    SStream_concat0(O, ", "); 
935
0
    printOperand(MI, 0, O); 
936
0
    return;
937
0
    break;
938
0
  case 5:
939
    // BPFCCNT
940
0
    SStream_concat0(O, ",pn ");
941
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
942
0
    printOperand(MI, 2, O); 
943
0
    SStream_concat0(O, ", "); 
944
0
    printOperand(MI, 0, O); 
945
0
    return;
946
0
    break;
947
213
  case 6:
948
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949
213
    SStream_concat0(O, " %icc, ");
950
213
  Sparc_add_reg(MI, SPARC_REG_ICC);
951
213
    break;
952
150
  case 7:
953
    // BPICCA
954
150
    SStream_concat0(O, ",a %icc, ");
955
150
  Sparc_add_hint(MI, SPARC_HINT_A);
956
150
  Sparc_add_reg(MI, SPARC_REG_ICC);
957
150
    printOperand(MI, 0, O); 
958
150
    return;
959
0
    break;
960
0
  case 8:
961
    // BPICCANT
962
0
    SStream_concat0(O, ",a,pn %icc, ");
963
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
965
0
    printOperand(MI, 0, O); 
966
0
    return;
967
0
    break;
968
0
  case 9:
969
    // BPICCNT
970
0
    SStream_concat0(O, ",pn %icc, ");
971
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
972
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
973
0
    printOperand(MI, 0, O); 
974
0
    return;
975
0
    break;
976
398
  case 10:
977
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978
398
    SStream_concat0(O, " %xcc, ");
979
398
  Sparc_add_reg(MI, SPARC_REG_XCC);
980
398
    break;
981
57
  case 11:
982
    // BPXCCA
983
57
    SStream_concat0(O, ",a %xcc, ");
984
57
  Sparc_add_hint(MI, SPARC_HINT_A);
985
57
  Sparc_add_reg(MI, SPARC_REG_XCC);
986
57
    printOperand(MI, 0, O); 
987
57
    return;
988
0
    break;
989
0
  case 12:
990
    // BPXCCANT
991
0
    SStream_concat0(O, ",a,pn %xcc, ");
992
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
994
0
    printOperand(MI, 0, O); 
995
0
    return;
996
0
    break;
997
0
  case 13:
998
    // BPXCCNT
999
0
    SStream_concat0(O, ",pn %xcc, ");
1000
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
1001
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
1002
0
    printOperand(MI, 0, O); 
1003
0
    return;
1004
0
    break;
1005
638
  case 14:
1006
    // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007
638
    SStream_concat0(O, "], "); 
1008
638
    break;
1009
188
  case 15:
1010
    // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011
188
    SStream_concat0(O, " %fcc0, ");
1012
188
  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013
188
    printOperand(MI, 1, O); 
1014
188
    SStream_concat0(O, ", "); 
1015
188
    printOperand(MI, 0, O); 
1016
188
    return;
1017
0
    break;
1018
14.8k
  }
1019
1020
1021
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022
  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023
5.86k
  switch ((Bits >> 20) & 3) {
1024
0
  default:   // unreachable.
1025
1.40k
  case 0:
1026
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027
1.40k
    printOperand(MI, 2, O); 
1028
1.40k
    SStream_concat0(O, ", "); 
1029
1.40k
    printOperand(MI, 0, O); 
1030
1.40k
    break;
1031
3.14k
  case 1:
1032
    // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033
3.14k
    printOperand(MI, 0, O); 
1034
3.14k
    break;
1035
1.32k
  case 2:
1036
    // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037
1.32k
    printOperand(MI, 1, O); 
1038
1.32k
    break;
1039
5.86k
  }
1040
1041
1042
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043
  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044
5.86k
  switch ((Bits >> 22) & 3) {
1045
0
  default:   // unreachable.
1046
5.20k
  case 0:
1047
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048
5.20k
    return;
1049
0
    break;
1050
574
  case 1:
1051
    // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052
574
    SStream_concat0(O, ", "); 
1053
574
    break;
1054
54
  case 2:
1055
    // TICCri, TICCrr, TXCCri, TXCCrr
1056
54
    SStream_concat0(O, " + ");  // qq
1057
54
    printOperand(MI, 1, O); 
1058
54
    return;
1059
0
    break;
1060
36
  case 3:
1061
    // WRYri, WRYrr
1062
36
    SStream_concat0(O, ", %y");
1063
36
  Sparc_add_reg(MI, SPARC_REG_Y);
1064
36
    return;
1065
0
    break;
1066
5.86k
  }
1067
1068
1069
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070
  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071
574
  switch ((Bits >> 24) & 3) {
1072
0
  default:   // unreachable.
1073
122
  case 0:
1074
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075
122
    printOperand(MI, 2, O); 
1076
122
    return;
1077
0
    break;
1078
452
  case 1:
1079
    // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080
452
    printOperand(MI, 0, O); 
1081
452
    return;
1082
0
    break;
1083
0
  case 2:
1084
    // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085
0
    printOperand(MI, 3, O); 
1086
0
    return;
1087
0
    break;
1088
574
  }
1089
574
}
1090
1091
1092
/// getRegisterName - This method is automatically generated by tblgen
1093
/// from the register set description.  This returns the assembler name
1094
/// for the specified register.
1095
static const char *getRegisterName(unsigned RegNo)
1096
14.5k
{
1097
  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098
1099
14.5k
#ifndef CAPSTONE_DIET
1100
14.5k
  static const char AsmStrs[] = {
1101
14.5k
  /* 0 */ 'f', '1', '0', 0,
1102
14.5k
  /* 4 */ 'f', '2', '0', 0,
1103
14.5k
  /* 8 */ 'f', '3', '0', 0,
1104
14.5k
  /* 12 */ 'f', '4', '0', 0,
1105
14.5k
  /* 16 */ 'f', '5', '0', 0,
1106
14.5k
  /* 20 */ 'f', '6', '0', 0,
1107
14.5k
  /* 24 */ 'f', 'c', 'c', '0', 0,
1108
14.5k
  /* 29 */ 'f', '0', 0,
1109
14.5k
  /* 32 */ 'g', '0', 0,
1110
14.5k
  /* 35 */ 'i', '0', 0,
1111
14.5k
  /* 38 */ 'l', '0', 0,
1112
14.5k
  /* 41 */ 'o', '0', 0,
1113
14.5k
  /* 44 */ 'f', '1', '1', 0,
1114
14.5k
  /* 48 */ 'f', '2', '1', 0,
1115
14.5k
  /* 52 */ 'f', '3', '1', 0,
1116
14.5k
  /* 56 */ 'f', 'c', 'c', '1', 0,
1117
14.5k
  /* 61 */ 'f', '1', 0,
1118
14.5k
  /* 64 */ 'g', '1', 0,
1119
14.5k
  /* 67 */ 'i', '1', 0,
1120
14.5k
  /* 70 */ 'l', '1', 0,
1121
14.5k
  /* 73 */ 'o', '1', 0,
1122
14.5k
  /* 76 */ 'f', '1', '2', 0,
1123
14.5k
  /* 80 */ 'f', '2', '2', 0,
1124
14.5k
  /* 84 */ 'f', '3', '2', 0,
1125
14.5k
  /* 88 */ 'f', '4', '2', 0,
1126
14.5k
  /* 92 */ 'f', '5', '2', 0,
1127
14.5k
  /* 96 */ 'f', '6', '2', 0,
1128
14.5k
  /* 100 */ 'f', 'c', 'c', '2', 0,
1129
14.5k
  /* 105 */ 'f', '2', 0,
1130
14.5k
  /* 108 */ 'g', '2', 0,
1131
14.5k
  /* 111 */ 'i', '2', 0,
1132
14.5k
  /* 114 */ 'l', '2', 0,
1133
14.5k
  /* 117 */ 'o', '2', 0,
1134
14.5k
  /* 120 */ 'f', '1', '3', 0,
1135
14.5k
  /* 124 */ 'f', '2', '3', 0,
1136
14.5k
  /* 128 */ 'f', 'c', 'c', '3', 0,
1137
14.5k
  /* 133 */ 'f', '3', 0,
1138
14.5k
  /* 136 */ 'g', '3', 0,
1139
14.5k
  /* 139 */ 'i', '3', 0,
1140
14.5k
  /* 142 */ 'l', '3', 0,
1141
14.5k
  /* 145 */ 'o', '3', 0,
1142
14.5k
  /* 148 */ 'f', '1', '4', 0,
1143
14.5k
  /* 152 */ 'f', '2', '4', 0,
1144
14.5k
  /* 156 */ 'f', '3', '4', 0,
1145
14.5k
  /* 160 */ 'f', '4', '4', 0,
1146
14.5k
  /* 164 */ 'f', '5', '4', 0,
1147
14.5k
  /* 168 */ 'f', '4', 0,
1148
14.5k
  /* 171 */ 'g', '4', 0,
1149
14.5k
  /* 174 */ 'i', '4', 0,
1150
14.5k
  /* 177 */ 'l', '4', 0,
1151
14.5k
  /* 180 */ 'o', '4', 0,
1152
14.5k
  /* 183 */ 'f', '1', '5', 0,
1153
14.5k
  /* 187 */ 'f', '2', '5', 0,
1154
14.5k
  /* 191 */ 'f', '5', 0,
1155
14.5k
  /* 194 */ 'g', '5', 0,
1156
14.5k
  /* 197 */ 'i', '5', 0,
1157
14.5k
  /* 200 */ 'l', '5', 0,
1158
14.5k
  /* 203 */ 'o', '5', 0,
1159
14.5k
  /* 206 */ 'f', '1', '6', 0,
1160
14.5k
  /* 210 */ 'f', '2', '6', 0,
1161
14.5k
  /* 214 */ 'f', '3', '6', 0,
1162
14.5k
  /* 218 */ 'f', '4', '6', 0,
1163
14.5k
  /* 222 */ 'f', '5', '6', 0,
1164
14.5k
  /* 226 */ 'f', '6', 0,
1165
14.5k
  /* 229 */ 'g', '6', 0,
1166
14.5k
  /* 232 */ 'l', '6', 0,
1167
14.5k
  /* 235 */ 'f', '1', '7', 0,
1168
14.5k
  /* 239 */ 'f', '2', '7', 0,
1169
14.5k
  /* 243 */ 'f', '7', 0,
1170
14.5k
  /* 246 */ 'g', '7', 0,
1171
14.5k
  /* 249 */ 'i', '7', 0,
1172
14.5k
  /* 252 */ 'l', '7', 0,
1173
14.5k
  /* 255 */ 'o', '7', 0,
1174
14.5k
  /* 258 */ 'f', '1', '8', 0,
1175
14.5k
  /* 262 */ 'f', '2', '8', 0,
1176
14.5k
  /* 266 */ 'f', '3', '8', 0,
1177
14.5k
  /* 270 */ 'f', '4', '8', 0,
1178
14.5k
  /* 274 */ 'f', '5', '8', 0,
1179
14.5k
  /* 278 */ 'f', '8', 0,
1180
14.5k
  /* 281 */ 'f', '1', '9', 0,
1181
14.5k
  /* 285 */ 'f', '2', '9', 0,
1182
14.5k
  /* 289 */ 'f', '9', 0,
1183
14.5k
  /* 292 */ 'i', 'c', 'c', 0,
1184
14.5k
  /* 296 */ 'f', 'p', 0,
1185
14.5k
  /* 299 */ 's', 'p', 0,
1186
14.5k
  /* 302 */ 'y', 0,
1187
14.5k
  };
1188
1189
14.5k
  static const uint16_t RegAsmOffset[] = {
1190
14.5k
    292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 
1191
14.5k
    152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 
1192
14.5k
    92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 
1193
14.5k
    278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 
1194
14.5k
    80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 
1195
14.5k
    32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 
1196
14.5k
    296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 
1197
14.5k
    180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 
1198
14.5k
    12, 160, 270, 92, 222, 20, 
1199
14.5k
  };
1200
1201
  //int i;
1202
  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203
  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204
  //printf("*************************\n");
1205
14.5k
  return AsmStrs+RegAsmOffset[RegNo-1];
1206
#else
1207
  return NULL;
1208
#endif
1209
14.5k
}
1210
1211
#ifdef PRINT_ALIAS_INSTR
1212
#undef PRINT_ALIAS_INSTR
1213
1214
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1215
  unsigned PrintMethodIdx, SStream *OS)
1216
0
{
1217
0
}
1218
1219
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1220
23.7k
{
1221
55.2k
  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1222
23.7k
  const char *AsmString;
1223
23.7k
  char *tmp, *AsmMnem, *AsmOps, *c;
1224
23.7k
  int OpIdx, PrintMethodIdx;
1225
23.7k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1226
23.7k
  switch (MCInst_getOpcode(MI)) {
1227
14.9k
  default: return NULL;
1228
929
  case SP_BCOND:
1229
929
    if (MCInst_getNumOperands(MI) == 2 &&
1230
929
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1231
929
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1232
      // (BCOND brtarget:$imm, 8)
1233
0
      AsmString = "ba $\x01";
1234
0
      break;
1235
0
    }
1236
929
    if (MCInst_getNumOperands(MI) == 2 &&
1237
929
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1238
929
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1239
      // (BCOND brtarget:$imm, 0)
1240
410
      AsmString = "bn $\x01";
1241
410
      break;
1242
410
    }
1243
519
    if (MCInst_getNumOperands(MI) == 2 &&
1244
519
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1245
519
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1246
      // (BCOND brtarget:$imm, 9)
1247
31
      AsmString = "bne $\x01";
1248
31
      break;
1249
31
    }
1250
488
    if (MCInst_getNumOperands(MI) == 2 &&
1251
488
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1252
488
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1253
      // (BCOND brtarget:$imm, 1)
1254
40
      AsmString = "be $\x01";
1255
40
      break;
1256
40
    }
1257
448
    if (MCInst_getNumOperands(MI) == 2 &&
1258
448
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1259
448
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1260
      // (BCOND brtarget:$imm, 10)
1261
17
      AsmString = "bg $\x01";
1262
17
      break;
1263
17
    }
1264
431
    if (MCInst_getNumOperands(MI) == 2 &&
1265
431
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1266
431
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1267
      // (BCOND brtarget:$imm, 2)
1268
23
      AsmString = "ble $\x01";
1269
23
      break;
1270
23
    }
1271
408
    if (MCInst_getNumOperands(MI) == 2 &&
1272
408
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1273
408
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1274
      // (BCOND brtarget:$imm, 11)
1275
4
      AsmString = "bge $\x01";
1276
4
      break;
1277
4
    }
1278
404
    if (MCInst_getNumOperands(MI) == 2 &&
1279
404
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1280
404
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1281
      // (BCOND brtarget:$imm, 3)
1282
29
      AsmString = "bl $\x01";
1283
29
      break;
1284
29
    }
1285
375
    if (MCInst_getNumOperands(MI) == 2 &&
1286
375
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1287
375
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1288
      // (BCOND brtarget:$imm, 12)
1289
40
      AsmString = "bgu $\x01";
1290
40
      break;
1291
40
    }
1292
335
    if (MCInst_getNumOperands(MI) == 2 &&
1293
335
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1294
335
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1295
      // (BCOND brtarget:$imm, 4)
1296
41
      AsmString = "bleu $\x01";
1297
41
      break;
1298
41
    }
1299
294
    if (MCInst_getNumOperands(MI) == 2 &&
1300
294
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1301
294
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1302
      // (BCOND brtarget:$imm, 13)
1303
42
      AsmString = "bcc $\x01";
1304
42
      break;
1305
42
    }
1306
252
    if (MCInst_getNumOperands(MI) == 2 &&
1307
252
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1308
252
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1309
      // (BCOND brtarget:$imm, 5)
1310
8
      AsmString = "bcs $\x01";
1311
8
      break;
1312
8
    }
1313
244
    if (MCInst_getNumOperands(MI) == 2 &&
1314
244
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1315
244
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1316
      // (BCOND brtarget:$imm, 14)
1317
0
      AsmString = "bpos $\x01";
1318
0
      break;
1319
0
    }
1320
244
    if (MCInst_getNumOperands(MI) == 2 &&
1321
244
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1322
244
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1323
      // (BCOND brtarget:$imm, 6)
1324
56
      AsmString = "bneg $\x01";
1325
56
      break;
1326
56
    }
1327
188
    if (MCInst_getNumOperands(MI) == 2 &&
1328
188
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1329
188
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1330
      // (BCOND brtarget:$imm, 15)
1331
21
      AsmString = "bvc $\x01";
1332
21
      break;
1333
21
    }
1334
167
    if (MCInst_getNumOperands(MI) == 2 &&
1335
167
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1336
167
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1337
      // (BCOND brtarget:$imm, 7)
1338
167
      AsmString = "bvs $\x01";
1339
167
      break;
1340
167
    }
1341
0
    return NULL;
1342
907
  case SP_BCONDA:
1343
907
    if (MCInst_getNumOperands(MI) == 2 &&
1344
907
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1345
907
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1346
      // (BCONDA brtarget:$imm, 8)
1347
26
      AsmString = "ba,a $\x01";
1348
26
      break;
1349
26
    }
1350
881
    if (MCInst_getNumOperands(MI) == 2 &&
1351
881
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1352
881
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1353
      // (BCONDA brtarget:$imm, 0)
1354
135
      AsmString = "bn,a $\x01";
1355
135
      break;
1356
135
    }
1357
746
    if (MCInst_getNumOperands(MI) == 2 &&
1358
746
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1359
746
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1360
      // (BCONDA brtarget:$imm, 9)
1361
13
      AsmString = "bne,a $\x01";
1362
13
      break;
1363
13
    }
1364
733
    if (MCInst_getNumOperands(MI) == 2 &&
1365
733
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1366
733
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1367
      // (BCONDA brtarget:$imm, 1)
1368
6
      AsmString = "be,a $\x01";
1369
6
      break;
1370
6
    }
1371
727
    if (MCInst_getNumOperands(MI) == 2 &&
1372
727
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1373
727
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1374
      // (BCONDA brtarget:$imm, 10)
1375
40
      AsmString = "bg,a $\x01";
1376
40
      break;
1377
40
    }
1378
687
    if (MCInst_getNumOperands(MI) == 2 &&
1379
687
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1380
687
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1381
      // (BCONDA brtarget:$imm, 2)
1382
7
      AsmString = "ble,a $\x01";
1383
7
      break;
1384
7
    }
1385
680
    if (MCInst_getNumOperands(MI) == 2 &&
1386
680
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1387
680
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1388
      // (BCONDA brtarget:$imm, 11)
1389
20
      AsmString = "bge,a $\x01";
1390
20
      break;
1391
20
    }
1392
660
    if (MCInst_getNumOperands(MI) == 2 &&
1393
660
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1394
660
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1395
      // (BCONDA brtarget:$imm, 3)
1396
54
      AsmString = "bl,a $\x01";
1397
54
      break;
1398
54
    }
1399
606
    if (MCInst_getNumOperands(MI) == 2 &&
1400
606
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1401
606
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1402
      // (BCONDA brtarget:$imm, 12)
1403
64
      AsmString = "bgu,a $\x01";
1404
64
      break;
1405
64
    }
1406
542
    if (MCInst_getNumOperands(MI) == 2 &&
1407
542
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1408
542
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1409
      // (BCONDA brtarget:$imm, 4)
1410
116
      AsmString = "bleu,a $\x01";
1411
116
      break;
1412
116
    }
1413
426
    if (MCInst_getNumOperands(MI) == 2 &&
1414
426
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1415
426
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1416
      // (BCONDA brtarget:$imm, 13)
1417
20
      AsmString = "bcc,a $\x01";
1418
20
      break;
1419
20
    }
1420
406
    if (MCInst_getNumOperands(MI) == 2 &&
1421
406
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1422
406
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1423
      // (BCONDA brtarget:$imm, 5)
1424
41
      AsmString = "bcs,a $\x01";
1425
41
      break;
1426
41
    }
1427
365
    if (MCInst_getNumOperands(MI) == 2 &&
1428
365
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1429
365
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1430
      // (BCONDA brtarget:$imm, 14)
1431
9
      AsmString = "bpos,a $\x01";
1432
9
      break;
1433
9
    }
1434
356
    if (MCInst_getNumOperands(MI) == 2 &&
1435
356
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1436
356
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1437
      // (BCONDA brtarget:$imm, 6)
1438
23
      AsmString = "bneg,a $\x01";
1439
23
      break;
1440
23
    }
1441
333
    if (MCInst_getNumOperands(MI) == 2 &&
1442
333
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1443
333
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1444
      // (BCONDA brtarget:$imm, 15)
1445
247
      AsmString = "bvc,a $\x01";
1446
247
      break;
1447
247
    }
1448
86
    if (MCInst_getNumOperands(MI) == 2 &&
1449
86
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1450
86
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1451
      // (BCONDA brtarget:$imm, 7)
1452
86
      AsmString = "bvs,a $\x01";
1453
86
      break;
1454
86
    }
1455
0
    return NULL;
1456
918
  case SP_BPFCCANT:
1457
918
    if (MCInst_getNumOperands(MI) == 3 &&
1458
918
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1459
918
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1460
918
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1461
918
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1462
      // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1463
4
      AsmString = "fba,a,pn $\x03, $\x01";
1464
4
      break;
1465
4
    }
1466
914
    if (MCInst_getNumOperands(MI) == 3 &&
1467
914
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1468
914
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1469
914
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1470
914
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1471
      // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1472
45
      AsmString = "fbn,a,pn $\x03, $\x01";
1473
45
      break;
1474
45
    }
1475
869
    if (MCInst_getNumOperands(MI) == 3 &&
1476
869
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1477
869
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1478
869
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1479
869
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1480
      // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1481
11
      AsmString = "fbu,a,pn $\x03, $\x01";
1482
11
      break;
1483
11
    }
1484
858
    if (MCInst_getNumOperands(MI) == 3 &&
1485
858
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1486
858
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1487
858
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1488
858
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1489
      // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1490
47
      AsmString = "fbg,a,pn $\x03, $\x01";
1491
47
      break;
1492
47
    }
1493
811
    if (MCInst_getNumOperands(MI) == 3 &&
1494
811
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1495
811
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1496
811
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1497
811
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1498
      // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1499
125
      AsmString = "fbug,a,pn $\x03, $\x01";
1500
125
      break;
1501
125
    }
1502
686
    if (MCInst_getNumOperands(MI) == 3 &&
1503
686
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1504
686
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1505
686
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1506
686
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1507
      // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1508
54
      AsmString = "fbl,a,pn $\x03, $\x01";
1509
54
      break;
1510
54
    }
1511
632
    if (MCInst_getNumOperands(MI) == 3 &&
1512
632
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1513
632
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1514
632
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1515
632
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1516
      // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1517
27
      AsmString = "fbul,a,pn $\x03, $\x01";
1518
27
      break;
1519
27
    }
1520
605
    if (MCInst_getNumOperands(MI) == 3 &&
1521
605
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1522
605
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1523
605
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1524
605
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1525
      // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1526
37
      AsmString = "fblg,a,pn $\x03, $\x01";
1527
37
      break;
1528
37
    }
1529
568
    if (MCInst_getNumOperands(MI) == 3 &&
1530
568
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1531
568
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1532
568
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1533
568
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1534
      // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1535
194
      AsmString = "fbne,a,pn $\x03, $\x01";
1536
194
      break;
1537
194
    }
1538
374
    if (MCInst_getNumOperands(MI) == 3 &&
1539
374
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1540
374
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1541
374
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1542
374
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1543
      // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1544
12
      AsmString = "fbe,a,pn $\x03, $\x01";
1545
12
      break;
1546
12
    }
1547
362
    if (MCInst_getNumOperands(MI) == 3 &&
1548
362
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1549
362
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1550
362
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1551
362
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1552
      // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1553
11
      AsmString = "fbue,a,pn $\x03, $\x01";
1554
11
      break;
1555
11
    }
1556
351
    if (MCInst_getNumOperands(MI) == 3 &&
1557
351
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1558
351
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1559
351
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1560
351
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1561
      // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1562
78
      AsmString = "fbge,a,pn $\x03, $\x01";
1563
78
      break;
1564
78
    }
1565
273
    if (MCInst_getNumOperands(MI) == 3 &&
1566
273
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1567
273
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1568
273
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1569
273
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1570
      // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1571
33
      AsmString = "fbuge,a,pn $\x03, $\x01";
1572
33
      break;
1573
33
    }
1574
240
    if (MCInst_getNumOperands(MI) == 3 &&
1575
240
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1576
240
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1577
240
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1578
240
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1579
      // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1580
3
      AsmString = "fble,a,pn $\x03, $\x01";
1581
3
      break;
1582
3
    }
1583
237
    if (MCInst_getNumOperands(MI) == 3 &&
1584
237
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1585
237
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1586
237
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1587
237
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1588
      // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1589
67
      AsmString = "fbule,a,pn $\x03, $\x01";
1590
67
      break;
1591
67
    }
1592
170
    if (MCInst_getNumOperands(MI) == 3 &&
1593
170
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1594
170
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1595
170
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1596
170
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1597
      // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1598
170
      AsmString = "fbo,a,pn $\x03, $\x01";
1599
170
      break;
1600
170
    }
1601
0
    return NULL;
1602
1.22k
  case SP_BPFCCNT:
1603
1.22k
    if (MCInst_getNumOperands(MI) == 3 &&
1604
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1605
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1606
1.22k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1607
1.22k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1608
      // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1609
134
      AsmString = "fba,pn $\x03, $\x01";
1610
134
      break;
1611
134
    }
1612
1.09k
    if (MCInst_getNumOperands(MI) == 3 &&
1613
1.09k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1614
1.09k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1615
1.09k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1616
1.09k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1617
      // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1618
147
      AsmString = "fbn,pn $\x03, $\x01";
1619
147
      break;
1620
147
    }
1621
945
    if (MCInst_getNumOperands(MI) == 3 &&
1622
945
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
945
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1624
945
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1625
945
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1626
      // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1627
66
      AsmString = "fbu,pn $\x03, $\x01";
1628
66
      break;
1629
66
    }
1630
879
    if (MCInst_getNumOperands(MI) == 3 &&
1631
879
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1632
879
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1633
879
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1634
879
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1635
      // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1636
9
      AsmString = "fbg,pn $\x03, $\x01";
1637
9
      break;
1638
9
    }
1639
870
    if (MCInst_getNumOperands(MI) == 3 &&
1640
870
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1641
870
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1642
870
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1643
870
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1644
      // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1645
56
      AsmString = "fbug,pn $\x03, $\x01";
1646
56
      break;
1647
56
    }
1648
814
    if (MCInst_getNumOperands(MI) == 3 &&
1649
814
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1650
814
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1651
814
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1652
814
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1653
      // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1654
62
      AsmString = "fbl,pn $\x03, $\x01";
1655
62
      break;
1656
62
    }
1657
752
    if (MCInst_getNumOperands(MI) == 3 &&
1658
752
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1659
752
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1660
752
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1661
752
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1662
      // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1663
156
      AsmString = "fbul,pn $\x03, $\x01";
1664
156
      break;
1665
156
    }
1666
596
    if (MCInst_getNumOperands(MI) == 3 &&
1667
596
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1668
596
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1669
596
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1670
596
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1671
      // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1672
70
      AsmString = "fblg,pn $\x03, $\x01";
1673
70
      break;
1674
70
    }
1675
526
    if (MCInst_getNumOperands(MI) == 3 &&
1676
526
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1677
526
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1678
526
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1679
526
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1680
      // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1681
37
      AsmString = "fbne,pn $\x03, $\x01";
1682
37
      break;
1683
37
    }
1684
489
    if (MCInst_getNumOperands(MI) == 3 &&
1685
489
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1686
489
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1687
489
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1688
489
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1689
      // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1690
49
      AsmString = "fbe,pn $\x03, $\x01";
1691
49
      break;
1692
49
    }
1693
440
    if (MCInst_getNumOperands(MI) == 3 &&
1694
440
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1695
440
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1696
440
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1697
440
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1698
      // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1699
5
      AsmString = "fbue,pn $\x03, $\x01";
1700
5
      break;
1701
5
    }
1702
435
    if (MCInst_getNumOperands(MI) == 3 &&
1703
435
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1704
435
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1705
435
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1706
435
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1707
      // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1708
17
      AsmString = "fbge,pn $\x03, $\x01";
1709
17
      break;
1710
17
    }
1711
418
    if (MCInst_getNumOperands(MI) == 3 &&
1712
418
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1713
418
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1714
418
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1715
418
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1716
      // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1717
152
      AsmString = "fbuge,pn $\x03, $\x01";
1718
152
      break;
1719
152
    }
1720
266
    if (MCInst_getNumOperands(MI) == 3 &&
1721
266
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1722
266
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1723
266
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1724
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1725
      // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1726
13
      AsmString = "fble,pn $\x03, $\x01";
1727
13
      break;
1728
13
    }
1729
253
    if (MCInst_getNumOperands(MI) == 3 &&
1730
253
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1731
253
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1732
253
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1733
253
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1734
      // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1735
219
      AsmString = "fbule,pn $\x03, $\x01";
1736
219
      break;
1737
219
    }
1738
34
    if (MCInst_getNumOperands(MI) == 3 &&
1739
34
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1740
34
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1741
34
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1742
34
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1743
      // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1744
34
      AsmString = "fbo,pn $\x03, $\x01";
1745
34
      break;
1746
34
    }
1747
0
    return NULL;
1748
712
  case SP_BPICCANT:
1749
712
    if (MCInst_getNumOperands(MI) == 2 &&
1750
712
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1751
712
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1752
      // (BPICCANT brtarget:$imm, 8)
1753
16
      AsmString = "ba,a,pn %icc, $\x01";
1754
16
      break;
1755
16
    }
1756
696
    if (MCInst_getNumOperands(MI) == 2 &&
1757
696
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
696
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1759
      // (BPICCANT brtarget:$imm, 0)
1760
24
      AsmString = "bn,a,pn %icc, $\x01";
1761
24
      break;
1762
24
    }
1763
672
    if (MCInst_getNumOperands(MI) == 2 &&
1764
672
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1765
672
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1766
      // (BPICCANT brtarget:$imm, 9)
1767
5
      AsmString = "bne,a,pn %icc, $\x01";
1768
5
      break;
1769
5
    }
1770
667
    if (MCInst_getNumOperands(MI) == 2 &&
1771
667
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1772
667
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1773
      // (BPICCANT brtarget:$imm, 1)
1774
218
      AsmString = "be,a,pn %icc, $\x01";
1775
218
      break;
1776
218
    }
1777
449
    if (MCInst_getNumOperands(MI) == 2 &&
1778
449
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1779
449
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1780
      // (BPICCANT brtarget:$imm, 10)
1781
55
      AsmString = "bg,a,pn %icc, $\x01";
1782
55
      break;
1783
55
    }
1784
394
    if (MCInst_getNumOperands(MI) == 2 &&
1785
394
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1786
394
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1787
      // (BPICCANT brtarget:$imm, 2)
1788
40
      AsmString = "ble,a,pn %icc, $\x01";
1789
40
      break;
1790
40
    }
1791
354
    if (MCInst_getNumOperands(MI) == 2 &&
1792
354
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1793
354
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1794
      // (BPICCANT brtarget:$imm, 11)
1795
11
      AsmString = "bge,a,pn %icc, $\x01";
1796
11
      break;
1797
11
    }
1798
343
    if (MCInst_getNumOperands(MI) == 2 &&
1799
343
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1800
343
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1801
      // (BPICCANT brtarget:$imm, 3)
1802
10
      AsmString = "bl,a,pn %icc, $\x01";
1803
10
      break;
1804
10
    }
1805
333
    if (MCInst_getNumOperands(MI) == 2 &&
1806
333
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1807
333
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1808
      // (BPICCANT brtarget:$imm, 12)
1809
80
      AsmString = "bgu,a,pn %icc, $\x01";
1810
80
      break;
1811
80
    }
1812
253
    if (MCInst_getNumOperands(MI) == 2 &&
1813
253
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1814
253
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1815
      // (BPICCANT brtarget:$imm, 4)
1816
140
      AsmString = "bleu,a,pn %icc, $\x01";
1817
140
      break;
1818
140
    }
1819
113
    if (MCInst_getNumOperands(MI) == 2 &&
1820
113
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1821
113
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1822
      // (BPICCANT brtarget:$imm, 13)
1823
2
      AsmString = "bcc,a,pn %icc, $\x01";
1824
2
      break;
1825
2
    }
1826
111
    if (MCInst_getNumOperands(MI) == 2 &&
1827
111
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1828
111
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1829
      // (BPICCANT brtarget:$imm, 5)
1830
36
      AsmString = "bcs,a,pn %icc, $\x01";
1831
36
      break;
1832
36
    }
1833
75
    if (MCInst_getNumOperands(MI) == 2 &&
1834
75
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1835
75
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1836
      // (BPICCANT brtarget:$imm, 14)
1837
11
      AsmString = "bpos,a,pn %icc, $\x01";
1838
11
      break;
1839
11
    }
1840
64
    if (MCInst_getNumOperands(MI) == 2 &&
1841
64
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1842
64
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1843
      // (BPICCANT brtarget:$imm, 6)
1844
10
      AsmString = "bneg,a,pn %icc, $\x01";
1845
10
      break;
1846
10
    }
1847
54
    if (MCInst_getNumOperands(MI) == 2 &&
1848
54
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1849
54
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1850
      // (BPICCANT brtarget:$imm, 15)
1851
41
      AsmString = "bvc,a,pn %icc, $\x01";
1852
41
      break;
1853
41
    }
1854
13
    if (MCInst_getNumOperands(MI) == 2 &&
1855
13
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1856
13
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1857
      // (BPICCANT brtarget:$imm, 7)
1858
13
      AsmString = "bvs,a,pn %icc, $\x01";
1859
13
      break;
1860
13
    }
1861
0
    return NULL;
1862
479
  case SP_BPICCNT:
1863
479
    if (MCInst_getNumOperands(MI) == 2 &&
1864
479
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1865
479
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1866
      // (BPICCNT brtarget:$imm, 8)
1867
21
      AsmString = "ba,pn %icc, $\x01";
1868
21
      break;
1869
21
    }
1870
458
    if (MCInst_getNumOperands(MI) == 2 &&
1871
458
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1872
458
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1873
      // (BPICCNT brtarget:$imm, 0)
1874
43
      AsmString = "bn,pn %icc, $\x01";
1875
43
      break;
1876
43
    }
1877
415
    if (MCInst_getNumOperands(MI) == 2 &&
1878
415
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1879
415
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1880
      // (BPICCNT brtarget:$imm, 9)
1881
54
      AsmString = "bne,pn %icc, $\x01";
1882
54
      break;
1883
54
    }
1884
361
    if (MCInst_getNumOperands(MI) == 2 &&
1885
361
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1886
361
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1887
      // (BPICCNT brtarget:$imm, 1)
1888
38
      AsmString = "be,pn %icc, $\x01";
1889
38
      break;
1890
38
    }
1891
323
    if (MCInst_getNumOperands(MI) == 2 &&
1892
323
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1893
323
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1894
      // (BPICCNT brtarget:$imm, 10)
1895
65
      AsmString = "bg,pn %icc, $\x01";
1896
65
      break;
1897
65
    }
1898
258
    if (MCInst_getNumOperands(MI) == 2 &&
1899
258
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1900
258
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1901
      // (BPICCNT brtarget:$imm, 2)
1902
39
      AsmString = "ble,pn %icc, $\x01";
1903
39
      break;
1904
39
    }
1905
219
    if (MCInst_getNumOperands(MI) == 2 &&
1906
219
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1907
219
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1908
      // (BPICCNT brtarget:$imm, 11)
1909
28
      AsmString = "bge,pn %icc, $\x01";
1910
28
      break;
1911
28
    }
1912
191
    if (MCInst_getNumOperands(MI) == 2 &&
1913
191
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1914
191
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1915
      // (BPICCNT brtarget:$imm, 3)
1916
37
      AsmString = "bl,pn %icc, $\x01";
1917
37
      break;
1918
37
    }
1919
154
    if (MCInst_getNumOperands(MI) == 2 &&
1920
154
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1921
154
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1922
      // (BPICCNT brtarget:$imm, 12)
1923
7
      AsmString = "bgu,pn %icc, $\x01";
1924
7
      break;
1925
7
    }
1926
147
    if (MCInst_getNumOperands(MI) == 2 &&
1927
147
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1928
147
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1929
      // (BPICCNT brtarget:$imm, 4)
1930
22
      AsmString = "bleu,pn %icc, $\x01";
1931
22
      break;
1932
22
    }
1933
125
    if (MCInst_getNumOperands(MI) == 2 &&
1934
125
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1935
125
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1936
      // (BPICCNT brtarget:$imm, 13)
1937
18
      AsmString = "bcc,pn %icc, $\x01";
1938
18
      break;
1939
18
    }
1940
107
    if (MCInst_getNumOperands(MI) == 2 &&
1941
107
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1942
107
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1943
      // (BPICCNT brtarget:$imm, 5)
1944
14
      AsmString = "bcs,pn %icc, $\x01";
1945
14
      break;
1946
14
    }
1947
93
    if (MCInst_getNumOperands(MI) == 2 &&
1948
93
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1949
93
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1950
      // (BPICCNT brtarget:$imm, 14)
1951
48
      AsmString = "bpos,pn %icc, $\x01";
1952
48
      break;
1953
48
    }
1954
45
    if (MCInst_getNumOperands(MI) == 2 &&
1955
45
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1956
45
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1957
      // (BPICCNT brtarget:$imm, 6)
1958
30
      AsmString = "bneg,pn %icc, $\x01";
1959
30
      break;
1960
30
    }
1961
15
    if (MCInst_getNumOperands(MI) == 2 &&
1962
15
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1963
15
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1964
      // (BPICCNT brtarget:$imm, 15)
1965
8
      AsmString = "bvc,pn %icc, $\x01";
1966
8
      break;
1967
8
    }
1968
7
    if (MCInst_getNumOperands(MI) == 2 &&
1969
7
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1970
7
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1971
      // (BPICCNT brtarget:$imm, 7)
1972
7
      AsmString = "bvs,pn %icc, $\x01";
1973
7
      break;
1974
7
    }
1975
0
    return NULL;
1976
615
  case SP_BPXCCANT:
1977
615
    if (MCInst_getNumOperands(MI) == 2 &&
1978
615
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1979
615
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1980
      // (BPXCCANT brtarget:$imm, 8)
1981
32
      AsmString = "ba,a,pn %xcc, $\x01";
1982
32
      break;
1983
32
    }
1984
583
    if (MCInst_getNumOperands(MI) == 2 &&
1985
583
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1986
583
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1987
      // (BPXCCANT brtarget:$imm, 0)
1988
28
      AsmString = "bn,a,pn %xcc, $\x01";
1989
28
      break;
1990
28
    }
1991
555
    if (MCInst_getNumOperands(MI) == 2 &&
1992
555
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1993
555
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1994
      // (BPXCCANT brtarget:$imm, 9)
1995
12
      AsmString = "bne,a,pn %xcc, $\x01";
1996
12
      break;
1997
12
    }
1998
543
    if (MCInst_getNumOperands(MI) == 2 &&
1999
543
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2000
543
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2001
      // (BPXCCANT brtarget:$imm, 1)
2002
24
      AsmString = "be,a,pn %xcc, $\x01";
2003
24
      break;
2004
24
    }
2005
519
    if (MCInst_getNumOperands(MI) == 2 &&
2006
519
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2007
519
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2008
      // (BPXCCANT brtarget:$imm, 10)
2009
57
      AsmString = "bg,a,pn %xcc, $\x01";
2010
57
      break;
2011
57
    }
2012
462
    if (MCInst_getNumOperands(MI) == 2 &&
2013
462
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2014
462
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2015
      // (BPXCCANT brtarget:$imm, 2)
2016
47
      AsmString = "ble,a,pn %xcc, $\x01";
2017
47
      break;
2018
47
    }
2019
415
    if (MCInst_getNumOperands(MI) == 2 &&
2020
415
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2021
415
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2022
      // (BPXCCANT brtarget:$imm, 11)
2023
10
      AsmString = "bge,a,pn %xcc, $\x01";
2024
10
      break;
2025
10
    }
2026
405
    if (MCInst_getNumOperands(MI) == 2 &&
2027
405
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2028
405
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2029
      // (BPXCCANT brtarget:$imm, 3)
2030
12
      AsmString = "bl,a,pn %xcc, $\x01";
2031
12
      break;
2032
12
    }
2033
393
    if (MCInst_getNumOperands(MI) == 2 &&
2034
393
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2035
393
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2036
      // (BPXCCANT brtarget:$imm, 12)
2037
206
      AsmString = "bgu,a,pn %xcc, $\x01";
2038
206
      break;
2039
206
    }
2040
187
    if (MCInst_getNumOperands(MI) == 2 &&
2041
187
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2042
187
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2043
      // (BPXCCANT brtarget:$imm, 4)
2044
17
      AsmString = "bleu,a,pn %xcc, $\x01";
2045
17
      break;
2046
17
    }
2047
170
    if (MCInst_getNumOperands(MI) == 2 &&
2048
170
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2049
170
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2050
      // (BPXCCANT brtarget:$imm, 13)
2051
31
      AsmString = "bcc,a,pn %xcc, $\x01";
2052
31
      break;
2053
31
    }
2054
139
    if (MCInst_getNumOperands(MI) == 2 &&
2055
139
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2056
139
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2057
      // (BPXCCANT brtarget:$imm, 5)
2058
65
      AsmString = "bcs,a,pn %xcc, $\x01";
2059
65
      break;
2060
65
    }
2061
74
    if (MCInst_getNumOperands(MI) == 2 &&
2062
74
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2063
74
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2064
      // (BPXCCANT brtarget:$imm, 14)
2065
15
      AsmString = "bpos,a,pn %xcc, $\x01";
2066
15
      break;
2067
15
    }
2068
59
    if (MCInst_getNumOperands(MI) == 2 &&
2069
59
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2070
59
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2071
      // (BPXCCANT brtarget:$imm, 6)
2072
20
      AsmString = "bneg,a,pn %xcc, $\x01";
2073
20
      break;
2074
20
    }
2075
39
    if (MCInst_getNumOperands(MI) == 2 &&
2076
39
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2077
39
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2078
      // (BPXCCANT brtarget:$imm, 15)
2079
23
      AsmString = "bvc,a,pn %xcc, $\x01";
2080
23
      break;
2081
23
    }
2082
16
    if (MCInst_getNumOperands(MI) == 2 &&
2083
16
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2084
16
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2085
      // (BPXCCANT brtarget:$imm, 7)
2086
16
      AsmString = "bvs,a,pn %xcc, $\x01";
2087
16
      break;
2088
16
    }
2089
0
    return NULL;
2090
855
  case SP_BPXCCNT:
2091
855
    if (MCInst_getNumOperands(MI) == 2 &&
2092
855
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2093
855
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2094
      // (BPXCCNT brtarget:$imm, 8)
2095
15
      AsmString = "ba,pn %xcc, $\x01";
2096
15
      break;
2097
15
    }
2098
840
    if (MCInst_getNumOperands(MI) == 2 &&
2099
840
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2100
840
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2101
      // (BPXCCNT brtarget:$imm, 0)
2102
92
      AsmString = "bn,pn %xcc, $\x01";
2103
92
      break;
2104
92
    }
2105
748
    if (MCInst_getNumOperands(MI) == 2 &&
2106
748
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2107
748
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2108
      // (BPXCCNT brtarget:$imm, 9)
2109
125
      AsmString = "bne,pn %xcc, $\x01";
2110
125
      break;
2111
125
    }
2112
623
    if (MCInst_getNumOperands(MI) == 2 &&
2113
623
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2114
623
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2115
      // (BPXCCNT brtarget:$imm, 1)
2116
1
      AsmString = "be,pn %xcc, $\x01";
2117
1
      break;
2118
1
    }
2119
622
    if (MCInst_getNumOperands(MI) == 2 &&
2120
622
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2121
622
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2122
      // (BPXCCNT brtarget:$imm, 10)
2123
77
      AsmString = "bg,pn %xcc, $\x01";
2124
77
      break;
2125
77
    }
2126
545
    if (MCInst_getNumOperands(MI) == 2 &&
2127
545
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2128
545
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2129
      // (BPXCCNT brtarget:$imm, 2)
2130
17
      AsmString = "ble,pn %xcc, $\x01";
2131
17
      break;
2132
17
    }
2133
528
    if (MCInst_getNumOperands(MI) == 2 &&
2134
528
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2135
528
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2136
      // (BPXCCNT brtarget:$imm, 11)
2137
35
      AsmString = "bge,pn %xcc, $\x01";
2138
35
      break;
2139
35
    }
2140
493
    if (MCInst_getNumOperands(MI) == 2 &&
2141
493
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2142
493
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2143
      // (BPXCCNT brtarget:$imm, 3)
2144
10
      AsmString = "bl,pn %xcc, $\x01";
2145
10
      break;
2146
10
    }
2147
483
    if (MCInst_getNumOperands(MI) == 2 &&
2148
483
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2149
483
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2150
      // (BPXCCNT brtarget:$imm, 12)
2151
270
      AsmString = "bgu,pn %xcc, $\x01";
2152
270
      break;
2153
270
    }
2154
213
    if (MCInst_getNumOperands(MI) == 2 &&
2155
213
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2156
213
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2157
      // (BPXCCNT brtarget:$imm, 4)
2158
78
      AsmString = "bleu,pn %xcc, $\x01";
2159
78
      break;
2160
78
    }
2161
135
    if (MCInst_getNumOperands(MI) == 2 &&
2162
135
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2163
135
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2164
      // (BPXCCNT brtarget:$imm, 13)
2165
45
      AsmString = "bcc,pn %xcc, $\x01";
2166
45
      break;
2167
45
    }
2168
90
    if (MCInst_getNumOperands(MI) == 2 &&
2169
90
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2170
90
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2171
      // (BPXCCNT brtarget:$imm, 5)
2172
34
      AsmString = "bcs,pn %xcc, $\x01";
2173
34
      break;
2174
34
    }
2175
56
    if (MCInst_getNumOperands(MI) == 2 &&
2176
56
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2177
56
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2178
      // (BPXCCNT brtarget:$imm, 14)
2179
10
      AsmString = "bpos,pn %xcc, $\x01";
2180
10
      break;
2181
10
    }
2182
46
    if (MCInst_getNumOperands(MI) == 2 &&
2183
46
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2184
46
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2185
      // (BPXCCNT brtarget:$imm, 6)
2186
40
      AsmString = "bneg,pn %xcc, $\x01";
2187
40
      break;
2188
40
    }
2189
6
    if (MCInst_getNumOperands(MI) == 2 &&
2190
6
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2191
6
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2192
      // (BPXCCNT brtarget:$imm, 15)
2193
3
      AsmString = "bvc,pn %xcc, $\x01";
2194
3
      break;
2195
3
    }
2196
3
    if (MCInst_getNumOperands(MI) == 2 &&
2197
3
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2198
3
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2199
      // (BPXCCNT brtarget:$imm, 7)
2200
3
      AsmString = "bvs,pn %xcc, $\x01";
2201
3
      break;
2202
3
    }
2203
0
    return NULL;
2204
14
  case SP_FMOVD_ICC:
2205
14
    if (MCInst_getNumOperands(MI) == 3 &&
2206
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2207
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2208
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2209
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2210
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2211
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2212
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2213
0
      AsmString = "fmovda %icc, $\x02, $\x01";
2214
0
      break;
2215
0
    }
2216
14
    if (MCInst_getNumOperands(MI) == 3 &&
2217
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2218
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2219
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2220
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2221
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2222
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2223
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2224
0
      AsmString = "fmovdn %icc, $\x02, $\x01";
2225
0
      break;
2226
0
    }
2227
14
    if (MCInst_getNumOperands(MI) == 3 &&
2228
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2229
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2230
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2231
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2232
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2233
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2234
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2235
0
      AsmString = "fmovdne %icc, $\x02, $\x01";
2236
0
      break;
2237
0
    }
2238
14
    if (MCInst_getNumOperands(MI) == 3 &&
2239
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2240
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2241
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2242
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2243
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2244
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2245
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2246
0
      AsmString = "fmovde %icc, $\x02, $\x01";
2247
0
      break;
2248
0
    }
2249
14
    if (MCInst_getNumOperands(MI) == 3 &&
2250
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2251
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2252
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2253
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2254
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2255
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2256
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2257
0
      AsmString = "fmovdg %icc, $\x02, $\x01";
2258
0
      break;
2259
0
    }
2260
14
    if (MCInst_getNumOperands(MI) == 3 &&
2261
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2262
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2263
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2264
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2265
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2266
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2267
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2268
0
      AsmString = "fmovdle %icc, $\x02, $\x01";
2269
0
      break;
2270
0
    }
2271
14
    if (MCInst_getNumOperands(MI) == 3 &&
2272
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2273
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2274
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2275
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2276
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2277
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2278
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2279
0
      AsmString = "fmovdge %icc, $\x02, $\x01";
2280
0
      break;
2281
0
    }
2282
14
    if (MCInst_getNumOperands(MI) == 3 &&
2283
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2285
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2287
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2288
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2289
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2290
0
      AsmString = "fmovdl %icc, $\x02, $\x01";
2291
0
      break;
2292
0
    }
2293
14
    if (MCInst_getNumOperands(MI) == 3 &&
2294
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2295
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2296
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2297
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2298
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2299
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2300
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2301
0
      AsmString = "fmovdgu %icc, $\x02, $\x01";
2302
0
      break;
2303
0
    }
2304
14
    if (MCInst_getNumOperands(MI) == 3 &&
2305
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2306
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2307
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2308
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2309
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2310
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2311
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2312
0
      AsmString = "fmovdleu %icc, $\x02, $\x01";
2313
0
      break;
2314
0
    }
2315
14
    if (MCInst_getNumOperands(MI) == 3 &&
2316
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2317
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2318
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2319
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2320
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2321
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2322
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2323
0
      AsmString = "fmovdcc %icc, $\x02, $\x01";
2324
0
      break;
2325
0
    }
2326
14
    if (MCInst_getNumOperands(MI) == 3 &&
2327
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2328
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2329
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2330
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2331
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2332
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2333
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2334
0
      AsmString = "fmovdcs %icc, $\x02, $\x01";
2335
0
      break;
2336
0
    }
2337
14
    if (MCInst_getNumOperands(MI) == 3 &&
2338
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2339
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2340
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2341
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2342
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2343
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2344
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2345
0
      AsmString = "fmovdpos %icc, $\x02, $\x01";
2346
0
      break;
2347
0
    }
2348
14
    if (MCInst_getNumOperands(MI) == 3 &&
2349
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2350
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2351
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2352
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2353
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2354
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2355
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2356
0
      AsmString = "fmovdneg %icc, $\x02, $\x01";
2357
0
      break;
2358
0
    }
2359
14
    if (MCInst_getNumOperands(MI) == 3 &&
2360
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2361
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2362
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2363
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2364
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2365
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2366
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2367
0
      AsmString = "fmovdvc %icc, $\x02, $\x01";
2368
0
      break;
2369
0
    }
2370
14
    if (MCInst_getNumOperands(MI) == 3 &&
2371
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2372
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2373
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2374
14
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2375
14
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2376
14
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2377
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2378
0
      AsmString = "fmovdvs %icc, $\x02, $\x01";
2379
0
      break;
2380
0
    }
2381
14
    return NULL;
2382
241
  case SP_FMOVD_XCC:
2383
241
    if (MCInst_getNumOperands(MI) == 3 &&
2384
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2385
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2386
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2387
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2388
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2389
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2390
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2391
0
      AsmString = "fmovda %xcc, $\x02, $\x01";
2392
0
      break;
2393
0
    }
2394
241
    if (MCInst_getNumOperands(MI) == 3 &&
2395
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2396
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2397
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2398
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2399
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2400
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2401
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2402
0
      AsmString = "fmovdn %xcc, $\x02, $\x01";
2403
0
      break;
2404
0
    }
2405
241
    if (MCInst_getNumOperands(MI) == 3 &&
2406
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2407
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2408
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2409
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2410
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2411
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2412
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2413
0
      AsmString = "fmovdne %xcc, $\x02, $\x01";
2414
0
      break;
2415
0
    }
2416
241
    if (MCInst_getNumOperands(MI) == 3 &&
2417
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2418
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2419
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2420
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2421
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2422
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2423
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2424
0
      AsmString = "fmovde %xcc, $\x02, $\x01";
2425
0
      break;
2426
0
    }
2427
241
    if (MCInst_getNumOperands(MI) == 3 &&
2428
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2429
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2430
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2431
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2432
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2433
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2434
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2435
0
      AsmString = "fmovdg %xcc, $\x02, $\x01";
2436
0
      break;
2437
0
    }
2438
241
    if (MCInst_getNumOperands(MI) == 3 &&
2439
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2440
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2441
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2442
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2443
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2444
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2445
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2446
0
      AsmString = "fmovdle %xcc, $\x02, $\x01";
2447
0
      break;
2448
0
    }
2449
241
    if (MCInst_getNumOperands(MI) == 3 &&
2450
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2451
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2452
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2453
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2454
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2455
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2456
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2457
0
      AsmString = "fmovdge %xcc, $\x02, $\x01";
2458
0
      break;
2459
0
    }
2460
241
    if (MCInst_getNumOperands(MI) == 3 &&
2461
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2462
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2463
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2464
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2465
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2466
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2467
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2468
0
      AsmString = "fmovdl %xcc, $\x02, $\x01";
2469
0
      break;
2470
0
    }
2471
241
    if (MCInst_getNumOperands(MI) == 3 &&
2472
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2473
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2474
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2475
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2476
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2477
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2478
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2479
0
      AsmString = "fmovdgu %xcc, $\x02, $\x01";
2480
0
      break;
2481
0
    }
2482
241
    if (MCInst_getNumOperands(MI) == 3 &&
2483
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2484
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2485
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2486
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2487
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2488
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2489
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2490
0
      AsmString = "fmovdleu %xcc, $\x02, $\x01";
2491
0
      break;
2492
0
    }
2493
241
    if (MCInst_getNumOperands(MI) == 3 &&
2494
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2495
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2496
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2497
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2498
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2499
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2500
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2501
0
      AsmString = "fmovdcc %xcc, $\x02, $\x01";
2502
0
      break;
2503
0
    }
2504
241
    if (MCInst_getNumOperands(MI) == 3 &&
2505
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2506
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2507
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2508
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2509
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2510
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2511
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2512
0
      AsmString = "fmovdcs %xcc, $\x02, $\x01";
2513
0
      break;
2514
0
    }
2515
241
    if (MCInst_getNumOperands(MI) == 3 &&
2516
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2518
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2519
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2520
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2521
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2522
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2523
0
      AsmString = "fmovdpos %xcc, $\x02, $\x01";
2524
0
      break;
2525
0
    }
2526
241
    if (MCInst_getNumOperands(MI) == 3 &&
2527
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2528
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2529
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2530
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2531
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2532
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2533
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2534
0
      AsmString = "fmovdneg %xcc, $\x02, $\x01";
2535
0
      break;
2536
0
    }
2537
241
    if (MCInst_getNumOperands(MI) == 3 &&
2538
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2539
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2540
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2541
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2542
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2543
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2544
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2545
0
      AsmString = "fmovdvc %xcc, $\x02, $\x01";
2546
0
      break;
2547
0
    }
2548
241
    if (MCInst_getNumOperands(MI) == 3 &&
2549
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2550
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2551
241
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2552
241
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2553
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2554
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2555
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2556
0
      AsmString = "fmovdvs %xcc, $\x02, $\x01";
2557
0
      break;
2558
0
    }
2559
241
    return NULL;
2560
79
  case SP_FMOVQ_ICC:
2561
79
    if (MCInst_getNumOperands(MI) == 3 &&
2562
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2563
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2564
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2565
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2566
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2567
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2568
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2569
0
      AsmString = "fmovqa %icc, $\x02, $\x01";
2570
0
      break;
2571
0
    }
2572
79
    if (MCInst_getNumOperands(MI) == 3 &&
2573
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2574
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2575
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2576
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2577
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2578
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2579
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2580
0
      AsmString = "fmovqn %icc, $\x02, $\x01";
2581
0
      break;
2582
0
    }
2583
79
    if (MCInst_getNumOperands(MI) == 3 &&
2584
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2585
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2586
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2587
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2588
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2589
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2590
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2591
0
      AsmString = "fmovqne %icc, $\x02, $\x01";
2592
0
      break;
2593
0
    }
2594
79
    if (MCInst_getNumOperands(MI) == 3 &&
2595
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2596
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2597
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2598
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2599
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2600
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2601
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2602
0
      AsmString = "fmovqe %icc, $\x02, $\x01";
2603
0
      break;
2604
0
    }
2605
79
    if (MCInst_getNumOperands(MI) == 3 &&
2606
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2607
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2608
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2609
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2610
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2611
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2612
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2613
0
      AsmString = "fmovqg %icc, $\x02, $\x01";
2614
0
      break;
2615
0
    }
2616
79
    if (MCInst_getNumOperands(MI) == 3 &&
2617
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2618
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2619
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2620
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2621
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2622
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2623
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2624
0
      AsmString = "fmovqle %icc, $\x02, $\x01";
2625
0
      break;
2626
0
    }
2627
79
    if (MCInst_getNumOperands(MI) == 3 &&
2628
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2629
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2630
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2631
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2632
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2633
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2634
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2635
0
      AsmString = "fmovqge %icc, $\x02, $\x01";
2636
0
      break;
2637
0
    }
2638
79
    if (MCInst_getNumOperands(MI) == 3 &&
2639
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2640
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2641
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2642
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2643
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2644
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2645
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2646
0
      AsmString = "fmovql %icc, $\x02, $\x01";
2647
0
      break;
2648
0
    }
2649
79
    if (MCInst_getNumOperands(MI) == 3 &&
2650
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2651
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2652
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2653
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2654
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2655
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2656
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2657
0
      AsmString = "fmovqgu %icc, $\x02, $\x01";
2658
0
      break;
2659
0
    }
2660
79
    if (MCInst_getNumOperands(MI) == 3 &&
2661
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2662
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2663
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2664
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2665
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2666
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2667
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2668
0
      AsmString = "fmovqleu %icc, $\x02, $\x01";
2669
0
      break;
2670
0
    }
2671
79
    if (MCInst_getNumOperands(MI) == 3 &&
2672
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2673
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2674
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2675
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2676
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2677
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2678
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2679
0
      AsmString = "fmovqcc %icc, $\x02, $\x01";
2680
0
      break;
2681
0
    }
2682
79
    if (MCInst_getNumOperands(MI) == 3 &&
2683
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2684
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2685
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2686
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2687
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2688
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2689
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2690
0
      AsmString = "fmovqcs %icc, $\x02, $\x01";
2691
0
      break;
2692
0
    }
2693
79
    if (MCInst_getNumOperands(MI) == 3 &&
2694
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2695
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2696
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2697
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2698
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2699
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2700
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2701
0
      AsmString = "fmovqpos %icc, $\x02, $\x01";
2702
0
      break;
2703
0
    }
2704
79
    if (MCInst_getNumOperands(MI) == 3 &&
2705
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2706
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2707
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2708
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2709
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2710
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2711
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2712
0
      AsmString = "fmovqneg %icc, $\x02, $\x01";
2713
0
      break;
2714
0
    }
2715
79
    if (MCInst_getNumOperands(MI) == 3 &&
2716
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2717
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2718
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2719
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2720
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2721
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2722
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2723
0
      AsmString = "fmovqvc %icc, $\x02, $\x01";
2724
0
      break;
2725
0
    }
2726
79
    if (MCInst_getNumOperands(MI) == 3 &&
2727
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2728
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2729
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2730
79
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2731
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2732
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2733
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2734
0
      AsmString = "fmovqvs %icc, $\x02, $\x01";
2735
0
      break;
2736
0
    }
2737
79
    return NULL;
2738
33
  case SP_FMOVQ_XCC:
2739
33
    if (MCInst_getNumOperands(MI) == 3 &&
2740
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2741
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2742
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2743
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2744
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2745
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2746
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2747
0
      AsmString = "fmovqa %xcc, $\x02, $\x01";
2748
0
      break;
2749
0
    }
2750
33
    if (MCInst_getNumOperands(MI) == 3 &&
2751
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2752
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2753
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2754
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2755
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2756
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2757
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2758
0
      AsmString = "fmovqn %xcc, $\x02, $\x01";
2759
0
      break;
2760
0
    }
2761
33
    if (MCInst_getNumOperands(MI) == 3 &&
2762
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2763
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2764
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2765
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2766
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2767
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2768
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2769
0
      AsmString = "fmovqne %xcc, $\x02, $\x01";
2770
0
      break;
2771
0
    }
2772
33
    if (MCInst_getNumOperands(MI) == 3 &&
2773
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2774
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2775
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2776
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2777
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2778
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2779
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2780
0
      AsmString = "fmovqe %xcc, $\x02, $\x01";
2781
0
      break;
2782
0
    }
2783
33
    if (MCInst_getNumOperands(MI) == 3 &&
2784
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2785
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2786
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2787
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2788
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2789
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2790
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2791
0
      AsmString = "fmovqg %xcc, $\x02, $\x01";
2792
0
      break;
2793
0
    }
2794
33
    if (MCInst_getNumOperands(MI) == 3 &&
2795
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2796
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2797
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2798
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2799
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2800
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2801
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2802
0
      AsmString = "fmovqle %xcc, $\x02, $\x01";
2803
0
      break;
2804
0
    }
2805
33
    if (MCInst_getNumOperands(MI) == 3 &&
2806
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2807
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2808
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2809
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2810
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2811
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2812
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2813
0
      AsmString = "fmovqge %xcc, $\x02, $\x01";
2814
0
      break;
2815
0
    }
2816
33
    if (MCInst_getNumOperands(MI) == 3 &&
2817
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2818
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2819
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2820
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2821
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2822
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2823
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2824
0
      AsmString = "fmovql %xcc, $\x02, $\x01";
2825
0
      break;
2826
0
    }
2827
33
    if (MCInst_getNumOperands(MI) == 3 &&
2828
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2829
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2830
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2831
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2832
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2834
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2835
0
      AsmString = "fmovqgu %xcc, $\x02, $\x01";
2836
0
      break;
2837
0
    }
2838
33
    if (MCInst_getNumOperands(MI) == 3 &&
2839
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2840
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2841
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2842
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2843
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2844
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2845
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2846
0
      AsmString = "fmovqleu %xcc, $\x02, $\x01";
2847
0
      break;
2848
0
    }
2849
33
    if (MCInst_getNumOperands(MI) == 3 &&
2850
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2851
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2852
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2853
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2854
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2855
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2856
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2857
0
      AsmString = "fmovqcc %xcc, $\x02, $\x01";
2858
0
      break;
2859
0
    }
2860
33
    if (MCInst_getNumOperands(MI) == 3 &&
2861
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2862
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2863
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2864
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2865
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2866
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2867
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2868
0
      AsmString = "fmovqcs %xcc, $\x02, $\x01";
2869
0
      break;
2870
0
    }
2871
33
    if (MCInst_getNumOperands(MI) == 3 &&
2872
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2873
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2874
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2875
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2876
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2877
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2878
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2879
0
      AsmString = "fmovqpos %xcc, $\x02, $\x01";
2880
0
      break;
2881
0
    }
2882
33
    if (MCInst_getNumOperands(MI) == 3 &&
2883
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2884
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2885
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2886
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2887
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2888
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2889
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2890
0
      AsmString = "fmovqneg %xcc, $\x02, $\x01";
2891
0
      break;
2892
0
    }
2893
33
    if (MCInst_getNumOperands(MI) == 3 &&
2894
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2895
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2896
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2897
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2898
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2899
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2900
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2901
0
      AsmString = "fmovqvc %xcc, $\x02, $\x01";
2902
0
      break;
2903
0
    }
2904
33
    if (MCInst_getNumOperands(MI) == 3 &&
2905
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2906
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2907
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2908
33
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2909
33
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2910
33
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2911
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2912
0
      AsmString = "fmovqvs %xcc, $\x02, $\x01";
2913
0
      break;
2914
0
    }
2915
33
    return NULL;
2916
11
  case SP_FMOVS_ICC:
2917
11
    if (MCInst_getNumOperands(MI) == 3 &&
2918
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2919
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2920
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2921
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2922
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2923
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2924
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2925
0
      AsmString = "fmovsa %icc, $\x02, $\x01";
2926
0
      break;
2927
0
    }
2928
11
    if (MCInst_getNumOperands(MI) == 3 &&
2929
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2930
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2931
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2932
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2933
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2934
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2935
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2936
0
      AsmString = "fmovsn %icc, $\x02, $\x01";
2937
0
      break;
2938
0
    }
2939
11
    if (MCInst_getNumOperands(MI) == 3 &&
2940
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2941
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2942
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2943
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2944
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2945
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2946
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2947
0
      AsmString = "fmovsne %icc, $\x02, $\x01";
2948
0
      break;
2949
0
    }
2950
11
    if (MCInst_getNumOperands(MI) == 3 &&
2951
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2952
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2953
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2954
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2955
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2956
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2957
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2958
0
      AsmString = "fmovse %icc, $\x02, $\x01";
2959
0
      break;
2960
0
    }
2961
11
    if (MCInst_getNumOperands(MI) == 3 &&
2962
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2963
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2964
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2965
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2966
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2967
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2968
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2969
0
      AsmString = "fmovsg %icc, $\x02, $\x01";
2970
0
      break;
2971
0
    }
2972
11
    if (MCInst_getNumOperands(MI) == 3 &&
2973
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2974
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2975
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2976
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2977
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2978
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2979
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2980
0
      AsmString = "fmovsle %icc, $\x02, $\x01";
2981
0
      break;
2982
0
    }
2983
11
    if (MCInst_getNumOperands(MI) == 3 &&
2984
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2985
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2986
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2987
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2988
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2989
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2990
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2991
0
      AsmString = "fmovsge %icc, $\x02, $\x01";
2992
0
      break;
2993
0
    }
2994
11
    if (MCInst_getNumOperands(MI) == 3 &&
2995
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2996
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2997
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2998
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2999
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3000
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3001
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3002
0
      AsmString = "fmovsl %icc, $\x02, $\x01";
3003
0
      break;
3004
0
    }
3005
11
    if (MCInst_getNumOperands(MI) == 3 &&
3006
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3007
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3008
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3009
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3010
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3011
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3012
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3013
0
      AsmString = "fmovsgu %icc, $\x02, $\x01";
3014
0
      break;
3015
0
    }
3016
11
    if (MCInst_getNumOperands(MI) == 3 &&
3017
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3018
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3019
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3020
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3021
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3022
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3023
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3024
0
      AsmString = "fmovsleu %icc, $\x02, $\x01";
3025
0
      break;
3026
0
    }
3027
11
    if (MCInst_getNumOperands(MI) == 3 &&
3028
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3029
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3030
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3031
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3032
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3033
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3034
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3035
0
      AsmString = "fmovscc %icc, $\x02, $\x01";
3036
0
      break;
3037
0
    }
3038
11
    if (MCInst_getNumOperands(MI) == 3 &&
3039
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3040
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3041
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3042
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3043
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3044
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3045
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3046
0
      AsmString = "fmovscs %icc, $\x02, $\x01";
3047
0
      break;
3048
0
    }
3049
11
    if (MCInst_getNumOperands(MI) == 3 &&
3050
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3051
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3052
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3053
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3054
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3055
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3056
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3057
0
      AsmString = "fmovspos %icc, $\x02, $\x01";
3058
0
      break;
3059
0
    }
3060
11
    if (MCInst_getNumOperands(MI) == 3 &&
3061
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3062
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3063
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3064
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3065
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3066
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3067
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3068
0
      AsmString = "fmovsneg %icc, $\x02, $\x01";
3069
0
      break;
3070
0
    }
3071
11
    if (MCInst_getNumOperands(MI) == 3 &&
3072
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3073
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3074
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3075
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3076
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3077
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3078
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3079
0
      AsmString = "fmovsvc %icc, $\x02, $\x01";
3080
0
      break;
3081
0
    }
3082
11
    if (MCInst_getNumOperands(MI) == 3 &&
3083
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3084
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3085
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3086
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3087
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3088
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3089
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3090
0
      AsmString = "fmovsvs %icc, $\x02, $\x01";
3091
0
      break;
3092
0
    }
3093
11
    return NULL;
3094
3
  case SP_FMOVS_XCC:
3095
3
    if (MCInst_getNumOperands(MI) == 3 &&
3096
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3097
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3098
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3099
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3100
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3101
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3102
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3103
0
      AsmString = "fmovsa %xcc, $\x02, $\x01";
3104
0
      break;
3105
0
    }
3106
3
    if (MCInst_getNumOperands(MI) == 3 &&
3107
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3108
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3109
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3110
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3111
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3112
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3113
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3114
0
      AsmString = "fmovsn %xcc, $\x02, $\x01";
3115
0
      break;
3116
0
    }
3117
3
    if (MCInst_getNumOperands(MI) == 3 &&
3118
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3119
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3120
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3121
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3122
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3123
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3124
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3125
0
      AsmString = "fmovsne %xcc, $\x02, $\x01";
3126
0
      break;
3127
0
    }
3128
3
    if (MCInst_getNumOperands(MI) == 3 &&
3129
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3130
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3131
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3132
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3133
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3134
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3135
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3136
0
      AsmString = "fmovse %xcc, $\x02, $\x01";
3137
0
      break;
3138
0
    }
3139
3
    if (MCInst_getNumOperands(MI) == 3 &&
3140
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3141
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3142
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3143
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3144
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3145
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3146
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3147
0
      AsmString = "fmovsg %xcc, $\x02, $\x01";
3148
0
      break;
3149
0
    }
3150
3
    if (MCInst_getNumOperands(MI) == 3 &&
3151
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3152
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3153
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3154
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3155
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3156
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3157
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3158
0
      AsmString = "fmovsle %xcc, $\x02, $\x01";
3159
0
      break;
3160
0
    }
3161
3
    if (MCInst_getNumOperands(MI) == 3 &&
3162
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3163
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3164
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3165
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3166
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3167
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3168
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3169
0
      AsmString = "fmovsge %xcc, $\x02, $\x01";
3170
0
      break;
3171
0
    }
3172
3
    if (MCInst_getNumOperands(MI) == 3 &&
3173
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3174
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3175
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3176
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3177
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3178
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3179
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3180
0
      AsmString = "fmovsl %xcc, $\x02, $\x01";
3181
0
      break;
3182
0
    }
3183
3
    if (MCInst_getNumOperands(MI) == 3 &&
3184
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3185
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3186
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3187
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3188
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3190
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3191
0
      AsmString = "fmovsgu %xcc, $\x02, $\x01";
3192
0
      break;
3193
0
    }
3194
3
    if (MCInst_getNumOperands(MI) == 3 &&
3195
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3196
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3197
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3198
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3199
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3200
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3201
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3202
0
      AsmString = "fmovsleu %xcc, $\x02, $\x01";
3203
0
      break;
3204
0
    }
3205
3
    if (MCInst_getNumOperands(MI) == 3 &&
3206
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3207
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3208
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3209
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3210
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3211
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3212
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3213
0
      AsmString = "fmovscc %xcc, $\x02, $\x01";
3214
0
      break;
3215
0
    }
3216
3
    if (MCInst_getNumOperands(MI) == 3 &&
3217
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3218
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3219
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3220
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3221
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3222
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3223
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3224
0
      AsmString = "fmovscs %xcc, $\x02, $\x01";
3225
0
      break;
3226
0
    }
3227
3
    if (MCInst_getNumOperands(MI) == 3 &&
3228
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3229
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3230
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3231
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3232
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3233
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3234
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3235
0
      AsmString = "fmovspos %xcc, $\x02, $\x01";
3236
0
      break;
3237
0
    }
3238
3
    if (MCInst_getNumOperands(MI) == 3 &&
3239
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3240
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3241
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3242
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3243
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3244
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3245
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3246
0
      AsmString = "fmovsneg %xcc, $\x02, $\x01";
3247
0
      break;
3248
0
    }
3249
3
    if (MCInst_getNumOperands(MI) == 3 &&
3250
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3251
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3252
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3253
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3254
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3255
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3256
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3257
0
      AsmString = "fmovsvc %xcc, $\x02, $\x01";
3258
0
      break;
3259
0
    }
3260
3
    if (MCInst_getNumOperands(MI) == 3 &&
3261
3
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3262
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3263
3
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3264
3
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3265
3
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3266
3
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3267
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3268
0
      AsmString = "fmovsvs %xcc, $\x02, $\x01";
3269
0
      break;
3270
0
    }
3271
3
    return NULL;
3272
16
  case SP_MOVICCri:
3273
16
    if (MCInst_getNumOperands(MI) == 3 &&
3274
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3275
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3276
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3277
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3278
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3279
0
      AsmString = "mova %icc, $\x02, $\x01";
3280
0
      break;
3281
0
    }
3282
16
    if (MCInst_getNumOperands(MI) == 3 &&
3283
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3284
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3285
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3286
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3287
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3288
0
      AsmString = "movn %icc, $\x02, $\x01";
3289
0
      break;
3290
0
    }
3291
16
    if (MCInst_getNumOperands(MI) == 3 &&
3292
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3293
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3294
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3295
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3296
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3297
0
      AsmString = "movne %icc, $\x02, $\x01";
3298
0
      break;
3299
0
    }
3300
16
    if (MCInst_getNumOperands(MI) == 3 &&
3301
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3302
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3303
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3304
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3305
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3306
0
      AsmString = "move %icc, $\x02, $\x01";
3307
0
      break;
3308
0
    }
3309
16
    if (MCInst_getNumOperands(MI) == 3 &&
3310
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3311
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3312
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3313
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3314
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3315
0
      AsmString = "movg %icc, $\x02, $\x01";
3316
0
      break;
3317
0
    }
3318
16
    if (MCInst_getNumOperands(MI) == 3 &&
3319
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3320
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3321
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3322
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3323
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3324
0
      AsmString = "movle %icc, $\x02, $\x01";
3325
0
      break;
3326
0
    }
3327
16
    if (MCInst_getNumOperands(MI) == 3 &&
3328
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3329
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3330
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3331
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3332
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3333
0
      AsmString = "movge %icc, $\x02, $\x01";
3334
0
      break;
3335
0
    }
3336
16
    if (MCInst_getNumOperands(MI) == 3 &&
3337
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3338
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3339
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3340
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3341
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3342
0
      AsmString = "movl %icc, $\x02, $\x01";
3343
0
      break;
3344
0
    }
3345
16
    if (MCInst_getNumOperands(MI) == 3 &&
3346
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3347
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3348
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3349
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3350
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3351
0
      AsmString = "movgu %icc, $\x02, $\x01";
3352
0
      break;
3353
0
    }
3354
16
    if (MCInst_getNumOperands(MI) == 3 &&
3355
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3356
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3357
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3358
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3359
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3360
0
      AsmString = "movleu %icc, $\x02, $\x01";
3361
0
      break;
3362
0
    }
3363
16
    if (MCInst_getNumOperands(MI) == 3 &&
3364
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3365
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3366
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3367
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3368
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3369
0
      AsmString = "movcc %icc, $\x02, $\x01";
3370
0
      break;
3371
0
    }
3372
16
    if (MCInst_getNumOperands(MI) == 3 &&
3373
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3374
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3375
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3376
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3377
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3378
0
      AsmString = "movcs %icc, $\x02, $\x01";
3379
0
      break;
3380
0
    }
3381
16
    if (MCInst_getNumOperands(MI) == 3 &&
3382
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3383
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3384
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3385
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3386
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3387
0
      AsmString = "movpos %icc, $\x02, $\x01";
3388
0
      break;
3389
0
    }
3390
16
    if (MCInst_getNumOperands(MI) == 3 &&
3391
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3392
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3393
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3394
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3395
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3396
0
      AsmString = "movneg %icc, $\x02, $\x01";
3397
0
      break;
3398
0
    }
3399
16
    if (MCInst_getNumOperands(MI) == 3 &&
3400
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3401
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3402
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3403
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3404
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3405
0
      AsmString = "movvc %icc, $\x02, $\x01";
3406
0
      break;
3407
0
    }
3408
16
    if (MCInst_getNumOperands(MI) == 3 &&
3409
16
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3410
16
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3411
16
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3412
16
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3413
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3414
0
      AsmString = "movvs %icc, $\x02, $\x01";
3415
0
      break;
3416
0
    }
3417
16
    return NULL;
3418
8
  case SP_MOVICCrr:
3419
8
    if (MCInst_getNumOperands(MI) == 3 &&
3420
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3421
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3422
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3423
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3424
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3425
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3426
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3427
0
      AsmString = "mova %icc, $\x02, $\x01";
3428
0
      break;
3429
0
    }
3430
8
    if (MCInst_getNumOperands(MI) == 3 &&
3431
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3432
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3433
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3434
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3435
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3436
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3437
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3438
0
      AsmString = "movn %icc, $\x02, $\x01";
3439
0
      break;
3440
0
    }
3441
8
    if (MCInst_getNumOperands(MI) == 3 &&
3442
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3443
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3444
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3445
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3446
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3447
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3448
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3449
0
      AsmString = "movne %icc, $\x02, $\x01";
3450
0
      break;
3451
0
    }
3452
8
    if (MCInst_getNumOperands(MI) == 3 &&
3453
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3454
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3455
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3456
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3457
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3458
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3459
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3460
0
      AsmString = "move %icc, $\x02, $\x01";
3461
0
      break;
3462
0
    }
3463
8
    if (MCInst_getNumOperands(MI) == 3 &&
3464
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3465
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3466
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3467
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3468
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3469
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3470
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3471
0
      AsmString = "movg %icc, $\x02, $\x01";
3472
0
      break;
3473
0
    }
3474
8
    if (MCInst_getNumOperands(MI) == 3 &&
3475
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3476
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3477
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3478
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3479
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3480
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3481
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3482
0
      AsmString = "movle %icc, $\x02, $\x01";
3483
0
      break;
3484
0
    }
3485
8
    if (MCInst_getNumOperands(MI) == 3 &&
3486
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3487
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3488
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3489
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3490
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3491
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3492
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3493
0
      AsmString = "movge %icc, $\x02, $\x01";
3494
0
      break;
3495
0
    }
3496
8
    if (MCInst_getNumOperands(MI) == 3 &&
3497
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3498
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3499
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3500
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3501
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3502
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3503
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3504
0
      AsmString = "movl %icc, $\x02, $\x01";
3505
0
      break;
3506
0
    }
3507
8
    if (MCInst_getNumOperands(MI) == 3 &&
3508
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3509
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3510
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3511
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3512
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3513
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3514
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3515
0
      AsmString = "movgu %icc, $\x02, $\x01";
3516
0
      break;
3517
0
    }
3518
8
    if (MCInst_getNumOperands(MI) == 3 &&
3519
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3520
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3521
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3522
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3523
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3524
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3525
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3526
0
      AsmString = "movleu %icc, $\x02, $\x01";
3527
0
      break;
3528
0
    }
3529
8
    if (MCInst_getNumOperands(MI) == 3 &&
3530
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3531
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3532
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3533
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3534
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3535
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3536
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3537
0
      AsmString = "movcc %icc, $\x02, $\x01";
3538
0
      break;
3539
0
    }
3540
8
    if (MCInst_getNumOperands(MI) == 3 &&
3541
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3542
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3543
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3544
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3545
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3546
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3547
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3548
0
      AsmString = "movcs %icc, $\x02, $\x01";
3549
0
      break;
3550
0
    }
3551
8
    if (MCInst_getNumOperands(MI) == 3 &&
3552
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3553
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3554
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3555
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3556
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3557
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3558
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3559
0
      AsmString = "movpos %icc, $\x02, $\x01";
3560
0
      break;
3561
0
    }
3562
8
    if (MCInst_getNumOperands(MI) == 3 &&
3563
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3564
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3565
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3566
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3567
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3568
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3569
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3570
0
      AsmString = "movneg %icc, $\x02, $\x01";
3571
0
      break;
3572
0
    }
3573
8
    if (MCInst_getNumOperands(MI) == 3 &&
3574
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3575
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3576
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3577
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3578
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3579
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3580
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3581
0
      AsmString = "movvc %icc, $\x02, $\x01";
3582
0
      break;
3583
0
    }
3584
8
    if (MCInst_getNumOperands(MI) == 3 &&
3585
8
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3586
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3587
8
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3588
8
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3589
8
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3590
8
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3591
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3592
0
      AsmString = "movvs %icc, $\x02, $\x01";
3593
0
      break;
3594
0
    }
3595
8
    return NULL;
3596
37
  case SP_MOVXCCri:
3597
37
    if (MCInst_getNumOperands(MI) == 3 &&
3598
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3599
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3600
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3601
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3602
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3603
0
      AsmString = "mova %xcc, $\x02, $\x01";
3604
0
      break;
3605
0
    }
3606
37
    if (MCInst_getNumOperands(MI) == 3 &&
3607
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3608
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3609
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3610
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3611
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3612
0
      AsmString = "movn %xcc, $\x02, $\x01";
3613
0
      break;
3614
0
    }
3615
37
    if (MCInst_getNumOperands(MI) == 3 &&
3616
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3617
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3618
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3619
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3620
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3621
0
      AsmString = "movne %xcc, $\x02, $\x01";
3622
0
      break;
3623
0
    }
3624
37
    if (MCInst_getNumOperands(MI) == 3 &&
3625
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3626
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3627
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3628
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3629
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3630
0
      AsmString = "move %xcc, $\x02, $\x01";
3631
0
      break;
3632
0
    }
3633
37
    if (MCInst_getNumOperands(MI) == 3 &&
3634
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3635
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3636
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3637
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3638
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3639
0
      AsmString = "movg %xcc, $\x02, $\x01";
3640
0
      break;
3641
0
    }
3642
37
    if (MCInst_getNumOperands(MI) == 3 &&
3643
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3644
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3645
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3646
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3647
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3648
0
      AsmString = "movle %xcc, $\x02, $\x01";
3649
0
      break;
3650
0
    }
3651
37
    if (MCInst_getNumOperands(MI) == 3 &&
3652
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3653
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3654
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3655
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3656
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3657
0
      AsmString = "movge %xcc, $\x02, $\x01";
3658
0
      break;
3659
0
    }
3660
37
    if (MCInst_getNumOperands(MI) == 3 &&
3661
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3662
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3663
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3664
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3665
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3666
0
      AsmString = "movl %xcc, $\x02, $\x01";
3667
0
      break;
3668
0
    }
3669
37
    if (MCInst_getNumOperands(MI) == 3 &&
3670
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3671
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3672
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3673
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3674
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3675
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3676
0
      break;
3677
0
    }
3678
37
    if (MCInst_getNumOperands(MI) == 3 &&
3679
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3680
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3681
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3682
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3683
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3684
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3685
0
      break;
3686
0
    }
3687
37
    if (MCInst_getNumOperands(MI) == 3 &&
3688
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3689
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3690
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3691
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3692
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3693
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3694
0
      break;
3695
0
    }
3696
37
    if (MCInst_getNumOperands(MI) == 3 &&
3697
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3698
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3699
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3700
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3701
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3702
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3703
0
      break;
3704
0
    }
3705
37
    if (MCInst_getNumOperands(MI) == 3 &&
3706
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3707
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3708
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3709
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3710
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3711
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3712
0
      break;
3713
0
    }
3714
37
    if (MCInst_getNumOperands(MI) == 3 &&
3715
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3716
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3717
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3718
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3719
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3720
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3721
0
      break;
3722
0
    }
3723
37
    if (MCInst_getNumOperands(MI) == 3 &&
3724
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3725
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3726
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3727
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3728
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3729
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3730
0
      break;
3731
0
    }
3732
37
    if (MCInst_getNumOperands(MI) == 3 &&
3733
37
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3734
37
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3735
37
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3736
37
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3737
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3738
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3739
0
      break;
3740
0
    }
3741
37
    return NULL;
3742
10
  case SP_MOVXCCrr:
3743
10
    if (MCInst_getNumOperands(MI) == 3 &&
3744
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3745
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3746
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3747
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3748
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3749
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3750
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3751
0
      AsmString = "mova %xcc, $\x02, $\x01";
3752
0
      break;
3753
0
    }
3754
10
    if (MCInst_getNumOperands(MI) == 3 &&
3755
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3756
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3757
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3758
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3759
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3760
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3761
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3762
0
      AsmString = "movn %xcc, $\x02, $\x01";
3763
0
      break;
3764
0
    }
3765
10
    if (MCInst_getNumOperands(MI) == 3 &&
3766
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3767
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3768
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3769
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3770
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3771
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3772
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3773
0
      AsmString = "movne %xcc, $\x02, $\x01";
3774
0
      break;
3775
0
    }
3776
10
    if (MCInst_getNumOperands(MI) == 3 &&
3777
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3778
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3779
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3780
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3781
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3782
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3783
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3784
0
      AsmString = "move %xcc, $\x02, $\x01";
3785
0
      break;
3786
0
    }
3787
10
    if (MCInst_getNumOperands(MI) == 3 &&
3788
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3789
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3790
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3791
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3792
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3793
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3794
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3795
0
      AsmString = "movg %xcc, $\x02, $\x01";
3796
0
      break;
3797
0
    }
3798
10
    if (MCInst_getNumOperands(MI) == 3 &&
3799
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3800
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3801
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3802
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3803
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3804
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3805
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3806
0
      AsmString = "movle %xcc, $\x02, $\x01";
3807
0
      break;
3808
0
    }
3809
10
    if (MCInst_getNumOperands(MI) == 3 &&
3810
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3811
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3812
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3813
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3814
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3815
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3816
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3817
0
      AsmString = "movge %xcc, $\x02, $\x01";
3818
0
      break;
3819
0
    }
3820
10
    if (MCInst_getNumOperands(MI) == 3 &&
3821
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3822
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3823
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3824
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3825
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3826
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3827
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3828
0
      AsmString = "movl %xcc, $\x02, $\x01";
3829
0
      break;
3830
0
    }
3831
10
    if (MCInst_getNumOperands(MI) == 3 &&
3832
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3833
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3834
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3835
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3836
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3837
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3838
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3839
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3840
0
      break;
3841
0
    }
3842
10
    if (MCInst_getNumOperands(MI) == 3 &&
3843
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3844
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3845
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3846
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3847
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3848
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3849
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3850
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3851
0
      break;
3852
0
    }
3853
10
    if (MCInst_getNumOperands(MI) == 3 &&
3854
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3855
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3856
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3857
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3858
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3859
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3860
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3861
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3862
0
      break;
3863
0
    }
3864
10
    if (MCInst_getNumOperands(MI) == 3 &&
3865
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3866
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3867
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3868
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3869
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3870
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3871
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3872
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3873
0
      break;
3874
0
    }
3875
10
    if (MCInst_getNumOperands(MI) == 3 &&
3876
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3877
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3878
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3879
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3880
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3881
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3882
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3883
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3884
0
      break;
3885
0
    }
3886
10
    if (MCInst_getNumOperands(MI) == 3 &&
3887
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3888
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3889
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3890
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3891
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3892
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3893
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3894
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3895
0
      break;
3896
0
    }
3897
10
    if (MCInst_getNumOperands(MI) == 3 &&
3898
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3899
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3900
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3901
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3902
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3903
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3904
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3905
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3906
0
      break;
3907
0
    }
3908
10
    if (MCInst_getNumOperands(MI) == 3 &&
3909
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3910
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3911
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3912
10
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3913
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3914
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3915
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3916
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3917
0
      break;
3918
0
    }
3919
10
    return NULL;
3920
58
  case SP_ORri:
3921
58
    if (MCInst_getNumOperands(MI) == 3 &&
3922
58
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3923
58
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3924
58
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3925
      // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3926
26
      AsmString = "mov $\x03, $\x01";
3927
26
      break;
3928
26
    }
3929
32
    return NULL;
3930
31
  case SP_ORrr:
3931
31
    if (MCInst_getNumOperands(MI) == 3 &&
3932
31
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3933
31
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3934
31
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3935
31
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3936
31
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3937
      // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3938
12
      AsmString = "mov $\x03, $\x01";
3939
12
      break;
3940
12
    }
3941
19
    return NULL;
3942
23
  case SP_RESTORErr:
3943
23
    if (MCInst_getNumOperands(MI) == 3 &&
3944
23
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3945
23
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3946
23
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3947
      // (RESTORErr G0, G0, G0)
3948
5
      AsmString = "restore";
3949
5
      break;
3950
5
    }
3951
18
    return NULL;
3952
0
  case SP_RET:
3953
0
    if (MCInst_getNumOperands(MI) == 1 &&
3954
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3955
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3956
      // (RET 8)
3957
0
      AsmString = "ret";
3958
0
      break;
3959
0
    }
3960
0
    return NULL;
3961
0
  case SP_RETL:
3962
0
    if (MCInst_getNumOperands(MI) == 1 &&
3963
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3964
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3965
      // (RETL 8)
3966
0
      AsmString = "retl";
3967
0
      break;
3968
0
    }
3969
0
    return NULL;
3970
619
  case SP_TXCCri:
3971
619
    if (MCInst_getNumOperands(MI) == 3 &&
3972
619
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3973
619
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3974
619
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3975
619
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3976
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3977
20
      AsmString = "ta %xcc, $\x01 + $\x02";
3978
20
      break;
3979
20
    }
3980
599
    if (MCInst_getNumOperands(MI) == 3 &&
3981
599
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3982
599
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3983
599
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3984
      // (TXCCri G0, i32imm:$imm, 8)
3985
0
      AsmString = "ta %xcc, $\x02";
3986
0
      break;
3987
0
    }
3988
599
    if (MCInst_getNumOperands(MI) == 3 &&
3989
599
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3990
599
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3991
599
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3992
599
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3993
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3994
54
      AsmString = "tn %xcc, $\x01 + $\x02";
3995
54
      break;
3996
54
    }
3997
545
    if (MCInst_getNumOperands(MI) == 3 &&
3998
545
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3999
545
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4000
545
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4001
      // (TXCCri G0, i32imm:$imm, 0)
4002
0
      AsmString = "tn %xcc, $\x02";
4003
0
      break;
4004
0
    }
4005
545
    if (MCInst_getNumOperands(MI) == 3 &&
4006
545
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4007
545
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4008
545
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4009
545
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4010
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4011
56
      AsmString = "tne %xcc, $\x01 + $\x02";
4012
56
      break;
4013
56
    }
4014
489
    if (MCInst_getNumOperands(MI) == 3 &&
4015
489
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4016
489
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4017
489
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4018
      // (TXCCri G0, i32imm:$imm, 9)
4019
0
      AsmString = "tne %xcc, $\x02";
4020
0
      break;
4021
0
    }
4022
489
    if (MCInst_getNumOperands(MI) == 3 &&
4023
489
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4024
489
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4025
489
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4026
489
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4027
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4028
17
      AsmString = "te %xcc, $\x01 + $\x02";
4029
17
      break;
4030
17
    }
4031
472
    if (MCInst_getNumOperands(MI) == 3 &&
4032
472
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4033
472
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4034
472
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4035
      // (TXCCri G0, i32imm:$imm, 1)
4036
0
      AsmString = "te %xcc, $\x02";
4037
0
      break;
4038
0
    }
4039
472
    if (MCInst_getNumOperands(MI) == 3 &&
4040
472
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4041
472
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4042
472
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4043
472
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4044
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4045
61
      AsmString = "tg %xcc, $\x01 + $\x02";
4046
61
      break;
4047
61
    }
4048
411
    if (MCInst_getNumOperands(MI) == 3 &&
4049
411
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4050
411
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4051
411
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4052
      // (TXCCri G0, i32imm:$imm, 10)
4053
0
      AsmString = "tg %xcc, $\x02";
4054
0
      break;
4055
0
    }
4056
411
    if (MCInst_getNumOperands(MI) == 3 &&
4057
411
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4058
411
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4059
411
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4060
411
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4061
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4062
19
      AsmString = "tle %xcc, $\x01 + $\x02";
4063
19
      break;
4064
19
    }
4065
392
    if (MCInst_getNumOperands(MI) == 3 &&
4066
392
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4067
392
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4068
392
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4069
      // (TXCCri G0, i32imm:$imm, 2)
4070
0
      AsmString = "tle %xcc, $\x02";
4071
0
      break;
4072
0
    }
4073
392
    if (MCInst_getNumOperands(MI) == 3 &&
4074
392
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4075
392
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4076
392
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4077
392
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4078
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4079
148
      AsmString = "tge %xcc, $\x01 + $\x02";
4080
148
      break;
4081
148
    }
4082
244
    if (MCInst_getNumOperands(MI) == 3 &&
4083
244
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4084
244
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4085
244
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4086
      // (TXCCri G0, i32imm:$imm, 11)
4087
0
      AsmString = "tge %xcc, $\x02";
4088
0
      break;
4089
0
    }
4090
244
    if (MCInst_getNumOperands(MI) == 3 &&
4091
244
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4092
244
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4093
244
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4094
244
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4095
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4096
3
      AsmString = "tl %xcc, $\x01 + $\x02";
4097
3
      break;
4098
3
    }
4099
241
    if (MCInst_getNumOperands(MI) == 3 &&
4100
241
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4101
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4102
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4103
      // (TXCCri G0, i32imm:$imm, 3)
4104
0
      AsmString = "tl %xcc, $\x02";
4105
0
      break;
4106
0
    }
4107
241
    if (MCInst_getNumOperands(MI) == 3 &&
4108
241
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4109
241
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4110
241
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4111
241
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4112
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4113
28
      AsmString = "tgu %xcc, $\x01 + $\x02";
4114
28
      break;
4115
28
    }
4116
213
    if (MCInst_getNumOperands(MI) == 3 &&
4117
213
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4118
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4119
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4120
      // (TXCCri G0, i32imm:$imm, 12)
4121
0
      AsmString = "tgu %xcc, $\x02";
4122
0
      break;
4123
0
    }
4124
213
    if (MCInst_getNumOperands(MI) == 3 &&
4125
213
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4126
213
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4127
213
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4128
213
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4129
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4130
3
      AsmString = "tleu %xcc, $\x01 + $\x02";
4131
3
      break;
4132
3
    }
4133
210
    if (MCInst_getNumOperands(MI) == 3 &&
4134
210
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4135
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4136
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4137
      // (TXCCri G0, i32imm:$imm, 4)
4138
0
      AsmString = "tleu %xcc, $\x02";
4139
0
      break;
4140
0
    }
4141
210
    if (MCInst_getNumOperands(MI) == 3 &&
4142
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4143
210
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4144
210
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4145
210
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4146
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4147
59
      AsmString = "tcc %xcc, $\x01 + $\x02";
4148
59
      break;
4149
59
    }
4150
151
    if (MCInst_getNumOperands(MI) == 3 &&
4151
151
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4152
151
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4153
151
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4154
      // (TXCCri G0, i32imm:$imm, 13)
4155
0
      AsmString = "tcc %xcc, $\x02";
4156
0
      break;
4157
0
    }
4158
151
    if (MCInst_getNumOperands(MI) == 3 &&
4159
151
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4160
151
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4161
151
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4162
151
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4163
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4164
3
      AsmString = "tcs %xcc, $\x01 + $\x02";
4165
3
      break;
4166
3
    }
4167
148
    if (MCInst_getNumOperands(MI) == 3 &&
4168
148
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4169
148
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4170
148
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4171
      // (TXCCri G0, i32imm:$imm, 5)
4172
0
      AsmString = "tcs %xcc, $\x02";
4173
0
      break;
4174
0
    }
4175
148
    if (MCInst_getNumOperands(MI) == 3 &&
4176
148
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4177
148
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4178
148
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4179
148
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4180
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4181
2
      AsmString = "tpos %xcc, $\x01 + $\x02";
4182
2
      break;
4183
2
    }
4184
146
    if (MCInst_getNumOperands(MI) == 3 &&
4185
146
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4186
146
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4187
146
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4188
      // (TXCCri G0, i32imm:$imm, 14)
4189
0
      AsmString = "tpos %xcc, $\x02";
4190
0
      break;
4191
0
    }
4192
146
    if (MCInst_getNumOperands(MI) == 3 &&
4193
146
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4194
146
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4195
146
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4196
146
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4197
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4198
17
      AsmString = "tneg %xcc, $\x01 + $\x02";
4199
17
      break;
4200
17
    }
4201
129
    if (MCInst_getNumOperands(MI) == 3 &&
4202
129
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4203
129
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4204
129
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4205
      // (TXCCri G0, i32imm:$imm, 6)
4206
0
      AsmString = "tneg %xcc, $\x02";
4207
0
      break;
4208
0
    }
4209
129
    if (MCInst_getNumOperands(MI) == 3 &&
4210
129
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4211
129
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4212
129
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4213
129
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4214
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4215
50
      AsmString = "tvc %xcc, $\x01 + $\x02";
4216
50
      break;
4217
50
    }
4218
79
    if (MCInst_getNumOperands(MI) == 3 &&
4219
79
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4220
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4221
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4222
      // (TXCCri G0, i32imm:$imm, 15)
4223
0
      AsmString = "tvc %xcc, $\x02";
4224
0
      break;
4225
0
    }
4226
79
    if (MCInst_getNumOperands(MI) == 3 &&
4227
79
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4228
79
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4229
79
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4230
79
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4231
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4232
79
      AsmString = "tvs %xcc, $\x01 + $\x02";
4233
79
      break;
4234
79
    }
4235
0
    if (MCInst_getNumOperands(MI) == 3 &&
4236
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4237
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4238
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4239
      // (TXCCri G0, i32imm:$imm, 7)
4240
0
      AsmString = "tvs %xcc, $\x02";
4241
0
      break;
4242
0
    }
4243
0
    return NULL;
4244
544
  case SP_TXCCrr:
4245
544
    if (MCInst_getNumOperands(MI) == 3 &&
4246
544
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4247
544
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4248
544
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4249
544
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4250
544
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4251
544
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4252
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4253
58
      AsmString = "ta %xcc, $\x01 + $\x02";
4254
58
      break;
4255
58
    }
4256
486
    if (MCInst_getNumOperands(MI) == 3 &&
4257
486
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4258
486
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4259
486
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4260
486
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4261
486
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4262
      // (TXCCrr G0, IntRegs:$rs2, 8)
4263
0
      AsmString = "ta %xcc, $\x02";
4264
0
      break;
4265
0
    }
4266
486
    if (MCInst_getNumOperands(MI) == 3 &&
4267
486
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4268
486
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4269
486
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4270
486
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4271
486
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4272
486
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4273
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4274
53
      AsmString = "tn %xcc, $\x01 + $\x02";
4275
53
      break;
4276
53
    }
4277
433
    if (MCInst_getNumOperands(MI) == 3 &&
4278
433
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4279
433
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4280
433
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4281
433
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4282
433
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4283
      // (TXCCrr G0, IntRegs:$rs2, 0)
4284
0
      AsmString = "tn %xcc, $\x02";
4285
0
      break;
4286
0
    }
4287
433
    if (MCInst_getNumOperands(MI) == 3 &&
4288
433
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4289
433
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4290
433
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4291
433
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4292
433
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4293
433
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4294
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4295
4
      AsmString = "tne %xcc, $\x01 + $\x02";
4296
4
      break;
4297
4
    }
4298
429
    if (MCInst_getNumOperands(MI) == 3 &&
4299
429
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4300
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4301
429
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4302
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4303
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4304
      // (TXCCrr G0, IntRegs:$rs2, 9)
4305
0
      AsmString = "tne %xcc, $\x02";
4306
0
      break;
4307
0
    }
4308
429
    if (MCInst_getNumOperands(MI) == 3 &&
4309
429
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4310
429
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4311
429
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4312
429
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4313
429
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4314
429
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4315
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4316
95
      AsmString = "te %xcc, $\x01 + $\x02";
4317
95
      break;
4318
95
    }
4319
334
    if (MCInst_getNumOperands(MI) == 3 &&
4320
334
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4321
334
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4322
334
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4323
334
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4324
334
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4325
      // (TXCCrr G0, IntRegs:$rs2, 1)
4326
0
      AsmString = "te %xcc, $\x02";
4327
0
      break;
4328
0
    }
4329
334
    if (MCInst_getNumOperands(MI) == 3 &&
4330
334
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4331
334
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4332
334
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4333
334
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4334
334
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4335
334
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4336
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4337
102
      AsmString = "tg %xcc, $\x01 + $\x02";
4338
102
      break;
4339
102
    }
4340
232
    if (MCInst_getNumOperands(MI) == 3 &&
4341
232
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4342
232
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4343
232
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4344
232
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4345
232
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4346
      // (TXCCrr G0, IntRegs:$rs2, 10)
4347
0
      AsmString = "tg %xcc, $\x02";
4348
0
      break;
4349
0
    }
4350
232
    if (MCInst_getNumOperands(MI) == 3 &&
4351
232
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4352
232
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4353
232
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4354
232
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4355
232
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4356
232
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4357
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4358
6
      AsmString = "tle %xcc, $\x01 + $\x02";
4359
6
      break;
4360
6
    }
4361
226
    if (MCInst_getNumOperands(MI) == 3 &&
4362
226
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4363
226
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4364
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4365
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4366
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4367
      // (TXCCrr G0, IntRegs:$rs2, 2)
4368
0
      AsmString = "tle %xcc, $\x02";
4369
0
      break;
4370
0
    }
4371
226
    if (MCInst_getNumOperands(MI) == 3 &&
4372
226
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4373
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4374
226
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4375
226
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4376
226
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4377
226
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4378
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4379
5
      AsmString = "tge %xcc, $\x01 + $\x02";
4380
5
      break;
4381
5
    }
4382
221
    if (MCInst_getNumOperands(MI) == 3 &&
4383
221
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4384
221
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4385
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4386
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4387
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4388
      // (TXCCrr G0, IntRegs:$rs2, 11)
4389
0
      AsmString = "tge %xcc, $\x02";
4390
0
      break;
4391
0
    }
4392
221
    if (MCInst_getNumOperands(MI) == 3 &&
4393
221
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4394
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4395
221
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4396
221
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4397
221
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4398
221
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4399
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4400
10
      AsmString = "tl %xcc, $\x01 + $\x02";
4401
10
      break;
4402
10
    }
4403
211
    if (MCInst_getNumOperands(MI) == 3 &&
4404
211
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4405
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4406
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4407
211
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4408
211
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4409
      // (TXCCrr G0, IntRegs:$rs2, 3)
4410
0
      AsmString = "tl %xcc, $\x02";
4411
0
      break;
4412
0
    }
4413
211
    if (MCInst_getNumOperands(MI) == 3 &&
4414
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4415
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4416
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4417
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4418
211
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4419
211
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4420
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4421
49
      AsmString = "tgu %xcc, $\x01 + $\x02";
4422
49
      break;
4423
49
    }
4424
162
    if (MCInst_getNumOperands(MI) == 3 &&
4425
162
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4426
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4427
162
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4428
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4429
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4430
      // (TXCCrr G0, IntRegs:$rs2, 12)
4431
0
      AsmString = "tgu %xcc, $\x02";
4432
0
      break;
4433
0
    }
4434
162
    if (MCInst_getNumOperands(MI) == 3 &&
4435
162
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4436
162
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4437
162
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4438
162
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4439
162
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4440
162
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4441
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4442
31
      AsmString = "tleu %xcc, $\x01 + $\x02";
4443
31
      break;
4444
31
    }
4445
131
    if (MCInst_getNumOperands(MI) == 3 &&
4446
131
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4447
131
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4448
131
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4449
131
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4450
131
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4451
      // (TXCCrr G0, IntRegs:$rs2, 4)
4452
0
      AsmString = "tleu %xcc, $\x02";
4453
0
      break;
4454
0
    }
4455
131
    if (MCInst_getNumOperands(MI) == 3 &&
4456
131
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4457
131
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4458
131
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4459
131
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4460
131
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4461
131
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4462
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4463
8
      AsmString = "tcc %xcc, $\x01 + $\x02";
4464
8
      break;
4465
8
    }
4466
123
    if (MCInst_getNumOperands(MI) == 3 &&
4467
123
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4468
123
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4469
123
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4470
123
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4471
123
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4472
      // (TXCCrr G0, IntRegs:$rs2, 13)
4473
0
      AsmString = "tcc %xcc, $\x02";
4474
0
      break;
4475
0
    }
4476
123
    if (MCInst_getNumOperands(MI) == 3 &&
4477
123
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4478
123
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4479
123
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4480
123
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4481
123
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4482
123
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4483
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4484
18
      AsmString = "tcs %xcc, $\x01 + $\x02";
4485
18
      break;
4486
18
    }
4487
105
    if (MCInst_getNumOperands(MI) == 3 &&
4488
105
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4489
105
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4490
105
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4491
105
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4492
105
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4493
      // (TXCCrr G0, IntRegs:$rs2, 5)
4494
0
      AsmString = "tcs %xcc, $\x02";
4495
0
      break;
4496
0
    }
4497
105
    if (MCInst_getNumOperands(MI) == 3 &&
4498
105
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4499
105
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4500
105
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4501
105
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4502
105
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4503
105
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4504
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4505
9
      AsmString = "tpos %xcc, $\x01 + $\x02";
4506
9
      break;
4507
9
    }
4508
96
    if (MCInst_getNumOperands(MI) == 3 &&
4509
96
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4510
96
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4511
96
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4512
96
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4513
96
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4514
      // (TXCCrr G0, IntRegs:$rs2, 14)
4515
0
      AsmString = "tpos %xcc, $\x02";
4516
0
      break;
4517
0
    }
4518
96
    if (MCInst_getNumOperands(MI) == 3 &&
4519
96
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4520
96
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4521
96
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4522
96
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4523
96
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4524
96
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4525
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4526
2
      AsmString = "tneg %xcc, $\x01 + $\x02";
4527
2
      break;
4528
2
    }
4529
94
    if (MCInst_getNumOperands(MI) == 3 &&
4530
94
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4531
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4532
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4533
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4534
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4535
      // (TXCCrr G0, IntRegs:$rs2, 6)
4536
0
      AsmString = "tneg %xcc, $\x02";
4537
0
      break;
4538
0
    }
4539
94
    if (MCInst_getNumOperands(MI) == 3 &&
4540
94
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4541
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4542
94
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4543
94
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4544
94
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4545
94
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4546
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4547
22
      AsmString = "tvc %xcc, $\x01 + $\x02";
4548
22
      break;
4549
22
    }
4550
72
    if (MCInst_getNumOperands(MI) == 3 &&
4551
72
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4552
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4553
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4554
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4555
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4556
      // (TXCCrr G0, IntRegs:$rs2, 15)
4557
0
      AsmString = "tvc %xcc, $\x02";
4558
0
      break;
4559
0
    }
4560
72
    if (MCInst_getNumOperands(MI) == 3 &&
4561
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4562
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4563
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4564
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4565
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4566
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4567
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4568
72
      AsmString = "tvs %xcc, $\x01 + $\x02";
4569
72
      break;
4570
72
    }
4571
0
    if (MCInst_getNumOperands(MI) == 3 &&
4572
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4573
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4574
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4575
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4576
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4577
      // (TXCCrr G0, IntRegs:$rs2, 7)
4578
0
      AsmString = "tvs %xcc, $\x02";
4579
0
      break;
4580
0
    }
4581
0
    return NULL;
4582
41
  case SP_V9FCMPD:
4583
41
    if (MCInst_getNumOperands(MI) == 3 &&
4584
41
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4585
41
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4586
41
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4587
41
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4588
41
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4589
      // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4590
10
      AsmString = "fcmpd $\x02, $\x03";
4591
10
      break;
4592
10
    }
4593
31
    return NULL;
4594
32
  case SP_V9FCMPED:
4595
32
    if (MCInst_getNumOperands(MI) == 3 &&
4596
32
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4597
32
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4598
32
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4599
32
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4600
32
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4601
      // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4602
25
      AsmString = "fcmped $\x02, $\x03";
4603
25
      break;
4604
25
    }
4605
7
    return NULL;
4606
27
  case SP_V9FCMPEQ:
4607
27
    if (MCInst_getNumOperands(MI) == 3 &&
4608
27
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4609
27
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4610
27
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4611
27
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4612
27
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4613
      // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4614
23
      AsmString = "fcmpeq $\x02, $\x03";
4615
23
      break;
4616
23
    }
4617
4
    return NULL;
4618
79
  case SP_V9FCMPES:
4619
79
    if (MCInst_getNumOperands(MI) == 3 &&
4620
79
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4621
79
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4622
79
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4623
79
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4624
79
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4625
      // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4626
56
      AsmString = "fcmpes $\x02, $\x03";
4627
56
      break;
4628
56
    }
4629
23
    return NULL;
4630
47
  case SP_V9FCMPQ:
4631
47
    if (MCInst_getNumOperands(MI) == 3 &&
4632
47
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4633
47
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4634
47
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4635
47
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4636
47
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4637
      // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4638
23
      AsmString = "fcmpq $\x02, $\x03";
4639
23
      break;
4640
23
    }
4641
24
    return NULL;
4642
41
  case SP_V9FCMPS:
4643
41
    if (MCInst_getNumOperands(MI) == 3 &&
4644
41
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4645
41
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4646
41
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4647
41
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4648
41
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4649
      // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4650
8
      AsmString = "fcmps $\x02, $\x03";
4651
8
      break;
4652
8
    }
4653
33
    return NULL;
4654
26
  case SP_V9FMOVD_FCC:
4655
26
    if (MCInst_getNumOperands(MI) == 4 &&
4656
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4657
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4658
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4659
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4660
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4661
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4662
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4663
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4664
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4665
0
      AsmString = "fmovda $\x02, $\x03, $\x01";
4666
0
      break;
4667
0
    }
4668
26
    if (MCInst_getNumOperands(MI) == 4 &&
4669
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4670
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4671
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4672
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4673
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4674
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4675
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4676
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4677
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4678
0
      AsmString = "fmovdn $\x02, $\x03, $\x01";
4679
0
      break;
4680
0
    }
4681
26
    if (MCInst_getNumOperands(MI) == 4 &&
4682
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4683
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4684
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4685
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4686
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4687
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4688
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4689
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4690
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4691
0
      AsmString = "fmovdu $\x02, $\x03, $\x01";
4692
0
      break;
4693
0
    }
4694
26
    if (MCInst_getNumOperands(MI) == 4 &&
4695
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4696
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4697
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4698
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4699
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4700
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4701
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4702
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4703
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4704
0
      AsmString = "fmovdg $\x02, $\x03, $\x01";
4705
0
      break;
4706
0
    }
4707
26
    if (MCInst_getNumOperands(MI) == 4 &&
4708
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4709
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4710
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4711
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4712
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4713
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4714
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4715
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4716
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4717
0
      AsmString = "fmovdug $\x02, $\x03, $\x01";
4718
0
      break;
4719
0
    }
4720
26
    if (MCInst_getNumOperands(MI) == 4 &&
4721
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4722
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4723
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4724
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4725
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4726
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4727
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4728
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4729
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4730
0
      AsmString = "fmovdl $\x02, $\x03, $\x01";
4731
0
      break;
4732
0
    }
4733
26
    if (MCInst_getNumOperands(MI) == 4 &&
4734
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4735
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4736
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4737
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4738
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4739
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4740
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4741
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4742
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4743
0
      AsmString = "fmovdul $\x02, $\x03, $\x01";
4744
0
      break;
4745
0
    }
4746
26
    if (MCInst_getNumOperands(MI) == 4 &&
4747
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4748
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4749
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4750
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4751
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4752
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4753
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4754
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4755
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4756
0
      AsmString = "fmovdlg $\x02, $\x03, $\x01";
4757
0
      break;
4758
0
    }
4759
26
    if (MCInst_getNumOperands(MI) == 4 &&
4760
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4761
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4762
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4763
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4764
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4765
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4766
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4767
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4768
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4769
0
      AsmString = "fmovdne $\x02, $\x03, $\x01";
4770
0
      break;
4771
0
    }
4772
26
    if (MCInst_getNumOperands(MI) == 4 &&
4773
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4774
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4775
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4776
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4777
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4778
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4779
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4780
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4781
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4782
0
      AsmString = "fmovde $\x02, $\x03, $\x01";
4783
0
      break;
4784
0
    }
4785
26
    if (MCInst_getNumOperands(MI) == 4 &&
4786
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4787
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4788
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4789
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4790
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4791
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4792
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4793
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4794
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4795
0
      AsmString = "fmovdue $\x02, $\x03, $\x01";
4796
0
      break;
4797
0
    }
4798
26
    if (MCInst_getNumOperands(MI) == 4 &&
4799
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4800
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4801
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4802
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4803
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4804
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4805
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4806
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4807
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4808
0
      AsmString = "fmovdge $\x02, $\x03, $\x01";
4809
0
      break;
4810
0
    }
4811
26
    if (MCInst_getNumOperands(MI) == 4 &&
4812
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4813
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4814
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4815
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4816
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4817
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4818
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4819
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4820
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4821
0
      AsmString = "fmovduge $\x02, $\x03, $\x01";
4822
0
      break;
4823
0
    }
4824
26
    if (MCInst_getNumOperands(MI) == 4 &&
4825
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4826
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4827
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4828
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4829
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4830
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4831
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4832
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4833
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4834
0
      AsmString = "fmovdle $\x02, $\x03, $\x01";
4835
0
      break;
4836
0
    }
4837
26
    if (MCInst_getNumOperands(MI) == 4 &&
4838
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4839
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4840
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4841
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4842
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4843
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4844
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4845
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4846
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4847
0
      AsmString = "fmovdule $\x02, $\x03, $\x01";
4848
0
      break;
4849
0
    }
4850
26
    if (MCInst_getNumOperands(MI) == 4 &&
4851
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4852
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4853
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4854
26
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4855
26
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4856
26
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4857
26
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4858
26
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4859
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4860
0
      AsmString = "fmovdo $\x02, $\x03, $\x01";
4861
0
      break;
4862
0
    }
4863
26
    return NULL;
4864
5
  case SP_V9FMOVQ_FCC:
4865
5
    if (MCInst_getNumOperands(MI) == 4 &&
4866
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4867
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4868
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4869
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4870
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4871
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4872
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4873
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4874
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4875
0
      AsmString = "fmovqa $\x02, $\x03, $\x01";
4876
0
      break;
4877
0
    }
4878
5
    if (MCInst_getNumOperands(MI) == 4 &&
4879
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4880
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4881
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4882
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4883
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4884
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4885
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4886
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4887
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4888
0
      AsmString = "fmovqn $\x02, $\x03, $\x01";
4889
0
      break;
4890
0
    }
4891
5
    if (MCInst_getNumOperands(MI) == 4 &&
4892
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4893
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4894
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4895
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4896
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4897
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4898
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4899
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4900
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4901
0
      AsmString = "fmovqu $\x02, $\x03, $\x01";
4902
0
      break;
4903
0
    }
4904
5
    if (MCInst_getNumOperands(MI) == 4 &&
4905
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4906
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4907
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4908
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4909
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4910
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4911
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4912
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4913
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4914
0
      AsmString = "fmovqg $\x02, $\x03, $\x01";
4915
0
      break;
4916
0
    }
4917
5
    if (MCInst_getNumOperands(MI) == 4 &&
4918
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4919
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4920
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4921
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4922
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4923
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4924
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4925
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4926
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4927
0
      AsmString = "fmovqug $\x02, $\x03, $\x01";
4928
0
      break;
4929
0
    }
4930
5
    if (MCInst_getNumOperands(MI) == 4 &&
4931
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4932
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4933
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4934
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4935
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4936
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4937
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4938
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4939
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4940
0
      AsmString = "fmovql $\x02, $\x03, $\x01";
4941
0
      break;
4942
0
    }
4943
5
    if (MCInst_getNumOperands(MI) == 4 &&
4944
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4945
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4946
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4947
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4948
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4949
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4950
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4951
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4952
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4953
0
      AsmString = "fmovqul $\x02, $\x03, $\x01";
4954
0
      break;
4955
0
    }
4956
5
    if (MCInst_getNumOperands(MI) == 4 &&
4957
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4958
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4959
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4960
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4961
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4962
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4963
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4964
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4965
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4966
0
      AsmString = "fmovqlg $\x02, $\x03, $\x01";
4967
0
      break;
4968
0
    }
4969
5
    if (MCInst_getNumOperands(MI) == 4 &&
4970
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4971
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4972
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4973
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4974
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4975
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4976
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4977
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4978
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4979
0
      AsmString = "fmovqne $\x02, $\x03, $\x01";
4980
0
      break;
4981
0
    }
4982
5
    if (MCInst_getNumOperands(MI) == 4 &&
4983
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4984
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4985
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4986
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4987
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4988
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4989
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4990
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4991
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4992
0
      AsmString = "fmovqe $\x02, $\x03, $\x01";
4993
0
      break;
4994
0
    }
4995
5
    if (MCInst_getNumOperands(MI) == 4 &&
4996
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4997
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4998
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4999
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5000
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5001
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5002
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5003
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5004
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5005
0
      AsmString = "fmovque $\x02, $\x03, $\x01";
5006
0
      break;
5007
0
    }
5008
5
    if (MCInst_getNumOperands(MI) == 4 &&
5009
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5010
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5011
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5012
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5013
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5014
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5015
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5016
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5017
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5018
0
      AsmString = "fmovqge $\x02, $\x03, $\x01";
5019
0
      break;
5020
0
    }
5021
5
    if (MCInst_getNumOperands(MI) == 4 &&
5022
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5023
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5024
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5025
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5026
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5027
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5028
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5029
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5030
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5031
0
      AsmString = "fmovquge $\x02, $\x03, $\x01";
5032
0
      break;
5033
0
    }
5034
5
    if (MCInst_getNumOperands(MI) == 4 &&
5035
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5036
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5037
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5038
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5039
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5040
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5041
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5042
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5043
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5044
0
      AsmString = "fmovqle $\x02, $\x03, $\x01";
5045
0
      break;
5046
0
    }
5047
5
    if (MCInst_getNumOperands(MI) == 4 &&
5048
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5049
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5050
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5051
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5052
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5053
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5054
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5055
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5056
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5057
0
      AsmString = "fmovqule $\x02, $\x03, $\x01";
5058
0
      break;
5059
0
    }
5060
5
    if (MCInst_getNumOperands(MI) == 4 &&
5061
5
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5062
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5063
5
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5064
5
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5065
5
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5066
5
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5067
5
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5068
5
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5069
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5070
0
      AsmString = "fmovqo $\x02, $\x03, $\x01";
5071
0
      break;
5072
0
    }
5073
5
    return NULL;
5074
21
  case SP_V9FMOVS_FCC:
5075
21
    if (MCInst_getNumOperands(MI) == 4 &&
5076
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5077
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5078
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5079
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5080
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5081
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5082
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5083
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5084
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5085
0
      AsmString = "fmovsa $\x02, $\x03, $\x01";
5086
0
      break;
5087
0
    }
5088
21
    if (MCInst_getNumOperands(MI) == 4 &&
5089
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5090
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5091
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5092
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5093
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5094
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5095
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5096
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5097
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5098
0
      AsmString = "fmovsn $\x02, $\x03, $\x01";
5099
0
      break;
5100
0
    }
5101
21
    if (MCInst_getNumOperands(MI) == 4 &&
5102
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5103
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5104
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5105
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5106
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5107
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5108
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5109
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5110
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5111
0
      AsmString = "fmovsu $\x02, $\x03, $\x01";
5112
0
      break;
5113
0
    }
5114
21
    if (MCInst_getNumOperands(MI) == 4 &&
5115
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5116
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5117
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5118
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5119
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5120
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5121
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5122
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5123
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5124
0
      AsmString = "fmovsg $\x02, $\x03, $\x01";
5125
0
      break;
5126
0
    }
5127
21
    if (MCInst_getNumOperands(MI) == 4 &&
5128
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5129
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5130
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5131
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5132
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5133
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5134
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5135
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5136
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5137
0
      AsmString = "fmovsug $\x02, $\x03, $\x01";
5138
0
      break;
5139
0
    }
5140
21
    if (MCInst_getNumOperands(MI) == 4 &&
5141
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5142
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5143
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5144
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5145
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5146
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5147
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5148
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5149
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5150
0
      AsmString = "fmovsl $\x02, $\x03, $\x01";
5151
0
      break;
5152
0
    }
5153
21
    if (MCInst_getNumOperands(MI) == 4 &&
5154
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5155
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5156
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5157
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5158
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5159
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5160
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5161
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5162
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5163
0
      AsmString = "fmovsul $\x02, $\x03, $\x01";
5164
0
      break;
5165
0
    }
5166
21
    if (MCInst_getNumOperands(MI) == 4 &&
5167
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5168
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5169
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5170
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5171
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5172
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5173
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5174
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5175
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5176
0
      AsmString = "fmovslg $\x02, $\x03, $\x01";
5177
0
      break;
5178
0
    }
5179
21
    if (MCInst_getNumOperands(MI) == 4 &&
5180
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5181
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5182
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5183
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5184
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5185
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5186
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5187
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5188
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5189
0
      AsmString = "fmovsne $\x02, $\x03, $\x01";
5190
0
      break;
5191
0
    }
5192
21
    if (MCInst_getNumOperands(MI) == 4 &&
5193
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5194
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5195
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5196
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5197
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5198
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5199
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5200
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5201
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5202
0
      AsmString = "fmovse $\x02, $\x03, $\x01";
5203
0
      break;
5204
0
    }
5205
21
    if (MCInst_getNumOperands(MI) == 4 &&
5206
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5207
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5208
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5209
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5210
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5211
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5212
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5213
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5214
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5215
0
      AsmString = "fmovsue $\x02, $\x03, $\x01";
5216
0
      break;
5217
0
    }
5218
21
    if (MCInst_getNumOperands(MI) == 4 &&
5219
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5220
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5221
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5222
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5223
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5224
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5225
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5226
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5227
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5228
0
      AsmString = "fmovsge $\x02, $\x03, $\x01";
5229
0
      break;
5230
0
    }
5231
21
    if (MCInst_getNumOperands(MI) == 4 &&
5232
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5233
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5234
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5235
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5236
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5237
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5238
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5239
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5240
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5241
0
      AsmString = "fmovsuge $\x02, $\x03, $\x01";
5242
0
      break;
5243
0
    }
5244
21
    if (MCInst_getNumOperands(MI) == 4 &&
5245
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5246
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5247
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5248
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5249
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5250
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5251
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5252
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5253
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5254
0
      AsmString = "fmovsle $\x02, $\x03, $\x01";
5255
0
      break;
5256
0
    }
5257
21
    if (MCInst_getNumOperands(MI) == 4 &&
5258
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5259
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5260
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5261
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5262
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5263
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5264
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5265
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5266
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5267
0
      AsmString = "fmovsule $\x02, $\x03, $\x01";
5268
0
      break;
5269
0
    }
5270
21
    if (MCInst_getNumOperands(MI) == 4 &&
5271
21
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5272
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5273
21
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5274
21
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5275
21
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5276
21
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5277
21
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5278
21
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5279
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5280
0
      AsmString = "fmovso $\x02, $\x03, $\x01";
5281
0
      break;
5282
0
    }
5283
21
    return NULL;
5284
54
  case SP_V9MOVFCCri:
5285
54
    if (MCInst_getNumOperands(MI) == 4 &&
5286
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5287
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5288
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5289
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5290
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5291
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5292
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5293
0
      AsmString = "mova $\x02, $\x03, $\x01";
5294
0
      break;
5295
0
    }
5296
54
    if (MCInst_getNumOperands(MI) == 4 &&
5297
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5298
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5299
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5300
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5301
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5302
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5303
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5304
0
      AsmString = "movn $\x02, $\x03, $\x01";
5305
0
      break;
5306
0
    }
5307
54
    if (MCInst_getNumOperands(MI) == 4 &&
5308
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5309
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5310
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5311
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5312
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5313
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5314
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5315
0
      AsmString = "movu $\x02, $\x03, $\x01";
5316
0
      break;
5317
0
    }
5318
54
    if (MCInst_getNumOperands(MI) == 4 &&
5319
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5320
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5321
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5322
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5323
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5324
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5325
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5326
0
      AsmString = "movg $\x02, $\x03, $\x01";
5327
0
      break;
5328
0
    }
5329
54
    if (MCInst_getNumOperands(MI) == 4 &&
5330
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5331
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5332
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5333
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5334
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5335
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5336
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5337
0
      AsmString = "movug $\x02, $\x03, $\x01";
5338
0
      break;
5339
0
    }
5340
54
    if (MCInst_getNumOperands(MI) == 4 &&
5341
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5342
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5343
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5344
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5345
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5346
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5347
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5348
0
      AsmString = "movl $\x02, $\x03, $\x01";
5349
0
      break;
5350
0
    }
5351
54
    if (MCInst_getNumOperands(MI) == 4 &&
5352
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5353
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5354
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5355
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5356
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5357
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5358
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5359
0
      AsmString = "movul $\x02, $\x03, $\x01";
5360
0
      break;
5361
0
    }
5362
54
    if (MCInst_getNumOperands(MI) == 4 &&
5363
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5364
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5365
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5366
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5367
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5368
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5369
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5370
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5371
0
      break;
5372
0
    }
5373
54
    if (MCInst_getNumOperands(MI) == 4 &&
5374
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5375
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5376
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5377
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5378
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5379
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5380
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5381
0
      AsmString = "movne $\x02, $\x03, $\x01";
5382
0
      break;
5383
0
    }
5384
54
    if (MCInst_getNumOperands(MI) == 4 &&
5385
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5386
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5387
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5388
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5389
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5390
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5391
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5392
0
      AsmString = "move $\x02, $\x03, $\x01";
5393
0
      break;
5394
0
    }
5395
54
    if (MCInst_getNumOperands(MI) == 4 &&
5396
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5397
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5398
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5399
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5400
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5401
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5402
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5403
0
      AsmString = "movue $\x02, $\x03, $\x01";
5404
0
      break;
5405
0
    }
5406
54
    if (MCInst_getNumOperands(MI) == 4 &&
5407
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5408
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5409
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5410
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5411
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5412
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5413
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5414
0
      AsmString = "movge $\x02, $\x03, $\x01";
5415
0
      break;
5416
0
    }
5417
54
    if (MCInst_getNumOperands(MI) == 4 &&
5418
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5419
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5420
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5421
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5422
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5423
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5424
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5425
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5426
0
      break;
5427
0
    }
5428
54
    if (MCInst_getNumOperands(MI) == 4 &&
5429
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5430
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5431
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5432
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5433
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5434
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5435
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5436
0
      AsmString = "movle $\x02, $\x03, $\x01";
5437
0
      break;
5438
0
    }
5439
54
    if (MCInst_getNumOperands(MI) == 4 &&
5440
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5441
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5442
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5443
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5444
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5445
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5446
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5447
0
      AsmString = "movule $\x02, $\x03, $\x01";
5448
0
      break;
5449
0
    }
5450
54
    if (MCInst_getNumOperands(MI) == 4 &&
5451
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5452
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5453
54
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5454
54
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5455
54
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5456
54
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5457
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5458
0
      AsmString = "movo $\x02, $\x03, $\x01";
5459
0
      break;
5460
0
    }
5461
54
    return NULL;
5462
85
  case SP_V9MOVFCCrr:
5463
85
    if (MCInst_getNumOperands(MI) == 4 &&
5464
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5465
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5466
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5467
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5468
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5469
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5470
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5471
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5472
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5473
0
      AsmString = "mova $\x02, $\x03, $\x01";
5474
0
      break;
5475
0
    }
5476
85
    if (MCInst_getNumOperands(MI) == 4 &&
5477
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5478
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5479
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5480
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5481
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5482
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5483
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5484
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5485
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5486
0
      AsmString = "movn $\x02, $\x03, $\x01";
5487
0
      break;
5488
0
    }
5489
85
    if (MCInst_getNumOperands(MI) == 4 &&
5490
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5491
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5492
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5493
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5494
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5495
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5496
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5497
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5498
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5499
0
      AsmString = "movu $\x02, $\x03, $\x01";
5500
0
      break;
5501
0
    }
5502
85
    if (MCInst_getNumOperands(MI) == 4 &&
5503
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5504
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5505
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5506
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5507
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5508
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5509
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5510
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5511
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5512
0
      AsmString = "movg $\x02, $\x03, $\x01";
5513
0
      break;
5514
0
    }
5515
85
    if (MCInst_getNumOperands(MI) == 4 &&
5516
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5517
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5518
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5519
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5520
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5521
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5522
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5523
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5524
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5525
0
      AsmString = "movug $\x02, $\x03, $\x01";
5526
0
      break;
5527
0
    }
5528
85
    if (MCInst_getNumOperands(MI) == 4 &&
5529
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5530
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5531
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5532
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5533
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5534
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5535
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5536
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5537
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5538
0
      AsmString = "movl $\x02, $\x03, $\x01";
5539
0
      break;
5540
0
    }
5541
85
    if (MCInst_getNumOperands(MI) == 4 &&
5542
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5543
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5544
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5545
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5546
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5547
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5548
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5549
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5550
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5551
0
      AsmString = "movul $\x02, $\x03, $\x01";
5552
0
      break;
5553
0
    }
5554
85
    if (MCInst_getNumOperands(MI) == 4 &&
5555
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5556
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5557
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5558
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5559
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5560
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5561
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5562
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5563
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5564
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5565
0
      break;
5566
0
    }
5567
85
    if (MCInst_getNumOperands(MI) == 4 &&
5568
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5569
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5570
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5571
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5572
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5573
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5574
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5575
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5576
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5577
0
      AsmString = "movne $\x02, $\x03, $\x01";
5578
0
      break;
5579
0
    }
5580
85
    if (MCInst_getNumOperands(MI) == 4 &&
5581
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5582
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5583
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5584
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5585
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5586
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5587
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5588
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5589
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5590
0
      AsmString = "move $\x02, $\x03, $\x01";
5591
0
      break;
5592
0
    }
5593
85
    if (MCInst_getNumOperands(MI) == 4 &&
5594
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5595
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5596
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5597
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5598
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5599
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5600
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5601
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5602
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5603
0
      AsmString = "movue $\x02, $\x03, $\x01";
5604
0
      break;
5605
0
    }
5606
85
    if (MCInst_getNumOperands(MI) == 4 &&
5607
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5608
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5609
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5610
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5611
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5612
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5613
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5614
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5615
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5616
0
      AsmString = "movge $\x02, $\x03, $\x01";
5617
0
      break;
5618
0
    }
5619
85
    if (MCInst_getNumOperands(MI) == 4 &&
5620
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5621
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5622
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5623
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5624
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5625
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5626
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5627
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5628
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5629
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5630
0
      break;
5631
0
    }
5632
85
    if (MCInst_getNumOperands(MI) == 4 &&
5633
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5634
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5635
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5636
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5637
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5638
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5639
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5640
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5641
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5642
0
      AsmString = "movle $\x02, $\x03, $\x01";
5643
0
      break;
5644
0
    }
5645
85
    if (MCInst_getNumOperands(MI) == 4 &&
5646
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5647
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5648
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5649
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5650
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5651
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5652
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5653
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5654
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5655
0
      AsmString = "movule $\x02, $\x03, $\x01";
5656
0
      break;
5657
0
    }
5658
85
    if (MCInst_getNumOperands(MI) == 4 &&
5659
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5660
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5661
85
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5662
85
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5663
85
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5664
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5665
85
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5666
85
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5667
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5668
0
      AsmString = "movo $\x02, $\x03, $\x01";
5669
0
      break;
5670
0
    }
5671
85
    return NULL;
5672
23.7k
  }
5673
5674
7.99k
  tmp = cs_strdup(AsmString);
5675
7.99k
  AsmMnem = tmp;
5676
53.5k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5677
53.5k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
5678
7.98k
      *AsmOps = '\0';
5679
7.98k
      AsmOps++;
5680
7.98k
      break;
5681
7.98k
    }
5682
53.5k
  }
5683
7.99k
  SStream_concat0(OS, AsmMnem);
5684
7.99k
  if (*AsmOps) {
5685
7.98k
    SStream_concat0(OS, "\t");
5686
7.98k
    if (strstr(AsmOps, "icc"))
5687
1.19k
      Sparc_addReg(MI, SPARC_REG_ICC);
5688
7.98k
    if (strstr(AsmOps, "xcc"))
5689
2.63k
      Sparc_addReg(MI, SPARC_REG_XCC);
5690
50.5k
    for (c = AsmOps; *c; c++) {
5691
42.5k
      if (*c == '$') {
5692
11.4k
        c += 1;
5693
11.4k
        if (*c == (char)0xff) {
5694
0
          c += 1;
5695
0
          OpIdx = *c - 1;
5696
0
          c += 1;
5697
0
          PrintMethodIdx = *c - 1;
5698
0
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5699
0
        } else
5700
11.4k
          printOperand(MI, *c - 1, OS);
5701
31.0k
      } else {
5702
31.0k
        SStream_concat(OS, "%c", *c);
5703
31.0k
      }
5704
42.5k
    }
5705
7.98k
  }
5706
7.99k
  return tmp;
5707
23.7k
}
5708
5709
#endif // PRINT_ALIAS_INSTR