/src/capstonev5/arch/Sparc/SparcInstPrinter.c

Source (jump to first uncovered line)
//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax --------===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an Sparc MCInst to a .s file.
//
//===----------------------------------------------------------------------===//

/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

#ifdef CAPSTONE_HAS_SPARC

#ifdef _MSC_VER
#define _CRT_SECURE_NO_WARNINGS
#endif

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <limits.h>

#include "SparcInstPrinter.h"
#include "../../MCInst.h"
#include "../../utils.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "../../MathExtras.h"
#include "SparcMapping.h"

#include "Sparc.h"

static const char *getRegisterName(unsigned RegNo);
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier);
static void printOperand(MCInst *MI, int opNum, SStream *O);

static void Sparc_add_hint(MCInst *MI, unsigned int hint)
{
  if (MI->csh->detail) {
    MI->flat_insn->detail->sparc.hint = hint;
  }
}

static void Sparc_add_reg(MCInst *MI, unsigned int reg)
{
  if (MI->csh->detail) {
    MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
    MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
    MI->flat_insn->detail->sparc.op_count++;
  }
}

static void set_mem_access(MCInst *MI, bool status)
{
  if (MI->csh->detail != CS_OPT_ON)
    return;

  MI->csh->doing_mem = status;

  if (status) {
    MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_MEM;
    MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = SPARC_REG_INVALID;
    MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = 0;
  } else {
    // done, create the next operand slot
    MI->flat_insn->detail->sparc.op_count++;
  }
}

void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
{
  if (((cs_struct *)ud)->detail != CS_OPT_ON)
    return;

  // fix up some instructions
  if (insn->id == SPARC_INS_CASX) {
    // first op is actually a memop, not regop
    insn->detail->sparc.operands[0].type = SPARC_OP_MEM;
    insn->detail->sparc.operands[0].mem.base = (uint8_t)insn->detail->sparc.operands[0].reg;
    insn->detail->sparc.operands[0].mem.disp = 0;
  }
}

static void printRegName(SStream *OS, unsigned RegNo)
{
  SStream_concat0(OS, "%");
  SStream_concat0(OS, getRegisterName(RegNo));
}

#define GET_INSTRINFO_ENUM
#include "SparcGenInstrInfo.inc"

#define GET_REGINFO_ENUM
#include "SparcGenRegisterInfo.inc"

static bool printSparcAliasInstr(MCInst *MI, SStream *O)
{
  switch (MCInst_getOpcode(MI)) {
    default: return false;
    case SP_JMPLrr:
    case SP_JMPLri:
         if (MCInst_getNumOperands(MI) != 3)
           return false;
         if (!MCOperand_isReg(MCInst_getOperand(MI, 0)))
           return false;

         switch (MCOperand_getReg(MCInst_getOperand(MI, 0))) {
           default: return false;
           case SP_G0: // jmp $addr | ret | retl
                if (MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
                  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
                  switch(MCOperand_getReg(MCInst_getOperand(MI, 1))) {
                    default: break;
                    case SP_I7: SStream_concat0(O, "ret"); MCInst_setOpcodePub(MI, SPARC_INS_RET); return true;
                    case SP_O7: SStream_concat0(O, "retl"); MCInst_setOpcodePub(MI, SPARC_INS_RETL); return true;
                  }
                }

                SStream_concat0(O, "jmp\t");
                MCInst_setOpcodePub(MI, SPARC_INS_JMP);
                printMemOperand(MI, 1, O, NULL);
                return true;
           case SP_O7: // call $addr
                SStream_concat0(O, "call ");
                MCInst_setOpcodePub(MI, SPARC_INS_CALL);
                printMemOperand(MI, 1, O, NULL);
                return true;
         }
    case SP_V9FCMPS:
    case SP_V9FCMPD:
    case SP_V9FCMPQ:
    case SP_V9FCMPES:
    case SP_V9FCMPED:
    case SP_V9FCMPEQ:
         if (MI->csh->mode & CS_MODE_V9 || (MCInst_getNumOperands(MI) != 3) ||
             (!MCOperand_isReg(MCInst_getOperand(MI, 0))) ||
             (MCOperand_getReg(MCInst_getOperand(MI, 0)) != SP_FCC0))
             return false;
         // if V8, skip printing %fcc0.
         switch(MCInst_getOpcode(MI)) {
           default:
           case SP_V9FCMPS:  SStream_concat0(O, "fcmps\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPS); break;
           case SP_V9FCMPD:  SStream_concat0(O, "fcmpd\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPD); break;
           case SP_V9FCMPQ:  SStream_concat0(O, "fcmpq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPQ); break;
           case SP_V9FCMPES: SStream_concat0(O, "fcmpes\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPES); break;
           case SP_V9FCMPED: SStream_concat0(O, "fcmped\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPED); break;
           case SP_V9FCMPEQ: SStream_concat0(O, "fcmpeq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPEQ); break;
         }
         printOperand(MI, 1, O);
         SStream_concat0(O, ", ");
         printOperand(MI, 2, O);
         return true;
  }
}

static void printOperand(MCInst *MI, int opNum, SStream *O)
{
  int64_t Imm;
  unsigned reg;
  MCOperand *MO = MCInst_getOperand(MI, opNum);

  if (MCOperand_isReg(MO)) {
    reg = MCOperand_getReg(MO);
    printRegName(O, reg);
    reg = Sparc_map_register(reg);

    if (MI->csh->detail) {
      if (MI->csh->doing_mem) {
        if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base)
          MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = (uint8_t)reg;
        else
          MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = (uint8_t)reg;
      } else {
        MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
        MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
        MI->flat_insn->detail->sparc.op_count++;
      }
    }

    return;
  }

  if (MCOperand_isImm(MO)) {
    Imm = (int)MCOperand_getImm(MO);

    // Conditional branches displacements needs to be signextended to be
    // able to jump backwards.
    //
    // Displacements are measured as the number of instructions forward or
    // backward, so they need to be multiplied by 4
    switch (MI->Opcode) {
      case SP_CALL:
        // Imm = SignExtend32(Imm, 30);
        Imm += MI->address;
        break;

      // Branch on integer condition with prediction (BPcc)
      // Branch on floating point condition with prediction (FBPfcc)
      case SP_BPICC:
      case SP_BPICCA:
      case SP_BPICCANT:
      case SP_BPICCNT:
      case SP_BPXCC:
      case SP_BPXCCA:
      case SP_BPXCCANT:
      case SP_BPXCCNT:
      case SP_BPFCC:
      case SP_BPFCCA:
      case SP_BPFCCANT:
      case SP_BPFCCNT:
        Imm = SignExtend32(Imm, 19);
        Imm = MI->address + Imm * 4;
        break;

      // Branch on integer condition (Bicc)
      // Branch on floating point condition (FBfcc)
      case SP_BA:
      case SP_BCOND:
      case SP_BCONDA:
      case SP_FBCOND:
      case SP_FBCONDA:
        Imm = SignExtend32(Imm, 22);
        Imm = MI->address + Imm * 4;
        break;

      // Branch on integer register with prediction (BPr)
      case SP_BPGEZapn:
      case SP_BPGEZapt:
      case SP_BPGEZnapn:
      case SP_BPGEZnapt:
      case SP_BPGZapn:
      case SP_BPGZapt:
      case SP_BPGZnapn:
      case SP_BPGZnapt:
      case SP_BPLEZapn:
      case SP_BPLEZapt:
      case SP_BPLEZnapn:
      case SP_BPLEZnapt:
      case SP_BPLZapn:
      case SP_BPLZapt:
      case SP_BPLZnapn:
      case SP_BPLZnapt:
      case SP_BPNZapn:
      case SP_BPNZapt:
      case SP_BPNZnapn:
      case SP_BPNZnapt:
      case SP_BPZapn:
      case SP_BPZapt:
      case SP_BPZnapn:
      case SP_BPZnapt:
        Imm = SignExtend32(Imm, 16);
        Imm = MI->address + Imm * 4;
        break;
    }
    
    printInt64(O, Imm);

    if (MI->csh->detail) {
      if (MI->csh->doing_mem) {
        MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = Imm;
      } else {
        MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_IMM;
        MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].imm = Imm;
        MI->flat_insn->detail->sparc.op_count++;
      }
    }
  }

  return;
}

static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier)
{
  MCOperand *MO;

  set_mem_access(MI, true);
  printOperand(MI, opNum, O);

  // If this is an ADD operand, emit it like normal operands.
  if (Modifier && !strcmp(Modifier, "arith")) {
    SStream_concat0(O, ", ");
    printOperand(MI, opNum + 1, O);
    set_mem_access(MI, false);
    return;
  }

  MO = MCInst_getOperand(MI, opNum + 1);

  if (MCOperand_isReg(MO) && (MCOperand_getReg(MO) == SP_G0)) {
    set_mem_access(MI, false);
    return;   // don't print "+%g0"
  }

  if (MCOperand_isImm(MO) && (MCOperand_getImm(MO) == 0)) {
    set_mem_access(MI, false);
    return;   // don't print "+0"
  }

  SStream_concat0(O, "+");  // qq

  printOperand(MI, opNum + 1, O);
  set_mem_access(MI, false);
}

static void printCCOperand(MCInst *MI, int opNum, SStream *O)
{
  int CC = (int)MCOperand_getImm(MCInst_getOperand(MI, opNum)) + 256;

  switch (MCInst_getOpcode(MI)) {
    default: break;
    case SP_FBCOND:
    case SP_FBCONDA:
    case SP_BPFCC:
    case SP_BPFCCA:
    case SP_BPFCCNT:
    case SP_BPFCCANT:
    case SP_MOVFCCrr:  case SP_V9MOVFCCrr:
    case SP_MOVFCCri:  case SP_V9MOVFCCri:
    case SP_FMOVS_FCC: case SP_V9FMOVS_FCC:
    case SP_FMOVD_FCC: case SP_V9FMOVD_FCC:
    case SP_FMOVQ_FCC: case SP_V9FMOVQ_FCC:
         // Make sure CC is a fp conditional flag.
         CC = (CC < 16+256) ? (CC + 16) : CC;
         break;
  }

  SStream_concat0(O, SPARCCondCodeToString((sparc_cc)CC));

  if (MI->csh->detail)
    MI->flat_insn->detail->sparc.cc = (sparc_cc)CC;
}


static bool printGetPCX(MCInst *MI, unsigned opNum, SStream *O)
{
  return true;
}


#define PRINT_ALIAS_INSTR
#include "SparcGenAsmWriter.inc"

void Sparc_printInst(MCInst *MI, SStream *O, void *Info)
{
  char *mnem, *p;
  char instr[64]; // Sparc has no instruction this long

  mnem = printAliasInstr(MI, O, Info);
  if (mnem) {
    // fixup instruction id due to the change in alias instruction
    unsigned cpy_len = sizeof(instr) < strlen(mnem) ? sizeof(instr) : strlen(mnem);
    memcpy(instr, mnem, cpy_len);
    instr[cpy_len - 1] = '\0';
    // does this contains hint with a coma?
    p = strchr(instr, ',');
    if (p)
      *p = '\0'; // now instr only has instruction mnemonic
    MCInst_setOpcodePub(MI, Sparc_map_insn(instr));
    switch(MCInst_getOpcode(MI)) {
      case SP_BCOND:
      case SP_BCONDA:
      case SP_BPICCANT:
      case SP_BPICCNT:
      case SP_BPXCCANT:
      case SP_BPXCCNT:
      case SP_TXCCri:
      case SP_TXCCrr:
        if (MI->csh->detail) {
          // skip 'b', 't'
          MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 1);
          MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
        }
        break;
      case SP_BPFCCANT:
      case SP_BPFCCNT:
        if (MI->csh->detail) {
          // skip 'fb'
          MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 2);
          MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
        }
        break;
      case SP_FMOVD_ICC:
      case SP_FMOVD_XCC:
      case SP_FMOVQ_ICC:
      case SP_FMOVQ_XCC:
      case SP_FMOVS_ICC:
      case SP_FMOVS_XCC:
        if (MI->csh->detail) {
          // skip 'fmovd', 'fmovq', 'fmovs'
          MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 5);
          MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
        }
        break;
      case SP_MOVICCri:
      case SP_MOVICCrr:
      case SP_MOVXCCri:
      case SP_MOVXCCrr:
        if (MI->csh->detail) {
          // skip 'mov'
          MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 3);
          MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
        }
        break;
      case SP_V9FMOVD_FCC:
      case SP_V9FMOVQ_FCC:
      case SP_V9FMOVS_FCC:
        if (MI->csh->detail) {
          // skip 'fmovd', 'fmovq', 'fmovs'
          MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 5);
          MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
        }
        break;
      case SP_V9MOVFCCri:
      case SP_V9MOVFCCrr:
        if (MI->csh->detail) {
          // skip 'mov'
          MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 3);
          MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
        }
        break;
      default:
        break;
    }
    cs_mem_free(mnem);
  } else {
    if (!printSparcAliasInstr(MI, O))
      printInstruction(MI, O, NULL);
  }
}

void Sparc_addReg(MCInst *MI, int reg)
{
  if (MI->csh->detail) {
    MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
    MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
    MI->flat_insn->detail->sparc.op_count++;
  }
}

#endif

Coverage Report

Created: 2023-09-25 06:24

Line	Count	Source (jump to first uncovered line)
1		//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax --------===//
2		//
3		// The LLVM Compiler Infrastructure
4		//
5		// This file is distributed under the University of Illinois Open Source
6		// License. See LICENSE.TXT for details.
7		//
8		//===----------------------------------------------------------------------===//
9		//
10		// This class prints an Sparc MCInst to a .s file.
11		//
12		//===----------------------------------------------------------------------===//
13
14		/* Capstone Disassembly Engine */
15		/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
16
17		#ifdef CAPSTONE_HAS_SPARC
18
19		#ifdef _MSC_VER
20		#define _CRT_SECURE_NO_WARNINGS
21		#endif
22
23		#include <stdio.h>
24		#include <stdlib.h>
25		#include <string.h>
26		#include <limits.h>
27
28		#include "SparcInstPrinter.h"
29		#include "../../MCInst.h"
30		#include "../../utils.h"
31		#include "../../SStream.h"
32		#include "../../MCRegisterInfo.h"
33		#include "../../MathExtras.h"
34		#include "SparcMapping.h"
35
36		#include "Sparc.h"
37
38		static const char *getRegisterName(unsigned RegNo);
39		static void printInstruction(MCInst MI, SStream O, const MCRegisterInfo *MRI);
40		static void printMemOperand(MCInst MI, int opNum, SStream O, const char *Modifier);
41		static void printOperand(MCInst MI, int opNum, SStream O);
42
43		static void Sparc_add_hint(MCInst *MI, unsigned int hint)
44	661	{
45	661	if (MI->csh->detail) {
46	661	MI->flat_insn->detail->sparc.hint = hint;
47	661	}
48	661	}
49
50		static void Sparc_add_reg(MCInst *MI, unsigned int reg)
51	1.04k	{
52	1.04k	if (MI->csh->detail) {
53	1.04k	MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
54	1.04k	MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
55	1.04k	MI->flat_insn->detail->sparc.op_count++;
56	1.04k	}
57	1.04k	}
58
59		static void set_mem_access(MCInst *MI, bool status)
60	2.60k	{
61	2.60k	if (MI->csh->detail != CS_OPT_ON)
62	0	return;
63
64	2.60k	MI->csh->doing_mem = status;
65
66	2.60k	if (status) {
67	1.30k	MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_MEM;
68	1.30k	MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = SPARC_REG_INVALID;
69	1.30k	MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = 0;
70	1.30k	} else {
71		// done, create the next operand slot
72	1.30k	MI->flat_insn->detail->sparc.op_count++;
73	1.30k	}
74	2.60k	}
75
76		void Sparc_post_printer(csh ud, cs_insn insn, char insn_asm, MCInst *mci)
77	23.7k	{
78	23.7k	if (((cs_struct *)ud)->detail != CS_OPT_ON)
79	0	return;
80
81		// fix up some instructions
82	23.7k	if (insn->id == SPARC_INS_CASX) {
83		// first op is actually a memop, not regop
84	4	insn->detail->sparc.operands[0].type = SPARC_OP_MEM;
85	4	insn->detail->sparc.operands[0].mem.base = (uint8_t)insn->detail->sparc.operands[0].reg;
86	4	insn->detail->sparc.operands[0].mem.disp = 0;
87	4	}
88	23.7k	}
89
90		static void printRegName(SStream *OS, unsigned RegNo)
91	14.5k	{
92	14.5k	SStream_concat0(OS, "%");
93	14.5k	SStream_concat0(OS, getRegisterName(RegNo));
94	14.5k	}
95
96		#define GET_INSTRINFO_ENUM
97		#include "SparcGenInstrInfo.inc"
98
99		#define GET_REGINFO_ENUM
100		#include "SparcGenRegisterInfo.inc"
101
102		static bool printSparcAliasInstr(MCInst MI, SStream O)
103	15.7k	{
104	15.7k	switch (MCInst_getOpcode(MI)) {
105	15.2k	default: return false;
106	45	case SP_JMPLrr:
107	414	case SP_JMPLri:
108	414	if (MCInst_getNumOperands(MI) != 3)
109	0	return false;
110	414	if (!MCOperand_isReg(MCInst_getOperand(MI, 0)))
111	0	return false;
112
113	414	switch (MCOperand_getReg(MCInst_getOperand(MI, 0))) {
114	22	default: return false;
115	371	case SP_G0: // jmp $addr \| ret \| retl
116	371	if (MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
117	371	MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
118	194	switch(MCOperand_getReg(MCInst_getOperand(MI, 1))) {
119	173	default: break;
120	173	case SP_I7: SStream_concat0(O, "ret"); MCInst_setOpcodePub(MI, SPARC_INS_RET); return true;
121	8	case SP_O7: SStream_concat0(O, "retl"); MCInst_setOpcodePub(MI, SPARC_INS_RETL); return true;
122	194	}
123	194	}
124
125	350	SStream_concat0(O, "jmp\t");
126	350	MCInst_setOpcodePub(MI, SPARC_INS_JMP);
127	350	printMemOperand(MI, 1, O, NULL);
128	350	return true;
129	21	case SP_O7: // call $addr
130	21	SStream_concat0(O, "call ");
131	21	MCInst_setOpcodePub(MI, SPARC_INS_CALL);
132	21	printMemOperand(MI, 1, O, NULL);
133	21	return true;
134	414	}
135	33	case SP_V9FCMPS:
136	64	case SP_V9FCMPD:
137	88	case SP_V9FCMPQ:
138	111	case SP_V9FCMPES:
139	118	case SP_V9FCMPED:
140	122	case SP_V9FCMPEQ:
141	122	if (MI->csh->mode & CS_MODE_V9 \|\| (MCInst_getNumOperands(MI) != 3) \|\|
142	122	(!MCOperand_isReg(MCInst_getOperand(MI, 0))) \|\|
143	122	(MCOperand_getReg(MCInst_getOperand(MI, 0)) != SP_FCC0))
144	122	return false;
145		// if V8, skip printing %fcc0.
146	0	switch(MCInst_getOpcode(MI)) {
147	0	default:
148	0	case SP_V9FCMPS: SStream_concat0(O, "fcmps\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPS); break;
149	0	case SP_V9FCMPD: SStream_concat0(O, "fcmpd\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPD); break;
150	0	case SP_V9FCMPQ: SStream_concat0(O, "fcmpq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPQ); break;
151	0	case SP_V9FCMPES: SStream_concat0(O, "fcmpes\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPES); break;
152	0	case SP_V9FCMPED: SStream_concat0(O, "fcmped\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPED); break;
153	0	case SP_V9FCMPEQ: SStream_concat0(O, "fcmpeq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPEQ); break;
154	0	}
155	0	printOperand(MI, 1, O);
156	0	SStream_concat0(O, ", ");
157	0	printOperand(MI, 2, O);
158	0	return true;
159	15.7k	}
160	15.7k	}
161
162		static void printOperand(MCInst MI, int opNum, SStream O)
163	35.2k	{
164	35.2k	int64_t Imm;
165	35.2k	unsigned reg;
166	35.2k	MCOperand *MO = MCInst_getOperand(MI, opNum);
167
168	35.2k	if (MCOperand_isReg(MO)) {
169	14.5k	reg = MCOperand_getReg(MO);
170	14.5k	printRegName(O, reg);
171	14.5k	reg = Sparc_map_register(reg);
172
173	14.5k	if (MI->csh->detail) {
174	14.5k	if (MI->csh->doing_mem) {
175	1.82k	if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base)
176	518	MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = (uint8_t)reg;
177	1.30k	else
178	1.30k	MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = (uint8_t)reg;
179	12.7k	} else {
180	12.7k	MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
181	12.7k	MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
182	12.7k	MI->flat_insn->detail->sparc.op_count++;
183	12.7k	}
184	14.5k	}
185
186	14.5k	return;
187	14.5k	}
188
189	20.6k	if (MCOperand_isImm(MO)) {
190	20.6k	Imm = (int)MCOperand_getImm(MO);
191
192		// Conditional branches displacements needs to be signextended to be
193		// able to jump backwards.
194		//
195		// Displacements are measured as the number of instructions forward or
196		// backward, so they need to be multiplied by 4
197	20.6k	switch (MI->Opcode) {
198	6.73k	case SP_CALL:
199		// Imm = SignExtend32(Imm, 30);
200	6.73k	Imm += MI->address;
201	6.73k	break;
202
203		// Branch on integer condition with prediction (BPcc)
204		// Branch on floating point condition with prediction (FBPfcc)
205	31	case SP_BPICC:
206	181	case SP_BPICCA:
207	893	case SP_BPICCANT:
208	1.37k	case SP_BPICCNT:
209	1.44k	case SP_BPXCC:
210	1.50k	case SP_BPXCCA:
211	2.11k	case SP_BPXCCANT:
212	2.97k	case SP_BPXCCNT:
213	3.24k	case SP_BPFCC:
214	3.35k	case SP_BPFCCA:
215	4.27k	case SP_BPFCCANT:
216	5.49k	case SP_BPFCCNT:
217	5.49k	Imm = SignExtend32(Imm, 19);
218	5.49k	Imm = MI->address + Imm * 4;
219	5.49k	break;
220
221		// Branch on integer condition (Bicc)
222		// Branch on floating point condition (FBfcc)
223	53	case SP_BA:
224	982	case SP_BCOND:
225	1.88k	case SP_BCONDA:
226	2.47k	case SP_FBCOND:
227	2.81k	case SP_FBCONDA:
228	2.81k	Imm = SignExtend32(Imm, 22);
229	2.81k	Imm = MI->address + Imm * 4;
230	2.81k	break;
231
232		// Branch on integer register with prediction (BPr)
233	35	case SP_BPGEZapn:
234	84	case SP_BPGEZapt:
235	135	case SP_BPGEZnapn:
236	138	case SP_BPGEZnapt:
237	153	case SP_BPGZapn:
238	158	case SP_BPGZapt:
239	243	case SP_BPGZnapn:
240	291	case SP_BPGZnapt:
241	296	case SP_BPLEZapn:
242	297	case SP_BPLEZapt:
243	327	case SP_BPLEZnapn:
244	330	case SP_BPLEZnapt:
245	363	case SP_BPLZapn:
246	388	case SP_BPLZapt:
247	398	case SP_BPLZnapn:
248	549	case SP_BPLZnapt:
249	575	case SP_BPNZapn:
250	600	case SP_BPNZapt:
251	621	case SP_BPNZnapn:
252	642	case SP_BPNZnapt:
253	645	case SP_BPZapn:
254	678	case SP_BPZapt:
255	688	case SP_BPZnapn:
256	709	case SP_BPZnapt:
257	709	Imm = SignExtend32(Imm, 16);
258	709	Imm = MI->address + Imm * 4;
259	709	break;
260	20.6k	}
261
262	20.6k	printInt64(O, Imm);
263
264	20.6k	if (MI->csh->detail) {
265	20.6k	if (MI->csh->doing_mem) {
266	695	MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = Imm;
267	19.9k	} else {
268	19.9k	MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_IMM;
269	19.9k	MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].imm = Imm;
270	19.9k	MI->flat_insn->detail->sparc.op_count++;
271	19.9k	}
272	20.6k	}
273	20.6k	}
274
275	20.6k	return;
276	20.6k	}
277
278		static void printMemOperand(MCInst MI, int opNum, SStream O, const char *Modifier)
279	1.30k	{
280	1.30k	MCOperand *MO;
281
282	1.30k	set_mem_access(MI, true);
283	1.30k	printOperand(MI, opNum, O);
284
285		// If this is an ADD operand, emit it like normal operands.
286	1.30k	if (Modifier && !strcmp(Modifier, "arith")) {
287	0	SStream_concat0(O, ", ");
288	0	printOperand(MI, opNum + 1, O);
289	0	set_mem_access(MI, false);
290	0	return;
291	0	}
292
293	1.30k	MO = MCInst_getOperand(MI, opNum + 1);
294
295	1.30k	if (MCOperand_isReg(MO) && (MCOperand_getReg(MO) == SP_G0)) {
296	84	set_mem_access(MI, false);
297	84	return; // don't print "+%g0"
298	84	}
299
300	1.21k	if (MCOperand_isImm(MO) && (MCOperand_getImm(MO) == 0)) {
301	6	set_mem_access(MI, false);
302	6	return; // don't print "+0"
303	6	}
304
305	1.21k	SStream_concat0(O, "+"); // qq
306
307	1.21k	printOperand(MI, opNum + 1, O);
308	1.21k	set_mem_access(MI, false);
309	1.21k	}
310
311		static void printCCOperand(MCInst MI, int opNum, SStream O)
312	2.50k	{
313	2.50k	int CC = (int)MCOperand_getImm(MCInst_getOperand(MI, opNum)) + 256;
314
315	2.50k	switch (MCInst_getOpcode(MI)) {
316	818	default: break;
317	818	case SP_FBCOND:
318	926	case SP_FBCONDA:
319	1.19k	case SP_BPFCC:
320	1.30k	case SP_BPFCCA:
321	1.30k	case SP_BPFCCNT:
322	1.30k	case SP_BPFCCANT:
323	1.40k	case SP_MOVFCCrr: case SP_V9MOVFCCrr:
324	1.46k	case SP_MOVFCCri: case SP_V9MOVFCCri:
325	1.63k	case SP_FMOVS_FCC: case SP_V9FMOVS_FCC:
326	1.67k	case SP_FMOVD_FCC: case SP_V9FMOVD_FCC:
327	1.68k	case SP_FMOVQ_FCC: case SP_V9FMOVQ_FCC:
328		// Make sure CC is a fp conditional flag.
329	1.68k	CC = (CC < 16+256) ? (CC + 16) : CC;
330	1.68k	break;
331	2.50k	}
332
333	2.50k	SStream_concat0(O, SPARCCondCodeToString((sparc_cc)CC));
334
335	2.50k	if (MI->csh->detail)
336	2.50k	MI->flat_insn->detail->sparc.cc = (sparc_cc)CC;
337	2.50k	}
338
339
340		static bool printGetPCX(MCInst MI, unsigned opNum, SStream O)
341	0	{
342	0	return true;
343	0	}
344
345
346		#define PRINT_ALIAS_INSTR
347		#include "SparcGenAsmWriter.inc"
348
349		void Sparc_printInst(MCInst MI, SStream O, void *Info)
350	23.7k	{
351	23.7k	char mnem, p;
352	23.7k	char instr[64]; // Sparc has no instruction this long
353
354	23.7k	mnem = printAliasInstr(MI, O, Info);
355	23.7k	if (mnem) {
356		// fixup instruction id due to the change in alias instruction
357	7.99k	unsigned cpy_len = sizeof(instr) < strlen(mnem) ? sizeof(instr) : strlen(mnem);
358	7.99k	memcpy(instr, mnem, cpy_len);
359	7.99k	instr[cpy_len - 1] = '\0';
360		// does this contains hint with a coma?
361	7.99k	p = strchr(instr, ',');
362	7.99k	if (p)
363	5.71k	*p = '\0'; // now instr only has instruction mnemonic
364	7.99k	MCInst_setOpcodePub(MI, Sparc_map_insn(instr));
365	7.99k	switch(MCInst_getOpcode(MI)) {
366	929	case SP_BCOND:
367	1.83k	case SP_BCONDA:
368	2.54k	case SP_BPICCANT:
369	3.02k	case SP_BPICCNT:
370	3.64k	case SP_BPXCCANT:
371	4.49k	case SP_BPXCCNT:
372	5.11k	case SP_TXCCri:
373	5.66k	case SP_TXCCrr:
374	5.66k	if (MI->csh->detail) {
375		// skip 'b', 't'
376	5.66k	MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 1);
377	5.66k	MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
378	5.66k	}
379	5.66k	break;
380	918	case SP_BPFCCANT:
381	2.14k	case SP_BPFCCNT:
382	2.14k	if (MI->csh->detail) {
383		// skip 'fb'
384	2.14k	MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 2);
385	2.14k	MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
386	2.14k	}
387	2.14k	break;
388	0	case SP_FMOVD_ICC:
389	0	case SP_FMOVD_XCC:
390	0	case SP_FMOVQ_ICC:
391	0	case SP_FMOVQ_XCC:
392	0	case SP_FMOVS_ICC:
393	0	case SP_FMOVS_XCC:
394	0	if (MI->csh->detail) {
395		// skip 'fmovd', 'fmovq', 'fmovs'
396	0	MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 5);
397	0	MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
398	0	}
399	0	break;
400	0	case SP_MOVICCri:
401	0	case SP_MOVICCrr:
402	0	case SP_MOVXCCri:
403	0	case SP_MOVXCCrr:
404	0	if (MI->csh->detail) {
405		// skip 'mov'
406	0	MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 3);
407	0	MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
408	0	}
409	0	break;
410	0	case SP_V9FMOVD_FCC:
411	0	case SP_V9FMOVQ_FCC:
412	0	case SP_V9FMOVS_FCC:
413	0	if (MI->csh->detail) {
414		// skip 'fmovd', 'fmovq', 'fmovs'
415	0	MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 5);
416	0	MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
417	0	}
418	0	break;
419	0	case SP_V9MOVFCCri:
420	0	case SP_V9MOVFCCrr:
421	0	if (MI->csh->detail) {
422		// skip 'mov'
423	0	MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 3);
424	0	MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
425	0	}
426	0	break;
427	188	default:
428	188	break;
429	7.99k	}
430	7.99k	cs_mem_free(mnem);
431	15.7k	} else {
432	15.7k	if (!printSparcAliasInstr(MI, O))
433	15.3k	printInstruction(MI, O, NULL);
434	15.7k	}
435	23.7k	}
436
437		void Sparc_addReg(MCInst *MI, int reg)
438	3.82k	{
439	3.82k	if (MI->csh->detail) {
440	3.82k	MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
441	3.82k	MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
442	3.82k	MI->flat_insn->detail->sparc.op_count++;
443	3.82k	}
444	3.82k	}
445
446		#endif