Coverage Report

Created: 2023-09-25 06:24

/src/capstonev5/arch/SystemZ/SystemZDisassembler.c
Line
Count
Source
1
//===------ SystemZDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
10
/* Capstone Disassembly Engine */
11
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
12
13
#ifdef CAPSTONE_HAS_SYSZ
14
15
#include <stdio.h>  // DEBUG
16
#include <stdlib.h>
17
#include <string.h>
18
19
#include "../../cs_priv.h"
20
#include "../../utils.h"
21
22
#include "SystemZDisassembler.h"
23
24
#include "../../MCInst.h"
25
#include "../../MCInstrDesc.h"
26
#include "../../MCFixedLenDisassembler.h"
27
#include "../../MCRegisterInfo.h"
28
#include "../../MCDisassembler.h"
29
#include "../../MathExtras.h"
30
31
#include "SystemZMCTargetDesc.h"
32
33
static uint64_t getFeatureBits(int mode)
34
28.7k
{
35
  // support everything
36
28.7k
  return (uint64_t)-1;
37
28.7k
}
38
39
static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs)
40
49.2k
{
41
  //assert(RegNo < 16 && "Invalid register");
42
49.2k
  RegNo = Regs[RegNo];
43
49.2k
  if (RegNo == 0)
44
64
    return MCDisassembler_Fail;
45
46
49.1k
  MCOperand_CreateReg0(Inst, (unsigned)RegNo);
47
49.1k
  return MCDisassembler_Success;
48
49.2k
}
49
50
static DecodeStatus DecodeGR32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
51
    uint64_t Address, const void *Decoder)
52
12.9k
{
53
12.9k
  return decodeRegisterClass(Inst, RegNo, SystemZMC_GR32Regs);
54
12.9k
}
55
56
static DecodeStatus DecodeGRH32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
57
    uint64_t Address, const void *Decoder)
58
1.88k
{
59
1.88k
  return decodeRegisterClass(Inst, RegNo, SystemZMC_GRH32Regs);
60
1.88k
}
61
62
static DecodeStatus DecodeGR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
63
    uint64_t Address, const void *Decoder)
64
7.61k
{
65
7.61k
  return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs);
66
7.61k
}
67
68
static DecodeStatus DecodeGR128BitRegisterClass(MCInst *Inst, uint64_t RegNo,
69
    uint64_t Address, const void *Decoder)
70
2.09k
{
71
2.09k
  return decodeRegisterClass(Inst, RegNo, SystemZMC_GR128Regs);
72
2.09k
}
73
74
static DecodeStatus DecodeADDR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
75
    uint64_t Address, const void *Decoder)
76
797
{
77
797
  return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs);
78
797
}
79
80
static DecodeStatus DecodeFP32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
81
    uint64_t Address, const void *Decoder) 
82
7.23k
{
83
7.23k
  return decodeRegisterClass(Inst, RegNo, SystemZMC_FP32Regs);
84
7.23k
}
85
86
static DecodeStatus DecodeFP64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
87
    uint64_t Address, const void *Decoder)
88
10.7k
{
89
10.7k
  return decodeRegisterClass(Inst, RegNo, SystemZMC_FP64Regs);
90
10.7k
}
91
92
static DecodeStatus DecodeFP128BitRegisterClass(MCInst *Inst, uint64_t RegNo,
93
    uint64_t Address, const void *Decoder)
94
1.32k
{
95
1.32k
  return decodeRegisterClass(Inst, RegNo, SystemZMC_FP128Regs);
96
1.32k
}
97
98
static DecodeStatus DecodeVR32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
99
    uint64_t Address, const void *Decoder)
100
279
{
101
279
  return decodeRegisterClass(Inst, RegNo, SystemZMC_VR32Regs);
102
279
}
103
104
static DecodeStatus DecodeVR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
105
    uint64_t Address, const void *Decoder)
106
838
{
107
838
  return decodeRegisterClass(Inst, RegNo, SystemZMC_VR64Regs);
108
838
}
109
110
static DecodeStatus DecodeVR128BitRegisterClass(MCInst *Inst, uint64_t RegNo,
111
    uint64_t Address, const void *Decoder)
112
2.74k
{
113
2.74k
  return decodeRegisterClass(Inst, RegNo, SystemZMC_VR128Regs);
114
2.74k
}
115
116
static DecodeStatus DecodeAR32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
117
    uint64_t Address, const void *Decoder)
118
292
{
119
292
  return decodeRegisterClass(Inst, RegNo, SystemZMC_AR32Regs);
120
292
}
121
122
static DecodeStatus DecodeCR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
123
    uint64_t Address, const void *Decoder)
124
394
{
125
394
  return decodeRegisterClass(Inst, RegNo, SystemZMC_CR64Regs);
126
394
}
127
128
static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm)
129
9.70k
{
130
  //assert(isUInt<N>(Imm) && "Invalid immediate");
131
9.70k
  MCOperand_CreateImm0(Inst, Imm);
132
9.70k
  return MCDisassembler_Success;
133
9.70k
}
134
135
static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, unsigned N)
136
1.93k
{
137
  //assert(isUInt<N>(Imm) && "Invalid immediate");
138
1.93k
  MCOperand_CreateImm0(Inst, SignExtend64(Imm, N));
139
1.93k
  return MCDisassembler_Success;
140
1.93k
}
141
142
static DecodeStatus decodeU1ImmOperand(MCInst *Inst, uint64_t Imm,
143
    uint64_t Address, const void *Decoder)
144
87
{
145
87
  return decodeUImmOperand(Inst, Imm);
146
87
}
147
148
static DecodeStatus decodeU2ImmOperand(MCInst *Inst, uint64_t Imm,
149
    uint64_t Address, const void *Decoder)
150
82
{
151
82
  return decodeUImmOperand(Inst, Imm);
152
82
}
153
154
static DecodeStatus decodeU3ImmOperand(MCInst *Inst, uint64_t Imm,
155
    uint64_t Address, const void *Decoder)
156
55
{
157
55
  return decodeUImmOperand(Inst, Imm);
158
55
}
159
160
static DecodeStatus decodeU4ImmOperand(MCInst *Inst, uint64_t Imm,
161
    uint64_t Address, const void *Decoder)
162
5.56k
{
163
5.56k
  return decodeUImmOperand(Inst, Imm);
164
5.56k
}
165
166
static DecodeStatus decodeU6ImmOperand(MCInst *Inst, uint64_t Imm,
167
    uint64_t Address, const void *Decoder)
168
313
{
169
313
  return decodeUImmOperand(Inst, Imm);
170
313
}
171
172
static DecodeStatus decodeU8ImmOperand(MCInst *Inst, uint64_t Imm,
173
    uint64_t Address, const void *Decoder)
174
1.92k
{
175
1.92k
  return decodeUImmOperand(Inst, Imm);
176
1.92k
}
177
178
static DecodeStatus decodeU12ImmOperand(MCInst *Inst, uint64_t Imm,
179
    uint64_t Address, const void *Decoder)
180
446
{
181
446
  return decodeUImmOperand(Inst, Imm);
182
446
}
183
184
static DecodeStatus decodeU16ImmOperand(MCInst *Inst, uint64_t Imm,
185
    uint64_t Address, const void *Decoder)
186
765
{
187
765
  return decodeUImmOperand(Inst, Imm);
188
765
}
189
190
static DecodeStatus decodeU32ImmOperand(MCInst *Inst, uint64_t Imm,
191
    uint64_t Address, const void *Decoder)
192
472
{
193
472
  return decodeUImmOperand(Inst, Imm);
194
472
}
195
196
static DecodeStatus decodeS8ImmOperand(MCInst *Inst, uint64_t Imm,
197
    uint64_t Address, const void *Decoder)
198
180
{
199
180
  return decodeSImmOperand(Inst, Imm, 8);
200
180
}
201
202
static DecodeStatus decodeS16ImmOperand(MCInst *Inst, uint64_t Imm,
203
    uint64_t Address, const void *Decoder) 
204
1.40k
{
205
1.40k
  return decodeSImmOperand(Inst, Imm, 16);
206
1.40k
}
207
208
static DecodeStatus decodeS32ImmOperand(MCInst *Inst, uint64_t Imm,
209
    uint64_t Address, const void *Decoder)
210
352
{
211
352
  return decodeSImmOperand(Inst, Imm, 32);
212
352
}
213
214
static DecodeStatus decodePCDBLOperand(MCInst *Inst, uint64_t Imm,
215
    uint64_t Address, unsigned N)
216
1.70k
{
217
  //assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
218
1.70k
  MCOperand_CreateImm0(Inst, SignExtend64(Imm, N) * 2 + Address);
219
1.70k
  return MCDisassembler_Success;
220
1.70k
}
221
222
static DecodeStatus decodePC12DBLBranchOperand(MCInst *Inst, uint64_t Imm,
223
    uint64_t Address,
224
    const void *Decoder)
225
174
{
226
174
  return decodePCDBLOperand(Inst, Imm, Address, 12);
227
174
}
228
229
static DecodeStatus decodePC16DBLBranchOperand(MCInst *Inst, uint64_t Imm,
230
    uint64_t Address,
231
    const void *Decoder)
232
786
{
233
786
  return decodePCDBLOperand(Inst, Imm, Address, 16);
234
786
}
235
236
static DecodeStatus decodePC24DBLBranchOperand(MCInst *Inst, uint64_t Imm,
237
    uint64_t Address,
238
    const void *Decoder)
239
174
{
240
174
  return decodePCDBLOperand(Inst, Imm, Address, 24);
241
174
}
242
243
static DecodeStatus decodePC32DBLBranchOperand(MCInst *Inst, uint64_t Imm,
244
    uint64_t Address,
245
    const void *Decoder)
246
167
{
247
167
  return decodePCDBLOperand(Inst, Imm, Address, 32);
248
167
}
249
250
static DecodeStatus decodePC32DBLOperand(MCInst *Inst, uint64_t Imm,
251
    uint64_t Address,
252
    const void *Decoder)
253
408
{
254
408
  return decodePCDBLOperand(Inst, Imm, Address, 32);
255
408
}
256
257
static DecodeStatus decodeBDAddr12Operand(MCInst *Inst, uint64_t Field,
258
    const unsigned *Regs)
259
3.99k
{
260
3.99k
  uint64_t Base = Field >> 12;
261
3.99k
  uint64_t Disp = Field & 0xfff;
262
  //assert(Base < 16 && "Invalid BDAddr12");
263
264
3.99k
  MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
265
3.99k
  MCOperand_CreateImm0(Inst, Disp);
266
267
3.99k
  return MCDisassembler_Success;
268
3.99k
}
269
270
static DecodeStatus decodeBDAddr20Operand(MCInst *Inst, uint64_t Field,
271
    const unsigned *Regs)
272
1.10k
{
273
1.10k
  uint64_t Base = Field >> 20;
274
1.10k
  uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
275
  //assert(Base < 16 && "Invalid BDAddr20");
276
277
1.10k
  MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
278
1.10k
  MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20));
279
1.10k
  return MCDisassembler_Success;
280
1.10k
}
281
282
static DecodeStatus decodeBDXAddr12Operand(MCInst *Inst, uint64_t Field,
283
    const unsigned *Regs)
284
5.02k
{
285
5.02k
  uint64_t Index = Field >> 16;
286
5.02k
  uint64_t Base = (Field >> 12) & 0xf;
287
5.02k
  uint64_t Disp = Field & 0xfff;
288
289
  //assert(Index < 16 && "Invalid BDXAddr12");
290
5.02k
  MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
291
5.02k
  MCOperand_CreateImm0(Inst, Disp);
292
5.02k
  MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]);
293
294
5.02k
  return MCDisassembler_Success;
295
5.02k
}
296
297
static DecodeStatus decodeBDXAddr20Operand(MCInst *Inst, uint64_t Field,
298
    const unsigned *Regs)
299
665
{
300
665
  uint64_t Index = Field >> 24;
301
665
  uint64_t Base = (Field >> 20) & 0xf;
302
665
  uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
303
304
  //assert(Index < 16 && "Invalid BDXAddr20");
305
665
  MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
306
665
  MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20));
307
665
  MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]);
308
309
665
  return MCDisassembler_Success;
310
665
}
311
312
static DecodeStatus decodeBDLAddr12Len8Operand(MCInst *Inst, uint64_t Field,
313
    const unsigned *Regs)
314
3.16k
{
315
3.16k
  uint64_t Length = Field >> 16;
316
3.16k
  uint64_t Base = (Field >> 12) & 0xf;
317
3.16k
  uint64_t Disp = Field & 0xfff;
318
  //assert(Length < 256 && "Invalid BDLAddr12Len8");
319
320
3.16k
  MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
321
3.16k
  MCOperand_CreateImm0(Inst, Disp);
322
3.16k
  MCOperand_CreateImm0(Inst, Length + 1);
323
324
3.16k
  return MCDisassembler_Success;
325
3.16k
}
326
327
static DecodeStatus decodeBDRAddr12Operand(MCInst *Inst, uint64_t Field,
328
    const unsigned *Regs)
329
356
{
330
356
  uint64_t Length = Field >> 16;
331
356
  uint64_t Base = (Field >> 12) & 0xf;
332
356
  uint64_t Disp = Field & 0xfff;
333
  //assert(Length < 16 && "Invalid BDRAddr12");
334
335
356
  MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
336
356
  MCOperand_CreateImm0(Inst, Disp);
337
356
  MCOperand_CreateReg0(Inst, Regs[Length]);
338
339
356
  return MCDisassembler_Success;
340
356
}
341
342
static DecodeStatus decodeBDVAddr12Operand(MCInst *Inst, uint64_t Field,
343
    const unsigned *Regs)
344
66
{
345
66
  uint64_t Index = Field >> 16;
346
66
  uint64_t Base = (Field >> 12) & 0xf;
347
66
  uint64_t Disp = Field & 0xfff;
348
  //assert(Index < 32 && "Invalid BDVAddr12");
349
350
66
  MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
351
66
  MCOperand_CreateImm0(Inst, Disp);
352
66
  MCOperand_CreateReg0(Inst, SystemZMC_VR128Regs[Index]);
353
354
66
  return MCDisassembler_Success;
355
66
}
356
357
static DecodeStatus decodeBDAddr32Disp12Operand(MCInst *Inst, uint64_t Field,
358
    uint64_t Address, const void *Decoder)
359
493
{
360
493
  return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR32Regs);
361
493
}
362
363
static DecodeStatus decodeBDAddr32Disp20Operand(MCInst *Inst, uint64_t Field,
364
    uint64_t Address, const void *Decoder)
365
154
{
366
154
  return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR32Regs);
367
154
}
368
369
static DecodeStatus decodeBDAddr64Disp12Operand(MCInst *Inst, uint64_t Field,
370
    uint64_t Address, const void *Decoder)
371
3.49k
{
372
3.49k
  return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR64Regs);
373
3.49k
}
374
375
static DecodeStatus decodeBDAddr64Disp20Operand(MCInst *Inst, uint64_t Field,
376
    uint64_t Address, const void *Decoder)
377
955
{
378
955
  return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR64Regs);
379
955
}
380
381
static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst *Inst, uint64_t Field,
382
    uint64_t Address, const void *Decoder)
383
5.02k
{
384
5.02k
  return decodeBDXAddr12Operand(Inst, Field, SystemZMC_GR64Regs);
385
5.02k
}
386
387
static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst *Inst, uint64_t Field,
388
    uint64_t Address, const void *Decoder)
389
665
{
390
665
  return decodeBDXAddr20Operand(Inst, Field, SystemZMC_GR64Regs);
391
665
}
392
393
static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst *Inst, uint64_t Field,
394
    uint64_t Address, const void *Decoder)
395
2.36k
{
396
2.36k
  return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs);
397
2.36k
}
398
399
static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst *Inst, uint64_t Field,
400
    uint64_t Address, const void *Decoder)
401
802
{
402
802
  return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs);
403
802
}
404
405
static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst *Inst, uint64_t Field,
406
    uint64_t Address, const void *Decoder)
407
356
{
408
356
  return decodeBDRAddr12Operand(Inst, Field, SystemZMC_GR64Regs);
409
356
}
410
411
static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst *Inst, uint64_t Field,
412
    uint64_t Address, const void *Decoder)
413
66
{
414
66
  return decodeBDVAddr12Operand(Inst, Field, SystemZMC_GR64Regs);
415
66
}
416
417
418
#define GET_SUBTARGETINFO_ENUM
419
#include "SystemZGenSubtargetInfo.inc"
420
#include "SystemZGenDisassemblerTables.inc"
421
bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,
422
    uint16_t *size, uint64_t address, void *info)
423
29.0k
{
424
29.0k
  uint64_t Inst;
425
29.0k
  const uint8_t *Table;
426
29.0k
  uint16_t I; 
427
428
  // The top 2 bits of the first byte specify the size.
429
29.0k
  if (*code < 0x40) {
430
8.23k
    *size = 2;
431
8.23k
    Table = DecoderTable16;
432
20.8k
  } else if (*code < 0xc0) {
433
11.2k
    *size = 4;
434
11.2k
    Table = DecoderTable32;
435
11.2k
  } else {
436
9.64k
    *size = 6;
437
9.64k
    Table = DecoderTable48;
438
9.64k
  }
439
440
29.0k
  if (code_len < *size)
441
    // short of input data
442
293
    return false;
443
444
28.7k
  if (MI->flat_insn->detail) {
445
28.7k
    memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sysz)+sizeof(cs_sysz));
446
28.7k
  }
447
448
  // Construct the instruction.
449
28.7k
  Inst = 0;
450
146k
  for (I = 0; I < *size; ++I)
451
117k
    Inst = (Inst << 8) | code[I];
452
453
28.7k
  return decodeInstruction(Table, MI, Inst, address, info, 0);
454
29.0k
}
455
456
#define GET_REGINFO_ENUM
457
#define GET_REGINFO_MC_DESC
458
#include "SystemZGenRegisterInfo.inc"
459
void SystemZ_init(MCRegisterInfo *MRI)
460
1.16k
{
461
  /*
462
  InitMCRegisterInfo(SystemZRegDesc, 98, RA, PC,
463
      SystemZMCRegisterClasses, 12,
464
      SystemZRegUnitRoots,
465
      49,
466
      SystemZRegDiffLists,
467
      SystemZRegStrings,
468
      SystemZSubRegIdxLists,
469
      7,
470
      SystemZSubRegIdxRanges,
471
      SystemZRegEncodingTable);
472
  */
473
474
1.16k
  MCRegisterInfo_InitMCRegisterInfo(MRI, SystemZRegDesc, 194,
475
1.16k
      0, 0,
476
1.16k
      SystemZMCRegisterClasses, 21,
477
1.16k
      0, 0,
478
1.16k
      SystemZRegDiffLists,
479
1.16k
      0,
480
1.16k
      SystemZSubRegIdxLists, 7,
481
1.16k
      0);
482
1.16k
}
483
484
#endif