/* Capstone Disassembly Engine, http://www.capstone-engine.org */

/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */

/*    Rot127 <unisono@quyllur.org> 2022-2023 */

/* Automatically translated source file from LLVM. */

/* LLVM-commit: <commit> */

/* LLVM-tag: <tag> */

/* Only small edits allowed. */

/* For multiple similar edits, please create a Patch for the translator. */

/* Capstone's C++ file translator: */

/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */

//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//

//

// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

// See https://llvm.org/LICENSE.txt for license information.

// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

//

//===----------------------------------------------------------------------===//

//

// This class prints an AArch64 MCInst to a .s file.

//

//===----------------------------------------------------------------------===//

#include <capstone/platform.h>

#include <ctype.h>

#include <stdio.h>

#include <stdlib.h>

#include <string.h>

#include "../../Mapping.h"

#include "../../MCInst.h"

#include "../../MCInstPrinter.h"

#include "../../MCRegisterInfo.h"

#include "../../SStream.h"

#include "../../utils.h"

#include "AArch64AddressingModes.h"

#include "AArch64BaseInfo.h"

#include "AArch64DisassemblerExtension.h"

#include "AArch64InstPrinter.h"

#include "AArch64Linkage.h"

#include "AArch64Mapping.h"

#define GET_BANKEDREG_IMPL

#include "AArch64GenSystemOperands.inc"

#define CONCAT(a, b) CONCAT_(a, b)

#define CONCAT_(a, b) a##_##b

#define CONCATs(a, b) CONCATS(a, b)

#define CONCATS(a, b) a##b

#define DEBUG_TYPE "asm-printer"

static void printCustomAliasOperand(

         MCInst *MI, uint64_t Address, unsigned OpIdx,

         unsigned PrintMethodIdx,

         SStream *OS);

#define DECLARE_printComplexRotationOp(Angle, Remainder) \

  static void CONCAT(printComplexRotationOp, CONCAT(Angle, Remainder))( \

    MCInst * MI, unsigned OpNo, SStream *O);

DECLARE_printComplexRotationOp(180, 90);

DECLARE_printComplexRotationOp(90, 0);

static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O);

#define GET_INSTRUCTION_NAME

#define PRINT_ALIAS_INSTR

#include "AArch64GenAsmWriter.inc"

void printRegName(SStream *OS, unsigned Reg)

{

  SStream_concat(OS, "%s%s", markup("<reg:"), getRegisterName(Reg, AArch64_NoRegAltName));

  SStream_concat0(OS, markup(">"));

}

void printRegNameAlt(SStream *OS, unsigned Reg, unsigned AltIdx)

{

  SStream_concat(OS, "%s%s", markup("<reg:"), getRegisterName(Reg, AltIdx));

  SStream_concat0(OS, markup(">"));

}

const char *getRegName(unsigned Reg) { return getRegisterName(Reg, AArch64_NoRegAltName); }

void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O)

{

  bool isAlias = false;

  bool useAliasDetails = map_use_alias_details(MI);

  map_set_fill_detail_ops(MI, useAliasDetails);

  unsigned Opcode = MCInst_getOpcode(MI);

  if (Opcode == AArch64_SYSxt) {

    if (printSysAlias(MI, O)) {

      isAlias = true;

      MCInst_setIsAlias(MI, isAlias);

      if (useAliasDetails)

        return;

    }

  }

  if (Opcode == AArch64_SYSPxt || Opcode == AArch64_SYSPxt_XZR) {

    if (printSyspAlias(MI, O)) {

      isAlias = true;

      MCInst_setIsAlias(MI, isAlias);

      if (useAliasDetails)

        return;

    }

  }

  // RPRFM overlaps PRFM (reg), so try to print it as RPRFM here.

  if ((Opcode == AArch64_PRFMroX) || (Opcode == AArch64_PRFMroW)) {

    if (printRangePrefetchAlias(MI, O, Annot)) {

      isAlias = true;

      MCInst_setIsAlias(MI, isAlias);

      if (useAliasDetails)

        return;

    }

  }

  // SBFM/UBFM should print to a nicer aliased form if possible.

  if (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri ||

    Opcode == AArch64_UBFMXri || Opcode == AArch64_UBFMWri) {

    MCOperand *Op0 = MCInst_getOperand(MI, (0));

    MCOperand *Op1 = MCInst_getOperand(MI, (1));

    MCOperand *Op2 = MCInst_getOperand(MI, (2));

    MCOperand *Op3 = MCInst_getOperand(MI, (3));

    bool IsSigned =

      (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri);

    bool Is64Bit = (Opcode == AArch64_SBFMXri || Opcode == AArch64_UBFMXri);

    if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 &&

      MCOperand_isImm(Op3)) {

      const char *AsmMnemonic = NULL;

      switch (MCOperand_getImm(Op3)) {

      default:

        break;

      case 7:

        if (IsSigned)

          AsmMnemonic = "sxtb";

        else if (!Is64Bit)

          AsmMnemonic = "uxtb";

        break;

      case 15:

        if (IsSigned)

          AsmMnemonic = "sxth";

        else if (!Is64Bit)

          AsmMnemonic = "uxth";

        break;

      case 31:

        // *xtw is only valid for signed 64-bit operations.

        if (Is64Bit && IsSigned)

          AsmMnemonic = "sxtw";

        break;

      }

      if (AsmMnemonic) {

        SStream_concat(O, "%s", AsmMnemonic);

        SStream_concat0(O, " ");

        printRegName(O, MCOperand_getReg(Op0));

        SStream_concat0(O, ", ");

        printRegName(O, getWRegFromXReg(MCOperand_getReg(Op1)));

        if (detail_is_set(MI) && useAliasDetails) {

          AArch64_set_detail_op_reg(MI, 0, MCOperand_getReg(Op0));

          AArch64_set_detail_op_reg(MI, 1, getWRegFromXReg(MCOperand_getReg(Op1)));

          if (strings_match(AsmMnemonic, "uxtb"))

            AArch64_get_detail_op(MI, -1)->ext = AArch64_EXT_UXTB;

          else if (strings_match(AsmMnemonic, "sxtb"))

            AArch64_get_detail_op(MI, -1)->ext = AArch64_EXT_SXTB;

          else if (strings_match(AsmMnemonic, "uxth"))

            AArch64_get_detail_op(MI, -1)->ext = AArch64_EXT_UXTH;

          else if (strings_match(AsmMnemonic, "sxth"))

            AArch64_get_detail_op(MI, -1)->ext = AArch64_EXT_SXTH;

          else if (strings_match(AsmMnemonic, "sxtw"))

            AArch64_get_detail_op(MI, -1)->ext = AArch64_EXT_SXTW;

          else

            AArch64_get_detail_op(MI, -1)->ext = AArch64_EXT_INVALID;

        }

        isAlias = true;

        MCInst_setIsAlias(MI, isAlias);

        if (useAliasDetails)

          return;

        else

          goto add_real_detail;

      }

    }

    // All immediate shifts are aliases, implemented using the Bitfield

    // instruction. In all cases the immediate shift amount shift must be in

    // the range 0 to (reg.size -1).

    if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) {

      const char *AsmMnemonic = NULL;

      int shift = 0;

      int64_t immr = MCOperand_getImm(Op2);

      int64_t imms = MCOperand_getImm(Op3);

      if (Opcode == AArch64_UBFMWri && imms != 0x1F &&

        ((imms + 1) == immr)) {

        AsmMnemonic = "lsl";

        shift = 31 - imms;

      } else if (Opcode == AArch64_UBFMXri && imms != 0x3f &&

             ((imms + 1 == immr))) {

        AsmMnemonic = "lsl";

        shift = 63 - imms;

      } else if (Opcode == AArch64_UBFMWri && imms == 0x1f) {

        AsmMnemonic = "lsr";

        shift = immr;

      } else if (Opcode == AArch64_UBFMXri && imms == 0x3f) {

        AsmMnemonic = "lsr";

        shift = immr;

      } else if (Opcode == AArch64_SBFMWri && imms == 0x1f) {

        AsmMnemonic = "asr";

        shift = immr;

      } else if (Opcode == AArch64_SBFMXri && imms == 0x3f) {

        AsmMnemonic = "asr";

        shift = immr;

      }

      if (AsmMnemonic) {

        SStream_concat(O, "%s", AsmMnemonic);

        SStream_concat0(O, " ");

        printRegName(O, MCOperand_getReg(Op0));

        SStream_concat0(O, ", ");

        printRegName(O, MCOperand_getReg(Op1));

        SStream_concat(O, "%s%s#%d", ", ", markup("<imm:"), shift);

        SStream_concat0(O, markup(">"));

        if (detail_is_set(MI) && useAliasDetails) {

          AArch64_set_detail_op_reg(MI, 0, MCOperand_getReg(Op0));

          AArch64_set_detail_op_reg(MI, 1, MCOperand_getReg(Op1));

          if (strings_match(AsmMnemonic, "lsl"))

            AArch64_get_detail_op(MI, -1)->shift.type = AArch64_SFT_LSL;

          else if (strings_match(AsmMnemonic, "lsr"))

            AArch64_get_detail_op(MI, -1)->shift.type = AArch64_SFT_LSR;

          else if (strings_match(AsmMnemonic, "asr"))

            AArch64_get_detail_op(MI, -1)->shift.type = AArch64_SFT_ASR;

          else

            AArch64_get_detail_op(MI, -1)->shift.type = AArch64_SFT_INVALID;

          AArch64_get_detail_op(MI, -1)->shift.value = shift;

        }

        isAlias = true;

        MCInst_setIsAlias(MI, isAlias);

        if (useAliasDetails)

          return;

        else

          goto add_real_detail;

      }

    }

    // SBFIZ/UBFIZ aliases

    if (MCOperand_getImm(Op2) > MCOperand_getImm(Op3)) {

      SStream_concat(O, "%s", (IsSigned ? "sbfiz" : "ubfiz"));

      SStream_concat0(O, " ");

      printRegName(O, MCOperand_getReg(Op0));

      SStream_concat0(O, ", ");

      printRegName(O, MCOperand_getReg(Op1));

      SStream_concat(O, "%s%s", ", ", markup("<imm:"));

      printUInt32Bang(O, (Is64Bit ? 64 : 32) - MCOperand_getImm(Op2));

      SStream_concat(O, "%s%s%s", markup(">"), ", ", markup("<imm:"));

      printInt64Bang(O, MCOperand_getImm(Op3) + 1);

      SStream_concat0(O, markup(">"));

      if (detail_is_set(MI) && useAliasDetails) {

        AArch64_set_detail_op_reg(MI, 0, MCOperand_getReg(Op0));

        AArch64_set_detail_op_reg(MI, 1, MCOperand_getReg(Op1));

        AArch64_set_detail_op_imm(MI, 2, AArch64_OP_IMM, (Is64Bit ? 64 : 32) - MCOperand_getImm(Op2));

        AArch64_set_detail_op_imm(MI, 3, AArch64_OP_IMM, MCOperand_getImm(Op3) + 1);

      }

      isAlias = true;

      MCInst_setIsAlias(MI, isAlias);

      if (useAliasDetails)

        return;

      else

        goto add_real_detail;

    }

    // Otherwise SBFX/UBFX is the preferred form

    SStream_concat(O, "%s", (IsSigned ? "sbfx" : "ubfx"));

    SStream_concat0(O, " ");

    printRegName(O, MCOperand_getReg(Op0));

    SStream_concat0(O, ", ");

    printRegName(O, MCOperand_getReg(Op1));

    SStream_concat(O, "%s%s", ", ", markup("<imm:"));

    printInt64Bang(O, MCOperand_getImm(Op2));

    SStream_concat(O, "%s%s%s", markup(">"), ", ", markup("<imm:"));

    printInt64Bang(O, MCOperand_getImm(Op3) - MCOperand_getImm(Op2) + 1);

    SStream_concat0(O, markup(">"));

    if (detail_is_set(MI) && useAliasDetails) {

      AArch64_set_detail_op_reg(MI, 0, MCOperand_getReg(Op0));

      AArch64_set_detail_op_reg(MI, 1, MCOperand_getReg(Op1));

      AArch64_set_detail_op_imm(MI, 2, AArch64_OP_IMM, MCOperand_getImm(Op2));

      AArch64_set_detail_op_imm(MI, 3, AArch64_OP_IMM, MCOperand_getImm(Op3) - MCOperand_getImm(Op2) + 1);

    }

    isAlias = true;

    MCInst_setIsAlias(MI, isAlias);

    if (useAliasDetails)

      return;

    else

      goto add_real_detail;

  }

  if (Opcode == AArch64_BFMXri || Opcode == AArch64_BFMWri) {

    isAlias = true;

    MCInst_setIsAlias(MI, isAlias);

    MCOperand *Op0 = MCInst_getOperand(MI, (0)); // Op1 == Op0

    MCOperand *Op2 = MCInst_getOperand(MI, (2));

    int ImmR = MCOperand_getImm(MCInst_getOperand(MI, (3)));

    int ImmS = MCOperand_getImm(MCInst_getOperand(MI, (4)));

    if ((MCOperand_getReg(Op2) == AArch64_WZR ||

       MCOperand_getReg(Op2) == AArch64_XZR) &&

      (ImmR == 0 || ImmS < ImmR) &&

      (AArch64_getFeatureBits(MI->csh->mode, AArch64_FeatureAll) ||

       AArch64_getFeatureBits(MI->csh->mode, AArch64_HasV8_2aOps))) {

      // BFC takes precedence over its entire range, sligtly differently

      // to BFI.

      int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32;

      int LSB = (BitWidth - ImmR) % BitWidth;

      int Width = ImmS + 1;

      SStream_concat0(O, "bfc ");

      printRegName(O, MCOperand_getReg(Op0));

      SStream_concat(O, "%s%s#%d", ", ", markup("<imm:"), LSB);

      SStream_concat(O, "%s%s%s#%d", markup(">"), ", ", markup("<imm:"), Width);

      SStream_concat0(O, markup(">"));

      if (detail_is_set(MI) && useAliasDetails) {

        AArch64_set_detail_op_reg(MI, 0, MCOperand_getReg(Op0));

        AArch64_set_detail_op_imm(MI, 3, AArch64_OP_IMM, LSB);

        AArch64_set_detail_op_imm(MI, 4, AArch64_OP_IMM, Width);

      }

      if (useAliasDetails)

        return;

      else

        goto add_real_detail;

    } else if (ImmS < ImmR) {

      // BFI alias

      int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32;

      int LSB = (BitWidth - ImmR) % BitWidth;

      int Width = ImmS + 1;

      SStream_concat0(O, "bfi ");

      printRegName(O, MCOperand_getReg(Op0));

      SStream_concat0(O, ", ");

      printRegName(O, MCOperand_getReg(Op2));

      SStream_concat(O, "%s%s#%d", ", ", markup("<imm:"), LSB);

      SStream_concat(O, "%s%s%s#%d", markup(">"), ", ", markup("<imm:"), Width);

      SStream_concat0(O, markup(">"));

      if (detail_is_set(MI) && useAliasDetails) {

        AArch64_set_detail_op_reg(MI, 0, MCOperand_getReg(Op0));

        AArch64_set_detail_op_reg(MI, 2, MCOperand_getReg(Op2));

        AArch64_set_detail_op_imm(MI, 3, AArch64_OP_IMM, LSB);

        AArch64_set_detail_op_imm(MI, 4, AArch64_OP_IMM, Width);

      }

      if (useAliasDetails)

        return;

      else

        goto add_real_detail;

    }

    int LSB = ImmR;

    int Width = ImmS - ImmR + 1;

    // Otherwise BFXIL the preferred form

    SStream_concat0(O, "bfxil ");

    printRegName(O, MCOperand_getReg(Op0));

    SStream_concat0(O, ", ");

    printRegName(O, MCOperand_getReg(Op2));

    SStream_concat(O, "%s%s#%d", ", ", markup("<imm:"), LSB);

    SStream_concat(O, "%s%s%s#%d", markup(">"), ", ", markup("<imm:"), Width);

    SStream_concat0(O, markup(">"));

    if (detail_is_set(MI) && useAliasDetails) {

      AArch64_set_detail_op_reg(MI, 0, MCOperand_getReg(Op0));

      AArch64_set_detail_op_reg(MI, 2, MCOperand_getReg(Op2));

      AArch64_set_detail_op_imm(MI, 3, AArch64_OP_IMM, LSB);

      AArch64_set_detail_op_imm(MI, 4, AArch64_OP_IMM, Width);

    }

    if (useAliasDetails)

      return;

  }

  // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift

  // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be

  // printed.

  if ((Opcode == AArch64_MOVZXi || Opcode == AArch64_MOVZWi ||

     Opcode == AArch64_MOVNXi || Opcode == AArch64_MOVNWi) &&

    MCOperand_isExpr(MCInst_getOperand(MI, (1)))) {

    assert(0 && "Expressions are not supported.");

  }

  if ((Opcode == AArch64_MOVKXi || Opcode == AArch64_MOVKWi) &&

    MCOperand_isExpr(MCInst_getOperand(MI, (2)))) {

    assert(0 && "Expressions are not supported.");

  }

  // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but

  // their domains overlap so they need to be prioritized. The chain is "MOVZ

  // lsl #0 > MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest

  // instruction that can represent the move is the MOV alias, and the rest

  // get printed normally.

  if ((Opcode == AArch64_MOVZXi || Opcode == AArch64_MOVZWi) &&

    MCOperand_isImm(MCInst_getOperand(MI, (1))) &&

    MCOperand_isImm(MCInst_getOperand(MI, (2)))) {

    int RegWidth = Opcode == AArch64_MOVZXi ? 64 : 32;

    int Shift = MCOperand_getImm(MCInst_getOperand(MI, (2)));

    uint64_t Value = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, (1)))

             << Shift;

    if (AArch64_AM_isMOVZMovAlias(Value, Shift,

                    Opcode == AArch64_MOVZXi ? 64 : 32)) {

      isAlias = true;

      MCInst_setIsAlias(MI, isAlias);

      SStream_concat0(O, "mov ");

      printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (0))));

      SStream_concat(O, "%s%s", ", ", markup("<imm:"));

      printInt64Bang(O, SignExtend64(Value, RegWidth));

      SStream_concat0(O, markup(">"));

      if (detail_is_set(MI) && useAliasDetails) {

        AArch64_set_detail_op_reg(MI, 0, MCInst_getOpVal(MI, 0));

        AArch64_set_detail_op_imm(MI, 1, AArch64_OP_IMM, SignExtend64(Value, RegWidth));

      }

      if (useAliasDetails)

        return;

    }

  }

  if ((Opcode == AArch64_MOVNXi || Opcode == AArch64_MOVNWi) &&

    MCOperand_isImm(MCInst_getOperand(MI, (1))) &&

    MCOperand_isImm(MCInst_getOperand(MI, (2)))) {

    int RegWidth = Opcode == AArch64_MOVNXi ? 64 : 32;

    int Shift = MCOperand_getImm(MCInst_getOperand(MI, (2)));

    uint64_t Value =

      ~((uint64_t)MCOperand_getImm(MCInst_getOperand(MI, (1))) << Shift);

    if (RegWidth == 32)

      Value = Value & 0xffffffff;

    if (AArch64_AM_isMOVNMovAlias(Value, Shift, RegWidth)) {

      isAlias = true;

      MCInst_setIsAlias(MI, isAlias);

      SStream_concat0(O, "mov ");

      printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (0))));

      SStream_concat(O, "%s%s", ", ", markup("<imm:"));

      printInt64Bang(O, SignExtend64(Value, RegWidth));

      SStream_concat0(O, markup(">"));

      if (detail_is_set(MI) && useAliasDetails) {

        AArch64_set_detail_op_reg(MI, 0, MCInst_getOpVal(MI, 0));

        AArch64_set_detail_op_imm(MI, 1, AArch64_OP_IMM, SignExtend64(Value, RegWidth));

      }

      if (useAliasDetails)

        return;

    }

  }

  if ((Opcode == AArch64_ORRXri || Opcode == AArch64_ORRWri) &&

    (MCOperand_getReg(MCInst_getOperand(MI, (1))) == AArch64_XZR ||

     MCOperand_getReg(MCInst_getOperand(MI, (1))) == AArch64_WZR) &&

    MCOperand_isImm(MCInst_getOperand(MI, (2)))) {

    int RegWidth = Opcode == AArch64_ORRXri ? 64 : 32;

    uint64_t Value = AArch64_AM_decodeLogicalImmediate(

      MCOperand_getImm(MCInst_getOperand(MI, (2))), RegWidth);

    if (!AArch64_AM_isAnyMOVWMovAlias(Value, RegWidth)) {

      isAlias = true;

      MCInst_setIsAlias(MI, isAlias);

      SStream_concat0(O, "mov ");

      printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (0))));

      SStream_concat(O, "%s%s", ", ", markup("<imm:"));

      printInt64Bang(O, SignExtend64(Value, RegWidth));

      SStream_concat0(O, markup(">"));

      if (detail_is_set(MI) && useAliasDetails) {

        AArch64_set_detail_op_reg(MI, 0, MCInst_getOpVal(MI, 0));

        AArch64_set_detail_op_imm(MI, 2, AArch64_OP_IMM, SignExtend64(Value, RegWidth));

      }

      if (useAliasDetails)

        return;

    }

  }

  if (Opcode == AArch64_SPACE) {

    isAlias = true;

    MCInst_setIsAlias(MI, isAlias);

    SStream_concat1(O, ' ');

    SStream_concat(O, "%s", " SPACE ");

    printInt64(O, MCOperand_getImm(MCInst_getOperand(MI, (1))));

    if (detail_is_set(MI) && useAliasDetails) {

      AArch64_set_detail_op_imm(MI, 1, AArch64_OP_IMM, MCInst_getOpVal(MI, 1));

    }

    if (useAliasDetails)

      return;

  }

  if (!isAlias)

    isAlias |= printAliasInstr(MI, Address, O);

add_real_detail:

  MCInst_setIsAlias(MI, isAlias);

  if (!isAlias || !useAliasDetails) {

    map_set_fill_detail_ops(MI, !(isAlias && useAliasDetails));

    if (isAlias)

      SStream_Close(O);

    printInstruction(MI, Address, O);

    if (isAlias)

      SStream_Open(O);

  }

}

static bool isTblTbxInstruction(unsigned Opcode, const char **Layout, bool *IsTbx)

{

  switch (Opcode) {

  case AArch64_TBXv8i8One:

  case AArch64_TBXv8i8Two:

  case AArch64_TBXv8i8Three:

  case AArch64_TBXv8i8Four:

    *IsTbx = true;

    *Layout = ".8b";

    return true;

  case AArch64_TBLv8i8One:

  case AArch64_TBLv8i8Two:

  case AArch64_TBLv8i8Three:

  case AArch64_TBLv8i8Four:

    *IsTbx = false;

    *Layout = ".8b";

    return true;

  case AArch64_TBXv16i8One:

  case AArch64_TBXv16i8Two:

  case AArch64_TBXv16i8Three:

  case AArch64_TBXv16i8Four:

    *IsTbx = true;

    *Layout = ".16b";

    return true;

  case AArch64_TBLv16i8One:

  case AArch64_TBLv16i8Two:

  case AArch64_TBLv16i8Three:

  case AArch64_TBLv16i8Four:

    *IsTbx = false;

    *Layout = ".16b";

    return true;

  default:

    return false;

  }

}

typedef struct LdStNInstrDesc {

  unsigned Opcode;

  const char *Mnemonic;

  const char *Layout;

  int ListOperand;

  bool HasLane;

  int NaturalOffset;

} LdStNInstrDesc;

static const LdStNInstrDesc LdStNInstInfo[] = {

  {AArch64_LD1i8, "ld1", ".b", 1, true, 0},

  {AArch64_LD1i16, "ld1", ".h", 1, true, 0},

  {AArch64_LD1i32, "ld1", ".s", 1, true, 0},

  {AArch64_LD1i64, "ld1", ".d", 1, true, 0},

  {AArch64_LD1i8_POST, "ld1", ".b", 2, true, 1},

  {AArch64_LD1i16_POST, "ld1", ".h", 2, true, 2},

  {AArch64_LD1i32_POST, "ld1", ".s", 2, true, 4},

  {AArch64_LD1i64_POST, "ld1", ".d", 2, true, 8},

  {AArch64_LD1Rv16b, "ld1r", ".16b", 0, false, 0},

  {AArch64_LD1Rv8h, "ld1r", ".8h", 0, false, 0},

  {AArch64_LD1Rv4s, "ld1r", ".4s", 0, false, 0},

  {AArch64_LD1Rv2d, "ld1r", ".2d", 0, false, 0},

  {AArch64_LD1Rv8b, "ld1r", ".8b", 0, false, 0},

  {AArch64_LD1Rv4h, "ld1r", ".4h", 0, false, 0},

  {AArch64_LD1Rv2s, "ld1r", ".2s", 0, false, 0},

  {AArch64_LD1Rv1d, "ld1r", ".1d", 0, false, 0},

  {AArch64_LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1},

  {AArch64_LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2},

  {AArch64_LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4},

  {AArch64_LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8},

  {AArch64_LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1},

  {AArch64_LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2},

  {AArch64_LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4},

  {AArch64_LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8},

  {AArch64_LD1Onev16b, "ld1", ".16b", 0, false, 0},

  {AArch64_LD1Onev8h, "ld1", ".8h", 0, false, 0},

  {AArch64_LD1Onev4s, "ld1", ".4s", 0, false, 0},

  {AArch64_LD1Onev2d, "ld1", ".2d", 0, false, 0},

  {AArch64_LD1Onev8b, "ld1", ".8b", 0, false, 0},

  {AArch64_LD1Onev4h, "ld1", ".4h", 0, false, 0},

  {AArch64_LD1Onev2s, "ld1", ".2s", 0, false, 0},

  {AArch64_LD1Onev1d, "ld1", ".1d", 0, false, 0},

  {AArch64_LD1Onev16b_POST, "ld1", ".16b", 1, false, 16},

  {AArch64_LD1Onev8h_POST, "ld1", ".8h", 1, false, 16},

  {AArch64_LD1Onev4s_POST, "ld1", ".4s", 1, false, 16},

  {AArch64_LD1Onev2d_POST, "ld1", ".2d", 1, false, 16},

  {AArch64_LD1Onev8b_POST, "ld1", ".8b", 1, false, 8},

  {AArch64_LD1Onev4h_POST, "ld1", ".4h", 1, false, 8},

  {AArch64_LD1Onev2s_POST, "ld1", ".2s", 1, false, 8},

  {AArch64_LD1Onev1d_POST, "ld1", ".1d", 1, false, 8},

  {AArch64_LD1Twov16b, "ld1", ".16b", 0, false, 0},

  {AArch64_LD1Twov8h, "ld1", ".8h", 0, false, 0},

  {AArch64_LD1Twov4s, "ld1", ".4s", 0, false, 0},

  {AArch64_LD1Twov2d, "ld1", ".2d", 0, false, 0},

  {AArch64_LD1Twov8b, "ld1", ".8b", 0, false, 0},

  {AArch64_LD1Twov4h, "ld1", ".4h", 0, false, 0},

  {AArch64_LD1Twov2s, "ld1", ".2s", 0, false, 0},

  {AArch64_LD1Twov1d, "ld1", ".1d", 0, false, 0},

  {AArch64_LD1Twov16b_POST, "ld1", ".16b", 1, false, 32},

  {AArch64_LD1Twov8h_POST, "ld1", ".8h", 1, false, 32},

  {AArch64_LD1Twov4s_POST, "ld1", ".4s", 1, false, 32},

  {AArch64_LD1Twov2d_POST, "ld1", ".2d", 1, false, 32},

  {AArch64_LD1Twov8b_POST, "ld1", ".8b", 1, false, 16},

  {AArch64_LD1Twov4h_POST, "ld1", ".4h", 1, false, 16},

  {AArch64_LD1Twov2s_POST, "ld1", ".2s", 1, false, 16},

  {AArch64_LD1Twov1d_POST, "ld1", ".1d", 1, false, 16},

  {AArch64_LD1Threev16b, "ld1", ".16b", 0, false, 0},

  {AArch64_LD1Threev8h, "ld1", ".8h", 0, false, 0},

  {AArch64_LD1Threev4s, "ld1", ".4s", 0, false, 0},

  {AArch64_LD1Threev2d, "ld1", ".2d", 0, false, 0},

  {AArch64_LD1Threev8b, "ld1", ".8b", 0, false, 0},

  {AArch64_LD1Threev4h, "ld1", ".4h", 0, false, 0},

  {AArch64_LD1Threev2s, "ld1", ".2s", 0, false, 0},

  {AArch64_LD1Threev1d, "ld1", ".1d", 0, false, 0},

  {AArch64_LD1Threev16b_POST, "ld1", ".16b", 1, false, 48},

  {AArch64_LD1Threev8h_POST, "ld1", ".8h", 1, false, 48},

  {AArch64_LD1Threev4s_POST, "ld1", ".4s", 1, false, 48},

  {AArch64_LD1Threev2d_POST, "ld1", ".2d", 1, false, 48},

  {AArch64_LD1Threev8b_POST, "ld1", ".8b", 1, false, 24},

  {AArch64_LD1Threev4h_POST, "ld1", ".4h", 1, false, 24},

  {AArch64_LD1Threev2s_POST, "ld1", ".2s", 1, false, 24},

  {AArch64_LD1Threev1d_POST, "ld1", ".1d", 1, false, 24},

  {AArch64_LD1Fourv16b, "ld1", ".16b", 0, false, 0},

  {AArch64_LD1Fourv8h, "ld1", ".8h", 0, false, 0},

  {AArch64_LD1Fourv4s, "ld1", ".4s", 0, false, 0},

  {AArch64_LD1Fourv2d, "ld1", ".2d", 0, false, 0},

  {AArch64_LD1Fourv8b, "ld1", ".8b", 0, false, 0},

  {AArch64_LD1Fourv4h, "ld1", ".4h", 0, false, 0},

  {AArch64_LD1Fourv2s, "ld1", ".2s", 0, false, 0},

  {AArch64_LD1Fourv1d, "ld1", ".1d", 0, false, 0},

  {AArch64_LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64},

  {AArch64_LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64},

  {AArch64_LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64},

  {AArch64_LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64},

  {AArch64_LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32},

  {AArch64_LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32},

  {AArch64_LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32},

  {AArch64_LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32},

  {AArch64_LD2i8, "ld2", ".b", 1, true, 0},

  {AArch64_LD2i16, "ld2", ".h", 1, true, 0},

  {AArch64_LD2i32, "ld2", ".s", 1, true, 0},

  {AArch64_LD2i64, "ld2", ".d", 1, true, 0},

  {AArch64_LD2i8_POST, "ld2", ".b", 2, true, 2},

  {AArch64_LD2i16_POST, "ld2", ".h", 2, true, 4},

  {AArch64_LD2i32_POST, "ld2", ".s", 2, true, 8},

  {AArch64_LD2i64_POST, "ld2", ".d", 2, true, 16},

  {AArch64_LD2Rv16b, "ld2r", ".16b", 0, false, 0},

  {AArch64_LD2Rv8h, "ld2r", ".8h", 0, false, 0},

  {AArch64_LD2Rv4s, "ld2r", ".4s", 0, false, 0},

  {AArch64_LD2Rv2d, "ld2r", ".2d", 0, false, 0},

  {AArch64_LD2Rv8b, "ld2r", ".8b", 0, false, 0},

  {AArch64_LD2Rv4h, "ld2r", ".4h", 0, false, 0},

  {AArch64_LD2Rv2s, "ld2r", ".2s", 0, false, 0},

  {AArch64_LD2Rv1d, "ld2r", ".1d", 0, false, 0},

  {AArch64_LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2},

  {AArch64_LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4},

  {AArch64_LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8},

  {AArch64_LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16},

  {AArch64_LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2},

  {AArch64_LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4},

  {AArch64_LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8},

  {AArch64_LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16},

  {AArch64_LD2Twov16b, "ld2", ".16b", 0, false, 0},

  {AArch64_LD2Twov8h, "ld2", ".8h", 0, false, 0},

  {AArch64_LD2Twov4s, "ld2", ".4s", 0, false, 0},

  {AArch64_LD2Twov2d, "ld2", ".2d", 0, false, 0},

  {AArch64_LD2Twov8b, "ld2", ".8b", 0, false, 0},

  {AArch64_LD2Twov4h, "ld2", ".4h", 0, false, 0},

  {AArch64_LD2Twov2s, "ld2", ".2s", 0, false, 0},

  {AArch64_LD2Twov16b_POST, "ld2", ".16b", 1, false, 32},

  {AArch64_LD2Twov8h_POST, "ld2", ".8h", 1, false, 32},

  {AArch64_LD2Twov4s_POST, "ld2", ".4s", 1, false, 32},

  {AArch64_LD2Twov2d_POST, "ld2", ".2d", 1, false, 32},

  {AArch64_LD2Twov8b_POST, "ld2", ".8b", 1, false, 16},

  {AArch64_LD2Twov4h_POST, "ld2", ".4h", 1, false, 16},

  {AArch64_LD2Twov2s_POST, "ld2", ".2s", 1, false, 16},

  {AArch64_LD3i8, "ld3", ".b", 1, true, 0},

  {AArch64_LD3i16, "ld3", ".h", 1, true, 0},

  {AArch64_LD3i32, "ld3", ".s", 1, true, 0},

  {AArch64_LD3i64, "ld3", ".d", 1, true, 0},

  {AArch64_LD3i8_POST, "ld3", ".b", 2, true, 3},

  {AArch64_LD3i16_POST, "ld3", ".h", 2, true, 6},

  {AArch64_LD3i32_POST, "ld3", ".s", 2, true, 12},

  {AArch64_LD3i64_POST, "ld3", ".d", 2, true, 24},

  {AArch64_LD3Rv16b, "ld3r", ".16b", 0, false, 0},

  {AArch64_LD3Rv8h, "ld3r", ".8h", 0, false, 0},

  {AArch64_LD3Rv4s, "ld3r", ".4s", 0, false, 0},

  {AArch64_LD3Rv2d, "ld3r", ".2d", 0, false, 0},

  {AArch64_LD3Rv8b, "ld3r", ".8b", 0, false, 0},

  {AArch64_LD3Rv4h, "ld3r", ".4h", 0, false, 0},

  {AArch64_LD3Rv2s, "ld3r", ".2s", 0, false, 0},

  {AArch64_LD3Rv1d, "ld3r", ".1d", 0, false, 0},

  {AArch64_LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3},

  {AArch64_LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6},

  {AArch64_LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12},

  {AArch64_LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24},

  {AArch64_LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3},

  {AArch64_LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6},

  {AArch64_LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12},

  {AArch64_LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24},

  {AArch64_LD3Threev16b, "ld3", ".16b", 0, false, 0},

  {AArch64_LD3Threev8h, "ld3", ".8h", 0, false, 0},

  {AArch64_LD3Threev4s, "ld3", ".4s", 0, false, 0},

  {AArch64_LD3Threev2d, "ld3", ".2d", 0, false, 0},

  {AArch64_LD3Threev8b, "ld3", ".8b", 0, false, 0},

  {AArch64_LD3Threev4h, "ld3", ".4h", 0, false, 0},

  {AArch64_LD3Threev2s, "ld3", ".2s", 0, false, 0},

  {AArch64_LD3Threev16b_POST, "ld3", ".16b", 1, false, 48},

  {AArch64_LD3Threev8h_POST, "ld3", ".8h", 1, false, 48},

  {AArch64_LD3Threev4s_POST, "ld3", ".4s", 1, false, 48},

  {AArch64_LD3Threev2d_POST, "ld3", ".2d", 1, false, 48},

  {AArch64_LD3Threev8b_POST, "ld3", ".8b", 1, false, 24},

  {AArch64_LD3Threev4h_POST, "ld3", ".4h", 1, false, 24},

  {AArch64_LD3Threev2s_POST, "ld3", ".2s", 1, false, 24},

  {AArch64_LD4i8, "ld4", ".b", 1, true, 0},

  {AArch64_LD4i16, "ld4", ".h", 1, true, 0},

  {AArch64_LD4i32, "ld4", ".s", 1, true, 0},

  {AArch64_LD4i64, "ld4", ".d", 1, true, 0},

  {AArch64_LD4i8_POST, "ld4", ".b", 2, true, 4},

  {AArch64_LD4i16_POST, "ld4", ".h", 2, true, 8},

  {AArch64_LD4i32_POST, "ld4", ".s", 2, true, 16},

  {AArch64_LD4i64_POST, "ld4", ".d", 2, true, 32},

  {AArch64_LD4Rv16b, "ld4r", ".16b", 0, false, 0},

  {AArch64_LD4Rv8h, "ld4r", ".8h", 0, false, 0},

  {AArch64_LD4Rv4s, "ld4r", ".4s", 0, false, 0},

  {AArch64_LD4Rv2d, "ld4r", ".2d", 0, false, 0},

  {AArch64_LD4Rv8b, "ld4r", ".8b", 0, false, 0},

  {AArch64_LD4Rv4h, "ld4r", ".4h", 0, false, 0},

  {AArch64_LD4Rv2s, "ld4r", ".2s", 0, false, 0},

  {AArch64_LD4Rv1d, "ld4r", ".1d", 0, false, 0},

  {AArch64_LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4},

  {AArch64_LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8},

  {AArch64_LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16},

  {AArch64_LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32},

  {AArch64_LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4},

  {AArch64_LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8},

  {AArch64_LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16},

  {AArch64_LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32},

  {AArch64_LD4Fourv16b, "ld4", ".16b", 0, false, 0},

  {AArch64_LD4Fourv8h, "ld4", ".8h", 0, false, 0},

  {AArch64_LD4Fourv4s, "ld4", ".4s", 0, false, 0},

  {AArch64_LD4Fourv2d, "ld4", ".2d", 0, false, 0},

  {AArch64_LD4Fourv8b, "ld4", ".8b", 0, false, 0},

  {AArch64_LD4Fourv4h, "ld4", ".4h", 0, false, 0},

  {AArch64_LD4Fourv2s, "ld4", ".2s", 0, false, 0},

  {AArch64_LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64},

  {AArch64_LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64},

  {AArch64_LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64},

  {AArch64_LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64},

  {AArch64_LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32},

  {AArch64_LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32},

  {AArch64_LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32},

  {AArch64_ST1i8, "st1", ".b", 0, true, 0},

  {AArch64_ST1i16, "st1", ".h", 0, true, 0},

  {AArch64_ST1i32, "st1", ".s", 0, true, 0},

  {AArch64_ST1i64, "st1", ".d", 0, true, 0},

  {AArch64_ST1i8_POST, "st1", ".b", 1, true, 1},

  {AArch64_ST1i16_POST, "st1", ".h", 1, true, 2},

  {AArch64_ST1i32_POST, "st1", ".s", 1, true, 4},

  {AArch64_ST1i64_POST, "st1", ".d", 1, true, 8},

  {AArch64_ST1Onev16b, "st1", ".16b", 0, false, 0},

  {AArch64_ST1Onev8h, "st1", ".8h", 0, false, 0},

  {AArch64_ST1Onev4s, "st1", ".4s", 0, false, 0},

  {AArch64_ST1Onev2d, "st1", ".2d", 0, false, 0},

  {AArch64_ST1Onev8b, "st1", ".8b", 0, false, 0},

  {AArch64_ST1Onev4h, "st1", ".4h", 0, false, 0},

  {AArch64_ST1Onev2s, "st1", ".2s", 0, false, 0},

  {AArch64_ST1Onev1d, "st1", ".1d", 0, false, 0},

  {AArch64_ST1Onev16b_POST, "st1", ".16b", 1, false, 16},

  {AArch64_ST1Onev8h_POST, "st1", ".8h", 1, false, 16},

  {AArch64_ST1Onev4s_POST, "st1", ".4s", 1, false, 16},

  {AArch64_ST1Onev2d_POST, "st1", ".2d", 1, false, 16},

  {AArch64_ST1Onev8b_POST, "st1", ".8b", 1, false, 8},

  {AArch64_ST1Onev4h_POST, "st1", ".4h", 1, false, 8},

  {AArch64_ST1Onev2s_POST, "st1", ".2s", 1, false, 8},

  {AArch64_ST1Onev1d_POST, "st1", ".1d", 1, false, 8},

  {AArch64_ST1Twov16b, "st1", ".16b", 0, false, 0},

  {AArch64_ST1Twov8h, "st1", ".8h", 0, false, 0},

  {AArch64_ST1Twov4s, "st1", ".4s", 0, false, 0},

  {AArch64_ST1Twov2d, "st1", ".2d", 0, false, 0},

  {AArch64_ST1Twov8b, "st1", ".8b", 0, false, 0},

  {AArch64_ST1Twov4h, "st1", ".4h", 0, false, 0},

  {AArch64_ST1Twov2s, "st1", ".2s", 0, false, 0},

  {AArch64_ST1Twov1d, "st1", ".1d", 0, false, 0},

  {AArch64_ST1Twov16b_POST, "st1", ".16b", 1, false, 32},

  {AArch64_ST1Twov8h_POST, "st1", ".8h", 1, false, 32},

  {AArch64_ST1Twov4s_POST, "st1", ".4s", 1, false, 32},

  {AArch64_ST1Twov2d_POST, "st1", ".2d", 1, false, 32},

  {AArch64_ST1Twov8b_POST, "st1", ".8b", 1, false, 16},

  {AArch64_ST1Twov4h_POST, "st1", ".4h", 1, false, 16},

  {AArch64_ST1Twov2s_POST, "st1", ".2s", 1, false, 16},

  {AArch64_ST1Twov1d_POST, "st1", ".1d", 1, false, 16},

  {AArch64_ST1Threev16b, "st1", ".16b", 0, false, 0},

  {AArch64_ST1Threev8h, "st1", ".8h", 0, false, 0},

  {AArch64_ST1Threev4s, "st1", ".4s", 0, false, 0},

  {AArch64_ST1Threev2d, "st1", ".2d", 0, false, 0},

  {AArch64_ST1Threev8b, "st1", ".8b", 0, false, 0},

  {AArch64_ST1Threev4h, "st1", ".4h", 0, false, 0},

  {AArch64_ST1Threev2s, "st1", ".2s", 0, false, 0},

  {AArch64_ST1Threev1d, "st1", ".1d", 0, false, 0},

  {AArch64_ST1Threev16b_POST, "st1", ".16b", 1, false, 48},

  {AArch64_ST1Threev8h_POST, "st1", ".8h", 1, false, 48},

  {AArch64_ST1Threev4s_POST, "st1", ".4s", 1, false, 48},

  {AArch64_ST1Threev2d_POST, "st1", ".2d", 1, false, 48},

  {AArch64_ST1Threev8b_POST, "st1", ".8b", 1, false, 24},

  {AArch64_ST1Threev4h_POST, "st1", ".4h", 1, false, 24},

  {AArch64_ST1Threev2s_POST, "st1", ".2s", 1, false, 24},

  {AArch64_ST1Threev1d_POST, "st1", ".1d", 1, false, 24},

  {AArch64_ST1Fourv16b, "st1", ".16b", 0, false, 0},

  {AArch64_ST1Fourv8h, "st1", ".8h", 0, false, 0},

  {AArch64_ST1Fourv4s, "st1", ".4s", 0, false, 0},

  {AArch64_ST1Fourv2d, "st1", ".2d", 0, false, 0},

  {AArch64_ST1Fourv8b, "st1", ".8b", 0, false, 0},

  {AArch64_ST1Fourv4h, "st1", ".4h", 0, false, 0},

  {AArch64_ST1Fourv2s, "st1", ".2s", 0, false, 0},

  {AArch64_ST1Fourv1d, "st1", ".1d", 0, false, 0},

  {AArch64_ST1Fourv16b_POST, "st1", ".16b", 1, false, 64},

  {AArch64_ST1Fourv8h_POST, "st1", ".8h", 1, false, 64},

  {AArch64_ST1Fourv4s_POST, "st1", ".4s", 1, false, 64},

  {AArch64_ST1Fourv2d_POST, "st1", ".2d", 1, false, 64},

  {AArch64_ST1Fourv8b_POST, "st1", ".8b", 1, false, 32},

  {AArch64_ST1Fourv4h_POST, "st1", ".4h", 1, false, 32},

  {AArch64_ST1Fourv2s_POST, "st1", ".2s", 1, false, 32},

  {AArch64_ST1Fourv1d_POST, "st1", ".1d", 1, false, 32},

  {AArch64_ST2i8, "st2", ".b", 0, true, 0},

  {AArch64_ST2i16, "st2", ".h", 0, true, 0},

  {AArch64_ST2i32, "st2", ".s", 0, true, 0},

  {AArch64_ST2i64, "st2", ".d", 0, true, 0},

  {AArch64_ST2i8_POST, "st2", ".b", 1, true, 2},

  {AArch64_ST2i16_POST, "st2", ".h", 1, true, 4},

  {AArch64_ST2i32_POST, "st2", ".s", 1, true, 8},

  {AArch64_ST2i64_POST, "st2", ".d", 1, true, 16},

  {AArch64_ST2Twov16b, "st2", ".16b", 0, false, 0},

  {AArch64_ST2Twov8h, "st2", ".8h", 0, false, 0},

  {AArch64_ST2Twov4s, "st2", ".4s", 0, false, 0},

  {AArch64_ST2Twov2d, "st2", ".2d", 0, false, 0},

  {AArch64_ST2Twov8b, "st2", ".8b", 0, false, 0},

  {AArch64_ST2Twov4h, "st2", ".4h", 0, false, 0},

  {AArch64_ST2Twov2s, "st2", ".2s", 0, false, 0},

  {AArch64_ST2Twov16b_POST, "st2", ".16b", 1, false, 32},

  {AArch64_ST2Twov8h_POST, "st2", ".8h", 1, false, 32},

  {AArch64_ST2Twov4s_POST, "st2", ".4s", 1, false, 32},

  {AArch64_ST2Twov2d_POST, "st2", ".2d", 1, false, 32},

  {AArch64_ST2Twov8b_POST, "st2", ".8b", 1, false, 16},

  {AArch64_ST2Twov4h_POST, "st2", ".4h", 1, false, 16},

  {AArch64_ST2Twov2s_POST, "st2", ".2s", 1, false, 16},

  {AArch64_ST3i8, "st3", ".b", 0, true, 0},

  {AArch64_ST3i16, "st3", ".h", 0, true, 0},

  {AArch64_ST3i32, "st3", ".s", 0, true, 0},

  {AArch64_ST3i64, "st3", ".d", 0, true, 0},

  {AArch64_ST3i8_POST, "st3", ".b", 1, true, 3},

  {AArch64_ST3i16_POST, "st3", ".h", 1, true, 6},

  {AArch64_ST3i32_POST, "st3", ".s", 1, true, 12},

  {AArch64_ST3i64_POST, "st3", ".d", 1, true, 24},

  {AArch64_ST3Threev16b, "st3", ".16b", 0, false, 0},

  {AArch64_ST3Threev8h, "st3", ".8h", 0, false, 0},

  {AArch64_ST3Threev4s, "st3", ".4s", 0, false, 0},

  {AArch64_ST3Threev2d, "st3", ".2d", 0, false, 0},

  {AArch64_ST3Threev8b, "st3", ".8b", 0, false, 0},

  {AArch64_ST3Threev4h, "st3", ".4h", 0, false, 0},

  {AArch64_ST3Threev2s, "st3", ".2s", 0, false, 0},

  {AArch64_ST3Threev16b_POST, "st3", ".16b", 1, false, 48},

  {AArch64_ST3Threev8h_POST, "st3", ".8h", 1, false, 48},

  {AArch64_ST3Threev4s_POST, "st3", ".4s", 1, false, 48},

  {AArch64_ST3Threev2d_POST, "st3", ".2d", 1, false, 48},

  {AArch64_ST3Threev8b_POST, "st3", ".8b", 1, false, 24},

  {AArch64_ST3Threev4h_POST, "st3", ".4h", 1, false, 24},

  {AArch64_ST3Threev2s_POST, "st3", ".2s", 1, false, 24},

  {AArch64_ST4i8, "st4", ".b", 0, true, 0},

  {AArch64_ST4i16, "st4", ".h", 0, true, 0},

  {AArch64_ST4i32, "st4", ".s", 0, true, 0},

  {AArch64_ST4i64, "st4", ".d", 0, true, 0},

  {AArch64_ST4i8_POST, "st4", ".b", 1, true, 4},

  {AArch64_ST4i16_POST, "st4", ".h", 1, true, 8},

  {AArch64_ST4i32_POST, "st4", ".s", 1, true, 16},

  {AArch64_ST4i64_POST, "st4", ".d", 1, true, 32},

  {AArch64_ST4Fourv16b, "st4", ".16b", 0, false, 0},

  {AArch64_ST4Fourv8h, "st4", ".8h", 0, false, 0},

  {AArch64_ST4Fourv4s, "st4", ".4s", 0, false, 0},

  {AArch64_ST4Fourv2d, "st4", ".2d", 0, false, 0},

  {AArch64_ST4Fourv8b, "st4", ".8b", 0, false, 0},

  {AArch64_ST4Fourv4h, "st4", ".4h", 0, false, 0},

  {AArch64_ST4Fourv2s, "st4", ".2s", 0, false, 0},

  {AArch64_ST4Fourv16b_POST, "st4", ".16b", 1, false, 64},

  {AArch64_ST4Fourv8h_POST, "st4", ".8h", 1, false, 64},

  {AArch64_ST4Fourv4s_POST, "st4", ".4s", 1, false, 64},

  {AArch64_ST4Fourv2d_POST, "st4", ".2d", 1, false, 64},

  {AArch64_ST4Fourv8b_POST, "st4", ".8b", 1, false, 32},

  {AArch64_ST4Fourv4h_POST, "st4", ".4h", 1, false, 32},

  {AArch64_ST4Fourv2s_POST, "st4", ".2s", 1, false, 32},

};

static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode)

{

  for (int i = 0; i < (sizeof(LdStNInstInfo)/sizeof(LdStNInstInfo[0])); ++i) {

    const LdStNInstrDesc *Info = &LdStNInstInfo[i];

    if (Info->Opcode == Opcode)

      return Info;

  }

  return NULL;

}

void AArch64AppleInstPrinter_printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O)

{

  unsigned Opcode = MCInst_getOpcode(MI);

  const char *Layout;

  bool IsTbx;

  if (isTblTbxInstruction(MCInst_getOpcode(MI), &Layout, &IsTbx)) {

    SStream_concat(O, "%s%s", (IsTbx ? "tbx" : "tbl"), Layout);

    SStream_concat0(O, " ");

    printRegNameAlt(O, MCOperand_getReg(MCInst_getOperand(MI, (0))),

           AArch64_vreg);

    SStream_concat0(O, ", ");

    unsigned ListOpNum = IsTbx ? 2 : 1;

    printVectorList(MI, ListOpNum, O, "");

    SStream_concat0(O, ", ");

    printRegNameAlt(O,

           MCOperand_getReg(MCInst_getOperand(MI, (ListOpNum + 1))),

           AArch64_vreg);

    ;

    return;

  }

  const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode);

  if (LdStDesc) {

    SStream_concat(O, "%s%s", LdStDesc->Mnemonic, LdStDesc->Layout);

    SStream_concat0(O, " ");

    // Now onto the operands: first a vector list with possible lane

    // specifier. E.g. { v0 }[2]

    int OpNum = LdStDesc->ListOperand;

    printVectorList(MI, OpNum++, O, "");

    if (LdStDesc->HasLane) {

      SStream_concat1(O, '[');

      SStream_concat(O, "%s",

               MCOperand_getImm(MCInst_getOperand(MI, (OpNum++))));

      SStream_concat0(O, "]");

    }

    // Next the address: [xN]

    unsigned AddrReg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum++)));

    SStream_concat0(O, ", [");

    printRegName(O, AddrReg);

    SStream_concat0(O, "]");

    // Finally, there might be a post-indexed offset.

    if (LdStDesc->NaturalOffset != 0) {

      unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum++)));

      if (Reg != AArch64_XZR) {

        SStream_concat0(O, ", ");

        printRegName(O, Reg);

      } else {

        SStream_concat(O, "%s%s%s%s", ", ", markup("<imm:"), "#",

                 LdStDesc->NaturalOffset);

        SStream_concat0(O, markup(">"));

      }

    }

    ;

    return;

  }

  printInst(MI, Address, Annot, O);

}

bool printRangePrefetchAlias(MCInst *MI, SStream *O, const char *Annot)

{

  unsigned Opcode = MCInst_getOpcode(MI);

#ifndef NDEBUG

#endif

  unsigned PRFOp = MCOperand_getImm(MCInst_getOperand(MI, (0)));

  unsigned Mask = 0x18; // 0b11000

  if ((PRFOp & Mask) != Mask)

    return false;    // Rt != '11xxx', it's a PRFM instruction.

  unsigned Rm = MCOperand_getReg(MCInst_getOperand(MI, (2)));

  // "Rm" must be a 64-bit GPR for RPRFM.

  if (MCRegisterInfo_getRegClass(MI->MRI, Rm))

    Rm = MCRegisterInfo_getMatchingSuperReg(MI->MRI, Rm, AArch64_sub_32,

                   MCRegisterInfo_getRegClass(MI->MRI, Rm));

  unsigned SignExtend =

    MCOperand_getImm(MCInst_getOperand(MI, (3))); // encoded in "option<2>".

  unsigned Shift =

    MCOperand_getImm(MCInst_getOperand(MI, (4))); // encoded in "S".

  unsigned Option0 = (Opcode == AArch64_PRFMroX) ? 1 : 0;

  // encoded in "option<2>:option<0>:S:Rt<2:0>".

  unsigned RPRFOp =

    (SignExtend << 5) | (Option0 << 4) | (Shift << 3) | (PRFOp & 0x7);

  SStream_concat0(O, "rprfm ");

  const AArch64RPRFM_RPRFM *RPRFM = AArch64RPRFM_lookupRPRFMByEncoding(RPRFOp);

  if (RPRFM) {

    SStream_concat0(O, RPRFM->Name);

    if (detail_is_set(MI)) {

      aarch64_sysop sysop;

      sysop.alias = RPRFM->SysAlias;

      sysop.sub_type = AArch64_OP_RPRFM;

      AArch64_get_detail_op(MI, 0)->type = AArch64_OP_SYSALIAS;

      AArch64_get_detail_op(MI, 0)->sysop = sysop;

      AArch64_inc_op_count(MI);

    }

  }

  SStream_concat0(O, ", [");

  printOperand(MI, 1, O); // "Rn".

  SStream_concat0(O, "]");

  ;

  return true;

}