Coverage Report

Created: 2023-12-08 06:05

/src/capstonenext/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|*Assembly Writer Source Fragment                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
15
16
/// printInstruction - This method is automatically generated by tablegen
17
/// from the instruction set description.
18
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19
29.5k
{
20
29.5k
  static const uint32_t OpInfo[] = {
21
29.5k
    0U, // PHI
22
29.5k
    0U, // INLINEASM
23
29.5k
    0U, // CFI_INSTRUCTION
24
29.5k
    0U, // EH_LABEL
25
29.5k
    0U, // GC_LABEL
26
29.5k
    0U, // KILL
27
29.5k
    0U, // EXTRACT_SUBREG
28
29.5k
    0U, // INSERT_SUBREG
29
29.5k
    0U, // IMPLICIT_DEF
30
29.5k
    0U, // SUBREG_TO_REG
31
29.5k
    0U, // COPY_TO_REGCLASS
32
29.5k
    2452U,  // DBG_VALUE
33
29.5k
    0U, // REG_SEQUENCE
34
29.5k
    0U, // COPY
35
29.5k
    2445U,  // BUNDLE
36
29.5k
    2462U,  // LIFETIME_START
37
29.5k
    2432U,  // LIFETIME_END
38
29.5k
    0U, // STACKMAP
39
29.5k
    0U, // PATCHPOINT
40
29.5k
    0U, // LOAD_STACK_GUARD
41
29.5k
    0U, // STATEPOINT
42
29.5k
    0U, // FRAME_ALLOC
43
29.5k
    4688U,  // ADDCCri
44
29.5k
    4688U,  // ADDCCrr
45
29.5k
    5925U,  // ADDCri
46
29.5k
    5925U,  // ADDCrr
47
29.5k
    4772U,  // ADDEri
48
29.5k
    4772U,  // ADDErr
49
29.5k
    4786U,  // ADDXC
50
29.5k
    4678U,  // ADDXCCC
51
29.5k
    4808U,  // ADDXri
52
29.5k
    4808U,  // ADDXrr
53
29.5k
    4808U,  // ADDri
54
29.5k
    4808U,  // ADDrr
55
29.5k
    74166U, // ADJCALLSTACKDOWN
56
29.5k
    74185U, // ADJCALLSTACKUP
57
29.5k
    5497U,  // ALIGNADDR
58
29.5k
    5127U,  // ALIGNADDRL
59
29.5k
    4695U,  // ANDCCri
60
29.5k
    4695U,  // ANDCCrr
61
29.5k
    4718U,  // ANDNCCri
62
29.5k
    4718U,  // ANDNCCrr
63
29.5k
    5182U,  // ANDNri
64
29.5k
    5182U,  // ANDNrr
65
29.5k
    5182U,  // ANDXNrr
66
29.5k
    4876U,  // ANDXri
67
29.5k
    4876U,  // ANDXrr
68
29.5k
    4876U,  // ANDri
69
29.5k
    4876U,  // ANDrr
70
29.5k
    4502U,  // ARRAY16
71
29.5k
    4255U,  // ARRAY32
72
29.5k
    4526U,  // ARRAY8
73
29.5k
    0U, // ATOMIC_LOAD_ADD_32
74
29.5k
    0U, // ATOMIC_LOAD_ADD_64
75
29.5k
    0U, // ATOMIC_LOAD_AND_32
76
29.5k
    0U, // ATOMIC_LOAD_AND_64
77
29.5k
    0U, // ATOMIC_LOAD_MAX_32
78
29.5k
    0U, // ATOMIC_LOAD_MAX_64
79
29.5k
    0U, // ATOMIC_LOAD_MIN_32
80
29.5k
    0U, // ATOMIC_LOAD_MIN_64
81
29.5k
    0U, // ATOMIC_LOAD_NAND_32
82
29.5k
    0U, // ATOMIC_LOAD_NAND_64
83
29.5k
    0U, // ATOMIC_LOAD_OR_32
84
29.5k
    0U, // ATOMIC_LOAD_OR_64
85
29.5k
    0U, // ATOMIC_LOAD_SUB_32
86
29.5k
    0U, // ATOMIC_LOAD_SUB_64
87
29.5k
    0U, // ATOMIC_LOAD_UMAX_32
88
29.5k
    0U, // ATOMIC_LOAD_UMAX_64
89
29.5k
    0U, // ATOMIC_LOAD_UMIN_32
90
29.5k
    0U, // ATOMIC_LOAD_UMIN_64
91
29.5k
    0U, // ATOMIC_LOAD_XOR_32
92
29.5k
    0U, // ATOMIC_LOAD_XOR_64
93
29.5k
    0U, // ATOMIC_SWAP_64
94
29.5k
    74271U, // BA
95
29.5k
    1194492U, // BCOND
96
29.5k
    1260028U, // BCONDA
97
29.5k
    17659U, // BINDri
98
29.5k
    17659U, // BINDrr
99
29.5k
    5065U,  // BMASK
100
29.5k
    145915U,  // BPFCC
101
29.5k
    211451U,  // BPFCCA
102
29.5k
    276987U,  // BPFCCANT
103
29.5k
    342523U,  // BPFCCNT
104
29.5k
    2106465U, // BPGEZapn
105
29.5k
    2105838U, // BPGEZapt
106
29.5k
    2106532U, // BPGEZnapn
107
29.5k
    2107288U, // BPGEZnapt
108
29.5k
    2106489U, // BPGZapn
109
29.5k
    2105856U, // BPGZapt
110
29.5k
    2106552U, // BPGZnapn
111
29.5k
    2107384U, // BPGZnapt
112
29.5k
    1456636U, // BPICC
113
29.5k
    473596U,  // BPICCA
114
29.5k
    539132U,  // BPICCANT
115
29.5k
    604668U,  // BPICCNT
116
29.5k
    2106477U, // BPLEZapn
117
29.5k
    2105847U, // BPLEZapt
118
29.5k
    2106542U, // BPLEZnapn
119
29.5k
    2107337U, // BPLEZnapt
120
29.5k
    2106500U, // BPLZapn
121
29.5k
    2105864U, // BPLZapt
122
29.5k
    2106561U, // BPLZnapn
123
29.5k
    2107428U, // BPLZnapt
124
29.5k
    2106511U, // BPNZapn
125
29.5k
    2105872U, // BPNZapt
126
29.5k
    2106570U, // BPNZnapn
127
29.5k
    2107472U, // BPNZnapt
128
29.5k
    1718780U, // BPXCC
129
29.5k
    735740U,  // BPXCCA
130
29.5k
    801276U,  // BPXCCANT
131
29.5k
    866812U,  // BPXCCNT
132
29.5k
    2106522U, // BPZapn
133
29.5k
    2105880U, // BPZapt
134
29.5k
    2106579U, // BPZnapn
135
29.5k
    2107505U, // BPZnapt
136
29.5k
    4983U,  // BSHUFFLE
137
29.5k
    74742U, // CALL
138
29.5k
    17398U, // CALLri
139
29.5k
    17398U, // CALLrr
140
29.5k
    924148U,  // CASXrr
141
29.5k
    924129U,  // CASrr
142
29.5k
    74001U, // CMASK16
143
29.5k
    73833U, // CMASK32
144
29.5k
    74150U, // CMASK8
145
29.5k
    2106607U, // CMPri
146
29.5k
    2106607U, // CMPrr
147
29.5k
    4332U,  // EDGE16
148
29.5k
    5081U,  // EDGE16L
149
29.5k
    5198U,  // EDGE16LN
150
29.5k
    5165U,  // EDGE16N
151
29.5k
    4164U,  // EDGE32
152
29.5k
    5072U,  // EDGE32L
153
29.5k
    5188U,  // EDGE32LN
154
29.5k
    5156U,  // EDGE32N
155
29.5k
    4511U,  // EDGE8
156
29.5k
    5090U,  // EDGE8L
157
29.5k
    5208U,  // EDGE8LN
158
29.5k
    5174U,  // EDGE8N
159
29.5k
    1053516U, // FABSD
160
29.5k
    1054031U, // FABSQ
161
29.5k
    1054376U, // FABSS
162
29.5k
    4813U,  // FADDD
163
29.5k
    5383U,  // FADDQ
164
29.5k
    5645U,  // FADDS
165
29.5k
    4648U,  // FALIGNADATA
166
29.5k
    4875U,  // FAND
167
29.5k
    4112U,  // FANDNOT1
168
29.5k
    5544U,  // FANDNOT1S
169
29.5k
    4271U,  // FANDNOT2
170
29.5k
    5591U,  // FANDNOT2S
171
29.5k
    5677U,  // FANDS
172
29.5k
    1194491U, // FBCOND
173
29.5k
    1260027U, // FBCONDA
174
29.5k
    4394U,  // FCHKSM16
175
29.5k
    2106173U, // FCMPD
176
29.5k
    4413U,  // FCMPEQ16
177
29.5k
    4226U,  // FCMPEQ32
178
29.5k
    4432U,  // FCMPGT16
179
29.5k
    4245U,  // FCMPGT32
180
29.5k
    4340U,  // FCMPLE16
181
29.5k
    4172U,  // FCMPLE32
182
29.5k
    4350U,  // FCMPNE16
183
29.5k
    4182U,  // FCMPNE32
184
29.5k
    2106696U, // FCMPQ
185
29.5k
    2107005U, // FCMPS
186
29.5k
    4960U,  // FDIVD
187
29.5k
    5475U,  // FDIVQ
188
29.5k
    5815U,  // FDIVS
189
29.5k
    5405U,  // FDMULQ
190
29.5k
    1053620U, // FDTOI
191
29.5k
    1053996U, // FDTOQ
192
29.5k
    1054305U, // FDTOS
193
29.5k
    1054536U, // FDTOX
194
29.5k
    1053464U, // FEXPAND
195
29.5k
    4820U,  // FHADDD
196
29.5k
    5652U,  // FHADDS
197
29.5k
    4800U,  // FHSUBD
198
29.5k
    5637U,  // FHSUBS
199
29.5k
    1053473U, // FITOD
200
29.5k
    1054003U, // FITOQ
201
29.5k
    1054312U, // FITOS
202
29.5k
    6300484U, // FLCMPD
203
29.5k
    6301316U, // FLCMPS
204
29.5k
    2606U,  // FLUSHW
205
29.5k
    4404U,  // FMEAN16
206
29.5k
    1053543U, // FMOVD
207
29.5k
    1006078U, // FMOVD_FCC
208
29.5k
    23484926U,  // FMOVD_ICC
209
29.5k
    23747070U,  // FMOVD_XCC
210
29.5k
    1054058U, // FMOVQ
211
29.5k
    1006102U, // FMOVQ_FCC
212
29.5k
    23484950U,  // FMOVQ_ICC
213
29.5k
    23747094U,  // FMOVQ_XCC
214
29.5k
    6018U,  // FMOVRGEZD
215
29.5k
    6029U,  // FMOVRGEZQ
216
29.5k
    6056U,  // FMOVRGEZS
217
29.5k
    6116U,  // FMOVRGZD
218
29.5k
    6126U,  // FMOVRGZQ
219
29.5k
    6150U,  // FMOVRGZS
220
29.5k
    6067U,  // FMOVRLEZD
221
29.5k
    6078U,  // FMOVRLEZQ
222
29.5k
    6105U,  // FMOVRLEZS
223
29.5k
    6160U,  // FMOVRLZD
224
29.5k
    6170U,  // FMOVRLZQ
225
29.5k
    6194U,  // FMOVRLZS
226
29.5k
    6204U,  // FMOVRNZD
227
29.5k
    6214U,  // FMOVRNZQ
228
29.5k
    6238U,  // FMOVRNZS
229
29.5k
    6009U,  // FMOVRZD
230
29.5k
    6248U,  // FMOVRZQ
231
29.5k
    6269U,  // FMOVRZS
232
29.5k
    1054398U, // FMOVS
233
29.5k
    1006114U, // FMOVS_FCC
234
29.5k
    23484962U,  // FMOVS_ICC
235
29.5k
    23747106U,  // FMOVS_XCC
236
29.5k
    4490U,  // FMUL8SUX16
237
29.5k
    4465U,  // FMUL8ULX16
238
29.5k
    4442U,  // FMUL8X16
239
29.5k
    5098U,  // FMUL8X16AL
240
29.5k
    5849U,  // FMUL8X16AU
241
29.5k
    4860U,  // FMULD
242
29.5k
    4477U,  // FMULD8SUX16
243
29.5k
    4452U,  // FMULD8ULX16
244
29.5k
    5413U,  // FMULQ
245
29.5k
    5714U,  // FMULS
246
29.5k
    4837U,  // FNADDD
247
29.5k
    5669U,  // FNADDS
248
29.5k
    4881U,  // FNAND
249
29.5k
    5684U,  // FNANDS
250
29.5k
    1053429U, // FNEGD
251
29.5k
    1053974U, // FNEGQ
252
29.5k
    1054283U, // FNEGS
253
29.5k
    4828U,  // FNHADDD
254
29.5k
    5660U,  // FNHADDS
255
29.5k
    4828U,  // FNMULD
256
29.5k
    5660U,  // FNMULS
257
29.5k
    5513U,  // FNOR
258
29.5k
    5778U,  // FNORS
259
29.5k
    1052698U, // FNOT1
260
29.5k
    1054131U, // FNOT1S
261
29.5k
    1052857U, // FNOT2
262
29.5k
    1054178U, // FNOT2S
263
29.5k
    5660U,  // FNSMULD
264
29.5k
    74625U, // FONE
265
29.5k
    75324U, // FONES
266
29.5k
    5508U,  // FOR
267
29.5k
    4129U,  // FORNOT1
268
29.5k
    5563U,  // FORNOT1S
269
29.5k
    4288U,  // FORNOT2
270
29.5k
    5610U,  // FORNOT2S
271
29.5k
    5772U,  // FORS
272
29.5k
    1052936U, // FPACK16
273
29.5k
    4192U,  // FPACK32
274
29.5k
    1054507U, // FPACKFIX
275
29.5k
    4323U,  // FPADD16
276
29.5k
    5620U,  // FPADD16S
277
29.5k
    4155U,  // FPADD32
278
29.5k
    5573U,  // FPADD32S
279
29.5k
    4297U,  // FPADD64
280
29.5k
    4974U,  // FPMERGE
281
29.5k
    4314U,  // FPSUB16
282
29.5k
    4580U,  // FPSUB16S
283
29.5k
    4146U,  // FPSUB32
284
29.5k
    4570U,  // FPSUB32S
285
29.5k
    1053480U, // FQTOD
286
29.5k
    1053627U, // FQTOI
287
29.5k
    1054319U, // FQTOS
288
29.5k
    1054552U, // FQTOX
289
29.5k
    4423U,  // FSLAS16
290
29.5k
    4236U,  // FSLAS32
291
29.5k
    4378U,  // FSLL16
292
29.5k
    4210U,  // FSLL32
293
29.5k
    4867U,  // FSMULD
294
29.5k
    1053523U, // FSQRTD
295
29.5k
    1054038U, // FSQRTQ
296
29.5k
    1054383U, // FSQRTS
297
29.5k
    4306U,  // FSRA16
298
29.5k
    4138U,  // FSRA32
299
29.5k
    1052681U, // FSRC1
300
29.5k
    1054112U, // FSRC1S
301
29.5k
    1052840U, // FSRC2
302
29.5k
    1054159U, // FSRC2S
303
29.5k
    4386U,  // FSRL16
304
29.5k
    4218U,  // FSRL32
305
29.5k
    1053487U, // FSTOD
306
29.5k
    1053634U, // FSTOI
307
29.5k
    1054010U, // FSTOQ
308
29.5k
    1054559U, // FSTOX
309
29.5k
    4793U,  // FSUBD
310
29.5k
    5376U,  // FSUBQ
311
29.5k
    5630U,  // FSUBS
312
29.5k
    5519U,  // FXNOR
313
29.5k
    5785U,  // FXNORS
314
29.5k
    5526U,  // FXOR
315
29.5k
    5793U,  // FXORS
316
29.5k
    1053494U, // FXTOD
317
29.5k
    1054017U, // FXTOQ
318
29.5k
    1054326U, // FXTOS
319
29.5k
    74984U, // FZERO
320
29.5k
    75353U, // FZEROS
321
29.5k
    24584U, // GETPCX
322
29.5k
    1078273U, // JMPLri
323
29.5k
    1078273U, // JMPLrr
324
29.5k
    1997243U, // LDDFri
325
29.5k
    1997243U, // LDDFrr
326
29.5k
    1997249U, // LDFri
327
29.5k
    1997249U, // LDFrr
328
29.5k
    1997275U, // LDQFri
329
29.5k
    1997275U, // LDQFrr
330
29.5k
    1997229U, // LDSBri
331
29.5k
    1997229U, // LDSBrr
332
29.5k
    1997254U, // LDSHri
333
29.5k
    1997254U, // LDSHrr
334
29.5k
    1997287U, // LDSWri
335
29.5k
    1997287U, // LDSWrr
336
29.5k
    1997236U, // LDUBri
337
29.5k
    1997236U, // LDUBrr
338
29.5k
    1997261U, // LDUHri
339
29.5k
    1997261U, // LDUHrr
340
29.5k
    1997294U, // LDXri
341
29.5k
    1997294U, // LDXrr
342
29.5k
    1997249U, // LDri
343
29.5k
    1997249U, // LDrr
344
29.5k
    33480U, // LEAX_ADDri
345
29.5k
    33480U, // LEA_ADDri
346
29.5k
    1054405U, // LZCNT
347
29.5k
    75121U, // MEMBARi
348
29.5k
    1054543U, // MOVDTOX
349
29.5k
    1006122U, // MOVFCCri
350
29.5k
    1006122U, // MOVFCCrr
351
29.5k
    23484970U,  // MOVICCri
352
29.5k
    23484970U,  // MOVICCrr
353
29.5k
    6047U,  // MOVRGEZri
354
29.5k
    6047U,  // MOVRGEZrr
355
29.5k
    6142U,  // MOVRGZri
356
29.5k
    6142U,  // MOVRGZrr
357
29.5k
    6096U,  // MOVRLEZri
358
29.5k
    6096U,  // MOVRLEZrr
359
29.5k
    6186U,  // MOVRLZri
360
29.5k
    6186U,  // MOVRLZrr
361
29.5k
    6230U,  // MOVRNZri
362
29.5k
    6230U,  // MOVRNZrr
363
29.5k
    6262U,  // MOVRRZri
364
29.5k
    6262U,  // MOVRRZrr
365
29.5k
    1054469U, // MOVSTOSW
366
29.5k
    1054479U, // MOVSTOUW
367
29.5k
    1054543U, // MOVWTOS
368
29.5k
    23747114U,  // MOVXCCri
369
29.5k
    23747114U,  // MOVXCCrr
370
29.5k
    1054543U, // MOVXTOD
371
29.5k
    5954U,  // MULXri
372
29.5k
    5954U,  // MULXrr
373
29.5k
    2578U,  // NOP
374
29.5k
    4735U,  // ORCCri
375
29.5k
    4735U,  // ORCCrr
376
29.5k
    4726U,  // ORNCCri
377
29.5k
    4726U,  // ORNCCrr
378
29.5k
    5339U,  // ORNri
379
29.5k
    5339U,  // ORNrr
380
29.5k
    5339U,  // ORXNrr
381
29.5k
    5509U,  // ORXri
382
29.5k
    5509U,  // ORXrr
383
29.5k
    5509U,  // ORri
384
29.5k
    5509U,  // ORrr
385
29.5k
    5836U,  // PDIST
386
29.5k
    5344U,  // PDISTN
387
29.5k
    1053356U, // POPCrr
388
29.5k
    73729U, // RDY
389
29.5k
    4999U,  // RESTOREri
390
29.5k
    4999U,  // RESTORErr
391
29.5k
    76132U, // RET
392
29.5k
    76141U, // RETL
393
29.5k
    18131U, // RETTri
394
29.5k
    18131U, // RETTrr
395
29.5k
    5008U,  // SAVEri
396
29.5k
    5008U,  // SAVErr
397
29.5k
    4748U,  // SDIVCCri
398
29.5k
    4748U,  // SDIVCCrr
399
29.5k
    5995U,  // SDIVXri
400
29.5k
    5995U,  // SDIVXrr
401
29.5k
    5861U,  // SDIVri
402
29.5k
    5861U,  // SDIVrr
403
29.5k
    2182U,  // SELECT_CC_DFP_FCC
404
29.5k
    2293U,  // SELECT_CC_DFP_ICC
405
29.5k
    2238U,  // SELECT_CC_FP_FCC
406
29.5k
    2349U,  // SELECT_CC_FP_ICC
407
29.5k
    2265U,  // SELECT_CC_Int_FCC
408
29.5k
    2376U,  // SELECT_CC_Int_ICC
409
29.5k
    2210U,  // SELECT_CC_QFP_FCC
410
29.5k
    2321U,  // SELECT_CC_QFP_ICC
411
29.5k
    1053595U, // SETHIXi
412
29.5k
    1053595U, // SETHIi
413
29.5k
    2569U,  // SHUTDOWN
414
29.5k
    2564U,  // SIAM
415
29.5k
    5941U,  // SLLXri
416
29.5k
    5941U,  // SLLXrr
417
29.5k
    5116U,  // SLLri
418
29.5k
    5116U,  // SLLrr
419
29.5k
    4702U,  // SMULCCri
420
29.5k
    4702U,  // SMULCCrr
421
29.5k
    5144U,  // SMULri
422
29.5k
    5144U,  // SMULrr
423
29.5k
    5913U,  // SRAXri
424
29.5k
    5913U,  // SRAXrr
425
29.5k
    4643U,  // SRAri
426
29.5k
    4643U,  // SRArr
427
29.5k
    5947U,  // SRLXri
428
29.5k
    5947U,  // SRLXrr
429
29.5k
    5139U,  // SRLri
430
29.5k
    5139U,  // SRLrr
431
29.5k
    2588U,  // STBAR
432
29.5k
    37428U, // STBri
433
29.5k
    37428U, // STBrr
434
29.5k
    37723U, // STDFri
435
29.5k
    37723U, // STDFrr
436
29.5k
    38607U, // STFri
437
29.5k
    38607U, // STFrr
438
29.5k
    37782U, // STHri
439
29.5k
    37782U, // STHrr
440
29.5k
    38238U, // STQFri
441
29.5k
    38238U, // STQFrr
442
29.5k
    38758U, // STXri
443
29.5k
    38758U, // STXrr
444
29.5k
    38607U, // STri
445
29.5k
    38607U, // STrr
446
29.5k
    4671U,  // SUBCCri
447
29.5k
    4671U,  // SUBCCrr
448
29.5k
    5919U,  // SUBCri
449
29.5k
    5919U,  // SUBCrr
450
29.5k
    4764U,  // SUBEri
451
29.5k
    4764U,  // SUBErr
452
29.5k
    4665U,  // SUBXri
453
29.5k
    4665U,  // SUBXrr
454
29.5k
    4665U,  // SUBri
455
29.5k
    4665U,  // SUBrr
456
29.5k
    1997268U, // SWAPri
457
29.5k
    1997268U, // SWAPrr
458
29.5k
    2422U,  // TA3
459
29.5k
    2427U,  // TA5
460
29.5k
    5883U,  // TADDCCTVri
461
29.5k
    5883U,  // TADDCCTVrr
462
29.5k
    4687U,  // TADDCCri
463
29.5k
    4687U,  // TADDCCrr
464
29.5k
    9873960U, // TICCri
465
29.5k
    9873960U, // TICCrr
466
29.5k
    37753544U,  // TLS_ADDXrr
467
29.5k
    37753544U,  // TLS_ADDrr
468
29.5k
    2106358U, // TLS_CALL
469
29.5k
    39746030U,  // TLS_LDXrr
470
29.5k
    39745985U,  // TLS_LDrr
471
29.5k
    5873U,  // TSUBCCTVri
472
29.5k
    5873U,  // TSUBCCTVrr
473
29.5k
    4670U,  // TSUBCCri
474
29.5k
    4670U,  // TSUBCCrr
475
29.5k
    10136104U,  // TXCCri
476
29.5k
    10136104U,  // TXCCrr
477
29.5k
    4756U,  // UDIVCCri
478
29.5k
    4756U,  // UDIVCCrr
479
29.5k
    6002U,  // UDIVXri
480
29.5k
    6002U,  // UDIVXrr
481
29.5k
    5867U,  // UDIVri
482
29.5k
    5867U,  // UDIVrr
483
29.5k
    4710U,  // UMULCCri
484
29.5k
    4710U,  // UMULCCrr
485
29.5k
    5026U,  // UMULXHI
486
29.5k
    5150U,  // UMULri
487
29.5k
    5150U,  // UMULrr
488
29.5k
    74996U, // UNIMP
489
29.5k
    6300477U, // V9FCMPD
490
29.5k
    6300397U, // V9FCMPED
491
29.5k
    6300942U, // V9FCMPEQ
492
29.5k
    6301251U, // V9FCMPES
493
29.5k
    6301000U, // V9FCMPQ
494
29.5k
    6301309U, // V9FCMPS
495
29.5k
    47614U, // V9FMOVD_FCC
496
29.5k
    47638U, // V9FMOVQ_FCC
497
29.5k
    47650U, // V9FMOVS_FCC
498
29.5k
    47658U, // V9MOVFCCri
499
29.5k
    47658U, // V9MOVFCCrr
500
29.5k
    14689692U,  // WRYri
501
29.5k
    14689692U,  // WRYrr
502
29.5k
    5953U,  // XMULX
503
29.5k
    5035U,  // XMULXHI
504
29.5k
    4733U,  // XNORCCri
505
29.5k
    4733U,  // XNORCCrr
506
29.5k
    5520U,  // XNORXrr
507
29.5k
    5520U,  // XNORri
508
29.5k
    5520U,  // XNORrr
509
29.5k
    4741U,  // XORCCri
510
29.5k
    4741U,  // XORCCrr
511
29.5k
    5527U,  // XORXri
512
29.5k
    5527U,  // XORXrr
513
29.5k
    5527U,  // XORri
514
29.5k
    5527U,  // XORrr
515
29.5k
    0U
516
29.5k
  };
517
518
29.5k
#ifndef CAPSTONE_DIET
519
29.5k
  static const char AsmStrs[] = {
520
29.5k
  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521
29.5k
  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522
29.5k
  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523
29.5k
  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524
29.5k
  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525
29.5k
  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526
29.5k
  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527
29.5k
  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528
29.5k
  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529
29.5k
  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530
29.5k
  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531
29.5k
  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532
29.5k
  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533
29.5k
  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534
29.5k
  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535
29.5k
  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536
29.5k
  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537
29.5k
  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538
29.5k
  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539
29.5k
  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540
29.5k
  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541
29.5k
  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542
29.5k
  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543
29.5k
  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544
29.5k
  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545
29.5k
  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546
29.5k
  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547
29.5k
  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548
29.5k
  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549
29.5k
  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550
29.5k
  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551
29.5k
  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552
29.5k
  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553
29.5k
  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554
29.5k
  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555
29.5k
  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556
29.5k
  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557
29.5k
  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558
29.5k
  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559
29.5k
  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560
29.5k
  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561
29.5k
  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562
29.5k
  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563
29.5k
  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564
29.5k
  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565
29.5k
  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566
29.5k
  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567
29.5k
  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568
29.5k
  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569
29.5k
  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570
29.5k
  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571
29.5k
  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572
29.5k
  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573
29.5k
  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574
29.5k
  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575
29.5k
  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576
29.5k
  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577
29.5k
  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578
29.5k
  /* 542 */ 'b', 'a', 32, 0,
579
29.5k
  /* 546 */ 's', 'r', 'a', 32, 0,
580
29.5k
  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581
29.5k
  /* 563 */ 's', 't', 'b', 32, 0,
582
29.5k
  /* 568 */ 's', 'u', 'b', 32, 0,
583
29.5k
  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584
29.5k
  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585
29.5k
  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586
29.5k
  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587
29.5k
  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588
29.5k
  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589
29.5k
  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590
29.5k
  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591
29.5k
  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592
29.5k
  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593
29.5k
  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594
29.5k
  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595
29.5k
  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596
29.5k
  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597
29.5k
  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598
29.5k
  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599
29.5k
  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600
29.5k
  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601
29.5k
  /* 711 */ 'a', 'd', 'd', 32, 0,
602
29.5k
  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603
29.5k
  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604
29.5k
  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605
29.5k
  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606
29.5k
  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607
29.5k
  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608
29.5k
  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609
29.5k
  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610
29.5k
  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611
29.5k
  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612
29.5k
  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613
29.5k
  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614
29.5k
  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615
29.5k
  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616
29.5k
  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617
29.5k
  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618
29.5k
  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619
29.5k
  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620
29.5k
  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621
29.5k
  /* 858 */ 's', 't', 'd', 32, 0,
622
29.5k
  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623
29.5k
  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624
29.5k
  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625
29.5k
  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626
29.5k
  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627
29.5k
  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628
29.5k
  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629
29.5k
  /* 917 */ 's', 't', 'h', 32, 0,
630
29.5k
  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631
29.5k
  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632
29.5k
  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633
29.5k
  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634
29.5k
  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635
29.5k
  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636
29.5k
  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637
29.5k
  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638
29.5k
  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639
29.5k
  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640
29.5k
  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641
29.5k
  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642
29.5k
  /* 1019 */ 's', 'l', 'l', 32, 0,
643
29.5k
  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644
29.5k
  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645
29.5k
  /* 1042 */ 's', 'r', 'l', 32, 0,
646
29.5k
  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647
29.5k
  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648
29.5k
  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649
29.5k
  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650
29.5k
  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651
29.5k
  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652
29.5k
  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653
29.5k
  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654
29.5k
  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655
29.5k
  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656
29.5k
  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657
29.5k
  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658
29.5k
  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659
29.5k
  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660
29.5k
  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661
29.5k
  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662
29.5k
  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663
29.5k
  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664
29.5k
  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665
29.5k
  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666
29.5k
  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667
29.5k
  /* 1242 */ 'o', 'r', 'n', 32, 0,
668
29.5k
  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669
29.5k
  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670
29.5k
  /* 1262 */ 'c', 'm', 'p', 32, 0,
671
29.5k
  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672
29.5k
  /* 1274 */ 'j', 'm', 'p', 32, 0,
673
29.5k
  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674
29.5k
  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675
29.5k
  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676
29.5k
  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677
29.5k
  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678
29.5k
  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679
29.5k
  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680
29.5k
  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681
29.5k
  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682
29.5k
  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683
29.5k
  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684
29.5k
  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685
29.5k
  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686
29.5k
  /* 1373 */ 's', 't', 'q', 32, 0,
687
29.5k
  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688
29.5k
  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689
29.5k
  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690
29.5k
  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691
29.5k
  /* 1411 */ 'f', 'o', 'r', 32, 0,
692
29.5k
  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693
29.5k
  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694
29.5k
  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695
29.5k
  /* 1435 */ 'w', 'r', 32, 0,
696
29.5k
  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697
29.5k
  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698
29.5k
  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699
29.5k
  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700
29.5k
  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701
29.5k
  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702
29.5k
  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703
29.5k
  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704
29.5k
  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705
29.5k
  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706
29.5k
  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707
29.5k
  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708
29.5k
  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709
29.5k
  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710
29.5k
  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711
29.5k
  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712
29.5k
  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713
29.5k
  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714
29.5k
  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715
29.5k
  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716
29.5k
  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717
29.5k
  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718
29.5k
  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719
29.5k
  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720
29.5k
  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721
29.5k
  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722
29.5k
  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723
29.5k
  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724
29.5k
  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725
29.5k
  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726
29.5k
  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727
29.5k
  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728
29.5k
  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729
29.5k
  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730
29.5k
  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731
29.5k
  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732
29.5k
  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733
29.5k
  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734
29.5k
  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735
29.5k
  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736
29.5k
  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737
29.5k
  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738
29.5k
  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739
29.5k
  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740
29.5k
  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741
29.5k
  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742
29.5k
  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743
29.5k
  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744
29.5k
  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745
29.5k
  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746
29.5k
  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747
29.5k
  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748
29.5k
  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749
29.5k
  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750
29.5k
  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751
29.5k
  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752
29.5k
  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753
29.5k
  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754
29.5k
  /* 1893 */ 's', 't', 'x', 32, 0,
755
29.5k
  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756
29.5k
  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757
29.5k
  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758
29.5k
  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759
29.5k
  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760
29.5k
  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761
29.5k
  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762
29.5k
  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763
29.5k
  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764
29.5k
  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765
29.5k
  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766
29.5k
  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767
29.5k
  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768
29.5k
  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769
29.5k
  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770
29.5k
  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771
29.5k
  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772
29.5k
  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773
29.5k
  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774
29.5k
  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775
29.5k
  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776
29.5k
  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777
29.5k
  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778
29.5k
  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779
29.5k
  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780
29.5k
  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781
29.5k
  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782
29.5k
  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783
29.5k
  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784
29.5k
  /* 2160 */ 'b', 'r', 'z', 32, 0,
785
29.5k
  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786
29.5k
  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787
29.5k
  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788
29.5k
  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789
29.5k
  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790
29.5k
  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791
29.5k
  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792
29.5k
  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793
29.5k
  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794
29.5k
  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795
29.5k
  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796
29.5k
  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797
29.5k
  /* 2421 */ 't', 'a', 32, '3', 0,
798
29.5k
  /* 2426 */ 't', 'a', 32, '5', 0,
799
29.5k
  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800
29.5k
  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801
29.5k
  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802
29.5k
  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803
29.5k
  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804
29.5k
  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805
29.5k
  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806
29.5k
  /* 2496 */ 'l', 'd', 32, '[', 0,
807
29.5k
  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808
29.5k
  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809
29.5k
  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810
29.5k
  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811
29.5k
  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812
29.5k
  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813
29.5k
  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814
29.5k
  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815
29.5k
  /* 2554 */ 'f', 'b', 0,
816
29.5k
  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817
29.5k
  /* 2563 */ 's', 'i', 'a', 'm', 0,
818
29.5k
  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819
29.5k
  /* 2577 */ 'n', 'o', 'p', 0,
820
29.5k
  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821
29.5k
  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822
29.5k
  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823
29.5k
  /* 2599 */ 't', 0,
824
29.5k
  /* 2601 */ 'm', 'o', 'v', 0,
825
29.5k
  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826
29.5k
  };
827
29.5k
#endif
828
829
  // Emit the opcode for the instruction.
830
29.5k
  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831
29.5k
#ifndef CAPSTONE_DIET
832
  // assert(Bits != 0 && "Cannot print this instruction.");
833
29.5k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834
29.5k
#endif
835
836
837
  // Fragment 0 encoded into 4 bits for 12 unique commands.
838
  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839
29.5k
  switch ((Bits >> 12) & 15) {
840
0
  default:   // unreachable.
841
53
  case 0:
842
    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843
53
    return;
844
0
    break;
845
5.90k
  case 1:
846
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847
5.90k
    printOperand(MI, 1, O); 
848
5.90k
    break;
849
17.9k
  case 2:
850
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851
17.9k
    printOperand(MI, 0, O); 
852
17.9k
    break;
853
1.99k
  case 3:
854
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855
1.99k
    printCCOperand(MI, 1, O); 
856
1.99k
    break;
857
147
  case 4:
858
    // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859
147
    printMemOperand(MI, 0, O, NULL); 
860
147
    return;
861
0
    break;
862
507
  case 5:
863
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864
507
    printCCOperand(MI, 3, O); 
865
507
    break;
866
0
  case 6:
867
    // GETPCX
868
0
    printGetPCX(MI, 0, O); 
869
0
    return;
870
0
    break;
871
1.34k
  case 7:
872
    // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873
1.34k
    printMemOperand(MI, 1, O, NULL); 
874
1.34k
    break;
875
0
  case 8:
876
    // LEAX_ADDri, LEA_ADDri
877
0
    printMemOperand(MI, 1, O, "arith"); 
878
0
    SStream_concat0(O, ", "); 
879
0
    printOperand(MI, 0, O); 
880
0
    return;
881
0
    break;
882
814
  case 9:
883
    // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884
814
    printOperand(MI, 2, O); 
885
814
    SStream_concat0(O, ", ["); 
886
814
    printMemOperand(MI, 0, O, NULL); 
887
814
    SStream_concat0(O, "]"); 
888
814
    return;
889
0
    break;
890
64
  case 10:
891
    // TICCri, TICCrr, TXCCri, TXCCrr
892
64
    printCCOperand(MI, 2, O); 
893
64
    break;
894
702
  case 11:
895
    // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896
702
    printCCOperand(MI, 4, O); 
897
702
    SStream_concat0(O, " "); 
898
702
    printOperand(MI, 1, O); 
899
702
    SStream_concat0(O, ", "); 
900
702
    printOperand(MI, 2, O); 
901
702
    SStream_concat0(O, ", "); 
902
702
    printOperand(MI, 0, O); 
903
702
    return;
904
0
    break;
905
29.5k
  }
906
907
908
  // Fragment 1 encoded into 4 bits for 16 unique commands.
909
  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910
27.8k
  switch ((Bits >> 16) & 15) {
911
0
  default:   // unreachable.
912
8.87k
  case 0:
913
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914
8.87k
    SStream_concat0(O, ", "); 
915
8.87k
    break;
916
15.0k
  case 1:
917
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918
15.0k
    return;
919
0
    break;
920
453
  case 2:
921
    // BCOND, BPFCC, FBCOND
922
453
    SStream_concat0(O, " "); 
923
453
    break;
924
906
  case 3:
925
    // BCONDA, BPFCCA, FBCONDA
926
906
    SStream_concat0(O, ",a ");
927
906
  Sparc_add_hint(MI, SPARC_HINT_A);
928
906
    break;
929
0
  case 4:
930
    // BPFCCANT
931
0
    SStream_concat0(O, ",a,pn ");
932
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933
0
    printOperand(MI, 2, O); 
934
0
    SStream_concat0(O, ", "); 
935
0
    printOperand(MI, 0, O); 
936
0
    return;
937
0
    break;
938
0
  case 5:
939
    // BPFCCNT
940
0
    SStream_concat0(O, ",pn ");
941
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
942
0
    printOperand(MI, 2, O); 
943
0
    SStream_concat0(O, ", "); 
944
0
    printOperand(MI, 0, O); 
945
0
    return;
946
0
    break;
947
423
  case 6:
948
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949
423
    SStream_concat0(O, " %icc, ");
950
423
  Sparc_add_reg(MI, SPARC_REG_ICC);
951
423
    break;
952
94
  case 7:
953
    // BPICCA
954
94
    SStream_concat0(O, ",a %icc, ");
955
94
  Sparc_add_hint(MI, SPARC_HINT_A);
956
94
  Sparc_add_reg(MI, SPARC_REG_ICC);
957
94
    printOperand(MI, 0, O); 
958
94
    return;
959
0
    break;
960
0
  case 8:
961
    // BPICCANT
962
0
    SStream_concat0(O, ",a,pn %icc, ");
963
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
965
0
    printOperand(MI, 0, O); 
966
0
    return;
967
0
    break;
968
0
  case 9:
969
    // BPICCNT
970
0
    SStream_concat0(O, ",pn %icc, ");
971
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
972
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
973
0
    printOperand(MI, 0, O); 
974
0
    return;
975
0
    break;
976
397
  case 10:
977
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978
397
    SStream_concat0(O, " %xcc, ");
979
397
  Sparc_add_reg(MI, SPARC_REG_XCC);
980
397
    break;
981
98
  case 11:
982
    // BPXCCA
983
98
    SStream_concat0(O, ",a %xcc, ");
984
98
  Sparc_add_hint(MI, SPARC_HINT_A);
985
98
  Sparc_add_reg(MI, SPARC_REG_XCC);
986
98
    printOperand(MI, 0, O); 
987
98
    return;
988
0
    break;
989
0
  case 12:
990
    // BPXCCANT
991
0
    SStream_concat0(O, ",a,pn %xcc, ");
992
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
994
0
    printOperand(MI, 0, O); 
995
0
    return;
996
0
    break;
997
0
  case 13:
998
    // BPXCCNT
999
0
    SStream_concat0(O, ",pn %xcc, ");
1000
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
1001
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
1002
0
    printOperand(MI, 0, O); 
1003
0
    return;
1004
0
    break;
1005
1.35k
  case 14:
1006
    // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007
1.35k
    SStream_concat0(O, "], "); 
1008
1.35k
    break;
1009
198
  case 15:
1010
    // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011
198
    SStream_concat0(O, " %fcc0, ");
1012
198
  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013
198
    printOperand(MI, 1, O); 
1014
198
    SStream_concat0(O, ", "); 
1015
198
    printOperand(MI, 0, O); 
1016
198
    return;
1017
0
    break;
1018
27.8k
  }
1019
1020
1021
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022
  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023
12.4k
  switch ((Bits >> 20) & 3) {
1024
0
  default:   // unreachable.
1025
3.75k
  case 0:
1026
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027
3.75k
    printOperand(MI, 2, O); 
1028
3.75k
    SStream_concat0(O, ", "); 
1029
3.75k
    printOperand(MI, 0, O); 
1030
3.75k
    break;
1031
5.36k
  case 1:
1032
    // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033
5.36k
    printOperand(MI, 0, O); 
1034
5.36k
    break;
1035
3.29k
  case 2:
1036
    // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037
3.29k
    printOperand(MI, 1, O); 
1038
3.29k
    break;
1039
12.4k
  }
1040
1041
1042
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043
  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044
12.4k
  switch ((Bits >> 22) & 3) {
1045
0
  default:   // unreachable.
1046
11.2k
  case 0:
1047
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048
11.2k
    return;
1049
0
    break;
1050
1.02k
  case 1:
1051
    // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052
1.02k
    SStream_concat0(O, ", "); 
1053
1.02k
    break;
1054
64
  case 2:
1055
    // TICCri, TICCrr, TXCCri, TXCCrr
1056
64
    SStream_concat0(O, " + ");  // qq
1057
64
    printOperand(MI, 1, O); 
1058
64
    return;
1059
0
    break;
1060
27
  case 3:
1061
    // WRYri, WRYrr
1062
27
    SStream_concat0(O, ", %y");
1063
27
  Sparc_add_reg(MI, SPARC_REG_Y);
1064
27
    return;
1065
0
    break;
1066
12.4k
  }
1067
1068
1069
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070
  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071
1.02k
  switch ((Bits >> 24) & 3) {
1072
0
  default:   // unreachable.
1073
712
  case 0:
1074
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075
712
    printOperand(MI, 2, O); 
1076
712
    return;
1077
0
    break;
1078
309
  case 1:
1079
    // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080
309
    printOperand(MI, 0, O); 
1081
309
    return;
1082
0
    break;
1083
0
  case 2:
1084
    // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085
0
    printOperand(MI, 3, O); 
1086
0
    return;
1087
0
    break;
1088
1.02k
  }
1089
1.02k
}
1090
1091
1092
/// getRegisterName - This method is automatically generated by tblgen
1093
/// from the register set description.  This returns the assembler name
1094
/// for the specified register.
1095
static const char *getRegisterName(unsigned RegNo)
1096
33.4k
{
1097
  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098
1099
33.4k
#ifndef CAPSTONE_DIET
1100
33.4k
  static const char AsmStrs[] = {
1101
33.4k
  /* 0 */ 'f', '1', '0', 0,
1102
33.4k
  /* 4 */ 'f', '2', '0', 0,
1103
33.4k
  /* 8 */ 'f', '3', '0', 0,
1104
33.4k
  /* 12 */ 'f', '4', '0', 0,
1105
33.4k
  /* 16 */ 'f', '5', '0', 0,
1106
33.4k
  /* 20 */ 'f', '6', '0', 0,
1107
33.4k
  /* 24 */ 'f', 'c', 'c', '0', 0,
1108
33.4k
  /* 29 */ 'f', '0', 0,
1109
33.4k
  /* 32 */ 'g', '0', 0,
1110
33.4k
  /* 35 */ 'i', '0', 0,
1111
33.4k
  /* 38 */ 'l', '0', 0,
1112
33.4k
  /* 41 */ 'o', '0', 0,
1113
33.4k
  /* 44 */ 'f', '1', '1', 0,
1114
33.4k
  /* 48 */ 'f', '2', '1', 0,
1115
33.4k
  /* 52 */ 'f', '3', '1', 0,
1116
33.4k
  /* 56 */ 'f', 'c', 'c', '1', 0,
1117
33.4k
  /* 61 */ 'f', '1', 0,
1118
33.4k
  /* 64 */ 'g', '1', 0,
1119
33.4k
  /* 67 */ 'i', '1', 0,
1120
33.4k
  /* 70 */ 'l', '1', 0,
1121
33.4k
  /* 73 */ 'o', '1', 0,
1122
33.4k
  /* 76 */ 'f', '1', '2', 0,
1123
33.4k
  /* 80 */ 'f', '2', '2', 0,
1124
33.4k
  /* 84 */ 'f', '3', '2', 0,
1125
33.4k
  /* 88 */ 'f', '4', '2', 0,
1126
33.4k
  /* 92 */ 'f', '5', '2', 0,
1127
33.4k
  /* 96 */ 'f', '6', '2', 0,
1128
33.4k
  /* 100 */ 'f', 'c', 'c', '2', 0,
1129
33.4k
  /* 105 */ 'f', '2', 0,
1130
33.4k
  /* 108 */ 'g', '2', 0,
1131
33.4k
  /* 111 */ 'i', '2', 0,
1132
33.4k
  /* 114 */ 'l', '2', 0,
1133
33.4k
  /* 117 */ 'o', '2', 0,
1134
33.4k
  /* 120 */ 'f', '1', '3', 0,
1135
33.4k
  /* 124 */ 'f', '2', '3', 0,
1136
33.4k
  /* 128 */ 'f', 'c', 'c', '3', 0,
1137
33.4k
  /* 133 */ 'f', '3', 0,
1138
33.4k
  /* 136 */ 'g', '3', 0,
1139
33.4k
  /* 139 */ 'i', '3', 0,
1140
33.4k
  /* 142 */ 'l', '3', 0,
1141
33.4k
  /* 145 */ 'o', '3', 0,
1142
33.4k
  /* 148 */ 'f', '1', '4', 0,
1143
33.4k
  /* 152 */ 'f', '2', '4', 0,
1144
33.4k
  /* 156 */ 'f', '3', '4', 0,
1145
33.4k
  /* 160 */ 'f', '4', '4', 0,
1146
33.4k
  /* 164 */ 'f', '5', '4', 0,
1147
33.4k
  /* 168 */ 'f', '4', 0,
1148
33.4k
  /* 171 */ 'g', '4', 0,
1149
33.4k
  /* 174 */ 'i', '4', 0,
1150
33.4k
  /* 177 */ 'l', '4', 0,
1151
33.4k
  /* 180 */ 'o', '4', 0,
1152
33.4k
  /* 183 */ 'f', '1', '5', 0,
1153
33.4k
  /* 187 */ 'f', '2', '5', 0,
1154
33.4k
  /* 191 */ 'f', '5', 0,
1155
33.4k
  /* 194 */ 'g', '5', 0,
1156
33.4k
  /* 197 */ 'i', '5', 0,
1157
33.4k
  /* 200 */ 'l', '5', 0,
1158
33.4k
  /* 203 */ 'o', '5', 0,
1159
33.4k
  /* 206 */ 'f', '1', '6', 0,
1160
33.4k
  /* 210 */ 'f', '2', '6', 0,
1161
33.4k
  /* 214 */ 'f', '3', '6', 0,
1162
33.4k
  /* 218 */ 'f', '4', '6', 0,
1163
33.4k
  /* 222 */ 'f', '5', '6', 0,
1164
33.4k
  /* 226 */ 'f', '6', 0,
1165
33.4k
  /* 229 */ 'g', '6', 0,
1166
33.4k
  /* 232 */ 'l', '6', 0,
1167
33.4k
  /* 235 */ 'f', '1', '7', 0,
1168
33.4k
  /* 239 */ 'f', '2', '7', 0,
1169
33.4k
  /* 243 */ 'f', '7', 0,
1170
33.4k
  /* 246 */ 'g', '7', 0,
1171
33.4k
  /* 249 */ 'i', '7', 0,
1172
33.4k
  /* 252 */ 'l', '7', 0,
1173
33.4k
  /* 255 */ 'o', '7', 0,
1174
33.4k
  /* 258 */ 'f', '1', '8', 0,
1175
33.4k
  /* 262 */ 'f', '2', '8', 0,
1176
33.4k
  /* 266 */ 'f', '3', '8', 0,
1177
33.4k
  /* 270 */ 'f', '4', '8', 0,
1178
33.4k
  /* 274 */ 'f', '5', '8', 0,
1179
33.4k
  /* 278 */ 'f', '8', 0,
1180
33.4k
  /* 281 */ 'f', '1', '9', 0,
1181
33.4k
  /* 285 */ 'f', '2', '9', 0,
1182
33.4k
  /* 289 */ 'f', '9', 0,
1183
33.4k
  /* 292 */ 'i', 'c', 'c', 0,
1184
33.4k
  /* 296 */ 'f', 'p', 0,
1185
33.4k
  /* 299 */ 's', 'p', 0,
1186
33.4k
  /* 302 */ 'y', 0,
1187
33.4k
  };
1188
1189
33.4k
  static const uint16_t RegAsmOffset[] = {
1190
33.4k
    292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 
1191
33.4k
    152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 
1192
33.4k
    92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 
1193
33.4k
    278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 
1194
33.4k
    80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 
1195
33.4k
    32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 
1196
33.4k
    296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 
1197
33.4k
    180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 
1198
33.4k
    12, 160, 270, 92, 222, 20, 
1199
33.4k
  };
1200
1201
  //int i;
1202
  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203
  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204
  //printf("*************************\n");
1205
33.4k
  return AsmStrs+RegAsmOffset[RegNo-1];
1206
#else
1207
  return NULL;
1208
#endif
1209
33.4k
}
1210
1211
#ifdef PRINT_ALIAS_INSTR
1212
#undef PRINT_ALIAS_INSTR
1213
1214
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1215
  unsigned PrintMethodIdx, SStream *OS)
1216
0
{
1217
0
}
1218
1219
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1220
47.7k
{
1221
186k
  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1222
47.7k
  const char *AsmString;
1223
47.7k
  char *tmp, *AsmMnem, *AsmOps, *c;
1224
47.7k
  int OpIdx, PrintMethodIdx;
1225
47.7k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1226
47.7k
  switch (MCInst_getOpcode(MI)) {
1227
27.9k
  default: return NULL;
1228
2.42k
  case SP_BCOND:
1229
2.42k
    if (MCInst_getNumOperands(MI) == 2 &&
1230
2.42k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1231
2.42k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1232
      // (BCOND brtarget:$imm, 8)
1233
0
      AsmString = "ba $\x01";
1234
0
      break;
1235
0
    }
1236
2.42k
    if (MCInst_getNumOperands(MI) == 2 &&
1237
2.42k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1238
2.42k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1239
      // (BCOND brtarget:$imm, 0)
1240
546
      AsmString = "bn $\x01";
1241
546
      break;
1242
546
    }
1243
1.87k
    if (MCInst_getNumOperands(MI) == 2 &&
1244
1.87k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1245
1.87k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1246
      // (BCOND brtarget:$imm, 9)
1247
25
      AsmString = "bne $\x01";
1248
25
      break;
1249
25
    }
1250
1.85k
    if (MCInst_getNumOperands(MI) == 2 &&
1251
1.85k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1252
1.85k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1253
      // (BCOND brtarget:$imm, 1)
1254
348
      AsmString = "be $\x01";
1255
348
      break;
1256
348
    }
1257
1.50k
    if (MCInst_getNumOperands(MI) == 2 &&
1258
1.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1259
1.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1260
      // (BCOND brtarget:$imm, 10)
1261
244
      AsmString = "bg $\x01";
1262
244
      break;
1263
244
    }
1264
1.26k
    if (MCInst_getNumOperands(MI) == 2 &&
1265
1.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1266
1.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1267
      // (BCOND brtarget:$imm, 2)
1268
416
      AsmString = "ble $\x01";
1269
416
      break;
1270
416
    }
1271
845
    if (MCInst_getNumOperands(MI) == 2 &&
1272
845
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1273
845
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1274
      // (BCOND brtarget:$imm, 11)
1275
42
      AsmString = "bge $\x01";
1276
42
      break;
1277
42
    }
1278
803
    if (MCInst_getNumOperands(MI) == 2 &&
1279
803
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1280
803
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1281
      // (BCOND brtarget:$imm, 3)
1282
28
      AsmString = "bl $\x01";
1283
28
      break;
1284
28
    }
1285
775
    if (MCInst_getNumOperands(MI) == 2 &&
1286
775
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1287
775
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1288
      // (BCOND brtarget:$imm, 12)
1289
64
      AsmString = "bgu $\x01";
1290
64
      break;
1291
64
    }
1292
711
    if (MCInst_getNumOperands(MI) == 2 &&
1293
711
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1294
711
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1295
      // (BCOND brtarget:$imm, 4)
1296
107
      AsmString = "bleu $\x01";
1297
107
      break;
1298
107
    }
1299
604
    if (MCInst_getNumOperands(MI) == 2 &&
1300
604
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1301
604
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1302
      // (BCOND brtarget:$imm, 13)
1303
21
      AsmString = "bcc $\x01";
1304
21
      break;
1305
21
    }
1306
583
    if (MCInst_getNumOperands(MI) == 2 &&
1307
583
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1308
583
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1309
      // (BCOND brtarget:$imm, 5)
1310
117
      AsmString = "bcs $\x01";
1311
117
      break;
1312
117
    }
1313
466
    if (MCInst_getNumOperands(MI) == 2 &&
1314
466
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1315
466
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1316
      // (BCOND brtarget:$imm, 14)
1317
33
      AsmString = "bpos $\x01";
1318
33
      break;
1319
33
    }
1320
433
    if (MCInst_getNumOperands(MI) == 2 &&
1321
433
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1322
433
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1323
      // (BCOND brtarget:$imm, 6)
1324
81
      AsmString = "bneg $\x01";
1325
81
      break;
1326
81
    }
1327
352
    if (MCInst_getNumOperands(MI) == 2 &&
1328
352
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1329
352
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1330
      // (BCOND brtarget:$imm, 15)
1331
280
      AsmString = "bvc $\x01";
1332
280
      break;
1333
280
    }
1334
72
    if (MCInst_getNumOperands(MI) == 2 &&
1335
72
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1336
72
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1337
      // (BCOND brtarget:$imm, 7)
1338
72
      AsmString = "bvs $\x01";
1339
72
      break;
1340
72
    }
1341
0
    return NULL;
1342
1.96k
  case SP_BCONDA:
1343
1.96k
    if (MCInst_getNumOperands(MI) == 2 &&
1344
1.96k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1345
1.96k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1346
      // (BCONDA brtarget:$imm, 8)
1347
241
      AsmString = "ba,a $\x01";
1348
241
      break;
1349
241
    }
1350
1.72k
    if (MCInst_getNumOperands(MI) == 2 &&
1351
1.72k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1352
1.72k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1353
      // (BCONDA brtarget:$imm, 0)
1354
100
      AsmString = "bn,a $\x01";
1355
100
      break;
1356
100
    }
1357
1.62k
    if (MCInst_getNumOperands(MI) == 2 &&
1358
1.62k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1359
1.62k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1360
      // (BCONDA brtarget:$imm, 9)
1361
95
      AsmString = "bne,a $\x01";
1362
95
      break;
1363
95
    }
1364
1.53k
    if (MCInst_getNumOperands(MI) == 2 &&
1365
1.53k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1366
1.53k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1367
      // (BCONDA brtarget:$imm, 1)
1368
84
      AsmString = "be,a $\x01";
1369
84
      break;
1370
84
    }
1371
1.44k
    if (MCInst_getNumOperands(MI) == 2 &&
1372
1.44k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1373
1.44k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1374
      // (BCONDA brtarget:$imm, 10)
1375
174
      AsmString = "bg,a $\x01";
1376
174
      break;
1377
174
    }
1378
1.27k
    if (MCInst_getNumOperands(MI) == 2 &&
1379
1.27k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1380
1.27k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1381
      // (BCONDA brtarget:$imm, 2)
1382
104
      AsmString = "ble,a $\x01";
1383
104
      break;
1384
104
    }
1385
1.16k
    if (MCInst_getNumOperands(MI) == 2 &&
1386
1.16k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1387
1.16k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1388
      // (BCONDA brtarget:$imm, 11)
1389
99
      AsmString = "bge,a $\x01";
1390
99
      break;
1391
99
    }
1392
1.07k
    if (MCInst_getNumOperands(MI) == 2 &&
1393
1.07k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1394
1.07k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1395
      // (BCONDA brtarget:$imm, 3)
1396
55
      AsmString = "bl,a $\x01";
1397
55
      break;
1398
55
    }
1399
1.01k
    if (MCInst_getNumOperands(MI) == 2 &&
1400
1.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1401
1.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1402
      // (BCONDA brtarget:$imm, 12)
1403
42
      AsmString = "bgu,a $\x01";
1404
42
      break;
1405
42
    }
1406
973
    if (MCInst_getNumOperands(MI) == 2 &&
1407
973
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1408
973
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1409
      // (BCONDA brtarget:$imm, 4)
1410
47
      AsmString = "bleu,a $\x01";
1411
47
      break;
1412
47
    }
1413
926
    if (MCInst_getNumOperands(MI) == 2 &&
1414
926
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1415
926
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1416
      // (BCONDA brtarget:$imm, 13)
1417
23
      AsmString = "bcc,a $\x01";
1418
23
      break;
1419
23
    }
1420
903
    if (MCInst_getNumOperands(MI) == 2 &&
1421
903
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1422
903
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1423
      // (BCONDA brtarget:$imm, 5)
1424
19
      AsmString = "bcs,a $\x01";
1425
19
      break;
1426
19
    }
1427
884
    if (MCInst_getNumOperands(MI) == 2 &&
1428
884
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1429
884
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1430
      // (BCONDA brtarget:$imm, 14)
1431
86
      AsmString = "bpos,a $\x01";
1432
86
      break;
1433
86
    }
1434
798
    if (MCInst_getNumOperands(MI) == 2 &&
1435
798
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1436
798
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1437
      // (BCONDA brtarget:$imm, 6)
1438
78
      AsmString = "bneg,a $\x01";
1439
78
      break;
1440
78
    }
1441
720
    if (MCInst_getNumOperands(MI) == 2 &&
1442
720
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1443
720
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1444
      // (BCONDA brtarget:$imm, 15)
1445
644
      AsmString = "bvc,a $\x01";
1446
644
      break;
1447
644
    }
1448
76
    if (MCInst_getNumOperands(MI) == 2 &&
1449
76
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1450
76
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1451
      // (BCONDA brtarget:$imm, 7)
1452
76
      AsmString = "bvs,a $\x01";
1453
76
      break;
1454
76
    }
1455
0
    return NULL;
1456
2.06k
  case SP_BPFCCANT:
1457
2.06k
    if (MCInst_getNumOperands(MI) == 3 &&
1458
2.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1459
2.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1460
2.06k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1461
2.06k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1462
      // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1463
239
      AsmString = "fba,a,pn $\x03, $\x01";
1464
239
      break;
1465
239
    }
1466
1.82k
    if (MCInst_getNumOperands(MI) == 3 &&
1467
1.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1468
1.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1469
1.82k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1470
1.82k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1471
      // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1472
30
      AsmString = "fbn,a,pn $\x03, $\x01";
1473
30
      break;
1474
30
    }
1475
1.79k
    if (MCInst_getNumOperands(MI) == 3 &&
1476
1.79k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1477
1.79k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1478
1.79k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1479
1.79k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1480
      // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1481
39
      AsmString = "fbu,a,pn $\x03, $\x01";
1482
39
      break;
1483
39
    }
1484
1.75k
    if (MCInst_getNumOperands(MI) == 3 &&
1485
1.75k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1486
1.75k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1487
1.75k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1488
1.75k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1489
      // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1490
335
      AsmString = "fbg,a,pn $\x03, $\x01";
1491
335
      break;
1492
335
    }
1493
1.42k
    if (MCInst_getNumOperands(MI) == 3 &&
1494
1.42k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1495
1.42k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1496
1.42k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1497
1.42k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1498
      // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1499
204
      AsmString = "fbug,a,pn $\x03, $\x01";
1500
204
      break;
1501
204
    }
1502
1.21k
    if (MCInst_getNumOperands(MI) == 3 &&
1503
1.21k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1504
1.21k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1505
1.21k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1506
1.21k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1507
      // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1508
298
      AsmString = "fbl,a,pn $\x03, $\x01";
1509
298
      break;
1510
298
    }
1511
920
    if (MCInst_getNumOperands(MI) == 3 &&
1512
920
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1513
920
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1514
920
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1515
920
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1516
      // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1517
106
      AsmString = "fbul,a,pn $\x03, $\x01";
1518
106
      break;
1519
106
    }
1520
814
    if (MCInst_getNumOperands(MI) == 3 &&
1521
814
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1522
814
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1523
814
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1524
814
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1525
      // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1526
286
      AsmString = "fblg,a,pn $\x03, $\x01";
1527
286
      break;
1528
286
    }
1529
528
    if (MCInst_getNumOperands(MI) == 3 &&
1530
528
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1531
528
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1532
528
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1533
528
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1534
      // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1535
44
      AsmString = "fbne,a,pn $\x03, $\x01";
1536
44
      break;
1537
44
    }
1538
484
    if (MCInst_getNumOperands(MI) == 3 &&
1539
484
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1540
484
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1541
484
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1542
484
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1543
      // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1544
94
      AsmString = "fbe,a,pn $\x03, $\x01";
1545
94
      break;
1546
94
    }
1547
390
    if (MCInst_getNumOperands(MI) == 3 &&
1548
390
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1549
390
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1550
390
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1551
390
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1552
      // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1553
24
      AsmString = "fbue,a,pn $\x03, $\x01";
1554
24
      break;
1555
24
    }
1556
366
    if (MCInst_getNumOperands(MI) == 3 &&
1557
366
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1558
366
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1559
366
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1560
366
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1561
      // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1562
12
      AsmString = "fbge,a,pn $\x03, $\x01";
1563
12
      break;
1564
12
    }
1565
354
    if (MCInst_getNumOperands(MI) == 3 &&
1566
354
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1567
354
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1568
354
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1569
354
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1570
      // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1571
88
      AsmString = "fbuge,a,pn $\x03, $\x01";
1572
88
      break;
1573
88
    }
1574
266
    if (MCInst_getNumOperands(MI) == 3 &&
1575
266
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1576
266
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1577
266
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1578
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1579
      // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1580
75
      AsmString = "fble,a,pn $\x03, $\x01";
1581
75
      break;
1582
75
    }
1583
191
    if (MCInst_getNumOperands(MI) == 3 &&
1584
191
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1585
191
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1586
191
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1587
191
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1588
      // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1589
110
      AsmString = "fbule,a,pn $\x03, $\x01";
1590
110
      break;
1591
110
    }
1592
81
    if (MCInst_getNumOperands(MI) == 3 &&
1593
81
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1594
81
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1595
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1596
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1597
      // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1598
81
      AsmString = "fbo,a,pn $\x03, $\x01";
1599
81
      break;
1600
81
    }
1601
0
    return NULL;
1602
1.62k
  case SP_BPFCCNT:
1603
1.62k
    if (MCInst_getNumOperands(MI) == 3 &&
1604
1.62k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1605
1.62k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1606
1.62k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1607
1.62k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1608
      // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1609
103
      AsmString = "fba,pn $\x03, $\x01";
1610
103
      break;
1611
103
    }
1612
1.52k
    if (MCInst_getNumOperands(MI) == 3 &&
1613
1.52k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1614
1.52k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1615
1.52k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1616
1.52k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1617
      // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1618
29
      AsmString = "fbn,pn $\x03, $\x01";
1619
29
      break;
1620
29
    }
1621
1.49k
    if (MCInst_getNumOperands(MI) == 3 &&
1622
1.49k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
1.49k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1624
1.49k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1625
1.49k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1626
      // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1627
121
      AsmString = "fbu,pn $\x03, $\x01";
1628
121
      break;
1629
121
    }
1630
1.37k
    if (MCInst_getNumOperands(MI) == 3 &&
1631
1.37k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1632
1.37k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1633
1.37k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1634
1.37k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1635
      // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1636
240
      AsmString = "fbg,pn $\x03, $\x01";
1637
240
      break;
1638
240
    }
1639
1.13k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
1.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1641
1.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1642
1.13k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1643
1.13k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1644
      // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1645
24
      AsmString = "fbug,pn $\x03, $\x01";
1646
24
      break;
1647
24
    }
1648
1.10k
    if (MCInst_getNumOperands(MI) == 3 &&
1649
1.10k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1650
1.10k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1651
1.10k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1652
1.10k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1653
      // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1654
20
      AsmString = "fbl,pn $\x03, $\x01";
1655
20
      break;
1656
20
    }
1657
1.08k
    if (MCInst_getNumOperands(MI) == 3 &&
1658
1.08k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1659
1.08k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1660
1.08k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1661
1.08k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1662
      // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1663
110
      AsmString = "fbul,pn $\x03, $\x01";
1664
110
      break;
1665
110
    }
1666
978
    if (MCInst_getNumOperands(MI) == 3 &&
1667
978
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1668
978
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1669
978
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1670
978
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1671
      // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1672
75
      AsmString = "fblg,pn $\x03, $\x01";
1673
75
      break;
1674
75
    }
1675
903
    if (MCInst_getNumOperands(MI) == 3 &&
1676
903
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1677
903
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1678
903
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1679
903
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1680
      // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1681
80
      AsmString = "fbne,pn $\x03, $\x01";
1682
80
      break;
1683
80
    }
1684
823
    if (MCInst_getNumOperands(MI) == 3 &&
1685
823
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1686
823
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1687
823
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1688
823
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1689
      // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1690
289
      AsmString = "fbe,pn $\x03, $\x01";
1691
289
      break;
1692
289
    }
1693
534
    if (MCInst_getNumOperands(MI) == 3 &&
1694
534
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1695
534
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1696
534
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1697
534
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1698
      // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1699
241
      AsmString = "fbue,pn $\x03, $\x01";
1700
241
      break;
1701
241
    }
1702
293
    if (MCInst_getNumOperands(MI) == 3 &&
1703
293
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1704
293
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1705
293
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1706
293
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1707
      // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1708
131
      AsmString = "fbge,pn $\x03, $\x01";
1709
131
      break;
1710
131
    }
1711
162
    if (MCInst_getNumOperands(MI) == 3 &&
1712
162
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1713
162
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1714
162
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1715
162
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1716
      // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1717
28
      AsmString = "fbuge,pn $\x03, $\x01";
1718
28
      break;
1719
28
    }
1720
134
    if (MCInst_getNumOperands(MI) == 3 &&
1721
134
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1722
134
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1723
134
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1724
134
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1725
      // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1726
61
      AsmString = "fble,pn $\x03, $\x01";
1727
61
      break;
1728
61
    }
1729
73
    if (MCInst_getNumOperands(MI) == 3 &&
1730
73
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1731
73
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1732
73
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1733
73
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1734
      // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1735
25
      AsmString = "fbule,pn $\x03, $\x01";
1736
25
      break;
1737
25
    }
1738
48
    if (MCInst_getNumOperands(MI) == 3 &&
1739
48
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1740
48
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1741
48
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1742
48
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1743
      // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1744
48
      AsmString = "fbo,pn $\x03, $\x01";
1745
48
      break;
1746
48
    }
1747
0
    return NULL;
1748
2.26k
  case SP_BPICCANT:
1749
2.26k
    if (MCInst_getNumOperands(MI) == 2 &&
1750
2.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1751
2.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1752
      // (BPICCANT brtarget:$imm, 8)
1753
86
      AsmString = "ba,a,pn %icc, $\x01";
1754
86
      break;
1755
86
    }
1756
2.18k
    if (MCInst_getNumOperands(MI) == 2 &&
1757
2.18k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
2.18k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1759
      // (BPICCANT brtarget:$imm, 0)
1760
487
      AsmString = "bn,a,pn %icc, $\x01";
1761
487
      break;
1762
487
    }
1763
1.69k
    if (MCInst_getNumOperands(MI) == 2 &&
1764
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1765
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1766
      // (BPICCANT brtarget:$imm, 9)
1767
34
      AsmString = "bne,a,pn %icc, $\x01";
1768
34
      break;
1769
34
    }
1770
1.66k
    if (MCInst_getNumOperands(MI) == 2 &&
1771
1.66k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1772
1.66k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1773
      // (BPICCANT brtarget:$imm, 1)
1774
43
      AsmString = "be,a,pn %icc, $\x01";
1775
43
      break;
1776
43
    }
1777
1.61k
    if (MCInst_getNumOperands(MI) == 2 &&
1778
1.61k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1779
1.61k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1780
      // (BPICCANT brtarget:$imm, 10)
1781
352
      AsmString = "bg,a,pn %icc, $\x01";
1782
352
      break;
1783
352
    }
1784
1.26k
    if (MCInst_getNumOperands(MI) == 2 &&
1785
1.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1786
1.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1787
      // (BPICCANT brtarget:$imm, 2)
1788
493
      AsmString = "ble,a,pn %icc, $\x01";
1789
493
      break;
1790
493
    }
1791
772
    if (MCInst_getNumOperands(MI) == 2 &&
1792
772
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1793
772
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1794
      // (BPICCANT brtarget:$imm, 11)
1795
18
      AsmString = "bge,a,pn %icc, $\x01";
1796
18
      break;
1797
18
    }
1798
754
    if (MCInst_getNumOperands(MI) == 2 &&
1799
754
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1800
754
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1801
      // (BPICCANT brtarget:$imm, 3)
1802
22
      AsmString = "bl,a,pn %icc, $\x01";
1803
22
      break;
1804
22
    }
1805
732
    if (MCInst_getNumOperands(MI) == 2 &&
1806
732
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1807
732
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1808
      // (BPICCANT brtarget:$imm, 12)
1809
83
      AsmString = "bgu,a,pn %icc, $\x01";
1810
83
      break;
1811
83
    }
1812
649
    if (MCInst_getNumOperands(MI) == 2 &&
1813
649
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1814
649
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1815
      // (BPICCANT brtarget:$imm, 4)
1816
149
      AsmString = "bleu,a,pn %icc, $\x01";
1817
149
      break;
1818
149
    }
1819
500
    if (MCInst_getNumOperands(MI) == 2 &&
1820
500
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1821
500
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1822
      // (BPICCANT brtarget:$imm, 13)
1823
38
      AsmString = "bcc,a,pn %icc, $\x01";
1824
38
      break;
1825
38
    }
1826
462
    if (MCInst_getNumOperands(MI) == 2 &&
1827
462
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1828
462
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1829
      // (BPICCANT brtarget:$imm, 5)
1830
89
      AsmString = "bcs,a,pn %icc, $\x01";
1831
89
      break;
1832
89
    }
1833
373
    if (MCInst_getNumOperands(MI) == 2 &&
1834
373
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1835
373
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1836
      // (BPICCANT brtarget:$imm, 14)
1837
121
      AsmString = "bpos,a,pn %icc, $\x01";
1838
121
      break;
1839
121
    }
1840
252
    if (MCInst_getNumOperands(MI) == 2 &&
1841
252
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1842
252
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1843
      // (BPICCANT brtarget:$imm, 6)
1844
90
      AsmString = "bneg,a,pn %icc, $\x01";
1845
90
      break;
1846
90
    }
1847
162
    if (MCInst_getNumOperands(MI) == 2 &&
1848
162
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1849
162
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1850
      // (BPICCANT brtarget:$imm, 15)
1851
138
      AsmString = "bvc,a,pn %icc, $\x01";
1852
138
      break;
1853
138
    }
1854
24
    if (MCInst_getNumOperands(MI) == 2 &&
1855
24
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1856
24
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1857
      // (BPICCANT brtarget:$imm, 7)
1858
24
      AsmString = "bvs,a,pn %icc, $\x01";
1859
24
      break;
1860
24
    }
1861
0
    return NULL;
1862
1.65k
  case SP_BPICCNT:
1863
1.65k
    if (MCInst_getNumOperands(MI) == 2 &&
1864
1.65k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1865
1.65k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1866
      // (BPICCNT brtarget:$imm, 8)
1867
109
      AsmString = "ba,pn %icc, $\x01";
1868
109
      break;
1869
109
    }
1870
1.54k
    if (MCInst_getNumOperands(MI) == 2 &&
1871
1.54k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1872
1.54k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1873
      // (BPICCNT brtarget:$imm, 0)
1874
313
      AsmString = "bn,pn %icc, $\x01";
1875
313
      break;
1876
313
    }
1877
1.23k
    if (MCInst_getNumOperands(MI) == 2 &&
1878
1.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1879
1.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1880
      // (BPICCNT brtarget:$imm, 9)
1881
142
      AsmString = "bne,pn %icc, $\x01";
1882
142
      break;
1883
142
    }
1884
1.09k
    if (MCInst_getNumOperands(MI) == 2 &&
1885
1.09k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1886
1.09k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1887
      // (BPICCNT brtarget:$imm, 1)
1888
31
      AsmString = "be,pn %icc, $\x01";
1889
31
      break;
1890
31
    }
1891
1.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1892
1.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1893
1.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1894
      // (BPICCNT brtarget:$imm, 10)
1895
131
      AsmString = "bg,pn %icc, $\x01";
1896
131
      break;
1897
131
    }
1898
931
    if (MCInst_getNumOperands(MI) == 2 &&
1899
931
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1900
931
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1901
      // (BPICCNT brtarget:$imm, 2)
1902
89
      AsmString = "ble,pn %icc, $\x01";
1903
89
      break;
1904
89
    }
1905
842
    if (MCInst_getNumOperands(MI) == 2 &&
1906
842
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1907
842
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1908
      // (BPICCNT brtarget:$imm, 11)
1909
22
      AsmString = "bge,pn %icc, $\x01";
1910
22
      break;
1911
22
    }
1912
820
    if (MCInst_getNumOperands(MI) == 2 &&
1913
820
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1914
820
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1915
      // (BPICCNT brtarget:$imm, 3)
1916
44
      AsmString = "bl,pn %icc, $\x01";
1917
44
      break;
1918
44
    }
1919
776
    if (MCInst_getNumOperands(MI) == 2 &&
1920
776
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1921
776
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1922
      // (BPICCNT brtarget:$imm, 12)
1923
83
      AsmString = "bgu,pn %icc, $\x01";
1924
83
      break;
1925
83
    }
1926
693
    if (MCInst_getNumOperands(MI) == 2 &&
1927
693
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1928
693
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1929
      // (BPICCNT brtarget:$imm, 4)
1930
37
      AsmString = "bleu,pn %icc, $\x01";
1931
37
      break;
1932
37
    }
1933
656
    if (MCInst_getNumOperands(MI) == 2 &&
1934
656
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1935
656
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1936
      // (BPICCNT brtarget:$imm, 13)
1937
19
      AsmString = "bcc,pn %icc, $\x01";
1938
19
      break;
1939
19
    }
1940
637
    if (MCInst_getNumOperands(MI) == 2 &&
1941
637
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1942
637
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1943
      // (BPICCNT brtarget:$imm, 5)
1944
352
      AsmString = "bcs,pn %icc, $\x01";
1945
352
      break;
1946
352
    }
1947
285
    if (MCInst_getNumOperands(MI) == 2 &&
1948
285
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1949
285
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1950
      // (BPICCNT brtarget:$imm, 14)
1951
25
      AsmString = "bpos,pn %icc, $\x01";
1952
25
      break;
1953
25
    }
1954
260
    if (MCInst_getNumOperands(MI) == 2 &&
1955
260
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1956
260
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1957
      // (BPICCNT brtarget:$imm, 6)
1958
46
      AsmString = "bneg,pn %icc, $\x01";
1959
46
      break;
1960
46
    }
1961
214
    if (MCInst_getNumOperands(MI) == 2 &&
1962
214
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1963
214
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1964
      // (BPICCNT brtarget:$imm, 15)
1965
121
      AsmString = "bvc,pn %icc, $\x01";
1966
121
      break;
1967
121
    }
1968
93
    if (MCInst_getNumOperands(MI) == 2 &&
1969
93
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1970
93
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1971
      // (BPICCNT brtarget:$imm, 7)
1972
93
      AsmString = "bvs,pn %icc, $\x01";
1973
93
      break;
1974
93
    }
1975
0
    return NULL;
1976
1.01k
  case SP_BPXCCANT:
1977
1.01k
    if (MCInst_getNumOperands(MI) == 2 &&
1978
1.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1979
1.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1980
      // (BPXCCANT brtarget:$imm, 8)
1981
47
      AsmString = "ba,a,pn %xcc, $\x01";
1982
47
      break;
1983
47
    }
1984
968
    if (MCInst_getNumOperands(MI) == 2 &&
1985
968
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1986
968
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1987
      // (BPXCCANT brtarget:$imm, 0)
1988
35
      AsmString = "bn,a,pn %xcc, $\x01";
1989
35
      break;
1990
35
    }
1991
933
    if (MCInst_getNumOperands(MI) == 2 &&
1992
933
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1993
933
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1994
      // (BPXCCANT brtarget:$imm, 9)
1995
13
      AsmString = "bne,a,pn %xcc, $\x01";
1996
13
      break;
1997
13
    }
1998
920
    if (MCInst_getNumOperands(MI) == 2 &&
1999
920
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2000
920
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2001
      // (BPXCCANT brtarget:$imm, 1)
2002
252
      AsmString = "be,a,pn %xcc, $\x01";
2003
252
      break;
2004
252
    }
2005
668
    if (MCInst_getNumOperands(MI) == 2 &&
2006
668
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2007
668
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2008
      // (BPXCCANT brtarget:$imm, 10)
2009
13
      AsmString = "bg,a,pn %xcc, $\x01";
2010
13
      break;
2011
13
    }
2012
655
    if (MCInst_getNumOperands(MI) == 2 &&
2013
655
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2014
655
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2015
      // (BPXCCANT brtarget:$imm, 2)
2016
88
      AsmString = "ble,a,pn %xcc, $\x01";
2017
88
      break;
2018
88
    }
2019
567
    if (MCInst_getNumOperands(MI) == 2 &&
2020
567
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2021
567
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2022
      // (BPXCCANT brtarget:$imm, 11)
2023
13
      AsmString = "bge,a,pn %xcc, $\x01";
2024
13
      break;
2025
13
    }
2026
554
    if (MCInst_getNumOperands(MI) == 2 &&
2027
554
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2028
554
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2029
      // (BPXCCANT brtarget:$imm, 3)
2030
10
      AsmString = "bl,a,pn %xcc, $\x01";
2031
10
      break;
2032
10
    }
2033
544
    if (MCInst_getNumOperands(MI) == 2 &&
2034
544
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2035
544
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2036
      // (BPXCCANT brtarget:$imm, 12)
2037
18
      AsmString = "bgu,a,pn %xcc, $\x01";
2038
18
      break;
2039
18
    }
2040
526
    if (MCInst_getNumOperands(MI) == 2 &&
2041
526
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2042
526
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2043
      // (BPXCCANT brtarget:$imm, 4)
2044
22
      AsmString = "bleu,a,pn %xcc, $\x01";
2045
22
      break;
2046
22
    }
2047
504
    if (MCInst_getNumOperands(MI) == 2 &&
2048
504
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2049
504
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2050
      // (BPXCCANT brtarget:$imm, 13)
2051
44
      AsmString = "bcc,a,pn %xcc, $\x01";
2052
44
      break;
2053
44
    }
2054
460
    if (MCInst_getNumOperands(MI) == 2 &&
2055
460
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2056
460
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2057
      // (BPXCCANT brtarget:$imm, 5)
2058
193
      AsmString = "bcs,a,pn %xcc, $\x01";
2059
193
      break;
2060
193
    }
2061
267
    if (MCInst_getNumOperands(MI) == 2 &&
2062
267
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2063
267
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2064
      // (BPXCCANT brtarget:$imm, 14)
2065
38
      AsmString = "bpos,a,pn %xcc, $\x01";
2066
38
      break;
2067
38
    }
2068
229
    if (MCInst_getNumOperands(MI) == 2 &&
2069
229
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2070
229
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2071
      // (BPXCCANT brtarget:$imm, 6)
2072
80
      AsmString = "bneg,a,pn %xcc, $\x01";
2073
80
      break;
2074
80
    }
2075
149
    if (MCInst_getNumOperands(MI) == 2 &&
2076
149
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2077
149
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2078
      // (BPXCCANT brtarget:$imm, 15)
2079
50
      AsmString = "bvc,a,pn %xcc, $\x01";
2080
50
      break;
2081
50
    }
2082
99
    if (MCInst_getNumOperands(MI) == 2 &&
2083
99
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2084
99
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2085
      // (BPXCCANT brtarget:$imm, 7)
2086
99
      AsmString = "bvs,a,pn %xcc, $\x01";
2087
99
      break;
2088
99
    }
2089
0
    return NULL;
2090
816
  case SP_BPXCCNT:
2091
816
    if (MCInst_getNumOperands(MI) == 2 &&
2092
816
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2093
816
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2094
      // (BPXCCNT brtarget:$imm, 8)
2095
103
      AsmString = "ba,pn %xcc, $\x01";
2096
103
      break;
2097
103
    }
2098
713
    if (MCInst_getNumOperands(MI) == 2 &&
2099
713
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2100
713
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2101
      // (BPXCCNT brtarget:$imm, 0)
2102
116
      AsmString = "bn,pn %xcc, $\x01";
2103
116
      break;
2104
116
    }
2105
597
    if (MCInst_getNumOperands(MI) == 2 &&
2106
597
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2107
597
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2108
      // (BPXCCNT brtarget:$imm, 9)
2109
10
      AsmString = "bne,pn %xcc, $\x01";
2110
10
      break;
2111
10
    }
2112
587
    if (MCInst_getNumOperands(MI) == 2 &&
2113
587
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2114
587
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2115
      // (BPXCCNT brtarget:$imm, 1)
2116
20
      AsmString = "be,pn %xcc, $\x01";
2117
20
      break;
2118
20
    }
2119
567
    if (MCInst_getNumOperands(MI) == 2 &&
2120
567
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2121
567
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2122
      // (BPXCCNT brtarget:$imm, 10)
2123
40
      AsmString = "bg,pn %xcc, $\x01";
2124
40
      break;
2125
40
    }
2126
527
    if (MCInst_getNumOperands(MI) == 2 &&
2127
527
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2128
527
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2129
      // (BPXCCNT brtarget:$imm, 2)
2130
46
      AsmString = "ble,pn %xcc, $\x01";
2131
46
      break;
2132
46
    }
2133
481
    if (MCInst_getNumOperands(MI) == 2 &&
2134
481
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2135
481
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2136
      // (BPXCCNT brtarget:$imm, 11)
2137
71
      AsmString = "bge,pn %xcc, $\x01";
2138
71
      break;
2139
71
    }
2140
410
    if (MCInst_getNumOperands(MI) == 2 &&
2141
410
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2142
410
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2143
      // (BPXCCNT brtarget:$imm, 3)
2144
87
      AsmString = "bl,pn %xcc, $\x01";
2145
87
      break;
2146
87
    }
2147
323
    if (MCInst_getNumOperands(MI) == 2 &&
2148
323
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2149
323
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2150
      // (BPXCCNT brtarget:$imm, 12)
2151
52
      AsmString = "bgu,pn %xcc, $\x01";
2152
52
      break;
2153
52
    }
2154
271
    if (MCInst_getNumOperands(MI) == 2 &&
2155
271
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2156
271
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2157
      // (BPXCCNT brtarget:$imm, 4)
2158
21
      AsmString = "bleu,pn %xcc, $\x01";
2159
21
      break;
2160
21
    }
2161
250
    if (MCInst_getNumOperands(MI) == 2 &&
2162
250
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2163
250
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2164
      // (BPXCCNT brtarget:$imm, 13)
2165
38
      AsmString = "bcc,pn %xcc, $\x01";
2166
38
      break;
2167
38
    }
2168
212
    if (MCInst_getNumOperands(MI) == 2 &&
2169
212
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2170
212
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2171
      // (BPXCCNT brtarget:$imm, 5)
2172
36
      AsmString = "bcs,pn %xcc, $\x01";
2173
36
      break;
2174
36
    }
2175
176
    if (MCInst_getNumOperands(MI) == 2 &&
2176
176
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2177
176
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2178
      // (BPXCCNT brtarget:$imm, 14)
2179
20
      AsmString = "bpos,pn %xcc, $\x01";
2180
20
      break;
2181
20
    }
2182
156
    if (MCInst_getNumOperands(MI) == 2 &&
2183
156
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2184
156
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2185
      // (BPXCCNT brtarget:$imm, 6)
2186
68
      AsmString = "bneg,pn %xcc, $\x01";
2187
68
      break;
2188
68
    }
2189
88
    if (MCInst_getNumOperands(MI) == 2 &&
2190
88
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2191
88
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2192
      // (BPXCCNT brtarget:$imm, 15)
2193
18
      AsmString = "bvc,pn %xcc, $\x01";
2194
18
      break;
2195
18
    }
2196
70
    if (MCInst_getNumOperands(MI) == 2 &&
2197
70
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2198
70
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2199
      // (BPXCCNT brtarget:$imm, 7)
2200
70
      AsmString = "bvs,pn %xcc, $\x01";
2201
70
      break;
2202
70
    }
2203
0
    return NULL;
2204
49
  case SP_FMOVD_ICC:
2205
49
    if (MCInst_getNumOperands(MI) == 3 &&
2206
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2207
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2208
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2209
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2210
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2211
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2212
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2213
0
      AsmString = "fmovda %icc, $\x02, $\x01";
2214
0
      break;
2215
0
    }
2216
49
    if (MCInst_getNumOperands(MI) == 3 &&
2217
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2218
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2219
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2220
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2221
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2222
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2223
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2224
0
      AsmString = "fmovdn %icc, $\x02, $\x01";
2225
0
      break;
2226
0
    }
2227
49
    if (MCInst_getNumOperands(MI) == 3 &&
2228
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2229
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2230
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2231
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2232
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2233
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2234
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2235
0
      AsmString = "fmovdne %icc, $\x02, $\x01";
2236
0
      break;
2237
0
    }
2238
49
    if (MCInst_getNumOperands(MI) == 3 &&
2239
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2240
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2241
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2242
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2243
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2244
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2245
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2246
0
      AsmString = "fmovde %icc, $\x02, $\x01";
2247
0
      break;
2248
0
    }
2249
49
    if (MCInst_getNumOperands(MI) == 3 &&
2250
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2251
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2252
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2253
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2254
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2255
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2256
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2257
0
      AsmString = "fmovdg %icc, $\x02, $\x01";
2258
0
      break;
2259
0
    }
2260
49
    if (MCInst_getNumOperands(MI) == 3 &&
2261
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2262
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2263
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2264
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2265
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2266
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2267
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2268
0
      AsmString = "fmovdle %icc, $\x02, $\x01";
2269
0
      break;
2270
0
    }
2271
49
    if (MCInst_getNumOperands(MI) == 3 &&
2272
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2273
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2274
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2275
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2276
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2277
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2278
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2279
0
      AsmString = "fmovdge %icc, $\x02, $\x01";
2280
0
      break;
2281
0
    }
2282
49
    if (MCInst_getNumOperands(MI) == 3 &&
2283
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2285
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2287
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2288
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2289
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2290
0
      AsmString = "fmovdl %icc, $\x02, $\x01";
2291
0
      break;
2292
0
    }
2293
49
    if (MCInst_getNumOperands(MI) == 3 &&
2294
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2295
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2296
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2297
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2298
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2299
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2300
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2301
0
      AsmString = "fmovdgu %icc, $\x02, $\x01";
2302
0
      break;
2303
0
    }
2304
49
    if (MCInst_getNumOperands(MI) == 3 &&
2305
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2306
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2307
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2308
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2309
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2310
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2311
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2312
0
      AsmString = "fmovdleu %icc, $\x02, $\x01";
2313
0
      break;
2314
0
    }
2315
49
    if (MCInst_getNumOperands(MI) == 3 &&
2316
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2317
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2318
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2319
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2320
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2321
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2322
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2323
0
      AsmString = "fmovdcc %icc, $\x02, $\x01";
2324
0
      break;
2325
0
    }
2326
49
    if (MCInst_getNumOperands(MI) == 3 &&
2327
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2328
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2329
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2330
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2331
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2332
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2333
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2334
0
      AsmString = "fmovdcs %icc, $\x02, $\x01";
2335
0
      break;
2336
0
    }
2337
49
    if (MCInst_getNumOperands(MI) == 3 &&
2338
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2339
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2340
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2341
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2342
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2343
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2344
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2345
0
      AsmString = "fmovdpos %icc, $\x02, $\x01";
2346
0
      break;
2347
0
    }
2348
49
    if (MCInst_getNumOperands(MI) == 3 &&
2349
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2350
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2351
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2352
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2353
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2354
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2355
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2356
0
      AsmString = "fmovdneg %icc, $\x02, $\x01";
2357
0
      break;
2358
0
    }
2359
49
    if (MCInst_getNumOperands(MI) == 3 &&
2360
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2361
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2362
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2363
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2364
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2365
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2366
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2367
0
      AsmString = "fmovdvc %icc, $\x02, $\x01";
2368
0
      break;
2369
0
    }
2370
49
    if (MCInst_getNumOperands(MI) == 3 &&
2371
49
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2372
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2373
49
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2374
49
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2375
49
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2376
49
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2377
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2378
0
      AsmString = "fmovdvs %icc, $\x02, $\x01";
2379
0
      break;
2380
0
    }
2381
49
    return NULL;
2382
44
  case SP_FMOVD_XCC:
2383
44
    if (MCInst_getNumOperands(MI) == 3 &&
2384
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2385
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2386
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2387
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2388
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2389
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2390
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2391
0
      AsmString = "fmovda %xcc, $\x02, $\x01";
2392
0
      break;
2393
0
    }
2394
44
    if (MCInst_getNumOperands(MI) == 3 &&
2395
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2396
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2397
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2398
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2399
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2400
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2401
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2402
0
      AsmString = "fmovdn %xcc, $\x02, $\x01";
2403
0
      break;
2404
0
    }
2405
44
    if (MCInst_getNumOperands(MI) == 3 &&
2406
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2407
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2408
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2409
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2410
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2411
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2412
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2413
0
      AsmString = "fmovdne %xcc, $\x02, $\x01";
2414
0
      break;
2415
0
    }
2416
44
    if (MCInst_getNumOperands(MI) == 3 &&
2417
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2418
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2419
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2420
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2421
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2422
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2423
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2424
0
      AsmString = "fmovde %xcc, $\x02, $\x01";
2425
0
      break;
2426
0
    }
2427
44
    if (MCInst_getNumOperands(MI) == 3 &&
2428
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2429
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2430
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2431
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2432
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2433
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2434
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2435
0
      AsmString = "fmovdg %xcc, $\x02, $\x01";
2436
0
      break;
2437
0
    }
2438
44
    if (MCInst_getNumOperands(MI) == 3 &&
2439
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2440
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2441
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2442
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2443
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2444
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2445
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2446
0
      AsmString = "fmovdle %xcc, $\x02, $\x01";
2447
0
      break;
2448
0
    }
2449
44
    if (MCInst_getNumOperands(MI) == 3 &&
2450
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2451
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2452
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2453
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2454
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2455
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2456
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2457
0
      AsmString = "fmovdge %xcc, $\x02, $\x01";
2458
0
      break;
2459
0
    }
2460
44
    if (MCInst_getNumOperands(MI) == 3 &&
2461
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2462
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2463
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2464
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2465
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2466
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2467
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2468
0
      AsmString = "fmovdl %xcc, $\x02, $\x01";
2469
0
      break;
2470
0
    }
2471
44
    if (MCInst_getNumOperands(MI) == 3 &&
2472
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2473
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2474
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2475
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2476
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2477
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2478
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2479
0
      AsmString = "fmovdgu %xcc, $\x02, $\x01";
2480
0
      break;
2481
0
    }
2482
44
    if (MCInst_getNumOperands(MI) == 3 &&
2483
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2484
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2485
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2486
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2487
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2488
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2489
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2490
0
      AsmString = "fmovdleu %xcc, $\x02, $\x01";
2491
0
      break;
2492
0
    }
2493
44
    if (MCInst_getNumOperands(MI) == 3 &&
2494
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2495
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2496
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2497
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2498
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2499
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2500
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2501
0
      AsmString = "fmovdcc %xcc, $\x02, $\x01";
2502
0
      break;
2503
0
    }
2504
44
    if (MCInst_getNumOperands(MI) == 3 &&
2505
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2506
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2507
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2508
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2509
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2510
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2511
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2512
0
      AsmString = "fmovdcs %xcc, $\x02, $\x01";
2513
0
      break;
2514
0
    }
2515
44
    if (MCInst_getNumOperands(MI) == 3 &&
2516
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2518
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2519
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2520
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2521
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2522
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2523
0
      AsmString = "fmovdpos %xcc, $\x02, $\x01";
2524
0
      break;
2525
0
    }
2526
44
    if (MCInst_getNumOperands(MI) == 3 &&
2527
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2528
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2529
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2530
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2531
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2532
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2533
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2534
0
      AsmString = "fmovdneg %xcc, $\x02, $\x01";
2535
0
      break;
2536
0
    }
2537
44
    if (MCInst_getNumOperands(MI) == 3 &&
2538
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2539
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2540
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2541
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2542
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2543
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2544
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2545
0
      AsmString = "fmovdvc %xcc, $\x02, $\x01";
2546
0
      break;
2547
0
    }
2548
44
    if (MCInst_getNumOperands(MI) == 3 &&
2549
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2550
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2551
44
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2552
44
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2553
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2554
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2555
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2556
0
      AsmString = "fmovdvs %xcc, $\x02, $\x01";
2557
0
      break;
2558
0
    }
2559
44
    return NULL;
2560
15
  case SP_FMOVQ_ICC:
2561
15
    if (MCInst_getNumOperands(MI) == 3 &&
2562
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2563
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2564
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2565
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2566
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2567
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2568
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2569
0
      AsmString = "fmovqa %icc, $\x02, $\x01";
2570
0
      break;
2571
0
    }
2572
15
    if (MCInst_getNumOperands(MI) == 3 &&
2573
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2574
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2575
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2576
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2577
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2578
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2579
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2580
0
      AsmString = "fmovqn %icc, $\x02, $\x01";
2581
0
      break;
2582
0
    }
2583
15
    if (MCInst_getNumOperands(MI) == 3 &&
2584
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2585
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2586
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2587
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2588
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2589
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2590
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2591
0
      AsmString = "fmovqne %icc, $\x02, $\x01";
2592
0
      break;
2593
0
    }
2594
15
    if (MCInst_getNumOperands(MI) == 3 &&
2595
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2596
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2597
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2598
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2599
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2600
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2601
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2602
0
      AsmString = "fmovqe %icc, $\x02, $\x01";
2603
0
      break;
2604
0
    }
2605
15
    if (MCInst_getNumOperands(MI) == 3 &&
2606
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2607
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2608
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2609
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2610
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2611
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2612
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2613
0
      AsmString = "fmovqg %icc, $\x02, $\x01";
2614
0
      break;
2615
0
    }
2616
15
    if (MCInst_getNumOperands(MI) == 3 &&
2617
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2618
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2619
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2620
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2621
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2622
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2623
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2624
0
      AsmString = "fmovqle %icc, $\x02, $\x01";
2625
0
      break;
2626
0
    }
2627
15
    if (MCInst_getNumOperands(MI) == 3 &&
2628
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2629
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2630
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2631
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2632
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2633
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2634
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2635
0
      AsmString = "fmovqge %icc, $\x02, $\x01";
2636
0
      break;
2637
0
    }
2638
15
    if (MCInst_getNumOperands(MI) == 3 &&
2639
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2640
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2641
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2642
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2643
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2644
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2645
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2646
0
      AsmString = "fmovql %icc, $\x02, $\x01";
2647
0
      break;
2648
0
    }
2649
15
    if (MCInst_getNumOperands(MI) == 3 &&
2650
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2651
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2652
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2653
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2654
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2655
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2656
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2657
0
      AsmString = "fmovqgu %icc, $\x02, $\x01";
2658
0
      break;
2659
0
    }
2660
15
    if (MCInst_getNumOperands(MI) == 3 &&
2661
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2662
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2663
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2664
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2665
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2666
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2667
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2668
0
      AsmString = "fmovqleu %icc, $\x02, $\x01";
2669
0
      break;
2670
0
    }
2671
15
    if (MCInst_getNumOperands(MI) == 3 &&
2672
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2673
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2674
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2675
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2676
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2677
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2678
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2679
0
      AsmString = "fmovqcc %icc, $\x02, $\x01";
2680
0
      break;
2681
0
    }
2682
15
    if (MCInst_getNumOperands(MI) == 3 &&
2683
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2684
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2685
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2686
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2687
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2688
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2689
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2690
0
      AsmString = "fmovqcs %icc, $\x02, $\x01";
2691
0
      break;
2692
0
    }
2693
15
    if (MCInst_getNumOperands(MI) == 3 &&
2694
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2695
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2696
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2697
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2698
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2699
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2700
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2701
0
      AsmString = "fmovqpos %icc, $\x02, $\x01";
2702
0
      break;
2703
0
    }
2704
15
    if (MCInst_getNumOperands(MI) == 3 &&
2705
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2706
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2707
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2708
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2709
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2710
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2711
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2712
0
      AsmString = "fmovqneg %icc, $\x02, $\x01";
2713
0
      break;
2714
0
    }
2715
15
    if (MCInst_getNumOperands(MI) == 3 &&
2716
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2717
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2718
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2719
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2720
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2721
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2722
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2723
0
      AsmString = "fmovqvc %icc, $\x02, $\x01";
2724
0
      break;
2725
0
    }
2726
15
    if (MCInst_getNumOperands(MI) == 3 &&
2727
15
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2728
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2729
15
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2730
15
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2731
15
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2732
15
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2733
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2734
0
      AsmString = "fmovqvs %icc, $\x02, $\x01";
2735
0
      break;
2736
0
    }
2737
15
    return NULL;
2738
26
  case SP_FMOVQ_XCC:
2739
26
    if (MCInst_getNumOperands(MI) == 3 &&
2740
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2741
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2742
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2743
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2744
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2745
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2746
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2747
0
      AsmString = "fmovqa %xcc, $\x02, $\x01";
2748
0
      break;
2749
0
    }
2750
26
    if (MCInst_getNumOperands(MI) == 3 &&
2751
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2752
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2753
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2754
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2755
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2756
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2757
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2758
0
      AsmString = "fmovqn %xcc, $\x02, $\x01";
2759
0
      break;
2760
0
    }
2761
26
    if (MCInst_getNumOperands(MI) == 3 &&
2762
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2763
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2764
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2765
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2766
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2767
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2768
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2769
0
      AsmString = "fmovqne %xcc, $\x02, $\x01";
2770
0
      break;
2771
0
    }
2772
26
    if (MCInst_getNumOperands(MI) == 3 &&
2773
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2774
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2775
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2776
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2777
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2778
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2779
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2780
0
      AsmString = "fmovqe %xcc, $\x02, $\x01";
2781
0
      break;
2782
0
    }
2783
26
    if (MCInst_getNumOperands(MI) == 3 &&
2784
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2785
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2786
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2787
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2788
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2789
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2790
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2791
0
      AsmString = "fmovqg %xcc, $\x02, $\x01";
2792
0
      break;
2793
0
    }
2794
26
    if (MCInst_getNumOperands(MI) == 3 &&
2795
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2796
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2797
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2798
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2799
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2800
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2801
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2802
0
      AsmString = "fmovqle %xcc, $\x02, $\x01";
2803
0
      break;
2804
0
    }
2805
26
    if (MCInst_getNumOperands(MI) == 3 &&
2806
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2807
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2808
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2809
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2810
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2811
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2812
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2813
0
      AsmString = "fmovqge %xcc, $\x02, $\x01";
2814
0
      break;
2815
0
    }
2816
26
    if (MCInst_getNumOperands(MI) == 3 &&
2817
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2818
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2819
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2820
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2821
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2822
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2823
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2824
0
      AsmString = "fmovql %xcc, $\x02, $\x01";
2825
0
      break;
2826
0
    }
2827
26
    if (MCInst_getNumOperands(MI) == 3 &&
2828
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2829
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2830
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2831
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2832
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2834
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2835
0
      AsmString = "fmovqgu %xcc, $\x02, $\x01";
2836
0
      break;
2837
0
    }
2838
26
    if (MCInst_getNumOperands(MI) == 3 &&
2839
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2840
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2841
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2842
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2843
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2844
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2845
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2846
0
      AsmString = "fmovqleu %xcc, $\x02, $\x01";
2847
0
      break;
2848
0
    }
2849
26
    if (MCInst_getNumOperands(MI) == 3 &&
2850
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2851
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2852
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2853
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2854
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2855
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2856
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2857
0
      AsmString = "fmovqcc %xcc, $\x02, $\x01";
2858
0
      break;
2859
0
    }
2860
26
    if (MCInst_getNumOperands(MI) == 3 &&
2861
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2862
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2863
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2864
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2865
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2866
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2867
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2868
0
      AsmString = "fmovqcs %xcc, $\x02, $\x01";
2869
0
      break;
2870
0
    }
2871
26
    if (MCInst_getNumOperands(MI) == 3 &&
2872
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2873
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2874
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2875
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2876
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2877
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2878
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2879
0
      AsmString = "fmovqpos %xcc, $\x02, $\x01";
2880
0
      break;
2881
0
    }
2882
26
    if (MCInst_getNumOperands(MI) == 3 &&
2883
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2884
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2885
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2886
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2887
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2888
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2889
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2890
0
      AsmString = "fmovqneg %xcc, $\x02, $\x01";
2891
0
      break;
2892
0
    }
2893
26
    if (MCInst_getNumOperands(MI) == 3 &&
2894
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2895
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2896
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2897
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2898
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2899
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2900
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2901
0
      AsmString = "fmovqvc %xcc, $\x02, $\x01";
2902
0
      break;
2903
0
    }
2904
26
    if (MCInst_getNumOperands(MI) == 3 &&
2905
26
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2906
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2907
26
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2908
26
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2909
26
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2910
26
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2911
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2912
0
      AsmString = "fmovqvs %xcc, $\x02, $\x01";
2913
0
      break;
2914
0
    }
2915
26
    return NULL;
2916
28
  case SP_FMOVS_ICC:
2917
28
    if (MCInst_getNumOperands(MI) == 3 &&
2918
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2919
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2920
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2921
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2922
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2923
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2924
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2925
0
      AsmString = "fmovsa %icc, $\x02, $\x01";
2926
0
      break;
2927
0
    }
2928
28
    if (MCInst_getNumOperands(MI) == 3 &&
2929
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2930
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2931
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2932
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2933
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2934
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2935
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2936
0
      AsmString = "fmovsn %icc, $\x02, $\x01";
2937
0
      break;
2938
0
    }
2939
28
    if (MCInst_getNumOperands(MI) == 3 &&
2940
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2941
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2942
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2943
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2944
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2945
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2946
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2947
0
      AsmString = "fmovsne %icc, $\x02, $\x01";
2948
0
      break;
2949
0
    }
2950
28
    if (MCInst_getNumOperands(MI) == 3 &&
2951
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2952
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2953
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2954
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2955
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2956
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2957
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2958
0
      AsmString = "fmovse %icc, $\x02, $\x01";
2959
0
      break;
2960
0
    }
2961
28
    if (MCInst_getNumOperands(MI) == 3 &&
2962
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2963
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2964
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2965
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2966
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2967
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2968
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2969
0
      AsmString = "fmovsg %icc, $\x02, $\x01";
2970
0
      break;
2971
0
    }
2972
28
    if (MCInst_getNumOperands(MI) == 3 &&
2973
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2974
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2975
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2976
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2977
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2978
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2979
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2980
0
      AsmString = "fmovsle %icc, $\x02, $\x01";
2981
0
      break;
2982
0
    }
2983
28
    if (MCInst_getNumOperands(MI) == 3 &&
2984
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2985
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2986
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2987
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2988
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2989
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2990
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2991
0
      AsmString = "fmovsge %icc, $\x02, $\x01";
2992
0
      break;
2993
0
    }
2994
28
    if (MCInst_getNumOperands(MI) == 3 &&
2995
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2996
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2997
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2998
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2999
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3000
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3001
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3002
0
      AsmString = "fmovsl %icc, $\x02, $\x01";
3003
0
      break;
3004
0
    }
3005
28
    if (MCInst_getNumOperands(MI) == 3 &&
3006
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3007
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3008
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3009
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3010
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3011
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3012
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3013
0
      AsmString = "fmovsgu %icc, $\x02, $\x01";
3014
0
      break;
3015
0
    }
3016
28
    if (MCInst_getNumOperands(MI) == 3 &&
3017
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3018
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3019
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3020
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3021
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3022
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3023
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3024
0
      AsmString = "fmovsleu %icc, $\x02, $\x01";
3025
0
      break;
3026
0
    }
3027
28
    if (MCInst_getNumOperands(MI) == 3 &&
3028
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3029
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3030
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3031
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3032
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3033
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3034
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3035
0
      AsmString = "fmovscc %icc, $\x02, $\x01";
3036
0
      break;
3037
0
    }
3038
28
    if (MCInst_getNumOperands(MI) == 3 &&
3039
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3040
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3041
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3042
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3043
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3044
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3045
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3046
0
      AsmString = "fmovscs %icc, $\x02, $\x01";
3047
0
      break;
3048
0
    }
3049
28
    if (MCInst_getNumOperands(MI) == 3 &&
3050
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3051
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3052
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3053
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3054
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3055
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3056
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3057
0
      AsmString = "fmovspos %icc, $\x02, $\x01";
3058
0
      break;
3059
0
    }
3060
28
    if (MCInst_getNumOperands(MI) == 3 &&
3061
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3062
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3063
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3064
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3065
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3066
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3067
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3068
0
      AsmString = "fmovsneg %icc, $\x02, $\x01";
3069
0
      break;
3070
0
    }
3071
28
    if (MCInst_getNumOperands(MI) == 3 &&
3072
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3073
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3074
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3075
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3076
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3077
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3078
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3079
0
      AsmString = "fmovsvc %icc, $\x02, $\x01";
3080
0
      break;
3081
0
    }
3082
28
    if (MCInst_getNumOperands(MI) == 3 &&
3083
28
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3084
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3085
28
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3086
28
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3087
28
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3088
28
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3089
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3090
0
      AsmString = "fmovsvs %icc, $\x02, $\x01";
3091
0
      break;
3092
0
    }
3093
28
    return NULL;
3094
11
  case SP_FMOVS_XCC:
3095
11
    if (MCInst_getNumOperands(MI) == 3 &&
3096
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3097
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3098
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3099
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3100
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3101
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3102
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3103
0
      AsmString = "fmovsa %xcc, $\x02, $\x01";
3104
0
      break;
3105
0
    }
3106
11
    if (MCInst_getNumOperands(MI) == 3 &&
3107
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3108
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3109
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3110
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3111
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3112
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3113
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3114
0
      AsmString = "fmovsn %xcc, $\x02, $\x01";
3115
0
      break;
3116
0
    }
3117
11
    if (MCInst_getNumOperands(MI) == 3 &&
3118
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3119
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3120
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3121
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3122
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3123
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3124
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3125
0
      AsmString = "fmovsne %xcc, $\x02, $\x01";
3126
0
      break;
3127
0
    }
3128
11
    if (MCInst_getNumOperands(MI) == 3 &&
3129
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3130
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3131
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3132
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3133
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3134
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3135
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3136
0
      AsmString = "fmovse %xcc, $\x02, $\x01";
3137
0
      break;
3138
0
    }
3139
11
    if (MCInst_getNumOperands(MI) == 3 &&
3140
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3141
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3142
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3143
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3144
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3145
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3146
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3147
0
      AsmString = "fmovsg %xcc, $\x02, $\x01";
3148
0
      break;
3149
0
    }
3150
11
    if (MCInst_getNumOperands(MI) == 3 &&
3151
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3152
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3153
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3154
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3155
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3156
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3157
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3158
0
      AsmString = "fmovsle %xcc, $\x02, $\x01";
3159
0
      break;
3160
0
    }
3161
11
    if (MCInst_getNumOperands(MI) == 3 &&
3162
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3163
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3164
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3165
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3166
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3167
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3168
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3169
0
      AsmString = "fmovsge %xcc, $\x02, $\x01";
3170
0
      break;
3171
0
    }
3172
11
    if (MCInst_getNumOperands(MI) == 3 &&
3173
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3174
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3175
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3176
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3177
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3178
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3179
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3180
0
      AsmString = "fmovsl %xcc, $\x02, $\x01";
3181
0
      break;
3182
0
    }
3183
11
    if (MCInst_getNumOperands(MI) == 3 &&
3184
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3185
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3186
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3187
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3188
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3190
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3191
0
      AsmString = "fmovsgu %xcc, $\x02, $\x01";
3192
0
      break;
3193
0
    }
3194
11
    if (MCInst_getNumOperands(MI) == 3 &&
3195
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3196
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3197
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3198
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3199
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3200
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3201
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3202
0
      AsmString = "fmovsleu %xcc, $\x02, $\x01";
3203
0
      break;
3204
0
    }
3205
11
    if (MCInst_getNumOperands(MI) == 3 &&
3206
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3207
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3208
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3209
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3210
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3211
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3212
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3213
0
      AsmString = "fmovscc %xcc, $\x02, $\x01";
3214
0
      break;
3215
0
    }
3216
11
    if (MCInst_getNumOperands(MI) == 3 &&
3217
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3218
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3219
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3220
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3221
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3222
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3223
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3224
0
      AsmString = "fmovscs %xcc, $\x02, $\x01";
3225
0
      break;
3226
0
    }
3227
11
    if (MCInst_getNumOperands(MI) == 3 &&
3228
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3229
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3230
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3231
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3232
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3233
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3234
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3235
0
      AsmString = "fmovspos %xcc, $\x02, $\x01";
3236
0
      break;
3237
0
    }
3238
11
    if (MCInst_getNumOperands(MI) == 3 &&
3239
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3240
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3241
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3242
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3243
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3244
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3245
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3246
0
      AsmString = "fmovsneg %xcc, $\x02, $\x01";
3247
0
      break;
3248
0
    }
3249
11
    if (MCInst_getNumOperands(MI) == 3 &&
3250
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3251
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3252
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3253
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3254
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3255
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3256
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3257
0
      AsmString = "fmovsvc %xcc, $\x02, $\x01";
3258
0
      break;
3259
0
    }
3260
11
    if (MCInst_getNumOperands(MI) == 3 &&
3261
11
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3262
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3263
11
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3264
11
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3265
11
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3266
11
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3267
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3268
0
      AsmString = "fmovsvs %xcc, $\x02, $\x01";
3269
0
      break;
3270
0
    }
3271
11
    return NULL;
3272
19
  case SP_MOVICCri:
3273
19
    if (MCInst_getNumOperands(MI) == 3 &&
3274
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3275
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3276
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3277
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3278
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3279
0
      AsmString = "mova %icc, $\x02, $\x01";
3280
0
      break;
3281
0
    }
3282
19
    if (MCInst_getNumOperands(MI) == 3 &&
3283
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3284
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3285
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3286
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3287
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3288
0
      AsmString = "movn %icc, $\x02, $\x01";
3289
0
      break;
3290
0
    }
3291
19
    if (MCInst_getNumOperands(MI) == 3 &&
3292
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3293
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3294
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3295
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3296
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3297
0
      AsmString = "movne %icc, $\x02, $\x01";
3298
0
      break;
3299
0
    }
3300
19
    if (MCInst_getNumOperands(MI) == 3 &&
3301
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3302
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3303
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3304
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3305
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3306
0
      AsmString = "move %icc, $\x02, $\x01";
3307
0
      break;
3308
0
    }
3309
19
    if (MCInst_getNumOperands(MI) == 3 &&
3310
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3311
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3312
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3313
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3314
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3315
0
      AsmString = "movg %icc, $\x02, $\x01";
3316
0
      break;
3317
0
    }
3318
19
    if (MCInst_getNumOperands(MI) == 3 &&
3319
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3320
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3321
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3322
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3323
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3324
0
      AsmString = "movle %icc, $\x02, $\x01";
3325
0
      break;
3326
0
    }
3327
19
    if (MCInst_getNumOperands(MI) == 3 &&
3328
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3329
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3330
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3331
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3332
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3333
0
      AsmString = "movge %icc, $\x02, $\x01";
3334
0
      break;
3335
0
    }
3336
19
    if (MCInst_getNumOperands(MI) == 3 &&
3337
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3338
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3339
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3340
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3341
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3342
0
      AsmString = "movl %icc, $\x02, $\x01";
3343
0
      break;
3344
0
    }
3345
19
    if (MCInst_getNumOperands(MI) == 3 &&
3346
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3347
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3348
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3349
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3350
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3351
0
      AsmString = "movgu %icc, $\x02, $\x01";
3352
0
      break;
3353
0
    }
3354
19
    if (MCInst_getNumOperands(MI) == 3 &&
3355
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3356
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3357
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3358
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3359
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3360
0
      AsmString = "movleu %icc, $\x02, $\x01";
3361
0
      break;
3362
0
    }
3363
19
    if (MCInst_getNumOperands(MI) == 3 &&
3364
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3365
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3366
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3367
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3368
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3369
0
      AsmString = "movcc %icc, $\x02, $\x01";
3370
0
      break;
3371
0
    }
3372
19
    if (MCInst_getNumOperands(MI) == 3 &&
3373
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3374
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3375
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3376
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3377
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3378
0
      AsmString = "movcs %icc, $\x02, $\x01";
3379
0
      break;
3380
0
    }
3381
19
    if (MCInst_getNumOperands(MI) == 3 &&
3382
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3383
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3384
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3385
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3386
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3387
0
      AsmString = "movpos %icc, $\x02, $\x01";
3388
0
      break;
3389
0
    }
3390
19
    if (MCInst_getNumOperands(MI) == 3 &&
3391
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3392
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3393
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3394
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3395
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3396
0
      AsmString = "movneg %icc, $\x02, $\x01";
3397
0
      break;
3398
0
    }
3399
19
    if (MCInst_getNumOperands(MI) == 3 &&
3400
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3401
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3402
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3403
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3404
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3405
0
      AsmString = "movvc %icc, $\x02, $\x01";
3406
0
      break;
3407
0
    }
3408
19
    if (MCInst_getNumOperands(MI) == 3 &&
3409
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3410
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3411
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3412
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3413
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3414
0
      AsmString = "movvs %icc, $\x02, $\x01";
3415
0
      break;
3416
0
    }
3417
19
    return NULL;
3418
22
  case SP_MOVICCrr:
3419
22
    if (MCInst_getNumOperands(MI) == 3 &&
3420
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3421
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3422
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3423
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3424
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3425
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3426
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3427
0
      AsmString = "mova %icc, $\x02, $\x01";
3428
0
      break;
3429
0
    }
3430
22
    if (MCInst_getNumOperands(MI) == 3 &&
3431
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3432
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3433
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3434
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3435
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3436
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3437
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3438
0
      AsmString = "movn %icc, $\x02, $\x01";
3439
0
      break;
3440
0
    }
3441
22
    if (MCInst_getNumOperands(MI) == 3 &&
3442
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3443
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3444
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3445
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3446
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3447
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3448
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3449
0
      AsmString = "movne %icc, $\x02, $\x01";
3450
0
      break;
3451
0
    }
3452
22
    if (MCInst_getNumOperands(MI) == 3 &&
3453
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3454
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3455
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3456
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3457
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3458
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3459
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3460
0
      AsmString = "move %icc, $\x02, $\x01";
3461
0
      break;
3462
0
    }
3463
22
    if (MCInst_getNumOperands(MI) == 3 &&
3464
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3465
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3466
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3467
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3468
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3469
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3470
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3471
0
      AsmString = "movg %icc, $\x02, $\x01";
3472
0
      break;
3473
0
    }
3474
22
    if (MCInst_getNumOperands(MI) == 3 &&
3475
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3476
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3477
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3478
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3479
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3480
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3481
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3482
0
      AsmString = "movle %icc, $\x02, $\x01";
3483
0
      break;
3484
0
    }
3485
22
    if (MCInst_getNumOperands(MI) == 3 &&
3486
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3487
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3488
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3489
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3490
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3491
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3492
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3493
0
      AsmString = "movge %icc, $\x02, $\x01";
3494
0
      break;
3495
0
    }
3496
22
    if (MCInst_getNumOperands(MI) == 3 &&
3497
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3498
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3499
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3500
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3501
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3502
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3503
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3504
0
      AsmString = "movl %icc, $\x02, $\x01";
3505
0
      break;
3506
0
    }
3507
22
    if (MCInst_getNumOperands(MI) == 3 &&
3508
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3509
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3510
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3511
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3512
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3513
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3514
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3515
0
      AsmString = "movgu %icc, $\x02, $\x01";
3516
0
      break;
3517
0
    }
3518
22
    if (MCInst_getNumOperands(MI) == 3 &&
3519
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3520
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3521
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3522
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3523
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3524
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3525
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3526
0
      AsmString = "movleu %icc, $\x02, $\x01";
3527
0
      break;
3528
0
    }
3529
22
    if (MCInst_getNumOperands(MI) == 3 &&
3530
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3531
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3532
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3533
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3534
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3535
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3536
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3537
0
      AsmString = "movcc %icc, $\x02, $\x01";
3538
0
      break;
3539
0
    }
3540
22
    if (MCInst_getNumOperands(MI) == 3 &&
3541
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3542
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3543
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3544
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3545
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3546
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3547
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3548
0
      AsmString = "movcs %icc, $\x02, $\x01";
3549
0
      break;
3550
0
    }
3551
22
    if (MCInst_getNumOperands(MI) == 3 &&
3552
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3553
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3554
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3555
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3556
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3557
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3558
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3559
0
      AsmString = "movpos %icc, $\x02, $\x01";
3560
0
      break;
3561
0
    }
3562
22
    if (MCInst_getNumOperands(MI) == 3 &&
3563
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3564
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3565
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3566
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3567
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3568
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3569
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3570
0
      AsmString = "movneg %icc, $\x02, $\x01";
3571
0
      break;
3572
0
    }
3573
22
    if (MCInst_getNumOperands(MI) == 3 &&
3574
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3575
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3576
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3577
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3578
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3579
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3580
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3581
0
      AsmString = "movvc %icc, $\x02, $\x01";
3582
0
      break;
3583
0
    }
3584
22
    if (MCInst_getNumOperands(MI) == 3 &&
3585
22
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3586
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3587
22
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3588
22
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3589
22
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3590
22
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3591
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3592
0
      AsmString = "movvs %icc, $\x02, $\x01";
3593
0
      break;
3594
0
    }
3595
22
    return NULL;
3596
76
  case SP_MOVXCCri:
3597
76
    if (MCInst_getNumOperands(MI) == 3 &&
3598
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3599
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3600
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3601
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3602
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3603
0
      AsmString = "mova %xcc, $\x02, $\x01";
3604
0
      break;
3605
0
    }
3606
76
    if (MCInst_getNumOperands(MI) == 3 &&
3607
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3608
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3609
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3610
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3611
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3612
0
      AsmString = "movn %xcc, $\x02, $\x01";
3613
0
      break;
3614
0
    }
3615
76
    if (MCInst_getNumOperands(MI) == 3 &&
3616
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3617
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3618
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3619
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3620
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3621
0
      AsmString = "movne %xcc, $\x02, $\x01";
3622
0
      break;
3623
0
    }
3624
76
    if (MCInst_getNumOperands(MI) == 3 &&
3625
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3626
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3627
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3628
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3629
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3630
0
      AsmString = "move %xcc, $\x02, $\x01";
3631
0
      break;
3632
0
    }
3633
76
    if (MCInst_getNumOperands(MI) == 3 &&
3634
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3635
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3636
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3637
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3638
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3639
0
      AsmString = "movg %xcc, $\x02, $\x01";
3640
0
      break;
3641
0
    }
3642
76
    if (MCInst_getNumOperands(MI) == 3 &&
3643
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3644
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3645
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3646
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3647
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3648
0
      AsmString = "movle %xcc, $\x02, $\x01";
3649
0
      break;
3650
0
    }
3651
76
    if (MCInst_getNumOperands(MI) == 3 &&
3652
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3653
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3654
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3655
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3656
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3657
0
      AsmString = "movge %xcc, $\x02, $\x01";
3658
0
      break;
3659
0
    }
3660
76
    if (MCInst_getNumOperands(MI) == 3 &&
3661
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3662
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3663
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3664
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3665
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3666
0
      AsmString = "movl %xcc, $\x02, $\x01";
3667
0
      break;
3668
0
    }
3669
76
    if (MCInst_getNumOperands(MI) == 3 &&
3670
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3671
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3672
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3673
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3674
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3675
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3676
0
      break;
3677
0
    }
3678
76
    if (MCInst_getNumOperands(MI) == 3 &&
3679
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3680
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3681
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3682
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3683
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3684
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3685
0
      break;
3686
0
    }
3687
76
    if (MCInst_getNumOperands(MI) == 3 &&
3688
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3689
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3690
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3691
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3692
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3693
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3694
0
      break;
3695
0
    }
3696
76
    if (MCInst_getNumOperands(MI) == 3 &&
3697
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3698
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3699
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3700
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3701
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3702
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3703
0
      break;
3704
0
    }
3705
76
    if (MCInst_getNumOperands(MI) == 3 &&
3706
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3707
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3708
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3709
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3710
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3711
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3712
0
      break;
3713
0
    }
3714
76
    if (MCInst_getNumOperands(MI) == 3 &&
3715
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3716
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3717
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3718
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3719
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3720
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3721
0
      break;
3722
0
    }
3723
76
    if (MCInst_getNumOperands(MI) == 3 &&
3724
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3725
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3726
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3727
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3728
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3729
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3730
0
      break;
3731
0
    }
3732
76
    if (MCInst_getNumOperands(MI) == 3 &&
3733
76
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3734
76
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3735
76
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3736
76
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3737
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3738
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3739
0
      break;
3740
0
    }
3741
76
    return NULL;
3742
19
  case SP_MOVXCCrr:
3743
19
    if (MCInst_getNumOperands(MI) == 3 &&
3744
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3745
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3746
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3747
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3748
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3749
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3750
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3751
0
      AsmString = "mova %xcc, $\x02, $\x01";
3752
0
      break;
3753
0
    }
3754
19
    if (MCInst_getNumOperands(MI) == 3 &&
3755
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3756
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3757
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3758
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3759
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3760
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3761
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3762
0
      AsmString = "movn %xcc, $\x02, $\x01";
3763
0
      break;
3764
0
    }
3765
19
    if (MCInst_getNumOperands(MI) == 3 &&
3766
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3767
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3768
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3769
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3770
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3771
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3772
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3773
0
      AsmString = "movne %xcc, $\x02, $\x01";
3774
0
      break;
3775
0
    }
3776
19
    if (MCInst_getNumOperands(MI) == 3 &&
3777
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3778
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3779
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3780
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3781
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3782
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3783
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3784
0
      AsmString = "move %xcc, $\x02, $\x01";
3785
0
      break;
3786
0
    }
3787
19
    if (MCInst_getNumOperands(MI) == 3 &&
3788
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3789
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3790
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3791
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3792
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3793
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3794
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3795
0
      AsmString = "movg %xcc, $\x02, $\x01";
3796
0
      break;
3797
0
    }
3798
19
    if (MCInst_getNumOperands(MI) == 3 &&
3799
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3800
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3801
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3802
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3803
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3804
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3805
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3806
0
      AsmString = "movle %xcc, $\x02, $\x01";
3807
0
      break;
3808
0
    }
3809
19
    if (MCInst_getNumOperands(MI) == 3 &&
3810
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3811
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3812
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3813
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3814
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3815
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3816
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3817
0
      AsmString = "movge %xcc, $\x02, $\x01";
3818
0
      break;
3819
0
    }
3820
19
    if (MCInst_getNumOperands(MI) == 3 &&
3821
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3822
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3823
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3824
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3825
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3826
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3827
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3828
0
      AsmString = "movl %xcc, $\x02, $\x01";
3829
0
      break;
3830
0
    }
3831
19
    if (MCInst_getNumOperands(MI) == 3 &&
3832
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3833
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3834
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3835
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3836
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3837
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3838
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3839
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3840
0
      break;
3841
0
    }
3842
19
    if (MCInst_getNumOperands(MI) == 3 &&
3843
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3844
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3845
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3846
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3847
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3848
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3849
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3850
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3851
0
      break;
3852
0
    }
3853
19
    if (MCInst_getNumOperands(MI) == 3 &&
3854
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3855
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3856
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3857
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3858
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3859
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3860
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3861
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3862
0
      break;
3863
0
    }
3864
19
    if (MCInst_getNumOperands(MI) == 3 &&
3865
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3866
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3867
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3868
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3869
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3870
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3871
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3872
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3873
0
      break;
3874
0
    }
3875
19
    if (MCInst_getNumOperands(MI) == 3 &&
3876
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3877
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3878
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3879
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3880
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3881
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3882
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3883
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3884
0
      break;
3885
0
    }
3886
19
    if (MCInst_getNumOperands(MI) == 3 &&
3887
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3888
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3889
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3890
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3891
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3892
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3893
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3894
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3895
0
      break;
3896
0
    }
3897
19
    if (MCInst_getNumOperands(MI) == 3 &&
3898
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3899
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3900
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3901
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3902
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3903
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3904
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3905
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3906
0
      break;
3907
0
    }
3908
19
    if (MCInst_getNumOperands(MI) == 3 &&
3909
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3910
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3911
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3912
19
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3913
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3914
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3915
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3916
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3917
0
      break;
3918
0
    }
3919
19
    return NULL;
3920
54
  case SP_ORri:
3921
54
    if (MCInst_getNumOperands(MI) == 3 &&
3922
54
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3923
54
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3924
54
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3925
      // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3926
21
      AsmString = "mov $\x03, $\x01";
3927
21
      break;
3928
21
    }
3929
33
    return NULL;
3930
110
  case SP_ORrr:
3931
110
    if (MCInst_getNumOperands(MI) == 3 &&
3932
110
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3933
110
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3934
110
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3935
110
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3936
110
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3937
      // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3938
41
      AsmString = "mov $\x03, $\x01";
3939
41
      break;
3940
41
    }
3941
69
    return NULL;
3942
88
  case SP_RESTORErr:
3943
88
    if (MCInst_getNumOperands(MI) == 3 &&
3944
88
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3945
88
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3946
88
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3947
      // (RESTORErr G0, G0, G0)
3948
15
      AsmString = "restore";
3949
15
      break;
3950
15
    }
3951
73
    return NULL;
3952
0
  case SP_RET:
3953
0
    if (MCInst_getNumOperands(MI) == 1 &&
3954
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3955
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3956
      // (RET 8)
3957
0
      AsmString = "ret";
3958
0
      break;
3959
0
    }
3960
0
    return NULL;
3961
0
  case SP_RETL:
3962
0
    if (MCInst_getNumOperands(MI) == 1 &&
3963
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3964
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3965
      // (RETL 8)
3966
0
      AsmString = "retl";
3967
0
      break;
3968
0
    }
3969
0
    return NULL;
3970
1.64k
  case SP_TXCCri:
3971
1.64k
    if (MCInst_getNumOperands(MI) == 3 &&
3972
1.64k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3973
1.64k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3974
1.64k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3975
1.64k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3976
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3977
11
      AsmString = "ta %xcc, $\x01 + $\x02";
3978
11
      break;
3979
11
    }
3980
1.63k
    if (MCInst_getNumOperands(MI) == 3 &&
3981
1.63k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3982
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3983
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3984
      // (TXCCri G0, i32imm:$imm, 8)
3985
0
      AsmString = "ta %xcc, $\x02";
3986
0
      break;
3987
0
    }
3988
1.63k
    if (MCInst_getNumOperands(MI) == 3 &&
3989
1.63k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3990
1.63k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3991
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3992
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3993
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3994
41
      AsmString = "tn %xcc, $\x01 + $\x02";
3995
41
      break;
3996
41
    }
3997
1.59k
    if (MCInst_getNumOperands(MI) == 3 &&
3998
1.59k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3999
1.59k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4000
1.59k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4001
      // (TXCCri G0, i32imm:$imm, 0)
4002
0
      AsmString = "tn %xcc, $\x02";
4003
0
      break;
4004
0
    }
4005
1.59k
    if (MCInst_getNumOperands(MI) == 3 &&
4006
1.59k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4007
1.59k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4008
1.59k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4009
1.59k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4010
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4011
53
      AsmString = "tne %xcc, $\x01 + $\x02";
4012
53
      break;
4013
53
    }
4014
1.53k
    if (MCInst_getNumOperands(MI) == 3 &&
4015
1.53k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4016
1.53k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4017
1.53k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4018
      // (TXCCri G0, i32imm:$imm, 9)
4019
0
      AsmString = "tne %xcc, $\x02";
4020
0
      break;
4021
0
    }
4022
1.53k
    if (MCInst_getNumOperands(MI) == 3 &&
4023
1.53k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4024
1.53k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4025
1.53k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4026
1.53k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4027
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4028
13
      AsmString = "te %xcc, $\x01 + $\x02";
4029
13
      break;
4030
13
    }
4031
1.52k
    if (MCInst_getNumOperands(MI) == 3 &&
4032
1.52k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4033
1.52k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4034
1.52k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4035
      // (TXCCri G0, i32imm:$imm, 1)
4036
0
      AsmString = "te %xcc, $\x02";
4037
0
      break;
4038
0
    }
4039
1.52k
    if (MCInst_getNumOperands(MI) == 3 &&
4040
1.52k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4041
1.52k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4042
1.52k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4043
1.52k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4044
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4045
129
      AsmString = "tg %xcc, $\x01 + $\x02";
4046
129
      break;
4047
129
    }
4048
1.39k
    if (MCInst_getNumOperands(MI) == 3 &&
4049
1.39k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4050
1.39k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4051
1.39k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4052
      // (TXCCri G0, i32imm:$imm, 10)
4053
0
      AsmString = "tg %xcc, $\x02";
4054
0
      break;
4055
0
    }
4056
1.39k
    if (MCInst_getNumOperands(MI) == 3 &&
4057
1.39k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4058
1.39k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4059
1.39k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4060
1.39k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4061
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4062
34
      AsmString = "tle %xcc, $\x01 + $\x02";
4063
34
      break;
4064
34
    }
4065
1.36k
    if (MCInst_getNumOperands(MI) == 3 &&
4066
1.36k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4067
1.36k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4068
1.36k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4069
      // (TXCCri G0, i32imm:$imm, 2)
4070
0
      AsmString = "tle %xcc, $\x02";
4071
0
      break;
4072
0
    }
4073
1.36k
    if (MCInst_getNumOperands(MI) == 3 &&
4074
1.36k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4075
1.36k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4076
1.36k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4077
1.36k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4078
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4079
10
      AsmString = "tge %xcc, $\x01 + $\x02";
4080
10
      break;
4081
10
    }
4082
1.35k
    if (MCInst_getNumOperands(MI) == 3 &&
4083
1.35k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4084
1.35k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4085
1.35k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4086
      // (TXCCri G0, i32imm:$imm, 11)
4087
0
      AsmString = "tge %xcc, $\x02";
4088
0
      break;
4089
0
    }
4090
1.35k
    if (MCInst_getNumOperands(MI) == 3 &&
4091
1.35k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4092
1.35k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4093
1.35k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4094
1.35k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4095
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4096
19
      AsmString = "tl %xcc, $\x01 + $\x02";
4097
19
      break;
4098
19
    }
4099
1.33k
    if (MCInst_getNumOperands(MI) == 3 &&
4100
1.33k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4101
1.33k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4102
1.33k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4103
      // (TXCCri G0, i32imm:$imm, 3)
4104
0
      AsmString = "tl %xcc, $\x02";
4105
0
      break;
4106
0
    }
4107
1.33k
    if (MCInst_getNumOperands(MI) == 3 &&
4108
1.33k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4109
1.33k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4110
1.33k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4111
1.33k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4112
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4113
10
      AsmString = "tgu %xcc, $\x01 + $\x02";
4114
10
      break;
4115
10
    }
4116
1.32k
    if (MCInst_getNumOperands(MI) == 3 &&
4117
1.32k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4118
1.32k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4119
1.32k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4120
      // (TXCCri G0, i32imm:$imm, 12)
4121
0
      AsmString = "tgu %xcc, $\x02";
4122
0
      break;
4123
0
    }
4124
1.32k
    if (MCInst_getNumOperands(MI) == 3 &&
4125
1.32k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4126
1.32k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4127
1.32k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4128
1.32k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4129
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4130
396
      AsmString = "tleu %xcc, $\x01 + $\x02";
4131
396
      break;
4132
396
    }
4133
926
    if (MCInst_getNumOperands(MI) == 3 &&
4134
926
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4135
926
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4136
926
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4137
      // (TXCCri G0, i32imm:$imm, 4)
4138
0
      AsmString = "tleu %xcc, $\x02";
4139
0
      break;
4140
0
    }
4141
926
    if (MCInst_getNumOperands(MI) == 3 &&
4142
926
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4143
926
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4144
926
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4145
926
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4146
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4147
113
      AsmString = "tcc %xcc, $\x01 + $\x02";
4148
113
      break;
4149
113
    }
4150
813
    if (MCInst_getNumOperands(MI) == 3 &&
4151
813
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4152
813
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4153
813
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4154
      // (TXCCri G0, i32imm:$imm, 13)
4155
0
      AsmString = "tcc %xcc, $\x02";
4156
0
      break;
4157
0
    }
4158
813
    if (MCInst_getNumOperands(MI) == 3 &&
4159
813
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4160
813
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4161
813
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4162
813
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4163
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4164
134
      AsmString = "tcs %xcc, $\x01 + $\x02";
4165
134
      break;
4166
134
    }
4167
679
    if (MCInst_getNumOperands(MI) == 3 &&
4168
679
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4169
679
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4170
679
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4171
      // (TXCCri G0, i32imm:$imm, 5)
4172
0
      AsmString = "tcs %xcc, $\x02";
4173
0
      break;
4174
0
    }
4175
679
    if (MCInst_getNumOperands(MI) == 3 &&
4176
679
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4177
679
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4178
679
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4179
679
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4180
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4181
389
      AsmString = "tpos %xcc, $\x01 + $\x02";
4182
389
      break;
4183
389
    }
4184
290
    if (MCInst_getNumOperands(MI) == 3 &&
4185
290
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4186
290
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4187
290
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4188
      // (TXCCri G0, i32imm:$imm, 14)
4189
0
      AsmString = "tpos %xcc, $\x02";
4190
0
      break;
4191
0
    }
4192
290
    if (MCInst_getNumOperands(MI) == 3 &&
4193
290
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4194
290
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4195
290
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4196
290
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4197
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4198
61
      AsmString = "tneg %xcc, $\x01 + $\x02";
4199
61
      break;
4200
61
    }
4201
229
    if (MCInst_getNumOperands(MI) == 3 &&
4202
229
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4203
229
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4204
229
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4205
      // (TXCCri G0, i32imm:$imm, 6)
4206
0
      AsmString = "tneg %xcc, $\x02";
4207
0
      break;
4208
0
    }
4209
229
    if (MCInst_getNumOperands(MI) == 3 &&
4210
229
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4211
229
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4212
229
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4213
229
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4214
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4215
105
      AsmString = "tvc %xcc, $\x01 + $\x02";
4216
105
      break;
4217
105
    }
4218
124
    if (MCInst_getNumOperands(MI) == 3 &&
4219
124
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4220
124
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4221
124
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4222
      // (TXCCri G0, i32imm:$imm, 15)
4223
0
      AsmString = "tvc %xcc, $\x02";
4224
0
      break;
4225
0
    }
4226
124
    if (MCInst_getNumOperands(MI) == 3 &&
4227
124
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4228
124
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4229
124
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4230
124
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4231
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4232
124
      AsmString = "tvs %xcc, $\x01 + $\x02";
4233
124
      break;
4234
124
    }
4235
0
    if (MCInst_getNumOperands(MI) == 3 &&
4236
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4237
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4238
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4239
      // (TXCCri G0, i32imm:$imm, 7)
4240
0
      AsmString = "tvs %xcc, $\x02";
4241
0
      break;
4242
0
    }
4243
0
    return NULL;
4244
1.81k
  case SP_TXCCrr:
4245
1.81k
    if (MCInst_getNumOperands(MI) == 3 &&
4246
1.81k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4247
1.81k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4248
1.81k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4249
1.81k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4250
1.81k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4251
1.81k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4252
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4253
29
      AsmString = "ta %xcc, $\x01 + $\x02";
4254
29
      break;
4255
29
    }
4256
1.78k
    if (MCInst_getNumOperands(MI) == 3 &&
4257
1.78k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4258
1.78k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4259
1.78k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4260
1.78k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4261
1.78k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4262
      // (TXCCrr G0, IntRegs:$rs2, 8)
4263
0
      AsmString = "ta %xcc, $\x02";
4264
0
      break;
4265
0
    }
4266
1.78k
    if (MCInst_getNumOperands(MI) == 3 &&
4267
1.78k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4268
1.78k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4269
1.78k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4270
1.78k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4271
1.78k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4272
1.78k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4273
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4274
22
      AsmString = "tn %xcc, $\x01 + $\x02";
4275
22
      break;
4276
22
    }
4277
1.76k
    if (MCInst_getNumOperands(MI) == 3 &&
4278
1.76k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4279
1.76k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4280
1.76k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4281
1.76k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4282
1.76k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4283
      // (TXCCrr G0, IntRegs:$rs2, 0)
4284
0
      AsmString = "tn %xcc, $\x02";
4285
0
      break;
4286
0
    }
4287
1.76k
    if (MCInst_getNumOperands(MI) == 3 &&
4288
1.76k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4289
1.76k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4290
1.76k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4291
1.76k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4292
1.76k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4293
1.76k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4294
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4295
19
      AsmString = "tne %xcc, $\x01 + $\x02";
4296
19
      break;
4297
19
    }
4298
1.74k
    if (MCInst_getNumOperands(MI) == 3 &&
4299
1.74k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4300
1.74k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4301
1.74k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4302
1.74k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4303
1.74k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4304
      // (TXCCrr G0, IntRegs:$rs2, 9)
4305
0
      AsmString = "tne %xcc, $\x02";
4306
0
      break;
4307
0
    }
4308
1.74k
    if (MCInst_getNumOperands(MI) == 3 &&
4309
1.74k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4310
1.74k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4311
1.74k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4312
1.74k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4313
1.74k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4314
1.74k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4315
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4316
11
      AsmString = "te %xcc, $\x01 + $\x02";
4317
11
      break;
4318
11
    }
4319
1.73k
    if (MCInst_getNumOperands(MI) == 3 &&
4320
1.73k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4321
1.73k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4322
1.73k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4323
1.73k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4324
1.73k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4325
      // (TXCCrr G0, IntRegs:$rs2, 1)
4326
0
      AsmString = "te %xcc, $\x02";
4327
0
      break;
4328
0
    }
4329
1.73k
    if (MCInst_getNumOperands(MI) == 3 &&
4330
1.73k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4331
1.73k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4332
1.73k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4333
1.73k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4334
1.73k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4335
1.73k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4336
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4337
68
      AsmString = "tg %xcc, $\x01 + $\x02";
4338
68
      break;
4339
68
    }
4340
1.66k
    if (MCInst_getNumOperands(MI) == 3 &&
4341
1.66k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4342
1.66k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4343
1.66k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4344
1.66k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4345
1.66k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4346
      // (TXCCrr G0, IntRegs:$rs2, 10)
4347
0
      AsmString = "tg %xcc, $\x02";
4348
0
      break;
4349
0
    }
4350
1.66k
    if (MCInst_getNumOperands(MI) == 3 &&
4351
1.66k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4352
1.66k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4353
1.66k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4354
1.66k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4355
1.66k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4356
1.66k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4357
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4358
19
      AsmString = "tle %xcc, $\x01 + $\x02";
4359
19
      break;
4360
19
    }
4361
1.64k
    if (MCInst_getNumOperands(MI) == 3 &&
4362
1.64k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4363
1.64k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4364
1.64k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4365
1.64k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4366
1.64k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4367
      // (TXCCrr G0, IntRegs:$rs2, 2)
4368
0
      AsmString = "tle %xcc, $\x02";
4369
0
      break;
4370
0
    }
4371
1.64k
    if (MCInst_getNumOperands(MI) == 3 &&
4372
1.64k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4373
1.64k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4374
1.64k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4375
1.64k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4376
1.64k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4377
1.64k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4378
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4379
36
      AsmString = "tge %xcc, $\x01 + $\x02";
4380
36
      break;
4381
36
    }
4382
1.61k
    if (MCInst_getNumOperands(MI) == 3 &&
4383
1.61k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4384
1.61k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4385
1.61k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4386
1.61k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4387
1.61k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4388
      // (TXCCrr G0, IntRegs:$rs2, 11)
4389
0
      AsmString = "tge %xcc, $\x02";
4390
0
      break;
4391
0
    }
4392
1.61k
    if (MCInst_getNumOperands(MI) == 3 &&
4393
1.61k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4394
1.61k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4395
1.61k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4396
1.61k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4397
1.61k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4398
1.61k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4399
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4400
34
      AsmString = "tl %xcc, $\x01 + $\x02";
4401
34
      break;
4402
34
    }
4403
1.57k
    if (MCInst_getNumOperands(MI) == 3 &&
4404
1.57k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4405
1.57k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4406
1.57k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4407
1.57k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4408
1.57k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4409
      // (TXCCrr G0, IntRegs:$rs2, 3)
4410
0
      AsmString = "tl %xcc, $\x02";
4411
0
      break;
4412
0
    }
4413
1.57k
    if (MCInst_getNumOperands(MI) == 3 &&
4414
1.57k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4415
1.57k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4416
1.57k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4417
1.57k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4418
1.57k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4419
1.57k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4420
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4421
741
      AsmString = "tgu %xcc, $\x01 + $\x02";
4422
741
      break;
4423
741
    }
4424
835
    if (MCInst_getNumOperands(MI) == 3 &&
4425
835
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4426
835
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4427
835
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4428
835
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4429
835
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4430
      // (TXCCrr G0, IntRegs:$rs2, 12)
4431
0
      AsmString = "tgu %xcc, $\x02";
4432
0
      break;
4433
0
    }
4434
835
    if (MCInst_getNumOperands(MI) == 3 &&
4435
835
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4436
835
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4437
835
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4438
835
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4439
835
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4440
835
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4441
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4442
155
      AsmString = "tleu %xcc, $\x01 + $\x02";
4443
155
      break;
4444
155
    }
4445
680
    if (MCInst_getNumOperands(MI) == 3 &&
4446
680
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4447
680
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4448
680
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4449
680
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4450
680
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4451
      // (TXCCrr G0, IntRegs:$rs2, 4)
4452
0
      AsmString = "tleu %xcc, $\x02";
4453
0
      break;
4454
0
    }
4455
680
    if (MCInst_getNumOperands(MI) == 3 &&
4456
680
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4457
680
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4458
680
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4459
680
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4460
680
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4461
680
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4462
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4463
41
      AsmString = "tcc %xcc, $\x01 + $\x02";
4464
41
      break;
4465
41
    }
4466
639
    if (MCInst_getNumOperands(MI) == 3 &&
4467
639
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4468
639
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4469
639
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4470
639
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4471
639
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4472
      // (TXCCrr G0, IntRegs:$rs2, 13)
4473
0
      AsmString = "tcc %xcc, $\x02";
4474
0
      break;
4475
0
    }
4476
639
    if (MCInst_getNumOperands(MI) == 3 &&
4477
639
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4478
639
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4479
639
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4480
639
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4481
639
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4482
639
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4483
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4484
49
      AsmString = "tcs %xcc, $\x01 + $\x02";
4485
49
      break;
4486
49
    }
4487
590
    if (MCInst_getNumOperands(MI) == 3 &&
4488
590
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4489
590
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4490
590
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4491
590
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4492
590
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4493
      // (TXCCrr G0, IntRegs:$rs2, 5)
4494
0
      AsmString = "tcs %xcc, $\x02";
4495
0
      break;
4496
0
    }
4497
590
    if (MCInst_getNumOperands(MI) == 3 &&
4498
590
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4499
590
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4500
590
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4501
590
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4502
590
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4503
590
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4504
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4505
36
      AsmString = "tpos %xcc, $\x01 + $\x02";
4506
36
      break;
4507
36
    }
4508
554
    if (MCInst_getNumOperands(MI) == 3 &&
4509
554
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4510
554
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4511
554
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4512
554
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4513
554
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4514
      // (TXCCrr G0, IntRegs:$rs2, 14)
4515
0
      AsmString = "tpos %xcc, $\x02";
4516
0
      break;
4517
0
    }
4518
554
    if (MCInst_getNumOperands(MI) == 3 &&
4519
554
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4520
554
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4521
554
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4522
554
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4523
554
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4524
554
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4525
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4526
21
      AsmString = "tneg %xcc, $\x01 + $\x02";
4527
21
      break;
4528
21
    }
4529
533
    if (MCInst_getNumOperands(MI) == 3 &&
4530
533
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4531
533
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4532
533
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4533
533
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4534
533
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4535
      // (TXCCrr G0, IntRegs:$rs2, 6)
4536
0
      AsmString = "tneg %xcc, $\x02";
4537
0
      break;
4538
0
    }
4539
533
    if (MCInst_getNumOperands(MI) == 3 &&
4540
533
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4541
533
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4542
533
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4543
533
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4544
533
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4545
533
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4546
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4547
191
      AsmString = "tvc %xcc, $\x01 + $\x02";
4548
191
      break;
4549
191
    }
4550
342
    if (MCInst_getNumOperands(MI) == 3 &&
4551
342
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4552
342
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4553
342
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4554
342
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4555
342
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4556
      // (TXCCrr G0, IntRegs:$rs2, 15)
4557
0
      AsmString = "tvc %xcc, $\x02";
4558
0
      break;
4559
0
    }
4560
342
    if (MCInst_getNumOperands(MI) == 3 &&
4561
342
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4562
342
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4563
342
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4564
342
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4565
342
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4566
342
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4567
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4568
342
      AsmString = "tvs %xcc, $\x01 + $\x02";
4569
342
      break;
4570
342
    }
4571
0
    if (MCInst_getNumOperands(MI) == 3 &&
4572
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4573
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4574
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4575
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4576
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4577
      // (TXCCrr G0, IntRegs:$rs2, 7)
4578
0
      AsmString = "tvs %xcc, $\x02";
4579
0
      break;
4580
0
    }
4581
0
    return NULL;
4582
586
  case SP_V9FCMPD:
4583
586
    if (MCInst_getNumOperands(MI) == 3 &&
4584
586
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4585
586
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4586
586
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4587
586
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4588
586
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4589
      // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4590
240
      AsmString = "fcmpd $\x02, $\x03";
4591
240
      break;
4592
240
    }
4593
346
    return NULL;
4594
41
  case SP_V9FCMPED:
4595
41
    if (MCInst_getNumOperands(MI) == 3 &&
4596
41
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4597
41
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4598
41
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4599
41
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4600
41
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4601
      // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4602
22
      AsmString = "fcmped $\x02, $\x03";
4603
22
      break;
4604
22
    }
4605
19
    return NULL;
4606
367
  case SP_V9FCMPEQ:
4607
367
    if (MCInst_getNumOperands(MI) == 3 &&
4608
367
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4609
367
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4610
367
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4611
367
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4612
367
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4613
      // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4614
120
      AsmString = "fcmpeq $\x02, $\x03";
4615
120
      break;
4616
120
    }
4617
247
    return NULL;
4618
103
  case SP_V9FCMPES:
4619
103
    if (MCInst_getNumOperands(MI) == 3 &&
4620
103
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4621
103
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4622
103
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4623
103
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4624
103
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4625
      // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4626
84
      AsmString = "fcmpes $\x02, $\x03";
4627
84
      break;
4628
84
    }
4629
19
    return NULL;
4630
74
  case SP_V9FCMPQ:
4631
74
    if (MCInst_getNumOperands(MI) == 3 &&
4632
74
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4633
74
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4634
74
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4635
74
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4636
74
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4637
      // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4638
30
      AsmString = "fcmpq $\x02, $\x03";
4639
30
      break;
4640
30
    }
4641
44
    return NULL;
4642
61
  case SP_V9FCMPS:
4643
61
    if (MCInst_getNumOperands(MI) == 3 &&
4644
61
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4645
61
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4646
61
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4647
61
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4648
61
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4649
      // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4650
24
      AsmString = "fcmps $\x02, $\x03";
4651
24
      break;
4652
24
    }
4653
37
    return NULL;
4654
33
  case SP_V9FMOVD_FCC:
4655
33
    if (MCInst_getNumOperands(MI) == 4 &&
4656
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4657
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4658
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4659
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4660
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4661
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4662
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4663
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4664
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4665
0
      AsmString = "fmovda $\x02, $\x03, $\x01";
4666
0
      break;
4667
0
    }
4668
33
    if (MCInst_getNumOperands(MI) == 4 &&
4669
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4670
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4671
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4672
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4673
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4674
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4675
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4676
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4677
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4678
0
      AsmString = "fmovdn $\x02, $\x03, $\x01";
4679
0
      break;
4680
0
    }
4681
33
    if (MCInst_getNumOperands(MI) == 4 &&
4682
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4683
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4684
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4685
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4686
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4687
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4688
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4689
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4690
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4691
0
      AsmString = "fmovdu $\x02, $\x03, $\x01";
4692
0
      break;
4693
0
    }
4694
33
    if (MCInst_getNumOperands(MI) == 4 &&
4695
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4696
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4697
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4698
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4699
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4700
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4701
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4702
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4703
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4704
0
      AsmString = "fmovdg $\x02, $\x03, $\x01";
4705
0
      break;
4706
0
    }
4707
33
    if (MCInst_getNumOperands(MI) == 4 &&
4708
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4709
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4710
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4711
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4712
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4713
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4714
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4715
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4716
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4717
0
      AsmString = "fmovdug $\x02, $\x03, $\x01";
4718
0
      break;
4719
0
    }
4720
33
    if (MCInst_getNumOperands(MI) == 4 &&
4721
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4722
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4723
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4724
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4725
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4726
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4727
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4728
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4729
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4730
0
      AsmString = "fmovdl $\x02, $\x03, $\x01";
4731
0
      break;
4732
0
    }
4733
33
    if (MCInst_getNumOperands(MI) == 4 &&
4734
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4735
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4736
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4737
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4738
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4739
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4740
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4741
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4742
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4743
0
      AsmString = "fmovdul $\x02, $\x03, $\x01";
4744
0
      break;
4745
0
    }
4746
33
    if (MCInst_getNumOperands(MI) == 4 &&
4747
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4748
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4749
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4750
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4751
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4752
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4753
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4754
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4755
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4756
0
      AsmString = "fmovdlg $\x02, $\x03, $\x01";
4757
0
      break;
4758
0
    }
4759
33
    if (MCInst_getNumOperands(MI) == 4 &&
4760
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4761
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4762
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4763
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4764
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4765
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4766
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4767
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4768
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4769
0
      AsmString = "fmovdne $\x02, $\x03, $\x01";
4770
0
      break;
4771
0
    }
4772
33
    if (MCInst_getNumOperands(MI) == 4 &&
4773
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4774
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4775
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4776
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4777
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4778
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4779
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4780
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4781
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4782
0
      AsmString = "fmovde $\x02, $\x03, $\x01";
4783
0
      break;
4784
0
    }
4785
33
    if (MCInst_getNumOperands(MI) == 4 &&
4786
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4787
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4788
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4789
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4790
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4791
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4792
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4793
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4794
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4795
0
      AsmString = "fmovdue $\x02, $\x03, $\x01";
4796
0
      break;
4797
0
    }
4798
33
    if (MCInst_getNumOperands(MI) == 4 &&
4799
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4800
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4801
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4802
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4803
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4804
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4805
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4806
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4807
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4808
0
      AsmString = "fmovdge $\x02, $\x03, $\x01";
4809
0
      break;
4810
0
    }
4811
33
    if (MCInst_getNumOperands(MI) == 4 &&
4812
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4813
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4814
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4815
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4816
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4817
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4818
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4819
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4820
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4821
0
      AsmString = "fmovduge $\x02, $\x03, $\x01";
4822
0
      break;
4823
0
    }
4824
33
    if (MCInst_getNumOperands(MI) == 4 &&
4825
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4826
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4827
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4828
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4829
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4830
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4831
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4832
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4833
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4834
0
      AsmString = "fmovdle $\x02, $\x03, $\x01";
4835
0
      break;
4836
0
    }
4837
33
    if (MCInst_getNumOperands(MI) == 4 &&
4838
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4839
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4840
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4841
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4842
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4843
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4844
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4845
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4846
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4847
0
      AsmString = "fmovdule $\x02, $\x03, $\x01";
4848
0
      break;
4849
0
    }
4850
33
    if (MCInst_getNumOperands(MI) == 4 &&
4851
33
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4852
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4853
33
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4854
33
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4855
33
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4856
33
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4857
33
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4858
33
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4859
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4860
0
      AsmString = "fmovdo $\x02, $\x03, $\x01";
4861
0
      break;
4862
0
    }
4863
33
    return NULL;
4864
14
  case SP_V9FMOVQ_FCC:
4865
14
    if (MCInst_getNumOperands(MI) == 4 &&
4866
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4867
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4868
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4869
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4870
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4871
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4872
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4873
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4874
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4875
0
      AsmString = "fmovqa $\x02, $\x03, $\x01";
4876
0
      break;
4877
0
    }
4878
14
    if (MCInst_getNumOperands(MI) == 4 &&
4879
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4880
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4881
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4882
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4883
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4884
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4885
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4886
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4887
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4888
0
      AsmString = "fmovqn $\x02, $\x03, $\x01";
4889
0
      break;
4890
0
    }
4891
14
    if (MCInst_getNumOperands(MI) == 4 &&
4892
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4893
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4894
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4895
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4896
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4897
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4898
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4899
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4900
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4901
0
      AsmString = "fmovqu $\x02, $\x03, $\x01";
4902
0
      break;
4903
0
    }
4904
14
    if (MCInst_getNumOperands(MI) == 4 &&
4905
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4906
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4907
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4908
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4909
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4910
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4911
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4912
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4913
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4914
0
      AsmString = "fmovqg $\x02, $\x03, $\x01";
4915
0
      break;
4916
0
    }
4917
14
    if (MCInst_getNumOperands(MI) == 4 &&
4918
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4919
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4920
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4921
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4922
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4923
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4924
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4925
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4926
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4927
0
      AsmString = "fmovqug $\x02, $\x03, $\x01";
4928
0
      break;
4929
0
    }
4930
14
    if (MCInst_getNumOperands(MI) == 4 &&
4931
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4932
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4933
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4934
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4935
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4936
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4937
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4938
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4939
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4940
0
      AsmString = "fmovql $\x02, $\x03, $\x01";
4941
0
      break;
4942
0
    }
4943
14
    if (MCInst_getNumOperands(MI) == 4 &&
4944
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4945
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4946
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4947
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4948
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4949
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4950
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4951
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4952
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4953
0
      AsmString = "fmovqul $\x02, $\x03, $\x01";
4954
0
      break;
4955
0
    }
4956
14
    if (MCInst_getNumOperands(MI) == 4 &&
4957
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4958
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4959
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4960
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4961
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4962
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4963
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4964
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4965
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4966
0
      AsmString = "fmovqlg $\x02, $\x03, $\x01";
4967
0
      break;
4968
0
    }
4969
14
    if (MCInst_getNumOperands(MI) == 4 &&
4970
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4971
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4972
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4973
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4974
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4975
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4976
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4977
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4978
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4979
0
      AsmString = "fmovqne $\x02, $\x03, $\x01";
4980
0
      break;
4981
0
    }
4982
14
    if (MCInst_getNumOperands(MI) == 4 &&
4983
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4984
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4985
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4986
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4987
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4988
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4989
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4990
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4991
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4992
0
      AsmString = "fmovqe $\x02, $\x03, $\x01";
4993
0
      break;
4994
0
    }
4995
14
    if (MCInst_getNumOperands(MI) == 4 &&
4996
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4997
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4998
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4999
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5000
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5001
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5002
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5003
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5004
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5005
0
      AsmString = "fmovque $\x02, $\x03, $\x01";
5006
0
      break;
5007
0
    }
5008
14
    if (MCInst_getNumOperands(MI) == 4 &&
5009
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5010
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5011
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5012
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5013
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5014
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5015
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5016
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5017
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5018
0
      AsmString = "fmovqge $\x02, $\x03, $\x01";
5019
0
      break;
5020
0
    }
5021
14
    if (MCInst_getNumOperands(MI) == 4 &&
5022
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5023
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5024
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5025
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5026
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5027
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5028
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5029
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5030
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5031
0
      AsmString = "fmovquge $\x02, $\x03, $\x01";
5032
0
      break;
5033
0
    }
5034
14
    if (MCInst_getNumOperands(MI) == 4 &&
5035
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5036
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5037
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5038
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5039
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5040
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5041
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5042
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5043
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5044
0
      AsmString = "fmovqle $\x02, $\x03, $\x01";
5045
0
      break;
5046
0
    }
5047
14
    if (MCInst_getNumOperands(MI) == 4 &&
5048
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5049
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5050
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5051
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5052
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5053
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5054
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5055
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5056
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5057
0
      AsmString = "fmovqule $\x02, $\x03, $\x01";
5058
0
      break;
5059
0
    }
5060
14
    if (MCInst_getNumOperands(MI) == 4 &&
5061
14
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5062
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5063
14
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5064
14
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5065
14
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5066
14
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5067
14
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5068
14
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5069
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5070
0
      AsmString = "fmovqo $\x02, $\x03, $\x01";
5071
0
      break;
5072
0
    }
5073
14
    return NULL;
5074
20
  case SP_V9FMOVS_FCC:
5075
20
    if (MCInst_getNumOperands(MI) == 4 &&
5076
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5077
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5078
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5079
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5080
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5081
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5082
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5083
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5084
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5085
0
      AsmString = "fmovsa $\x02, $\x03, $\x01";
5086
0
      break;
5087
0
    }
5088
20
    if (MCInst_getNumOperands(MI) == 4 &&
5089
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5090
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5091
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5092
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5093
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5094
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5095
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5096
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5097
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5098
0
      AsmString = "fmovsn $\x02, $\x03, $\x01";
5099
0
      break;
5100
0
    }
5101
20
    if (MCInst_getNumOperands(MI) == 4 &&
5102
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5103
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5104
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5105
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5106
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5107
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5108
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5109
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5110
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5111
0
      AsmString = "fmovsu $\x02, $\x03, $\x01";
5112
0
      break;
5113
0
    }
5114
20
    if (MCInst_getNumOperands(MI) == 4 &&
5115
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5116
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5117
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5118
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5119
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5120
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5121
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5122
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5123
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5124
0
      AsmString = "fmovsg $\x02, $\x03, $\x01";
5125
0
      break;
5126
0
    }
5127
20
    if (MCInst_getNumOperands(MI) == 4 &&
5128
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5129
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5130
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5131
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5132
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5133
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5134
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5135
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5136
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5137
0
      AsmString = "fmovsug $\x02, $\x03, $\x01";
5138
0
      break;
5139
0
    }
5140
20
    if (MCInst_getNumOperands(MI) == 4 &&
5141
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5142
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5143
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5144
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5145
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5146
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5147
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5148
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5149
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5150
0
      AsmString = "fmovsl $\x02, $\x03, $\x01";
5151
0
      break;
5152
0
    }
5153
20
    if (MCInst_getNumOperands(MI) == 4 &&
5154
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5155
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5156
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5157
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5158
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5159
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5160
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5161
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5162
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5163
0
      AsmString = "fmovsul $\x02, $\x03, $\x01";
5164
0
      break;
5165
0
    }
5166
20
    if (MCInst_getNumOperands(MI) == 4 &&
5167
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5168
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5169
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5170
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5171
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5172
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5173
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5174
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5175
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5176
0
      AsmString = "fmovslg $\x02, $\x03, $\x01";
5177
0
      break;
5178
0
    }
5179
20
    if (MCInst_getNumOperands(MI) == 4 &&
5180
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5181
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5182
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5183
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5184
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5185
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5186
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5187
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5188
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5189
0
      AsmString = "fmovsne $\x02, $\x03, $\x01";
5190
0
      break;
5191
0
    }
5192
20
    if (MCInst_getNumOperands(MI) == 4 &&
5193
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5194
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5195
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5196
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5197
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5198
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5199
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5200
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5201
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5202
0
      AsmString = "fmovse $\x02, $\x03, $\x01";
5203
0
      break;
5204
0
    }
5205
20
    if (MCInst_getNumOperands(MI) == 4 &&
5206
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5207
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5208
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5209
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5210
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5211
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5212
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5213
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5214
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5215
0
      AsmString = "fmovsue $\x02, $\x03, $\x01";
5216
0
      break;
5217
0
    }
5218
20
    if (MCInst_getNumOperands(MI) == 4 &&
5219
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5220
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5221
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5222
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5223
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5224
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5225
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5226
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5227
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5228
0
      AsmString = "fmovsge $\x02, $\x03, $\x01";
5229
0
      break;
5230
0
    }
5231
20
    if (MCInst_getNumOperands(MI) == 4 &&
5232
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5233
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5234
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5235
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5236
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5237
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5238
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5239
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5240
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5241
0
      AsmString = "fmovsuge $\x02, $\x03, $\x01";
5242
0
      break;
5243
0
    }
5244
20
    if (MCInst_getNumOperands(MI) == 4 &&
5245
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5246
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5247
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5248
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5249
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5250
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5251
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5252
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5253
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5254
0
      AsmString = "fmovsle $\x02, $\x03, $\x01";
5255
0
      break;
5256
0
    }
5257
20
    if (MCInst_getNumOperands(MI) == 4 &&
5258
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5259
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5260
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5261
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5262
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5263
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5264
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5265
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5266
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5267
0
      AsmString = "fmovsule $\x02, $\x03, $\x01";
5268
0
      break;
5269
0
    }
5270
20
    if (MCInst_getNumOperands(MI) == 4 &&
5271
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5272
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5273
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5274
20
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5275
20
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5276
20
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5277
20
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5278
20
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5279
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5280
0
      AsmString = "fmovso $\x02, $\x03, $\x01";
5281
0
      break;
5282
0
    }
5283
20
    return NULL;
5284
560
  case SP_V9MOVFCCri:
5285
560
    if (MCInst_getNumOperands(MI) == 4 &&
5286
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5287
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5288
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5289
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5290
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5291
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5292
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5293
0
      AsmString = "mova $\x02, $\x03, $\x01";
5294
0
      break;
5295
0
    }
5296
560
    if (MCInst_getNumOperands(MI) == 4 &&
5297
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5298
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5299
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5300
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5301
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5302
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5303
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5304
0
      AsmString = "movn $\x02, $\x03, $\x01";
5305
0
      break;
5306
0
    }
5307
560
    if (MCInst_getNumOperands(MI) == 4 &&
5308
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5309
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5310
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5311
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5312
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5313
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5314
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5315
0
      AsmString = "movu $\x02, $\x03, $\x01";
5316
0
      break;
5317
0
    }
5318
560
    if (MCInst_getNumOperands(MI) == 4 &&
5319
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5320
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5321
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5322
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5323
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5324
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5325
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5326
0
      AsmString = "movg $\x02, $\x03, $\x01";
5327
0
      break;
5328
0
    }
5329
560
    if (MCInst_getNumOperands(MI) == 4 &&
5330
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5331
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5332
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5333
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5334
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5335
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5336
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5337
0
      AsmString = "movug $\x02, $\x03, $\x01";
5338
0
      break;
5339
0
    }
5340
560
    if (MCInst_getNumOperands(MI) == 4 &&
5341
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5342
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5343
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5344
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5345
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5346
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5347
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5348
0
      AsmString = "movl $\x02, $\x03, $\x01";
5349
0
      break;
5350
0
    }
5351
560
    if (MCInst_getNumOperands(MI) == 4 &&
5352
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5353
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5354
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5355
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5356
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5357
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5358
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5359
0
      AsmString = "movul $\x02, $\x03, $\x01";
5360
0
      break;
5361
0
    }
5362
560
    if (MCInst_getNumOperands(MI) == 4 &&
5363
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5364
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5365
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5366
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5367
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5368
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5369
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5370
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5371
0
      break;
5372
0
    }
5373
560
    if (MCInst_getNumOperands(MI) == 4 &&
5374
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5375
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5376
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5377
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5378
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5379
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5380
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5381
0
      AsmString = "movne $\x02, $\x03, $\x01";
5382
0
      break;
5383
0
    }
5384
560
    if (MCInst_getNumOperands(MI) == 4 &&
5385
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5386
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5387
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5388
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5389
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5390
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5391
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5392
0
      AsmString = "move $\x02, $\x03, $\x01";
5393
0
      break;
5394
0
    }
5395
560
    if (MCInst_getNumOperands(MI) == 4 &&
5396
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5397
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5398
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5399
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5400
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5401
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5402
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5403
0
      AsmString = "movue $\x02, $\x03, $\x01";
5404
0
      break;
5405
0
    }
5406
560
    if (MCInst_getNumOperands(MI) == 4 &&
5407
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5408
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5409
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5410
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5411
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5412
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5413
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5414
0
      AsmString = "movge $\x02, $\x03, $\x01";
5415
0
      break;
5416
0
    }
5417
560
    if (MCInst_getNumOperands(MI) == 4 &&
5418
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5419
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5420
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5421
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5422
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5423
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5424
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5425
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5426
0
      break;
5427
0
    }
5428
560
    if (MCInst_getNumOperands(MI) == 4 &&
5429
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5430
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5431
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5432
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5433
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5434
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5435
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5436
0
      AsmString = "movle $\x02, $\x03, $\x01";
5437
0
      break;
5438
0
    }
5439
560
    if (MCInst_getNumOperands(MI) == 4 &&
5440
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5441
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5442
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5443
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5444
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5445
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5446
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5447
0
      AsmString = "movule $\x02, $\x03, $\x01";
5448
0
      break;
5449
0
    }
5450
560
    if (MCInst_getNumOperands(MI) == 4 &&
5451
560
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5452
560
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5453
560
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5454
560
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5455
560
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5456
560
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5457
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5458
0
      AsmString = "movo $\x02, $\x03, $\x01";
5459
0
      break;
5460
0
    }
5461
560
    return NULL;
5462
75
  case SP_V9MOVFCCrr:
5463
75
    if (MCInst_getNumOperands(MI) == 4 &&
5464
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5465
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5466
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5467
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5468
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5469
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5470
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5471
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5472
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5473
0
      AsmString = "mova $\x02, $\x03, $\x01";
5474
0
      break;
5475
0
    }
5476
75
    if (MCInst_getNumOperands(MI) == 4 &&
5477
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5478
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5479
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5480
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5481
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5482
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5483
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5484
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5485
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5486
0
      AsmString = "movn $\x02, $\x03, $\x01";
5487
0
      break;
5488
0
    }
5489
75
    if (MCInst_getNumOperands(MI) == 4 &&
5490
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5491
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5492
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5493
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5494
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5495
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5496
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5497
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5498
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5499
0
      AsmString = "movu $\x02, $\x03, $\x01";
5500
0
      break;
5501
0
    }
5502
75
    if (MCInst_getNumOperands(MI) == 4 &&
5503
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5504
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5505
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5506
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5507
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5508
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5509
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5510
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5511
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5512
0
      AsmString = "movg $\x02, $\x03, $\x01";
5513
0
      break;
5514
0
    }
5515
75
    if (MCInst_getNumOperands(MI) == 4 &&
5516
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5517
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5518
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5519
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5520
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5521
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5522
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5523
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5524
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5525
0
      AsmString = "movug $\x02, $\x03, $\x01";
5526
0
      break;
5527
0
    }
5528
75
    if (MCInst_getNumOperands(MI) == 4 &&
5529
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5530
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5531
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5532
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5533
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5534
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5535
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5536
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5537
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5538
0
      AsmString = "movl $\x02, $\x03, $\x01";
5539
0
      break;
5540
0
    }
5541
75
    if (MCInst_getNumOperands(MI) == 4 &&
5542
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5543
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5544
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5545
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5546
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5547
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5548
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5549
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5550
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5551
0
      AsmString = "movul $\x02, $\x03, $\x01";
5552
0
      break;
5553
0
    }
5554
75
    if (MCInst_getNumOperands(MI) == 4 &&
5555
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5556
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5557
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5558
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5559
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5560
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5561
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5562
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5563
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5564
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5565
0
      break;
5566
0
    }
5567
75
    if (MCInst_getNumOperands(MI) == 4 &&
5568
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5569
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5570
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5571
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5572
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5573
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5574
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5575
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5576
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5577
0
      AsmString = "movne $\x02, $\x03, $\x01";
5578
0
      break;
5579
0
    }
5580
75
    if (MCInst_getNumOperands(MI) == 4 &&
5581
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5582
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5583
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5584
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5585
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5586
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5587
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5588
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5589
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5590
0
      AsmString = "move $\x02, $\x03, $\x01";
5591
0
      break;
5592
0
    }
5593
75
    if (MCInst_getNumOperands(MI) == 4 &&
5594
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5595
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5596
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5597
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5598
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5599
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5600
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5601
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5602
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5603
0
      AsmString = "movue $\x02, $\x03, $\x01";
5604
0
      break;
5605
0
    }
5606
75
    if (MCInst_getNumOperands(MI) == 4 &&
5607
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5608
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5609
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5610
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5611
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5612
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5613
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5614
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5615
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5616
0
      AsmString = "movge $\x02, $\x03, $\x01";
5617
0
      break;
5618
0
    }
5619
75
    if (MCInst_getNumOperands(MI) == 4 &&
5620
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5621
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5622
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5623
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5624
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5625
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5626
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5627
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5628
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5629
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5630
0
      break;
5631
0
    }
5632
75
    if (MCInst_getNumOperands(MI) == 4 &&
5633
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5634
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5635
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5636
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5637
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5638
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5639
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5640
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5641
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5642
0
      AsmString = "movle $\x02, $\x03, $\x01";
5643
0
      break;
5644
0
    }
5645
75
    if (MCInst_getNumOperands(MI) == 4 &&
5646
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5647
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5648
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5649
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5650
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5651
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5652
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5653
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5654
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5655
0
      AsmString = "movule $\x02, $\x03, $\x01";
5656
0
      break;
5657
0
    }
5658
75
    if (MCInst_getNumOperands(MI) == 4 &&
5659
75
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5660
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5661
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5662
75
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5663
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5664
75
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5665
75
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5666
75
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5667
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5668
0
      AsmString = "movo $\x02, $\x03, $\x01";
5669
0
      break;
5670
0
    }
5671
75
    return NULL;
5672
47.7k
  }
5673
5674
17.8k
  tmp = cs_strdup(AsmString);
5675
17.8k
  AsmMnem = tmp;
5676
115k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5677
115k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
5678
17.8k
      *AsmOps = '\0';
5679
17.8k
      AsmOps++;
5680
17.8k
      break;
5681
17.8k
    }
5682
115k
  }
5683
17.8k
  SStream_concat0(OS, AsmMnem);
5684
17.8k
  if (*AsmOps) {
5685
17.8k
    SStream_concat0(OS, "\t");
5686
17.8k
    if (strstr(AsmOps, "icc"))
5687
3.92k
      Sparc_addReg(MI, SPARC_REG_ICC);
5688
17.8k
    if (strstr(AsmOps, "xcc"))
5689
5.28k
      Sparc_addReg(MI, SPARC_REG_XCC);
5690
117k
    for (c = AsmOps; *c; c++) {
5691
99.7k
      if (*c == '$') {
5692
25.6k
        c += 1;
5693
25.6k
        if (*c == (char)0xff) {
5694
0
          c += 1;
5695
0
          OpIdx = *c - 1;
5696
0
          c += 1;
5697
0
          PrintMethodIdx = *c - 1;
5698
0
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5699
0
        } else
5700
25.6k
          printOperand(MI, *c - 1, OS);
5701
74.1k
      } else {
5702
74.1k
        SStream_concat(OS, "%c", *c);
5703
74.1k
      }
5704
99.7k
    }
5705
17.8k
  }
5706
17.8k
  return tmp;
5707
47.7k
}
5708
5709
#endif // PRINT_ALIAS_INSTR