/src/capstonev5/arch/Mips/MipsInstPrinter.c

Source (jump to first uncovered line)
//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an Mips MCInst to a .s file.
//
//===----------------------------------------------------------------------===//

/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

#ifdef CAPSTONE_HAS_MIPS

#include <capstone/platform.h>
#include <stdlib.h>
#include <stdio.h>  // debug
#include <string.h>

#include "MipsInstPrinter.h"
#include "../../MCInst.h"
#include "../../utils.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "MipsMapping.h"

#include "MipsInstPrinter.h"

static void printUnsignedImm(MCInst *MI, int opNum, SStream *O);
static char *printAliasInstr(MCInst *MI, SStream *O, void *info);
static char *printAlias(MCInst *MI, SStream *OS);

// These enumeration declarations were originally in MipsInstrInfo.h but
// had to be moved here to avoid circular dependencies between
// LLVMMipsCodeGen and LLVMMipsAsmPrinter.

// Mips Condition Codes
typedef enum Mips_CondCode {
  // To be used with float branch True
  Mips_FCOND_F,
  Mips_FCOND_UN,
  Mips_FCOND_OEQ,
  Mips_FCOND_UEQ,
  Mips_FCOND_OLT,
  Mips_FCOND_ULT,
  Mips_FCOND_OLE,
  Mips_FCOND_ULE,
  Mips_FCOND_SF,
  Mips_FCOND_NGLE,
  Mips_FCOND_SEQ,
  Mips_FCOND_NGL,
  Mips_FCOND_LT,
  Mips_FCOND_NGE,
  Mips_FCOND_LE,
  Mips_FCOND_NGT,

  // To be used with float branch False
  // This conditions have the same mnemonic as the
  // above ones, but are used with a branch False;
  Mips_FCOND_T,
  Mips_FCOND_OR,
  Mips_FCOND_UNE,
  Mips_FCOND_ONE,
  Mips_FCOND_UGE,
  Mips_FCOND_OGE,
  Mips_FCOND_UGT,
  Mips_FCOND_OGT,
  Mips_FCOND_ST,
  Mips_FCOND_GLE,
  Mips_FCOND_SNE,
  Mips_FCOND_GL,
  Mips_FCOND_NLT,
  Mips_FCOND_GE,
  Mips_FCOND_NLE,
  Mips_FCOND_GT
} Mips_CondCode;

#define GET_INSTRINFO_ENUM
#include "MipsGenInstrInfo.inc"

static const char *getRegisterName(unsigned RegNo);
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);

static void set_mem_access(MCInst *MI, bool status)
{
  MI->csh->doing_mem = status;

  if (MI->csh->detail != CS_OPT_ON)
    return;

  if (status) {
    MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM;
    MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID;
    MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0;
  } else {
    // done, create the next operand slot
    MI->flat_insn->detail->mips.op_count++;
  }
}

static bool isReg(MCInst *MI, unsigned OpNo, unsigned R)
{
  return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) &&
      MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R);
}

static const char* MipsFCCToString(Mips_CondCode CC)
{
  switch (CC) {
    default: return 0; // never reach
    case Mips_FCOND_F:
    case Mips_FCOND_T:   return "f";
    case Mips_FCOND_UN:
    case Mips_FCOND_OR:  return "un";
    case Mips_FCOND_OEQ:
    case Mips_FCOND_UNE: return "eq";
    case Mips_FCOND_UEQ:
    case Mips_FCOND_ONE: return "ueq";
    case Mips_FCOND_OLT:
    case Mips_FCOND_UGE: return "olt";
    case Mips_FCOND_ULT:
    case Mips_FCOND_OGE: return "ult";
    case Mips_FCOND_OLE:
    case Mips_FCOND_UGT: return "ole";
    case Mips_FCOND_ULE:
    case Mips_FCOND_OGT: return "ule";
    case Mips_FCOND_SF:
    case Mips_FCOND_ST:  return "sf";
    case Mips_FCOND_NGLE:
    case Mips_FCOND_GLE: return "ngle";
    case Mips_FCOND_SEQ:
    case Mips_FCOND_SNE: return "seq";
    case Mips_FCOND_NGL:
    case Mips_FCOND_GL:  return "ngl";
    case Mips_FCOND_LT:
    case Mips_FCOND_NLT: return "lt";
    case Mips_FCOND_NGE:
    case Mips_FCOND_GE:  return "nge";
    case Mips_FCOND_LE:
    case Mips_FCOND_NLE: return "le";
    case Mips_FCOND_NGT:
    case Mips_FCOND_GT:  return "ngt";
  }
}

static void printRegName(SStream *OS, unsigned RegNo)
{
  SStream_concat(OS, "$%s", getRegisterName(RegNo));
}

void Mips_printInst(MCInst *MI, SStream *O, void *info)
{
  char *mnem;

  switch (MCInst_getOpcode(MI)) {
    default: break;
    case Mips_Save16:
    case Mips_SaveX16:
    case Mips_Restore16:
    case Mips_RestoreX16:
      return;
  }

  // Try to print any aliases first.
  mnem = printAliasInstr(MI, O, info);
  if (!mnem) {
    mnem = printAlias(MI, O);
    if (!mnem) {
      printInstruction(MI, O, NULL);
    }
  }

  if (mnem) {
    // fixup instruction id due to the change in alias instruction
    MCInst_setOpcodePub(MI, Mips_map_insn(mnem));
    cs_mem_free(mnem);
  }
}

static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op;

  if (OpNo >= MI->size)
    return;

  Op = MCInst_getOperand(MI, OpNo);
  if (MCOperand_isReg(Op)) {
    unsigned int reg = MCOperand_getReg(Op);
    printRegName(O, reg);
    reg = Mips_map_register(reg);
    if (MI->csh->detail) {
      if (MI->csh->doing_mem) {
        MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg;
      } else {
        MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG;
        MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg;
        MI->flat_insn->detail->mips.op_count++;
      }
    }
  } else if (MCOperand_isImm(Op)) {
    int64_t imm = MCOperand_getImm(Op);
    if (MI->csh->doing_mem) {
      if (imm) { // only print Imm offset if it is not 0
        printInt64(O, imm);
      }
      if (MI->csh->detail)
        MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm;
    } else {
      printInt64(O, imm);

      if (MI->csh->detail) {
        MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
        MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
        MI->flat_insn->detail->mips.op_count++;
      }
    }
  }
}

static void printUnsignedImm(MCInst *MI, int opNum, SStream *O)
{
  MCOperand *MO = MCInst_getOperand(MI, opNum);
  if (MCOperand_isImm(MO)) {
    int64_t imm = MCOperand_getImm(MO);
    printInt64(O, imm);

    if (MI->csh->detail) {
      MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
      MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm;
      MI->flat_insn->detail->mips.op_count++;
    }
  } else
    printOperand(MI, opNum, O);
}

static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O)
{
  MCOperand *MO = MCInst_getOperand(MI, opNum);
  if (MCOperand_isImm(MO)) {
    uint8_t imm = (uint8_t)MCOperand_getImm(MO);
    if (imm > HEX_THRESHOLD)
      SStream_concat(O, "0x%x", imm);
    else
      SStream_concat(O, "%u", imm);
    if (MI->csh->detail) {
      MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
      MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
      MI->flat_insn->detail->mips.op_count++;
    }
  } else
    printOperand(MI, opNum, O);
}

static void printMemOperand(MCInst *MI, int opNum, SStream *O)
{
  // Load/Store memory operands -- imm($reg)
  // If PIC target the target is loaded as the
  // pattern lw $25,%call16($28)

  // opNum can be invalid if instruction had reglist as operand.
  // MemOperand is always last operand of instruction (base + offset).
  switch (MCInst_getOpcode(MI)) {
    default:
      break;
    case Mips_SWM32_MM:
    case Mips_LWM32_MM:
    case Mips_SWM16_MM:
    case Mips_LWM16_MM:
      opNum = MCInst_getNumOperands(MI) - 2;
      break;
  }

  set_mem_access(MI, true);
  printOperand(MI, opNum + 1, O);
  SStream_concat0(O, "(");
  printOperand(MI, opNum, O);
  SStream_concat0(O, ")");
  set_mem_access(MI, false);
}

// TODO???
static void printMemOperandEA(MCInst *MI, int opNum, SStream *O)
{
  // when using stack locations for not load/store instructions
  // print the same way as all normal 3 operand instructions.
  printOperand(MI, opNum, O);
  SStream_concat0(O, ", ");
  printOperand(MI, opNum + 1, O);
  return;
}

static void printFCCOperand(MCInst *MI, int opNum, SStream *O)
{
  MCOperand *MO = MCInst_getOperand(MI, opNum);
  SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO)));
}

static void printRegisterPair(MCInst *MI, int opNum, SStream *O)
{
  printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, opNum)));
}

static char *printAlias1(const char *Str, MCInst *MI, unsigned OpNo, SStream *OS)
{
  SStream_concat(OS, "%s\t", Str);
  printOperand(MI, OpNo, OS);
  return cs_strdup(Str);
}

static char *printAlias2(const char *Str, MCInst *MI,
    unsigned OpNo0, unsigned OpNo1, SStream *OS)
{
  char *tmp;

  tmp = printAlias1(Str, MI, OpNo0, OS);
  SStream_concat0(OS, ", ");
  printOperand(MI, OpNo1, OS);

  return tmp;
}

#define GET_REGINFO_ENUM
#include "MipsGenRegisterInfo.inc"

static char *printAlias(MCInst *MI, SStream *OS)
{
  switch (MCInst_getOpcode(MI)) {
    case Mips_BEQ:
    case Mips_BEQ_MM:
      // beq $zero, $zero, $L2 => b $L2
      // beq $r0, $zero, $L2 => beqz $r0, $L2
      if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO))
        return printAlias1("b", MI, 2, OS);
      if (isReg(MI, 1, Mips_ZERO))
        return printAlias2("beqz", MI, 0, 2, OS);
      return NULL;
    case Mips_BEQ64:
      // beq $r0, $zero, $L2 => beqz $r0, $L2
      if (isReg(MI, 1, Mips_ZERO_64))
        return printAlias2("beqz", MI, 0, 2, OS);
      return NULL;
    case Mips_BNE:
      // bne $r0, $zero, $L2 => bnez $r0, $L2
      if (isReg(MI, 1, Mips_ZERO))
        return printAlias2("bnez", MI, 0, 2, OS);
      return NULL;
    case Mips_BNE64:
      // bne $r0, $zero, $L2 => bnez $r0, $L2
      if (isReg(MI, 1, Mips_ZERO_64))
        return printAlias2("bnez", MI, 0, 2, OS);
      return NULL;
    case Mips_BGEZAL:
      // bgezal $zero, $L1 => bal $L1
      if (isReg(MI, 0, Mips_ZERO))
        return printAlias1("bal", MI, 1, OS);
      return NULL;
    case Mips_BC1T:
      // bc1t $fcc0, $L1 => bc1t $L1
      if (isReg(MI, 0, Mips_FCC0))
        return printAlias1("bc1t", MI, 1, OS);
      return NULL;
    case Mips_BC1F:
      // bc1f $fcc0, $L1 => bc1f $L1
      if (isReg(MI, 0, Mips_FCC0))
        return printAlias1("bc1f", MI, 1, OS);
      return NULL;
    case Mips_JALR:
      // jalr $ra, $r1 => jalr $r1
      if (isReg(MI, 0, Mips_RA))
        return printAlias1("jalr", MI, 1, OS);
      return NULL;
    case Mips_JALR64:
      // jalr $ra, $r1 => jalr $r1
      if (isReg(MI, 0, Mips_RA_64))
        return printAlias1("jalr", MI, 1, OS);
      return NULL;
    case Mips_NOR:
    case Mips_NOR_MM:
      // nor $r0, $r1, $zero => not $r0, $r1
      if (isReg(MI, 2, Mips_ZERO))
        return printAlias2("not", MI, 0, 1, OS);
      return NULL;
    case Mips_NOR64:
      // nor $r0, $r1, $zero => not $r0, $r1
      if (isReg(MI, 2, Mips_ZERO_64))
        return printAlias2("not", MI, 0, 1, OS);
      return NULL;
    case Mips_OR:
      // or $r0, $r1, $zero => move $r0, $r1
      if (isReg(MI, 2, Mips_ZERO))
        return printAlias2("move", MI, 0, 1, OS);
      return NULL;
    default: return NULL;
  }
}

static void printRegisterList(MCInst *MI, int opNum, SStream *O)
{
  int i, e, reg;

  // - 2 because register List is always first operand of instruction and it is
  // always followed by memory operand (base + offset).
  for (i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) {
    if (i != opNum)
      SStream_concat0(O, ", ");
    reg = MCOperand_getReg(MCInst_getOperand(MI, i));
    printRegName(O, reg);
    if (MI->csh->detail) {
      MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG;
      MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg;
      MI->flat_insn->detail->mips.op_count++;
    }
  }
}

#define PRINT_ALIAS_INSTR
#include "MipsGenAsmWriter.inc"

#endif

Coverage Report

Created: 2023-12-08 06:05

Line	Count	Source (jump to first uncovered line)
1		//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
2		//
3		// The LLVM Compiler Infrastructure
4		//
5		// This file is distributed under the University of Illinois Open Source
6		// License. See LICENSE.TXT for details.
7		//
8		//===----------------------------------------------------------------------===//
9		//
10		// This class prints an Mips MCInst to a .s file.
11		//
12		//===----------------------------------------------------------------------===//
13
14		/* Capstone Disassembly Engine */
15		/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
16
17		#ifdef CAPSTONE_HAS_MIPS
18
19		#include <capstone/platform.h>
20		#include <stdlib.h>
21		#include <stdio.h> // debug
22		#include <string.h>
23
24		#include "MipsInstPrinter.h"
25		#include "../../MCInst.h"
26		#include "../../utils.h"
27		#include "../../SStream.h"
28		#include "../../MCRegisterInfo.h"
29		#include "MipsMapping.h"
30
31		#include "MipsInstPrinter.h"
32
33		static void printUnsignedImm(MCInst MI, int opNum, SStream O);
34		static char printAliasInstr(MCInst MI, SStream O, void info);
35		static char printAlias(MCInst MI, SStream *OS);
36
37		// These enumeration declarations were originally in MipsInstrInfo.h but
38		// had to be moved here to avoid circular dependencies between
39		// LLVMMipsCodeGen and LLVMMipsAsmPrinter.
40
41		// Mips Condition Codes
42		typedef enum Mips_CondCode {
43		// To be used with float branch True
44		Mips_FCOND_F,
45		Mips_FCOND_UN,
46		Mips_FCOND_OEQ,
47		Mips_FCOND_UEQ,
48		Mips_FCOND_OLT,
49		Mips_FCOND_ULT,
50		Mips_FCOND_OLE,
51		Mips_FCOND_ULE,
52		Mips_FCOND_SF,
53		Mips_FCOND_NGLE,
54		Mips_FCOND_SEQ,
55		Mips_FCOND_NGL,
56		Mips_FCOND_LT,
57		Mips_FCOND_NGE,
58		Mips_FCOND_LE,
59		Mips_FCOND_NGT,
60
61		// To be used with float branch False
62		// This conditions have the same mnemonic as the
63		// above ones, but are used with a branch False;
64		Mips_FCOND_T,
65		Mips_FCOND_OR,
66		Mips_FCOND_UNE,
67		Mips_FCOND_ONE,
68		Mips_FCOND_UGE,
69		Mips_FCOND_OGE,
70		Mips_FCOND_UGT,
71		Mips_FCOND_OGT,
72		Mips_FCOND_ST,
73		Mips_FCOND_GLE,
74		Mips_FCOND_SNE,
75		Mips_FCOND_GL,
76		Mips_FCOND_NLT,
77		Mips_FCOND_GE,
78		Mips_FCOND_NLE,
79		Mips_FCOND_GT
80		} Mips_CondCode;
81
82		#define GET_INSTRINFO_ENUM
83		#include "MipsGenInstrInfo.inc"
84
85		static const char *getRegisterName(unsigned RegNo);
86		static void printInstruction(MCInst MI, SStream O, const MCRegisterInfo *MRI);
87
88		static void set_mem_access(MCInst *MI, bool status)
89	40.1k	{
90	40.1k	MI->csh->doing_mem = status;
91
92	40.1k	if (MI->csh->detail != CS_OPT_ON)
93	0	return;
94
95	40.1k	if (status) {
96	20.0k	MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM;
97	20.0k	MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID;
98	20.0k	MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0;
99	20.0k	} else {
100		// done, create the next operand slot
101	20.0k	MI->flat_insn->detail->mips.op_count++;
102	20.0k	}
103	40.1k	}
104
105		static bool isReg(MCInst *MI, unsigned OpNo, unsigned R)
106	8.62k	{
107	8.62k	return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) &&
108	8.62k	MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R);
109	8.62k	}
110
111		static const char* MipsFCCToString(Mips_CondCode CC)
112	0	{
113	0	switch (CC) {
114	0	default: return 0; // never reach
115	0	case Mips_FCOND_F:
116	0	case Mips_FCOND_T: return "f";
117	0	case Mips_FCOND_UN:
118	0	case Mips_FCOND_OR: return "un";
119	0	case Mips_FCOND_OEQ:
120	0	case Mips_FCOND_UNE: return "eq";
121	0	case Mips_FCOND_UEQ:
122	0	case Mips_FCOND_ONE: return "ueq";
123	0	case Mips_FCOND_OLT:
124	0	case Mips_FCOND_UGE: return "olt";
125	0	case Mips_FCOND_ULT:
126	0	case Mips_FCOND_OGE: return "ult";
127	0	case Mips_FCOND_OLE:
128	0	case Mips_FCOND_UGT: return "ole";
129	0	case Mips_FCOND_ULE:
130	0	case Mips_FCOND_OGT: return "ule";
131	0	case Mips_FCOND_SF:
132	0	case Mips_FCOND_ST: return "sf";
133	0	case Mips_FCOND_NGLE:
134	0	case Mips_FCOND_GLE: return "ngle";
135	0	case Mips_FCOND_SEQ:
136	0	case Mips_FCOND_SNE: return "seq";
137	0	case Mips_FCOND_NGL:
138	0	case Mips_FCOND_GL: return "ngl";
139	0	case Mips_FCOND_LT:
140	0	case Mips_FCOND_NLT: return "lt";
141	0	case Mips_FCOND_NGE:
142	0	case Mips_FCOND_GE: return "nge";
143	0	case Mips_FCOND_LE:
144	0	case Mips_FCOND_NLE: return "le";
145	0	case Mips_FCOND_NGT:
146	0	case Mips_FCOND_GT: return "ngt";
147	0	}
148	0	}
149
150		static void printRegName(SStream *OS, unsigned RegNo)
151	141k	{
152	141k	SStream_concat(OS, "$%s", getRegisterName(RegNo));
153	141k	}
154
155		void Mips_printInst(MCInst MI, SStream O, void *info)
156	87.1k	{
157	87.1k	char *mnem;
158
159	87.1k	switch (MCInst_getOpcode(MI)) {
160	87.1k	default: break;
161	87.1k	case Mips_Save16:
162	0	case Mips_SaveX16:
163	0	case Mips_Restore16:
164	0	case Mips_RestoreX16:
165	0	return;
166	87.1k	}
167
168		// Try to print any aliases first.
169	87.1k	mnem = printAliasInstr(MI, O, info);
170	87.1k	if (!mnem) {
171	78.4k	mnem = printAlias(MI, O);
172	78.4k	if (!mnem) {
173	77.2k	printInstruction(MI, O, NULL);
174	77.2k	}
175	78.4k	}
176
177	87.1k	if (mnem) {
178		// fixup instruction id due to the change in alias instruction
179	9.88k	MCInst_setOpcodePub(MI, Mips_map_insn(mnem));
180	9.88k	cs_mem_free(mnem);
181	9.88k	}
182	87.1k	}
183
184		static void printOperand(MCInst MI, unsigned OpNo, SStream O)
185	191k	{
186	191k	MCOperand *Op;
187
188	191k	if (OpNo >= MI->size)
189	0	return;
190
191	191k	Op = MCInst_getOperand(MI, OpNo);
192	191k	if (MCOperand_isReg(Op)) {
193	136k	unsigned int reg = MCOperand_getReg(Op);
194	136k	printRegName(O, reg);
195	136k	reg = Mips_map_register(reg);
196	136k	if (MI->csh->detail) {
197	136k	if (MI->csh->doing_mem) {
198	20.0k	MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg;
199	116k	} else {
200	116k	MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG;
201	116k	MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg;
202	116k	MI->flat_insn->detail->mips.op_count++;
203	116k	}
204	136k	}
205	136k	} else if (MCOperand_isImm(Op)) {
206	55.2k	int64_t imm = MCOperand_getImm(Op);
207	55.2k	if (MI->csh->doing_mem) {
208	20.0k	if (imm) { // only print Imm offset if it is not 0
209	19.1k	printInt64(O, imm);
210	19.1k	}
211	20.0k	if (MI->csh->detail)
212	20.0k	MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm;
213	35.2k	} else {
214	35.2k	printInt64(O, imm);
215
216	35.2k	if (MI->csh->detail) {
217	35.2k	MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
218	35.2k	MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
219	35.2k	MI->flat_insn->detail->mips.op_count++;
220	35.2k	}
221	35.2k	}
222	55.2k	}
223	191k	}
224
225		static void printUnsignedImm(MCInst MI, int opNum, SStream O)
226	13.6k	{
227	13.6k	MCOperand *MO = MCInst_getOperand(MI, opNum);
228	13.6k	if (MCOperand_isImm(MO)) {
229	13.6k	int64_t imm = MCOperand_getImm(MO);
230	13.6k	printInt64(O, imm);
231
232	13.6k	if (MI->csh->detail) {
233	13.6k	MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
234	13.6k	MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm;
235	13.6k	MI->flat_insn->detail->mips.op_count++;
236	13.6k	}
237	13.6k	} else
238	0	printOperand(MI, opNum, O);
239	13.6k	}
240
241		static void printUnsignedImm8(MCInst MI, int opNum, SStream O)
242	4.06k	{
243	4.06k	MCOperand *MO = MCInst_getOperand(MI, opNum);
244	4.06k	if (MCOperand_isImm(MO)) {
245	4.06k	uint8_t imm = (uint8_t)MCOperand_getImm(MO);
246	4.06k	if (imm > HEX_THRESHOLD)
247	648	SStream_concat(O, "0x%x", imm);
248	3.41k	else
249	3.41k	SStream_concat(O, "%u", imm);
250	4.06k	if (MI->csh->detail) {
251	4.06k	MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
252	4.06k	MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
253	4.06k	MI->flat_insn->detail->mips.op_count++;
254	4.06k	}
255	4.06k	} else
256	0	printOperand(MI, opNum, O);
257	4.06k	}
258
259		static void printMemOperand(MCInst MI, int opNum, SStream O)
260	20.0k	{
261		// Load/Store memory operands -- imm($reg)
262		// If PIC target the target is loaded as the
263		// pattern lw $25,%call16($28)
264
265		// opNum can be invalid if instruction had reglist as operand.
266		// MemOperand is always last operand of instruction (base + offset).
267	20.0k	switch (MCInst_getOpcode(MI)) {
268	19.1k	default:
269	19.1k	break;
270	19.1k	case Mips_SWM32_MM:
271	304	case Mips_LWM32_MM:
272	629	case Mips_SWM16_MM:
273	960	case Mips_LWM16_MM:
274	960	opNum = MCInst_getNumOperands(MI) - 2;
275	960	break;
276	20.0k	}
277
278	20.0k	set_mem_access(MI, true);
279	20.0k	printOperand(MI, opNum + 1, O);
280	20.0k	SStream_concat0(O, "(");
281	20.0k	printOperand(MI, opNum, O);
282	20.0k	SStream_concat0(O, ")");
283	20.0k	set_mem_access(MI, false);
284	20.0k	}
285
286		// TODO???
287		static void printMemOperandEA(MCInst MI, int opNum, SStream O)
288	0	{
289		// when using stack locations for not load/store instructions
290		// print the same way as all normal 3 operand instructions.
291	0	printOperand(MI, opNum, O);
292	0	SStream_concat0(O, ", ");
293	0	printOperand(MI, opNum + 1, O);
294	0	return;
295	0	}
296
297		static void printFCCOperand(MCInst MI, int opNum, SStream O)
298	0	{
299	0	MCOperand *MO = MCInst_getOperand(MI, opNum);
300	0	SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO)));
301	0	}
302
303		static void printRegisterPair(MCInst MI, int opNum, SStream O)
304	264	{
305	264	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, opNum)));
306	264	}
307
308		static char printAlias1(const char Str, MCInst MI, unsigned OpNo, SStream OS)
309	1.25k	{
310	1.25k	SStream_concat(OS, "%s\t", Str);
311	1.25k	printOperand(MI, OpNo, OS);
312	1.25k	return cs_strdup(Str);
313	1.25k	}
314
315		static char printAlias2(const char Str, MCInst *MI,
316		unsigned OpNo0, unsigned OpNo1, SStream *OS)
317	724	{
318	724	char *tmp;
319
320	724	tmp = printAlias1(Str, MI, OpNo0, OS);
321	724	SStream_concat0(OS, ", ");
322	724	printOperand(MI, OpNo1, OS);
323
324	724	return tmp;
325	724	}
326
327		#define GET_REGINFO_ENUM
328		#include "MipsGenRegisterInfo.inc"
329
330		static char printAlias(MCInst MI, SStream *OS)
331	78.4k	{
332	78.4k	switch (MCInst_getOpcode(MI)) {
333	2.57k	case Mips_BEQ:
334	2.79k	case Mips_BEQ_MM:
335		// beq $zero, $zero, $L2 => b $L2
336		// beq $r0, $zero, $L2 => beqz $r0, $L2
337	2.79k	if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO))
338	279	return printAlias1("b", MI, 2, OS);
339	2.51k	if (isReg(MI, 1, Mips_ZERO))
340	246	return printAlias2("beqz", MI, 0, 2, OS);
341	2.27k	return NULL;
342	0	case Mips_BEQ64:
343		// beq $r0, $zero, $L2 => beqz $r0, $L2
344	0	if (isReg(MI, 1, Mips_ZERO_64))
345	0	return printAlias2("beqz", MI, 0, 2, OS);
346	0	return NULL;
347	791	case Mips_BNE:
348		// bne $r0, $zero, $L2 => bnez $r0, $L2
349	791	if (isReg(MI, 1, Mips_ZERO))
350	369	return printAlias2("bnez", MI, 0, 2, OS);
351	422	return NULL;
352	0	case Mips_BNE64:
353		// bne $r0, $zero, $L2 => bnez $r0, $L2
354	0	if (isReg(MI, 1, Mips_ZERO_64))
355	0	return printAlias2("bnez", MI, 0, 2, OS);
356	0	return NULL;
357	279	case Mips_BGEZAL:
358		// bgezal $zero, $L1 => bal $L1
359	279	if (isReg(MI, 0, Mips_ZERO))
360	72	return printAlias1("bal", MI, 1, OS);
361	207	return NULL;
362	88	case Mips_BC1T:
363		// bc1t $fcc0, $L1 => bc1t $L1
364	88	if (isReg(MI, 0, Mips_FCC0))
365	0	return printAlias1("bc1t", MI, 1, OS);
366	88	return NULL;
367	337	case Mips_BC1F:
368		// bc1f $fcc0, $L1 => bc1f $L1
369	337	if (isReg(MI, 0, Mips_FCC0))
370	0	return printAlias1("bc1f", MI, 1, OS);
371	337	return NULL;
372	708	case Mips_JALR:
373		// jalr $ra, $r1 => jalr $r1
374	708	if (isReg(MI, 0, Mips_RA))
375	183	return printAlias1("jalr", MI, 1, OS);
376	525	return NULL;
377	0	case Mips_JALR64:
378		// jalr $ra, $r1 => jalr $r1
379	0	if (isReg(MI, 0, Mips_RA_64))
380	0	return printAlias1("jalr", MI, 1, OS);
381	0	return NULL;
382	97	case Mips_NOR:
383	131	case Mips_NOR_MM:
384		// nor $r0, $r1, $zero => not $r0, $r1
385	131	if (isReg(MI, 2, Mips_ZERO))
386	20	return printAlias2("not", MI, 0, 1, OS);
387	111	return NULL;
388	0	case Mips_NOR64:
389		// nor $r0, $r1, $zero => not $r0, $r1
390	0	if (isReg(MI, 2, Mips_ZERO_64))
391	0	return printAlias2("not", MI, 0, 1, OS);
392	0	return NULL;
393	159	case Mips_OR:
394		// or $r0, $r1, $zero => move $r0, $r1
395	159	if (isReg(MI, 2, Mips_ZERO))
396	89	return printAlias2("move", MI, 0, 1, OS);
397	70	return NULL;
398	73.1k	default: return NULL;
399	78.4k	}
400	78.4k	}
401
402		static void printRegisterList(MCInst MI, int opNum, SStream O)
403	1.22k	{
404	1.22k	int i, e, reg;
405
406		// - 2 because register List is always first operand of instruction and it is
407		// always followed by memory operand (base + offset).
408	5.86k	for (i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) {
409	4.63k	if (i != opNum)
410	3.40k	SStream_concat0(O, ", ");
411	4.63k	reg = MCOperand_getReg(MCInst_getOperand(MI, i));
412	4.63k	printRegName(O, reg);
413	4.63k	if (MI->csh->detail) {
414	4.63k	MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG;
415	4.63k	MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg;
416	4.63k	MI->flat_insn->detail->mips.op_count++;
417	4.63k	}
418	4.63k	}
419	1.22k	}
420
421		#define PRINT_ALIAS_INSTR
422		#include "MipsGenAsmWriter.inc"
423
424		#endif