Coverage Report

Created: 2023-12-08 06:05

/src/capstonev5/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|*Assembly Writer Source Fragment                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
15
16
/// printInstruction - This method is automatically generated by tablegen
17
/// from the instruction set description.
18
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19
43.2k
{
20
43.2k
  static const uint32_t OpInfo[] = {
21
43.2k
    0U, // PHI
22
43.2k
    0U, // INLINEASM
23
43.2k
    0U, // CFI_INSTRUCTION
24
43.2k
    0U, // EH_LABEL
25
43.2k
    0U, // GC_LABEL
26
43.2k
    0U, // KILL
27
43.2k
    0U, // EXTRACT_SUBREG
28
43.2k
    0U, // INSERT_SUBREG
29
43.2k
    0U, // IMPLICIT_DEF
30
43.2k
    0U, // SUBREG_TO_REG
31
43.2k
    0U, // COPY_TO_REGCLASS
32
43.2k
    2452U,  // DBG_VALUE
33
43.2k
    0U, // REG_SEQUENCE
34
43.2k
    0U, // COPY
35
43.2k
    2445U,  // BUNDLE
36
43.2k
    2462U,  // LIFETIME_START
37
43.2k
    2432U,  // LIFETIME_END
38
43.2k
    0U, // STACKMAP
39
43.2k
    0U, // PATCHPOINT
40
43.2k
    0U, // LOAD_STACK_GUARD
41
43.2k
    0U, // STATEPOINT
42
43.2k
    0U, // FRAME_ALLOC
43
43.2k
    4688U,  // ADDCCri
44
43.2k
    4688U,  // ADDCCrr
45
43.2k
    5925U,  // ADDCri
46
43.2k
    5925U,  // ADDCrr
47
43.2k
    4772U,  // ADDEri
48
43.2k
    4772U,  // ADDErr
49
43.2k
    4786U,  // ADDXC
50
43.2k
    4678U,  // ADDXCCC
51
43.2k
    4808U,  // ADDXri
52
43.2k
    4808U,  // ADDXrr
53
43.2k
    4808U,  // ADDri
54
43.2k
    4808U,  // ADDrr
55
43.2k
    74166U, // ADJCALLSTACKDOWN
56
43.2k
    74185U, // ADJCALLSTACKUP
57
43.2k
    5497U,  // ALIGNADDR
58
43.2k
    5127U,  // ALIGNADDRL
59
43.2k
    4695U,  // ANDCCri
60
43.2k
    4695U,  // ANDCCrr
61
43.2k
    4718U,  // ANDNCCri
62
43.2k
    4718U,  // ANDNCCrr
63
43.2k
    5182U,  // ANDNri
64
43.2k
    5182U,  // ANDNrr
65
43.2k
    5182U,  // ANDXNrr
66
43.2k
    4876U,  // ANDXri
67
43.2k
    4876U,  // ANDXrr
68
43.2k
    4876U,  // ANDri
69
43.2k
    4876U,  // ANDrr
70
43.2k
    4502U,  // ARRAY16
71
43.2k
    4255U,  // ARRAY32
72
43.2k
    4526U,  // ARRAY8
73
43.2k
    0U, // ATOMIC_LOAD_ADD_32
74
43.2k
    0U, // ATOMIC_LOAD_ADD_64
75
43.2k
    0U, // ATOMIC_LOAD_AND_32
76
43.2k
    0U, // ATOMIC_LOAD_AND_64
77
43.2k
    0U, // ATOMIC_LOAD_MAX_32
78
43.2k
    0U, // ATOMIC_LOAD_MAX_64
79
43.2k
    0U, // ATOMIC_LOAD_MIN_32
80
43.2k
    0U, // ATOMIC_LOAD_MIN_64
81
43.2k
    0U, // ATOMIC_LOAD_NAND_32
82
43.2k
    0U, // ATOMIC_LOAD_NAND_64
83
43.2k
    0U, // ATOMIC_LOAD_OR_32
84
43.2k
    0U, // ATOMIC_LOAD_OR_64
85
43.2k
    0U, // ATOMIC_LOAD_SUB_32
86
43.2k
    0U, // ATOMIC_LOAD_SUB_64
87
43.2k
    0U, // ATOMIC_LOAD_UMAX_32
88
43.2k
    0U, // ATOMIC_LOAD_UMAX_64
89
43.2k
    0U, // ATOMIC_LOAD_UMIN_32
90
43.2k
    0U, // ATOMIC_LOAD_UMIN_64
91
43.2k
    0U, // ATOMIC_LOAD_XOR_32
92
43.2k
    0U, // ATOMIC_LOAD_XOR_64
93
43.2k
    0U, // ATOMIC_SWAP_64
94
43.2k
    74271U, // BA
95
43.2k
    1194492U, // BCOND
96
43.2k
    1260028U, // BCONDA
97
43.2k
    17659U, // BINDri
98
43.2k
    17659U, // BINDrr
99
43.2k
    5065U,  // BMASK
100
43.2k
    145915U,  // BPFCC
101
43.2k
    211451U,  // BPFCCA
102
43.2k
    276987U,  // BPFCCANT
103
43.2k
    342523U,  // BPFCCNT
104
43.2k
    2106465U, // BPGEZapn
105
43.2k
    2105838U, // BPGEZapt
106
43.2k
    2106532U, // BPGEZnapn
107
43.2k
    2107288U, // BPGEZnapt
108
43.2k
    2106489U, // BPGZapn
109
43.2k
    2105856U, // BPGZapt
110
43.2k
    2106552U, // BPGZnapn
111
43.2k
    2107384U, // BPGZnapt
112
43.2k
    1456636U, // BPICC
113
43.2k
    473596U,  // BPICCA
114
43.2k
    539132U,  // BPICCANT
115
43.2k
    604668U,  // BPICCNT
116
43.2k
    2106477U, // BPLEZapn
117
43.2k
    2105847U, // BPLEZapt
118
43.2k
    2106542U, // BPLEZnapn
119
43.2k
    2107337U, // BPLEZnapt
120
43.2k
    2106500U, // BPLZapn
121
43.2k
    2105864U, // BPLZapt
122
43.2k
    2106561U, // BPLZnapn
123
43.2k
    2107428U, // BPLZnapt
124
43.2k
    2106511U, // BPNZapn
125
43.2k
    2105872U, // BPNZapt
126
43.2k
    2106570U, // BPNZnapn
127
43.2k
    2107472U, // BPNZnapt
128
43.2k
    1718780U, // BPXCC
129
43.2k
    735740U,  // BPXCCA
130
43.2k
    801276U,  // BPXCCANT
131
43.2k
    866812U,  // BPXCCNT
132
43.2k
    2106522U, // BPZapn
133
43.2k
    2105880U, // BPZapt
134
43.2k
    2106579U, // BPZnapn
135
43.2k
    2107505U, // BPZnapt
136
43.2k
    4983U,  // BSHUFFLE
137
43.2k
    74742U, // CALL
138
43.2k
    17398U, // CALLri
139
43.2k
    17398U, // CALLrr
140
43.2k
    924148U,  // CASXrr
141
43.2k
    924129U,  // CASrr
142
43.2k
    74001U, // CMASK16
143
43.2k
    73833U, // CMASK32
144
43.2k
    74150U, // CMASK8
145
43.2k
    2106607U, // CMPri
146
43.2k
    2106607U, // CMPrr
147
43.2k
    4332U,  // EDGE16
148
43.2k
    5081U,  // EDGE16L
149
43.2k
    5198U,  // EDGE16LN
150
43.2k
    5165U,  // EDGE16N
151
43.2k
    4164U,  // EDGE32
152
43.2k
    5072U,  // EDGE32L
153
43.2k
    5188U,  // EDGE32LN
154
43.2k
    5156U,  // EDGE32N
155
43.2k
    4511U,  // EDGE8
156
43.2k
    5090U,  // EDGE8L
157
43.2k
    5208U,  // EDGE8LN
158
43.2k
    5174U,  // EDGE8N
159
43.2k
    1053516U, // FABSD
160
43.2k
    1054031U, // FABSQ
161
43.2k
    1054376U, // FABSS
162
43.2k
    4813U,  // FADDD
163
43.2k
    5383U,  // FADDQ
164
43.2k
    5645U,  // FADDS
165
43.2k
    4648U,  // FALIGNADATA
166
43.2k
    4875U,  // FAND
167
43.2k
    4112U,  // FANDNOT1
168
43.2k
    5544U,  // FANDNOT1S
169
43.2k
    4271U,  // FANDNOT2
170
43.2k
    5591U,  // FANDNOT2S
171
43.2k
    5677U,  // FANDS
172
43.2k
    1194491U, // FBCOND
173
43.2k
    1260027U, // FBCONDA
174
43.2k
    4394U,  // FCHKSM16
175
43.2k
    2106173U, // FCMPD
176
43.2k
    4413U,  // FCMPEQ16
177
43.2k
    4226U,  // FCMPEQ32
178
43.2k
    4432U,  // FCMPGT16
179
43.2k
    4245U,  // FCMPGT32
180
43.2k
    4340U,  // FCMPLE16
181
43.2k
    4172U,  // FCMPLE32
182
43.2k
    4350U,  // FCMPNE16
183
43.2k
    4182U,  // FCMPNE32
184
43.2k
    2106696U, // FCMPQ
185
43.2k
    2107005U, // FCMPS
186
43.2k
    4960U,  // FDIVD
187
43.2k
    5475U,  // FDIVQ
188
43.2k
    5815U,  // FDIVS
189
43.2k
    5405U,  // FDMULQ
190
43.2k
    1053620U, // FDTOI
191
43.2k
    1053996U, // FDTOQ
192
43.2k
    1054305U, // FDTOS
193
43.2k
    1054536U, // FDTOX
194
43.2k
    1053464U, // FEXPAND
195
43.2k
    4820U,  // FHADDD
196
43.2k
    5652U,  // FHADDS
197
43.2k
    4800U,  // FHSUBD
198
43.2k
    5637U,  // FHSUBS
199
43.2k
    1053473U, // FITOD
200
43.2k
    1054003U, // FITOQ
201
43.2k
    1054312U, // FITOS
202
43.2k
    6300484U, // FLCMPD
203
43.2k
    6301316U, // FLCMPS
204
43.2k
    2606U,  // FLUSHW
205
43.2k
    4404U,  // FMEAN16
206
43.2k
    1053543U, // FMOVD
207
43.2k
    1006078U, // FMOVD_FCC
208
43.2k
    23484926U,  // FMOVD_ICC
209
43.2k
    23747070U,  // FMOVD_XCC
210
43.2k
    1054058U, // FMOVQ
211
43.2k
    1006102U, // FMOVQ_FCC
212
43.2k
    23484950U,  // FMOVQ_ICC
213
43.2k
    23747094U,  // FMOVQ_XCC
214
43.2k
    6018U,  // FMOVRGEZD
215
43.2k
    6029U,  // FMOVRGEZQ
216
43.2k
    6056U,  // FMOVRGEZS
217
43.2k
    6116U,  // FMOVRGZD
218
43.2k
    6126U,  // FMOVRGZQ
219
43.2k
    6150U,  // FMOVRGZS
220
43.2k
    6067U,  // FMOVRLEZD
221
43.2k
    6078U,  // FMOVRLEZQ
222
43.2k
    6105U,  // FMOVRLEZS
223
43.2k
    6160U,  // FMOVRLZD
224
43.2k
    6170U,  // FMOVRLZQ
225
43.2k
    6194U,  // FMOVRLZS
226
43.2k
    6204U,  // FMOVRNZD
227
43.2k
    6214U,  // FMOVRNZQ
228
43.2k
    6238U,  // FMOVRNZS
229
43.2k
    6009U,  // FMOVRZD
230
43.2k
    6248U,  // FMOVRZQ
231
43.2k
    6269U,  // FMOVRZS
232
43.2k
    1054398U, // FMOVS
233
43.2k
    1006114U, // FMOVS_FCC
234
43.2k
    23484962U,  // FMOVS_ICC
235
43.2k
    23747106U,  // FMOVS_XCC
236
43.2k
    4490U,  // FMUL8SUX16
237
43.2k
    4465U,  // FMUL8ULX16
238
43.2k
    4442U,  // FMUL8X16
239
43.2k
    5098U,  // FMUL8X16AL
240
43.2k
    5849U,  // FMUL8X16AU
241
43.2k
    4860U,  // FMULD
242
43.2k
    4477U,  // FMULD8SUX16
243
43.2k
    4452U,  // FMULD8ULX16
244
43.2k
    5413U,  // FMULQ
245
43.2k
    5714U,  // FMULS
246
43.2k
    4837U,  // FNADDD
247
43.2k
    5669U,  // FNADDS
248
43.2k
    4881U,  // FNAND
249
43.2k
    5684U,  // FNANDS
250
43.2k
    1053429U, // FNEGD
251
43.2k
    1053974U, // FNEGQ
252
43.2k
    1054283U, // FNEGS
253
43.2k
    4828U,  // FNHADDD
254
43.2k
    5660U,  // FNHADDS
255
43.2k
    4828U,  // FNMULD
256
43.2k
    5660U,  // FNMULS
257
43.2k
    5513U,  // FNOR
258
43.2k
    5778U,  // FNORS
259
43.2k
    1052698U, // FNOT1
260
43.2k
    1054131U, // FNOT1S
261
43.2k
    1052857U, // FNOT2
262
43.2k
    1054178U, // FNOT2S
263
43.2k
    5660U,  // FNSMULD
264
43.2k
    74625U, // FONE
265
43.2k
    75324U, // FONES
266
43.2k
    5508U,  // FOR
267
43.2k
    4129U,  // FORNOT1
268
43.2k
    5563U,  // FORNOT1S
269
43.2k
    4288U,  // FORNOT2
270
43.2k
    5610U,  // FORNOT2S
271
43.2k
    5772U,  // FORS
272
43.2k
    1052936U, // FPACK16
273
43.2k
    4192U,  // FPACK32
274
43.2k
    1054507U, // FPACKFIX
275
43.2k
    4323U,  // FPADD16
276
43.2k
    5620U,  // FPADD16S
277
43.2k
    4155U,  // FPADD32
278
43.2k
    5573U,  // FPADD32S
279
43.2k
    4297U,  // FPADD64
280
43.2k
    4974U,  // FPMERGE
281
43.2k
    4314U,  // FPSUB16
282
43.2k
    4580U,  // FPSUB16S
283
43.2k
    4146U,  // FPSUB32
284
43.2k
    4570U,  // FPSUB32S
285
43.2k
    1053480U, // FQTOD
286
43.2k
    1053627U, // FQTOI
287
43.2k
    1054319U, // FQTOS
288
43.2k
    1054552U, // FQTOX
289
43.2k
    4423U,  // FSLAS16
290
43.2k
    4236U,  // FSLAS32
291
43.2k
    4378U,  // FSLL16
292
43.2k
    4210U,  // FSLL32
293
43.2k
    4867U,  // FSMULD
294
43.2k
    1053523U, // FSQRTD
295
43.2k
    1054038U, // FSQRTQ
296
43.2k
    1054383U, // FSQRTS
297
43.2k
    4306U,  // FSRA16
298
43.2k
    4138U,  // FSRA32
299
43.2k
    1052681U, // FSRC1
300
43.2k
    1054112U, // FSRC1S
301
43.2k
    1052840U, // FSRC2
302
43.2k
    1054159U, // FSRC2S
303
43.2k
    4386U,  // FSRL16
304
43.2k
    4218U,  // FSRL32
305
43.2k
    1053487U, // FSTOD
306
43.2k
    1053634U, // FSTOI
307
43.2k
    1054010U, // FSTOQ
308
43.2k
    1054559U, // FSTOX
309
43.2k
    4793U,  // FSUBD
310
43.2k
    5376U,  // FSUBQ
311
43.2k
    5630U,  // FSUBS
312
43.2k
    5519U,  // FXNOR
313
43.2k
    5785U,  // FXNORS
314
43.2k
    5526U,  // FXOR
315
43.2k
    5793U,  // FXORS
316
43.2k
    1053494U, // FXTOD
317
43.2k
    1054017U, // FXTOQ
318
43.2k
    1054326U, // FXTOS
319
43.2k
    74984U, // FZERO
320
43.2k
    75353U, // FZEROS
321
43.2k
    24584U, // GETPCX
322
43.2k
    1078273U, // JMPLri
323
43.2k
    1078273U, // JMPLrr
324
43.2k
    1997243U, // LDDFri
325
43.2k
    1997243U, // LDDFrr
326
43.2k
    1997249U, // LDFri
327
43.2k
    1997249U, // LDFrr
328
43.2k
    1997275U, // LDQFri
329
43.2k
    1997275U, // LDQFrr
330
43.2k
    1997229U, // LDSBri
331
43.2k
    1997229U, // LDSBrr
332
43.2k
    1997254U, // LDSHri
333
43.2k
    1997254U, // LDSHrr
334
43.2k
    1997287U, // LDSWri
335
43.2k
    1997287U, // LDSWrr
336
43.2k
    1997236U, // LDUBri
337
43.2k
    1997236U, // LDUBrr
338
43.2k
    1997261U, // LDUHri
339
43.2k
    1997261U, // LDUHrr
340
43.2k
    1997294U, // LDXri
341
43.2k
    1997294U, // LDXrr
342
43.2k
    1997249U, // LDri
343
43.2k
    1997249U, // LDrr
344
43.2k
    33480U, // LEAX_ADDri
345
43.2k
    33480U, // LEA_ADDri
346
43.2k
    1054405U, // LZCNT
347
43.2k
    75121U, // MEMBARi
348
43.2k
    1054543U, // MOVDTOX
349
43.2k
    1006122U, // MOVFCCri
350
43.2k
    1006122U, // MOVFCCrr
351
43.2k
    23484970U,  // MOVICCri
352
43.2k
    23484970U,  // MOVICCrr
353
43.2k
    6047U,  // MOVRGEZri
354
43.2k
    6047U,  // MOVRGEZrr
355
43.2k
    6142U,  // MOVRGZri
356
43.2k
    6142U,  // MOVRGZrr
357
43.2k
    6096U,  // MOVRLEZri
358
43.2k
    6096U,  // MOVRLEZrr
359
43.2k
    6186U,  // MOVRLZri
360
43.2k
    6186U,  // MOVRLZrr
361
43.2k
    6230U,  // MOVRNZri
362
43.2k
    6230U,  // MOVRNZrr
363
43.2k
    6262U,  // MOVRRZri
364
43.2k
    6262U,  // MOVRRZrr
365
43.2k
    1054469U, // MOVSTOSW
366
43.2k
    1054479U, // MOVSTOUW
367
43.2k
    1054543U, // MOVWTOS
368
43.2k
    23747114U,  // MOVXCCri
369
43.2k
    23747114U,  // MOVXCCrr
370
43.2k
    1054543U, // MOVXTOD
371
43.2k
    5954U,  // MULXri
372
43.2k
    5954U,  // MULXrr
373
43.2k
    2578U,  // NOP
374
43.2k
    4735U,  // ORCCri
375
43.2k
    4735U,  // ORCCrr
376
43.2k
    4726U,  // ORNCCri
377
43.2k
    4726U,  // ORNCCrr
378
43.2k
    5339U,  // ORNri
379
43.2k
    5339U,  // ORNrr
380
43.2k
    5339U,  // ORXNrr
381
43.2k
    5509U,  // ORXri
382
43.2k
    5509U,  // ORXrr
383
43.2k
    5509U,  // ORri
384
43.2k
    5509U,  // ORrr
385
43.2k
    5836U,  // PDIST
386
43.2k
    5344U,  // PDISTN
387
43.2k
    1053356U, // POPCrr
388
43.2k
    73729U, // RDY
389
43.2k
    4999U,  // RESTOREri
390
43.2k
    4999U,  // RESTORErr
391
43.2k
    76132U, // RET
392
43.2k
    76141U, // RETL
393
43.2k
    18131U, // RETTri
394
43.2k
    18131U, // RETTrr
395
43.2k
    5008U,  // SAVEri
396
43.2k
    5008U,  // SAVErr
397
43.2k
    4748U,  // SDIVCCri
398
43.2k
    4748U,  // SDIVCCrr
399
43.2k
    5995U,  // SDIVXri
400
43.2k
    5995U,  // SDIVXrr
401
43.2k
    5861U,  // SDIVri
402
43.2k
    5861U,  // SDIVrr
403
43.2k
    2182U,  // SELECT_CC_DFP_FCC
404
43.2k
    2293U,  // SELECT_CC_DFP_ICC
405
43.2k
    2238U,  // SELECT_CC_FP_FCC
406
43.2k
    2349U,  // SELECT_CC_FP_ICC
407
43.2k
    2265U,  // SELECT_CC_Int_FCC
408
43.2k
    2376U,  // SELECT_CC_Int_ICC
409
43.2k
    2210U,  // SELECT_CC_QFP_FCC
410
43.2k
    2321U,  // SELECT_CC_QFP_ICC
411
43.2k
    1053595U, // SETHIXi
412
43.2k
    1053595U, // SETHIi
413
43.2k
    2569U,  // SHUTDOWN
414
43.2k
    2564U,  // SIAM
415
43.2k
    5941U,  // SLLXri
416
43.2k
    5941U,  // SLLXrr
417
43.2k
    5116U,  // SLLri
418
43.2k
    5116U,  // SLLrr
419
43.2k
    4702U,  // SMULCCri
420
43.2k
    4702U,  // SMULCCrr
421
43.2k
    5144U,  // SMULri
422
43.2k
    5144U,  // SMULrr
423
43.2k
    5913U,  // SRAXri
424
43.2k
    5913U,  // SRAXrr
425
43.2k
    4643U,  // SRAri
426
43.2k
    4643U,  // SRArr
427
43.2k
    5947U,  // SRLXri
428
43.2k
    5947U,  // SRLXrr
429
43.2k
    5139U,  // SRLri
430
43.2k
    5139U,  // SRLrr
431
43.2k
    2588U,  // STBAR
432
43.2k
    37428U, // STBri
433
43.2k
    37428U, // STBrr
434
43.2k
    37723U, // STDFri
435
43.2k
    37723U, // STDFrr
436
43.2k
    38607U, // STFri
437
43.2k
    38607U, // STFrr
438
43.2k
    37782U, // STHri
439
43.2k
    37782U, // STHrr
440
43.2k
    38238U, // STQFri
441
43.2k
    38238U, // STQFrr
442
43.2k
    38758U, // STXri
443
43.2k
    38758U, // STXrr
444
43.2k
    38607U, // STri
445
43.2k
    38607U, // STrr
446
43.2k
    4671U,  // SUBCCri
447
43.2k
    4671U,  // SUBCCrr
448
43.2k
    5919U,  // SUBCri
449
43.2k
    5919U,  // SUBCrr
450
43.2k
    4764U,  // SUBEri
451
43.2k
    4764U,  // SUBErr
452
43.2k
    4665U,  // SUBXri
453
43.2k
    4665U,  // SUBXrr
454
43.2k
    4665U,  // SUBri
455
43.2k
    4665U,  // SUBrr
456
43.2k
    1997268U, // SWAPri
457
43.2k
    1997268U, // SWAPrr
458
43.2k
    2422U,  // TA3
459
43.2k
    2427U,  // TA5
460
43.2k
    5883U,  // TADDCCTVri
461
43.2k
    5883U,  // TADDCCTVrr
462
43.2k
    4687U,  // TADDCCri
463
43.2k
    4687U,  // TADDCCrr
464
43.2k
    9873960U, // TICCri
465
43.2k
    9873960U, // TICCrr
466
43.2k
    37753544U,  // TLS_ADDXrr
467
43.2k
    37753544U,  // TLS_ADDrr
468
43.2k
    2106358U, // TLS_CALL
469
43.2k
    39746030U,  // TLS_LDXrr
470
43.2k
    39745985U,  // TLS_LDrr
471
43.2k
    5873U,  // TSUBCCTVri
472
43.2k
    5873U,  // TSUBCCTVrr
473
43.2k
    4670U,  // TSUBCCri
474
43.2k
    4670U,  // TSUBCCrr
475
43.2k
    10136104U,  // TXCCri
476
43.2k
    10136104U,  // TXCCrr
477
43.2k
    4756U,  // UDIVCCri
478
43.2k
    4756U,  // UDIVCCrr
479
43.2k
    6002U,  // UDIVXri
480
43.2k
    6002U,  // UDIVXrr
481
43.2k
    5867U,  // UDIVri
482
43.2k
    5867U,  // UDIVrr
483
43.2k
    4710U,  // UMULCCri
484
43.2k
    4710U,  // UMULCCrr
485
43.2k
    5026U,  // UMULXHI
486
43.2k
    5150U,  // UMULri
487
43.2k
    5150U,  // UMULrr
488
43.2k
    74996U, // UNIMP
489
43.2k
    6300477U, // V9FCMPD
490
43.2k
    6300397U, // V9FCMPED
491
43.2k
    6300942U, // V9FCMPEQ
492
43.2k
    6301251U, // V9FCMPES
493
43.2k
    6301000U, // V9FCMPQ
494
43.2k
    6301309U, // V9FCMPS
495
43.2k
    47614U, // V9FMOVD_FCC
496
43.2k
    47638U, // V9FMOVQ_FCC
497
43.2k
    47650U, // V9FMOVS_FCC
498
43.2k
    47658U, // V9MOVFCCri
499
43.2k
    47658U, // V9MOVFCCrr
500
43.2k
    14689692U,  // WRYri
501
43.2k
    14689692U,  // WRYrr
502
43.2k
    5953U,  // XMULX
503
43.2k
    5035U,  // XMULXHI
504
43.2k
    4733U,  // XNORCCri
505
43.2k
    4733U,  // XNORCCrr
506
43.2k
    5520U,  // XNORXrr
507
43.2k
    5520U,  // XNORri
508
43.2k
    5520U,  // XNORrr
509
43.2k
    4741U,  // XORCCri
510
43.2k
    4741U,  // XORCCrr
511
43.2k
    5527U,  // XORXri
512
43.2k
    5527U,  // XORXrr
513
43.2k
    5527U,  // XORri
514
43.2k
    5527U,  // XORrr
515
43.2k
    0U
516
43.2k
  };
517
518
43.2k
#ifndef CAPSTONE_DIET
519
43.2k
  static const char AsmStrs[] = {
520
43.2k
  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521
43.2k
  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522
43.2k
  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523
43.2k
  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524
43.2k
  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525
43.2k
  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526
43.2k
  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527
43.2k
  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528
43.2k
  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529
43.2k
  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530
43.2k
  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531
43.2k
  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532
43.2k
  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533
43.2k
  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534
43.2k
  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535
43.2k
  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536
43.2k
  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537
43.2k
  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538
43.2k
  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539
43.2k
  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540
43.2k
  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541
43.2k
  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542
43.2k
  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543
43.2k
  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544
43.2k
  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545
43.2k
  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546
43.2k
  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547
43.2k
  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548
43.2k
  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549
43.2k
  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550
43.2k
  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551
43.2k
  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552
43.2k
  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553
43.2k
  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554
43.2k
  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555
43.2k
  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556
43.2k
  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557
43.2k
  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558
43.2k
  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559
43.2k
  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560
43.2k
  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561
43.2k
  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562
43.2k
  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563
43.2k
  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564
43.2k
  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565
43.2k
  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566
43.2k
  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567
43.2k
  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568
43.2k
  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569
43.2k
  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570
43.2k
  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571
43.2k
  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572
43.2k
  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573
43.2k
  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574
43.2k
  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575
43.2k
  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576
43.2k
  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577
43.2k
  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578
43.2k
  /* 542 */ 'b', 'a', 32, 0,
579
43.2k
  /* 546 */ 's', 'r', 'a', 32, 0,
580
43.2k
  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581
43.2k
  /* 563 */ 's', 't', 'b', 32, 0,
582
43.2k
  /* 568 */ 's', 'u', 'b', 32, 0,
583
43.2k
  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584
43.2k
  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585
43.2k
  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586
43.2k
  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587
43.2k
  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588
43.2k
  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589
43.2k
  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590
43.2k
  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591
43.2k
  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592
43.2k
  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593
43.2k
  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594
43.2k
  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595
43.2k
  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596
43.2k
  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597
43.2k
  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598
43.2k
  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599
43.2k
  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600
43.2k
  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601
43.2k
  /* 711 */ 'a', 'd', 'd', 32, 0,
602
43.2k
  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603
43.2k
  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604
43.2k
  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605
43.2k
  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606
43.2k
  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607
43.2k
  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608
43.2k
  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609
43.2k
  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610
43.2k
  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611
43.2k
  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612
43.2k
  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613
43.2k
  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614
43.2k
  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615
43.2k
  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616
43.2k
  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617
43.2k
  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618
43.2k
  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619
43.2k
  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620
43.2k
  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621
43.2k
  /* 858 */ 's', 't', 'd', 32, 0,
622
43.2k
  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623
43.2k
  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624
43.2k
  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625
43.2k
  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626
43.2k
  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627
43.2k
  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628
43.2k
  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629
43.2k
  /* 917 */ 's', 't', 'h', 32, 0,
630
43.2k
  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631
43.2k
  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632
43.2k
  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633
43.2k
  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634
43.2k
  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635
43.2k
  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636
43.2k
  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637
43.2k
  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638
43.2k
  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639
43.2k
  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640
43.2k
  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641
43.2k
  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642
43.2k
  /* 1019 */ 's', 'l', 'l', 32, 0,
643
43.2k
  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644
43.2k
  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645
43.2k
  /* 1042 */ 's', 'r', 'l', 32, 0,
646
43.2k
  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647
43.2k
  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648
43.2k
  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649
43.2k
  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650
43.2k
  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651
43.2k
  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652
43.2k
  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653
43.2k
  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654
43.2k
  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655
43.2k
  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656
43.2k
  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657
43.2k
  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658
43.2k
  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659
43.2k
  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660
43.2k
  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661
43.2k
  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662
43.2k
  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663
43.2k
  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664
43.2k
  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665
43.2k
  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666
43.2k
  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667
43.2k
  /* 1242 */ 'o', 'r', 'n', 32, 0,
668
43.2k
  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669
43.2k
  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670
43.2k
  /* 1262 */ 'c', 'm', 'p', 32, 0,
671
43.2k
  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672
43.2k
  /* 1274 */ 'j', 'm', 'p', 32, 0,
673
43.2k
  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674
43.2k
  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675
43.2k
  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676
43.2k
  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677
43.2k
  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678
43.2k
  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679
43.2k
  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680
43.2k
  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681
43.2k
  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682
43.2k
  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683
43.2k
  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684
43.2k
  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685
43.2k
  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686
43.2k
  /* 1373 */ 's', 't', 'q', 32, 0,
687
43.2k
  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688
43.2k
  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689
43.2k
  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690
43.2k
  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691
43.2k
  /* 1411 */ 'f', 'o', 'r', 32, 0,
692
43.2k
  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693
43.2k
  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694
43.2k
  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695
43.2k
  /* 1435 */ 'w', 'r', 32, 0,
696
43.2k
  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697
43.2k
  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698
43.2k
  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699
43.2k
  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700
43.2k
  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701
43.2k
  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702
43.2k
  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703
43.2k
  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704
43.2k
  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705
43.2k
  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706
43.2k
  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707
43.2k
  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708
43.2k
  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709
43.2k
  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710
43.2k
  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711
43.2k
  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712
43.2k
  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713
43.2k
  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714
43.2k
  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715
43.2k
  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716
43.2k
  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717
43.2k
  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718
43.2k
  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719
43.2k
  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720
43.2k
  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721
43.2k
  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722
43.2k
  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723
43.2k
  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724
43.2k
  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725
43.2k
  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726
43.2k
  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727
43.2k
  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728
43.2k
  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729
43.2k
  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730
43.2k
  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731
43.2k
  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732
43.2k
  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733
43.2k
  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734
43.2k
  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735
43.2k
  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736
43.2k
  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737
43.2k
  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738
43.2k
  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739
43.2k
  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740
43.2k
  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741
43.2k
  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742
43.2k
  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743
43.2k
  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744
43.2k
  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745
43.2k
  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746
43.2k
  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747
43.2k
  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748
43.2k
  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749
43.2k
  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750
43.2k
  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751
43.2k
  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752
43.2k
  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753
43.2k
  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754
43.2k
  /* 1893 */ 's', 't', 'x', 32, 0,
755
43.2k
  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756
43.2k
  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757
43.2k
  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758
43.2k
  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759
43.2k
  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760
43.2k
  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761
43.2k
  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762
43.2k
  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763
43.2k
  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764
43.2k
  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765
43.2k
  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766
43.2k
  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767
43.2k
  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768
43.2k
  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769
43.2k
  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770
43.2k
  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771
43.2k
  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772
43.2k
  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773
43.2k
  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774
43.2k
  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775
43.2k
  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776
43.2k
  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777
43.2k
  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778
43.2k
  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779
43.2k
  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780
43.2k
  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781
43.2k
  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782
43.2k
  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783
43.2k
  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784
43.2k
  /* 2160 */ 'b', 'r', 'z', 32, 0,
785
43.2k
  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786
43.2k
  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787
43.2k
  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788
43.2k
  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789
43.2k
  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790
43.2k
  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791
43.2k
  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792
43.2k
  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793
43.2k
  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794
43.2k
  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795
43.2k
  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796
43.2k
  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797
43.2k
  /* 2421 */ 't', 'a', 32, '3', 0,
798
43.2k
  /* 2426 */ 't', 'a', 32, '5', 0,
799
43.2k
  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800
43.2k
  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801
43.2k
  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802
43.2k
  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803
43.2k
  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804
43.2k
  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805
43.2k
  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806
43.2k
  /* 2496 */ 'l', 'd', 32, '[', 0,
807
43.2k
  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808
43.2k
  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809
43.2k
  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810
43.2k
  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811
43.2k
  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812
43.2k
  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813
43.2k
  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814
43.2k
  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815
43.2k
  /* 2554 */ 'f', 'b', 0,
816
43.2k
  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817
43.2k
  /* 2563 */ 's', 'i', 'a', 'm', 0,
818
43.2k
  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819
43.2k
  /* 2577 */ 'n', 'o', 'p', 0,
820
43.2k
  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821
43.2k
  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822
43.2k
  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823
43.2k
  /* 2599 */ 't', 0,
824
43.2k
  /* 2601 */ 'm', 'o', 'v', 0,
825
43.2k
  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826
43.2k
  };
827
43.2k
#endif
828
829
  // Emit the opcode for the instruction.
830
43.2k
  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831
43.2k
#ifndef CAPSTONE_DIET
832
  // assert(Bits != 0 && "Cannot print this instruction.");
833
43.2k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834
43.2k
#endif
835
836
837
  // Fragment 0 encoded into 4 bits for 12 unique commands.
838
  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839
43.2k
  switch ((Bits >> 12) & 15) {
840
0
  default:   // unreachable.
841
109
  case 0:
842
    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843
109
    return;
844
0
    break;
845
9.43k
  case 1:
846
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847
9.43k
    printOperand(MI, 1, O); 
848
9.43k
    break;
849
25.5k
  case 2:
850
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851
25.5k
    printOperand(MI, 0, O); 
852
25.5k
    break;
853
3.37k
  case 3:
854
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855
3.37k
    printCCOperand(MI, 1, O); 
856
3.37k
    break;
857
38
  case 4:
858
    // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859
38
    printMemOperand(MI, 0, O, NULL); 
860
38
    return;
861
0
    break;
862
1.14k
  case 5:
863
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864
1.14k
    printCCOperand(MI, 3, O); 
865
1.14k
    break;
866
0
  case 6:
867
    // GETPCX
868
0
    printGetPCX(MI, 0, O); 
869
0
    return;
870
0
    break;
871
2.11k
  case 7:
872
    // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873
2.11k
    printMemOperand(MI, 1, O, NULL); 
874
2.11k
    break;
875
0
  case 8:
876
    // LEAX_ADDri, LEA_ADDri
877
0
    printMemOperand(MI, 1, O, "arith"); 
878
0
    SStream_concat0(O, ", "); 
879
0
    printOperand(MI, 0, O); 
880
0
    return;
881
0
    break;
882
587
  case 9:
883
    // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884
587
    printOperand(MI, 2, O); 
885
587
    SStream_concat0(O, ", ["); 
886
587
    printMemOperand(MI, 0, O, NULL); 
887
587
    SStream_concat0(O, "]"); 
888
587
    return;
889
0
    break;
890
29
  case 10:
891
    // TICCri, TICCrr, TXCCri, TXCCrr
892
29
    printCCOperand(MI, 2, O); 
893
29
    break;
894
913
  case 11:
895
    // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896
913
    printCCOperand(MI, 4, O); 
897
913
    SStream_concat0(O, " "); 
898
913
    printOperand(MI, 1, O); 
899
913
    SStream_concat0(O, ", "); 
900
913
    printOperand(MI, 2, O); 
901
913
    SStream_concat0(O, ", "); 
902
913
    printOperand(MI, 0, O); 
903
913
    return;
904
0
    break;
905
43.2k
  }
906
907
908
  // Fragment 1 encoded into 4 bits for 16 unique commands.
909
  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910
41.6k
  switch ((Bits >> 16) & 15) {
911
0
  default:   // unreachable.
912
13.6k
  case 0:
913
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914
13.6k
    SStream_concat0(O, ", "); 
915
13.6k
    break;
916
21.4k
  case 1:
917
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918
21.4k
    return;
919
0
    break;
920
835
  case 2:
921
    // BCOND, BPFCC, FBCOND
922
835
    SStream_concat0(O, " "); 
923
835
    break;
924
1.08k
  case 3:
925
    // BCONDA, BPFCCA, FBCONDA
926
1.08k
    SStream_concat0(O, ",a ");
927
1.08k
  Sparc_add_hint(MI, SPARC_HINT_A);
928
1.08k
    break;
929
0
  case 4:
930
    // BPFCCANT
931
0
    SStream_concat0(O, ",a,pn ");
932
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933
0
    printOperand(MI, 2, O); 
934
0
    SStream_concat0(O, ", "); 
935
0
    printOperand(MI, 0, O); 
936
0
    return;
937
0
    break;
938
0
  case 5:
939
    // BPFCCNT
940
0
    SStream_concat0(O, ",pn ");
941
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
942
0
    printOperand(MI, 2, O); 
943
0
    SStream_concat0(O, ", "); 
944
0
    printOperand(MI, 0, O); 
945
0
    return;
946
0
    break;
947
951
  case 6:
948
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949
951
    SStream_concat0(O, " %icc, ");
950
951
  Sparc_add_reg(MI, SPARC_REG_ICC);
951
951
    break;
952
215
  case 7:
953
    // BPICCA
954
215
    SStream_concat0(O, ",a %icc, ");
955
215
  Sparc_add_hint(MI, SPARC_HINT_A);
956
215
  Sparc_add_reg(MI, SPARC_REG_ICC);
957
215
    printOperand(MI, 0, O); 
958
215
    return;
959
0
    break;
960
0
  case 8:
961
    // BPICCANT
962
0
    SStream_concat0(O, ",a,pn %icc, ");
963
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
965
0
    printOperand(MI, 0, O); 
966
0
    return;
967
0
    break;
968
0
  case 9:
969
    // BPICCNT
970
0
    SStream_concat0(O, ",pn %icc, ");
971
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
972
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
973
0
    printOperand(MI, 0, O); 
974
0
    return;
975
0
    break;
976
1.09k
  case 10:
977
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978
1.09k
    SStream_concat0(O, " %xcc, ");
979
1.09k
  Sparc_add_reg(MI, SPARC_REG_XCC);
980
1.09k
    break;
981
116
  case 11:
982
    // BPXCCA
983
116
    SStream_concat0(O, ",a %xcc, ");
984
116
  Sparc_add_hint(MI, SPARC_HINT_A);
985
116
  Sparc_add_reg(MI, SPARC_REG_XCC);
986
116
    printOperand(MI, 0, O); 
987
116
    return;
988
0
    break;
989
0
  case 12:
990
    // BPXCCANT
991
0
    SStream_concat0(O, ",a,pn %xcc, ");
992
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
994
0
    printOperand(MI, 0, O); 
995
0
    return;
996
0
    break;
997
0
  case 13:
998
    // BPXCCNT
999
0
    SStream_concat0(O, ",pn %xcc, ");
1000
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
1001
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
1002
0
    printOperand(MI, 0, O); 
1003
0
    return;
1004
0
    break;
1005
2.03k
  case 14:
1006
    // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007
2.03k
    SStream_concat0(O, "], "); 
1008
2.03k
    break;
1009
263
  case 15:
1010
    // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011
263
    SStream_concat0(O, " %fcc0, ");
1012
263
  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013
263
    printOperand(MI, 1, O); 
1014
263
    SStream_concat0(O, ", "); 
1015
263
    printOperand(MI, 0, O); 
1016
263
    return;
1017
0
    break;
1018
41.6k
  }
1019
1020
1021
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022
  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023
19.6k
  switch ((Bits >> 20) & 3) {
1024
0
  default:   // unreachable.
1025
4.78k
  case 0:
1026
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027
4.78k
    printOperand(MI, 2, O); 
1028
4.78k
    SStream_concat0(O, ", "); 
1029
4.78k
    printOperand(MI, 0, O); 
1030
4.78k
    break;
1031
9.84k
  case 1:
1032
    // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033
9.84k
    printOperand(MI, 0, O); 
1034
9.84k
    break;
1035
5.00k
  case 2:
1036
    // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037
5.00k
    printOperand(MI, 1, O); 
1038
5.00k
    break;
1039
19.6k
  }
1040
1041
1042
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043
  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044
19.6k
  switch ((Bits >> 22) & 3) {
1045
0
  default:   // unreachable.
1046
16.8k
  case 0:
1047
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048
16.8k
    return;
1049
0
    break;
1050
2.72k
  case 1:
1051
    // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052
2.72k
    SStream_concat0(O, ", "); 
1053
2.72k
    break;
1054
29
  case 2:
1055
    // TICCri, TICCrr, TXCCri, TXCCrr
1056
29
    SStream_concat0(O, " + ");  // qq
1057
29
    printOperand(MI, 1, O); 
1058
29
    return;
1059
0
    break;
1060
56
  case 3:
1061
    // WRYri, WRYrr
1062
56
    SStream_concat0(O, ", %y");
1063
56
  Sparc_add_reg(MI, SPARC_REG_Y);
1064
56
    return;
1065
0
    break;
1066
19.6k
  }
1067
1068
1069
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070
  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071
2.72k
  switch ((Bits >> 24) & 3) {
1072
0
  default:   // unreachable.
1073
1.83k
  case 0:
1074
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075
1.83k
    printOperand(MI, 2, O); 
1076
1.83k
    return;
1077
0
    break;
1078
884
  case 1:
1079
    // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080
884
    printOperand(MI, 0, O); 
1081
884
    return;
1082
0
    break;
1083
0
  case 2:
1084
    // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085
0
    printOperand(MI, 3, O); 
1086
0
    return;
1087
0
    break;
1088
2.72k
  }
1089
2.72k
}
1090
1091
1092
/// getRegisterName - This method is automatically generated by tblgen
1093
/// from the register set description.  This returns the assembler name
1094
/// for the specified register.
1095
static const char *getRegisterName(unsigned RegNo)
1096
47.5k
{
1097
  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098
1099
47.5k
#ifndef CAPSTONE_DIET
1100
47.5k
  static const char AsmStrs[] = {
1101
47.5k
  /* 0 */ 'f', '1', '0', 0,
1102
47.5k
  /* 4 */ 'f', '2', '0', 0,
1103
47.5k
  /* 8 */ 'f', '3', '0', 0,
1104
47.5k
  /* 12 */ 'f', '4', '0', 0,
1105
47.5k
  /* 16 */ 'f', '5', '0', 0,
1106
47.5k
  /* 20 */ 'f', '6', '0', 0,
1107
47.5k
  /* 24 */ 'f', 'c', 'c', '0', 0,
1108
47.5k
  /* 29 */ 'f', '0', 0,
1109
47.5k
  /* 32 */ 'g', '0', 0,
1110
47.5k
  /* 35 */ 'i', '0', 0,
1111
47.5k
  /* 38 */ 'l', '0', 0,
1112
47.5k
  /* 41 */ 'o', '0', 0,
1113
47.5k
  /* 44 */ 'f', '1', '1', 0,
1114
47.5k
  /* 48 */ 'f', '2', '1', 0,
1115
47.5k
  /* 52 */ 'f', '3', '1', 0,
1116
47.5k
  /* 56 */ 'f', 'c', 'c', '1', 0,
1117
47.5k
  /* 61 */ 'f', '1', 0,
1118
47.5k
  /* 64 */ 'g', '1', 0,
1119
47.5k
  /* 67 */ 'i', '1', 0,
1120
47.5k
  /* 70 */ 'l', '1', 0,
1121
47.5k
  /* 73 */ 'o', '1', 0,
1122
47.5k
  /* 76 */ 'f', '1', '2', 0,
1123
47.5k
  /* 80 */ 'f', '2', '2', 0,
1124
47.5k
  /* 84 */ 'f', '3', '2', 0,
1125
47.5k
  /* 88 */ 'f', '4', '2', 0,
1126
47.5k
  /* 92 */ 'f', '5', '2', 0,
1127
47.5k
  /* 96 */ 'f', '6', '2', 0,
1128
47.5k
  /* 100 */ 'f', 'c', 'c', '2', 0,
1129
47.5k
  /* 105 */ 'f', '2', 0,
1130
47.5k
  /* 108 */ 'g', '2', 0,
1131
47.5k
  /* 111 */ 'i', '2', 0,
1132
47.5k
  /* 114 */ 'l', '2', 0,
1133
47.5k
  /* 117 */ 'o', '2', 0,
1134
47.5k
  /* 120 */ 'f', '1', '3', 0,
1135
47.5k
  /* 124 */ 'f', '2', '3', 0,
1136
47.5k
  /* 128 */ 'f', 'c', 'c', '3', 0,
1137
47.5k
  /* 133 */ 'f', '3', 0,
1138
47.5k
  /* 136 */ 'g', '3', 0,
1139
47.5k
  /* 139 */ 'i', '3', 0,
1140
47.5k
  /* 142 */ 'l', '3', 0,
1141
47.5k
  /* 145 */ 'o', '3', 0,
1142
47.5k
  /* 148 */ 'f', '1', '4', 0,
1143
47.5k
  /* 152 */ 'f', '2', '4', 0,
1144
47.5k
  /* 156 */ 'f', '3', '4', 0,
1145
47.5k
  /* 160 */ 'f', '4', '4', 0,
1146
47.5k
  /* 164 */ 'f', '5', '4', 0,
1147
47.5k
  /* 168 */ 'f', '4', 0,
1148
47.5k
  /* 171 */ 'g', '4', 0,
1149
47.5k
  /* 174 */ 'i', '4', 0,
1150
47.5k
  /* 177 */ 'l', '4', 0,
1151
47.5k
  /* 180 */ 'o', '4', 0,
1152
47.5k
  /* 183 */ 'f', '1', '5', 0,
1153
47.5k
  /* 187 */ 'f', '2', '5', 0,
1154
47.5k
  /* 191 */ 'f', '5', 0,
1155
47.5k
  /* 194 */ 'g', '5', 0,
1156
47.5k
  /* 197 */ 'i', '5', 0,
1157
47.5k
  /* 200 */ 'l', '5', 0,
1158
47.5k
  /* 203 */ 'o', '5', 0,
1159
47.5k
  /* 206 */ 'f', '1', '6', 0,
1160
47.5k
  /* 210 */ 'f', '2', '6', 0,
1161
47.5k
  /* 214 */ 'f', '3', '6', 0,
1162
47.5k
  /* 218 */ 'f', '4', '6', 0,
1163
47.5k
  /* 222 */ 'f', '5', '6', 0,
1164
47.5k
  /* 226 */ 'f', '6', 0,
1165
47.5k
  /* 229 */ 'g', '6', 0,
1166
47.5k
  /* 232 */ 'l', '6', 0,
1167
47.5k
  /* 235 */ 'f', '1', '7', 0,
1168
47.5k
  /* 239 */ 'f', '2', '7', 0,
1169
47.5k
  /* 243 */ 'f', '7', 0,
1170
47.5k
  /* 246 */ 'g', '7', 0,
1171
47.5k
  /* 249 */ 'i', '7', 0,
1172
47.5k
  /* 252 */ 'l', '7', 0,
1173
47.5k
  /* 255 */ 'o', '7', 0,
1174
47.5k
  /* 258 */ 'f', '1', '8', 0,
1175
47.5k
  /* 262 */ 'f', '2', '8', 0,
1176
47.5k
  /* 266 */ 'f', '3', '8', 0,
1177
47.5k
  /* 270 */ 'f', '4', '8', 0,
1178
47.5k
  /* 274 */ 'f', '5', '8', 0,
1179
47.5k
  /* 278 */ 'f', '8', 0,
1180
47.5k
  /* 281 */ 'f', '1', '9', 0,
1181
47.5k
  /* 285 */ 'f', '2', '9', 0,
1182
47.5k
  /* 289 */ 'f', '9', 0,
1183
47.5k
  /* 292 */ 'i', 'c', 'c', 0,
1184
47.5k
  /* 296 */ 'f', 'p', 0,
1185
47.5k
  /* 299 */ 's', 'p', 0,
1186
47.5k
  /* 302 */ 'y', 0,
1187
47.5k
  };
1188
1189
47.5k
  static const uint16_t RegAsmOffset[] = {
1190
47.5k
    292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 
1191
47.5k
    152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 
1192
47.5k
    92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 
1193
47.5k
    278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 
1194
47.5k
    80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 
1195
47.5k
    32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 
1196
47.5k
    296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 
1197
47.5k
    180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 
1198
47.5k
    12, 160, 270, 92, 222, 20, 
1199
47.5k
  };
1200
1201
  //int i;
1202
  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203
  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204
  //printf("*************************\n");
1205
47.5k
  return AsmStrs+RegAsmOffset[RegNo-1];
1206
#else
1207
  return NULL;
1208
#endif
1209
47.5k
}
1210
1211
#ifdef PRINT_ALIAS_INSTR
1212
#undef PRINT_ALIAS_INSTR
1213
1214
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1215
  unsigned PrintMethodIdx, SStream *OS)
1216
0
{
1217
0
}
1218
1219
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1220
68.4k
{
1221
159k
  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1222
68.4k
  const char *AsmString;
1223
68.4k
  char *tmp, *AsmMnem, *AsmOps, *c;
1224
68.4k
  int OpIdx, PrintMethodIdx;
1225
68.4k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1226
68.4k
  switch (MCInst_getOpcode(MI)) {
1227
39.7k
  default: return NULL;
1228
3.53k
  case SP_BCOND:
1229
3.53k
    if (MCInst_getNumOperands(MI) == 2 &&
1230
3.53k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1231
3.53k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1232
      // (BCOND brtarget:$imm, 8)
1233
0
      AsmString = "ba $\x01";
1234
0
      break;
1235
0
    }
1236
3.53k
    if (MCInst_getNumOperands(MI) == 2 &&
1237
3.53k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1238
3.53k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1239
      // (BCOND brtarget:$imm, 0)
1240
1.19k
      AsmString = "bn $\x01";
1241
1.19k
      break;
1242
1.19k
    }
1243
2.34k
    if (MCInst_getNumOperands(MI) == 2 &&
1244
2.34k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1245
2.34k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1246
      // (BCOND brtarget:$imm, 9)
1247
23
      AsmString = "bne $\x01";
1248
23
      break;
1249
23
    }
1250
2.31k
    if (MCInst_getNumOperands(MI) == 2 &&
1251
2.31k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1252
2.31k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1253
      // (BCOND brtarget:$imm, 1)
1254
91
      AsmString = "be $\x01";
1255
91
      break;
1256
91
    }
1257
2.22k
    if (MCInst_getNumOperands(MI) == 2 &&
1258
2.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1259
2.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1260
      // (BCOND brtarget:$imm, 10)
1261
68
      AsmString = "bg $\x01";
1262
68
      break;
1263
68
    }
1264
2.16k
    if (MCInst_getNumOperands(MI) == 2 &&
1265
2.16k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1266
2.16k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1267
      // (BCOND brtarget:$imm, 2)
1268
522
      AsmString = "ble $\x01";
1269
522
      break;
1270
522
    }
1271
1.63k
    if (MCInst_getNumOperands(MI) == 2 &&
1272
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1273
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1274
      // (BCOND brtarget:$imm, 11)
1275
38
      AsmString = "bge $\x01";
1276
38
      break;
1277
38
    }
1278
1.60k
    if (MCInst_getNumOperands(MI) == 2 &&
1279
1.60k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1280
1.60k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1281
      // (BCOND brtarget:$imm, 3)
1282
371
      AsmString = "bl $\x01";
1283
371
      break;
1284
371
    }
1285
1.22k
    if (MCInst_getNumOperands(MI) == 2 &&
1286
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1287
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1288
      // (BCOND brtarget:$imm, 12)
1289
71
      AsmString = "bgu $\x01";
1290
71
      break;
1291
71
    }
1292
1.15k
    if (MCInst_getNumOperands(MI) == 2 &&
1293
1.15k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1294
1.15k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1295
      // (BCOND brtarget:$imm, 4)
1296
205
      AsmString = "bleu $\x01";
1297
205
      break;
1298
205
    }
1299
953
    if (MCInst_getNumOperands(MI) == 2 &&
1300
953
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1301
953
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1302
      // (BCOND brtarget:$imm, 13)
1303
90
      AsmString = "bcc $\x01";
1304
90
      break;
1305
90
    }
1306
863
    if (MCInst_getNumOperands(MI) == 2 &&
1307
863
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1308
863
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1309
      // (BCOND brtarget:$imm, 5)
1310
74
      AsmString = "bcs $\x01";
1311
74
      break;
1312
74
    }
1313
789
    if (MCInst_getNumOperands(MI) == 2 &&
1314
789
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1315
789
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1316
      // (BCOND brtarget:$imm, 14)
1317
54
      AsmString = "bpos $\x01";
1318
54
      break;
1319
54
    }
1320
735
    if (MCInst_getNumOperands(MI) == 2 &&
1321
735
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1322
735
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1323
      // (BCOND brtarget:$imm, 6)
1324
325
      AsmString = "bneg $\x01";
1325
325
      break;
1326
325
    }
1327
410
    if (MCInst_getNumOperands(MI) == 2 &&
1328
410
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1329
410
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1330
      // (BCOND brtarget:$imm, 15)
1331
276
      AsmString = "bvc $\x01";
1332
276
      break;
1333
276
    }
1334
134
    if (MCInst_getNumOperands(MI) == 2 &&
1335
134
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1336
134
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1337
      // (BCOND brtarget:$imm, 7)
1338
134
      AsmString = "bvs $\x01";
1339
134
      break;
1340
134
    }
1341
0
    return NULL;
1342
3.10k
  case SP_BCONDA:
1343
3.10k
    if (MCInst_getNumOperands(MI) == 2 &&
1344
3.10k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1345
3.10k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1346
      // (BCONDA brtarget:$imm, 8)
1347
115
      AsmString = "ba,a $\x01";
1348
115
      break;
1349
115
    }
1350
2.98k
    if (MCInst_getNumOperands(MI) == 2 &&
1351
2.98k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1352
2.98k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1353
      // (BCONDA brtarget:$imm, 0)
1354
197
      AsmString = "bn,a $\x01";
1355
197
      break;
1356
197
    }
1357
2.79k
    if (MCInst_getNumOperands(MI) == 2 &&
1358
2.79k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1359
2.79k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1360
      // (BCONDA brtarget:$imm, 9)
1361
78
      AsmString = "bne,a $\x01";
1362
78
      break;
1363
78
    }
1364
2.71k
    if (MCInst_getNumOperands(MI) == 2 &&
1365
2.71k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1366
2.71k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1367
      // (BCONDA brtarget:$imm, 1)
1368
481
      AsmString = "be,a $\x01";
1369
481
      break;
1370
481
    }
1371
2.23k
    if (MCInst_getNumOperands(MI) == 2 &&
1372
2.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1373
2.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1374
      // (BCONDA brtarget:$imm, 10)
1375
233
      AsmString = "bg,a $\x01";
1376
233
      break;
1377
233
    }
1378
1.99k
    if (MCInst_getNumOperands(MI) == 2 &&
1379
1.99k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1380
1.99k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1381
      // (BCONDA brtarget:$imm, 2)
1382
335
      AsmString = "ble,a $\x01";
1383
335
      break;
1384
335
    }
1385
1.66k
    if (MCInst_getNumOperands(MI) == 2 &&
1386
1.66k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1387
1.66k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1388
      // (BCONDA brtarget:$imm, 11)
1389
214
      AsmString = "bge,a $\x01";
1390
214
      break;
1391
214
    }
1392
1.44k
    if (MCInst_getNumOperands(MI) == 2 &&
1393
1.44k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1394
1.44k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1395
      // (BCONDA brtarget:$imm, 3)
1396
71
      AsmString = "bl,a $\x01";
1397
71
      break;
1398
71
    }
1399
1.37k
    if (MCInst_getNumOperands(MI) == 2 &&
1400
1.37k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1401
1.37k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1402
      // (BCONDA brtarget:$imm, 12)
1403
84
      AsmString = "bgu,a $\x01";
1404
84
      break;
1405
84
    }
1406
1.29k
    if (MCInst_getNumOperands(MI) == 2 &&
1407
1.29k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1408
1.29k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1409
      // (BCONDA brtarget:$imm, 4)
1410
79
      AsmString = "bleu,a $\x01";
1411
79
      break;
1412
79
    }
1413
1.21k
    if (MCInst_getNumOperands(MI) == 2 &&
1414
1.21k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1415
1.21k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1416
      // (BCONDA brtarget:$imm, 13)
1417
240
      AsmString = "bcc,a $\x01";
1418
240
      break;
1419
240
    }
1420
975
    if (MCInst_getNumOperands(MI) == 2 &&
1421
975
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1422
975
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1423
      // (BCONDA brtarget:$imm, 5)
1424
98
      AsmString = "bcs,a $\x01";
1425
98
      break;
1426
98
    }
1427
877
    if (MCInst_getNumOperands(MI) == 2 &&
1428
877
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1429
877
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1430
      // (BCONDA brtarget:$imm, 14)
1431
206
      AsmString = "bpos,a $\x01";
1432
206
      break;
1433
206
    }
1434
671
    if (MCInst_getNumOperands(MI) == 2 &&
1435
671
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1436
671
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1437
      // (BCONDA brtarget:$imm, 6)
1438
206
      AsmString = "bneg,a $\x01";
1439
206
      break;
1440
206
    }
1441
465
    if (MCInst_getNumOperands(MI) == 2 &&
1442
465
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1443
465
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1444
      // (BCONDA brtarget:$imm, 15)
1445
80
      AsmString = "bvc,a $\x01";
1446
80
      break;
1447
80
    }
1448
385
    if (MCInst_getNumOperands(MI) == 2 &&
1449
385
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1450
385
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1451
      // (BCONDA brtarget:$imm, 7)
1452
385
      AsmString = "bvs,a $\x01";
1453
385
      break;
1454
385
    }
1455
0
    return NULL;
1456
2.63k
  case SP_BPFCCANT:
1457
2.63k
    if (MCInst_getNumOperands(MI) == 3 &&
1458
2.63k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1459
2.63k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1460
2.63k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1461
2.63k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1462
      // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1463
298
      AsmString = "fba,a,pn $\x03, $\x01";
1464
298
      break;
1465
298
    }
1466
2.33k
    if (MCInst_getNumOperands(MI) == 3 &&
1467
2.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1468
2.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1469
2.33k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1470
2.33k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1471
      // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1472
269
      AsmString = "fbn,a,pn $\x03, $\x01";
1473
269
      break;
1474
269
    }
1475
2.06k
    if (MCInst_getNumOperands(MI) == 3 &&
1476
2.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1477
2.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1478
2.06k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1479
2.06k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1480
      // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1481
222
      AsmString = "fbu,a,pn $\x03, $\x01";
1482
222
      break;
1483
222
    }
1484
1.84k
    if (MCInst_getNumOperands(MI) == 3 &&
1485
1.84k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1486
1.84k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1487
1.84k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1488
1.84k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1489
      // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1490
71
      AsmString = "fbg,a,pn $\x03, $\x01";
1491
71
      break;
1492
71
    }
1493
1.77k
    if (MCInst_getNumOperands(MI) == 3 &&
1494
1.77k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1495
1.77k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1496
1.77k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1497
1.77k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1498
      // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1499
91
      AsmString = "fbug,a,pn $\x03, $\x01";
1500
91
      break;
1501
91
    }
1502
1.68k
    if (MCInst_getNumOperands(MI) == 3 &&
1503
1.68k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1504
1.68k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1505
1.68k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1506
1.68k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1507
      // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1508
90
      AsmString = "fbl,a,pn $\x03, $\x01";
1509
90
      break;
1510
90
    }
1511
1.59k
    if (MCInst_getNumOperands(MI) == 3 &&
1512
1.59k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1513
1.59k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1514
1.59k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1515
1.59k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1516
      // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1517
168
      AsmString = "fbul,a,pn $\x03, $\x01";
1518
168
      break;
1519
168
    }
1520
1.42k
    if (MCInst_getNumOperands(MI) == 3 &&
1521
1.42k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1522
1.42k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1523
1.42k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1524
1.42k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1525
      // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1526
59
      AsmString = "fblg,a,pn $\x03, $\x01";
1527
59
      break;
1528
59
    }
1529
1.36k
    if (MCInst_getNumOperands(MI) == 3 &&
1530
1.36k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1531
1.36k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1532
1.36k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1533
1.36k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1534
      // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1535
78
      AsmString = "fbne,a,pn $\x03, $\x01";
1536
78
      break;
1537
78
    }
1538
1.28k
    if (MCInst_getNumOperands(MI) == 3 &&
1539
1.28k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1540
1.28k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1541
1.28k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1542
1.28k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1543
      // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1544
108
      AsmString = "fbe,a,pn $\x03, $\x01";
1545
108
      break;
1546
108
    }
1547
1.17k
    if (MCInst_getNumOperands(MI) == 3 &&
1548
1.17k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1549
1.17k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1550
1.17k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1551
1.17k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1552
      // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1553
43
      AsmString = "fbue,a,pn $\x03, $\x01";
1554
43
      break;
1555
43
    }
1556
1.13k
    if (MCInst_getNumOperands(MI) == 3 &&
1557
1.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1558
1.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1559
1.13k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1560
1.13k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1561
      // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1562
267
      AsmString = "fbge,a,pn $\x03, $\x01";
1563
267
      break;
1564
267
    }
1565
868
    if (MCInst_getNumOperands(MI) == 3 &&
1566
868
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1567
868
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1568
868
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1569
868
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1570
      // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1571
86
      AsmString = "fbuge,a,pn $\x03, $\x01";
1572
86
      break;
1573
86
    }
1574
782
    if (MCInst_getNumOperands(MI) == 3 &&
1575
782
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1576
782
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1577
782
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1578
782
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1579
      // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1580
301
      AsmString = "fble,a,pn $\x03, $\x01";
1581
301
      break;
1582
301
    }
1583
481
    if (MCInst_getNumOperands(MI) == 3 &&
1584
481
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1585
481
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1586
481
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1587
481
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1588
      // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1589
257
      AsmString = "fbule,a,pn $\x03, $\x01";
1590
257
      break;
1591
257
    }
1592
224
    if (MCInst_getNumOperands(MI) == 3 &&
1593
224
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1594
224
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1595
224
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1596
224
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1597
      // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1598
224
      AsmString = "fbo,a,pn $\x03, $\x01";
1599
224
      break;
1600
224
    }
1601
0
    return NULL;
1602
3.28k
  case SP_BPFCCNT:
1603
3.28k
    if (MCInst_getNumOperands(MI) == 3 &&
1604
3.28k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1605
3.28k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1606
3.28k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1607
3.28k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1608
      // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1609
235
      AsmString = "fba,pn $\x03, $\x01";
1610
235
      break;
1611
235
    }
1612
3.04k
    if (MCInst_getNumOperands(MI) == 3 &&
1613
3.04k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1614
3.04k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1615
3.04k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1616
3.04k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1617
      // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1618
549
      AsmString = "fbn,pn $\x03, $\x01";
1619
549
      break;
1620
549
    }
1621
2.50k
    if (MCInst_getNumOperands(MI) == 3 &&
1622
2.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
2.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1624
2.50k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1625
2.50k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1626
      // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1627
379
      AsmString = "fbu,pn $\x03, $\x01";
1628
379
      break;
1629
379
    }
1630
2.12k
    if (MCInst_getNumOperands(MI) == 3 &&
1631
2.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1632
2.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1633
2.12k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1634
2.12k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1635
      // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1636
309
      AsmString = "fbg,pn $\x03, $\x01";
1637
309
      break;
1638
309
    }
1639
1.81k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
1.81k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1641
1.81k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1642
1.81k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1643
1.81k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1644
      // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1645
54
      AsmString = "fbug,pn $\x03, $\x01";
1646
54
      break;
1647
54
    }
1648
1.75k
    if (MCInst_getNumOperands(MI) == 3 &&
1649
1.75k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1650
1.75k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1651
1.75k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1652
1.75k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1653
      // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1654
125
      AsmString = "fbl,pn $\x03, $\x01";
1655
125
      break;
1656
125
    }
1657
1.63k
    if (MCInst_getNumOperands(MI) == 3 &&
1658
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1659
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1660
1.63k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1661
1.63k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1662
      // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1663
214
      AsmString = "fbul,pn $\x03, $\x01";
1664
214
      break;
1665
214
    }
1666
1.41k
    if (MCInst_getNumOperands(MI) == 3 &&
1667
1.41k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1668
1.41k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1669
1.41k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1670
1.41k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1671
      // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1672
205
      AsmString = "fblg,pn $\x03, $\x01";
1673
205
      break;
1674
205
    }
1675
1.21k
    if (MCInst_getNumOperands(MI) == 3 &&
1676
1.21k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1677
1.21k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1678
1.21k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1679
1.21k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1680
      // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1681
230
      AsmString = "fbne,pn $\x03, $\x01";
1682
230
      break;
1683
230
    }
1684
984
    if (MCInst_getNumOperands(MI) == 3 &&
1685
984
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1686
984
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1687
984
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1688
984
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1689
      // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1690
286
      AsmString = "fbe,pn $\x03, $\x01";
1691
286
      break;
1692
286
    }
1693
698
    if (MCInst_getNumOperands(MI) == 3 &&
1694
698
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1695
698
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1696
698
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1697
698
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1698
      // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1699
43
      AsmString = "fbue,pn $\x03, $\x01";
1700
43
      break;
1701
43
    }
1702
655
    if (MCInst_getNumOperands(MI) == 3 &&
1703
655
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1704
655
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1705
655
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1706
655
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1707
      // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1708
71
      AsmString = "fbge,pn $\x03, $\x01";
1709
71
      break;
1710
71
    }
1711
584
    if (MCInst_getNumOperands(MI) == 3 &&
1712
584
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1713
584
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1714
584
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1715
584
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1716
      // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1717
213
      AsmString = "fbuge,pn $\x03, $\x01";
1718
213
      break;
1719
213
    }
1720
371
    if (MCInst_getNumOperands(MI) == 3 &&
1721
371
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1722
371
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1723
371
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1724
371
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1725
      // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1726
84
      AsmString = "fble,pn $\x03, $\x01";
1727
84
      break;
1728
84
    }
1729
287
    if (MCInst_getNumOperands(MI) == 3 &&
1730
287
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1731
287
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1732
287
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1733
287
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1734
      // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1735
198
      AsmString = "fbule,pn $\x03, $\x01";
1736
198
      break;
1737
198
    }
1738
89
    if (MCInst_getNumOperands(MI) == 3 &&
1739
89
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1740
89
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1741
89
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1742
89
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1743
      // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1744
89
      AsmString = "fbo,pn $\x03, $\x01";
1745
89
      break;
1746
89
    }
1747
0
    return NULL;
1748
1.98k
  case SP_BPICCANT:
1749
1.98k
    if (MCInst_getNumOperands(MI) == 2 &&
1750
1.98k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1751
1.98k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1752
      // (BPICCANT brtarget:$imm, 8)
1753
102
      AsmString = "ba,a,pn %icc, $\x01";
1754
102
      break;
1755
102
    }
1756
1.88k
    if (MCInst_getNumOperands(MI) == 2 &&
1757
1.88k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
1.88k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1759
      // (BPICCANT brtarget:$imm, 0)
1760
171
      AsmString = "bn,a,pn %icc, $\x01";
1761
171
      break;
1762
171
    }
1763
1.71k
    if (MCInst_getNumOperands(MI) == 2 &&
1764
1.71k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1765
1.71k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1766
      // (BPICCANT brtarget:$imm, 9)
1767
56
      AsmString = "bne,a,pn %icc, $\x01";
1768
56
      break;
1769
56
    }
1770
1.65k
    if (MCInst_getNumOperands(MI) == 2 &&
1771
1.65k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1772
1.65k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1773
      // (BPICCANT brtarget:$imm, 1)
1774
210
      AsmString = "be,a,pn %icc, $\x01";
1775
210
      break;
1776
210
    }
1777
1.44k
    if (MCInst_getNumOperands(MI) == 2 &&
1778
1.44k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1779
1.44k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1780
      // (BPICCANT brtarget:$imm, 10)
1781
248
      AsmString = "bg,a,pn %icc, $\x01";
1782
248
      break;
1783
248
    }
1784
1.19k
    if (MCInst_getNumOperands(MI) == 2 &&
1785
1.19k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1786
1.19k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1787
      // (BPICCANT brtarget:$imm, 2)
1788
130
      AsmString = "ble,a,pn %icc, $\x01";
1789
130
      break;
1790
130
    }
1791
1.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1792
1.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1793
1.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1794
      // (BPICCANT brtarget:$imm, 11)
1795
82
      AsmString = "bge,a,pn %icc, $\x01";
1796
82
      break;
1797
82
    }
1798
984
    if (MCInst_getNumOperands(MI) == 2 &&
1799
984
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1800
984
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1801
      // (BPICCANT brtarget:$imm, 3)
1802
36
      AsmString = "bl,a,pn %icc, $\x01";
1803
36
      break;
1804
36
    }
1805
948
    if (MCInst_getNumOperands(MI) == 2 &&
1806
948
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1807
948
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1808
      // (BPICCANT brtarget:$imm, 12)
1809
42
      AsmString = "bgu,a,pn %icc, $\x01";
1810
42
      break;
1811
42
    }
1812
906
    if (MCInst_getNumOperands(MI) == 2 &&
1813
906
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1814
906
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1815
      // (BPICCANT brtarget:$imm, 4)
1816
391
      AsmString = "bleu,a,pn %icc, $\x01";
1817
391
      break;
1818
391
    }
1819
515
    if (MCInst_getNumOperands(MI) == 2 &&
1820
515
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1821
515
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1822
      // (BPICCANT brtarget:$imm, 13)
1823
89
      AsmString = "bcc,a,pn %icc, $\x01";
1824
89
      break;
1825
89
    }
1826
426
    if (MCInst_getNumOperands(MI) == 2 &&
1827
426
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1828
426
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1829
      // (BPICCANT brtarget:$imm, 5)
1830
49
      AsmString = "bcs,a,pn %icc, $\x01";
1831
49
      break;
1832
49
    }
1833
377
    if (MCInst_getNumOperands(MI) == 2 &&
1834
377
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1835
377
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1836
      // (BPICCANT brtarget:$imm, 14)
1837
80
      AsmString = "bpos,a,pn %icc, $\x01";
1838
80
      break;
1839
80
    }
1840
297
    if (MCInst_getNumOperands(MI) == 2 &&
1841
297
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1842
297
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1843
      // (BPICCANT brtarget:$imm, 6)
1844
78
      AsmString = "bneg,a,pn %icc, $\x01";
1845
78
      break;
1846
78
    }
1847
219
    if (MCInst_getNumOperands(MI) == 2 &&
1848
219
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1849
219
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1850
      // (BPICCANT brtarget:$imm, 15)
1851
135
      AsmString = "bvc,a,pn %icc, $\x01";
1852
135
      break;
1853
135
    }
1854
84
    if (MCInst_getNumOperands(MI) == 2 &&
1855
84
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1856
84
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1857
      // (BPICCANT brtarget:$imm, 7)
1858
84
      AsmString = "bvs,a,pn %icc, $\x01";
1859
84
      break;
1860
84
    }
1861
0
    return NULL;
1862
2.17k
  case SP_BPICCNT:
1863
2.17k
    if (MCInst_getNumOperands(MI) == 2 &&
1864
2.17k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1865
2.17k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1866
      // (BPICCNT brtarget:$imm, 8)
1867
83
      AsmString = "ba,pn %icc, $\x01";
1868
83
      break;
1869
83
    }
1870
2.09k
    if (MCInst_getNumOperands(MI) == 2 &&
1871
2.09k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1872
2.09k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1873
      // (BPICCNT brtarget:$imm, 0)
1874
349
      AsmString = "bn,pn %icc, $\x01";
1875
349
      break;
1876
349
    }
1877
1.74k
    if (MCInst_getNumOperands(MI) == 2 &&
1878
1.74k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1879
1.74k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1880
      // (BPICCNT brtarget:$imm, 9)
1881
88
      AsmString = "bne,pn %icc, $\x01";
1882
88
      break;
1883
88
    }
1884
1.65k
    if (MCInst_getNumOperands(MI) == 2 &&
1885
1.65k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1886
1.65k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1887
      // (BPICCNT brtarget:$imm, 1)
1888
248
      AsmString = "be,pn %icc, $\x01";
1889
248
      break;
1890
248
    }
1891
1.40k
    if (MCInst_getNumOperands(MI) == 2 &&
1892
1.40k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1893
1.40k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1894
      // (BPICCNT brtarget:$imm, 10)
1895
194
      AsmString = "bg,pn %icc, $\x01";
1896
194
      break;
1897
194
    }
1898
1.21k
    if (MCInst_getNumOperands(MI) == 2 &&
1899
1.21k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1900
1.21k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1901
      // (BPICCNT brtarget:$imm, 2)
1902
80
      AsmString = "ble,pn %icc, $\x01";
1903
80
      break;
1904
80
    }
1905
1.13k
    if (MCInst_getNumOperands(MI) == 2 &&
1906
1.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1907
1.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1908
      // (BPICCNT brtarget:$imm, 11)
1909
123
      AsmString = "bge,pn %icc, $\x01";
1910
123
      break;
1911
123
    }
1912
1.00k
    if (MCInst_getNumOperands(MI) == 2 &&
1913
1.00k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1914
1.00k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1915
      // (BPICCNT brtarget:$imm, 3)
1916
103
      AsmString = "bl,pn %icc, $\x01";
1917
103
      break;
1918
103
    }
1919
906
    if (MCInst_getNumOperands(MI) == 2 &&
1920
906
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1921
906
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1922
      // (BPICCNT brtarget:$imm, 12)
1923
69
      AsmString = "bgu,pn %icc, $\x01";
1924
69
      break;
1925
69
    }
1926
837
    if (MCInst_getNumOperands(MI) == 2 &&
1927
837
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1928
837
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1929
      // (BPICCNT brtarget:$imm, 4)
1930
105
      AsmString = "bleu,pn %icc, $\x01";
1931
105
      break;
1932
105
    }
1933
732
    if (MCInst_getNumOperands(MI) == 2 &&
1934
732
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1935
732
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1936
      // (BPICCNT brtarget:$imm, 13)
1937
18
      AsmString = "bcc,pn %icc, $\x01";
1938
18
      break;
1939
18
    }
1940
714
    if (MCInst_getNumOperands(MI) == 2 &&
1941
714
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1942
714
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1943
      // (BPICCNT brtarget:$imm, 5)
1944
45
      AsmString = "bcs,pn %icc, $\x01";
1945
45
      break;
1946
45
    }
1947
669
    if (MCInst_getNumOperands(MI) == 2 &&
1948
669
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1949
669
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1950
      // (BPICCNT brtarget:$imm, 14)
1951
76
      AsmString = "bpos,pn %icc, $\x01";
1952
76
      break;
1953
76
    }
1954
593
    if (MCInst_getNumOperands(MI) == 2 &&
1955
593
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1956
593
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1957
      // (BPICCNT brtarget:$imm, 6)
1958
340
      AsmString = "bneg,pn %icc, $\x01";
1959
340
      break;
1960
340
    }
1961
253
    if (MCInst_getNumOperands(MI) == 2 &&
1962
253
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1963
253
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1964
      // (BPICCNT brtarget:$imm, 15)
1965
142
      AsmString = "bvc,pn %icc, $\x01";
1966
142
      break;
1967
142
    }
1968
111
    if (MCInst_getNumOperands(MI) == 2 &&
1969
111
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1970
111
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1971
      // (BPICCNT brtarget:$imm, 7)
1972
111
      AsmString = "bvs,pn %icc, $\x01";
1973
111
      break;
1974
111
    }
1975
0
    return NULL;
1976
2.12k
  case SP_BPXCCANT:
1977
2.12k
    if (MCInst_getNumOperands(MI) == 2 &&
1978
2.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1979
2.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1980
      // (BPXCCANT brtarget:$imm, 8)
1981
338
      AsmString = "ba,a,pn %xcc, $\x01";
1982
338
      break;
1983
338
    }
1984
1.78k
    if (MCInst_getNumOperands(MI) == 2 &&
1985
1.78k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1986
1.78k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1987
      // (BPXCCANT brtarget:$imm, 0)
1988
319
      AsmString = "bn,a,pn %xcc, $\x01";
1989
319
      break;
1990
319
    }
1991
1.46k
    if (MCInst_getNumOperands(MI) == 2 &&
1992
1.46k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1993
1.46k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1994
      // (BPXCCANT brtarget:$imm, 9)
1995
83
      AsmString = "bne,a,pn %xcc, $\x01";
1996
83
      break;
1997
83
    }
1998
1.38k
    if (MCInst_getNumOperands(MI) == 2 &&
1999
1.38k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2000
1.38k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2001
      // (BPXCCANT brtarget:$imm, 1)
2002
91
      AsmString = "be,a,pn %xcc, $\x01";
2003
91
      break;
2004
91
    }
2005
1.29k
    if (MCInst_getNumOperands(MI) == 2 &&
2006
1.29k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2007
1.29k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2008
      // (BPXCCANT brtarget:$imm, 10)
2009
85
      AsmString = "bg,a,pn %xcc, $\x01";
2010
85
      break;
2011
85
    }
2012
1.20k
    if (MCInst_getNumOperands(MI) == 2 &&
2013
1.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2014
1.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2015
      // (BPXCCANT brtarget:$imm, 2)
2016
29
      AsmString = "ble,a,pn %xcc, $\x01";
2017
29
      break;
2018
29
    }
2019
1.17k
    if (MCInst_getNumOperands(MI) == 2 &&
2020
1.17k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2021
1.17k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2022
      // (BPXCCANT brtarget:$imm, 11)
2023
162
      AsmString = "bge,a,pn %xcc, $\x01";
2024
162
      break;
2025
162
    }
2026
1.01k
    if (MCInst_getNumOperands(MI) == 2 &&
2027
1.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2028
1.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2029
      // (BPXCCANT brtarget:$imm, 3)
2030
79
      AsmString = "bl,a,pn %xcc, $\x01";
2031
79
      break;
2032
79
    }
2033
936
    if (MCInst_getNumOperands(MI) == 2 &&
2034
936
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2035
936
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2036
      // (BPXCCANT brtarget:$imm, 12)
2037
84
      AsmString = "bgu,a,pn %xcc, $\x01";
2038
84
      break;
2039
84
    }
2040
852
    if (MCInst_getNumOperands(MI) == 2 &&
2041
852
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2042
852
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2043
      // (BPXCCANT brtarget:$imm, 4)
2044
50
      AsmString = "bleu,a,pn %xcc, $\x01";
2045
50
      break;
2046
50
    }
2047
802
    if (MCInst_getNumOperands(MI) == 2 &&
2048
802
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2049
802
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2050
      // (BPXCCANT brtarget:$imm, 13)
2051
82
      AsmString = "bcc,a,pn %xcc, $\x01";
2052
82
      break;
2053
82
    }
2054
720
    if (MCInst_getNumOperands(MI) == 2 &&
2055
720
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2056
720
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2057
      // (BPXCCANT brtarget:$imm, 5)
2058
210
      AsmString = "bcs,a,pn %xcc, $\x01";
2059
210
      break;
2060
210
    }
2061
510
    if (MCInst_getNumOperands(MI) == 2 &&
2062
510
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2063
510
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2064
      // (BPXCCANT brtarget:$imm, 14)
2065
98
      AsmString = "bpos,a,pn %xcc, $\x01";
2066
98
      break;
2067
98
    }
2068
412
    if (MCInst_getNumOperands(MI) == 2 &&
2069
412
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2070
412
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2071
      // (BPXCCANT brtarget:$imm, 6)
2072
147
      AsmString = "bneg,a,pn %xcc, $\x01";
2073
147
      break;
2074
147
    }
2075
265
    if (MCInst_getNumOperands(MI) == 2 &&
2076
265
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2077
265
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2078
      // (BPXCCANT brtarget:$imm, 15)
2079
127
      AsmString = "bvc,a,pn %xcc, $\x01";
2080
127
      break;
2081
127
    }
2082
138
    if (MCInst_getNumOperands(MI) == 2 &&
2083
138
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2084
138
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2085
      // (BPXCCANT brtarget:$imm, 7)
2086
138
      AsmString = "bvs,a,pn %xcc, $\x01";
2087
138
      break;
2088
138
    }
2089
0
    return NULL;
2090
2.60k
  case SP_BPXCCNT:
2091
2.60k
    if (MCInst_getNumOperands(MI) == 2 &&
2092
2.60k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2093
2.60k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2094
      // (BPXCCNT brtarget:$imm, 8)
2095
271
      AsmString = "ba,pn %xcc, $\x01";
2096
271
      break;
2097
271
    }
2098
2.33k
    if (MCInst_getNumOperands(MI) == 2 &&
2099
2.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2100
2.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2101
      // (BPXCCNT brtarget:$imm, 0)
2102
471
      AsmString = "bn,pn %xcc, $\x01";
2103
471
      break;
2104
471
    }
2105
1.86k
    if (MCInst_getNumOperands(MI) == 2 &&
2106
1.86k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2107
1.86k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2108
      // (BPXCCNT brtarget:$imm, 9)
2109
454
      AsmString = "bne,pn %xcc, $\x01";
2110
454
      break;
2111
454
    }
2112
1.40k
    if (MCInst_getNumOperands(MI) == 2 &&
2113
1.40k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2114
1.40k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2115
      // (BPXCCNT brtarget:$imm, 1)
2116
87
      AsmString = "be,pn %xcc, $\x01";
2117
87
      break;
2118
87
    }
2119
1.32k
    if (MCInst_getNumOperands(MI) == 2 &&
2120
1.32k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2121
1.32k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2122
      // (BPXCCNT brtarget:$imm, 10)
2123
35
      AsmString = "bg,pn %xcc, $\x01";
2124
35
      break;
2125
35
    }
2126
1.28k
    if (MCInst_getNumOperands(MI) == 2 &&
2127
1.28k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2128
1.28k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2129
      // (BPXCCNT brtarget:$imm, 2)
2130
72
      AsmString = "ble,pn %xcc, $\x01";
2131
72
      break;
2132
72
    }
2133
1.21k
    if (MCInst_getNumOperands(MI) == 2 &&
2134
1.21k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2135
1.21k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2136
      // (BPXCCNT brtarget:$imm, 11)
2137
67
      AsmString = "bge,pn %xcc, $\x01";
2138
67
      break;
2139
67
    }
2140
1.14k
    if (MCInst_getNumOperands(MI) == 2 &&
2141
1.14k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2142
1.14k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2143
      // (BPXCCNT brtarget:$imm, 3)
2144
160
      AsmString = "bl,pn %xcc, $\x01";
2145
160
      break;
2146
160
    }
2147
987
    if (MCInst_getNumOperands(MI) == 2 &&
2148
987
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2149
987
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2150
      // (BPXCCNT brtarget:$imm, 12)
2151
201
      AsmString = "bgu,pn %xcc, $\x01";
2152
201
      break;
2153
201
    }
2154
786
    if (MCInst_getNumOperands(MI) == 2 &&
2155
786
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2156
786
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2157
      // (BPXCCNT brtarget:$imm, 4)
2158
39
      AsmString = "bleu,pn %xcc, $\x01";
2159
39
      break;
2160
39
    }
2161
747
    if (MCInst_getNumOperands(MI) == 2 &&
2162
747
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2163
747
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2164
      // (BPXCCNT brtarget:$imm, 13)
2165
67
      AsmString = "bcc,pn %xcc, $\x01";
2166
67
      break;
2167
67
    }
2168
680
    if (MCInst_getNumOperands(MI) == 2 &&
2169
680
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2170
680
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2171
      // (BPXCCNT brtarget:$imm, 5)
2172
371
      AsmString = "bcs,pn %xcc, $\x01";
2173
371
      break;
2174
371
    }
2175
309
    if (MCInst_getNumOperands(MI) == 2 &&
2176
309
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2177
309
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2178
      // (BPXCCNT brtarget:$imm, 14)
2179
76
      AsmString = "bpos,pn %xcc, $\x01";
2180
76
      break;
2181
76
    }
2182
233
    if (MCInst_getNumOperands(MI) == 2 &&
2183
233
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2184
233
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2185
      // (BPXCCNT brtarget:$imm, 6)
2186
103
      AsmString = "bneg,pn %xcc, $\x01";
2187
103
      break;
2188
103
    }
2189
130
    if (MCInst_getNumOperands(MI) == 2 &&
2190
130
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2191
130
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2192
      // (BPXCCNT brtarget:$imm, 15)
2193
72
      AsmString = "bvc,pn %xcc, $\x01";
2194
72
      break;
2195
72
    }
2196
58
    if (MCInst_getNumOperands(MI) == 2 &&
2197
58
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2198
58
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2199
      // (BPXCCNT brtarget:$imm, 7)
2200
58
      AsmString = "bvs,pn %xcc, $\x01";
2201
58
      break;
2202
58
    }
2203
0
    return NULL;
2204
34
  case SP_FMOVD_ICC:
2205
34
    if (MCInst_getNumOperands(MI) == 3 &&
2206
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2207
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2208
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2209
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2210
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2211
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2212
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2213
0
      AsmString = "fmovda %icc, $\x02, $\x01";
2214
0
      break;
2215
0
    }
2216
34
    if (MCInst_getNumOperands(MI) == 3 &&
2217
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2218
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2219
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2220
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2221
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2222
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2223
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2224
0
      AsmString = "fmovdn %icc, $\x02, $\x01";
2225
0
      break;
2226
0
    }
2227
34
    if (MCInst_getNumOperands(MI) == 3 &&
2228
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2229
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2230
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2231
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2232
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2233
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2234
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2235
0
      AsmString = "fmovdne %icc, $\x02, $\x01";
2236
0
      break;
2237
0
    }
2238
34
    if (MCInst_getNumOperands(MI) == 3 &&
2239
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2240
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2241
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2242
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2243
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2244
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2245
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2246
0
      AsmString = "fmovde %icc, $\x02, $\x01";
2247
0
      break;
2248
0
    }
2249
34
    if (MCInst_getNumOperands(MI) == 3 &&
2250
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2251
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2252
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2253
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2254
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2255
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2256
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2257
0
      AsmString = "fmovdg %icc, $\x02, $\x01";
2258
0
      break;
2259
0
    }
2260
34
    if (MCInst_getNumOperands(MI) == 3 &&
2261
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2262
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2263
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2264
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2265
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2266
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2267
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2268
0
      AsmString = "fmovdle %icc, $\x02, $\x01";
2269
0
      break;
2270
0
    }
2271
34
    if (MCInst_getNumOperands(MI) == 3 &&
2272
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2273
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2274
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2275
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2276
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2277
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2278
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2279
0
      AsmString = "fmovdge %icc, $\x02, $\x01";
2280
0
      break;
2281
0
    }
2282
34
    if (MCInst_getNumOperands(MI) == 3 &&
2283
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2285
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2287
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2288
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2289
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2290
0
      AsmString = "fmovdl %icc, $\x02, $\x01";
2291
0
      break;
2292
0
    }
2293
34
    if (MCInst_getNumOperands(MI) == 3 &&
2294
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2295
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2296
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2297
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2298
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2299
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2300
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2301
0
      AsmString = "fmovdgu %icc, $\x02, $\x01";
2302
0
      break;
2303
0
    }
2304
34
    if (MCInst_getNumOperands(MI) == 3 &&
2305
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2306
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2307
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2308
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2309
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2310
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2311
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2312
0
      AsmString = "fmovdleu %icc, $\x02, $\x01";
2313
0
      break;
2314
0
    }
2315
34
    if (MCInst_getNumOperands(MI) == 3 &&
2316
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2317
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2318
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2319
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2320
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2321
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2322
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2323
0
      AsmString = "fmovdcc %icc, $\x02, $\x01";
2324
0
      break;
2325
0
    }
2326
34
    if (MCInst_getNumOperands(MI) == 3 &&
2327
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2328
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2329
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2330
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2331
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2332
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2333
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2334
0
      AsmString = "fmovdcs %icc, $\x02, $\x01";
2335
0
      break;
2336
0
    }
2337
34
    if (MCInst_getNumOperands(MI) == 3 &&
2338
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2339
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2340
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2341
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2342
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2343
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2344
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2345
0
      AsmString = "fmovdpos %icc, $\x02, $\x01";
2346
0
      break;
2347
0
    }
2348
34
    if (MCInst_getNumOperands(MI) == 3 &&
2349
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2350
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2351
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2352
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2353
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2354
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2355
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2356
0
      AsmString = "fmovdneg %icc, $\x02, $\x01";
2357
0
      break;
2358
0
    }
2359
34
    if (MCInst_getNumOperands(MI) == 3 &&
2360
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2361
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2362
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2363
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2364
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2365
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2366
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2367
0
      AsmString = "fmovdvc %icc, $\x02, $\x01";
2368
0
      break;
2369
0
    }
2370
34
    if (MCInst_getNumOperands(MI) == 3 &&
2371
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2372
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2373
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2374
34
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2375
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2376
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2377
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2378
0
      AsmString = "fmovdvs %icc, $\x02, $\x01";
2379
0
      break;
2380
0
    }
2381
34
    return NULL;
2382
18
  case SP_FMOVD_XCC:
2383
18
    if (MCInst_getNumOperands(MI) == 3 &&
2384
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2385
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2386
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2387
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2388
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2389
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2390
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2391
0
      AsmString = "fmovda %xcc, $\x02, $\x01";
2392
0
      break;
2393
0
    }
2394
18
    if (MCInst_getNumOperands(MI) == 3 &&
2395
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2396
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2397
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2398
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2399
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2400
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2401
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2402
0
      AsmString = "fmovdn %xcc, $\x02, $\x01";
2403
0
      break;
2404
0
    }
2405
18
    if (MCInst_getNumOperands(MI) == 3 &&
2406
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2407
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2408
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2409
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2410
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2411
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2412
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2413
0
      AsmString = "fmovdne %xcc, $\x02, $\x01";
2414
0
      break;
2415
0
    }
2416
18
    if (MCInst_getNumOperands(MI) == 3 &&
2417
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2418
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2419
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2420
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2421
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2422
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2423
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2424
0
      AsmString = "fmovde %xcc, $\x02, $\x01";
2425
0
      break;
2426
0
    }
2427
18
    if (MCInst_getNumOperands(MI) == 3 &&
2428
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2429
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2430
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2431
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2432
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2433
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2434
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2435
0
      AsmString = "fmovdg %xcc, $\x02, $\x01";
2436
0
      break;
2437
0
    }
2438
18
    if (MCInst_getNumOperands(MI) == 3 &&
2439
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2440
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2441
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2442
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2443
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2444
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2445
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2446
0
      AsmString = "fmovdle %xcc, $\x02, $\x01";
2447
0
      break;
2448
0
    }
2449
18
    if (MCInst_getNumOperands(MI) == 3 &&
2450
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2451
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2452
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2453
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2454
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2455
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2456
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2457
0
      AsmString = "fmovdge %xcc, $\x02, $\x01";
2458
0
      break;
2459
0
    }
2460
18
    if (MCInst_getNumOperands(MI) == 3 &&
2461
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2462
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2463
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2464
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2465
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2466
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2467
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2468
0
      AsmString = "fmovdl %xcc, $\x02, $\x01";
2469
0
      break;
2470
0
    }
2471
18
    if (MCInst_getNumOperands(MI) == 3 &&
2472
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2473
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2474
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2475
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2476
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2477
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2478
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2479
0
      AsmString = "fmovdgu %xcc, $\x02, $\x01";
2480
0
      break;
2481
0
    }
2482
18
    if (MCInst_getNumOperands(MI) == 3 &&
2483
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2484
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2485
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2486
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2487
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2488
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2489
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2490
0
      AsmString = "fmovdleu %xcc, $\x02, $\x01";
2491
0
      break;
2492
0
    }
2493
18
    if (MCInst_getNumOperands(MI) == 3 &&
2494
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2495
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2496
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2497
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2498
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2499
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2500
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2501
0
      AsmString = "fmovdcc %xcc, $\x02, $\x01";
2502
0
      break;
2503
0
    }
2504
18
    if (MCInst_getNumOperands(MI) == 3 &&
2505
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2506
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2507
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2508
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2509
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2510
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2511
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2512
0
      AsmString = "fmovdcs %xcc, $\x02, $\x01";
2513
0
      break;
2514
0
    }
2515
18
    if (MCInst_getNumOperands(MI) == 3 &&
2516
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2518
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2519
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2520
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2521
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2522
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2523
0
      AsmString = "fmovdpos %xcc, $\x02, $\x01";
2524
0
      break;
2525
0
    }
2526
18
    if (MCInst_getNumOperands(MI) == 3 &&
2527
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2528
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2529
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2530
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2531
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2532
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2533
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2534
0
      AsmString = "fmovdneg %xcc, $\x02, $\x01";
2535
0
      break;
2536
0
    }
2537
18
    if (MCInst_getNumOperands(MI) == 3 &&
2538
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2539
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2540
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2541
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2542
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2543
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2544
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2545
0
      AsmString = "fmovdvc %xcc, $\x02, $\x01";
2546
0
      break;
2547
0
    }
2548
18
    if (MCInst_getNumOperands(MI) == 3 &&
2549
18
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2550
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2551
18
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2552
18
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2553
18
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2554
18
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2555
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2556
0
      AsmString = "fmovdvs %xcc, $\x02, $\x01";
2557
0
      break;
2558
0
    }
2559
18
    return NULL;
2560
446
  case SP_FMOVQ_ICC:
2561
446
    if (MCInst_getNumOperands(MI) == 3 &&
2562
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2563
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2564
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2565
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2566
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2567
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2568
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2569
0
      AsmString = "fmovqa %icc, $\x02, $\x01";
2570
0
      break;
2571
0
    }
2572
446
    if (MCInst_getNumOperands(MI) == 3 &&
2573
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2574
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2575
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2576
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2577
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2578
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2579
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2580
0
      AsmString = "fmovqn %icc, $\x02, $\x01";
2581
0
      break;
2582
0
    }
2583
446
    if (MCInst_getNumOperands(MI) == 3 &&
2584
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2585
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2586
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2587
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2588
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2589
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2590
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2591
0
      AsmString = "fmovqne %icc, $\x02, $\x01";
2592
0
      break;
2593
0
    }
2594
446
    if (MCInst_getNumOperands(MI) == 3 &&
2595
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2596
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2597
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2598
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2599
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2600
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2601
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2602
0
      AsmString = "fmovqe %icc, $\x02, $\x01";
2603
0
      break;
2604
0
    }
2605
446
    if (MCInst_getNumOperands(MI) == 3 &&
2606
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2607
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2608
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2609
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2610
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2611
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2612
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2613
0
      AsmString = "fmovqg %icc, $\x02, $\x01";
2614
0
      break;
2615
0
    }
2616
446
    if (MCInst_getNumOperands(MI) == 3 &&
2617
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2618
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2619
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2620
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2621
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2622
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2623
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2624
0
      AsmString = "fmovqle %icc, $\x02, $\x01";
2625
0
      break;
2626
0
    }
2627
446
    if (MCInst_getNumOperands(MI) == 3 &&
2628
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2629
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2630
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2631
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2632
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2633
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2634
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2635
0
      AsmString = "fmovqge %icc, $\x02, $\x01";
2636
0
      break;
2637
0
    }
2638
446
    if (MCInst_getNumOperands(MI) == 3 &&
2639
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2640
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2641
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2642
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2643
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2644
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2645
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2646
0
      AsmString = "fmovql %icc, $\x02, $\x01";
2647
0
      break;
2648
0
    }
2649
446
    if (MCInst_getNumOperands(MI) == 3 &&
2650
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2651
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2652
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2653
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2654
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2655
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2656
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2657
0
      AsmString = "fmovqgu %icc, $\x02, $\x01";
2658
0
      break;
2659
0
    }
2660
446
    if (MCInst_getNumOperands(MI) == 3 &&
2661
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2662
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2663
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2664
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2665
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2666
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2667
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2668
0
      AsmString = "fmovqleu %icc, $\x02, $\x01";
2669
0
      break;
2670
0
    }
2671
446
    if (MCInst_getNumOperands(MI) == 3 &&
2672
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2673
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2674
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2675
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2676
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2677
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2678
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2679
0
      AsmString = "fmovqcc %icc, $\x02, $\x01";
2680
0
      break;
2681
0
    }
2682
446
    if (MCInst_getNumOperands(MI) == 3 &&
2683
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2684
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2685
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2686
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2687
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2688
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2689
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2690
0
      AsmString = "fmovqcs %icc, $\x02, $\x01";
2691
0
      break;
2692
0
    }
2693
446
    if (MCInst_getNumOperands(MI) == 3 &&
2694
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2695
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2696
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2697
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2698
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2699
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2700
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2701
0
      AsmString = "fmovqpos %icc, $\x02, $\x01";
2702
0
      break;
2703
0
    }
2704
446
    if (MCInst_getNumOperands(MI) == 3 &&
2705
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2706
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2707
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2708
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2709
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2710
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2711
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2712
0
      AsmString = "fmovqneg %icc, $\x02, $\x01";
2713
0
      break;
2714
0
    }
2715
446
    if (MCInst_getNumOperands(MI) == 3 &&
2716
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2717
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2718
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2719
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2720
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2721
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2722
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2723
0
      AsmString = "fmovqvc %icc, $\x02, $\x01";
2724
0
      break;
2725
0
    }
2726
446
    if (MCInst_getNumOperands(MI) == 3 &&
2727
446
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2728
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2729
446
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2730
446
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2731
446
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2732
446
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2733
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2734
0
      AsmString = "fmovqvs %icc, $\x02, $\x01";
2735
0
      break;
2736
0
    }
2737
446
    return NULL;
2738
68
  case SP_FMOVQ_XCC:
2739
68
    if (MCInst_getNumOperands(MI) == 3 &&
2740
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2741
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2742
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2743
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2744
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2745
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2746
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2747
0
      AsmString = "fmovqa %xcc, $\x02, $\x01";
2748
0
      break;
2749
0
    }
2750
68
    if (MCInst_getNumOperands(MI) == 3 &&
2751
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2752
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2753
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2754
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2755
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2756
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2757
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2758
0
      AsmString = "fmovqn %xcc, $\x02, $\x01";
2759
0
      break;
2760
0
    }
2761
68
    if (MCInst_getNumOperands(MI) == 3 &&
2762
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2763
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2764
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2765
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2766
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2767
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2768
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2769
0
      AsmString = "fmovqne %xcc, $\x02, $\x01";
2770
0
      break;
2771
0
    }
2772
68
    if (MCInst_getNumOperands(MI) == 3 &&
2773
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2774
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2775
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2776
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2777
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2778
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2779
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2780
0
      AsmString = "fmovqe %xcc, $\x02, $\x01";
2781
0
      break;
2782
0
    }
2783
68
    if (MCInst_getNumOperands(MI) == 3 &&
2784
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2785
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2786
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2787
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2788
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2789
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2790
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2791
0
      AsmString = "fmovqg %xcc, $\x02, $\x01";
2792
0
      break;
2793
0
    }
2794
68
    if (MCInst_getNumOperands(MI) == 3 &&
2795
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2796
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2797
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2798
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2799
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2800
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2801
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2802
0
      AsmString = "fmovqle %xcc, $\x02, $\x01";
2803
0
      break;
2804
0
    }
2805
68
    if (MCInst_getNumOperands(MI) == 3 &&
2806
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2807
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2808
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2809
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2810
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2811
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2812
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2813
0
      AsmString = "fmovqge %xcc, $\x02, $\x01";
2814
0
      break;
2815
0
    }
2816
68
    if (MCInst_getNumOperands(MI) == 3 &&
2817
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2818
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2819
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2820
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2821
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2822
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2823
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2824
0
      AsmString = "fmovql %xcc, $\x02, $\x01";
2825
0
      break;
2826
0
    }
2827
68
    if (MCInst_getNumOperands(MI) == 3 &&
2828
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2829
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2830
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2831
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2832
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2834
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2835
0
      AsmString = "fmovqgu %xcc, $\x02, $\x01";
2836
0
      break;
2837
0
    }
2838
68
    if (MCInst_getNumOperands(MI) == 3 &&
2839
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2840
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2841
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2842
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2843
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2844
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2845
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2846
0
      AsmString = "fmovqleu %xcc, $\x02, $\x01";
2847
0
      break;
2848
0
    }
2849
68
    if (MCInst_getNumOperands(MI) == 3 &&
2850
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2851
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2852
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2853
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2854
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2855
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2856
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2857
0
      AsmString = "fmovqcc %xcc, $\x02, $\x01";
2858
0
      break;
2859
0
    }
2860
68
    if (MCInst_getNumOperands(MI) == 3 &&
2861
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2862
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2863
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2864
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2865
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2866
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2867
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2868
0
      AsmString = "fmovqcs %xcc, $\x02, $\x01";
2869
0
      break;
2870
0
    }
2871
68
    if (MCInst_getNumOperands(MI) == 3 &&
2872
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2873
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2874
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2875
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2876
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2877
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2878
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2879
0
      AsmString = "fmovqpos %xcc, $\x02, $\x01";
2880
0
      break;
2881
0
    }
2882
68
    if (MCInst_getNumOperands(MI) == 3 &&
2883
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2884
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2885
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2886
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2887
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2888
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2889
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2890
0
      AsmString = "fmovqneg %xcc, $\x02, $\x01";
2891
0
      break;
2892
0
    }
2893
68
    if (MCInst_getNumOperands(MI) == 3 &&
2894
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2895
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2896
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2897
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2898
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2899
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2900
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2901
0
      AsmString = "fmovqvc %xcc, $\x02, $\x01";
2902
0
      break;
2903
0
    }
2904
68
    if (MCInst_getNumOperands(MI) == 3 &&
2905
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2906
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2907
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2908
68
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2909
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2910
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2911
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2912
0
      AsmString = "fmovqvs %xcc, $\x02, $\x01";
2913
0
      break;
2914
0
    }
2915
68
    return NULL;
2916
35
  case SP_FMOVS_ICC:
2917
35
    if (MCInst_getNumOperands(MI) == 3 &&
2918
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2919
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2920
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2921
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2922
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2923
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2924
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2925
0
      AsmString = "fmovsa %icc, $\x02, $\x01";
2926
0
      break;
2927
0
    }
2928
35
    if (MCInst_getNumOperands(MI) == 3 &&
2929
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2930
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2931
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2932
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2933
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2934
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2935
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2936
0
      AsmString = "fmovsn %icc, $\x02, $\x01";
2937
0
      break;
2938
0
    }
2939
35
    if (MCInst_getNumOperands(MI) == 3 &&
2940
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2941
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2942
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2943
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2944
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2945
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2946
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2947
0
      AsmString = "fmovsne %icc, $\x02, $\x01";
2948
0
      break;
2949
0
    }
2950
35
    if (MCInst_getNumOperands(MI) == 3 &&
2951
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2952
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2953
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2954
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2955
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2956
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2957
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2958
0
      AsmString = "fmovse %icc, $\x02, $\x01";
2959
0
      break;
2960
0
    }
2961
35
    if (MCInst_getNumOperands(MI) == 3 &&
2962
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2963
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2964
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2965
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2966
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2967
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2968
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2969
0
      AsmString = "fmovsg %icc, $\x02, $\x01";
2970
0
      break;
2971
0
    }
2972
35
    if (MCInst_getNumOperands(MI) == 3 &&
2973
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2974
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2975
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2976
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2977
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2978
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2979
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2980
0
      AsmString = "fmovsle %icc, $\x02, $\x01";
2981
0
      break;
2982
0
    }
2983
35
    if (MCInst_getNumOperands(MI) == 3 &&
2984
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2985
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2986
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2987
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2988
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2989
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2990
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2991
0
      AsmString = "fmovsge %icc, $\x02, $\x01";
2992
0
      break;
2993
0
    }
2994
35
    if (MCInst_getNumOperands(MI) == 3 &&
2995
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2996
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2997
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2998
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2999
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3000
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3001
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3002
0
      AsmString = "fmovsl %icc, $\x02, $\x01";
3003
0
      break;
3004
0
    }
3005
35
    if (MCInst_getNumOperands(MI) == 3 &&
3006
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3007
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3008
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3009
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3010
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3011
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3012
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3013
0
      AsmString = "fmovsgu %icc, $\x02, $\x01";
3014
0
      break;
3015
0
    }
3016
35
    if (MCInst_getNumOperands(MI) == 3 &&
3017
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3018
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3019
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3020
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3021
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3022
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3023
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3024
0
      AsmString = "fmovsleu %icc, $\x02, $\x01";
3025
0
      break;
3026
0
    }
3027
35
    if (MCInst_getNumOperands(MI) == 3 &&
3028
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3029
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3030
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3031
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3032
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3033
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3034
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3035
0
      AsmString = "fmovscc %icc, $\x02, $\x01";
3036
0
      break;
3037
0
    }
3038
35
    if (MCInst_getNumOperands(MI) == 3 &&
3039
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3040
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3041
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3042
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3043
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3044
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3045
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3046
0
      AsmString = "fmovscs %icc, $\x02, $\x01";
3047
0
      break;
3048
0
    }
3049
35
    if (MCInst_getNumOperands(MI) == 3 &&
3050
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3051
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3052
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3053
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3054
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3055
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3056
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3057
0
      AsmString = "fmovspos %icc, $\x02, $\x01";
3058
0
      break;
3059
0
    }
3060
35
    if (MCInst_getNumOperands(MI) == 3 &&
3061
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3062
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3063
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3064
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3065
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3066
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3067
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3068
0
      AsmString = "fmovsneg %icc, $\x02, $\x01";
3069
0
      break;
3070
0
    }
3071
35
    if (MCInst_getNumOperands(MI) == 3 &&
3072
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3073
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3074
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3075
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3076
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3077
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3078
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3079
0
      AsmString = "fmovsvc %icc, $\x02, $\x01";
3080
0
      break;
3081
0
    }
3082
35
    if (MCInst_getNumOperands(MI) == 3 &&
3083
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3084
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3085
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3086
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3087
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3088
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3089
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3090
0
      AsmString = "fmovsvs %icc, $\x02, $\x01";
3091
0
      break;
3092
0
    }
3093
35
    return NULL;
3094
10
  case SP_FMOVS_XCC:
3095
10
    if (MCInst_getNumOperands(MI) == 3 &&
3096
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3097
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3098
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3099
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3100
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3101
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3102
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3103
0
      AsmString = "fmovsa %xcc, $\x02, $\x01";
3104
0
      break;
3105
0
    }
3106
10
    if (MCInst_getNumOperands(MI) == 3 &&
3107
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3108
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3109
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3110
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3111
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3112
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3113
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3114
0
      AsmString = "fmovsn %xcc, $\x02, $\x01";
3115
0
      break;
3116
0
    }
3117
10
    if (MCInst_getNumOperands(MI) == 3 &&
3118
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3119
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3120
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3121
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3122
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3123
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3124
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3125
0
      AsmString = "fmovsne %xcc, $\x02, $\x01";
3126
0
      break;
3127
0
    }
3128
10
    if (MCInst_getNumOperands(MI) == 3 &&
3129
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3130
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3131
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3132
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3133
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3134
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3135
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3136
0
      AsmString = "fmovse %xcc, $\x02, $\x01";
3137
0
      break;
3138
0
    }
3139
10
    if (MCInst_getNumOperands(MI) == 3 &&
3140
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3141
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3142
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3143
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3144
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3145
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3146
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3147
0
      AsmString = "fmovsg %xcc, $\x02, $\x01";
3148
0
      break;
3149
0
    }
3150
10
    if (MCInst_getNumOperands(MI) == 3 &&
3151
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3152
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3153
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3154
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3155
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3156
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3157
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3158
0
      AsmString = "fmovsle %xcc, $\x02, $\x01";
3159
0
      break;
3160
0
    }
3161
10
    if (MCInst_getNumOperands(MI) == 3 &&
3162
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3163
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3164
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3165
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3166
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3167
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3168
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3169
0
      AsmString = "fmovsge %xcc, $\x02, $\x01";
3170
0
      break;
3171
0
    }
3172
10
    if (MCInst_getNumOperands(MI) == 3 &&
3173
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3174
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3175
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3176
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3177
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3178
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3179
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3180
0
      AsmString = "fmovsl %xcc, $\x02, $\x01";
3181
0
      break;
3182
0
    }
3183
10
    if (MCInst_getNumOperands(MI) == 3 &&
3184
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3185
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3186
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3187
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3188
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3190
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3191
0
      AsmString = "fmovsgu %xcc, $\x02, $\x01";
3192
0
      break;
3193
0
    }
3194
10
    if (MCInst_getNumOperands(MI) == 3 &&
3195
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3196
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3197
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3198
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3199
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3200
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3201
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3202
0
      AsmString = "fmovsleu %xcc, $\x02, $\x01";
3203
0
      break;
3204
0
    }
3205
10
    if (MCInst_getNumOperands(MI) == 3 &&
3206
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3207
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3208
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3209
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3210
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3211
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3212
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3213
0
      AsmString = "fmovscc %xcc, $\x02, $\x01";
3214
0
      break;
3215
0
    }
3216
10
    if (MCInst_getNumOperands(MI) == 3 &&
3217
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3218
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3219
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3220
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3221
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3222
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3223
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3224
0
      AsmString = "fmovscs %xcc, $\x02, $\x01";
3225
0
      break;
3226
0
    }
3227
10
    if (MCInst_getNumOperands(MI) == 3 &&
3228
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3229
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3230
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3231
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3232
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3233
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3234
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3235
0
      AsmString = "fmovspos %xcc, $\x02, $\x01";
3236
0
      break;
3237
0
    }
3238
10
    if (MCInst_getNumOperands(MI) == 3 &&
3239
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3240
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3241
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3242
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3243
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3244
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3245
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3246
0
      AsmString = "fmovsneg %xcc, $\x02, $\x01";
3247
0
      break;
3248
0
    }
3249
10
    if (MCInst_getNumOperands(MI) == 3 &&
3250
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3251
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3252
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3253
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3254
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3255
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3256
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3257
0
      AsmString = "fmovsvc %xcc, $\x02, $\x01";
3258
0
      break;
3259
0
    }
3260
10
    if (MCInst_getNumOperands(MI) == 3 &&
3261
10
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3262
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3263
10
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3264
10
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3265
10
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3266
10
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3267
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3268
0
      AsmString = "fmovsvs %xcc, $\x02, $\x01";
3269
0
      break;
3270
0
    }
3271
10
    return NULL;
3272
89
  case SP_MOVICCri:
3273
89
    if (MCInst_getNumOperands(MI) == 3 &&
3274
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3275
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3276
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3277
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3278
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3279
0
      AsmString = "mova %icc, $\x02, $\x01";
3280
0
      break;
3281
0
    }
3282
89
    if (MCInst_getNumOperands(MI) == 3 &&
3283
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3284
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3285
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3286
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3287
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3288
0
      AsmString = "movn %icc, $\x02, $\x01";
3289
0
      break;
3290
0
    }
3291
89
    if (MCInst_getNumOperands(MI) == 3 &&
3292
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3293
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3294
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3295
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3296
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3297
0
      AsmString = "movne %icc, $\x02, $\x01";
3298
0
      break;
3299
0
    }
3300
89
    if (MCInst_getNumOperands(MI) == 3 &&
3301
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3302
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3303
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3304
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3305
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3306
0
      AsmString = "move %icc, $\x02, $\x01";
3307
0
      break;
3308
0
    }
3309
89
    if (MCInst_getNumOperands(MI) == 3 &&
3310
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3311
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3312
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3313
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3314
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3315
0
      AsmString = "movg %icc, $\x02, $\x01";
3316
0
      break;
3317
0
    }
3318
89
    if (MCInst_getNumOperands(MI) == 3 &&
3319
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3320
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3321
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3322
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3323
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3324
0
      AsmString = "movle %icc, $\x02, $\x01";
3325
0
      break;
3326
0
    }
3327
89
    if (MCInst_getNumOperands(MI) == 3 &&
3328
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3329
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3330
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3331
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3332
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3333
0
      AsmString = "movge %icc, $\x02, $\x01";
3334
0
      break;
3335
0
    }
3336
89
    if (MCInst_getNumOperands(MI) == 3 &&
3337
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3338
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3339
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3340
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3341
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3342
0
      AsmString = "movl %icc, $\x02, $\x01";
3343
0
      break;
3344
0
    }
3345
89
    if (MCInst_getNumOperands(MI) == 3 &&
3346
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3347
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3348
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3349
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3350
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3351
0
      AsmString = "movgu %icc, $\x02, $\x01";
3352
0
      break;
3353
0
    }
3354
89
    if (MCInst_getNumOperands(MI) == 3 &&
3355
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3356
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3357
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3358
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3359
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3360
0
      AsmString = "movleu %icc, $\x02, $\x01";
3361
0
      break;
3362
0
    }
3363
89
    if (MCInst_getNumOperands(MI) == 3 &&
3364
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3365
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3366
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3367
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3368
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3369
0
      AsmString = "movcc %icc, $\x02, $\x01";
3370
0
      break;
3371
0
    }
3372
89
    if (MCInst_getNumOperands(MI) == 3 &&
3373
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3374
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3375
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3376
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3377
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3378
0
      AsmString = "movcs %icc, $\x02, $\x01";
3379
0
      break;
3380
0
    }
3381
89
    if (MCInst_getNumOperands(MI) == 3 &&
3382
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3383
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3384
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3385
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3386
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3387
0
      AsmString = "movpos %icc, $\x02, $\x01";
3388
0
      break;
3389
0
    }
3390
89
    if (MCInst_getNumOperands(MI) == 3 &&
3391
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3392
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3393
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3394
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3395
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3396
0
      AsmString = "movneg %icc, $\x02, $\x01";
3397
0
      break;
3398
0
    }
3399
89
    if (MCInst_getNumOperands(MI) == 3 &&
3400
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3401
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3402
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3403
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3404
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3405
0
      AsmString = "movvc %icc, $\x02, $\x01";
3406
0
      break;
3407
0
    }
3408
89
    if (MCInst_getNumOperands(MI) == 3 &&
3409
89
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3410
89
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3411
89
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3412
89
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3413
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3414
0
      AsmString = "movvs %icc, $\x02, $\x01";
3415
0
      break;
3416
0
    }
3417
89
    return NULL;
3418
72
  case SP_MOVICCrr:
3419
72
    if (MCInst_getNumOperands(MI) == 3 &&
3420
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3421
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3422
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3423
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3424
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3425
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3426
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3427
0
      AsmString = "mova %icc, $\x02, $\x01";
3428
0
      break;
3429
0
    }
3430
72
    if (MCInst_getNumOperands(MI) == 3 &&
3431
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3432
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3433
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3434
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3435
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3436
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3437
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3438
0
      AsmString = "movn %icc, $\x02, $\x01";
3439
0
      break;
3440
0
    }
3441
72
    if (MCInst_getNumOperands(MI) == 3 &&
3442
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3443
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3444
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3445
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3446
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3447
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3448
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3449
0
      AsmString = "movne %icc, $\x02, $\x01";
3450
0
      break;
3451
0
    }
3452
72
    if (MCInst_getNumOperands(MI) == 3 &&
3453
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3454
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3455
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3456
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3457
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3458
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3459
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3460
0
      AsmString = "move %icc, $\x02, $\x01";
3461
0
      break;
3462
0
    }
3463
72
    if (MCInst_getNumOperands(MI) == 3 &&
3464
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3465
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3466
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3467
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3468
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3469
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3470
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3471
0
      AsmString = "movg %icc, $\x02, $\x01";
3472
0
      break;
3473
0
    }
3474
72
    if (MCInst_getNumOperands(MI) == 3 &&
3475
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3476
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3477
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3478
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3479
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3480
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3481
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3482
0
      AsmString = "movle %icc, $\x02, $\x01";
3483
0
      break;
3484
0
    }
3485
72
    if (MCInst_getNumOperands(MI) == 3 &&
3486
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3487
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3488
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3489
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3490
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3491
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3492
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3493
0
      AsmString = "movge %icc, $\x02, $\x01";
3494
0
      break;
3495
0
    }
3496
72
    if (MCInst_getNumOperands(MI) == 3 &&
3497
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3498
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3499
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3500
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3501
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3502
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3503
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3504
0
      AsmString = "movl %icc, $\x02, $\x01";
3505
0
      break;
3506
0
    }
3507
72
    if (MCInst_getNumOperands(MI) == 3 &&
3508
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3509
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3510
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3511
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3512
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3513
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3514
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3515
0
      AsmString = "movgu %icc, $\x02, $\x01";
3516
0
      break;
3517
0
    }
3518
72
    if (MCInst_getNumOperands(MI) == 3 &&
3519
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3520
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3521
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3522
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3523
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3524
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3525
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3526
0
      AsmString = "movleu %icc, $\x02, $\x01";
3527
0
      break;
3528
0
    }
3529
72
    if (MCInst_getNumOperands(MI) == 3 &&
3530
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3531
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3532
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3533
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3534
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3535
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3536
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3537
0
      AsmString = "movcc %icc, $\x02, $\x01";
3538
0
      break;
3539
0
    }
3540
72
    if (MCInst_getNumOperands(MI) == 3 &&
3541
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3542
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3543
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3544
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3545
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3546
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3547
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3548
0
      AsmString = "movcs %icc, $\x02, $\x01";
3549
0
      break;
3550
0
    }
3551
72
    if (MCInst_getNumOperands(MI) == 3 &&
3552
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3553
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3554
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3555
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3556
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3557
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3558
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3559
0
      AsmString = "movpos %icc, $\x02, $\x01";
3560
0
      break;
3561
0
    }
3562
72
    if (MCInst_getNumOperands(MI) == 3 &&
3563
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3564
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3565
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3566
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3567
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3568
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3569
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3570
0
      AsmString = "movneg %icc, $\x02, $\x01";
3571
0
      break;
3572
0
    }
3573
72
    if (MCInst_getNumOperands(MI) == 3 &&
3574
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3575
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3576
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3577
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3578
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3579
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3580
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3581
0
      AsmString = "movvc %icc, $\x02, $\x01";
3582
0
      break;
3583
0
    }
3584
72
    if (MCInst_getNumOperands(MI) == 3 &&
3585
72
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3586
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3587
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3588
72
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3589
72
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3590
72
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3591
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3592
0
      AsmString = "movvs %icc, $\x02, $\x01";
3593
0
      break;
3594
0
    }
3595
72
    return NULL;
3596
44
  case SP_MOVXCCri:
3597
44
    if (MCInst_getNumOperands(MI) == 3 &&
3598
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3599
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3600
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3601
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3602
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3603
0
      AsmString = "mova %xcc, $\x02, $\x01";
3604
0
      break;
3605
0
    }
3606
44
    if (MCInst_getNumOperands(MI) == 3 &&
3607
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3608
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3609
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3610
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3611
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3612
0
      AsmString = "movn %xcc, $\x02, $\x01";
3613
0
      break;
3614
0
    }
3615
44
    if (MCInst_getNumOperands(MI) == 3 &&
3616
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3617
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3618
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3619
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3620
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3621
0
      AsmString = "movne %xcc, $\x02, $\x01";
3622
0
      break;
3623
0
    }
3624
44
    if (MCInst_getNumOperands(MI) == 3 &&
3625
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3626
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3627
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3628
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3629
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3630
0
      AsmString = "move %xcc, $\x02, $\x01";
3631
0
      break;
3632
0
    }
3633
44
    if (MCInst_getNumOperands(MI) == 3 &&
3634
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3635
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3636
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3637
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3638
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3639
0
      AsmString = "movg %xcc, $\x02, $\x01";
3640
0
      break;
3641
0
    }
3642
44
    if (MCInst_getNumOperands(MI) == 3 &&
3643
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3644
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3645
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3646
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3647
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3648
0
      AsmString = "movle %xcc, $\x02, $\x01";
3649
0
      break;
3650
0
    }
3651
44
    if (MCInst_getNumOperands(MI) == 3 &&
3652
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3653
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3654
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3655
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3656
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3657
0
      AsmString = "movge %xcc, $\x02, $\x01";
3658
0
      break;
3659
0
    }
3660
44
    if (MCInst_getNumOperands(MI) == 3 &&
3661
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3662
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3663
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3664
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3665
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3666
0
      AsmString = "movl %xcc, $\x02, $\x01";
3667
0
      break;
3668
0
    }
3669
44
    if (MCInst_getNumOperands(MI) == 3 &&
3670
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3671
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3672
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3673
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3674
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3675
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3676
0
      break;
3677
0
    }
3678
44
    if (MCInst_getNumOperands(MI) == 3 &&
3679
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3680
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3681
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3682
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3683
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3684
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3685
0
      break;
3686
0
    }
3687
44
    if (MCInst_getNumOperands(MI) == 3 &&
3688
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3689
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3690
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3691
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3692
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3693
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3694
0
      break;
3695
0
    }
3696
44
    if (MCInst_getNumOperands(MI) == 3 &&
3697
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3698
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3699
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3700
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3701
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3702
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3703
0
      break;
3704
0
    }
3705
44
    if (MCInst_getNumOperands(MI) == 3 &&
3706
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3707
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3708
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3709
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3710
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3711
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3712
0
      break;
3713
0
    }
3714
44
    if (MCInst_getNumOperands(MI) == 3 &&
3715
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3716
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3717
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3718
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3719
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3720
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3721
0
      break;
3722
0
    }
3723
44
    if (MCInst_getNumOperands(MI) == 3 &&
3724
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3725
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3726
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3727
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3728
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3729
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3730
0
      break;
3731
0
    }
3732
44
    if (MCInst_getNumOperands(MI) == 3 &&
3733
44
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3734
44
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3735
44
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3736
44
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3737
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3738
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3739
0
      break;
3740
0
    }
3741
44
    return NULL;
3742
68
  case SP_MOVXCCrr:
3743
68
    if (MCInst_getNumOperands(MI) == 3 &&
3744
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3745
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3746
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3747
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3748
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3749
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3750
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3751
0
      AsmString = "mova %xcc, $\x02, $\x01";
3752
0
      break;
3753
0
    }
3754
68
    if (MCInst_getNumOperands(MI) == 3 &&
3755
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3756
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3757
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3758
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3759
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3760
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3761
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3762
0
      AsmString = "movn %xcc, $\x02, $\x01";
3763
0
      break;
3764
0
    }
3765
68
    if (MCInst_getNumOperands(MI) == 3 &&
3766
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3767
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3768
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3769
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3770
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3771
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3772
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3773
0
      AsmString = "movne %xcc, $\x02, $\x01";
3774
0
      break;
3775
0
    }
3776
68
    if (MCInst_getNumOperands(MI) == 3 &&
3777
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3778
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3779
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3780
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3781
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3782
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3783
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3784
0
      AsmString = "move %xcc, $\x02, $\x01";
3785
0
      break;
3786
0
    }
3787
68
    if (MCInst_getNumOperands(MI) == 3 &&
3788
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3789
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3790
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3791
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3792
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3793
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3794
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3795
0
      AsmString = "movg %xcc, $\x02, $\x01";
3796
0
      break;
3797
0
    }
3798
68
    if (MCInst_getNumOperands(MI) == 3 &&
3799
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3800
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3801
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3802
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3803
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3804
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3805
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3806
0
      AsmString = "movle %xcc, $\x02, $\x01";
3807
0
      break;
3808
0
    }
3809
68
    if (MCInst_getNumOperands(MI) == 3 &&
3810
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3811
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3812
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3813
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3814
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3815
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3816
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3817
0
      AsmString = "movge %xcc, $\x02, $\x01";
3818
0
      break;
3819
0
    }
3820
68
    if (MCInst_getNumOperands(MI) == 3 &&
3821
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3822
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3823
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3824
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3825
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3826
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3827
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3828
0
      AsmString = "movl %xcc, $\x02, $\x01";
3829
0
      break;
3830
0
    }
3831
68
    if (MCInst_getNumOperands(MI) == 3 &&
3832
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3833
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3834
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3835
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3836
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3837
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3838
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3839
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3840
0
      break;
3841
0
    }
3842
68
    if (MCInst_getNumOperands(MI) == 3 &&
3843
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3844
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3845
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3846
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3847
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3848
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3849
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3850
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3851
0
      break;
3852
0
    }
3853
68
    if (MCInst_getNumOperands(MI) == 3 &&
3854
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3855
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3856
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3857
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3858
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3859
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3860
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3861
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3862
0
      break;
3863
0
    }
3864
68
    if (MCInst_getNumOperands(MI) == 3 &&
3865
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3866
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3867
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3868
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3869
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3870
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3871
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3872
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3873
0
      break;
3874
0
    }
3875
68
    if (MCInst_getNumOperands(MI) == 3 &&
3876
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3877
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3878
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3879
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3880
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3881
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3882
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3883
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3884
0
      break;
3885
0
    }
3886
68
    if (MCInst_getNumOperands(MI) == 3 &&
3887
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3888
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3889
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3890
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3891
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3892
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3893
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3894
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3895
0
      break;
3896
0
    }
3897
68
    if (MCInst_getNumOperands(MI) == 3 &&
3898
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3899
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3900
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3901
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3902
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3903
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3904
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3905
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3906
0
      break;
3907
0
    }
3908
68
    if (MCInst_getNumOperands(MI) == 3 &&
3909
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3910
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3911
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3912
68
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3913
68
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3914
68
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3915
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3916
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3917
0
      break;
3918
0
    }
3919
68
    return NULL;
3920
270
  case SP_ORri:
3921
270
    if (MCInst_getNumOperands(MI) == 3 &&
3922
270
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3923
270
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3924
270
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3925
      // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3926
36
      AsmString = "mov $\x03, $\x01";
3927
36
      break;
3928
36
    }
3929
234
    return NULL;
3930
215
  case SP_ORrr:
3931
215
    if (MCInst_getNumOperands(MI) == 3 &&
3932
215
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3933
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3934
215
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3935
215
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3936
215
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3937
      // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3938
53
      AsmString = "mov $\x03, $\x01";
3939
53
      break;
3940
53
    }
3941
162
    return NULL;
3942
120
  case SP_RESTORErr:
3943
120
    if (MCInst_getNumOperands(MI) == 3 &&
3944
120
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3945
120
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3946
120
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3947
      // (RESTORErr G0, G0, G0)
3948
10
      AsmString = "restore";
3949
10
      break;
3950
10
    }
3951
110
    return NULL;
3952
0
  case SP_RET:
3953
0
    if (MCInst_getNumOperands(MI) == 1 &&
3954
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3955
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3956
      // (RET 8)
3957
0
      AsmString = "ret";
3958
0
      break;
3959
0
    }
3960
0
    return NULL;
3961
0
  case SP_RETL:
3962
0
    if (MCInst_getNumOperands(MI) == 1 &&
3963
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3964
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3965
      // (RETL 8)
3966
0
      AsmString = "retl";
3967
0
      break;
3968
0
    }
3969
0
    return NULL;
3970
1.22k
  case SP_TXCCri:
3971
1.22k
    if (MCInst_getNumOperands(MI) == 3 &&
3972
1.22k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3973
1.22k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3974
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3975
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3976
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3977
88
      AsmString = "ta %xcc, $\x01 + $\x02";
3978
88
      break;
3979
88
    }
3980
1.13k
    if (MCInst_getNumOperands(MI) == 3 &&
3981
1.13k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3982
1.13k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3983
1.13k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3984
      // (TXCCri G0, i32imm:$imm, 8)
3985
0
      AsmString = "ta %xcc, $\x02";
3986
0
      break;
3987
0
    }
3988
1.13k
    if (MCInst_getNumOperands(MI) == 3 &&
3989
1.13k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3990
1.13k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3991
1.13k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3992
1.13k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3993
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3994
67
      AsmString = "tn %xcc, $\x01 + $\x02";
3995
67
      break;
3996
67
    }
3997
1.06k
    if (MCInst_getNumOperands(MI) == 3 &&
3998
1.06k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3999
1.06k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4000
1.06k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4001
      // (TXCCri G0, i32imm:$imm, 0)
4002
0
      AsmString = "tn %xcc, $\x02";
4003
0
      break;
4004
0
    }
4005
1.06k
    if (MCInst_getNumOperands(MI) == 3 &&
4006
1.06k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4007
1.06k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4008
1.06k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4009
1.06k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4010
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4011
206
      AsmString = "tne %xcc, $\x01 + $\x02";
4012
206
      break;
4013
206
    }
4014
860
    if (MCInst_getNumOperands(MI) == 3 &&
4015
860
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4016
860
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4017
860
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4018
      // (TXCCri G0, i32imm:$imm, 9)
4019
0
      AsmString = "tne %xcc, $\x02";
4020
0
      break;
4021
0
    }
4022
860
    if (MCInst_getNumOperands(MI) == 3 &&
4023
860
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4024
860
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4025
860
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4026
860
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4027
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4028
10
      AsmString = "te %xcc, $\x01 + $\x02";
4029
10
      break;
4030
10
    }
4031
850
    if (MCInst_getNumOperands(MI) == 3 &&
4032
850
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4033
850
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4034
850
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4035
      // (TXCCri G0, i32imm:$imm, 1)
4036
0
      AsmString = "te %xcc, $\x02";
4037
0
      break;
4038
0
    }
4039
850
    if (MCInst_getNumOperands(MI) == 3 &&
4040
850
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4041
850
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4042
850
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4043
850
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4044
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4045
74
      AsmString = "tg %xcc, $\x01 + $\x02";
4046
74
      break;
4047
74
    }
4048
776
    if (MCInst_getNumOperands(MI) == 3 &&
4049
776
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4050
776
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4051
776
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4052
      // (TXCCri G0, i32imm:$imm, 10)
4053
0
      AsmString = "tg %xcc, $\x02";
4054
0
      break;
4055
0
    }
4056
776
    if (MCInst_getNumOperands(MI) == 3 &&
4057
776
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4058
776
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4059
776
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4060
776
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4061
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4062
45
      AsmString = "tle %xcc, $\x01 + $\x02";
4063
45
      break;
4064
45
    }
4065
731
    if (MCInst_getNumOperands(MI) == 3 &&
4066
731
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4067
731
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4068
731
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4069
      // (TXCCri G0, i32imm:$imm, 2)
4070
0
      AsmString = "tle %xcc, $\x02";
4071
0
      break;
4072
0
    }
4073
731
    if (MCInst_getNumOperands(MI) == 3 &&
4074
731
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4075
731
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4076
731
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4077
731
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4078
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4079
151
      AsmString = "tge %xcc, $\x01 + $\x02";
4080
151
      break;
4081
151
    }
4082
580
    if (MCInst_getNumOperands(MI) == 3 &&
4083
580
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4084
580
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4085
580
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4086
      // (TXCCri G0, i32imm:$imm, 11)
4087
0
      AsmString = "tge %xcc, $\x02";
4088
0
      break;
4089
0
    }
4090
580
    if (MCInst_getNumOperands(MI) == 3 &&
4091
580
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4092
580
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4093
580
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4094
580
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4095
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4096
70
      AsmString = "tl %xcc, $\x01 + $\x02";
4097
70
      break;
4098
70
    }
4099
510
    if (MCInst_getNumOperands(MI) == 3 &&
4100
510
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4101
510
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4102
510
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4103
      // (TXCCri G0, i32imm:$imm, 3)
4104
0
      AsmString = "tl %xcc, $\x02";
4105
0
      break;
4106
0
    }
4107
510
    if (MCInst_getNumOperands(MI) == 3 &&
4108
510
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4109
510
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4110
510
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4111
510
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4112
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4113
34
      AsmString = "tgu %xcc, $\x01 + $\x02";
4114
34
      break;
4115
34
    }
4116
476
    if (MCInst_getNumOperands(MI) == 3 &&
4117
476
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4118
476
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4119
476
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4120
      // (TXCCri G0, i32imm:$imm, 12)
4121
0
      AsmString = "tgu %xcc, $\x02";
4122
0
      break;
4123
0
    }
4124
476
    if (MCInst_getNumOperands(MI) == 3 &&
4125
476
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4126
476
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4127
476
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4128
476
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4129
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4130
67
      AsmString = "tleu %xcc, $\x01 + $\x02";
4131
67
      break;
4132
67
    }
4133
409
    if (MCInst_getNumOperands(MI) == 3 &&
4134
409
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4135
409
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4136
409
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4137
      // (TXCCri G0, i32imm:$imm, 4)
4138
0
      AsmString = "tleu %xcc, $\x02";
4139
0
      break;
4140
0
    }
4141
409
    if (MCInst_getNumOperands(MI) == 3 &&
4142
409
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4143
409
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4144
409
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4145
409
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4146
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4147
82
      AsmString = "tcc %xcc, $\x01 + $\x02";
4148
82
      break;
4149
82
    }
4150
327
    if (MCInst_getNumOperands(MI) == 3 &&
4151
327
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4152
327
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4153
327
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4154
      // (TXCCri G0, i32imm:$imm, 13)
4155
0
      AsmString = "tcc %xcc, $\x02";
4156
0
      break;
4157
0
    }
4158
327
    if (MCInst_getNumOperands(MI) == 3 &&
4159
327
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4160
327
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4161
327
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4162
327
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4163
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4164
36
      AsmString = "tcs %xcc, $\x01 + $\x02";
4165
36
      break;
4166
36
    }
4167
291
    if (MCInst_getNumOperands(MI) == 3 &&
4168
291
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4169
291
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4170
291
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4171
      // (TXCCri G0, i32imm:$imm, 5)
4172
0
      AsmString = "tcs %xcc, $\x02";
4173
0
      break;
4174
0
    }
4175
291
    if (MCInst_getNumOperands(MI) == 3 &&
4176
291
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4177
291
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4178
291
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4179
291
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4180
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4181
34
      AsmString = "tpos %xcc, $\x01 + $\x02";
4182
34
      break;
4183
34
    }
4184
257
    if (MCInst_getNumOperands(MI) == 3 &&
4185
257
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4186
257
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4187
257
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4188
      // (TXCCri G0, i32imm:$imm, 14)
4189
0
      AsmString = "tpos %xcc, $\x02";
4190
0
      break;
4191
0
    }
4192
257
    if (MCInst_getNumOperands(MI) == 3 &&
4193
257
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4194
257
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4195
257
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4196
257
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4197
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4198
18
      AsmString = "tneg %xcc, $\x01 + $\x02";
4199
18
      break;
4200
18
    }
4201
239
    if (MCInst_getNumOperands(MI) == 3 &&
4202
239
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4203
239
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4204
239
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4205
      // (TXCCri G0, i32imm:$imm, 6)
4206
0
      AsmString = "tneg %xcc, $\x02";
4207
0
      break;
4208
0
    }
4209
239
    if (MCInst_getNumOperands(MI) == 3 &&
4210
239
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4211
239
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4212
239
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4213
239
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4214
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4215
71
      AsmString = "tvc %xcc, $\x01 + $\x02";
4216
71
      break;
4217
71
    }
4218
168
    if (MCInst_getNumOperands(MI) == 3 &&
4219
168
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4220
168
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4221
168
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4222
      // (TXCCri G0, i32imm:$imm, 15)
4223
0
      AsmString = "tvc %xcc, $\x02";
4224
0
      break;
4225
0
    }
4226
168
    if (MCInst_getNumOperands(MI) == 3 &&
4227
168
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4228
168
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4229
168
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4230
168
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4231
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4232
168
      AsmString = "tvs %xcc, $\x01 + $\x02";
4233
168
      break;
4234
168
    }
4235
0
    if (MCInst_getNumOperands(MI) == 3 &&
4236
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4237
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4238
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4239
      // (TXCCri G0, i32imm:$imm, 7)
4240
0
      AsmString = "tvs %xcc, $\x02";
4241
0
      break;
4242
0
    }
4243
0
    return NULL;
4244
1.21k
  case SP_TXCCrr:
4245
1.21k
    if (MCInst_getNumOperands(MI) == 3 &&
4246
1.21k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4247
1.21k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4248
1.21k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4249
1.21k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4250
1.21k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4251
1.21k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4252
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4253
164
      AsmString = "ta %xcc, $\x01 + $\x02";
4254
164
      break;
4255
164
    }
4256
1.05k
    if (MCInst_getNumOperands(MI) == 3 &&
4257
1.05k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4258
1.05k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4259
1.05k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4260
1.05k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4261
1.05k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4262
      // (TXCCrr G0, IntRegs:$rs2, 8)
4263
0
      AsmString = "ta %xcc, $\x02";
4264
0
      break;
4265
0
    }
4266
1.05k
    if (MCInst_getNumOperands(MI) == 3 &&
4267
1.05k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4268
1.05k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4269
1.05k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4270
1.05k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4271
1.05k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4272
1.05k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4273
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4274
74
      AsmString = "tn %xcc, $\x01 + $\x02";
4275
74
      break;
4276
74
    }
4277
979
    if (MCInst_getNumOperands(MI) == 3 &&
4278
979
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4279
979
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4280
979
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4281
979
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4282
979
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4283
      // (TXCCrr G0, IntRegs:$rs2, 0)
4284
0
      AsmString = "tn %xcc, $\x02";
4285
0
      break;
4286
0
    }
4287
979
    if (MCInst_getNumOperands(MI) == 3 &&
4288
979
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4289
979
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4290
979
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4291
979
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4292
979
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4293
979
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4294
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4295
21
      AsmString = "tne %xcc, $\x01 + $\x02";
4296
21
      break;
4297
21
    }
4298
958
    if (MCInst_getNumOperands(MI) == 3 &&
4299
958
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4300
958
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4301
958
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4302
958
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4303
958
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4304
      // (TXCCrr G0, IntRegs:$rs2, 9)
4305
0
      AsmString = "tne %xcc, $\x02";
4306
0
      break;
4307
0
    }
4308
958
    if (MCInst_getNumOperands(MI) == 3 &&
4309
958
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4310
958
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4311
958
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4312
958
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4313
958
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4314
958
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4315
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4316
39
      AsmString = "te %xcc, $\x01 + $\x02";
4317
39
      break;
4318
39
    }
4319
919
    if (MCInst_getNumOperands(MI) == 3 &&
4320
919
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4321
919
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4322
919
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4323
919
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4324
919
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4325
      // (TXCCrr G0, IntRegs:$rs2, 1)
4326
0
      AsmString = "te %xcc, $\x02";
4327
0
      break;
4328
0
    }
4329
919
    if (MCInst_getNumOperands(MI) == 3 &&
4330
919
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4331
919
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4332
919
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4333
919
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4334
919
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4335
919
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4336
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4337
36
      AsmString = "tg %xcc, $\x01 + $\x02";
4338
36
      break;
4339
36
    }
4340
883
    if (MCInst_getNumOperands(MI) == 3 &&
4341
883
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4342
883
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4343
883
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4344
883
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4345
883
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4346
      // (TXCCrr G0, IntRegs:$rs2, 10)
4347
0
      AsmString = "tg %xcc, $\x02";
4348
0
      break;
4349
0
    }
4350
883
    if (MCInst_getNumOperands(MI) == 3 &&
4351
883
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4352
883
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4353
883
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4354
883
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4355
883
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4356
883
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4357
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4358
34
      AsmString = "tle %xcc, $\x01 + $\x02";
4359
34
      break;
4360
34
    }
4361
849
    if (MCInst_getNumOperands(MI) == 3 &&
4362
849
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4363
849
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4364
849
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4365
849
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4366
849
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4367
      // (TXCCrr G0, IntRegs:$rs2, 2)
4368
0
      AsmString = "tle %xcc, $\x02";
4369
0
      break;
4370
0
    }
4371
849
    if (MCInst_getNumOperands(MI) == 3 &&
4372
849
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4373
849
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4374
849
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4375
849
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4376
849
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4377
849
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4378
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4379
10
      AsmString = "tge %xcc, $\x01 + $\x02";
4380
10
      break;
4381
10
    }
4382
839
    if (MCInst_getNumOperands(MI) == 3 &&
4383
839
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4384
839
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4385
839
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4386
839
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4387
839
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4388
      // (TXCCrr G0, IntRegs:$rs2, 11)
4389
0
      AsmString = "tge %xcc, $\x02";
4390
0
      break;
4391
0
    }
4392
839
    if (MCInst_getNumOperands(MI) == 3 &&
4393
839
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4394
839
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4395
839
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4396
839
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4397
839
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4398
839
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4399
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4400
36
      AsmString = "tl %xcc, $\x01 + $\x02";
4401
36
      break;
4402
36
    }
4403
803
    if (MCInst_getNumOperands(MI) == 3 &&
4404
803
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4405
803
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4406
803
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4407
803
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4408
803
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4409
      // (TXCCrr G0, IntRegs:$rs2, 3)
4410
0
      AsmString = "tl %xcc, $\x02";
4411
0
      break;
4412
0
    }
4413
803
    if (MCInst_getNumOperands(MI) == 3 &&
4414
803
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4415
803
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4416
803
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4417
803
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4418
803
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4419
803
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4420
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4421
115
      AsmString = "tgu %xcc, $\x01 + $\x02";
4422
115
      break;
4423
115
    }
4424
688
    if (MCInst_getNumOperands(MI) == 3 &&
4425
688
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4426
688
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4427
688
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4428
688
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4429
688
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4430
      // (TXCCrr G0, IntRegs:$rs2, 12)
4431
0
      AsmString = "tgu %xcc, $\x02";
4432
0
      break;
4433
0
    }
4434
688
    if (MCInst_getNumOperands(MI) == 3 &&
4435
688
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4436
688
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4437
688
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4438
688
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4439
688
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4440
688
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4441
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4442
38
      AsmString = "tleu %xcc, $\x01 + $\x02";
4443
38
      break;
4444
38
    }
4445
650
    if (MCInst_getNumOperands(MI) == 3 &&
4446
650
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4447
650
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4448
650
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4449
650
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4450
650
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4451
      // (TXCCrr G0, IntRegs:$rs2, 4)
4452
0
      AsmString = "tleu %xcc, $\x02";
4453
0
      break;
4454
0
    }
4455
650
    if (MCInst_getNumOperands(MI) == 3 &&
4456
650
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4457
650
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4458
650
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4459
650
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4460
650
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4461
650
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4462
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4463
22
      AsmString = "tcc %xcc, $\x01 + $\x02";
4464
22
      break;
4465
22
    }
4466
628
    if (MCInst_getNumOperands(MI) == 3 &&
4467
628
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4468
628
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4469
628
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4470
628
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4471
628
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4472
      // (TXCCrr G0, IntRegs:$rs2, 13)
4473
0
      AsmString = "tcc %xcc, $\x02";
4474
0
      break;
4475
0
    }
4476
628
    if (MCInst_getNumOperands(MI) == 3 &&
4477
628
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4478
628
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4479
628
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4480
628
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4481
628
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4482
628
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4483
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4484
10
      AsmString = "tcs %xcc, $\x01 + $\x02";
4485
10
      break;
4486
10
    }
4487
618
    if (MCInst_getNumOperands(MI) == 3 &&
4488
618
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4489
618
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4490
618
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4491
618
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4492
618
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4493
      // (TXCCrr G0, IntRegs:$rs2, 5)
4494
0
      AsmString = "tcs %xcc, $\x02";
4495
0
      break;
4496
0
    }
4497
618
    if (MCInst_getNumOperands(MI) == 3 &&
4498
618
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4499
618
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4500
618
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4501
618
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4502
618
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4503
618
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4504
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4505
20
      AsmString = "tpos %xcc, $\x01 + $\x02";
4506
20
      break;
4507
20
    }
4508
598
    if (MCInst_getNumOperands(MI) == 3 &&
4509
598
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4510
598
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4511
598
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4512
598
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4513
598
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4514
      // (TXCCrr G0, IntRegs:$rs2, 14)
4515
0
      AsmString = "tpos %xcc, $\x02";
4516
0
      break;
4517
0
    }
4518
598
    if (MCInst_getNumOperands(MI) == 3 &&
4519
598
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4520
598
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4521
598
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4522
598
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4523
598
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4524
598
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4525
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4526
23
      AsmString = "tneg %xcc, $\x01 + $\x02";
4527
23
      break;
4528
23
    }
4529
575
    if (MCInst_getNumOperands(MI) == 3 &&
4530
575
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4531
575
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4532
575
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4533
575
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4534
575
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4535
      // (TXCCrr G0, IntRegs:$rs2, 6)
4536
0
      AsmString = "tneg %xcc, $\x02";
4537
0
      break;
4538
0
    }
4539
575
    if (MCInst_getNumOperands(MI) == 3 &&
4540
575
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4541
575
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4542
575
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4543
575
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4544
575
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4545
575
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4546
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4547
203
      AsmString = "tvc %xcc, $\x01 + $\x02";
4548
203
      break;
4549
203
    }
4550
372
    if (MCInst_getNumOperands(MI) == 3 &&
4551
372
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4552
372
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4553
372
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4554
372
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4555
372
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4556
      // (TXCCrr G0, IntRegs:$rs2, 15)
4557
0
      AsmString = "tvc %xcc, $\x02";
4558
0
      break;
4559
0
    }
4560
372
    if (MCInst_getNumOperands(MI) == 3 &&
4561
372
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4562
372
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4563
372
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4564
372
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4565
372
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4566
372
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4567
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4568
372
      AsmString = "tvs %xcc, $\x01 + $\x02";
4569
372
      break;
4570
372
    }
4571
0
    if (MCInst_getNumOperands(MI) == 3 &&
4572
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4573
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4574
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4575
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4576
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4577
      // (TXCCrr G0, IntRegs:$rs2, 7)
4578
0
      AsmString = "tvs %xcc, $\x02";
4579
0
      break;
4580
0
    }
4581
0
    return NULL;
4582
669
  case SP_V9FCMPD:
4583
669
    if (MCInst_getNumOperands(MI) == 3 &&
4584
669
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4585
669
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4586
669
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4587
669
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4588
669
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4589
      // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4590
205
      AsmString = "fcmpd $\x02, $\x03";
4591
205
      break;
4592
205
    }
4593
464
    return NULL;
4594
613
  case SP_V9FCMPED:
4595
613
    if (MCInst_getNumOperands(MI) == 3 &&
4596
613
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4597
613
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4598
613
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4599
613
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4600
613
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4601
      // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4602
107
      AsmString = "fcmped $\x02, $\x03";
4603
107
      break;
4604
107
    }
4605
506
    return NULL;
4606
117
  case SP_V9FCMPEQ:
4607
117
    if (MCInst_getNumOperands(MI) == 3 &&
4608
117
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4609
117
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4610
117
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4611
117
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4612
117
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4613
      // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4614
50
      AsmString = "fcmpeq $\x02, $\x03";
4615
50
      break;
4616
50
    }
4617
67
    return NULL;
4618
559
  case SP_V9FCMPES:
4619
559
    if (MCInst_getNumOperands(MI) == 3 &&
4620
559
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4621
559
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4622
559
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4623
559
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4624
559
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4625
      // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4626
165
      AsmString = "fcmpes $\x02, $\x03";
4627
165
      break;
4628
165
    }
4629
394
    return NULL;
4630
72
  case SP_V9FCMPQ:
4631
72
    if (MCInst_getNumOperands(MI) == 3 &&
4632
72
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4633
72
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4634
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4635
72
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4636
72
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4637
      // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4638
18
      AsmString = "fcmpq $\x02, $\x03";
4639
18
      break;
4640
18
    }
4641
54
    return NULL;
4642
398
  case SP_V9FCMPS:
4643
398
    if (MCInst_getNumOperands(MI) == 3 &&
4644
398
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4645
398
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4646
398
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4647
398
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4648
398
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4649
      // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4650
44
      AsmString = "fcmps $\x02, $\x03";
4651
44
      break;
4652
44
    }
4653
354
    return NULL;
4654
81
  case SP_V9FMOVD_FCC:
4655
81
    if (MCInst_getNumOperands(MI) == 4 &&
4656
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4657
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4658
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4659
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4660
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4661
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4662
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4663
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4664
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4665
0
      AsmString = "fmovda $\x02, $\x03, $\x01";
4666
0
      break;
4667
0
    }
4668
81
    if (MCInst_getNumOperands(MI) == 4 &&
4669
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4670
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4671
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4672
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4673
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4674
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4675
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4676
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4677
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4678
0
      AsmString = "fmovdn $\x02, $\x03, $\x01";
4679
0
      break;
4680
0
    }
4681
81
    if (MCInst_getNumOperands(MI) == 4 &&
4682
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4683
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4684
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4685
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4686
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4687
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4688
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4689
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4690
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4691
0
      AsmString = "fmovdu $\x02, $\x03, $\x01";
4692
0
      break;
4693
0
    }
4694
81
    if (MCInst_getNumOperands(MI) == 4 &&
4695
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4696
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4697
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4698
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4699
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4700
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4701
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4702
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4703
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4704
0
      AsmString = "fmovdg $\x02, $\x03, $\x01";
4705
0
      break;
4706
0
    }
4707
81
    if (MCInst_getNumOperands(MI) == 4 &&
4708
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4709
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4710
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4711
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4712
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4713
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4714
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4715
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4716
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4717
0
      AsmString = "fmovdug $\x02, $\x03, $\x01";
4718
0
      break;
4719
0
    }
4720
81
    if (MCInst_getNumOperands(MI) == 4 &&
4721
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4722
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4723
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4724
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4725
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4726
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4727
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4728
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4729
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4730
0
      AsmString = "fmovdl $\x02, $\x03, $\x01";
4731
0
      break;
4732
0
    }
4733
81
    if (MCInst_getNumOperands(MI) == 4 &&
4734
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4735
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4736
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4737
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4738
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4739
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4740
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4741
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4742
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4743
0
      AsmString = "fmovdul $\x02, $\x03, $\x01";
4744
0
      break;
4745
0
    }
4746
81
    if (MCInst_getNumOperands(MI) == 4 &&
4747
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4748
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4749
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4750
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4751
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4752
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4753
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4754
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4755
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4756
0
      AsmString = "fmovdlg $\x02, $\x03, $\x01";
4757
0
      break;
4758
0
    }
4759
81
    if (MCInst_getNumOperands(MI) == 4 &&
4760
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4761
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4762
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4763
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4764
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4765
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4766
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4767
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4768
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4769
0
      AsmString = "fmovdne $\x02, $\x03, $\x01";
4770
0
      break;
4771
0
    }
4772
81
    if (MCInst_getNumOperands(MI) == 4 &&
4773
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4774
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4775
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4776
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4777
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4778
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4779
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4780
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4781
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4782
0
      AsmString = "fmovde $\x02, $\x03, $\x01";
4783
0
      break;
4784
0
    }
4785
81
    if (MCInst_getNumOperands(MI) == 4 &&
4786
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4787
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4788
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4789
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4790
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4791
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4792
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4793
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4794
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4795
0
      AsmString = "fmovdue $\x02, $\x03, $\x01";
4796
0
      break;
4797
0
    }
4798
81
    if (MCInst_getNumOperands(MI) == 4 &&
4799
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4800
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4801
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4802
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4803
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4804
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4805
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4806
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4807
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4808
0
      AsmString = "fmovdge $\x02, $\x03, $\x01";
4809
0
      break;
4810
0
    }
4811
81
    if (MCInst_getNumOperands(MI) == 4 &&
4812
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4813
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4814
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4815
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4816
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4817
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4818
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4819
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4820
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4821
0
      AsmString = "fmovduge $\x02, $\x03, $\x01";
4822
0
      break;
4823
0
    }
4824
81
    if (MCInst_getNumOperands(MI) == 4 &&
4825
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4826
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4827
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4828
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4829
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4830
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4831
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4832
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4833
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4834
0
      AsmString = "fmovdle $\x02, $\x03, $\x01";
4835
0
      break;
4836
0
    }
4837
81
    if (MCInst_getNumOperands(MI) == 4 &&
4838
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4839
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4840
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4841
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4842
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4843
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4844
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4845
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4846
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4847
0
      AsmString = "fmovdule $\x02, $\x03, $\x01";
4848
0
      break;
4849
0
    }
4850
81
    if (MCInst_getNumOperands(MI) == 4 &&
4851
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4852
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4853
81
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4854
81
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4855
81
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4856
81
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4857
81
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4858
81
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4859
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4860
0
      AsmString = "fmovdo $\x02, $\x03, $\x01";
4861
0
      break;
4862
0
    }
4863
81
    return NULL;
4864
39
  case SP_V9FMOVQ_FCC:
4865
39
    if (MCInst_getNumOperands(MI) == 4 &&
4866
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4867
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4868
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4869
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4870
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4871
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4872
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4873
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4874
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4875
0
      AsmString = "fmovqa $\x02, $\x03, $\x01";
4876
0
      break;
4877
0
    }
4878
39
    if (MCInst_getNumOperands(MI) == 4 &&
4879
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4880
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4881
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4882
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4883
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4884
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4885
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4886
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4887
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4888
0
      AsmString = "fmovqn $\x02, $\x03, $\x01";
4889
0
      break;
4890
0
    }
4891
39
    if (MCInst_getNumOperands(MI) == 4 &&
4892
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4893
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4894
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4895
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4896
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4897
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4898
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4899
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4900
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4901
0
      AsmString = "fmovqu $\x02, $\x03, $\x01";
4902
0
      break;
4903
0
    }
4904
39
    if (MCInst_getNumOperands(MI) == 4 &&
4905
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4906
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4907
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4908
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4909
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4910
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4911
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4912
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4913
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4914
0
      AsmString = "fmovqg $\x02, $\x03, $\x01";
4915
0
      break;
4916
0
    }
4917
39
    if (MCInst_getNumOperands(MI) == 4 &&
4918
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4919
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4920
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4921
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4922
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4923
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4924
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4925
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4926
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4927
0
      AsmString = "fmovqug $\x02, $\x03, $\x01";
4928
0
      break;
4929
0
    }
4930
39
    if (MCInst_getNumOperands(MI) == 4 &&
4931
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4932
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4933
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4934
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4935
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4936
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4937
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4938
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4939
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4940
0
      AsmString = "fmovql $\x02, $\x03, $\x01";
4941
0
      break;
4942
0
    }
4943
39
    if (MCInst_getNumOperands(MI) == 4 &&
4944
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4945
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4946
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4947
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4948
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4949
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4950
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4951
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4952
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4953
0
      AsmString = "fmovqul $\x02, $\x03, $\x01";
4954
0
      break;
4955
0
    }
4956
39
    if (MCInst_getNumOperands(MI) == 4 &&
4957
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4958
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4959
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4960
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4961
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4962
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4963
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4964
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4965
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4966
0
      AsmString = "fmovqlg $\x02, $\x03, $\x01";
4967
0
      break;
4968
0
    }
4969
39
    if (MCInst_getNumOperands(MI) == 4 &&
4970
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4971
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4972
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4973
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4974
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4975
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4976
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4977
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4978
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4979
0
      AsmString = "fmovqne $\x02, $\x03, $\x01";
4980
0
      break;
4981
0
    }
4982
39
    if (MCInst_getNumOperands(MI) == 4 &&
4983
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4984
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4985
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4986
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4987
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4988
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4989
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4990
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4991
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4992
0
      AsmString = "fmovqe $\x02, $\x03, $\x01";
4993
0
      break;
4994
0
    }
4995
39
    if (MCInst_getNumOperands(MI) == 4 &&
4996
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4997
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4998
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4999
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5000
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5001
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5002
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5003
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5004
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5005
0
      AsmString = "fmovque $\x02, $\x03, $\x01";
5006
0
      break;
5007
0
    }
5008
39
    if (MCInst_getNumOperands(MI) == 4 &&
5009
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5010
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5011
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5012
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5013
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5014
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5015
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5016
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5017
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5018
0
      AsmString = "fmovqge $\x02, $\x03, $\x01";
5019
0
      break;
5020
0
    }
5021
39
    if (MCInst_getNumOperands(MI) == 4 &&
5022
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5023
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5024
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5025
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5026
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5027
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5028
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5029
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5030
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5031
0
      AsmString = "fmovquge $\x02, $\x03, $\x01";
5032
0
      break;
5033
0
    }
5034
39
    if (MCInst_getNumOperands(MI) == 4 &&
5035
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5036
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5037
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5038
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5039
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5040
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5041
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5042
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5043
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5044
0
      AsmString = "fmovqle $\x02, $\x03, $\x01";
5045
0
      break;
5046
0
    }
5047
39
    if (MCInst_getNumOperands(MI) == 4 &&
5048
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5049
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5050
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5051
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5052
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5053
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5054
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5055
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5056
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5057
0
      AsmString = "fmovqule $\x02, $\x03, $\x01";
5058
0
      break;
5059
0
    }
5060
39
    if (MCInst_getNumOperands(MI) == 4 &&
5061
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5062
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5063
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5064
39
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5065
39
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5066
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5067
39
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5068
39
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5069
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5070
0
      AsmString = "fmovqo $\x02, $\x03, $\x01";
5071
0
      break;
5072
0
    }
5073
39
    return NULL;
5074
210
  case SP_V9FMOVS_FCC:
5075
210
    if (MCInst_getNumOperands(MI) == 4 &&
5076
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5077
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5078
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5079
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5080
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5081
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5082
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5083
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5084
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5085
0
      AsmString = "fmovsa $\x02, $\x03, $\x01";
5086
0
      break;
5087
0
    }
5088
210
    if (MCInst_getNumOperands(MI) == 4 &&
5089
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5090
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5091
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5092
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5093
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5094
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5095
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5096
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5097
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5098
0
      AsmString = "fmovsn $\x02, $\x03, $\x01";
5099
0
      break;
5100
0
    }
5101
210
    if (MCInst_getNumOperands(MI) == 4 &&
5102
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5103
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5104
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5105
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5106
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5107
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5108
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5109
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5110
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5111
0
      AsmString = "fmovsu $\x02, $\x03, $\x01";
5112
0
      break;
5113
0
    }
5114
210
    if (MCInst_getNumOperands(MI) == 4 &&
5115
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5116
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5117
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5118
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5119
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5120
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5121
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5122
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5123
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5124
0
      AsmString = "fmovsg $\x02, $\x03, $\x01";
5125
0
      break;
5126
0
    }
5127
210
    if (MCInst_getNumOperands(MI) == 4 &&
5128
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5129
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5130
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5131
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5132
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5133
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5134
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5135
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5136
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5137
0
      AsmString = "fmovsug $\x02, $\x03, $\x01";
5138
0
      break;
5139
0
    }
5140
210
    if (MCInst_getNumOperands(MI) == 4 &&
5141
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5142
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5143
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5144
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5145
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5146
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5147
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5148
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5149
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5150
0
      AsmString = "fmovsl $\x02, $\x03, $\x01";
5151
0
      break;
5152
0
    }
5153
210
    if (MCInst_getNumOperands(MI) == 4 &&
5154
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5155
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5156
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5157
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5158
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5159
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5160
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5161
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5162
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5163
0
      AsmString = "fmovsul $\x02, $\x03, $\x01";
5164
0
      break;
5165
0
    }
5166
210
    if (MCInst_getNumOperands(MI) == 4 &&
5167
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5168
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5169
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5170
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5171
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5172
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5173
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5174
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5175
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5176
0
      AsmString = "fmovslg $\x02, $\x03, $\x01";
5177
0
      break;
5178
0
    }
5179
210
    if (MCInst_getNumOperands(MI) == 4 &&
5180
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5181
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5182
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5183
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5184
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5185
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5186
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5187
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5188
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5189
0
      AsmString = "fmovsne $\x02, $\x03, $\x01";
5190
0
      break;
5191
0
    }
5192
210
    if (MCInst_getNumOperands(MI) == 4 &&
5193
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5194
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5195
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5196
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5197
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5198
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5199
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5200
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5201
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5202
0
      AsmString = "fmovse $\x02, $\x03, $\x01";
5203
0
      break;
5204
0
    }
5205
210
    if (MCInst_getNumOperands(MI) == 4 &&
5206
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5207
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5208
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5209
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5210
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5211
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5212
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5213
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5214
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5215
0
      AsmString = "fmovsue $\x02, $\x03, $\x01";
5216
0
      break;
5217
0
    }
5218
210
    if (MCInst_getNumOperands(MI) == 4 &&
5219
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5220
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5221
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5222
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5223
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5224
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5225
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5226
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5227
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5228
0
      AsmString = "fmovsge $\x02, $\x03, $\x01";
5229
0
      break;
5230
0
    }
5231
210
    if (MCInst_getNumOperands(MI) == 4 &&
5232
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5233
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5234
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5235
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5236
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5237
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5238
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5239
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5240
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5241
0
      AsmString = "fmovsuge $\x02, $\x03, $\x01";
5242
0
      break;
5243
0
    }
5244
210
    if (MCInst_getNumOperands(MI) == 4 &&
5245
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5246
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5247
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5248
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5249
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5250
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5251
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5252
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5253
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5254
0
      AsmString = "fmovsle $\x02, $\x03, $\x01";
5255
0
      break;
5256
0
    }
5257
210
    if (MCInst_getNumOperands(MI) == 4 &&
5258
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5259
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5260
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5261
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5262
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5263
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5264
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5265
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5266
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5267
0
      AsmString = "fmovsule $\x02, $\x03, $\x01";
5268
0
      break;
5269
0
    }
5270
210
    if (MCInst_getNumOperands(MI) == 4 &&
5271
210
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5272
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5273
210
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5274
210
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5275
210
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5276
210
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5277
210
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5278
210
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5279
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5280
0
      AsmString = "fmovso $\x02, $\x03, $\x01";
5281
0
      break;
5282
0
    }
5283
210
    return NULL;
5284
355
  case SP_V9MOVFCCri:
5285
355
    if (MCInst_getNumOperands(MI) == 4 &&
5286
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5287
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5288
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5289
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5290
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5291
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5292
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5293
0
      AsmString = "mova $\x02, $\x03, $\x01";
5294
0
      break;
5295
0
    }
5296
355
    if (MCInst_getNumOperands(MI) == 4 &&
5297
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5298
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5299
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5300
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5301
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5302
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5303
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5304
0
      AsmString = "movn $\x02, $\x03, $\x01";
5305
0
      break;
5306
0
    }
5307
355
    if (MCInst_getNumOperands(MI) == 4 &&
5308
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5309
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5310
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5311
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5312
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5313
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5314
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5315
0
      AsmString = "movu $\x02, $\x03, $\x01";
5316
0
      break;
5317
0
    }
5318
355
    if (MCInst_getNumOperands(MI) == 4 &&
5319
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5320
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5321
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5322
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5323
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5324
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5325
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5326
0
      AsmString = "movg $\x02, $\x03, $\x01";
5327
0
      break;
5328
0
    }
5329
355
    if (MCInst_getNumOperands(MI) == 4 &&
5330
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5331
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5332
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5333
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5334
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5335
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5336
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5337
0
      AsmString = "movug $\x02, $\x03, $\x01";
5338
0
      break;
5339
0
    }
5340
355
    if (MCInst_getNumOperands(MI) == 4 &&
5341
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5342
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5343
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5344
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5345
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5346
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5347
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5348
0
      AsmString = "movl $\x02, $\x03, $\x01";
5349
0
      break;
5350
0
    }
5351
355
    if (MCInst_getNumOperands(MI) == 4 &&
5352
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5353
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5354
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5355
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5356
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5357
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5358
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5359
0
      AsmString = "movul $\x02, $\x03, $\x01";
5360
0
      break;
5361
0
    }
5362
355
    if (MCInst_getNumOperands(MI) == 4 &&
5363
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5364
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5365
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5366
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5367
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5368
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5369
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5370
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5371
0
      break;
5372
0
    }
5373
355
    if (MCInst_getNumOperands(MI) == 4 &&
5374
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5375
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5376
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5377
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5378
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5379
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5380
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5381
0
      AsmString = "movne $\x02, $\x03, $\x01";
5382
0
      break;
5383
0
    }
5384
355
    if (MCInst_getNumOperands(MI) == 4 &&
5385
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5386
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5387
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5388
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5389
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5390
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5391
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5392
0
      AsmString = "move $\x02, $\x03, $\x01";
5393
0
      break;
5394
0
    }
5395
355
    if (MCInst_getNumOperands(MI) == 4 &&
5396
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5397
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5398
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5399
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5400
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5401
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5402
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5403
0
      AsmString = "movue $\x02, $\x03, $\x01";
5404
0
      break;
5405
0
    }
5406
355
    if (MCInst_getNumOperands(MI) == 4 &&
5407
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5408
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5409
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5410
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5411
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5412
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5413
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5414
0
      AsmString = "movge $\x02, $\x03, $\x01";
5415
0
      break;
5416
0
    }
5417
355
    if (MCInst_getNumOperands(MI) == 4 &&
5418
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5419
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5420
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5421
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5422
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5423
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5424
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5425
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5426
0
      break;
5427
0
    }
5428
355
    if (MCInst_getNumOperands(MI) == 4 &&
5429
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5430
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5431
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5432
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5433
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5434
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5435
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5436
0
      AsmString = "movle $\x02, $\x03, $\x01";
5437
0
      break;
5438
0
    }
5439
355
    if (MCInst_getNumOperands(MI) == 4 &&
5440
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5441
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5442
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5443
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5444
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5445
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5446
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5447
0
      AsmString = "movule $\x02, $\x03, $\x01";
5448
0
      break;
5449
0
    }
5450
355
    if (MCInst_getNumOperands(MI) == 4 &&
5451
355
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5452
355
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5453
355
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5454
355
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5455
355
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5456
355
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5457
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5458
0
      AsmString = "movo $\x02, $\x03, $\x01";
5459
0
      break;
5460
0
    }
5461
355
    return NULL;
5462
228
  case SP_V9MOVFCCrr:
5463
228
    if (MCInst_getNumOperands(MI) == 4 &&
5464
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5465
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5466
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5467
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5468
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5469
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5470
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5471
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5472
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5473
0
      AsmString = "mova $\x02, $\x03, $\x01";
5474
0
      break;
5475
0
    }
5476
228
    if (MCInst_getNumOperands(MI) == 4 &&
5477
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5478
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5479
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5480
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5481
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5482
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5483
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5484
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5485
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5486
0
      AsmString = "movn $\x02, $\x03, $\x01";
5487
0
      break;
5488
0
    }
5489
228
    if (MCInst_getNumOperands(MI) == 4 &&
5490
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5491
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5492
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5493
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5494
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5495
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5496
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5497
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5498
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5499
0
      AsmString = "movu $\x02, $\x03, $\x01";
5500
0
      break;
5501
0
    }
5502
228
    if (MCInst_getNumOperands(MI) == 4 &&
5503
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5504
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5505
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5506
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5507
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5508
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5509
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5510
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5511
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5512
0
      AsmString = "movg $\x02, $\x03, $\x01";
5513
0
      break;
5514
0
    }
5515
228
    if (MCInst_getNumOperands(MI) == 4 &&
5516
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5517
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5518
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5519
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5520
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5521
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5522
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5523
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5524
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5525
0
      AsmString = "movug $\x02, $\x03, $\x01";
5526
0
      break;
5527
0
    }
5528
228
    if (MCInst_getNumOperands(MI) == 4 &&
5529
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5530
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5531
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5532
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5533
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5534
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5535
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5536
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5537
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5538
0
      AsmString = "movl $\x02, $\x03, $\x01";
5539
0
      break;
5540
0
    }
5541
228
    if (MCInst_getNumOperands(MI) == 4 &&
5542
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5543
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5544
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5545
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5546
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5547
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5548
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5549
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5550
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5551
0
      AsmString = "movul $\x02, $\x03, $\x01";
5552
0
      break;
5553
0
    }
5554
228
    if (MCInst_getNumOperands(MI) == 4 &&
5555
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5556
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5557
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5558
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5559
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5560
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5561
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5562
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5563
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5564
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5565
0
      break;
5566
0
    }
5567
228
    if (MCInst_getNumOperands(MI) == 4 &&
5568
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5569
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5570
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5571
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5572
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5573
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5574
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5575
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5576
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5577
0
      AsmString = "movne $\x02, $\x03, $\x01";
5578
0
      break;
5579
0
    }
5580
228
    if (MCInst_getNumOperands(MI) == 4 &&
5581
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5582
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5583
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5584
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5585
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5586
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5587
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5588
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5589
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5590
0
      AsmString = "move $\x02, $\x03, $\x01";
5591
0
      break;
5592
0
    }
5593
228
    if (MCInst_getNumOperands(MI) == 4 &&
5594
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5595
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5596
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5597
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5598
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5599
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5600
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5601
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5602
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5603
0
      AsmString = "movue $\x02, $\x03, $\x01";
5604
0
      break;
5605
0
    }
5606
228
    if (MCInst_getNumOperands(MI) == 4 &&
5607
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5608
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5609
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5610
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5611
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5612
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5613
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5614
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5615
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5616
0
      AsmString = "movge $\x02, $\x03, $\x01";
5617
0
      break;
5618
0
    }
5619
228
    if (MCInst_getNumOperands(MI) == 4 &&
5620
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5621
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5622
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5623
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5624
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5625
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5626
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5627
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5628
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5629
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5630
0
      break;
5631
0
    }
5632
228
    if (MCInst_getNumOperands(MI) == 4 &&
5633
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5634
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5635
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5636
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5637
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5638
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5639
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5640
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5641
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5642
0
      AsmString = "movle $\x02, $\x03, $\x01";
5643
0
      break;
5644
0
    }
5645
228
    if (MCInst_getNumOperands(MI) == 4 &&
5646
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5647
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5648
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5649
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5650
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5651
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5652
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5653
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5654
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5655
0
      AsmString = "movule $\x02, $\x03, $\x01";
5656
0
      break;
5657
0
    }
5658
228
    if (MCInst_getNumOperands(MI) == 4 &&
5659
228
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5660
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5661
228
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5662
228
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5663
228
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5664
228
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5665
228
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5666
228
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5667
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5668
0
      AsmString = "movo $\x02, $\x03, $\x01";
5669
0
      break;
5670
0
    }
5671
228
    return NULL;
5672
68.4k
  }
5673
5674
24.5k
  tmp = cs_strdup(AsmString);
5675
24.5k
  AsmMnem = tmp;
5676
162k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5677
162k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
5678
24.5k
      *AsmOps = '\0';
5679
24.5k
      AsmOps++;
5680
24.5k
      break;
5681
24.5k
    }
5682
162k
  }
5683
24.5k
  SStream_concat0(OS, AsmMnem);
5684
24.5k
  if (*AsmOps) {
5685
24.5k
    SStream_concat0(OS, "\t");
5686
24.5k
    if (strstr(AsmOps, "icc"))
5687
4.15k
      Sparc_addReg(MI, SPARC_REG_ICC);
5688
24.5k
    if (strstr(AsmOps, "xcc"))
5689
7.16k
      Sparc_addReg(MI, SPARC_REG_XCC);
5690
146k
    for (c = AsmOps; *c; c++) {
5691
122k
      if (*c == '$') {
5692
33.5k
        c += 1;
5693
33.5k
        if (*c == (char)0xff) {
5694
0
          c += 1;
5695
0
          OpIdx = *c - 1;
5696
0
          c += 1;
5697
0
          PrintMethodIdx = *c - 1;
5698
0
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5699
0
        } else
5700
33.5k
          printOperand(MI, *c - 1, OS);
5701
88.4k
      } else {
5702
88.4k
        SStream_concat(OS, "%c", *c);
5703
88.4k
      }
5704
122k
    }
5705
24.5k
  }
5706
24.5k
  return tmp;
5707
68.4k
}
5708
5709
#endif // PRINT_ALIAS_INSTR