/src/capstonenext/arch/HPPA/HPPAInstPrinter.c
Line | Count | Source (jump to first uncovered line) |
1 | | /* Capstone Disassembly Engine */ |
2 | | /* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */ |
3 | | |
4 | | #ifdef CAPSTONE_HAS_HPPA |
5 | | |
6 | | #include <capstone/platform.h> |
7 | | #include "../../Mapping.h" |
8 | | #include "../../utils.h" |
9 | | |
10 | | #include "HPPAInstPrinter.h" |
11 | | #include "HPPAMapping.h" |
12 | | |
13 | | static const struct pa_insn pa_insns[] = { |
14 | | { HPPA_INS_LDI, HPPA_GRP_LONG_IMM }, |
15 | | { HPPA_INS_CMPIB, HPPA_GRP_BRANCH }, |
16 | | { HPPA_INS_COMIB, HPPA_GRP_BRANCH }, |
17 | | { HPPA_INS_CMPB, HPPA_GRP_BRANCH }, |
18 | | { HPPA_INS_COMB, HPPA_GRP_BRANCH }, |
19 | | { HPPA_INS_ADDB, HPPA_GRP_BRANCH }, |
20 | | { HPPA_INS_ADDIB, HPPA_GRP_BRANCH }, |
21 | | { HPPA_INS_NOP, HPPA_GRP_COMPUTATION }, |
22 | | { HPPA_INS_COPY, HPPA_GRP_COMPUTATION }, |
23 | | { HPPA_INS_MTSAR, HPPA_GRP_SYSCTRL }, |
24 | | { HPPA_INS_LDD, HPPA_GRP_MEM_REF }, |
25 | | { HPPA_INS_LDW, HPPA_GRP_MEM_REF }, |
26 | | { HPPA_INS_LDH, HPPA_GRP_MEM_REF }, |
27 | | { HPPA_INS_LDB, HPPA_GRP_MEM_REF }, |
28 | | { HPPA_INS_STD, HPPA_GRP_MEM_REF }, |
29 | | { HPPA_INS_STW, HPPA_GRP_MEM_REF }, |
30 | | { HPPA_INS_STH, HPPA_GRP_MEM_REF }, |
31 | | { HPPA_INS_STB, HPPA_GRP_MEM_REF }, |
32 | | { HPPA_INS_LDWM, HPPA_GRP_MEM_REF }, |
33 | | { HPPA_INS_STWM, HPPA_GRP_MEM_REF }, |
34 | | { HPPA_INS_LDWX, HPPA_GRP_MEM_REF }, |
35 | | { HPPA_INS_LDHX, HPPA_GRP_MEM_REF }, |
36 | | { HPPA_INS_LDBX, HPPA_GRP_MEM_REF }, |
37 | | { HPPA_INS_LDWA, HPPA_GRP_MEM_REF }, |
38 | | { HPPA_INS_LDCW, HPPA_GRP_MEM_REF }, |
39 | | { HPPA_INS_STWA, HPPA_GRP_MEM_REF }, |
40 | | { HPPA_INS_STBY, HPPA_GRP_MEM_REF }, |
41 | | { HPPA_INS_LDDA, HPPA_GRP_MEM_REF }, |
42 | | { HPPA_INS_LDCD, HPPA_GRP_MEM_REF }, |
43 | | { HPPA_INS_STDA, HPPA_GRP_MEM_REF }, |
44 | | { HPPA_INS_LDWAX, HPPA_GRP_MEM_REF }, |
45 | | { HPPA_INS_LDCWX, HPPA_GRP_MEM_REF }, |
46 | | { HPPA_INS_LDWS, HPPA_GRP_MEM_REF }, |
47 | | { HPPA_INS_LDHS, HPPA_GRP_MEM_REF }, |
48 | | { HPPA_INS_LDBS, HPPA_GRP_MEM_REF }, |
49 | | { HPPA_INS_LDWAS, HPPA_GRP_MEM_REF }, |
50 | | { HPPA_INS_LDCWS, HPPA_GRP_MEM_REF }, |
51 | | { HPPA_INS_STWS, HPPA_GRP_MEM_REF }, |
52 | | { HPPA_INS_STHS, HPPA_GRP_MEM_REF }, |
53 | | { HPPA_INS_STBS, HPPA_GRP_MEM_REF }, |
54 | | { HPPA_INS_STWAS, HPPA_GRP_MEM_REF }, |
55 | | { HPPA_INS_STDBY, HPPA_GRP_MEM_REF }, |
56 | | { HPPA_INS_STBYS, HPPA_GRP_MEM_REF }, |
57 | | { HPPA_INS_LDO, HPPA_GRP_LONG_IMM }, |
58 | | { HPPA_INS_LDIL, HPPA_GRP_LONG_IMM }, |
59 | | { HPPA_INS_ADDIL, HPPA_GRP_LONG_IMM }, |
60 | | { HPPA_INS_B, HPPA_GRP_BRANCH }, |
61 | | { HPPA_INS_BL, HPPA_GRP_BRANCH }, |
62 | | { HPPA_INS_GATE, HPPA_GRP_BRANCH }, |
63 | | { HPPA_INS_BLR, HPPA_GRP_BRANCH }, |
64 | | { HPPA_INS_BV, HPPA_GRP_BRANCH }, |
65 | | { HPPA_INS_BVE, HPPA_GRP_BRANCH }, |
66 | | { HPPA_INS_BE, HPPA_GRP_BRANCH }, |
67 | | { HPPA_INS_BLE, HPPA_GRP_BRANCH }, |
68 | | { HPPA_INS_MOVB, HPPA_GRP_BRANCH }, |
69 | | { HPPA_INS_MOVIB, HPPA_GRP_BRANCH }, |
70 | | { HPPA_INS_COMBT, HPPA_GRP_BRANCH }, |
71 | | { HPPA_INS_COMBF, HPPA_GRP_BRANCH }, |
72 | | { HPPA_INS_COMIBT, HPPA_GRP_BRANCH }, |
73 | | { HPPA_INS_COMIBF, HPPA_GRP_BRANCH }, |
74 | | { HPPA_INS_ADDBT, HPPA_GRP_BRANCH }, |
75 | | { HPPA_INS_ADDBF, HPPA_GRP_BRANCH }, |
76 | | { HPPA_INS_ADDIBT, HPPA_GRP_BRANCH }, |
77 | | { HPPA_INS_ADDIBF, HPPA_GRP_BRANCH }, |
78 | | { HPPA_INS_BB, HPPA_GRP_BRANCH }, |
79 | | { HPPA_INS_BVB, HPPA_GRP_BRANCH }, |
80 | | { HPPA_INS_CLRBTS, HPPA_GRP_BRANCH }, |
81 | | { HPPA_INS_POPBTS, HPPA_GRP_BRANCH }, |
82 | | { HPPA_INS_PUSHNOM, HPPA_GRP_BRANCH }, |
83 | | { HPPA_INS_PUSHBTS, HPPA_GRP_BRANCH }, |
84 | | { HPPA_INS_CMPCLR, HPPA_GRP_COMPUTATION }, |
85 | | { HPPA_INS_COMCLR, HPPA_GRP_COMPUTATION }, |
86 | | { HPPA_INS_OR, HPPA_GRP_COMPUTATION }, |
87 | | { HPPA_INS_XOR, HPPA_GRP_COMPUTATION }, |
88 | | { HPPA_INS_AND, HPPA_GRP_COMPUTATION }, |
89 | | { HPPA_INS_ANDCM, HPPA_GRP_COMPUTATION }, |
90 | | { HPPA_INS_UXOR, HPPA_GRP_COMPUTATION }, |
91 | | { HPPA_INS_UADDCM, HPPA_GRP_COMPUTATION }, |
92 | | { HPPA_INS_UADDCMT, HPPA_GRP_COMPUTATION }, |
93 | | { HPPA_INS_DCOR, HPPA_GRP_COMPUTATION }, |
94 | | { HPPA_INS_IDCOR, HPPA_GRP_COMPUTATION }, |
95 | | { HPPA_INS_ADDI, HPPA_GRP_COMPUTATION }, |
96 | | { HPPA_INS_ADDIO, HPPA_GRP_COMPUTATION }, |
97 | | { HPPA_INS_ADDIT, HPPA_GRP_COMPUTATION }, |
98 | | { HPPA_INS_ADDITO, HPPA_GRP_COMPUTATION }, |
99 | | { HPPA_INS_ADD, HPPA_GRP_COMPUTATION }, |
100 | | { HPPA_INS_ADDL, HPPA_GRP_COMPUTATION }, |
101 | | { HPPA_INS_ADDO, HPPA_GRP_COMPUTATION }, |
102 | | { HPPA_INS_ADDC, HPPA_GRP_COMPUTATION }, |
103 | | { HPPA_INS_ADDCO, HPPA_GRP_COMPUTATION }, |
104 | | { HPPA_INS_SUB, HPPA_GRP_COMPUTATION }, |
105 | | { HPPA_INS_SUBO, HPPA_GRP_COMPUTATION }, |
106 | | { HPPA_INS_SUBB, HPPA_GRP_COMPUTATION }, |
107 | | { HPPA_INS_SUBBO, HPPA_GRP_COMPUTATION }, |
108 | | { HPPA_INS_SUBT, HPPA_GRP_COMPUTATION }, |
109 | | { HPPA_INS_SUBTO, HPPA_GRP_COMPUTATION }, |
110 | | { HPPA_INS_DS, HPPA_GRP_COMPUTATION }, |
111 | | { HPPA_INS_SUBI, HPPA_GRP_COMPUTATION }, |
112 | | { HPPA_INS_SUBIO, HPPA_GRP_COMPUTATION }, |
113 | | { HPPA_INS_CMPICLR, HPPA_GRP_COMPUTATION }, |
114 | | { HPPA_INS_COMICLR, HPPA_GRP_COMPUTATION }, |
115 | | { HPPA_INS_SHLADD, HPPA_GRP_COMPUTATION }, |
116 | | { HPPA_INS_SH1ADD, HPPA_GRP_COMPUTATION }, |
117 | | { HPPA_INS_SH1ADDL, HPPA_GRP_COMPUTATION }, |
118 | | { HPPA_INS_SH1ADDO, HPPA_GRP_COMPUTATION }, |
119 | | { HPPA_INS_SH2ADD, HPPA_GRP_COMPUTATION }, |
120 | | { HPPA_INS_SH2ADDL, HPPA_GRP_COMPUTATION }, |
121 | | { HPPA_INS_SH2ADDO, HPPA_GRP_COMPUTATION }, |
122 | | { HPPA_INS_SH3ADD, HPPA_GRP_COMPUTATION }, |
123 | | { HPPA_INS_SH3ADDL, HPPA_GRP_COMPUTATION }, |
124 | | { HPPA_INS_SH3ADDO, HPPA_GRP_COMPUTATION }, |
125 | | { HPPA_INS_HADD, HPPA_GRP_MULTIMEDIA }, |
126 | | { HPPA_INS_HAVG, HPPA_GRP_MULTIMEDIA }, |
127 | | { HPPA_INS_HSHL, HPPA_GRP_MULTIMEDIA }, |
128 | | { HPPA_INS_HSHLADD, HPPA_GRP_MULTIMEDIA }, |
129 | | { HPPA_INS_HSHR, HPPA_GRP_MULTIMEDIA }, |
130 | | { HPPA_INS_HSHRADD, HPPA_GRP_MULTIMEDIA }, |
131 | | { HPPA_INS_HSUB, HPPA_GRP_MULTIMEDIA }, |
132 | | { HPPA_INS_MIXH, HPPA_GRP_MULTIMEDIA }, |
133 | | { HPPA_INS_MIXW, HPPA_GRP_MULTIMEDIA }, |
134 | | { HPPA_INS_PERMH, HPPA_GRP_MULTIMEDIA }, |
135 | | { HPPA_INS_SHRPD, HPPA_GRP_COMPUTATION }, |
136 | | { HPPA_INS_SHRPW, HPPA_GRP_COMPUTATION }, |
137 | | { HPPA_INS_VSHD, HPPA_GRP_COMPUTATION }, |
138 | | { HPPA_INS_SHD, HPPA_GRP_COMPUTATION }, |
139 | | { HPPA_INS_EXTRD, HPPA_GRP_COMPUTATION }, |
140 | | { HPPA_INS_EXTRW, HPPA_GRP_COMPUTATION }, |
141 | | { HPPA_INS_VEXTRU, HPPA_GRP_COMPUTATION }, |
142 | | { HPPA_INS_VEXTRS, HPPA_GRP_COMPUTATION }, |
143 | | { HPPA_INS_EXTRU, HPPA_GRP_COMPUTATION }, |
144 | | { HPPA_INS_EXTRS, HPPA_GRP_COMPUTATION }, |
145 | | { HPPA_INS_DEPD, HPPA_GRP_COMPUTATION }, |
146 | | { HPPA_INS_DEPDI, HPPA_GRP_COMPUTATION }, |
147 | | { HPPA_INS_DEPW, HPPA_GRP_COMPUTATION }, |
148 | | { HPPA_INS_DEPWI, HPPA_GRP_COMPUTATION }, |
149 | | { HPPA_INS_ZVDEP, HPPA_GRP_COMPUTATION }, |
150 | | { HPPA_INS_VDEP, HPPA_GRP_COMPUTATION }, |
151 | | { HPPA_INS_ZDEP, HPPA_GRP_COMPUTATION }, |
152 | | { HPPA_INS_DEP, HPPA_GRP_COMPUTATION }, |
153 | | { HPPA_INS_ZVDEPI, HPPA_GRP_COMPUTATION }, |
154 | | { HPPA_INS_VDEPI, HPPA_GRP_COMPUTATION }, |
155 | | { HPPA_INS_ZDEPI, HPPA_GRP_COMPUTATION }, |
156 | | { HPPA_INS_DEPI, HPPA_GRP_COMPUTATION }, |
157 | | { HPPA_INS_BREAK, HPPA_GRP_SYSCTRL }, |
158 | | { HPPA_INS_RFI, HPPA_GRP_SYSCTRL }, |
159 | | { HPPA_INS_RFIR, HPPA_GRP_SYSCTRL }, |
160 | | { HPPA_INS_SSM, HPPA_GRP_SYSCTRL }, |
161 | | { HPPA_INS_RSM, HPPA_GRP_SYSCTRL }, |
162 | | { HPPA_INS_MTSM, HPPA_GRP_SYSCTRL }, |
163 | | { HPPA_INS_LDSID, HPPA_GRP_SYSCTRL }, |
164 | | { HPPA_INS_MTSP, HPPA_GRP_SYSCTRL }, |
165 | | { HPPA_INS_MTCTL, HPPA_GRP_SYSCTRL }, |
166 | | { HPPA_INS_MTSARCM, HPPA_GRP_SYSCTRL }, |
167 | | { HPPA_INS_MFIA, HPPA_GRP_SYSCTRL }, |
168 | | { HPPA_INS_MFSP, HPPA_GRP_SYSCTRL }, |
169 | | { HPPA_INS_MFCTL, HPPA_GRP_SYSCTRL }, |
170 | | { HPPA_INS_SYNC, HPPA_GRP_SYSCTRL }, |
171 | | { HPPA_INS_SYNCDMA, HPPA_GRP_SYSCTRL }, |
172 | | { HPPA_INS_PROBE, HPPA_GRP_SYSCTRL }, |
173 | | { HPPA_INS_PROBEI, HPPA_GRP_SYSCTRL }, |
174 | | { HPPA_INS_PROBER, HPPA_GRP_SYSCTRL }, |
175 | | { HPPA_INS_PROBERI, HPPA_GRP_SYSCTRL }, |
176 | | { HPPA_INS_PROBEW, HPPA_GRP_SYSCTRL }, |
177 | | { HPPA_INS_PROBEWI, HPPA_GRP_SYSCTRL }, |
178 | | { HPPA_INS_LPA, HPPA_GRP_SYSCTRL }, |
179 | | { HPPA_INS_LCI, HPPA_GRP_SYSCTRL }, |
180 | | { HPPA_INS_PDTLB, HPPA_GRP_SYSCTRL }, |
181 | | { HPPA_INS_PITLB, HPPA_GRP_SYSCTRL }, |
182 | | { HPPA_INS_PDTLBE, HPPA_GRP_SYSCTRL }, |
183 | | { HPPA_INS_PITLBE, HPPA_GRP_SYSCTRL }, |
184 | | { HPPA_INS_IDTLBA, HPPA_GRP_SYSCTRL }, |
185 | | { HPPA_INS_IITLBA, HPPA_GRP_SYSCTRL }, |
186 | | { HPPA_INS_IDTLBP, HPPA_GRP_SYSCTRL }, |
187 | | { HPPA_INS_IITLBP, HPPA_GRP_SYSCTRL }, |
188 | | { HPPA_INS_PDC, HPPA_GRP_SYSCTRL }, |
189 | | { HPPA_INS_FDC, HPPA_GRP_SYSCTRL }, |
190 | | { HPPA_INS_FIC, HPPA_GRP_SYSCTRL }, |
191 | | { HPPA_INS_FDCE, HPPA_GRP_SYSCTRL }, |
192 | | { HPPA_INS_FICE, HPPA_GRP_SYSCTRL }, |
193 | | { HPPA_INS_DIAG, HPPA_GRP_SYSCTRL }, |
194 | | { HPPA_INS_IDTLBT, HPPA_GRP_SYSCTRL }, |
195 | | { HPPA_INS_IITLBT, HPPA_GRP_SYSCTRL }, |
196 | | { HPPA_INS_MTCPU, HPPA_GRP_SYSCTRL }, |
197 | | { HPPA_INS_MFCPU, HPPA_GRP_SYSCTRL }, |
198 | | { HPPA_INS_TOCEN, HPPA_GRP_SYSCTRL }, |
199 | | { HPPA_INS_TOCDIS, HPPA_GRP_SYSCTRL }, |
200 | | { HPPA_INS_SHDWGR, HPPA_GRP_SYSCTRL }, |
201 | | { HPPA_INS_GRSHDW, HPPA_GRP_SYSCTRL }, |
202 | | { HPPA_INS_GFW, HPPA_GRP_SYSCTRL }, |
203 | | { HPPA_INS_GFR, HPPA_GRP_SYSCTRL }, |
204 | | { HPPA_INS_FLDW, HPPA_GRP_FLOAT }, |
205 | | { HPPA_INS_FLDD, HPPA_GRP_FLOAT }, |
206 | | { HPPA_INS_FSTW, HPPA_GRP_FLOAT }, |
207 | | { HPPA_INS_FSTD, HPPA_GRP_FLOAT }, |
208 | | { HPPA_INS_FLDWX, HPPA_GRP_FLOAT }, |
209 | | { HPPA_INS_FLDDX, HPPA_GRP_FLOAT }, |
210 | | { HPPA_INS_FSTWX, HPPA_GRP_FLOAT }, |
211 | | { HPPA_INS_FSTDX, HPPA_GRP_FLOAT }, |
212 | | { HPPA_INS_FSTQX, HPPA_GRP_FLOAT }, |
213 | | { HPPA_INS_FLDWS, HPPA_GRP_FLOAT }, |
214 | | { HPPA_INS_FLDDS, HPPA_GRP_FLOAT }, |
215 | | { HPPA_INS_FSTWS, HPPA_GRP_FLOAT }, |
216 | | { HPPA_INS_FSTDS, HPPA_GRP_FLOAT }, |
217 | | { HPPA_INS_FSTQS, HPPA_GRP_FLOAT }, |
218 | | { HPPA_INS_FADD, HPPA_GRP_FLOAT }, |
219 | | { HPPA_INS_FSUB, HPPA_GRP_FLOAT }, |
220 | | { HPPA_INS_FMPY, HPPA_GRP_FLOAT }, |
221 | | { HPPA_INS_FDIV, HPPA_GRP_FLOAT }, |
222 | | { HPPA_INS_FSQRT, HPPA_GRP_FLOAT }, |
223 | | { HPPA_INS_FABS, HPPA_GRP_FLOAT }, |
224 | | { HPPA_INS_FREM, HPPA_GRP_FLOAT }, |
225 | | { HPPA_INS_FRND, HPPA_GRP_FLOAT }, |
226 | | { HPPA_INS_FCPY, HPPA_GRP_FLOAT }, |
227 | | { HPPA_INS_FCNVFF, HPPA_GRP_FLOAT }, |
228 | | { HPPA_INS_FCNVXF, HPPA_GRP_FLOAT }, |
229 | | { HPPA_INS_FCNVFX, HPPA_GRP_FLOAT }, |
230 | | { HPPA_INS_FCNVFXT, HPPA_GRP_FLOAT }, |
231 | | { HPPA_INS_FMPYFADD, HPPA_GRP_FLOAT }, |
232 | | { HPPA_INS_FMPYNFADD, HPPA_GRP_FLOAT }, |
233 | | { HPPA_INS_FNEG, HPPA_GRP_FLOAT }, |
234 | | { HPPA_INS_FNEGABS, HPPA_GRP_FLOAT }, |
235 | | { HPPA_INS_FCNV, HPPA_GRP_FLOAT }, |
236 | | { HPPA_INS_FCMP, HPPA_GRP_FLOAT }, |
237 | | { HPPA_INS_XMPYU, HPPA_GRP_FLOAT }, |
238 | | { HPPA_INS_FMPYADD, HPPA_GRP_FLOAT }, |
239 | | { HPPA_INS_FMPYSUB, HPPA_GRP_FLOAT }, |
240 | | { HPPA_INS_FTEST, HPPA_GRP_FLOAT }, |
241 | | { HPPA_INS_FID, HPPA_GRP_FLOAT }, |
242 | | { HPPA_INS_PMDIS, HPPA_GRP_PERFMON }, |
243 | | { HPPA_INS_PMENB, HPPA_GRP_PERFMON }, |
244 | | { HPPA_INS_SPOP0, HPPA_GRP_ASSIST }, |
245 | | { HPPA_INS_SPOP1, HPPA_GRP_ASSIST }, |
246 | | { HPPA_INS_SPOP2, HPPA_GRP_ASSIST }, |
247 | | { HPPA_INS_SPOP3, HPPA_GRP_ASSIST }, |
248 | | { HPPA_INS_COPR, HPPA_GRP_ASSIST }, |
249 | | { HPPA_INS_CLDW, HPPA_GRP_ASSIST }, |
250 | | { HPPA_INS_CLDD, HPPA_GRP_ASSIST }, |
251 | | { HPPA_INS_CSTW, HPPA_GRP_ASSIST }, |
252 | | { HPPA_INS_CSTD, HPPA_GRP_ASSIST }, |
253 | | { HPPA_INS_CLDWX, HPPA_GRP_ASSIST }, |
254 | | { HPPA_INS_CLDDX, HPPA_GRP_ASSIST }, |
255 | | { HPPA_INS_CSTWX, HPPA_GRP_ASSIST }, |
256 | | { HPPA_INS_CSTDX, HPPA_GRP_ASSIST }, |
257 | | { HPPA_INS_CLDWS, HPPA_GRP_ASSIST }, |
258 | | { HPPA_INS_CLDDS, HPPA_GRP_ASSIST }, |
259 | | { HPPA_INS_CSTWS, HPPA_GRP_ASSIST }, |
260 | | { HPPA_INS_CSTDS, HPPA_GRP_ASSIST }, |
261 | | { HPPA_INS_CALL, HPPA_GRP_INVALID }, |
262 | | { HPPA_INS_RET, HPPA_GRP_INVALID }, |
263 | | }; |
264 | | |
265 | | static void set_op_imm(cs_hppa *hppa, uint64_t val) |
266 | 0 | { |
267 | 0 | cs_hppa_op *op = &hppa->operands[hppa->op_count++]; |
268 | 0 | op->type = HPPA_OP_IMM; |
269 | 0 | op->imm = val; |
270 | 0 | } |
271 | | |
272 | | static void set_op_reg(cs_hppa *hppa, uint64_t val, cs_ac_type access) |
273 | 0 | { |
274 | 0 | cs_hppa_op *op = &hppa->operands[hppa->op_count++]; |
275 | 0 | op->type = HPPA_OP_REG; |
276 | 0 | op->reg = val; |
277 | 0 | op->access = access; |
278 | 0 | } |
279 | | |
280 | | static void set_op_idx_reg(cs_hppa *hppa, uint64_t reg) |
281 | 0 | { |
282 | 0 | cs_hppa_op *op = &hppa->operands[hppa->op_count++]; |
283 | 0 | op->type = HPPA_OP_IDX_REG; |
284 | 0 | op->reg = reg; |
285 | 0 | op->access = CS_AC_READ; |
286 | 0 | } |
287 | | |
288 | | static void set_op_disp(cs_hppa *hppa, uint64_t val) |
289 | 0 | { |
290 | 0 | cs_hppa_op *op = &hppa->operands[hppa->op_count++]; |
291 | 0 | op->type = HPPA_OP_DISP; |
292 | 0 | op->imm = val; |
293 | 0 | } |
294 | | |
295 | | static void set_op_target(cs_hppa *hppa, uint64_t val) |
296 | 0 | { |
297 | 0 | cs_hppa_op *op = &hppa->operands[hppa->op_count++]; |
298 | 0 | op->type = HPPA_OP_TARGET; |
299 | 0 | op->imm = val; |
300 | 0 | } |
301 | | |
302 | | static void set_op_mem(cs_hppa *hppa, uint32_t base, uint32_t space, |
303 | | cs_ac_type base_access) |
304 | 0 | { |
305 | 0 | cs_hppa_op *op = &hppa->operands[hppa->op_count++]; |
306 | 0 | op->type = HPPA_OP_MEM; |
307 | 0 | op->mem.base = base; |
308 | 0 | op->mem.space = space; |
309 | 0 | op->mem.base_access = base_access; |
310 | 0 | } |
311 | | /* HPPA instruction formats (access) |
312 | | i - imm arguments |
313 | | R - read access register |
314 | | W - write access register |
315 | | w - read + write access register |
316 | | r - index register (read only) |
317 | | T - offset (pc relative) |
318 | | o - displacement (imm) |
319 | | x - [r] or [o] defined by the operand kind |
320 | | b - base register (may be writable in some cases) |
321 | | */ |
322 | | static const struct pa_insn_fmt pa_formats[] = { |
323 | | { HPPA_INS_LDI, "iW", false }, |
324 | | |
325 | | { HPPA_INS_CMPIB, "iRT", false }, |
326 | | { HPPA_INS_COMIB, "iRT", false }, |
327 | | |
328 | | { HPPA_INS_CMPB, "RRT", false }, |
329 | | { HPPA_INS_COMB, "RRT", false }, |
330 | | |
331 | | { HPPA_INS_ADDB, "RwT", false }, |
332 | | |
333 | | { HPPA_INS_ADDIB, "iwT", false }, |
334 | | |
335 | | { HPPA_INS_NOP, "", false }, |
336 | | { HPPA_INS_COPY, "RW", false }, |
337 | | { HPPA_INS_MTSAR, "R", false }, |
338 | | |
339 | | { HPPA_INS_LDD, "x(Rb)W", false }, |
340 | | { HPPA_INS_LDW, "x(Rb)W", false }, |
341 | | { HPPA_INS_LDH, "x(Rb)W", false }, |
342 | | { HPPA_INS_LDB, "x(Rb)W", false }, |
343 | | { HPPA_INS_STD, "Ro(Rb)", false }, |
344 | | { HPPA_INS_STW, "Ro(Rb)", false }, |
345 | | { HPPA_INS_STH, "Ro(Rb)", false }, |
346 | | { HPPA_INS_STB, "Ro(Rb)", false }, |
347 | | { HPPA_INS_LDWM, "o(Rw)W", false }, |
348 | | { HPPA_INS_STWM, "Ro(Rw)", false }, |
349 | | { HPPA_INS_LDWX, "r(Rb)W", false }, |
350 | | { HPPA_INS_LDHX, "r(Rb)W", false }, |
351 | | { HPPA_INS_LDBX, "r(Rb)W", false }, |
352 | | { HPPA_INS_LDWA, "x(R)W", false }, |
353 | | { HPPA_INS_LDCW, "x(Rb)W", false }, |
354 | | { HPPA_INS_STWA, "Ro(b)", false }, |
355 | | { HPPA_INS_STBY, "Ro(Rb)", false }, |
356 | | { HPPA_INS_LDDA, "x(b)W", false }, |
357 | | { HPPA_INS_LDCD, "x(Rb)W", false }, |
358 | | { HPPA_INS_STDA, "Ro(b)", false }, |
359 | | { HPPA_INS_LDWAX, "r(b)W", false }, |
360 | | { HPPA_INS_LDCWX, "r(Rb)W", false }, |
361 | | { HPPA_INS_LDWS, "o(Rb)W", false }, |
362 | | { HPPA_INS_LDHS, "o(Rb)W", false }, |
363 | | { HPPA_INS_LDBS, "o(Rb)W", false }, |
364 | | { HPPA_INS_LDWAS, "o(b)W", false }, |
365 | | { HPPA_INS_LDCWS, "o(Rb)W", false }, |
366 | | { HPPA_INS_STWS, "Ro(Rb)", false }, |
367 | | { HPPA_INS_STHS, "Ro(Rb)", false }, |
368 | | { HPPA_INS_STBS, "Ro(Rb)", false }, |
369 | | { HPPA_INS_STWAS, "Ro(b)", false }, |
370 | | { HPPA_INS_STDBY, "Ro(Rb)", false }, |
371 | | { HPPA_INS_STBYS, "Ro(Rb)", false }, |
372 | | |
373 | | { HPPA_INS_LDO, "o(R)W", false }, |
374 | | { HPPA_INS_LDIL, "iW", false }, |
375 | | { HPPA_INS_ADDIL, "iR", false }, |
376 | | |
377 | | { HPPA_INS_B, "TW", false }, |
378 | | { HPPA_INS_BL, "TW", false }, |
379 | | { HPPA_INS_GATE, "TW", false }, |
380 | | { HPPA_INS_BLR, "RW", false }, |
381 | | { HPPA_INS_BV, "x(R)", false }, |
382 | | { HPPA_INS_BVE, "(b)", false }, |
383 | | { HPPA_INS_BVE, "(b)W", true }, |
384 | | { HPPA_INS_BE, "o(RR)", false }, |
385 | | { HPPA_INS_BE, "o(RR)WW", true }, |
386 | | { HPPA_INS_BLE, "o(RR)", false }, |
387 | | { HPPA_INS_MOVB, "RWT", false }, |
388 | | { HPPA_INS_MOVIB, "iWT", false }, |
389 | | { HPPA_INS_COMBT, "RRT", false }, |
390 | | { HPPA_INS_COMBF, "RRT", false }, |
391 | | { HPPA_INS_COMIBT, "iRT", false }, |
392 | | { HPPA_INS_COMIBF, "iRT", false }, |
393 | | { HPPA_INS_ADDBT, "RwT", false }, |
394 | | { HPPA_INS_ADDBF, "RwT", false }, |
395 | | { HPPA_INS_ADDIBT, "iwT", false }, |
396 | | { HPPA_INS_ADDIBF, "iwT", false }, |
397 | | { HPPA_INS_BB, "RiT", false }, |
398 | | { HPPA_INS_BVB, "RT", false }, |
399 | | { HPPA_INS_CLRBTS, "", false }, |
400 | | { HPPA_INS_POPBTS, "i", false }, |
401 | | { HPPA_INS_PUSHNOM, "", false }, |
402 | | { HPPA_INS_PUSHBTS, "R", false }, |
403 | | |
404 | | { HPPA_INS_CMPCLR, "RRW", false }, |
405 | | { HPPA_INS_COMCLR, "RRW", false }, |
406 | | { HPPA_INS_OR, "RRW", false }, |
407 | | { HPPA_INS_XOR, "RRW", false }, |
408 | | { HPPA_INS_AND, "RRW", false }, |
409 | | { HPPA_INS_ANDCM, "RRW", false }, |
410 | | { HPPA_INS_UXOR, "RRW", false }, |
411 | | { HPPA_INS_UADDCM, "RRW", false }, |
412 | | { HPPA_INS_UADDCMT, "RRW", false }, |
413 | | { HPPA_INS_DCOR, "RW", false }, |
414 | | { HPPA_INS_IDCOR, "RW", false }, |
415 | | { HPPA_INS_ADDI, "iRW", false }, |
416 | | { HPPA_INS_ADDIO, "iRW", false }, |
417 | | { HPPA_INS_ADDIT, "iRW", false }, |
418 | | { HPPA_INS_ADDITO, "iRW", false }, |
419 | | { HPPA_INS_ADD, "RRW", false }, |
420 | | { HPPA_INS_ADDL, "RRW", false }, |
421 | | { HPPA_INS_ADDO, "RRW", false }, |
422 | | { HPPA_INS_ADDC, "RRW", false }, |
423 | | { HPPA_INS_ADDCO, "RRW", false }, |
424 | | { HPPA_INS_SUB, "RRW", false }, |
425 | | { HPPA_INS_SUBO, "RRW", false }, |
426 | | { HPPA_INS_SUBB, "RRW", false }, |
427 | | { HPPA_INS_SUBBO, "RRW", false }, |
428 | | { HPPA_INS_SUBT, "RRW", false }, |
429 | | { HPPA_INS_SUBTO, "RRW", false }, |
430 | | { HPPA_INS_DS, "RRW", false }, |
431 | | { HPPA_INS_SUBI, "iRW", false }, |
432 | | { HPPA_INS_SUBIO, "iRW", false }, |
433 | | { HPPA_INS_CMPICLR, "iRW", false }, |
434 | | { HPPA_INS_COMICLR, "iRW", false }, |
435 | | { HPPA_INS_SHLADD, "RiRW", false }, |
436 | | { HPPA_INS_SH1ADD, "RRW", false }, |
437 | | { HPPA_INS_SH1ADDL, "RRW", false }, |
438 | | { HPPA_INS_SH1ADDO, "RRW", false }, |
439 | | { HPPA_INS_SH2ADD, "RRW", false }, |
440 | | { HPPA_INS_SH2ADDL, "RRW", false }, |
441 | | { HPPA_INS_SH2ADDO, "RRW", false }, |
442 | | { HPPA_INS_SH3ADD, "RRW", false }, |
443 | | { HPPA_INS_SH3ADDL, "RRW", false }, |
444 | | { HPPA_INS_SH3ADDO, "RRW", false }, |
445 | | |
446 | | { HPPA_INS_HADD, "RRW", false }, |
447 | | { HPPA_INS_HAVG, "RRW", false }, |
448 | | { HPPA_INS_HSHL, "RiW", false }, |
449 | | { HPPA_INS_HSHLADD, "RiRW", false }, |
450 | | { HPPA_INS_HSHR, "RiW", false }, |
451 | | { HPPA_INS_HSHRADD, "RiRW", false }, |
452 | | { HPPA_INS_HSUB, "RRW", false }, |
453 | | { HPPA_INS_MIXH, "RRW", false }, |
454 | | { HPPA_INS_MIXW, "RRW", false }, |
455 | | { HPPA_INS_PERMH, "RW", false }, |
456 | | |
457 | | { HPPA_INS_SHRPD, "RRiW", false }, |
458 | | { HPPA_INS_SHRPD, "RRRW", true }, |
459 | | { HPPA_INS_SHRPW, "RRiW", false }, |
460 | | { HPPA_INS_SHRPW, "RRRW", true }, |
461 | | { HPPA_INS_VSHD, "RRW", false }, |
462 | | { HPPA_INS_SHD, "RRiW", false }, |
463 | | { HPPA_INS_EXTRD, "RiiW", false }, |
464 | | { HPPA_INS_EXTRD, "RRiW", true }, |
465 | | { HPPA_INS_EXTRW, "RiiW", false }, |
466 | | { HPPA_INS_EXTRW, "RRiW", true }, |
467 | | { HPPA_INS_VEXTRU, "RiW", false }, |
468 | | { HPPA_INS_VEXTRS, "RiW", false }, |
469 | | { HPPA_INS_EXTRU, "RiiW", false }, |
470 | | { HPPA_INS_EXTRS, "RiiW", false }, |
471 | | { HPPA_INS_DEPD, "RiiW", false }, |
472 | | { HPPA_INS_DEPDI, "iiiW", false }, |
473 | | { HPPA_INS_DEPW, "RiiW", false }, |
474 | | { HPPA_INS_DEPW, "RRiW", true }, |
475 | | { HPPA_INS_DEPWI, "iiiW", false }, |
476 | | { HPPA_INS_DEPWI, "iRiW", true }, |
477 | | { HPPA_INS_ZVDEP, "RiW", false }, |
478 | | { HPPA_INS_VDEP, "RiW", false }, |
479 | | { HPPA_INS_ZDEP, "RiiW", false }, |
480 | | { HPPA_INS_DEP, "RiiW", false }, |
481 | | { HPPA_INS_ZVDEPI, "iiW", false }, |
482 | | { HPPA_INS_VDEPI, "iiW", false }, |
483 | | { HPPA_INS_ZDEPI, "iiiW", false }, |
484 | | { HPPA_INS_DEPI, "iiiW", false }, |
485 | | |
486 | | { HPPA_INS_BREAK, "ii", false }, |
487 | | { HPPA_INS_RFI, "", false }, |
488 | | { HPPA_INS_RFIR, "", false }, |
489 | | { HPPA_INS_SSM, "iW", false }, |
490 | | { HPPA_INS_RSM, "iW", false }, |
491 | | { HPPA_INS_MTSM, "R", false }, |
492 | | { HPPA_INS_LDSID, "(RR)W", false }, |
493 | | { HPPA_INS_MTSP, "RW", false }, |
494 | | { HPPA_INS_MTCTL, "RW", false }, |
495 | | { HPPA_INS_MTSARCM, "R", false }, |
496 | | { HPPA_INS_MFIA, "W", false }, |
497 | | { HPPA_INS_MFSP, "RW", false }, |
498 | | { HPPA_INS_MFCTL, "RW", false }, |
499 | | { HPPA_INS_SYNC, "", false }, |
500 | | { HPPA_INS_SYNCDMA, "", false }, |
501 | | { HPPA_INS_PROBE, "(RR)RW", false }, |
502 | | { HPPA_INS_PROBEI, "(RR)iW", false }, |
503 | | { HPPA_INS_PROBER, "(RR)RW", false }, |
504 | | { HPPA_INS_PROBERI, "(RR)iW", false }, |
505 | | { HPPA_INS_PROBEW, "(RR)RW", false }, |
506 | | { HPPA_INS_PROBEWI, "(RR)iW", false }, |
507 | | { HPPA_INS_LPA, "r(Rb)W", false }, |
508 | | { HPPA_INS_LCI, "r(RR)W", false }, |
509 | | { HPPA_INS_PDTLB, "r(Rb)", false }, |
510 | | { HPPA_INS_PITLB, "r(Rb)", false }, |
511 | | { HPPA_INS_PDTLBE, "r(Rb)", false }, |
512 | | { HPPA_INS_PITLBE, "r(Rb)", false }, |
513 | | { HPPA_INS_IDTLBA, "R(RR)", false }, |
514 | | { HPPA_INS_IITLBA, "R(RR)", false }, |
515 | | { HPPA_INS_IDTLBP, "R(RR)", false }, |
516 | | { HPPA_INS_IITLBP, "R(RR)", false }, |
517 | | { HPPA_INS_PDC, "r(Rb)", false }, |
518 | | { HPPA_INS_FDC, "x(Rb)", false }, |
519 | | { HPPA_INS_FIC, "r(Rb)", false }, |
520 | | { HPPA_INS_FDCE, "r(Rb)", false }, |
521 | | { HPPA_INS_FICE, "r(Rb)", false }, |
522 | | { HPPA_INS_DIAG, "i", false }, |
523 | | { HPPA_INS_IDTLBT, "RR", false }, |
524 | | { HPPA_INS_IITLBT, "RR", false }, |
525 | | |
526 | | { HPPA_INS_FLDW, "x(Rb)W", false }, |
527 | | { HPPA_INS_FLDD, "x(Rb)W", false }, |
528 | | { HPPA_INS_FSTW, "Rx(Rb)", false }, |
529 | | { HPPA_INS_FSTD, "Rx(Rb)", false }, |
530 | | { HPPA_INS_FLDWX, "r(Rb)W", false }, |
531 | | { HPPA_INS_FLDDX, "r(Rb)W", false }, |
532 | | { HPPA_INS_FSTWX, "Rr(Rb)", false }, |
533 | | { HPPA_INS_FSTDX, "Rr(Rb)", false }, |
534 | | { HPPA_INS_FSTQX, "", false }, |
535 | | { HPPA_INS_FLDWS, "o(Rb)W", false }, |
536 | | { HPPA_INS_FLDDS, "o(Rb)W", false }, |
537 | | { HPPA_INS_FSTWS, "Ro(Rb)", false }, |
538 | | { HPPA_INS_FSTDS, "Ro(Rb)", false }, |
539 | | { HPPA_INS_FSTQS, "Ro(Rb)", false }, |
540 | | { HPPA_INS_FADD, "RRW", false }, |
541 | | { HPPA_INS_FSUB, "RRW", false }, |
542 | | { HPPA_INS_FMPY, "RRW", false }, |
543 | | { HPPA_INS_FDIV, "RRW", false }, |
544 | | { HPPA_INS_FSQRT, "RW", false }, |
545 | | { HPPA_INS_FABS, "RW", false }, |
546 | | { HPPA_INS_FREM, "", false }, |
547 | | { HPPA_INS_FRND, "RW", false }, |
548 | | { HPPA_INS_FCPY, "RW", false }, |
549 | | { HPPA_INS_FCNVFF, "RW", false }, |
550 | | { HPPA_INS_FCNVXF, "RW", false }, |
551 | | { HPPA_INS_FCNVFX, "RW", false }, |
552 | | { HPPA_INS_FCNVFXT, "RW", false }, |
553 | | { HPPA_INS_FMPYFADD, "RRRW", false }, |
554 | | { HPPA_INS_FMPYNFADD, "RRRW", false }, |
555 | | { HPPA_INS_FNEG, "RW", false }, |
556 | | { HPPA_INS_FNEGABS, "RW", false }, |
557 | | { HPPA_INS_FCNV, "RW", false }, |
558 | | { HPPA_INS_FCMP, "RR", false }, |
559 | | { HPPA_INS_FCMP, "RRi", true }, |
560 | | { HPPA_INS_XMPYU, "RRW", false }, |
561 | | { HPPA_INS_FMPYADD, "RRWRw", false }, |
562 | | { HPPA_INS_FMPYSUB, "RRWRw", false }, |
563 | | { HPPA_INS_FTEST, "", false }, |
564 | | { HPPA_INS_FTEST, "i", true }, |
565 | | { HPPA_INS_FID, "", false }, |
566 | | |
567 | | { HPPA_INS_PMDIS, "", false }, |
568 | | { HPPA_INS_PMENB, "", false }, |
569 | | |
570 | | { HPPA_INS_SPOP0, "", false }, |
571 | | { HPPA_INS_SPOP1, "W", false }, |
572 | | { HPPA_INS_SPOP2, "R", false }, |
573 | | { HPPA_INS_SPOP3, "RR", false }, |
574 | | { HPPA_INS_COPR, "", false }, |
575 | | { HPPA_INS_CLDW, "x(Rb)W", false }, |
576 | | { HPPA_INS_CLDD, "o(Rb)W", false }, |
577 | | { HPPA_INS_CSTW, "Rx(Rb)", false }, |
578 | | { HPPA_INS_CSTD, "Rx(Rb)", false }, |
579 | | { HPPA_INS_CLDWX, "r(Rb)W", false }, |
580 | | { HPPA_INS_CLDDX, "r(Rb)W", false }, |
581 | | { HPPA_INS_CSTWX, "Rr(Rb)", false }, |
582 | | { HPPA_INS_CSTDX, "Rr(Rb)", false }, |
583 | | { HPPA_INS_CLDWS, "o(Rb)W", false }, |
584 | | { HPPA_INS_CLDDS, "o(Rb)W", false }, |
585 | | { HPPA_INS_CSTWS, "Ro(Rb)", false }, |
586 | | { HPPA_INS_CSTDS, "Ro(Rb)", false }, |
587 | | |
588 | | { HPPA_INS_CALL, "", false }, |
589 | | { HPPA_INS_RET, "", false }, |
590 | | }; |
591 | | |
592 | | static void print_operand(MCInst *MI, SStream *O, const cs_hppa_op *op) |
593 | 0 | { |
594 | 0 | switch (op->type) { |
595 | 0 | case HPPA_OP_INVALID: |
596 | 0 | SStream_concat(O, "invalid"); |
597 | 0 | break; |
598 | 0 | case HPPA_OP_REG: |
599 | 0 | SStream_concat(O, HPPA_reg_name((csh)MI->csh, op->reg)); |
600 | 0 | break; |
601 | 0 | case HPPA_OP_IMM: |
602 | 0 | printInt32(O, op->imm); |
603 | 0 | break; |
604 | 0 | case HPPA_OP_DISP: |
605 | 0 | printInt32(O, op->imm); |
606 | 0 | break; |
607 | 0 | case HPPA_OP_IDX_REG: |
608 | 0 | SStream_concat(O, HPPA_reg_name((csh)MI->csh, op->reg)); |
609 | 0 | break; |
610 | 0 | case HPPA_OP_MEM: |
611 | 0 | SStream_concat(O, "("); |
612 | 0 | if (op->mem.space != HPPA_REG_INVALID && |
613 | 0 | op->mem.space != HPPA_REG_SR0) { |
614 | 0 | SStream_concat(O, HPPA_reg_name((csh)MI->csh, |
615 | 0 | op->mem.space)); |
616 | 0 | SStream_concat(O, ","); |
617 | 0 | } |
618 | 0 | SStream_concat(O, HPPA_reg_name((csh)MI->csh, op->mem.base)); |
619 | 0 | SStream_concat(O, ")"); |
620 | 0 | break; |
621 | 0 | case HPPA_OP_TARGET: |
622 | 0 | printUInt64(O, MI->address + op->imm); |
623 | 0 | break; |
624 | 0 | } |
625 | 0 | } |
626 | | |
627 | 0 | #define NUMFMTS ARR_SIZE(pa_formats) |
628 | | |
629 | | static void fill_operands(MCInst *MI, cs_hppa *hppa) |
630 | 0 | { |
631 | 0 | hppa->op_count = 0; |
632 | 0 | unsigned mc_op_count = MCInst_getNumOperands(MI); |
633 | 0 | if (mc_op_count == 0) |
634 | 0 | return; |
635 | | |
636 | 0 | hppa_ext *hppa_ext = &MI->hppa_ext; |
637 | 0 | uint32_t opcode = MCInst_getOpcode(MI); |
638 | |
|
639 | 0 | for (int i = 0; i < NUMFMTS; ++i) { |
640 | 0 | const struct pa_insn_fmt *pa_fmt = &pa_formats[i]; |
641 | 0 | if (opcode != pa_fmt->insn_id || |
642 | 0 | hppa_ext->is_alternative != pa_fmt->is_alternative) { |
643 | 0 | continue; |
644 | 0 | } |
645 | 0 | const char *fmt = pa_fmt->format; |
646 | 0 | uint8_t idx = 0; |
647 | 0 | uint32_t space_regs[2] = { HPPA_REG_INVALID, HPPA_REG_INVALID }; |
648 | 0 | uint8_t space_reg_idx = 0; |
649 | 0 | cs_ac_type base_access = CS_AC_INVALID; |
650 | 0 | MCOperand *op = NULL; |
651 | 0 | while (*fmt) { |
652 | 0 | op = MCInst_getOperand(MI, idx++); |
653 | 0 | switch (*fmt++) { |
654 | 0 | case 'i': |
655 | 0 | if (MCOperand_isReg(op)) { |
656 | 0 | set_op_reg(hppa, MCOperand_getReg(op), |
657 | 0 | CS_AC_READ); |
658 | 0 | } else { |
659 | 0 | set_op_imm(hppa, MCOperand_getImm(op)); |
660 | 0 | } |
661 | 0 | break; |
662 | 0 | case 'o': |
663 | 0 | set_op_disp(hppa, MCOperand_getImm(op)); |
664 | 0 | break; |
665 | | |
666 | 0 | case 'R': |
667 | 0 | set_op_reg(hppa, MCOperand_getReg(op), |
668 | 0 | CS_AC_READ); |
669 | 0 | break; |
670 | | |
671 | 0 | case 'W': |
672 | 0 | set_op_reg(hppa, MCOperand_getReg(op), |
673 | 0 | CS_AC_WRITE); |
674 | 0 | break; |
675 | | |
676 | 0 | case 'w': |
677 | 0 | set_op_reg(hppa, MCOperand_getReg(op), |
678 | 0 | CS_AC_READ_WRITE); |
679 | 0 | break; |
680 | | |
681 | 0 | case 'r': |
682 | 0 | set_op_idx_reg(hppa, MCOperand_getReg(op)); |
683 | 0 | break; |
684 | | |
685 | 0 | case 'T': |
686 | 0 | set_op_target(hppa, MCOperand_getImm(op) + 8); |
687 | 0 | break; |
688 | | |
689 | 0 | case 'x': |
690 | 0 | if (MCOperand_isReg(op)) { |
691 | 0 | set_op_idx_reg(hppa, |
692 | 0 | MCOperand_getReg(op)); |
693 | 0 | } else { |
694 | 0 | set_op_disp(hppa, MCOperand_getImm(op)); |
695 | 0 | } |
696 | 0 | break; |
697 | | |
698 | 0 | case '(': |
699 | 0 | while (*fmt != ')') { |
700 | 0 | if (space_reg_idx > 0) { |
701 | 0 | op = MCInst_getOperand(MI, |
702 | 0 | idx++); |
703 | 0 | } |
704 | 0 | CS_ASSERT_RET(space_reg_idx < |
705 | 0 | ARR_SIZE(space_regs)); |
706 | 0 | space_regs[space_reg_idx] = |
707 | 0 | MCOperand_getReg(op); |
708 | 0 | if (*fmt == 'R') { |
709 | 0 | base_access = CS_AC_READ; |
710 | 0 | } else if (*fmt == 'W') { |
711 | 0 | base_access = CS_AC_WRITE; |
712 | 0 | } else if (*fmt == 'b') { |
713 | 0 | base_access = CS_AC_READ; |
714 | 0 | if (hppa_ext->b_writeble) |
715 | 0 | base_access |= |
716 | 0 | CS_AC_WRITE; |
717 | 0 | } |
718 | 0 | fmt++; |
719 | 0 | space_reg_idx++; |
720 | 0 | } |
721 | |
|
722 | 0 | if (space_regs[1] == HPPA_REG_INVALID) |
723 | 0 | set_op_mem(hppa, space_regs[0], |
724 | 0 | space_regs[1], base_access); |
725 | 0 | else |
726 | 0 | set_op_mem(hppa, space_regs[1], |
727 | 0 | space_regs[0], base_access); |
728 | 0 | fmt++; |
729 | 0 | break; |
730 | | |
731 | 0 | default: |
732 | 0 | printf("Unknown: %c\n", *(fmt - 1)); |
733 | 0 | break; |
734 | 0 | } |
735 | 0 | } |
736 | 0 | break; |
737 | 0 | } |
738 | 0 | } |
739 | | |
740 | | static void print_modifiers(MCInst *MI, SStream *O) |
741 | 0 | { |
742 | 0 | hppa_ext *hppa_ext = &MI->hppa_ext; |
743 | 0 | for (uint8_t i = 0; i < hppa_ext->mod_num; ++i) { |
744 | 0 | SStream_concat(O, ","); |
745 | 0 | if (hppa_ext->modifiers[i].type == HPPA_MOD_STR) |
746 | 0 | SStream_concat(O, hppa_ext->modifiers[i].str_mod); |
747 | 0 | else |
748 | 0 | SStream_concat(O, "%d", hppa_ext->modifiers[i].int_mod); |
749 | 0 | } |
750 | 0 | } |
751 | | |
752 | | static void add_groups(MCInst *MI) |
753 | 0 | { |
754 | 0 | unsigned int opcode = MCInst_getOpcode(MI); |
755 | 0 | for (unsigned i = 0; i < ARR_SIZE(pa_insns); ++i) { |
756 | 0 | if (pa_insns[i].insn != opcode) { |
757 | 0 | continue; |
758 | 0 | } |
759 | 0 | add_group(MI, pa_insns[i].grp); |
760 | 0 | } |
761 | 0 | } |
762 | | |
763 | | #ifndef CAPSTONE_DIET |
764 | | static void update_regs_access(MCInst *MI, unsigned int opcode) |
765 | 0 | { |
766 | 0 | if (opcode == HPPA_INS_INVALID) |
767 | 0 | return; |
768 | | |
769 | 0 | hppa_ext *hppa_ext = &MI->hppa_ext; |
770 | 0 | switch (opcode) { |
771 | 0 | default: |
772 | 0 | break; |
773 | 0 | case HPPA_INS_BLE: |
774 | 0 | map_add_implicit_write(MI, HPPA_REG_GR31); |
775 | 0 | map_add_implicit_write(MI, HPPA_REG_SR0); |
776 | 0 | break; |
777 | 0 | case HPPA_INS_BVB: |
778 | 0 | map_add_implicit_read(MI, HPPA_REG_CR11); |
779 | 0 | break; |
780 | 0 | case HPPA_INS_RFI: |
781 | 0 | if (hppa_ext->mod_num == 0) { |
782 | 0 | break; |
783 | 0 | } |
784 | | // fallthrough |
785 | 0 | case HPPA_INS_RFIR: |
786 | 0 | map_add_implicit_write(MI, HPPA_REG_GR1); |
787 | 0 | map_add_implicit_write(MI, HPPA_REG_GR8); |
788 | 0 | map_add_implicit_write(MI, HPPA_REG_GR9); |
789 | 0 | map_add_implicit_write(MI, HPPA_REG_GR16); |
790 | 0 | map_add_implicit_write(MI, HPPA_REG_GR17); |
791 | 0 | map_add_implicit_write(MI, HPPA_REG_GR24); |
792 | 0 | map_add_implicit_write(MI, HPPA_REG_GR25); |
793 | 0 | break; |
794 | 0 | case HPPA_INS_VDEP: |
795 | 0 | case HPPA_INS_VDEPI: |
796 | 0 | case HPPA_INS_VEXTRS: |
797 | 0 | case HPPA_INS_VEXTRU: |
798 | 0 | case HPPA_INS_VSHD: |
799 | 0 | case HPPA_INS_ZVDEPI: |
800 | 0 | map_add_implicit_read(MI, HPPA_REG_CR11); |
801 | 0 | break; |
802 | 0 | case HPPA_INS_ADDIL: |
803 | 0 | map_add_implicit_write(MI, HPPA_REG_GR1); |
804 | 0 | break; |
805 | 0 | } |
806 | 0 | } |
807 | | #endif |
808 | | |
809 | | void HPPA_printInst(MCInst *MI, SStream *O, void *Info) |
810 | 0 | { |
811 | 0 | cs_hppa hppa; |
812 | | |
813 | | /* set pubOpcode as instruction id */ |
814 | 0 | MCInst_setOpcodePub(MI, MCInst_getOpcode(MI)); |
815 | |
|
816 | 0 | SStream_concat(O, HPPA_insn_name((csh)MI->csh, MCInst_getOpcode(MI))); |
817 | 0 | print_modifiers(MI, O); |
818 | 0 | SStream_concat(O, " "); |
819 | 0 | fill_operands(MI, &hppa); |
820 | 0 | for (int i = 0; i < hppa.op_count; i++) { |
821 | 0 | cs_hppa_op *op = &hppa.operands[i]; |
822 | 0 | print_operand(MI, O, op); |
823 | 0 | if (op->type != HPPA_OP_IDX_REG && op->type != HPPA_OP_DISP && |
824 | 0 | i != hppa.op_count - 1) { |
825 | 0 | SStream_concat(O, ","); |
826 | 0 | } |
827 | 0 | } |
828 | |
|
829 | 0 | if (detail_is_set(MI)) { |
830 | 0 | cs_hppa *hppa_detail = HPPA_get_detail(MI); |
831 | 0 | *hppa_detail = hppa; |
832 | 0 | add_groups(MI); |
833 | 0 | #ifndef CAPSTONE_DIET |
834 | 0 | update_regs_access(MI, MCInst_getOpcode(MI)); |
835 | 0 | #endif |
836 | 0 | } |
837 | 0 | } |
838 | | |
839 | | #endif |