Coverage Report

Created: 2025-07-01 07:03

/src/capstonenext/arch/Xtensa/XtensaGenDisassemblerTables.inc
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/*    Rot127 <unisono@quyllur.org> 2022-2024 */
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/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Do not edit. */
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/* Capstone's LLVM TableGen Backends: */
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/* https://github.com/capstone-engine/llvm-capstone */
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#include "../../MCInst.h"
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#include "../../cs_priv.h"
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#include "../../LEB128.h"
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// Helper function for extracting fields from encoded instructions.
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#define FieldFromInstruction(fname, InsnType) \
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static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
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{ \
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  InsnType fieldMask; \
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  if (numBits == sizeof(InsnType) * 8) \
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    fieldMask = (InsnType)(-1LL); \
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  else \
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    fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
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  return (insn & fieldMask) >> startBit; \
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}
XtensaDisassembler.c:fieldFromInstruction_2
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98.4k
static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
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{ \
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  InsnType fieldMask; \
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  if (numBits == sizeof(InsnType) * 8) \
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    fieldMask = (InsnType)(-1LL); \
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  else \
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    fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
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  return (insn & fieldMask) >> startBit; \
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}
XtensaDisassembler.c:fieldFromInstruction_3
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static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
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{ \
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  InsnType fieldMask; \
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  if (numBits == sizeof(InsnType) * 8) \
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    fieldMask = (InsnType)(-1LL); \
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  else \
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    fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
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  return (insn & fieldMask) >> startBit; \
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}
XtensaDisassembler.c:fieldFromInstruction_4
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static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
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{ \
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  InsnType fieldMask; \
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  if (numBits == sizeof(InsnType) * 8) \
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    fieldMask = (InsnType)(-1LL); \
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  else \
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    fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
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  return (insn & fieldMask) >> startBit; \
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}
XtensaDisassembler.c:fieldFromInstruction_6
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static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
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{ \
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  InsnType fieldMask; \
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  if (numBits == sizeof(InsnType) * 8) \
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    fieldMask = (InsnType)(-1LL); \
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  else \
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    fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
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  return (insn & fieldMask) >> startBit; \
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}
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static bool Check(DecodeStatus *Out, const DecodeStatus In) {
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  *Out = (DecodeStatus) (*Out & In);
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  return *Out != MCDisassembler_Fail;
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}
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static const uint8_t DecoderTable16[] = {
36
/* 0 */       MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
37
/* 3 */       MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 17
38
/* 8 */       MCD_OPC_CheckPredicate, 0, 163, 0, 0, // Skip to: 176
39
/* 13 */      MCD_OPC_Decode, 179, 13, 0, // Opcode: L32I_N
40
/* 17 */      MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 31
41
/* 22 */      MCD_OPC_CheckPredicate, 0, 149, 0, 0, // Skip to: 176
42
/* 27 */      MCD_OPC_Decode, 234, 14, 0, // Opcode: S32I_N
43
/* 31 */      MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 45
44
/* 36 */      MCD_OPC_CheckPredicate, 0, 135, 0, 0, // Skip to: 176
45
/* 41 */      MCD_OPC_Decode, 208, 4, 1, // Opcode: ADD_N
46
/* 45 */      MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 59
47
/* 50 */      MCD_OPC_CheckPredicate, 0, 121, 0, 0, // Skip to: 176
48
/* 55 */      MCD_OPC_Decode, 203, 4, 2, // Opcode: ADDI_N
49
/* 59 */      MCD_OPC_FilterValue, 12, 40, 0, 0, // Skip to: 104
50
/* 64 */      MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
51
/* 67 */      MCD_OPC_FilterValue, 0, 104, 0, 0, // Skip to: 176
52
/* 72 */      MCD_OPC_CheckPredicate, 1, 18, 0, 0, // Skip to: 95
53
/* 77 */      MCD_OPC_CheckField, 12, 4, 15, 11, 0, 0, // Skip to: 95
54
/* 84 */      MCD_OPC_CheckField, 4, 3, 2, 4, 0, 0, // Skip to: 95
55
/* 91 */      MCD_OPC_Decode, 184, 11, 3, // Opcode: BREAK_N
56
/* 95 */      MCD_OPC_CheckPredicate, 0, 76, 0, 0, // Skip to: 176
57
/* 100 */     MCD_OPC_Decode, 208, 13, 4, // Opcode: MOVI_N
58
/* 104 */     MCD_OPC_FilterValue, 13, 67, 0, 0, // Skip to: 176
59
/* 109 */     MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
60
/* 112 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 126
61
/* 117 */     MCD_OPC_CheckPredicate, 0, 54, 0, 0, // Skip to: 176
62
/* 122 */     MCD_OPC_Decode, 216, 13, 5, // Opcode: MOV_N
63
/* 126 */     MCD_OPC_FilterValue, 15, 45, 0, 0, // Skip to: 176
64
/* 131 */     MCD_OPC_ExtractField, 4, 8,  // Inst{11-4} ...
65
/* 134 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 148
66
/* 139 */     MCD_OPC_CheckPredicate, 0, 32, 0, 0, // Skip to: 176
67
/* 144 */     MCD_OPC_Decode, 182, 14, 6, // Opcode: RET_N
68
/* 148 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 162
69
/* 153 */     MCD_OPC_CheckPredicate, 2, 18, 0, 0, // Skip to: 176
70
/* 158 */     MCD_OPC_Decode, 181, 14, 6, // Opcode: RETW_N
71
/* 162 */     MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 176
72
/* 167 */     MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 176
73
/* 172 */     MCD_OPC_Decode, 171, 13, 6, // Opcode: ILL_N
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/* 176 */     MCD_OPC_Fail,
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  0
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};
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static const uint8_t DecoderTable24[] = {
79
/* 0 */       MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
80
/* 3 */       MCD_OPC_FilterValue, 0, 112, 10, 0, // Skip to: 2680
81
/* 8 */       MCD_OPC_ExtractField, 17, 3,  // Inst{19-17} ...
82
/* 11 */      MCD_OPC_FilterValue, 0, 77, 4, 0, // Skip to: 1117
83
/* 16 */      MCD_OPC_ExtractField, 21, 3,  // Inst{23-21} ...
84
/* 19 */      MCD_OPC_FilterValue, 0, 223, 1, 0, // Skip to: 503
85
/* 24 */      MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
86
/* 27 */      MCD_OPC_FilterValue, 0, 206, 1, 0, // Skip to: 494
87
/* 32 */      MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
88
/* 35 */      MCD_OPC_FilterValue, 0, 189, 1, 0, // Skip to: 485
89
/* 40 */      MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
90
/* 43 */      MCD_OPC_FilterValue, 0, 116, 0, 0, // Skip to: 164
91
/* 48 */      MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
92
/* 51 */      MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 67
93
/* 56 */      MCD_OPC_CheckField, 8, 4, 0, 251, 19, 0, // Skip to: 5178
94
/* 63 */      MCD_OPC_Decode, 170, 13, 6, // Opcode: ILL
95
/* 67 */      MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 83
96
/* 72 */      MCD_OPC_CheckField, 8, 4, 0, 235, 19, 0, // Skip to: 5178
97
/* 79 */      MCD_OPC_Decode, 179, 14, 6, // Opcode: RET
98
/* 83 */      MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 104
99
/* 88 */      MCD_OPC_CheckPredicate, 3, 221, 19, 0, // Skip to: 5178
100
/* 93 */      MCD_OPC_CheckField, 8, 4, 0, 214, 19, 0, // Skip to: 5178
101
/* 100 */     MCD_OPC_Decode, 180, 14, 6, // Opcode: RETW
102
/* 104 */     MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 113
103
/* 109 */     MCD_OPC_Decode, 174, 13, 7, // Opcode: JX
104
/* 113 */     MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 122
105
/* 118 */     MCD_OPC_Decode, 190, 11, 7, // Opcode: CALLX0
106
/* 122 */     MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 136
107
/* 127 */     MCD_OPC_CheckPredicate, 3, 182, 19, 0, // Skip to: 5178
108
/* 132 */     MCD_OPC_Decode, 192, 11, 7, // Opcode: CALLX4
109
/* 136 */     MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 150
110
/* 141 */     MCD_OPC_CheckPredicate, 3, 168, 19, 0, // Skip to: 5178
111
/* 146 */     MCD_OPC_Decode, 193, 11, 7, // Opcode: CALLX8
112
/* 150 */     MCD_OPC_FilterValue, 15, 159, 19, 0, // Skip to: 5178
113
/* 155 */     MCD_OPC_CheckPredicate, 3, 154, 19, 0, // Skip to: 5178
114
/* 160 */     MCD_OPC_Decode, 191, 11, 7, // Opcode: CALLX12
115
/* 164 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 178
116
/* 169 */     MCD_OPC_CheckPredicate, 3, 140, 19, 0, // Skip to: 5178
117
/* 174 */     MCD_OPC_Decode, 213, 13, 5, // Opcode: MOVSP
118
/* 178 */     MCD_OPC_FilterValue, 2, 80, 0, 0, // Skip to: 263
119
/* 183 */     MCD_OPC_ExtractField, 4, 8,  // Inst{11-4} ...
120
/* 186 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 195
121
/* 191 */     MCD_OPC_Decode, 172, 13, 6, // Opcode: ISYNC
122
/* 195 */     MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 204
123
/* 200 */     MCD_OPC_Decode, 194, 14, 6, // Opcode: RSYNC
124
/* 204 */     MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 213
125
/* 209 */     MCD_OPC_Decode, 163, 13, 6, // Opcode: ESYNC
126
/* 213 */     MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 222
127
/* 218 */     MCD_OPC_Decode, 200, 11, 6, // Opcode: DSYNC
128
/* 222 */     MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 236
129
/* 227 */     MCD_OPC_CheckPredicate, 4, 82, 19, 0, // Skip to: 5178
130
/* 232 */     MCD_OPC_Decode, 164, 13, 6, // Opcode: EXCW
131
/* 236 */     MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 245
132
/* 241 */     MCD_OPC_Decode, 196, 13, 6, // Opcode: MEMW
133
/* 245 */     MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 254
134
/* 250 */     MCD_OPC_Decode, 166, 13, 6, // Opcode: EXTW
135
/* 254 */     MCD_OPC_FilterValue, 15, 55, 19, 0, // Skip to: 5178
136
/* 259 */     MCD_OPC_Decode, 164, 14, 6, // Opcode: NOP
137
/* 263 */     MCD_OPC_FilterValue, 3, 81, 0, 0, // Skip to: 349
138
/* 268 */     MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
139
/* 271 */     MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 335
140
/* 276 */     MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
141
/* 279 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 293
142
/* 284 */     MCD_OPC_CheckPredicate, 4, 25, 19, 0, // Skip to: 5178
143
/* 289 */     MCD_OPC_Decode, 184, 14, 6, // Opcode: RFE
144
/* 293 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 307
145
/* 298 */     MCD_OPC_CheckPredicate, 4, 11, 19, 0, // Skip to: 5178
146
/* 303 */     MCD_OPC_Decode, 183, 14, 6, // Opcode: RFDE
147
/* 307 */     MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 321
148
/* 312 */     MCD_OPC_CheckPredicate, 3, 253, 18, 0, // Skip to: 5178
149
/* 317 */     MCD_OPC_Decode, 187, 14, 6, // Opcode: RFWO
150
/* 321 */     MCD_OPC_FilterValue, 5, 244, 18, 0, // Skip to: 5178
151
/* 326 */     MCD_OPC_CheckPredicate, 3, 239, 18, 0, // Skip to: 5178
152
/* 331 */     MCD_OPC_Decode, 188, 14, 6, // Opcode: RFWU
153
/* 335 */     MCD_OPC_FilterValue, 1, 230, 18, 0, // Skip to: 5178
154
/* 340 */     MCD_OPC_CheckPredicate, 5, 225, 18, 0, // Skip to: 5178
155
/* 345 */     MCD_OPC_Decode, 185, 14, 3, // Opcode: RFI
156
/* 349 */     MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 363
157
/* 354 */     MCD_OPC_CheckPredicate, 6, 211, 18, 0, // Skip to: 5178
158
/* 359 */     MCD_OPC_Decode, 183, 11, 8, // Opcode: BREAK
159
/* 363 */     MCD_OPC_FilterValue, 5, 26, 0, 0, // Skip to: 394
160
/* 368 */     MCD_OPC_ExtractField, 4, 8,  // Inst{11-4} ...
161
/* 371 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 385
162
/* 376 */     MCD_OPC_CheckPredicate, 4, 189, 18, 0, // Skip to: 5178
163
/* 381 */     MCD_OPC_Decode, 132, 15, 6, // Opcode: SYSCALL
164
/* 385 */     MCD_OPC_FilterValue, 16, 180, 18, 0, // Skip to: 5178
165
/* 390 */     MCD_OPC_Decode, 238, 14, 6, // Opcode: SIMCALL
166
/* 394 */     MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 408
167
/* 399 */     MCD_OPC_CheckPredicate, 5, 166, 18, 0, // Skip to: 5178
168
/* 404 */     MCD_OPC_Decode, 191, 14, 9, // Opcode: RSIL
169
/* 408 */     MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 429
170
/* 413 */     MCD_OPC_CheckPredicate, 5, 152, 18, 0, // Skip to: 5178
171
/* 418 */     MCD_OPC_CheckField, 4, 4, 0, 145, 18, 0, // Skip to: 5178
172
/* 425 */     MCD_OPC_Decode, 144, 15, 3, // Opcode: WAITI
173
/* 429 */     MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 443
174
/* 434 */     MCD_OPC_CheckPredicate, 7, 131, 18, 0, // Skip to: 5178
175
/* 439 */     MCD_OPC_Decode, 156, 11, 10, // Opcode: ANY4
176
/* 443 */     MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 457
177
/* 448 */     MCD_OPC_CheckPredicate, 7, 117, 18, 0, // Skip to: 5178
178
/* 453 */     MCD_OPC_Decode, 151, 11, 10, // Opcode: ALL4
179
/* 457 */     MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 471
180
/* 462 */     MCD_OPC_CheckPredicate, 7, 103, 18, 0, // Skip to: 5178
181
/* 467 */     MCD_OPC_Decode, 157, 11, 10, // Opcode: ANY8
182
/* 471 */     MCD_OPC_FilterValue, 11, 94, 18, 0, // Skip to: 5178
183
/* 476 */     MCD_OPC_CheckPredicate, 7, 89, 18, 0, // Skip to: 5178
184
/* 481 */     MCD_OPC_Decode, 152, 11, 10, // Opcode: ALL8
185
/* 485 */     MCD_OPC_FilterValue, 1, 80, 18, 0, // Skip to: 5178
186
/* 490 */     MCD_OPC_Decode, 153, 11, 1, // Opcode: AND
187
/* 494 */     MCD_OPC_FilterValue, 1, 71, 18, 0, // Skip to: 5178
188
/* 499 */     MCD_OPC_Decode, 240, 14, 11, // Opcode: SLLI
189
/* 503 */     MCD_OPC_FilterValue, 1, 38, 0, 0, // Skip to: 546
190
/* 508 */     MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
191
/* 511 */     MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 537
192
/* 516 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
193
/* 519 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 528
194
/* 524 */     MCD_OPC_Decode, 170, 14, 1, // Opcode: OR
195
/* 528 */     MCD_OPC_FilterValue, 1, 37, 18, 0, // Skip to: 5178
196
/* 533 */     MCD_OPC_Decode, 188, 15, 1, // Opcode: XOR
197
/* 537 */     MCD_OPC_FilterValue, 1, 28, 18, 0, // Skip to: 5178
198
/* 542 */     MCD_OPC_Decode, 243, 14, 12, // Opcode: SRAI
199
/* 546 */     MCD_OPC_FilterValue, 2, 251, 0, 0, // Skip to: 802
200
/* 551 */     MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
201
/* 554 */     MCD_OPC_FilterValue, 0, 227, 0, 0, // Skip to: 786
202
/* 559 */     MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
203
/* 562 */     MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 585
204
/* 567 */     MCD_OPC_CheckField, 20, 1, 0, 252, 17, 0, // Skip to: 5178
205
/* 574 */     MCD_OPC_CheckField, 4, 4, 0, 245, 17, 0, // Skip to: 5178
206
/* 581 */     MCD_OPC_Decode, 252, 14, 7, // Opcode: SSR
207
/* 585 */     MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 608
208
/* 590 */     MCD_OPC_CheckField, 20, 1, 0, 229, 17, 0, // Skip to: 5178
209
/* 597 */     MCD_OPC_CheckField, 4, 4, 0, 222, 17, 0, // Skip to: 5178
210
/* 604 */     MCD_OPC_Decode, 251, 14, 7, // Opcode: SSL
211
/* 608 */     MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 631
212
/* 613 */     MCD_OPC_CheckField, 20, 1, 0, 206, 17, 0, // Skip to: 5178
213
/* 620 */     MCD_OPC_CheckField, 4, 4, 0, 199, 17, 0, // Skip to: 5178
214
/* 627 */     MCD_OPC_Decode, 247, 14, 7, // Opcode: SSA8L
215
/* 631 */     MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 654
216
/* 636 */     MCD_OPC_CheckField, 20, 1, 0, 183, 17, 0, // Skip to: 5178
217
/* 643 */     MCD_OPC_CheckField, 5, 3, 0, 176, 17, 0, // Skip to: 5178
218
/* 650 */     MCD_OPC_Decode, 248, 14, 13, // Opcode: SSAI
219
/* 654 */     MCD_OPC_FilterValue, 6, 26, 0, 0, // Skip to: 685
220
/* 659 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
221
/* 662 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 671
222
/* 667 */     MCD_OPC_Decode, 178, 14, 5, // Opcode: RER
223
/* 671 */     MCD_OPC_FilterValue, 1, 150, 17, 0, // Skip to: 5178
224
/* 676 */     MCD_OPC_CheckPredicate, 8, 145, 17, 0, // Skip to: 5178
225
/* 681 */     MCD_OPC_Decode, 148, 15, 5, // Opcode: WITLB
226
/* 685 */     MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 701
227
/* 690 */     MCD_OPC_CheckField, 20, 1, 0, 129, 17, 0, // Skip to: 5178
228
/* 697 */     MCD_OPC_Decode, 146, 15, 5, // Opcode: WER
229
/* 701 */     MCD_OPC_FilterValue, 8, 23, 0, 0, // Skip to: 729
230
/* 706 */     MCD_OPC_CheckPredicate, 3, 115, 17, 0, // Skip to: 5178
231
/* 711 */     MCD_OPC_CheckField, 20, 1, 0, 108, 17, 0, // Skip to: 5178
232
/* 718 */     MCD_OPC_CheckField, 8, 4, 0, 101, 17, 0, // Skip to: 5178
233
/* 725 */     MCD_OPC_Decode, 189, 14, 14, // Opcode: ROTW
234
/* 729 */     MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 765
235
/* 734 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
236
/* 737 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 751
237
/* 742 */     MCD_OPC_CheckPredicate, 9, 79, 17, 0, // Skip to: 5178
238
/* 747 */     MCD_OPC_Decode, 165, 14, 5, // Opcode: NSA
239
/* 751 */     MCD_OPC_FilterValue, 1, 70, 17, 0, // Skip to: 5178
240
/* 756 */     MCD_OPC_CheckPredicate, 8, 65, 17, 0, // Skip to: 5178
241
/* 761 */     MCD_OPC_Decode, 145, 15, 5, // Opcode: WDTLB
242
/* 765 */     MCD_OPC_FilterValue, 15, 56, 17, 0, // Skip to: 5178
243
/* 770 */     MCD_OPC_CheckPredicate, 9, 51, 17, 0, // Skip to: 5178
244
/* 775 */     MCD_OPC_CheckField, 20, 1, 0, 44, 17, 0, // Skip to: 5178
245
/* 782 */     MCD_OPC_Decode, 166, 14, 5, // Opcode: NSAU
246
/* 786 */     MCD_OPC_FilterValue, 1, 35, 17, 0, // Skip to: 5178
247
/* 791 */     MCD_OPC_CheckField, 20, 1, 0, 28, 17, 0, // Skip to: 5178
248
/* 798 */     MCD_OPC_Decode, 246, 14, 15, // Opcode: SRLI
249
/* 802 */     MCD_OPC_FilterValue, 3, 59, 0, 0, // Skip to: 866
250
/* 807 */     MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
251
/* 810 */     MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 850
252
/* 815 */     MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
253
/* 818 */     MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 834
254
/* 823 */     MCD_OPC_CheckField, 20, 1, 0, 252, 16, 0, // Skip to: 5178
255
/* 830 */     MCD_OPC_Decode, 161, 14, 16, // Opcode: NEG
256
/* 834 */     MCD_OPC_FilterValue, 1, 243, 16, 0, // Skip to: 5178
257
/* 839 */     MCD_OPC_CheckField, 20, 1, 0, 236, 16, 0, // Skip to: 5178
258
/* 846 */     MCD_OPC_Decode, 197, 4, 16, // Opcode: ABS
259
/* 850 */     MCD_OPC_FilterValue, 1, 227, 16, 0, // Skip to: 5178
260
/* 855 */     MCD_OPC_CheckField, 20, 1, 0, 220, 16, 0, // Skip to: 5178
261
/* 862 */     MCD_OPC_Decode, 190, 15, 17, // Opcode: XSR
262
/* 866 */     MCD_OPC_FilterValue, 4, 62, 0, 0, // Skip to: 933
263
/* 871 */     MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
264
/* 874 */     MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 900
265
/* 879 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
266
/* 882 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 891
267
/* 887 */     MCD_OPC_Decode, 199, 4, 1, // Opcode: ADD
268
/* 891 */     MCD_OPC_FilterValue, 1, 186, 16, 0, // Skip to: 5178
269
/* 896 */     MCD_OPC_Decode, 205, 4, 1, // Opcode: ADDX2
270
/* 900 */     MCD_OPC_FilterValue, 1, 177, 16, 0, // Skip to: 5178
271
/* 905 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
272
/* 908 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 917
273
/* 913 */     MCD_OPC_Decode, 244, 14, 1, // Opcode: SRC
274
/* 917 */     MCD_OPC_FilterValue, 1, 160, 16, 0, // Skip to: 5178
275
/* 922 */     MCD_OPC_CheckField, 8, 4, 0, 153, 16, 0, // Skip to: 5178
276
/* 929 */     MCD_OPC_Decode, 245, 14, 16, // Opcode: SRL
277
/* 933 */     MCD_OPC_FilterValue, 5, 69, 0, 0, // Skip to: 1007
278
/* 938 */     MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
279
/* 941 */     MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 967
280
/* 946 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
281
/* 949 */     MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 958
282
/* 954 */     MCD_OPC_Decode, 206, 4, 1, // Opcode: ADDX4
283
/* 958 */     MCD_OPC_FilterValue, 1, 119, 16, 0, // Skip to: 5178
284
/* 963 */     MCD_OPC_Decode, 207, 4, 1, // Opcode: ADDX8
285
/* 967 */     MCD_OPC_FilterValue, 1, 110, 16, 0, // Skip to: 5178
286
/* 972 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
287
/* 975 */     MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 991
288
/* 980 */     MCD_OPC_CheckField, 4, 4, 0, 95, 16, 0, // Skip to: 5178
289
/* 987 */     MCD_OPC_Decode, 239, 14, 18, // Opcode: SLL
290
/* 991 */     MCD_OPC_FilterValue, 1, 86, 16, 0, // Skip to: 5178
291
/* 996 */     MCD_OPC_CheckField, 8, 4, 0, 79, 16, 0, // Skip to: 5178
292
/* 1003 */    MCD_OPC_Decode, 242, 14, 16, // Opcode: SRA
293
/* 1007 */    MCD_OPC_FilterValue, 6, 65, 0, 0, // Skip to: 1077
294
/* 1012 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
295
/* 1015 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 1041
296
/* 1020 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
297
/* 1023 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1032
298
/* 1028 */    MCD_OPC_Decode, 255, 14, 1, // Opcode: SUB
299
/* 1032 */    MCD_OPC_FilterValue, 1, 45, 16, 0, // Skip to: 5178
300
/* 1037 */    MCD_OPC_Decode, 128, 15, 1, // Opcode: SUBX2
301
/* 1041 */    MCD_OPC_FilterValue, 1, 36, 16, 0, // Skip to: 5178
302
/* 1046 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
303
/* 1049 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1063
304
/* 1054 */    MCD_OPC_CheckPredicate, 10, 23, 16, 0, // Skip to: 5178
305
/* 1059 */    MCD_OPC_Decode, 220, 13, 1, // Opcode: MUL16U
306
/* 1063 */    MCD_OPC_FilterValue, 1, 14, 16, 0, // Skip to: 5178
307
/* 1068 */    MCD_OPC_CheckPredicate, 10, 9, 16, 0, // Skip to: 5178
308
/* 1073 */    MCD_OPC_Decode, 219, 13, 1, // Opcode: MUL16S
309
/* 1077 */    MCD_OPC_FilterValue, 7, 0, 16, 0, // Skip to: 5178
310
/* 1082 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
311
/* 1085 */    MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 1101
312
/* 1090 */    MCD_OPC_CheckField, 16, 1, 0, 241, 15, 0, // Skip to: 5178
313
/* 1097 */    MCD_OPC_Decode, 129, 15, 1, // Opcode: SUBX4
314
/* 1101 */    MCD_OPC_FilterValue, 1, 232, 15, 0, // Skip to: 5178
315
/* 1106 */    MCD_OPC_CheckField, 16, 1, 0, 225, 15, 0, // Skip to: 5178
316
/* 1113 */    MCD_OPC_Decode, 130, 15, 1, // Opcode: SUBX8
317
/* 1117 */    MCD_OPC_FilterValue, 1, 246, 1, 0, // Skip to: 1624
318
/* 1122 */    MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
319
/* 1125 */    MCD_OPC_FilterValue, 0, 26, 0, 0, // Skip to: 1156
320
/* 1130 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
321
/* 1133 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1147
322
/* 1138 */    MCD_OPC_CheckPredicate, 7, 195, 15, 0, // Skip to: 5178
323
/* 1143 */    MCD_OPC_Decode, 154, 11, 19, // Opcode: ANDB
324
/* 1147 */    MCD_OPC_FilterValue, 1, 186, 15, 0, // Skip to: 5178
325
/* 1152 */    MCD_OPC_Decode, 193, 14, 20, // Opcode: RSR
326
/* 1156 */    MCD_OPC_FilterValue, 1, 26, 0, 0, // Skip to: 1187
327
/* 1161 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
328
/* 1164 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1178
329
/* 1169 */    MCD_OPC_CheckPredicate, 7, 164, 15, 0, // Skip to: 5178
330
/* 1174 */    MCD_OPC_Decode, 155, 11, 19, // Opcode: ANDBC
331
/* 1178 */    MCD_OPC_FilterValue, 1, 155, 15, 0, // Skip to: 5178
332
/* 1183 */    MCD_OPC_Decode, 150, 15, 21, // Opcode: WSR
333
/* 1187 */    MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 1223
334
/* 1192 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
335
/* 1195 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1209
336
/* 1200 */    MCD_OPC_CheckPredicate, 7, 133, 15, 0, // Skip to: 5178
337
/* 1205 */    MCD_OPC_Decode, 171, 14, 19, // Opcode: ORB
338
/* 1209 */    MCD_OPC_FilterValue, 1, 124, 15, 0, // Skip to: 5178
339
/* 1214 */    MCD_OPC_CheckPredicate, 11, 119, 15, 0, // Skip to: 5178
340
/* 1219 */    MCD_OPC_Decode, 237, 14, 22, // Opcode: SEXT
341
/* 1223 */    MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 1259
342
/* 1228 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
343
/* 1231 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1245
344
/* 1236 */    MCD_OPC_CheckPredicate, 7, 97, 15, 0, // Skip to: 5178
345
/* 1241 */    MCD_OPC_Decode, 172, 14, 19, // Opcode: ORBC
346
/* 1245 */    MCD_OPC_FilterValue, 1, 88, 15, 0, // Skip to: 5178
347
/* 1250 */    MCD_OPC_CheckPredicate, 12, 83, 15, 0, // Skip to: 5178
348
/* 1255 */    MCD_OPC_Decode, 195, 11, 22, // Opcode: CLAMPS
349
/* 1259 */    MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 1295
350
/* 1264 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
351
/* 1267 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1281
352
/* 1272 */    MCD_OPC_CheckPredicate, 7, 61, 15, 0, // Skip to: 5178
353
/* 1277 */    MCD_OPC_Decode, 189, 15, 19, // Opcode: XORB
354
/* 1281 */    MCD_OPC_FilterValue, 1, 52, 15, 0, // Skip to: 5178
355
/* 1286 */    MCD_OPC_CheckPredicate, 13, 47, 15, 0, // Skip to: 5178
356
/* 1291 */    MCD_OPC_Decode, 197, 13, 1, // Opcode: MIN
357
/* 1295 */    MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 1316
358
/* 1300 */    MCD_OPC_CheckPredicate, 13, 33, 15, 0, // Skip to: 5178
359
/* 1305 */    MCD_OPC_CheckField, 16, 1, 1, 26, 15, 0, // Skip to: 5178
360
/* 1312 */    MCD_OPC_Decode, 194, 13, 1, // Opcode: MAX
361
/* 1316 */    MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 1337
362
/* 1321 */    MCD_OPC_CheckPredicate, 13, 12, 15, 0, // Skip to: 5178
363
/* 1326 */    MCD_OPC_CheckField, 16, 1, 1, 5, 15, 0, // Skip to: 5178
364
/* 1333 */    MCD_OPC_Decode, 198, 13, 1, // Opcode: MINU
365
/* 1337 */    MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 1358
366
/* 1342 */    MCD_OPC_CheckPredicate, 13, 247, 14, 0, // Skip to: 5178
367
/* 1347 */    MCD_OPC_CheckField, 16, 1, 1, 240, 14, 0, // Skip to: 5178
368
/* 1354 */    MCD_OPC_Decode, 195, 13, 1, // Opcode: MAXU
369
/* 1358 */    MCD_OPC_FilterValue, 8, 26, 0, 0, // Skip to: 1389
370
/* 1363 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
371
/* 1366 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1380
372
/* 1371 */    MCD_OPC_CheckPredicate, 14, 218, 14, 0, // Skip to: 5178
373
/* 1376 */    MCD_OPC_Decode, 253, 13, 1, // Opcode: MULL
374
/* 1380 */    MCD_OPC_FilterValue, 1, 209, 14, 0, // Skip to: 5178
375
/* 1385 */    MCD_OPC_Decode, 201, 13, 1, // Opcode: MOVEQZ
376
/* 1389 */    MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 1405
377
/* 1394 */    MCD_OPC_CheckField, 16, 1, 1, 193, 14, 0, // Skip to: 5178
378
/* 1401 */    MCD_OPC_Decode, 211, 13, 1, // Opcode: MOVNEZ
379
/* 1405 */    MCD_OPC_FilterValue, 10, 26, 0, 0, // Skip to: 1436
380
/* 1410 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
381
/* 1413 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1427
382
/* 1418 */    MCD_OPC_CheckPredicate, 15, 171, 14, 0, // Skip to: 5178
383
/* 1423 */    MCD_OPC_Decode, 143, 14, 1, // Opcode: MULUH
384
/* 1427 */    MCD_OPC_FilterValue, 1, 162, 14, 0, // Skip to: 5178
385
/* 1432 */    MCD_OPC_Decode, 209, 13, 1, // Opcode: MOVLTZ
386
/* 1436 */    MCD_OPC_FilterValue, 11, 26, 0, 0, // Skip to: 1467
387
/* 1441 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
388
/* 1444 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1458
389
/* 1449 */    MCD_OPC_CheckPredicate, 15, 140, 14, 0, // Skip to: 5178
390
/* 1454 */    MCD_OPC_Decode, 254, 13, 1, // Opcode: MULSH
391
/* 1458 */    MCD_OPC_FilterValue, 1, 131, 14, 0, // Skip to: 5178
392
/* 1463 */    MCD_OPC_Decode, 205, 13, 1, // Opcode: MOVGEZ
393
/* 1467 */    MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 1503
394
/* 1472 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
395
/* 1475 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1489
396
/* 1480 */    MCD_OPC_CheckPredicate, 16, 109, 14, 0, // Skip to: 5178
397
/* 1485 */    MCD_OPC_Decode, 174, 14, 1, // Opcode: QUOU
398
/* 1489 */    MCD_OPC_FilterValue, 1, 100, 14, 0, // Skip to: 5178
399
/* 1494 */    MCD_OPC_CheckPredicate, 7, 95, 14, 0, // Skip to: 5178
400
/* 1499 */    MCD_OPC_Decode, 203, 13, 23, // Opcode: MOVF
401
/* 1503 */    MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 1539
402
/* 1508 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
403
/* 1511 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1525
404
/* 1516 */    MCD_OPC_CheckPredicate, 16, 73, 14, 0, // Skip to: 5178
405
/* 1521 */    MCD_OPC_Decode, 173, 14, 1, // Opcode: QUOS
406
/* 1525 */    MCD_OPC_FilterValue, 1, 64, 14, 0, // Skip to: 5178
407
/* 1530 */    MCD_OPC_CheckPredicate, 7, 59, 14, 0, // Skip to: 5178
408
/* 1535 */    MCD_OPC_Decode, 214, 13, 23, // Opcode: MOVT
409
/* 1539 */    MCD_OPC_FilterValue, 14, 26, 0, 0, // Skip to: 1570
410
/* 1544 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
411
/* 1547 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1561
412
/* 1552 */    MCD_OPC_CheckPredicate, 16, 37, 14, 0, // Skip to: 5178
413
/* 1557 */    MCD_OPC_Decode, 177, 14, 1, // Opcode: REMU
414
/* 1561 */    MCD_OPC_FilterValue, 1, 28, 14, 0, // Skip to: 5178
415
/* 1566 */    MCD_OPC_Decode, 195, 14, 24, // Opcode: RUR
416
/* 1570 */    MCD_OPC_FilterValue, 15, 19, 14, 0, // Skip to: 5178
417
/* 1575 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
418
/* 1578 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1592
419
/* 1583 */    MCD_OPC_CheckPredicate, 16, 6, 14, 0, // Skip to: 5178
420
/* 1588 */    MCD_OPC_Decode, 176, 14, 1, // Opcode: REMS
421
/* 1592 */    MCD_OPC_FilterValue, 1, 253, 13, 0, // Skip to: 5178
422
/* 1597 */    MCD_OPC_ExtractField, 8, 8,  // Inst{15-8} ...
423
/* 1600 */    MCD_OPC_FilterValue, 232, 1, 4, 0, 0, // Skip to: 1610
424
/* 1606 */    MCD_OPC_Decode, 169, 15, 25, // Opcode: WUR_FCR
425
/* 1610 */    MCD_OPC_FilterValue, 233, 1, 4, 0, 0, // Skip to: 1620
426
/* 1616 */    MCD_OPC_Decode, 171, 15, 25, // Opcode: WUR_FSR
427
/* 1620 */    MCD_OPC_Decode, 151, 15, 26, // Opcode: WUR
428
/* 1624 */    MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1633
429
/* 1629 */    MCD_OPC_Decode, 165, 13, 27, // Opcode: EXTUI
430
/* 1633 */    MCD_OPC_FilterValue, 3, 94, 0, 0, // Skip to: 1732
431
/* 1638 */    MCD_OPC_ExtractField, 12, 5,  // Inst{16-12} ...
432
/* 1641 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1662
433
/* 1646 */    MCD_OPC_CheckPredicate, 17, 199, 13, 0, // Skip to: 5178
434
/* 1651 */    MCD_OPC_CheckField, 20, 4, 0, 192, 13, 0, // Skip to: 5178
435
/* 1658 */    MCD_OPC_Decode, 196, 11, 28, // Opcode: CLR_BIT_GPIO_OUT
436
/* 1662 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 1683
437
/* 1667 */    MCD_OPC_CheckPredicate, 17, 178, 13, 0, // Skip to: 5178
438
/* 1672 */    MCD_OPC_CheckField, 20, 4, 0, 171, 13, 0, // Skip to: 5178
439
/* 1679 */    MCD_OPC_Decode, 236, 14, 28, // Opcode: SET_BIT_GPIO_OUT
440
/* 1683 */    MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 1704
441
/* 1688 */    MCD_OPC_CheckPredicate, 17, 157, 13, 0, // Skip to: 5178
442
/* 1693 */    MCD_OPC_CheckField, 20, 4, 0, 150, 13, 0, // Skip to: 5178
443
/* 1700 */    MCD_OPC_Decode, 149, 15, 29, // Opcode: WR_MASK_GPIO_OUT
444
/* 1704 */    MCD_OPC_FilterValue, 3, 141, 13, 0, // Skip to: 5178
445
/* 1709 */    MCD_OPC_CheckPredicate, 17, 136, 13, 0, // Skip to: 5178
446
/* 1714 */    MCD_OPC_CheckField, 20, 4, 0, 129, 13, 0, // Skip to: 5178
447
/* 1721 */    MCD_OPC_CheckField, 8, 4, 0, 122, 13, 0, // Skip to: 5178
448
/* 1728 */    MCD_OPC_Decode, 169, 13, 25, // Opcode: GET_GPIO_IN
449
/* 1732 */    MCD_OPC_FilterValue, 4, 117, 0, 0, // Skip to: 1854
450
/* 1737 */    MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
451
/* 1740 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 1776
452
/* 1745 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
453
/* 1748 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1762
454
/* 1753 */    MCD_OPC_CheckPredicate, 18, 92, 13, 0, // Skip to: 5178
455
/* 1758 */    MCD_OPC_Decode, 190, 13, 30, // Opcode: LSX
456
/* 1762 */    MCD_OPC_FilterValue, 1, 83, 13, 0, // Skip to: 5178
457
/* 1767 */    MCD_OPC_CheckPredicate, 3, 78, 13, 0, // Skip to: 5178
458
/* 1772 */    MCD_OPC_Decode, 177, 13, 31, // Opcode: L32E
459
/* 1776 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 1797
460
/* 1781 */    MCD_OPC_CheckPredicate, 18, 64, 13, 0, // Skip to: 5178
461
/* 1786 */    MCD_OPC_CheckField, 16, 1, 0, 57, 13, 0, // Skip to: 5178
462
/* 1793 */    MCD_OPC_Decode, 191, 13, 32, // Opcode: LSXP
463
/* 1797 */    MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 1833
464
/* 1802 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
465
/* 1805 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1819
466
/* 1810 */    MCD_OPC_CheckPredicate, 18, 35, 13, 0, // Skip to: 5178
467
/* 1815 */    MCD_OPC_Decode, 253, 14, 30, // Opcode: SSX
468
/* 1819 */    MCD_OPC_FilterValue, 1, 26, 13, 0, // Skip to: 5178
469
/* 1824 */    MCD_OPC_CheckPredicate, 3, 21, 13, 0, // Skip to: 5178
470
/* 1829 */    MCD_OPC_Decode, 232, 14, 31, // Opcode: S32E
471
/* 1833 */    MCD_OPC_FilterValue, 5, 12, 13, 0, // Skip to: 5178
472
/* 1838 */    MCD_OPC_CheckPredicate, 18, 7, 13, 0, // Skip to: 5178
473
/* 1843 */    MCD_OPC_CheckField, 16, 1, 0, 0, 13, 0, // Skip to: 5178
474
/* 1850 */    MCD_OPC_Decode, 254, 14, 33, // Opcode: SSXP
475
/* 1854 */    MCD_OPC_FilterValue, 5, 247, 12, 0, // Skip to: 5178
476
/* 1859 */    MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
477
/* 1862 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1883
478
/* 1867 */    MCD_OPC_CheckPredicate, 18, 234, 12, 0, // Skip to: 5178
479
/* 1872 */    MCD_OPC_CheckField, 16, 1, 0, 227, 12, 0, // Skip to: 5178
480
/* 1879 */    MCD_OPC_Decode, 209, 4, 34, // Opcode: ADD_S
481
/* 1883 */    MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 1919
482
/* 1888 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
483
/* 1891 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1905
484
/* 1896 */    MCD_OPC_CheckPredicate, 18, 205, 12, 0, // Skip to: 5178
485
/* 1901 */    MCD_OPC_Decode, 131, 15, 34, // Opcode: SUB_S
486
/* 1905 */    MCD_OPC_FilterValue, 1, 196, 12, 0, // Skip to: 5178
487
/* 1910 */    MCD_OPC_CheckPredicate, 18, 191, 12, 0, // Skip to: 5178
488
/* 1915 */    MCD_OPC_Decode, 142, 15, 35, // Opcode: UN_S
489
/* 1919 */    MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 1955
490
/* 1924 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
491
/* 1927 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1941
492
/* 1932 */    MCD_OPC_CheckPredicate, 18, 169, 12, 0, // Skip to: 5178
493
/* 1937 */    MCD_OPC_Decode, 160, 14, 34, // Opcode: MUL_S
494
/* 1941 */    MCD_OPC_FilterValue, 1, 160, 12, 0, // Skip to: 5178
495
/* 1946 */    MCD_OPC_CheckPredicate, 18, 155, 12, 0, // Skip to: 5178
496
/* 1951 */    MCD_OPC_Decode, 167, 14, 35, // Opcode: OEQ_S
497
/* 1955 */    MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 1976
498
/* 1960 */    MCD_OPC_CheckPredicate, 18, 141, 12, 0, // Skip to: 5178
499
/* 1965 */    MCD_OPC_CheckField, 16, 1, 1, 134, 12, 0, // Skip to: 5178
500
/* 1972 */    MCD_OPC_Decode, 134, 15, 35, // Opcode: UEQ_S
501
/* 1976 */    MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 2012
502
/* 1981 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
503
/* 1984 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1998
504
/* 1989 */    MCD_OPC_CheckPredicate, 18, 112, 12, 0, // Skip to: 5178
505
/* 1994 */    MCD_OPC_Decode, 193, 13, 36, // Opcode: MADD_S
506
/* 1998 */    MCD_OPC_FilterValue, 1, 103, 12, 0, // Skip to: 5178
507
/* 2003 */    MCD_OPC_CheckPredicate, 18, 98, 12, 0, // Skip to: 5178
508
/* 2008 */    MCD_OPC_Decode, 169, 14, 35, // Opcode: OLT_S
509
/* 2012 */    MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 2048
510
/* 2017 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
511
/* 2020 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2034
512
/* 2025 */    MCD_OPC_CheckPredicate, 18, 76, 12, 0, // Skip to: 5178
513
/* 2030 */    MCD_OPC_Decode, 218, 13, 36, // Opcode: MSUB_S
514
/* 2034 */    MCD_OPC_FilterValue, 1, 67, 12, 0, // Skip to: 5178
515
/* 2039 */    MCD_OPC_CheckPredicate, 18, 62, 12, 0, // Skip to: 5178
516
/* 2044 */    MCD_OPC_Decode, 137, 15, 35, // Opcode: ULT_S
517
/* 2048 */    MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 2084
518
/* 2053 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
519
/* 2056 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2070
520
/* 2061 */    MCD_OPC_CheckPredicate, 18, 40, 12, 0, // Skip to: 5178
521
/* 2066 */    MCD_OPC_Decode, 192, 13, 36, // Opcode: MADDN_S
522
/* 2070 */    MCD_OPC_FilterValue, 1, 31, 12, 0, // Skip to: 5178
523
/* 2075 */    MCD_OPC_CheckPredicate, 18, 26, 12, 0, // Skip to: 5178
524
/* 2080 */    MCD_OPC_Decode, 168, 14, 35, // Opcode: OLE_S
525
/* 2084 */    MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 2120
526
/* 2089 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
527
/* 2092 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2106
528
/* 2097 */    MCD_OPC_CheckPredicate, 18, 4, 12, 0, // Skip to: 5178
529
/* 2102 */    MCD_OPC_Decode, 199, 11, 36, // Opcode: DIVN_S
530
/* 2106 */    MCD_OPC_FilterValue, 1, 251, 11, 0, // Skip to: 5178
531
/* 2111 */    MCD_OPC_CheckPredicate, 18, 246, 11, 0, // Skip to: 5178
532
/* 2116 */    MCD_OPC_Decode, 136, 15, 35, // Opcode: ULE_S
533
/* 2120 */    MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 2156
534
/* 2125 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
535
/* 2128 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2142
536
/* 2133 */    MCD_OPC_CheckPredicate, 18, 224, 11, 0, // Skip to: 5178
537
/* 2138 */    MCD_OPC_Decode, 190, 14, 37, // Opcode: ROUND_S
538
/* 2142 */    MCD_OPC_FilterValue, 1, 215, 11, 0, // Skip to: 5178
539
/* 2147 */    MCD_OPC_CheckPredicate, 18, 210, 11, 0, // Skip to: 5178
540
/* 2152 */    MCD_OPC_Decode, 202, 13, 38, // Opcode: MOVEQZ_S
541
/* 2156 */    MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 2192
542
/* 2161 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
543
/* 2164 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2178
544
/* 2169 */    MCD_OPC_CheckPredicate, 18, 188, 11, 0, // Skip to: 5178
545
/* 2174 */    MCD_OPC_Decode, 133, 15, 37, // Opcode: TRUNC_S
546
/* 2178 */    MCD_OPC_FilterValue, 1, 179, 11, 0, // Skip to: 5178
547
/* 2183 */    MCD_OPC_CheckPredicate, 18, 174, 11, 0, // Skip to: 5178
548
/* 2188 */    MCD_OPC_Decode, 212, 13, 38, // Opcode: MOVNEZ_S
549
/* 2192 */    MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 2228
550
/* 2197 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
551
/* 2200 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2214
552
/* 2205 */    MCD_OPC_CheckPredicate, 18, 152, 11, 0, // Skip to: 5178
553
/* 2210 */    MCD_OPC_Decode, 168, 13, 37, // Opcode: FLOOR_S
554
/* 2214 */    MCD_OPC_FilterValue, 1, 143, 11, 0, // Skip to: 5178
555
/* 2219 */    MCD_OPC_CheckPredicate, 18, 138, 11, 0, // Skip to: 5178
556
/* 2224 */    MCD_OPC_Decode, 210, 13, 38, // Opcode: MOVLTZ_S
557
/* 2228 */    MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 2264
558
/* 2233 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
559
/* 2236 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2250
560
/* 2241 */    MCD_OPC_CheckPredicate, 18, 116, 11, 0, // Skip to: 5178
561
/* 2246 */    MCD_OPC_Decode, 194, 11, 37, // Opcode: CEIL_S
562
/* 2250 */    MCD_OPC_FilterValue, 1, 107, 11, 0, // Skip to: 5178
563
/* 2255 */    MCD_OPC_CheckPredicate, 18, 102, 11, 0, // Skip to: 5178
564
/* 2260 */    MCD_OPC_Decode, 206, 13, 38, // Opcode: MOVGEZ_S
565
/* 2264 */    MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 2300
566
/* 2269 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
567
/* 2272 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2286
568
/* 2277 */    MCD_OPC_CheckPredicate, 18, 80, 11, 0, // Skip to: 5178
569
/* 2282 */    MCD_OPC_Decode, 167, 13, 39, // Opcode: FLOAT_S
570
/* 2286 */    MCD_OPC_FilterValue, 1, 71, 11, 0, // Skip to: 5178
571
/* 2291 */    MCD_OPC_CheckPredicate, 19, 66, 11, 0, // Skip to: 5178
572
/* 2296 */    MCD_OPC_Decode, 204, 13, 40, // Opcode: MOVF_S
573
/* 2300 */    MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 2336
574
/* 2305 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
575
/* 2308 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2322
576
/* 2313 */    MCD_OPC_CheckPredicate, 18, 44, 11, 0, // Skip to: 5178
577
/* 2318 */    MCD_OPC_Decode, 135, 15, 39, // Opcode: UFLOAT_S
578
/* 2322 */    MCD_OPC_FilterValue, 1, 35, 11, 0, // Skip to: 5178
579
/* 2327 */    MCD_OPC_CheckPredicate, 19, 30, 11, 0, // Skip to: 5178
580
/* 2332 */    MCD_OPC_Decode, 215, 13, 40, // Opcode: MOVT_S
581
/* 2336 */    MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 2357
582
/* 2341 */    MCD_OPC_CheckPredicate, 18, 16, 11, 0, // Skip to: 5178
583
/* 2346 */    MCD_OPC_CheckField, 16, 1, 0, 9, 11, 0, // Skip to: 5178
584
/* 2353 */    MCD_OPC_Decode, 143, 15, 37, // Opcode: UTRUNC_S
585
/* 2357 */    MCD_OPC_FilterValue, 15, 0, 11, 0, // Skip to: 5178
586
/* 2362 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
587
/* 2365 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2386
588
/* 2370 */    MCD_OPC_CheckPredicate, 18, 243, 10, 0, // Skip to: 5178
589
/* 2375 */    MCD_OPC_CheckField, 16, 1, 0, 236, 10, 0, // Skip to: 5178
590
/* 2382 */    MCD_OPC_Decode, 217, 13, 41, // Opcode: MOV_S
591
/* 2386 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 2407
592
/* 2391 */    MCD_OPC_CheckPredicate, 18, 222, 10, 0, // Skip to: 5178
593
/* 2396 */    MCD_OPC_CheckField, 16, 1, 0, 215, 10, 0, // Skip to: 5178
594
/* 2403 */    MCD_OPC_Decode, 198, 4, 41, // Opcode: ABS_S
595
/* 2407 */    MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 2428
596
/* 2412 */    MCD_OPC_CheckPredicate, 18, 201, 10, 0, // Skip to: 5178
597
/* 2417 */    MCD_OPC_CheckField, 16, 1, 0, 194, 10, 0, // Skip to: 5178
598
/* 2424 */    MCD_OPC_Decode, 197, 11, 42, // Opcode: CONST_S
599
/* 2428 */    MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 2449
600
/* 2433 */    MCD_OPC_CheckPredicate, 18, 180, 10, 0, // Skip to: 5178
601
/* 2438 */    MCD_OPC_CheckField, 16, 1, 0, 173, 10, 0, // Skip to: 5178
602
/* 2445 */    MCD_OPC_Decode, 186, 14, 43, // Opcode: RFR
603
/* 2449 */    MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 2470
604
/* 2454 */    MCD_OPC_CheckPredicate, 18, 159, 10, 0, // Skip to: 5178
605
/* 2459 */    MCD_OPC_CheckField, 16, 1, 0, 152, 10, 0, // Skip to: 5178
606
/* 2466 */    MCD_OPC_Decode, 147, 15, 44, // Opcode: WFR
607
/* 2470 */    MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2491
608
/* 2475 */    MCD_OPC_CheckPredicate, 18, 138, 10, 0, // Skip to: 5178
609
/* 2480 */    MCD_OPC_CheckField, 16, 1, 0, 131, 10, 0, // Skip to: 5178
610
/* 2487 */    MCD_OPC_Decode, 162, 14, 41, // Opcode: NEG_S
611
/* 2491 */    MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 2512
612
/* 2496 */    MCD_OPC_CheckPredicate, 18, 117, 10, 0, // Skip to: 5178
613
/* 2501 */    MCD_OPC_CheckField, 16, 1, 0, 110, 10, 0, // Skip to: 5178
614
/* 2508 */    MCD_OPC_Decode, 198, 11, 41, // Opcode: DIV0_S
615
/* 2512 */    MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 2533
616
/* 2517 */    MCD_OPC_CheckPredicate, 18, 96, 10, 0, // Skip to: 5178
617
/* 2522 */    MCD_OPC_CheckField, 16, 1, 0, 89, 10, 0, // Skip to: 5178
618
/* 2529 */    MCD_OPC_Decode, 175, 14, 41, // Opcode: RECIP0_S
619
/* 2533 */    MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 2554
620
/* 2538 */    MCD_OPC_CheckPredicate, 18, 75, 10, 0, // Skip to: 5178
621
/* 2543 */    MCD_OPC_CheckField, 16, 1, 0, 68, 10, 0, // Skip to: 5178
622
/* 2550 */    MCD_OPC_Decode, 241, 14, 41, // Opcode: SQRT0_S
623
/* 2554 */    MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 2575
624
/* 2559 */    MCD_OPC_CheckPredicate, 18, 54, 10, 0, // Skip to: 5178
625
/* 2564 */    MCD_OPC_CheckField, 16, 1, 0, 47, 10, 0, // Skip to: 5178
626
/* 2571 */    MCD_OPC_Decode, 192, 14, 41, // Opcode: RSQRT0_S
627
/* 2575 */    MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 2596
628
/* 2580 */    MCD_OPC_CheckPredicate, 18, 33, 10, 0, // Skip to: 5178
629
/* 2585 */    MCD_OPC_CheckField, 16, 1, 0, 26, 10, 0, // Skip to: 5178
630
/* 2592 */    MCD_OPC_Decode, 163, 14, 41, // Opcode: NEXP01_S
631
/* 2596 */    MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 2617
632
/* 2601 */    MCD_OPC_CheckPredicate, 18, 12, 10, 0, // Skip to: 5178
633
/* 2606 */    MCD_OPC_CheckField, 16, 1, 0, 5, 10, 0, // Skip to: 5178
634
/* 2613 */    MCD_OPC_Decode, 200, 13, 41, // Opcode: MKSADJ_S
635
/* 2617 */    MCD_OPC_FilterValue, 13, 16, 0, 0, // Skip to: 2638
636
/* 2622 */    MCD_OPC_CheckPredicate, 18, 247, 9, 0, // Skip to: 5178
637
/* 2627 */    MCD_OPC_CheckField, 16, 1, 0, 240, 9, 0, // Skip to: 5178
638
/* 2634 */    MCD_OPC_Decode, 199, 13, 45, // Opcode: MKDADJ_S
639
/* 2638 */    MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 2659
640
/* 2643 */    MCD_OPC_CheckPredicate, 18, 226, 9, 0, // Skip to: 5178
641
/* 2648 */    MCD_OPC_CheckField, 16, 1, 0, 219, 9, 0, // Skip to: 5178
642
/* 2655 */    MCD_OPC_Decode, 201, 4, 45, // Opcode: ADDEXP_S
643
/* 2659 */    MCD_OPC_FilterValue, 15, 210, 9, 0, // Skip to: 5178
644
/* 2664 */    MCD_OPC_CheckPredicate, 18, 205, 9, 0, // Skip to: 5178
645
/* 2669 */    MCD_OPC_CheckField, 16, 1, 0, 198, 9, 0, // Skip to: 5178
646
/* 2676 */    MCD_OPC_Decode, 200, 4, 45, // Opcode: ADDEXPM_S
647
/* 2680 */    MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2689
648
/* 2685 */    MCD_OPC_Decode, 180, 13, 46, // Opcode: L32R
649
/* 2689 */    MCD_OPC_FilterValue, 2, 107, 0, 0, // Skip to: 2801
650
/* 2694 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
651
/* 2697 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2706
652
/* 2702 */    MCD_OPC_Decode, 181, 13, 47, // Opcode: L8UI
653
/* 2706 */    MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2715
654
/* 2711 */    MCD_OPC_Decode, 176, 13, 48, // Opcode: L16UI
655
/* 2715 */    MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 2724
656
/* 2720 */    MCD_OPC_Decode, 178, 13, 49, // Opcode: L32I
657
/* 2724 */    MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 2733
658
/* 2729 */    MCD_OPC_Decode, 235, 14, 47, // Opcode: S8I
659
/* 2733 */    MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 2742
660
/* 2738 */    MCD_OPC_Decode, 230, 14, 48, // Opcode: S16I
661
/* 2742 */    MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 2751
662
/* 2747 */    MCD_OPC_Decode, 233, 14, 49, // Opcode: S32I
663
/* 2751 */    MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 2760
664
/* 2756 */    MCD_OPC_Decode, 175, 13, 48, // Opcode: L16SI
665
/* 2760 */    MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 2769
666
/* 2765 */    MCD_OPC_Decode, 207, 13, 50, // Opcode: MOVI
667
/* 2769 */    MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 2778
668
/* 2774 */    MCD_OPC_Decode, 202, 4, 51, // Opcode: ADDI
669
/* 2778 */    MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 2787
670
/* 2783 */    MCD_OPC_Decode, 204, 4, 52, // Opcode: ADDMI
671
/* 2787 */    MCD_OPC_FilterValue, 14, 82, 9, 0, // Skip to: 5178
672
/* 2792 */    MCD_OPC_CheckPredicate, 20, 77, 9, 0, // Skip to: 5178
673
/* 2797 */    MCD_OPC_Decode, 231, 14, 53, // Opcode: S32C1I
674
/* 2801 */    MCD_OPC_FilterValue, 3, 59, 0, 0, // Skip to: 2865
675
/* 2806 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
676
/* 2809 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2823
677
/* 2814 */    MCD_OPC_CheckPredicate, 18, 55, 9, 0, // Skip to: 5178
678
/* 2819 */    MCD_OPC_Decode, 188, 13, 54, // Opcode: LSI
679
/* 2823 */    MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2837
680
/* 2828 */    MCD_OPC_CheckPredicate, 18, 41, 9, 0, // Skip to: 5178
681
/* 2833 */    MCD_OPC_Decode, 249, 14, 54, // Opcode: SSI
682
/* 2837 */    MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2851
683
/* 2842 */    MCD_OPC_CheckPredicate, 18, 27, 9, 0, // Skip to: 5178
684
/* 2847 */    MCD_OPC_Decode, 189, 13, 55, // Opcode: LSIP
685
/* 2851 */    MCD_OPC_FilterValue, 12, 18, 9, 0, // Skip to: 5178
686
/* 2856 */    MCD_OPC_CheckPredicate, 18, 13, 9, 0, // Skip to: 5178
687
/* 2861 */    MCD_OPC_Decode, 250, 14, 56, // Opcode: SSIP
688
/* 2865 */    MCD_OPC_FilterValue, 4, 52, 7, 0, // Skip to: 4714
689
/* 2870 */    MCD_OPC_ExtractField, 15, 9,  // Inst{23-15} ...
690
/* 2873 */    MCD_OPC_FilterValue, 16, 23, 0, 0, // Skip to: 2901
691
/* 2878 */    MCD_OPC_CheckPredicate, 21, 247, 8, 0, // Skip to: 5178
692
/* 2883 */    MCD_OPC_CheckField, 7, 1, 0, 240, 8, 0, // Skip to: 5178
693
/* 2890 */    MCD_OPC_CheckField, 4, 2, 0, 233, 8, 0, // Skip to: 5178
694
/* 2897 */    MCD_OPC_Decode, 252, 13, 57, // Opcode: MULA_DD_LL_LDINC
695
/* 2901 */    MCD_OPC_FilterValue, 18, 23, 0, 0, // Skip to: 2929
696
/* 2906 */    MCD_OPC_CheckPredicate, 21, 219, 8, 0, // Skip to: 5178
697
/* 2911 */    MCD_OPC_CheckField, 7, 1, 0, 212, 8, 0, // Skip to: 5178
698
/* 2918 */    MCD_OPC_CheckField, 4, 2, 0, 205, 8, 0, // Skip to: 5178
699
/* 2925 */    MCD_OPC_Decode, 246, 13, 57, // Opcode: MULA_DD_HL_LDINC
700
/* 2929 */    MCD_OPC_FilterValue, 20, 23, 0, 0, // Skip to: 2957
701
/* 2934 */    MCD_OPC_CheckPredicate, 21, 191, 8, 0, // Skip to: 5178
702
/* 2939 */    MCD_OPC_CheckField, 7, 1, 0, 184, 8, 0, // Skip to: 5178
703
/* 2946 */    MCD_OPC_CheckField, 4, 2, 0, 177, 8, 0, // Skip to: 5178
704
/* 2953 */    MCD_OPC_Decode, 249, 13, 57, // Opcode: MULA_DD_LH_LDINC
705
/* 2957 */    MCD_OPC_FilterValue, 22, 23, 0, 0, // Skip to: 2985
706
/* 2962 */    MCD_OPC_CheckPredicate, 21, 163, 8, 0, // Skip to: 5178
707
/* 2967 */    MCD_OPC_CheckField, 7, 1, 0, 156, 8, 0, // Skip to: 5178
708
/* 2974 */    MCD_OPC_CheckField, 4, 2, 0, 149, 8, 0, // Skip to: 5178
709
/* 2981 */    MCD_OPC_Decode, 243, 13, 57, // Opcode: MULA_DD_HH_LDINC
710
/* 2985 */    MCD_OPC_FilterValue, 48, 23, 0, 0, // Skip to: 3013
711
/* 2990 */    MCD_OPC_CheckPredicate, 21, 135, 8, 0, // Skip to: 5178
712
/* 2995 */    MCD_OPC_CheckField, 7, 1, 0, 128, 8, 0, // Skip to: 5178
713
/* 3002 */    MCD_OPC_CheckField, 4, 2, 0, 121, 8, 0, // Skip to: 5178
714
/* 3009 */    MCD_OPC_Decode, 251, 13, 57, // Opcode: MULA_DD_LL_LDDEC
715
/* 3013 */    MCD_OPC_FilterValue, 50, 23, 0, 0, // Skip to: 3041
716
/* 3018 */    MCD_OPC_CheckPredicate, 21, 107, 8, 0, // Skip to: 5178
717
/* 3023 */    MCD_OPC_CheckField, 7, 1, 0, 100, 8, 0, // Skip to: 5178
718
/* 3030 */    MCD_OPC_CheckField, 4, 2, 0, 93, 8, 0, // Skip to: 5178
719
/* 3037 */    MCD_OPC_Decode, 245, 13, 57, // Opcode: MULA_DD_HL_LDDEC
720
/* 3041 */    MCD_OPC_FilterValue, 52, 23, 0, 0, // Skip to: 3069
721
/* 3046 */    MCD_OPC_CheckPredicate, 21, 79, 8, 0, // Skip to: 5178
722
/* 3051 */    MCD_OPC_CheckField, 7, 1, 0, 72, 8, 0, // Skip to: 5178
723
/* 3058 */    MCD_OPC_CheckField, 4, 2, 0, 65, 8, 0, // Skip to: 5178
724
/* 3065 */    MCD_OPC_Decode, 248, 13, 57, // Opcode: MULA_DD_LH_LDDEC
725
/* 3069 */    MCD_OPC_FilterValue, 54, 23, 0, 0, // Skip to: 3097
726
/* 3074 */    MCD_OPC_CheckPredicate, 21, 51, 8, 0, // Skip to: 5178
727
/* 3079 */    MCD_OPC_CheckField, 7, 1, 0, 44, 8, 0, // Skip to: 5178
728
/* 3086 */    MCD_OPC_CheckField, 4, 2, 0, 37, 8, 0, // Skip to: 5178
729
/* 3093 */    MCD_OPC_Decode, 242, 13, 57, // Opcode: MULA_DD_HH_LDDEC
730
/* 3097 */    MCD_OPC_FilterValue, 72, 23, 0, 0, // Skip to: 3125
731
/* 3102 */    MCD_OPC_CheckPredicate, 21, 23, 8, 0, // Skip to: 5178
732
/* 3107 */    MCD_OPC_CheckField, 7, 7, 0, 16, 8, 0, // Skip to: 5178
733
/* 3114 */    MCD_OPC_CheckField, 4, 2, 0, 9, 8, 0, // Skip to: 5178
734
/* 3121 */    MCD_OPC_Decode, 159, 14, 58, // Opcode: MUL_DD_LL
735
/* 3125 */    MCD_OPC_FilterValue, 74, 23, 0, 0, // Skip to: 3153
736
/* 3130 */    MCD_OPC_CheckPredicate, 21, 251, 7, 0, // Skip to: 5178
737
/* 3135 */    MCD_OPC_CheckField, 7, 7, 0, 244, 7, 0, // Skip to: 5178
738
/* 3142 */    MCD_OPC_CheckField, 4, 2, 0, 237, 7, 0, // Skip to: 5178
739
/* 3149 */    MCD_OPC_Decode, 157, 14, 58, // Opcode: MUL_DD_HL
740
/* 3153 */    MCD_OPC_FilterValue, 76, 23, 0, 0, // Skip to: 3181
741
/* 3158 */    MCD_OPC_CheckPredicate, 21, 223, 7, 0, // Skip to: 5178
742
/* 3163 */    MCD_OPC_CheckField, 7, 7, 0, 216, 7, 0, // Skip to: 5178
743
/* 3170 */    MCD_OPC_CheckField, 4, 2, 0, 209, 7, 0, // Skip to: 5178
744
/* 3177 */    MCD_OPC_Decode, 158, 14, 58, // Opcode: MUL_DD_LH
745
/* 3181 */    MCD_OPC_FilterValue, 78, 23, 0, 0, // Skip to: 3209
746
/* 3186 */    MCD_OPC_CheckPredicate, 21, 195, 7, 0, // Skip to: 5178
747
/* 3191 */    MCD_OPC_CheckField, 7, 7, 0, 188, 7, 0, // Skip to: 5178
748
/* 3198 */    MCD_OPC_CheckField, 4, 2, 0, 181, 7, 0, // Skip to: 5178
749
/* 3205 */    MCD_OPC_Decode, 156, 14, 58, // Opcode: MUL_DD_HH
750
/* 3209 */    MCD_OPC_FilterValue, 80, 23, 0, 0, // Skip to: 3237
751
/* 3214 */    MCD_OPC_CheckPredicate, 21, 167, 7, 0, // Skip to: 5178
752
/* 3219 */    MCD_OPC_CheckField, 7, 7, 0, 160, 7, 0, // Skip to: 5178
753
/* 3226 */    MCD_OPC_CheckField, 4, 2, 0, 153, 7, 0, // Skip to: 5178
754
/* 3233 */    MCD_OPC_Decode, 250, 13, 58, // Opcode: MULA_DD_LL
755
/* 3237 */    MCD_OPC_FilterValue, 82, 23, 0, 0, // Skip to: 3265
756
/* 3242 */    MCD_OPC_CheckPredicate, 21, 139, 7, 0, // Skip to: 5178
757
/* 3247 */    MCD_OPC_CheckField, 7, 7, 0, 132, 7, 0, // Skip to: 5178
758
/* 3254 */    MCD_OPC_CheckField, 4, 2, 0, 125, 7, 0, // Skip to: 5178
759
/* 3261 */    MCD_OPC_Decode, 244, 13, 58, // Opcode: MULA_DD_HL
760
/* 3265 */    MCD_OPC_FilterValue, 84, 23, 0, 0, // Skip to: 3293
761
/* 3270 */    MCD_OPC_CheckPredicate, 21, 111, 7, 0, // Skip to: 5178
762
/* 3275 */    MCD_OPC_CheckField, 7, 7, 0, 104, 7, 0, // Skip to: 5178
763
/* 3282 */    MCD_OPC_CheckField, 4, 2, 0, 97, 7, 0, // Skip to: 5178
764
/* 3289 */    MCD_OPC_Decode, 247, 13, 58, // Opcode: MULA_DD_LH
765
/* 3293 */    MCD_OPC_FilterValue, 86, 23, 0, 0, // Skip to: 3321
766
/* 3298 */    MCD_OPC_CheckPredicate, 21, 83, 7, 0, // Skip to: 5178
767
/* 3303 */    MCD_OPC_CheckField, 7, 7, 0, 76, 7, 0, // Skip to: 5178
768
/* 3310 */    MCD_OPC_CheckField, 4, 2, 0, 69, 7, 0, // Skip to: 5178
769
/* 3317 */    MCD_OPC_Decode, 241, 13, 58, // Opcode: MULA_DD_HH
770
/* 3321 */    MCD_OPC_FilterValue, 88, 23, 0, 0, // Skip to: 3349
771
/* 3326 */    MCD_OPC_CheckPredicate, 21, 55, 7, 0, // Skip to: 5178
772
/* 3331 */    MCD_OPC_CheckField, 7, 7, 0, 48, 7, 0, // Skip to: 5178
773
/* 3338 */    MCD_OPC_CheckField, 4, 2, 0, 41, 7, 0, // Skip to: 5178
774
/* 3345 */    MCD_OPC_Decode, 142, 14, 58, // Opcode: MULS_DD_LL
775
/* 3349 */    MCD_OPC_FilterValue, 90, 23, 0, 0, // Skip to: 3377
776
/* 3354 */    MCD_OPC_CheckPredicate, 21, 27, 7, 0, // Skip to: 5178
777
/* 3359 */    MCD_OPC_CheckField, 7, 7, 0, 20, 7, 0, // Skip to: 5178
778
/* 3366 */    MCD_OPC_CheckField, 4, 2, 0, 13, 7, 0, // Skip to: 5178
779
/* 3373 */    MCD_OPC_Decode, 140, 14, 58, // Opcode: MULS_DD_HL
780
/* 3377 */    MCD_OPC_FilterValue, 92, 23, 0, 0, // Skip to: 3405
781
/* 3382 */    MCD_OPC_CheckPredicate, 21, 255, 6, 0, // Skip to: 5178
782
/* 3387 */    MCD_OPC_CheckField, 7, 7, 0, 248, 6, 0, // Skip to: 5178
783
/* 3394 */    MCD_OPC_CheckField, 4, 2, 0, 241, 6, 0, // Skip to: 5178
784
/* 3401 */    MCD_OPC_Decode, 141, 14, 58, // Opcode: MULS_DD_LH
785
/* 3405 */    MCD_OPC_FilterValue, 94, 23, 0, 0, // Skip to: 3433
786
/* 3410 */    MCD_OPC_CheckPredicate, 21, 227, 6, 0, // Skip to: 5178
787
/* 3415 */    MCD_OPC_CheckField, 7, 7, 0, 220, 6, 0, // Skip to: 5178
788
/* 3422 */    MCD_OPC_CheckField, 4, 2, 0, 213, 6, 0, // Skip to: 5178
789
/* 3429 */    MCD_OPC_Decode, 139, 14, 58, // Opcode: MULS_DD_HH
790
/* 3433 */    MCD_OPC_FilterValue, 104, 30, 0, 0, // Skip to: 3468
791
/* 3438 */    MCD_OPC_CheckPredicate, 21, 199, 6, 0, // Skip to: 5178
792
/* 3443 */    MCD_OPC_CheckField, 12, 3, 0, 192, 6, 0, // Skip to: 5178
793
/* 3450 */    MCD_OPC_CheckField, 7, 1, 0, 185, 6, 0, // Skip to: 5178
794
/* 3457 */    MCD_OPC_CheckField, 4, 2, 0, 178, 6, 0, // Skip to: 5178
795
/* 3464 */    MCD_OPC_Decode, 151, 14, 59, // Opcode: MUL_AD_LL
796
/* 3468 */    MCD_OPC_FilterValue, 106, 30, 0, 0, // Skip to: 3503
797
/* 3473 */    MCD_OPC_CheckPredicate, 21, 164, 6, 0, // Skip to: 5178
798
/* 3478 */    MCD_OPC_CheckField, 12, 3, 0, 157, 6, 0, // Skip to: 5178
799
/* 3485 */    MCD_OPC_CheckField, 7, 1, 0, 150, 6, 0, // Skip to: 5178
800
/* 3492 */    MCD_OPC_CheckField, 4, 2, 0, 143, 6, 0, // Skip to: 5178
801
/* 3499 */    MCD_OPC_Decode, 149, 14, 59, // Opcode: MUL_AD_HL
802
/* 3503 */    MCD_OPC_FilterValue, 108, 30, 0, 0, // Skip to: 3538
803
/* 3508 */    MCD_OPC_CheckPredicate, 21, 129, 6, 0, // Skip to: 5178
804
/* 3513 */    MCD_OPC_CheckField, 12, 3, 0, 122, 6, 0, // Skip to: 5178
805
/* 3520 */    MCD_OPC_CheckField, 7, 1, 0, 115, 6, 0, // Skip to: 5178
806
/* 3527 */    MCD_OPC_CheckField, 4, 2, 0, 108, 6, 0, // Skip to: 5178
807
/* 3534 */    MCD_OPC_Decode, 150, 14, 59, // Opcode: MUL_AD_LH
808
/* 3538 */    MCD_OPC_FilterValue, 110, 30, 0, 0, // Skip to: 3573
809
/* 3543 */    MCD_OPC_CheckPredicate, 21, 94, 6, 0, // Skip to: 5178
810
/* 3548 */    MCD_OPC_CheckField, 12, 3, 0, 87, 6, 0, // Skip to: 5178
811
/* 3555 */    MCD_OPC_CheckField, 7, 1, 0, 80, 6, 0, // Skip to: 5178
812
/* 3562 */    MCD_OPC_CheckField, 4, 2, 0, 73, 6, 0, // Skip to: 5178
813
/* 3569 */    MCD_OPC_Decode, 148, 14, 59, // Opcode: MUL_AD_HH
814
/* 3573 */    MCD_OPC_FilterValue, 112, 30, 0, 0, // Skip to: 3608
815
/* 3578 */    MCD_OPC_CheckPredicate, 21, 59, 6, 0, // Skip to: 5178
816
/* 3583 */    MCD_OPC_CheckField, 12, 3, 0, 52, 6, 0, // Skip to: 5178
817
/* 3590 */    MCD_OPC_CheckField, 7, 1, 0, 45, 6, 0, // Skip to: 5178
818
/* 3597 */    MCD_OPC_CheckField, 4, 2, 0, 38, 6, 0, // Skip to: 5178
819
/* 3604 */    MCD_OPC_Decode, 228, 13, 59, // Opcode: MULA_AD_LL
820
/* 3608 */    MCD_OPC_FilterValue, 114, 30, 0, 0, // Skip to: 3643
821
/* 3613 */    MCD_OPC_CheckPredicate, 21, 24, 6, 0, // Skip to: 5178
822
/* 3618 */    MCD_OPC_CheckField, 12, 3, 0, 17, 6, 0, // Skip to: 5178
823
/* 3625 */    MCD_OPC_CheckField, 7, 1, 0, 10, 6, 0, // Skip to: 5178
824
/* 3632 */    MCD_OPC_CheckField, 4, 2, 0, 3, 6, 0, // Skip to: 5178
825
/* 3639 */    MCD_OPC_Decode, 226, 13, 59, // Opcode: MULA_AD_HL
826
/* 3643 */    MCD_OPC_FilterValue, 116, 30, 0, 0, // Skip to: 3678
827
/* 3648 */    MCD_OPC_CheckPredicate, 21, 245, 5, 0, // Skip to: 5178
828
/* 3653 */    MCD_OPC_CheckField, 12, 3, 0, 238, 5, 0, // Skip to: 5178
829
/* 3660 */    MCD_OPC_CheckField, 7, 1, 0, 231, 5, 0, // Skip to: 5178
830
/* 3667 */    MCD_OPC_CheckField, 4, 2, 0, 224, 5, 0, // Skip to: 5178
831
/* 3674 */    MCD_OPC_Decode, 227, 13, 59, // Opcode: MULA_AD_LH
832
/* 3678 */    MCD_OPC_FilterValue, 118, 30, 0, 0, // Skip to: 3713
833
/* 3683 */    MCD_OPC_CheckPredicate, 21, 210, 5, 0, // Skip to: 5178
834
/* 3688 */    MCD_OPC_CheckField, 12, 3, 0, 203, 5, 0, // Skip to: 5178
835
/* 3695 */    MCD_OPC_CheckField, 7, 1, 0, 196, 5, 0, // Skip to: 5178
836
/* 3702 */    MCD_OPC_CheckField, 4, 2, 0, 189, 5, 0, // Skip to: 5178
837
/* 3709 */    MCD_OPC_Decode, 225, 13, 59, // Opcode: MULA_AD_HH
838
/* 3713 */    MCD_OPC_FilterValue, 120, 30, 0, 0, // Skip to: 3748
839
/* 3718 */    MCD_OPC_CheckPredicate, 21, 175, 5, 0, // Skip to: 5178
840
/* 3723 */    MCD_OPC_CheckField, 12, 3, 0, 168, 5, 0, // Skip to: 5178
841
/* 3730 */    MCD_OPC_CheckField, 7, 1, 0, 161, 5, 0, // Skip to: 5178
842
/* 3737 */    MCD_OPC_CheckField, 4, 2, 0, 154, 5, 0, // Skip to: 5178
843
/* 3744 */    MCD_OPC_Decode, 134, 14, 59, // Opcode: MULS_AD_LL
844
/* 3748 */    MCD_OPC_FilterValue, 122, 30, 0, 0, // Skip to: 3783
845
/* 3753 */    MCD_OPC_CheckPredicate, 21, 140, 5, 0, // Skip to: 5178
846
/* 3758 */    MCD_OPC_CheckField, 12, 3, 0, 133, 5, 0, // Skip to: 5178
847
/* 3765 */    MCD_OPC_CheckField, 7, 1, 0, 126, 5, 0, // Skip to: 5178
848
/* 3772 */    MCD_OPC_CheckField, 4, 2, 0, 119, 5, 0, // Skip to: 5178
849
/* 3779 */    MCD_OPC_Decode, 132, 14, 59, // Opcode: MULS_AD_HL
850
/* 3783 */    MCD_OPC_FilterValue, 124, 30, 0, 0, // Skip to: 3818
851
/* 3788 */    MCD_OPC_CheckPredicate, 21, 105, 5, 0, // Skip to: 5178
852
/* 3793 */    MCD_OPC_CheckField, 12, 3, 0, 98, 5, 0, // Skip to: 5178
853
/* 3800 */    MCD_OPC_CheckField, 7, 1, 0, 91, 5, 0, // Skip to: 5178
854
/* 3807 */    MCD_OPC_CheckField, 4, 2, 0, 84, 5, 0, // Skip to: 5178
855
/* 3814 */    MCD_OPC_Decode, 133, 14, 59, // Opcode: MULS_AD_LH
856
/* 3818 */    MCD_OPC_FilterValue, 126, 30, 0, 0, // Skip to: 3853
857
/* 3823 */    MCD_OPC_CheckPredicate, 21, 70, 5, 0, // Skip to: 5178
858
/* 3828 */    MCD_OPC_CheckField, 12, 3, 0, 63, 5, 0, // Skip to: 5178
859
/* 3835 */    MCD_OPC_CheckField, 7, 1, 0, 56, 5, 0, // Skip to: 5178
860
/* 3842 */    MCD_OPC_CheckField, 4, 2, 0, 49, 5, 0, // Skip to: 5178
861
/* 3849 */    MCD_OPC_Decode, 131, 14, 59, // Opcode: MULS_AD_HH
862
/* 3853 */    MCD_OPC_FilterValue, 144, 1, 9, 0, 0, // Skip to: 3868
863
/* 3859 */    MCD_OPC_CheckPredicate, 21, 34, 5, 0, // Skip to: 5178
864
/* 3864 */    MCD_OPC_Decode, 240, 13, 60, // Opcode: MULA_DA_LL_LDINC
865
/* 3868 */    MCD_OPC_FilterValue, 146, 1, 9, 0, 0, // Skip to: 3883
866
/* 3874 */    MCD_OPC_CheckPredicate, 21, 19, 5, 0, // Skip to: 5178
867
/* 3879 */    MCD_OPC_Decode, 234, 13, 60, // Opcode: MULA_DA_HL_LDINC
868
/* 3883 */    MCD_OPC_FilterValue, 148, 1, 9, 0, 0, // Skip to: 3898
869
/* 3889 */    MCD_OPC_CheckPredicate, 21, 4, 5, 0, // Skip to: 5178
870
/* 3894 */    MCD_OPC_Decode, 237, 13, 60, // Opcode: MULA_DA_LH_LDINC
871
/* 3898 */    MCD_OPC_FilterValue, 150, 1, 9, 0, 0, // Skip to: 3913
872
/* 3904 */    MCD_OPC_CheckPredicate, 21, 245, 4, 0, // Skip to: 5178
873
/* 3909 */    MCD_OPC_Decode, 231, 13, 60, // Opcode: MULA_DA_HH_LDINC
874
/* 3913 */    MCD_OPC_FilterValue, 176, 1, 9, 0, 0, // Skip to: 3928
875
/* 3919 */    MCD_OPC_CheckPredicate, 21, 230, 4, 0, // Skip to: 5178
876
/* 3924 */    MCD_OPC_Decode, 239, 13, 61, // Opcode: MULA_DA_LL_LDDEC
877
/* 3928 */    MCD_OPC_FilterValue, 178, 1, 9, 0, 0, // Skip to: 3943
878
/* 3934 */    MCD_OPC_CheckPredicate, 21, 215, 4, 0, // Skip to: 5178
879
/* 3939 */    MCD_OPC_Decode, 233, 13, 61, // Opcode: MULA_DA_HL_LDDEC
880
/* 3943 */    MCD_OPC_FilterValue, 180, 1, 9, 0, 0, // Skip to: 3958
881
/* 3949 */    MCD_OPC_CheckPredicate, 21, 200, 4, 0, // Skip to: 5178
882
/* 3954 */    MCD_OPC_Decode, 236, 13, 61, // Opcode: MULA_DA_LH_LDDEC
883
/* 3958 */    MCD_OPC_FilterValue, 182, 1, 9, 0, 0, // Skip to: 3973
884
/* 3964 */    MCD_OPC_CheckPredicate, 21, 185, 4, 0, // Skip to: 5178
885
/* 3969 */    MCD_OPC_Decode, 230, 13, 61, // Opcode: MULA_DA_HH_LDDEC
886
/* 3973 */    MCD_OPC_FilterValue, 200, 1, 16, 0, 0, // Skip to: 3995
887
/* 3979 */    MCD_OPC_CheckPredicate, 21, 170, 4, 0, // Skip to: 5178
888
/* 3984 */    MCD_OPC_CheckField, 8, 6, 0, 163, 4, 0, // Skip to: 5178
889
/* 3991 */    MCD_OPC_Decode, 155, 14, 62, // Opcode: MUL_DA_LL
890
/* 3995 */    MCD_OPC_FilterValue, 202, 1, 38, 0, 0, // Skip to: 4039
891
/* 4001 */    MCD_OPC_ExtractField, 8, 6,  // Inst{13-8} ...
892
/* 4004 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4018
893
/* 4009 */    MCD_OPC_CheckPredicate, 21, 140, 4, 0, // Skip to: 5178
894
/* 4014 */    MCD_OPC_Decode, 153, 14, 62, // Opcode: MUL_DA_HL
895
/* 4018 */    MCD_OPC_FilterValue, 8, 131, 4, 0, // Skip to: 5178
896
/* 4023 */    MCD_OPC_CheckPredicate, 22, 126, 4, 0, // Skip to: 5178
897
/* 4028 */    MCD_OPC_CheckField, 14, 1, 0, 119, 4, 0, // Skip to: 5178
898
/* 4035 */    MCD_OPC_Decode, 216, 11, 25, // Opcode: EE_GET_GPIO_IN
899
/* 4039 */    MCD_OPC_FilterValue, 204, 1, 16, 0, 0, // Skip to: 4061
900
/* 4045 */    MCD_OPC_CheckPredicate, 21, 104, 4, 0, // Skip to: 5178
901
/* 4050 */    MCD_OPC_CheckField, 8, 6, 0, 97, 4, 0, // Skip to: 5178
902
/* 4057 */    MCD_OPC_Decode, 154, 14, 62, // Opcode: MUL_DA_LH
903
/* 4061 */    MCD_OPC_FilterValue, 206, 1, 16, 0, 0, // Skip to: 4083
904
/* 4067 */    MCD_OPC_CheckPredicate, 21, 82, 4, 0, // Skip to: 5178
905
/* 4072 */    MCD_OPC_CheckField, 8, 6, 0, 75, 4, 0, // Skip to: 5178
906
/* 4079 */    MCD_OPC_Decode, 152, 14, 62, // Opcode: MUL_DA_HH
907
/* 4083 */    MCD_OPC_FilterValue, 208, 1, 16, 0, 0, // Skip to: 4105
908
/* 4089 */    MCD_OPC_CheckPredicate, 21, 60, 4, 0, // Skip to: 5178
909
/* 4094 */    MCD_OPC_CheckField, 8, 6, 0, 53, 4, 0, // Skip to: 5178
910
/* 4101 */    MCD_OPC_Decode, 238, 13, 62, // Opcode: MULA_DA_LL
911
/* 4105 */    MCD_OPC_FilterValue, 210, 1, 16, 0, 0, // Skip to: 4127
912
/* 4111 */    MCD_OPC_CheckPredicate, 21, 38, 4, 0, // Skip to: 5178
913
/* 4116 */    MCD_OPC_CheckField, 8, 6, 0, 31, 4, 0, // Skip to: 5178
914
/* 4123 */    MCD_OPC_Decode, 232, 13, 62, // Opcode: MULA_DA_HL
915
/* 4127 */    MCD_OPC_FilterValue, 212, 1, 16, 0, 0, // Skip to: 4149
916
/* 4133 */    MCD_OPC_CheckPredicate, 21, 16, 4, 0, // Skip to: 5178
917
/* 4138 */    MCD_OPC_CheckField, 8, 6, 0, 9, 4, 0, // Skip to: 5178
918
/* 4145 */    MCD_OPC_Decode, 235, 13, 62, // Opcode: MULA_DA_LH
919
/* 4149 */    MCD_OPC_FilterValue, 214, 1, 16, 0, 0, // Skip to: 4171
920
/* 4155 */    MCD_OPC_CheckPredicate, 21, 250, 3, 0, // Skip to: 5178
921
/* 4160 */    MCD_OPC_CheckField, 8, 6, 0, 243, 3, 0, // Skip to: 5178
922
/* 4167 */    MCD_OPC_Decode, 229, 13, 62, // Opcode: MULA_DA_HH
923
/* 4171 */    MCD_OPC_FilterValue, 216, 1, 16, 0, 0, // Skip to: 4193
924
/* 4177 */    MCD_OPC_CheckPredicate, 21, 228, 3, 0, // Skip to: 5178
925
/* 4182 */    MCD_OPC_CheckField, 8, 6, 0, 221, 3, 0, // Skip to: 5178
926
/* 4189 */    MCD_OPC_Decode, 138, 14, 62, // Opcode: MULS_DA_LL
927
/* 4193 */    MCD_OPC_FilterValue, 218, 1, 16, 0, 0, // Skip to: 4215
928
/* 4199 */    MCD_OPC_CheckPredicate, 21, 206, 3, 0, // Skip to: 5178
929
/* 4204 */    MCD_OPC_CheckField, 8, 6, 0, 199, 3, 0, // Skip to: 5178
930
/* 4211 */    MCD_OPC_Decode, 136, 14, 62, // Opcode: MULS_DA_HL
931
/* 4215 */    MCD_OPC_FilterValue, 220, 1, 16, 0, 0, // Skip to: 4237
932
/* 4221 */    MCD_OPC_CheckPredicate, 21, 184, 3, 0, // Skip to: 5178
933
/* 4226 */    MCD_OPC_CheckField, 8, 6, 0, 177, 3, 0, // Skip to: 5178
934
/* 4233 */    MCD_OPC_Decode, 137, 14, 62, // Opcode: MULS_DA_LH
935
/* 4237 */    MCD_OPC_FilterValue, 222, 1, 16, 0, 0, // Skip to: 4259
936
/* 4243 */    MCD_OPC_CheckPredicate, 21, 162, 3, 0, // Skip to: 5178
937
/* 4248 */    MCD_OPC_CheckField, 8, 6, 0, 155, 3, 0, // Skip to: 5178
938
/* 4255 */    MCD_OPC_Decode, 135, 14, 62, // Opcode: MULS_DA_HH
939
/* 4259 */    MCD_OPC_FilterValue, 224, 1, 16, 0, 0, // Skip to: 4281
940
/* 4265 */    MCD_OPC_CheckPredicate, 21, 140, 3, 0, // Skip to: 5178
941
/* 4270 */    MCD_OPC_CheckField, 12, 3, 0, 133, 3, 0, // Skip to: 5178
942
/* 4277 */    MCD_OPC_Decode, 141, 15, 29, // Opcode: UMUL_AA_LL
943
/* 4281 */    MCD_OPC_FilterValue, 226, 1, 16, 0, 0, // Skip to: 4303
944
/* 4287 */    MCD_OPC_CheckPredicate, 21, 118, 3, 0, // Skip to: 5178
945
/* 4292 */    MCD_OPC_CheckField, 12, 3, 0, 111, 3, 0, // Skip to: 5178
946
/* 4299 */    MCD_OPC_Decode, 139, 15, 29, // Opcode: UMUL_AA_HL
947
/* 4303 */    MCD_OPC_FilterValue, 228, 1, 31, 0, 0, // Skip to: 4340
948
/* 4309 */    MCD_OPC_ExtractField, 12, 3,  // Inst{14-12} ...
949
/* 4312 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4326
950
/* 4317 */    MCD_OPC_CheckPredicate, 21, 88, 3, 0, // Skip to: 5178
951
/* 4322 */    MCD_OPC_Decode, 140, 15, 29, // Opcode: UMUL_AA_LH
952
/* 4326 */    MCD_OPC_FilterValue, 4, 79, 3, 0, // Skip to: 5178
953
/* 4331 */    MCD_OPC_CheckPredicate, 22, 74, 3, 0, // Skip to: 5178
954
/* 4336 */    MCD_OPC_Decode, 157, 13, 5, // Opcode: EE_WR_MASK_GPIO_OUT
955
/* 4340 */    MCD_OPC_FilterValue, 230, 1, 16, 0, 0, // Skip to: 4362
956
/* 4346 */    MCD_OPC_CheckPredicate, 21, 59, 3, 0, // Skip to: 5178
957
/* 4351 */    MCD_OPC_CheckField, 12, 3, 0, 52, 3, 0, // Skip to: 5178
958
/* 4358 */    MCD_OPC_Decode, 138, 15, 29, // Opcode: UMUL_AA_HH
959
/* 4362 */    MCD_OPC_FilterValue, 232, 1, 16, 0, 0, // Skip to: 4384
960
/* 4368 */    MCD_OPC_CheckPredicate, 21, 37, 3, 0, // Skip to: 5178
961
/* 4373 */    MCD_OPC_CheckField, 12, 3, 0, 30, 3, 0, // Skip to: 5178
962
/* 4380 */    MCD_OPC_Decode, 147, 14, 29, // Opcode: MUL_AA_LL
963
/* 4384 */    MCD_OPC_FilterValue, 234, 1, 31, 0, 0, // Skip to: 4421
964
/* 4390 */    MCD_OPC_ExtractField, 12, 3,  // Inst{14-12} ...
965
/* 4393 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4407
966
/* 4398 */    MCD_OPC_CheckPredicate, 21, 7, 3, 0, // Skip to: 5178
967
/* 4403 */    MCD_OPC_Decode, 145, 14, 29, // Opcode: MUL_AA_HL
968
/* 4407 */    MCD_OPC_FilterValue, 4, 254, 2, 0, // Skip to: 5178
969
/* 4412 */    MCD_OPC_CheckPredicate, 22, 249, 2, 0, // Skip to: 5178
970
/* 4417 */    MCD_OPC_Decode, 246, 11, 28, // Opcode: EE_SET_BIT_GPIO_OUT
971
/* 4421 */    MCD_OPC_FilterValue, 236, 1, 31, 0, 0, // Skip to: 4458
972
/* 4427 */    MCD_OPC_ExtractField, 12, 3,  // Inst{14-12} ...
973
/* 4430 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4444
974
/* 4435 */    MCD_OPC_CheckPredicate, 21, 226, 2, 0, // Skip to: 5178
975
/* 4440 */    MCD_OPC_Decode, 146, 14, 29, // Opcode: MUL_AA_LH
976
/* 4444 */    MCD_OPC_FilterValue, 4, 217, 2, 0, // Skip to: 5178
977
/* 4449 */    MCD_OPC_CheckPredicate, 22, 212, 2, 0, // Skip to: 5178
978
/* 4454 */    MCD_OPC_Decode, 203, 11, 28, // Opcode: EE_CLR_BIT_GPIO_OUT
979
/* 4458 */    MCD_OPC_FilterValue, 238, 1, 16, 0, 0, // Skip to: 4480
980
/* 4464 */    MCD_OPC_CheckPredicate, 21, 197, 2, 0, // Skip to: 5178
981
/* 4469 */    MCD_OPC_CheckField, 12, 3, 0, 190, 2, 0, // Skip to: 5178
982
/* 4476 */    MCD_OPC_Decode, 144, 14, 29, // Opcode: MUL_AA_HH
983
/* 4480 */    MCD_OPC_FilterValue, 240, 1, 16, 0, 0, // Skip to: 4502
984
/* 4486 */    MCD_OPC_CheckPredicate, 21, 175, 2, 0, // Skip to: 5178
985
/* 4491 */    MCD_OPC_CheckField, 12, 3, 0, 168, 2, 0, // Skip to: 5178
986
/* 4498 */    MCD_OPC_Decode, 224, 13, 29, // Opcode: MULA_AA_LL
987
/* 4502 */    MCD_OPC_FilterValue, 242, 1, 16, 0, 0, // Skip to: 4524
988
/* 4508 */    MCD_OPC_CheckPredicate, 21, 153, 2, 0, // Skip to: 5178
989
/* 4513 */    MCD_OPC_CheckField, 12, 3, 0, 146, 2, 0, // Skip to: 5178
990
/* 4520 */    MCD_OPC_Decode, 222, 13, 29, // Opcode: MULA_AA_HL
991
/* 4524 */    MCD_OPC_FilterValue, 244, 1, 16, 0, 0, // Skip to: 4546
992
/* 4530 */    MCD_OPC_CheckPredicate, 21, 131, 2, 0, // Skip to: 5178
993
/* 4535 */    MCD_OPC_CheckField, 12, 3, 0, 124, 2, 0, // Skip to: 5178
994
/* 4542 */    MCD_OPC_Decode, 223, 13, 29, // Opcode: MULA_AA_LH
995
/* 4546 */    MCD_OPC_FilterValue, 246, 1, 16, 0, 0, // Skip to: 4568
996
/* 4552 */    MCD_OPC_CheckPredicate, 21, 109, 2, 0, // Skip to: 5178
997
/* 4557 */    MCD_OPC_CheckField, 12, 3, 0, 102, 2, 0, // Skip to: 5178
998
/* 4564 */    MCD_OPC_Decode, 221, 13, 29, // Opcode: MULA_AA_HH
999
/* 4568 */    MCD_OPC_FilterValue, 248, 1, 16, 0, 0, // Skip to: 4590
1000
/* 4574 */    MCD_OPC_CheckPredicate, 21, 87, 2, 0, // Skip to: 5178
1001
/* 4579 */    MCD_OPC_CheckField, 12, 3, 0, 80, 2, 0, // Skip to: 5178
1002
/* 4586 */    MCD_OPC_Decode, 130, 14, 29, // Opcode: MULS_AA_LL
1003
/* 4590 */    MCD_OPC_FilterValue, 250, 1, 16, 0, 0, // Skip to: 4612
1004
/* 4596 */    MCD_OPC_CheckPredicate, 21, 65, 2, 0, // Skip to: 5178
1005
/* 4601 */    MCD_OPC_CheckField, 12, 3, 0, 58, 2, 0, // Skip to: 5178
1006
/* 4608 */    MCD_OPC_Decode, 128, 14, 29, // Opcode: MULS_AA_HL
1007
/* 4612 */    MCD_OPC_FilterValue, 252, 1, 16, 0, 0, // Skip to: 4634
1008
/* 4618 */    MCD_OPC_CheckPredicate, 21, 43, 2, 0, // Skip to: 5178
1009
/* 4623 */    MCD_OPC_CheckField, 12, 3, 0, 36, 2, 0, // Skip to: 5178
1010
/* 4630 */    MCD_OPC_Decode, 129, 14, 29, // Opcode: MULS_AA_LH
1011
/* 4634 */    MCD_OPC_FilterValue, 254, 1, 16, 0, 0, // Skip to: 4656
1012
/* 4640 */    MCD_OPC_CheckPredicate, 21, 21, 2, 0, // Skip to: 5178
1013
/* 4645 */    MCD_OPC_CheckField, 12, 3, 0, 14, 2, 0, // Skip to: 5178
1014
/* 4652 */    MCD_OPC_Decode, 255, 13, 29, // Opcode: MULS_AA_HH
1015
/* 4656 */    MCD_OPC_FilterValue, 128, 2, 23, 0, 0, // Skip to: 4685
1016
/* 4662 */    MCD_OPC_CheckPredicate, 21, 255, 1, 0, // Skip to: 5178
1017
/* 4667 */    MCD_OPC_CheckField, 14, 1, 0, 248, 1, 0, // Skip to: 5178
1018
/* 4674 */    MCD_OPC_CheckField, 4, 4, 0, 241, 1, 0, // Skip to: 5178
1019
/* 4681 */    MCD_OPC_Decode, 183, 13, 63, // Opcode: LDINC
1020
/* 4685 */    MCD_OPC_FilterValue, 160, 2, 231, 1, 0, // Skip to: 5178
1021
/* 4691 */    MCD_OPC_CheckPredicate, 21, 226, 1, 0, // Skip to: 5178
1022
/* 4696 */    MCD_OPC_CheckField, 14, 1, 0, 219, 1, 0, // Skip to: 5178
1023
/* 4703 */    MCD_OPC_CheckField, 4, 4, 0, 212, 1, 0, // Skip to: 5178
1024
/* 4710 */    MCD_OPC_Decode, 182, 13, 63, // Opcode: LDDEC
1025
/* 4714 */    MCD_OPC_FilterValue, 5, 54, 0, 0, // Skip to: 4773
1026
/* 4719 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
1027
/* 4722 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4731
1028
/* 4727 */    MCD_OPC_Decode, 186, 11, 64, // Opcode: CALL0
1029
/* 4731 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4745
1030
/* 4736 */    MCD_OPC_CheckPredicate, 3, 181, 1, 0, // Skip to: 5178
1031
/* 4741 */    MCD_OPC_Decode, 188, 11, 64, // Opcode: CALL4
1032
/* 4745 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 4759
1033
/* 4750 */    MCD_OPC_CheckPredicate, 3, 167, 1, 0, // Skip to: 5178
1034
/* 4755 */    MCD_OPC_Decode, 189, 11, 64, // Opcode: CALL8
1035
/* 4759 */    MCD_OPC_FilterValue, 3, 158, 1, 0, // Skip to: 5178
1036
/* 4764 */    MCD_OPC_CheckPredicate, 3, 153, 1, 0, // Skip to: 5178
1037
/* 4769 */    MCD_OPC_Decode, 187, 11, 64, // Opcode: CALL12
1038
/* 4773 */    MCD_OPC_FilterValue, 6, 218, 0, 0, // Skip to: 4996
1039
/* 4778 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
1040
/* 4781 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4790
1041
/* 4786 */    MCD_OPC_Decode, 173, 13, 65, // Opcode: J
1042
/* 4790 */    MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 4834
1043
/* 4795 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
1044
/* 4798 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4807
1045
/* 4803 */    MCD_OPC_Decode, 166, 11, 66, // Opcode: BEQZ
1046
/* 4807 */    MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 4816
1047
/* 4812 */    MCD_OPC_Decode, 181, 11, 66, // Opcode: BNEZ
1048
/* 4816 */    MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 4825
1049
/* 4821 */    MCD_OPC_Decode, 177, 11, 66, // Opcode: BLTZ
1050
/* 4825 */    MCD_OPC_FilterValue, 3, 92, 1, 0, // Skip to: 5178
1051
/* 4830 */    MCD_OPC_Decode, 172, 11, 66, // Opcode: BGEZ
1052
/* 4834 */    MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 4878
1053
/* 4839 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
1054
/* 4842 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4851
1055
/* 4847 */    MCD_OPC_Decode, 165, 11, 67, // Opcode: BEQI
1056
/* 4851 */    MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 4860
1057
/* 4856 */    MCD_OPC_Decode, 180, 11, 67, // Opcode: BNEI
1058
/* 4860 */    MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 4869
1059
/* 4865 */    MCD_OPC_Decode, 174, 11, 67, // Opcode: BLTI
1060
/* 4869 */    MCD_OPC_FilterValue, 3, 48, 1, 0, // Skip to: 5178
1061
/* 4874 */    MCD_OPC_Decode, 169, 11, 67, // Opcode: BGEI
1062
/* 4878 */    MCD_OPC_FilterValue, 3, 39, 1, 0, // Skip to: 5178
1063
/* 4883 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
1064
/* 4886 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4900
1065
/* 4891 */    MCD_OPC_CheckPredicate, 3, 26, 1, 0, // Skip to: 5178
1066
/* 4896 */    MCD_OPC_Decode, 162, 13, 68, // Opcode: ENTRY
1067
/* 4900 */    MCD_OPC_FilterValue, 1, 73, 0, 0, // Skip to: 4978
1068
/* 4905 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
1069
/* 4908 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4922
1070
/* 4913 */    MCD_OPC_CheckPredicate, 7, 4, 1, 0, // Skip to: 5178
1071
/* 4918 */    MCD_OPC_Decode, 167, 11, 69, // Opcode: BF
1072
/* 4922 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4936
1073
/* 4927 */    MCD_OPC_CheckPredicate, 7, 246, 0, 0, // Skip to: 5178
1074
/* 4932 */    MCD_OPC_Decode, 185, 11, 69, // Opcode: BT
1075
/* 4936 */    MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 4950
1076
/* 4941 */    MCD_OPC_CheckPredicate, 23, 232, 0, 0, // Skip to: 5178
1077
/* 4946 */    MCD_OPC_Decode, 185, 13, 70, // Opcode: LOOP
1078
/* 4950 */    MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 4964
1079
/* 4955 */    MCD_OPC_CheckPredicate, 23, 218, 0, 0, // Skip to: 5178
1080
/* 4960 */    MCD_OPC_Decode, 187, 13, 70, // Opcode: LOOPNEZ
1081
/* 4964 */    MCD_OPC_FilterValue, 10, 209, 0, 0, // Skip to: 5178
1082
/* 4969 */    MCD_OPC_CheckPredicate, 23, 204, 0, 0, // Skip to: 5178
1083
/* 4974 */    MCD_OPC_Decode, 186, 13, 70, // Opcode: LOOPGTZ
1084
/* 4978 */    MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 4987
1085
/* 4983 */    MCD_OPC_Decode, 176, 11, 71, // Opcode: BLTUI
1086
/* 4987 */    MCD_OPC_FilterValue, 3, 186, 0, 0, // Skip to: 5178
1087
/* 4992 */    MCD_OPC_Decode, 171, 11, 71, // Opcode: BGEUI
1088
/* 4996 */    MCD_OPC_FilterValue, 7, 177, 0, 0, // Skip to: 5178
1089
/* 5001 */    MCD_OPC_ExtractField, 13, 3,  // Inst{15-13} ...
1090
/* 5004 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 5030
1091
/* 5009 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
1092
/* 5012 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5021
1093
/* 5017 */    MCD_OPC_Decode, 182, 11, 72, // Opcode: BNONE
1094
/* 5021 */    MCD_OPC_FilterValue, 1, 152, 0, 0, // Skip to: 5178
1095
/* 5026 */    MCD_OPC_Decode, 164, 11, 72, // Opcode: BEQ
1096
/* 5030 */    MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 5056
1097
/* 5035 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
1098
/* 5038 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5047
1099
/* 5043 */    MCD_OPC_Decode, 173, 11, 72, // Opcode: BLT
1100
/* 5047 */    MCD_OPC_FilterValue, 1, 126, 0, 0, // Skip to: 5178
1101
/* 5052 */    MCD_OPC_Decode, 175, 11, 72, // Opcode: BLTU
1102
/* 5056 */    MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 5082
1103
/* 5061 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
1104
/* 5064 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5073
1105
/* 5069 */    MCD_OPC_Decode, 158, 11, 72, // Opcode: BALL
1106
/* 5073 */    MCD_OPC_FilterValue, 1, 100, 0, 0, // Skip to: 5178
1107
/* 5078 */    MCD_OPC_Decode, 160, 11, 72, // Opcode: BBC
1108
/* 5082 */    MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 5091
1109
/* 5087 */    MCD_OPC_Decode, 161, 11, 73, // Opcode: BBCI
1110
/* 5091 */    MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 5117
1111
/* 5096 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
1112
/* 5099 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5108
1113
/* 5104 */    MCD_OPC_Decode, 159, 11, 72, // Opcode: BANY
1114
/* 5108 */    MCD_OPC_FilterValue, 1, 65, 0, 0, // Skip to: 5178
1115
/* 5113 */    MCD_OPC_Decode, 179, 11, 72, // Opcode: BNE
1116
/* 5117 */    MCD_OPC_FilterValue, 5, 21, 0, 0, // Skip to: 5143
1117
/* 5122 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
1118
/* 5125 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5134
1119
/* 5130 */    MCD_OPC_Decode, 168, 11, 72, // Opcode: BGE
1120
/* 5134 */    MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 5178
1121
/* 5139 */    MCD_OPC_Decode, 170, 11, 72, // Opcode: BGEU
1122
/* 5143 */    MCD_OPC_FilterValue, 6, 21, 0, 0, // Skip to: 5169
1123
/* 5148 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
1124
/* 5151 */    MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5160
1125
/* 5156 */    MCD_OPC_Decode, 178, 11, 72, // Opcode: BNALL
1126
/* 5160 */    MCD_OPC_FilterValue, 1, 13, 0, 0, // Skip to: 5178
1127
/* 5165 */    MCD_OPC_Decode, 162, 11, 72, // Opcode: BBS
1128
/* 5169 */    MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 5178
1129
/* 5174 */    MCD_OPC_Decode, 163, 11, 73, // Opcode: BBSI
1130
/* 5178 */    MCD_OPC_Fail,
1131
  0
1132
};
1133
1134
static const uint8_t DecoderTableESP32S324[] = {
1135
/* 0 */       MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
1136
/* 3 */       MCD_OPC_FilterValue, 0, 108, 0, 0, // Skip to: 116
1137
/* 8 */       MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
1138
/* 11 */      MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 46
1139
/* 16 */      MCD_OPC_CheckPredicate, 22, 64, 16, 0, // Skip to: 4181
1140
/* 21 */      MCD_OPC_CheckField, 23, 1, 0, 57, 16, 0, // Skip to: 4181
1141
/* 28 */      MCD_OPC_CheckField, 15, 1, 0, 50, 16, 0, // Skip to: 4181
1142
/* 35 */      MCD_OPC_CheckField, 0, 4, 4, 43, 16, 0, // Skip to: 4181
1143
/* 42 */      MCD_OPC_Decode, 236, 11, 74, // Opcode: EE_LD_QACC_L_L_128_IP
1144
/* 46 */      MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 81
1145
/* 51 */      MCD_OPC_CheckPredicate, 22, 29, 16, 0, // Skip to: 4181
1146
/* 56 */      MCD_OPC_CheckField, 23, 1, 0, 22, 16, 0, // Skip to: 4181
1147
/* 63 */      MCD_OPC_CheckField, 15, 1, 0, 15, 16, 0, // Skip to: 4181
1148
/* 70 */      MCD_OPC_CheckField, 0, 4, 4, 8, 16, 0, // Skip to: 4181
1149
/* 77 */      MCD_OPC_Decode, 237, 11, 74, // Opcode: EE_LD_UA_STATE_IP
1150
/* 81 */      MCD_OPC_FilterValue, 3, 255, 15, 0, // Skip to: 4181
1151
/* 86 */      MCD_OPC_CheckPredicate, 22, 250, 15, 0, // Skip to: 4181
1152
/* 91 */      MCD_OPC_CheckField, 22, 2, 1, 243, 15, 0, // Skip to: 4181
1153
/* 98 */      MCD_OPC_CheckField, 12, 4, 4, 236, 15, 0, // Skip to: 4181
1154
/* 105 */     MCD_OPC_CheckField, 0, 4, 4, 229, 15, 0, // Skip to: 4181
1155
/* 112 */     MCD_OPC_Decode, 228, 11, 75, // Opcode: EE_LDQA_U8_128_XP
1156
/* 116 */     MCD_OPC_FilterValue, 1, 123, 0, 0, // Skip to: 244
1157
/* 121 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
1158
/* 124 */     MCD_OPC_FilterValue, 0, 94, 0, 0, // Skip to: 223
1159
/* 129 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
1160
/* 132 */     MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 160
1161
/* 137 */     MCD_OPC_CheckPredicate, 22, 199, 15, 0, // Skip to: 4181
1162
/* 142 */     MCD_OPC_CheckField, 15, 1, 0, 192, 15, 0, // Skip to: 4181
1163
/* 149 */     MCD_OPC_CheckField, 0, 4, 4, 185, 15, 0, // Skip to: 4181
1164
/* 156 */     MCD_OPC_Decode, 221, 11, 74, // Opcode: EE_LDQA_S16_128_IP
1165
/* 160 */     MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 188
1166
/* 165 */     MCD_OPC_CheckPredicate, 22, 171, 15, 0, // Skip to: 4181
1167
/* 170 */     MCD_OPC_CheckField, 15, 1, 0, 164, 15, 0, // Skip to: 4181
1168
/* 177 */     MCD_OPC_CheckField, 0, 4, 4, 157, 15, 0, // Skip to: 4181
1169
/* 184 */     MCD_OPC_Decode, 223, 11, 74, // Opcode: EE_LDQA_S8_128_IP
1170
/* 188 */     MCD_OPC_FilterValue, 3, 148, 15, 0, // Skip to: 4181
1171
/* 193 */     MCD_OPC_CheckPredicate, 22, 143, 15, 0, // Skip to: 4181
1172
/* 198 */     MCD_OPC_CheckField, 22, 1, 1, 136, 15, 0, // Skip to: 4181
1173
/* 205 */     MCD_OPC_CheckField, 12, 4, 4, 129, 15, 0, // Skip to: 4181
1174
/* 212 */     MCD_OPC_CheckField, 0, 4, 4, 122, 15, 0, // Skip to: 4181
1175
/* 219 */     MCD_OPC_Decode, 224, 11, 75, // Opcode: EE_LDQA_S8_128_XP
1176
/* 223 */     MCD_OPC_FilterValue, 1, 113, 15, 0, // Skip to: 4181
1177
/* 228 */     MCD_OPC_CheckPredicate, 22, 108, 15, 0, // Skip to: 4181
1178
/* 233 */     MCD_OPC_CheckField, 0, 4, 4, 101, 15, 0, // Skip to: 4181
1179
/* 240 */     MCD_OPC_Decode, 230, 11, 76, // Opcode: EE_LD_128_USAR_IP
1180
/* 244 */     MCD_OPC_FilterValue, 2, 88, 0, 0, // Skip to: 337
1181
/* 249 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
1182
/* 252 */     MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 316
1183
/* 257 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
1184
/* 260 */     MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 288
1185
/* 265 */     MCD_OPC_CheckPredicate, 22, 71, 15, 0, // Skip to: 4181
1186
/* 270 */     MCD_OPC_CheckField, 15, 1, 0, 64, 15, 0, // Skip to: 4181
1187
/* 277 */     MCD_OPC_CheckField, 0, 4, 4, 57, 15, 0, // Skip to: 4181
1188
/* 284 */     MCD_OPC_Decode, 136, 12, 77, // Opcode: EE_ST_ACCX_IP
1189
/* 288 */     MCD_OPC_FilterValue, 1, 48, 15, 0, // Skip to: 4181
1190
/* 293 */     MCD_OPC_CheckPredicate, 22, 43, 15, 0, // Skip to: 4181
1191
/* 298 */     MCD_OPC_CheckField, 15, 1, 0, 36, 15, 0, // Skip to: 4181
1192
/* 305 */     MCD_OPC_CheckField, 0, 4, 4, 29, 15, 0, // Skip to: 4181
1193
/* 312 */     MCD_OPC_Decode, 137, 12, 78, // Opcode: EE_ST_QACC_H_H_32_IP
1194
/* 316 */     MCD_OPC_FilterValue, 1, 20, 15, 0, // Skip to: 4181
1195
/* 321 */     MCD_OPC_CheckPredicate, 22, 15, 15, 0, // Skip to: 4181
1196
/* 326 */     MCD_OPC_CheckField, 0, 4, 4, 8, 15, 0, // Skip to: 4181
1197
/* 333 */     MCD_OPC_Decode, 164, 12, 79, // Opcode: EE_VLDBC_32_IP
1198
/* 337 */     MCD_OPC_FilterValue, 3, 48, 3, 0, // Skip to: 1158
1199
/* 342 */     MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
1200
/* 345 */     MCD_OPC_FilterValue, 0, 19, 3, 0, // Skip to: 1137
1201
/* 350 */     MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
1202
/* 353 */     MCD_OPC_FilterValue, 0, 15, 1, 0, // Skip to: 629
1203
/* 358 */     MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
1204
/* 361 */     MCD_OPC_FilterValue, 14, 227, 0, 0, // Skip to: 593
1205
/* 366 */     MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
1206
/* 369 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 383
1207
/* 374 */     MCD_OPC_CheckPredicate, 22, 218, 14, 0, // Skip to: 4181
1208
/* 379 */     MCD_OPC_Decode, 196, 14, 80, // Opcode: RUR_ACCX_0
1209
/* 383 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 397
1210
/* 388 */     MCD_OPC_CheckPredicate, 22, 204, 14, 0, // Skip to: 4181
1211
/* 393 */     MCD_OPC_Decode, 197, 14, 80, // Opcode: RUR_ACCX_1
1212
/* 397 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 411
1213
/* 402 */     MCD_OPC_CheckPredicate, 22, 190, 14, 0, // Skip to: 4181
1214
/* 407 */     MCD_OPC_Decode, 215, 14, 80, // Opcode: RUR_QACC_H_0
1215
/* 411 */     MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 425
1216
/* 416 */     MCD_OPC_CheckPredicate, 22, 176, 14, 0, // Skip to: 4181
1217
/* 421 */     MCD_OPC_Decode, 216, 14, 80, // Opcode: RUR_QACC_H_1
1218
/* 425 */     MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 439
1219
/* 430 */     MCD_OPC_CheckPredicate, 22, 162, 14, 0, // Skip to: 4181
1220
/* 435 */     MCD_OPC_Decode, 217, 14, 80, // Opcode: RUR_QACC_H_2
1221
/* 439 */     MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 453
1222
/* 444 */     MCD_OPC_CheckPredicate, 22, 148, 14, 0, // Skip to: 4181
1223
/* 449 */     MCD_OPC_Decode, 218, 14, 80, // Opcode: RUR_QACC_H_3
1224
/* 453 */     MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 467
1225
/* 458 */     MCD_OPC_CheckPredicate, 22, 134, 14, 0, // Skip to: 4181
1226
/* 463 */     MCD_OPC_Decode, 219, 14, 80, // Opcode: RUR_QACC_H_4
1227
/* 467 */     MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 481
1228
/* 472 */     MCD_OPC_CheckPredicate, 22, 120, 14, 0, // Skip to: 4181
1229
/* 477 */     MCD_OPC_Decode, 220, 14, 80, // Opcode: RUR_QACC_L_0
1230
/* 481 */     MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 495
1231
/* 486 */     MCD_OPC_CheckPredicate, 22, 106, 14, 0, // Skip to: 4181
1232
/* 491 */     MCD_OPC_Decode, 221, 14, 80, // Opcode: RUR_QACC_L_1
1233
/* 495 */     MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 509
1234
/* 500 */     MCD_OPC_CheckPredicate, 22, 92, 14, 0, // Skip to: 4181
1235
/* 505 */     MCD_OPC_Decode, 222, 14, 80, // Opcode: RUR_QACC_L_2
1236
/* 509 */     MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 523
1237
/* 514 */     MCD_OPC_CheckPredicate, 22, 78, 14, 0, // Skip to: 4181
1238
/* 519 */     MCD_OPC_Decode, 223, 14, 80, // Opcode: RUR_QACC_L_3
1239
/* 523 */     MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 537
1240
/* 528 */     MCD_OPC_CheckPredicate, 22, 64, 14, 0, // Skip to: 4181
1241
/* 533 */     MCD_OPC_Decode, 224, 14, 80, // Opcode: RUR_QACC_L_4
1242
/* 537 */     MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 551
1243
/* 542 */     MCD_OPC_CheckPredicate, 22, 50, 14, 0, // Skip to: 4181
1244
/* 547 */     MCD_OPC_Decode, 214, 14, 80, // Opcode: RUR_GPIO_OUT
1245
/* 551 */     MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 565
1246
/* 556 */     MCD_OPC_CheckPredicate, 22, 36, 14, 0, // Skip to: 4181
1247
/* 561 */     MCD_OPC_Decode, 225, 14, 80, // Opcode: RUR_SAR_BYTE
1248
/* 565 */     MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 579
1249
/* 570 */     MCD_OPC_CheckPredicate, 22, 22, 14, 0, // Skip to: 4181
1250
/* 575 */     MCD_OPC_Decode, 213, 14, 80, // Opcode: RUR_FFT_BIT_WIDTH
1251
/* 579 */     MCD_OPC_FilterValue, 15, 13, 14, 0, // Skip to: 4181
1252
/* 584 */     MCD_OPC_CheckPredicate, 22, 8, 14, 0, // Skip to: 4181
1253
/* 589 */     MCD_OPC_Decode, 226, 14, 80, // Opcode: RUR_UA_STATE_0
1254
/* 593 */     MCD_OPC_FilterValue, 15, 255, 13, 0, // Skip to: 4181
1255
/* 598 */     MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
1256
/* 601 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 615
1257
/* 606 */     MCD_OPC_CheckPredicate, 22, 242, 13, 0, // Skip to: 4181
1258
/* 611 */     MCD_OPC_Decode, 152, 15, 25, // Opcode: WUR_ACCX_0
1259
/* 615 */     MCD_OPC_FilterValue, 1, 233, 13, 0, // Skip to: 4181
1260
/* 620 */     MCD_OPC_CheckPredicate, 22, 228, 13, 0, // Skip to: 4181
1261
/* 625 */     MCD_OPC_Decode, 185, 15, 25, // Opcode: WUR_UA_STATE_1
1262
/* 629 */     MCD_OPC_FilterValue, 1, 89, 0, 0, // Skip to: 723
1263
/* 634 */     MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
1264
/* 637 */     MCD_OPC_FilterValue, 14, 45, 0, 0, // Skip to: 687
1265
/* 642 */     MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
1266
/* 645 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 659
1267
/* 650 */     MCD_OPC_CheckPredicate, 22, 198, 13, 0, // Skip to: 4181
1268
/* 655 */     MCD_OPC_Decode, 227, 14, 80, // Opcode: RUR_UA_STATE_1
1269
/* 659 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 673
1270
/* 664 */     MCD_OPC_CheckPredicate, 22, 184, 13, 0, // Skip to: 4181
1271
/* 669 */     MCD_OPC_Decode, 228, 14, 80, // Opcode: RUR_UA_STATE_2
1272
/* 673 */     MCD_OPC_FilterValue, 2, 175, 13, 0, // Skip to: 4181
1273
/* 678 */     MCD_OPC_CheckPredicate, 22, 170, 13, 0, // Skip to: 4181
1274
/* 683 */     MCD_OPC_Decode, 229, 14, 80, // Opcode: RUR_UA_STATE_3
1275
/* 687 */     MCD_OPC_FilterValue, 15, 161, 13, 0, // Skip to: 4181
1276
/* 692 */     MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
1277
/* 695 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 709
1278
/* 700 */     MCD_OPC_CheckPredicate, 22, 148, 13, 0, // Skip to: 4181
1279
/* 705 */     MCD_OPC_Decode, 153, 15, 25, // Opcode: WUR_ACCX_1
1280
/* 709 */     MCD_OPC_FilterValue, 1, 139, 13, 0, // Skip to: 4181
1281
/* 714 */     MCD_OPC_CheckPredicate, 22, 134, 13, 0, // Skip to: 4181
1282
/* 719 */     MCD_OPC_Decode, 186, 15, 25, // Opcode: WUR_UA_STATE_2
1283
/* 723 */     MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 773
1284
/* 728 */     MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
1285
/* 731 */     MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 752
1286
/* 736 */     MCD_OPC_CheckPredicate, 22, 112, 13, 0, // Skip to: 4181
1287
/* 741 */     MCD_OPC_CheckField, 20, 4, 15, 105, 13, 0, // Skip to: 4181
1288
/* 748 */     MCD_OPC_Decode, 173, 15, 25, // Opcode: WUR_QACC_H_0
1289
/* 752 */     MCD_OPC_FilterValue, 1, 96, 13, 0, // Skip to: 4181
1290
/* 757 */     MCD_OPC_CheckPredicate, 22, 91, 13, 0, // Skip to: 4181
1291
/* 762 */     MCD_OPC_CheckField, 20, 4, 15, 84, 13, 0, // Skip to: 4181
1292
/* 769 */     MCD_OPC_Decode, 187, 15, 25, // Opcode: WUR_UA_STATE_3
1293
/* 773 */     MCD_OPC_FilterValue, 3, 23, 0, 0, // Skip to: 801
1294
/* 778 */     MCD_OPC_CheckPredicate, 22, 70, 13, 0, // Skip to: 4181
1295
/* 783 */     MCD_OPC_CheckField, 20, 4, 15, 63, 13, 0, // Skip to: 4181
1296
/* 790 */     MCD_OPC_CheckField, 12, 4, 0, 56, 13, 0, // Skip to: 4181
1297
/* 797 */     MCD_OPC_Decode, 174, 15, 25, // Opcode: WUR_QACC_H_1
1298
/* 801 */     MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 829
1299
/* 806 */     MCD_OPC_CheckPredicate, 22, 42, 13, 0, // Skip to: 4181
1300
/* 811 */     MCD_OPC_CheckField, 20, 4, 15, 35, 13, 0, // Skip to: 4181
1301
/* 818 */     MCD_OPC_CheckField, 12, 4, 0, 28, 13, 0, // Skip to: 4181
1302
/* 825 */     MCD_OPC_Decode, 175, 15, 25, // Opcode: WUR_QACC_H_2
1303
/* 829 */     MCD_OPC_FilterValue, 5, 23, 0, 0, // Skip to: 857
1304
/* 834 */     MCD_OPC_CheckPredicate, 22, 14, 13, 0, // Skip to: 4181
1305
/* 839 */     MCD_OPC_CheckField, 20, 4, 15, 7, 13, 0, // Skip to: 4181
1306
/* 846 */     MCD_OPC_CheckField, 12, 4, 0, 0, 13, 0, // Skip to: 4181
1307
/* 853 */     MCD_OPC_Decode, 176, 15, 25, // Opcode: WUR_QACC_H_3
1308
/* 857 */     MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 885
1309
/* 862 */     MCD_OPC_CheckPredicate, 22, 242, 12, 0, // Skip to: 4181
1310
/* 867 */     MCD_OPC_CheckField, 20, 4, 15, 235, 12, 0, // Skip to: 4181
1311
/* 874 */     MCD_OPC_CheckField, 12, 4, 0, 228, 12, 0, // Skip to: 4181
1312
/* 881 */     MCD_OPC_Decode, 177, 15, 25, // Opcode: WUR_QACC_H_4
1313
/* 885 */     MCD_OPC_FilterValue, 7, 23, 0, 0, // Skip to: 913
1314
/* 890 */     MCD_OPC_CheckPredicate, 22, 214, 12, 0, // Skip to: 4181
1315
/* 895 */     MCD_OPC_CheckField, 20, 4, 15, 207, 12, 0, // Skip to: 4181
1316
/* 902 */     MCD_OPC_CheckField, 12, 4, 0, 200, 12, 0, // Skip to: 4181
1317
/* 909 */     MCD_OPC_Decode, 178, 15, 25, // Opcode: WUR_QACC_L_0
1318
/* 913 */     MCD_OPC_FilterValue, 8, 23, 0, 0, // Skip to: 941
1319
/* 918 */     MCD_OPC_CheckPredicate, 22, 186, 12, 0, // Skip to: 4181
1320
/* 923 */     MCD_OPC_CheckField, 20, 4, 15, 179, 12, 0, // Skip to: 4181
1321
/* 930 */     MCD_OPC_CheckField, 12, 4, 0, 172, 12, 0, // Skip to: 4181
1322
/* 937 */     MCD_OPC_Decode, 179, 15, 25, // Opcode: WUR_QACC_L_1
1323
/* 941 */     MCD_OPC_FilterValue, 9, 23, 0, 0, // Skip to: 969
1324
/* 946 */     MCD_OPC_CheckPredicate, 22, 158, 12, 0, // Skip to: 4181
1325
/* 951 */     MCD_OPC_CheckField, 20, 4, 15, 151, 12, 0, // Skip to: 4181
1326
/* 958 */     MCD_OPC_CheckField, 12, 4, 0, 144, 12, 0, // Skip to: 4181
1327
/* 965 */     MCD_OPC_Decode, 180, 15, 25, // Opcode: WUR_QACC_L_2
1328
/* 969 */     MCD_OPC_FilterValue, 10, 23, 0, 0, // Skip to: 997
1329
/* 974 */     MCD_OPC_CheckPredicate, 22, 130, 12, 0, // Skip to: 4181
1330
/* 979 */     MCD_OPC_CheckField, 20, 4, 15, 123, 12, 0, // Skip to: 4181
1331
/* 986 */     MCD_OPC_CheckField, 12, 4, 0, 116, 12, 0, // Skip to: 4181
1332
/* 993 */     MCD_OPC_Decode, 181, 15, 25, // Opcode: WUR_QACC_L_3
1333
/* 997 */     MCD_OPC_FilterValue, 11, 23, 0, 0, // Skip to: 1025
1334
/* 1002 */    MCD_OPC_CheckPredicate, 22, 102, 12, 0, // Skip to: 4181
1335
/* 1007 */    MCD_OPC_CheckField, 20, 4, 15, 95, 12, 0, // Skip to: 4181
1336
/* 1014 */    MCD_OPC_CheckField, 12, 4, 0, 88, 12, 0, // Skip to: 4181
1337
/* 1021 */    MCD_OPC_Decode, 182, 15, 25, // Opcode: WUR_QACC_L_4
1338
/* 1025 */    MCD_OPC_FilterValue, 12, 23, 0, 0, // Skip to: 1053
1339
/* 1030 */    MCD_OPC_CheckPredicate, 22, 74, 12, 0, // Skip to: 4181
1340
/* 1035 */    MCD_OPC_CheckField, 20, 4, 15, 67, 12, 0, // Skip to: 4181
1341
/* 1042 */    MCD_OPC_CheckField, 12, 4, 0, 60, 12, 0, // Skip to: 4181
1342
/* 1049 */    MCD_OPC_Decode, 172, 15, 25, // Opcode: WUR_GPIO_OUT
1343
/* 1053 */    MCD_OPC_FilterValue, 13, 23, 0, 0, // Skip to: 1081
1344
/* 1058 */    MCD_OPC_CheckPredicate, 22, 46, 12, 0, // Skip to: 4181
1345
/* 1063 */    MCD_OPC_CheckField, 20, 4, 15, 39, 12, 0, // Skip to: 4181
1346
/* 1070 */    MCD_OPC_CheckField, 12, 4, 0, 32, 12, 0, // Skip to: 4181
1347
/* 1077 */    MCD_OPC_Decode, 183, 15, 25, // Opcode: WUR_SAR_BYTE
1348
/* 1081 */    MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 1109
1349
/* 1086 */    MCD_OPC_CheckPredicate, 22, 18, 12, 0, // Skip to: 4181
1350
/* 1091 */    MCD_OPC_CheckField, 20, 4, 15, 11, 12, 0, // Skip to: 4181
1351
/* 1098 */    MCD_OPC_CheckField, 12, 4, 0, 4, 12, 0, // Skip to: 4181
1352
/* 1105 */    MCD_OPC_Decode, 170, 15, 25, // Opcode: WUR_FFT_BIT_WIDTH
1353
/* 1109 */    MCD_OPC_FilterValue, 15, 251, 11, 0, // Skip to: 4181
1354
/* 1114 */    MCD_OPC_CheckPredicate, 22, 246, 11, 0, // Skip to: 4181
1355
/* 1119 */    MCD_OPC_CheckField, 20, 4, 15, 239, 11, 0, // Skip to: 4181
1356
/* 1126 */    MCD_OPC_CheckField, 12, 4, 0, 232, 11, 0, // Skip to: 4181
1357
/* 1133 */    MCD_OPC_Decode, 184, 15, 25, // Opcode: WUR_UA_STATE_0
1358
/* 1137 */    MCD_OPC_FilterValue, 4, 223, 11, 0, // Skip to: 4181
1359
/* 1142 */    MCD_OPC_CheckPredicate, 22, 218, 11, 0, // Skip to: 4181
1360
/* 1147 */    MCD_OPC_CheckField, 23, 1, 1, 211, 11, 0, // Skip to: 4181
1361
/* 1154 */    MCD_OPC_Decode, 170, 12, 76, // Opcode: EE_VLD_128_IP
1362
/* 1158 */    MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 1186
1363
/* 1163 */    MCD_OPC_CheckPredicate, 22, 197, 11, 0, // Skip to: 4181
1364
/* 1168 */    MCD_OPC_CheckField, 23, 1, 1, 190, 11, 0, // Skip to: 4181
1365
/* 1175 */    MCD_OPC_CheckField, 0, 4, 4, 183, 11, 0, // Skip to: 4181
1366
/* 1182 */    MCD_OPC_Decode, 140, 13, 81, // Opcode: EE_VST_L_64_IP
1367
/* 1186 */    MCD_OPC_FilterValue, 5, 169, 0, 0, // Skip to: 1360
1368
/* 1191 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
1369
/* 1194 */    MCD_OPC_FilterValue, 0, 111, 0, 0, // Skip to: 1310
1370
/* 1199 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
1371
/* 1202 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 1230
1372
/* 1207 */    MCD_OPC_CheckPredicate, 22, 153, 11, 0, // Skip to: 4181
1373
/* 1212 */    MCD_OPC_CheckField, 15, 1, 0, 146, 11, 0, // Skip to: 4181
1374
/* 1219 */    MCD_OPC_CheckField, 0, 4, 4, 139, 11, 0, // Skip to: 4181
1375
/* 1226 */    MCD_OPC_Decode, 225, 11, 74, // Opcode: EE_LDQA_U16_128_IP
1376
/* 1230 */    MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 1258
1377
/* 1235 */    MCD_OPC_CheckPredicate, 22, 125, 11, 0, // Skip to: 4181
1378
/* 1240 */    MCD_OPC_CheckField, 15, 1, 0, 118, 11, 0, // Skip to: 4181
1379
/* 1247 */    MCD_OPC_CheckField, 0, 4, 4, 111, 11, 0, // Skip to: 4181
1380
/* 1254 */    MCD_OPC_Decode, 227, 11, 74, // Opcode: EE_LDQA_U8_128_IP
1381
/* 1258 */    MCD_OPC_FilterValue, 2, 102, 11, 0, // Skip to: 4181
1382
/* 1263 */    MCD_OPC_ExtractField, 0, 16,  // Inst{15-0} ...
1383
/* 1266 */    MCD_OPC_FilterValue, 132, 16, 16, 0, 0, // Skip to: 1288
1384
/* 1272 */    MCD_OPC_CheckPredicate, 22, 88, 11, 0, // Skip to: 4181
1385
/* 1277 */    MCD_OPC_CheckField, 22, 1, 0, 81, 11, 0, // Skip to: 4181
1386
/* 1284 */    MCD_OPC_Decode, 159, 13, 6, // Opcode: EE_ZERO_ACCX
1387
/* 1288 */    MCD_OPC_FilterValue, 196, 16, 71, 11, 0, // Skip to: 4181
1388
/* 1294 */    MCD_OPC_CheckPredicate, 22, 66, 11, 0, // Skip to: 4181
1389
/* 1299 */    MCD_OPC_CheckField, 22, 1, 0, 59, 11, 0, // Skip to: 4181
1390
/* 1306 */    MCD_OPC_Decode, 161, 13, 6, // Opcode: EE_ZERO_QACC
1391
/* 1310 */    MCD_OPC_FilterValue, 1, 50, 11, 0, // Skip to: 4181
1392
/* 1315 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
1393
/* 1318 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1339
1394
/* 1323 */    MCD_OPC_CheckPredicate, 22, 37, 11, 0, // Skip to: 4181
1395
/* 1328 */    MCD_OPC_CheckField, 0, 4, 4, 30, 11, 0, // Skip to: 4181
1396
/* 1335 */    MCD_OPC_Decode, 161, 12, 82, // Opcode: EE_VLDBC_16_IP
1397
/* 1339 */    MCD_OPC_FilterValue, 1, 21, 11, 0, // Skip to: 4181
1398
/* 1344 */    MCD_OPC_CheckPredicate, 22, 16, 11, 0, // Skip to: 4181
1399
/* 1349 */    MCD_OPC_CheckField, 0, 4, 4, 9, 11, 0, // Skip to: 4181
1400
/* 1356 */    MCD_OPC_Decode, 167, 12, 83, // Opcode: EE_VLDBC_8_IP
1401
/* 1360 */    MCD_OPC_FilterValue, 6, 111, 0, 0, // Skip to: 1476
1402
/* 1365 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
1403
/* 1368 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1382
1404
/* 1373 */    MCD_OPC_CheckPredicate, 22, 243, 10, 0, // Skip to: 4181
1405
/* 1378 */    MCD_OPC_Decode, 220, 11, 84, // Opcode: EE_LDF_64_XP
1406
/* 1382 */    MCD_OPC_FilterValue, 4, 234, 10, 0, // Skip to: 4181
1407
/* 1387 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
1408
/* 1390 */    MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 1440
1409
/* 1395 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
1410
/* 1398 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1419
1411
/* 1403 */    MCD_OPC_CheckPredicate, 22, 213, 10, 0, // Skip to: 4181
1412
/* 1408 */    MCD_OPC_CheckField, 15, 1, 0, 206, 10, 0, // Skip to: 4181
1413
/* 1415 */    MCD_OPC_Decode, 234, 11, 74, // Opcode: EE_LD_QACC_H_L_128_IP
1414
/* 1419 */    MCD_OPC_FilterValue, 1, 197, 10, 0, // Skip to: 4181
1415
/* 1424 */    MCD_OPC_CheckPredicate, 22, 192, 10, 0, // Skip to: 4181
1416
/* 1429 */    MCD_OPC_CheckField, 15, 1, 0, 185, 10, 0, // Skip to: 4181
1417
/* 1436 */    MCD_OPC_Decode, 235, 11, 78, // Opcode: EE_LD_QACC_L_H_32_IP
1418
/* 1440 */    MCD_OPC_FilterValue, 1, 176, 10, 0, // Skip to: 4181
1419
/* 1445 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
1420
/* 1448 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1462
1421
/* 1453 */    MCD_OPC_CheckPredicate, 22, 163, 10, 0, // Skip to: 4181
1422
/* 1458 */    MCD_OPC_Decode, 248, 11, 85, // Opcode: EE_SLCXXP_2Q
1423
/* 1462 */    MCD_OPC_FilterValue, 1, 154, 10, 0, // Skip to: 4181
1424
/* 1467 */    MCD_OPC_CheckPredicate, 22, 149, 10, 0, // Skip to: 4181
1425
/* 1472 */    MCD_OPC_Decode, 253, 11, 85, // Opcode: EE_SRCXXP_2Q
1426
/* 1476 */    MCD_OPC_FilterValue, 7, 81, 0, 0, // Skip to: 1562
1427
/* 1481 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
1428
/* 1484 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1498
1429
/* 1489 */    MCD_OPC_CheckPredicate, 22, 127, 10, 0, // Skip to: 4181
1430
/* 1494 */    MCD_OPC_Decode, 134, 12, 86, // Opcode: EE_STF_64_XP
1431
/* 1498 */    MCD_OPC_FilterValue, 4, 118, 10, 0, // Skip to: 4181
1432
/* 1503 */    MCD_OPC_ExtractField, 21, 3,  // Inst{23-21} ...
1433
/* 1506 */    MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1520
1434
/* 1511 */    MCD_OPC_CheckPredicate, 22, 105, 10, 0, // Skip to: 4181
1435
/* 1516 */    MCD_OPC_Decode, 200, 12, 87, // Opcode: EE_VMULAS_S16_QACC_LDBC_INCP
1436
/* 1520 */    MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1534
1437
/* 1525 */    MCD_OPC_CheckPredicate, 22, 91, 10, 0, // Skip to: 4181
1438
/* 1530 */    MCD_OPC_Decode, 212, 12, 87, // Opcode: EE_VMULAS_S8_QACC_LDBC_INCP
1439
/* 1534 */    MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1548
1440
/* 1539 */    MCD_OPC_CheckPredicate, 22, 77, 10, 0, // Skip to: 4181
1441
/* 1544 */    MCD_OPC_Decode, 224, 12, 87, // Opcode: EE_VMULAS_U16_QACC_LDBC_INCP
1442
/* 1548 */    MCD_OPC_FilterValue, 7, 68, 10, 0, // Skip to: 4181
1443
/* 1553 */    MCD_OPC_CheckPredicate, 22, 63, 10, 0, // Skip to: 4181
1444
/* 1558 */    MCD_OPC_Decode, 236, 12, 87, // Opcode: EE_VMULAS_U8_QACC_LDBC_INCP
1445
/* 1562 */    MCD_OPC_FilterValue, 8, 23, 0, 0, // Skip to: 1590
1446
/* 1567 */    MCD_OPC_CheckPredicate, 22, 49, 10, 0, // Skip to: 4181
1447
/* 1572 */    MCD_OPC_CheckField, 23, 1, 1, 42, 10, 0, // Skip to: 4181
1448
/* 1579 */    MCD_OPC_CheckField, 0, 4, 4, 35, 10, 0, // Skip to: 4181
1449
/* 1586 */    MCD_OPC_Decode, 172, 12, 88, // Opcode: EE_VLD_H_64_IP
1450
/* 1590 */    MCD_OPC_FilterValue, 9, 23, 0, 0, // Skip to: 1618
1451
/* 1595 */    MCD_OPC_CheckPredicate, 22, 21, 10, 0, // Skip to: 4181
1452
/* 1600 */    MCD_OPC_CheckField, 23, 1, 1, 14, 10, 0, // Skip to: 4181
1453
/* 1607 */    MCD_OPC_CheckField, 0, 4, 4, 7, 10, 0, // Skip to: 4181
1454
/* 1614 */    MCD_OPC_Decode, 174, 12, 88, // Opcode: EE_VLD_L_64_IP
1455
/* 1618 */    MCD_OPC_FilterValue, 10, 24, 1, 0, // Skip to: 1903
1456
/* 1623 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
1457
/* 1626 */    MCD_OPC_FilterValue, 0, 251, 0, 0, // Skip to: 1882
1458
/* 1631 */    MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
1459
/* 1634 */    MCD_OPC_FilterValue, 0, 105, 0, 0, // Skip to: 1744
1460
/* 1639 */    MCD_OPC_ExtractField, 0, 8,  // Inst{7-0} ...
1461
/* 1642 */    MCD_OPC_FilterValue, 132, 1, 45, 0, 0, // Skip to: 1693
1462
/* 1648 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1463
/* 1651 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1672
1464
/* 1656 */    MCD_OPC_CheckPredicate, 22, 216, 9, 0, // Skip to: 4181
1465
/* 1661 */    MCD_OPC_CheckField, 15, 1, 0, 209, 9, 0, // Skip to: 4181
1466
/* 1668 */    MCD_OPC_Decode, 218, 12, 89, // Opcode: EE_VMULAS_U16_ACCX
1467
/* 1672 */    MCD_OPC_FilterValue, 1, 200, 9, 0, // Skip to: 4181
1468
/* 1677 */    MCD_OPC_CheckPredicate, 22, 195, 9, 0, // Skip to: 4181
1469
/* 1682 */    MCD_OPC_CheckField, 15, 1, 0, 188, 9, 0, // Skip to: 4181
1470
/* 1689 */    MCD_OPC_Decode, 223, 12, 89, // Opcode: EE_VMULAS_U16_QACC
1471
/* 1693 */    MCD_OPC_FilterValue, 196, 1, 178, 9, 0, // Skip to: 4181
1472
/* 1699 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1473
/* 1702 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1723
1474
/* 1707 */    MCD_OPC_CheckPredicate, 22, 165, 9, 0, // Skip to: 4181
1475
/* 1712 */    MCD_OPC_CheckField, 15, 1, 0, 158, 9, 0, // Skip to: 4181
1476
/* 1719 */    MCD_OPC_Decode, 230, 12, 89, // Opcode: EE_VMULAS_U8_ACCX
1477
/* 1723 */    MCD_OPC_FilterValue, 1, 149, 9, 0, // Skip to: 4181
1478
/* 1728 */    MCD_OPC_CheckPredicate, 22, 144, 9, 0, // Skip to: 4181
1479
/* 1733 */    MCD_OPC_CheckField, 15, 1, 0, 137, 9, 0, // Skip to: 4181
1480
/* 1740 */    MCD_OPC_Decode, 235, 12, 89, // Opcode: EE_VMULAS_U8_QACC
1481
/* 1744 */    MCD_OPC_FilterValue, 1, 105, 0, 0, // Skip to: 1854
1482
/* 1749 */    MCD_OPC_ExtractField, 0, 8,  // Inst{7-0} ...
1483
/* 1752 */    MCD_OPC_FilterValue, 132, 1, 45, 0, 0, // Skip to: 1803
1484
/* 1758 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1485
/* 1761 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1782
1486
/* 1766 */    MCD_OPC_CheckPredicate, 22, 106, 9, 0, // Skip to: 4181
1487
/* 1771 */    MCD_OPC_CheckField, 15, 1, 0, 99, 9, 0, // Skip to: 4181
1488
/* 1778 */    MCD_OPC_Decode, 194, 12, 89, // Opcode: EE_VMULAS_S16_ACCX
1489
/* 1782 */    MCD_OPC_FilterValue, 1, 90, 9, 0, // Skip to: 4181
1490
/* 1787 */    MCD_OPC_CheckPredicate, 22, 85, 9, 0, // Skip to: 4181
1491
/* 1792 */    MCD_OPC_CheckField, 15, 1, 0, 78, 9, 0, // Skip to: 4181
1492
/* 1799 */    MCD_OPC_Decode, 199, 12, 89, // Opcode: EE_VMULAS_S16_QACC
1493
/* 1803 */    MCD_OPC_FilterValue, 196, 1, 68, 9, 0, // Skip to: 4181
1494
/* 1809 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1495
/* 1812 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1833
1496
/* 1817 */    MCD_OPC_CheckPredicate, 22, 55, 9, 0, // Skip to: 4181
1497
/* 1822 */    MCD_OPC_CheckField, 15, 1, 0, 48, 9, 0, // Skip to: 4181
1498
/* 1829 */    MCD_OPC_Decode, 206, 12, 89, // Opcode: EE_VMULAS_S8_ACCX
1499
/* 1833 */    MCD_OPC_FilterValue, 1, 39, 9, 0, // Skip to: 4181
1500
/* 1838 */    MCD_OPC_CheckPredicate, 22, 34, 9, 0, // Skip to: 4181
1501
/* 1843 */    MCD_OPC_CheckField, 15, 1, 0, 27, 9, 0, // Skip to: 4181
1502
/* 1850 */    MCD_OPC_Decode, 211, 12, 89, // Opcode: EE_VMULAS_S8_QACC
1503
/* 1854 */    MCD_OPC_FilterValue, 7, 18, 9, 0, // Skip to: 4181
1504
/* 1859 */    MCD_OPC_CheckPredicate, 22, 13, 9, 0, // Skip to: 4181
1505
/* 1864 */    MCD_OPC_CheckField, 12, 4, 4, 6, 9, 0, // Skip to: 4181
1506
/* 1871 */    MCD_OPC_CheckField, 0, 4, 4, 255, 8, 0, // Skip to: 4181
1507
/* 1878 */    MCD_OPC_Decode, 226, 11, 75, // Opcode: EE_LDQA_U16_128_XP
1508
/* 1882 */    MCD_OPC_FilterValue, 1, 246, 8, 0, // Skip to: 4181
1509
/* 1887 */    MCD_OPC_CheckPredicate, 22, 241, 8, 0, // Skip to: 4181
1510
/* 1892 */    MCD_OPC_CheckField, 0, 4, 4, 234, 8, 0, // Skip to: 4181
1511
/* 1899 */    MCD_OPC_Decode, 136, 13, 90, // Opcode: EE_VST_128_IP
1512
/* 1903 */    MCD_OPC_FilterValue, 11, 23, 0, 0, // Skip to: 1931
1513
/* 1908 */    MCD_OPC_CheckPredicate, 22, 220, 8, 0, // Skip to: 4181
1514
/* 1913 */    MCD_OPC_CheckField, 23, 1, 1, 213, 8, 0, // Skip to: 4181
1515
/* 1920 */    MCD_OPC_CheckField, 0, 4, 4, 206, 8, 0, // Skip to: 4181
1516
/* 1927 */    MCD_OPC_Decode, 138, 13, 81, // Opcode: EE_VST_H_64_IP
1517
/* 1931 */    MCD_OPC_FilterValue, 12, 169, 1, 0, // Skip to: 2361
1518
/* 1936 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
1519
/* 1939 */    MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 2003
1520
/* 1944 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
1521
/* 1947 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 1975
1522
/* 1952 */    MCD_OPC_CheckPredicate, 22, 176, 8, 0, // Skip to: 4181
1523
/* 1957 */    MCD_OPC_CheckField, 15, 1, 0, 169, 8, 0, // Skip to: 4181
1524
/* 1964 */    MCD_OPC_CheckField, 0, 4, 4, 162, 8, 0, // Skip to: 4181
1525
/* 1971 */    MCD_OPC_Decode, 140, 12, 74, // Opcode: EE_ST_QACC_L_L_128_IP
1526
/* 1975 */    MCD_OPC_FilterValue, 1, 153, 8, 0, // Skip to: 4181
1527
/* 1980 */    MCD_OPC_CheckPredicate, 22, 148, 8, 0, // Skip to: 4181
1528
/* 1985 */    MCD_OPC_CheckField, 15, 1, 0, 141, 8, 0, // Skip to: 4181
1529
/* 1992 */    MCD_OPC_CheckField, 0, 4, 4, 134, 8, 0, // Skip to: 4181
1530
/* 1999 */    MCD_OPC_Decode, 141, 12, 74, // Opcode: EE_ST_UA_STATE_IP
1531
/* 2003 */    MCD_OPC_FilterValue, 1, 125, 8, 0, // Skip to: 4181
1532
/* 2008 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
1533
/* 2011 */    MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 2061
1534
/* 2016 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1535
/* 2019 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2040
1536
/* 2024 */    MCD_OPC_CheckPredicate, 22, 104, 8, 0, // Skip to: 4181
1537
/* 2029 */    MCD_OPC_CheckField, 0, 4, 4, 97, 8, 0, // Skip to: 4181
1538
/* 2036 */    MCD_OPC_Decode, 254, 12, 91, // Opcode: EE_VPRELU_S16
1539
/* 2040 */    MCD_OPC_FilterValue, 1, 88, 8, 0, // Skip to: 4181
1540
/* 2045 */    MCD_OPC_CheckPredicate, 22, 83, 8, 0, // Skip to: 4181
1541
/* 2050 */    MCD_OPC_CheckField, 0, 4, 4, 76, 8, 0, // Skip to: 4181
1542
/* 2057 */    MCD_OPC_Decode, 255, 12, 91, // Opcode: EE_VPRELU_S8
1543
/* 2061 */    MCD_OPC_FilterValue, 1, 67, 8, 0, // Skip to: 4181
1544
/* 2066 */    MCD_OPC_ExtractField, 9, 1,  // Inst{9} ...
1545
/* 2069 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2090
1546
/* 2074 */    MCD_OPC_CheckPredicate, 22, 54, 8, 0, // Skip to: 4181
1547
/* 2079 */    MCD_OPC_CheckField, 0, 4, 4, 47, 8, 0, // Skip to: 4181
1548
/* 2086 */    MCD_OPC_Decode, 213, 11, 92, // Opcode: EE_FFT_R2BF_S16
1549
/* 2090 */    MCD_OPC_FilterValue, 1, 38, 8, 0, // Skip to: 4181
1550
/* 2095 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
1551
/* 2098 */    MCD_OPC_FilterValue, 0, 145, 0, 0, // Skip to: 2248
1552
/* 2103 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
1553
/* 2106 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2127
1554
/* 2111 */    MCD_OPC_CheckPredicate, 22, 17, 8, 0, // Skip to: 4181
1555
/* 2116 */    MCD_OPC_CheckField, 0, 4, 4, 10, 8, 0, // Skip to: 4181
1556
/* 2123 */    MCD_OPC_Decode, 169, 12, 93, // Opcode: EE_VLDHBC_16_INCP
1557
/* 2127 */    MCD_OPC_FilterValue, 1, 1, 8, 0, // Skip to: 4181
1558
/* 2132 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
1559
/* 2135 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2156
1560
/* 2140 */    MCD_OPC_CheckPredicate, 22, 244, 7, 0, // Skip to: 4181
1561
/* 2145 */    MCD_OPC_CheckField, 0, 4, 4, 237, 7, 0, // Skip to: 4181
1562
/* 2152 */    MCD_OPC_Decode, 254, 11, 94, // Opcode: EE_SRC_Q
1563
/* 2156 */    MCD_OPC_FilterValue, 1, 228, 7, 0, // Skip to: 4181
1564
/* 2161 */    MCD_OPC_ExtractField, 0, 7,  // Inst{6-0} ...
1565
/* 2164 */    MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2178
1566
/* 2169 */    MCD_OPC_CheckPredicate, 22, 215, 7, 0, // Skip to: 4181
1567
/* 2174 */    MCD_OPC_Decode, 151, 13, 95, // Opcode: EE_VUNZIP_16
1568
/* 2178 */    MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 2192
1569
/* 2183 */    MCD_OPC_CheckPredicate, 22, 201, 7, 0, // Skip to: 4181
1570
/* 2188 */    MCD_OPC_Decode, 152, 13, 95, // Opcode: EE_VUNZIP_32
1571
/* 2192 */    MCD_OPC_FilterValue, 36, 9, 0, 0, // Skip to: 2206
1572
/* 2197 */    MCD_OPC_CheckPredicate, 22, 187, 7, 0, // Skip to: 4181
1573
/* 2202 */    MCD_OPC_Decode, 153, 13, 95, // Opcode: EE_VUNZIP_8
1574
/* 2206 */    MCD_OPC_FilterValue, 52, 9, 0, 0, // Skip to: 2220
1575
/* 2211 */    MCD_OPC_CheckPredicate, 22, 173, 7, 0, // Skip to: 4181
1576
/* 2216 */    MCD_OPC_Decode, 154, 13, 95, // Opcode: EE_VZIP_16
1577
/* 2220 */    MCD_OPC_FilterValue, 68, 9, 0, 0, // Skip to: 2234
1578
/* 2225 */    MCD_OPC_CheckPredicate, 22, 159, 7, 0, // Skip to: 4181
1579
/* 2230 */    MCD_OPC_Decode, 155, 13, 95, // Opcode: EE_VZIP_32
1580
/* 2234 */    MCD_OPC_FilterValue, 84, 150, 7, 0, // Skip to: 4181
1581
/* 2239 */    MCD_OPC_CheckPredicate, 22, 145, 7, 0, // Skip to: 4181
1582
/* 2244 */    MCD_OPC_Decode, 156, 13, 95, // Opcode: EE_VZIP_8
1583
/* 2248 */    MCD_OPC_FilterValue, 1, 52, 0, 0, // Skip to: 2305
1584
/* 2253 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
1585
/* 2256 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2277
1586
/* 2261 */    MCD_OPC_CheckPredicate, 22, 123, 7, 0, // Skip to: 4181
1587
/* 2266 */    MCD_OPC_CheckField, 0, 4, 4, 116, 7, 0, // Skip to: 4181
1588
/* 2273 */    MCD_OPC_Decode, 247, 11, 96, // Opcode: EE_SLCI_2Q
1589
/* 2277 */    MCD_OPC_FilterValue, 1, 107, 7, 0, // Skip to: 4181
1590
/* 2282 */    MCD_OPC_CheckPredicate, 22, 102, 7, 0, // Skip to: 4181
1591
/* 2287 */    MCD_OPC_CheckField, 7, 1, 0, 95, 7, 0, // Skip to: 4181
1592
/* 2294 */    MCD_OPC_CheckField, 0, 4, 4, 88, 7, 0, // Skip to: 4181
1593
/* 2301 */    MCD_OPC_Decode, 129, 12, 97, // Opcode: EE_SRC_Q_QUP
1594
/* 2305 */    MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 2333
1595
/* 2310 */    MCD_OPC_CheckPredicate, 22, 74, 7, 0, // Skip to: 4181
1596
/* 2315 */    MCD_OPC_CheckField, 8, 1, 0, 67, 7, 0, // Skip to: 4181
1597
/* 2322 */    MCD_OPC_CheckField, 0, 4, 4, 60, 7, 0, // Skip to: 4181
1598
/* 2329 */    MCD_OPC_Decode, 249, 11, 96, // Opcode: EE_SRCI_2Q
1599
/* 2333 */    MCD_OPC_FilterValue, 3, 51, 7, 0, // Skip to: 4181
1600
/* 2338 */    MCD_OPC_CheckPredicate, 22, 46, 7, 0, // Skip to: 4181
1601
/* 2343 */    MCD_OPC_CheckField, 8, 1, 0, 39, 7, 0, // Skip to: 4181
1602
/* 2350 */    MCD_OPC_CheckField, 0, 4, 4, 32, 7, 0, // Skip to: 4181
1603
/* 2357 */    MCD_OPC_Decode, 252, 11, 98, // Opcode: EE_SRCQ_128_ST_INCP
1604
/* 2361 */    MCD_OPC_FilterValue, 13, 101, 3, 0, // Skip to: 3235
1605
/* 2366 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
1606
/* 2369 */    MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 2433
1607
/* 2374 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
1608
/* 2377 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 2405
1609
/* 2382 */    MCD_OPC_CheckPredicate, 22, 2, 7, 0, // Skip to: 4181
1610
/* 2387 */    MCD_OPC_CheckField, 15, 1, 0, 251, 6, 0, // Skip to: 4181
1611
/* 2394 */    MCD_OPC_CheckField, 0, 4, 4, 244, 6, 0, // Skip to: 4181
1612
/* 2401 */    MCD_OPC_Decode, 138, 12, 74, // Opcode: EE_ST_QACC_H_L_128_IP
1613
/* 2405 */    MCD_OPC_FilterValue, 1, 235, 6, 0, // Skip to: 4181
1614
/* 2410 */    MCD_OPC_CheckPredicate, 22, 230, 6, 0, // Skip to: 4181
1615
/* 2415 */    MCD_OPC_CheckField, 15, 1, 0, 223, 6, 0, // Skip to: 4181
1616
/* 2422 */    MCD_OPC_CheckField, 0, 4, 4, 216, 6, 0, // Skip to: 4181
1617
/* 2429 */    MCD_OPC_Decode, 139, 12, 78, // Opcode: EE_ST_QACC_L_H_32_IP
1618
/* 2433 */    MCD_OPC_FilterValue, 1, 207, 6, 0, // Skip to: 4181
1619
/* 2438 */    MCD_OPC_ExtractField, 12, 3,  // Inst{14-12} ...
1620
/* 2441 */    MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 2491
1621
/* 2446 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
1622
/* 2449 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2470
1623
/* 2454 */    MCD_OPC_CheckPredicate, 22, 186, 6, 0, // Skip to: 4181
1624
/* 2459 */    MCD_OPC_CheckField, 0, 4, 4, 179, 6, 0, // Skip to: 4181
1625
/* 2466 */    MCD_OPC_Decode, 231, 11, 99, // Opcode: EE_LD_128_USAR_XP
1626
/* 2470 */    MCD_OPC_FilterValue, 1, 170, 6, 0, // Skip to: 4181
1627
/* 2475 */    MCD_OPC_CheckPredicate, 22, 165, 6, 0, // Skip to: 4181
1628
/* 2480 */    MCD_OPC_CheckField, 0, 4, 4, 158, 6, 0, // Skip to: 4181
1629
/* 2487 */    MCD_OPC_Decode, 139, 13, 100, // Opcode: EE_VST_H_64_XP
1630
/* 2491 */    MCD_OPC_FilterValue, 1, 45, 0, 0, // Skip to: 2541
1631
/* 2496 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
1632
/* 2499 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2520
1633
/* 2504 */    MCD_OPC_CheckPredicate, 22, 136, 6, 0, // Skip to: 4181
1634
/* 2509 */    MCD_OPC_CheckField, 0, 4, 4, 129, 6, 0, // Skip to: 4181
1635
/* 2516 */    MCD_OPC_Decode, 165, 12, 99, // Opcode: EE_VLDBC_32_XP
1636
/* 2520 */    MCD_OPC_FilterValue, 1, 120, 6, 0, // Skip to: 4181
1637
/* 2525 */    MCD_OPC_CheckPredicate, 22, 115, 6, 0, // Skip to: 4181
1638
/* 2530 */    MCD_OPC_CheckField, 0, 4, 4, 108, 6, 0, // Skip to: 4181
1639
/* 2537 */    MCD_OPC_Decode, 128, 13, 101, // Opcode: EE_VRELU_S16
1640
/* 2541 */    MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 2569
1641
/* 2546 */    MCD_OPC_CheckPredicate, 22, 94, 6, 0, // Skip to: 4181
1642
/* 2551 */    MCD_OPC_CheckField, 22, 1, 0, 87, 6, 0, // Skip to: 4181
1643
/* 2558 */    MCD_OPC_CheckField, 0, 4, 4, 80, 6, 0, // Skip to: 4181
1644
/* 2565 */    MCD_OPC_Decode, 171, 12, 99, // Opcode: EE_VLD_128_XP
1645
/* 2569 */    MCD_OPC_FilterValue, 3, 203, 0, 0, // Skip to: 2777
1646
/* 2574 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
1647
/* 2577 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2598
1648
/* 2582 */    MCD_OPC_CheckPredicate, 22, 58, 6, 0, // Skip to: 4181
1649
/* 2587 */    MCD_OPC_CheckField, 0, 4, 4, 51, 6, 0, // Skip to: 4181
1650
/* 2594 */    MCD_OPC_Decode, 175, 12, 99, // Opcode: EE_VLD_L_64_XP
1651
/* 2598 */    MCD_OPC_FilterValue, 1, 42, 6, 0, // Skip to: 4181
1652
/* 2603 */    MCD_OPC_ExtractField, 8, 2,  // Inst{9-8} ...
1653
/* 2606 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2627
1654
/* 2611 */    MCD_OPC_CheckPredicate, 22, 29, 6, 0, // Skip to: 4181
1655
/* 2616 */    MCD_OPC_CheckField, 0, 4, 4, 22, 6, 0, // Skip to: 4181
1656
/* 2623 */    MCD_OPC_Decode, 201, 11, 102, // Opcode: EE_ANDQ
1657
/* 2627 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 2648
1658
/* 2632 */    MCD_OPC_CheckPredicate, 22, 8, 6, 0, // Skip to: 4181
1659
/* 2637 */    MCD_OPC_CheckField, 0, 4, 4, 1, 6, 0, // Skip to: 4181
1660
/* 2644 */    MCD_OPC_Decode, 158, 13, 102, // Opcode: EE_XORQ
1661
/* 2648 */    MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 2669
1662
/* 2653 */    MCD_OPC_CheckPredicate, 22, 243, 5, 0, // Skip to: 4181
1663
/* 2658 */    MCD_OPC_CheckField, 0, 4, 4, 236, 5, 0, // Skip to: 4181
1664
/* 2665 */    MCD_OPC_Decode, 239, 11, 103, // Opcode: EE_MOVI_32_Q
1665
/* 2669 */    MCD_OPC_FilterValue, 3, 227, 5, 0, // Skip to: 4181
1666
/* 2674 */    MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
1667
/* 2677 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2698
1668
/* 2682 */    MCD_OPC_CheckPredicate, 22, 214, 5, 0, // Skip to: 4181
1669
/* 2687 */    MCD_OPC_CheckField, 0, 4, 4, 207, 5, 0, // Skip to: 4181
1670
/* 2694 */    MCD_OPC_Decode, 215, 11, 104, // Opcode: EE_FFT_VST_R32_DECP
1671
/* 2698 */    MCD_OPC_FilterValue, 1, 198, 5, 0, // Skip to: 4181
1672
/* 2703 */    MCD_OPC_ExtractField, 10, 1,  // Inst{10} ...
1673
/* 2706 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2727
1674
/* 2711 */    MCD_OPC_CheckPredicate, 22, 185, 5, 0, // Skip to: 4181
1675
/* 2716 */    MCD_OPC_CheckField, 0, 4, 4, 178, 5, 0, // Skip to: 4181
1676
/* 2723 */    MCD_OPC_Decode, 166, 12, 105, // Opcode: EE_VLDBC_8
1677
/* 2727 */    MCD_OPC_FilterValue, 1, 169, 5, 0, // Skip to: 4181
1678
/* 2732 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
1679
/* 2735 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2756
1680
/* 2740 */    MCD_OPC_CheckPredicate, 22, 156, 5, 0, // Skip to: 4181
1681
/* 2745 */    MCD_OPC_CheckField, 0, 4, 4, 149, 5, 0, // Skip to: 4181
1682
/* 2752 */    MCD_OPC_Decode, 130, 13, 106, // Opcode: EE_VSL_32
1683
/* 2756 */    MCD_OPC_FilterValue, 1, 140, 5, 0, // Skip to: 4181
1684
/* 2761 */    MCD_OPC_CheckPredicate, 22, 135, 5, 0, // Skip to: 4181
1685
/* 2766 */    MCD_OPC_CheckField, 0, 4, 4, 128, 5, 0, // Skip to: 4181
1686
/* 2773 */    MCD_OPC_Decode, 135, 13, 106, // Opcode: EE_VSR_32
1687
/* 2777 */    MCD_OPC_FilterValue, 4, 45, 0, 0, // Skip to: 2827
1688
/* 2782 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
1689
/* 2785 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2806
1690
/* 2790 */    MCD_OPC_CheckPredicate, 22, 106, 5, 0, // Skip to: 4181
1691
/* 2795 */    MCD_OPC_CheckField, 0, 4, 4, 99, 5, 0, // Skip to: 4181
1692
/* 2802 */    MCD_OPC_Decode, 162, 12, 99, // Opcode: EE_VLDBC_16_XP
1693
/* 2806 */    MCD_OPC_FilterValue, 1, 90, 5, 0, // Skip to: 4181
1694
/* 2811 */    MCD_OPC_CheckPredicate, 22, 85, 5, 0, // Skip to: 4181
1695
/* 2816 */    MCD_OPC_CheckField, 0, 4, 4, 78, 5, 0, // Skip to: 4181
1696
/* 2823 */    MCD_OPC_Decode, 141, 13, 100, // Opcode: EE_VST_L_64_XP
1697
/* 2827 */    MCD_OPC_FilterValue, 5, 45, 0, 0, // Skip to: 2877
1698
/* 2832 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
1699
/* 2835 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2856
1700
/* 2840 */    MCD_OPC_CheckPredicate, 22, 56, 5, 0, // Skip to: 4181
1701
/* 2845 */    MCD_OPC_CheckField, 0, 4, 4, 49, 5, 0, // Skip to: 4181
1702
/* 2852 */    MCD_OPC_Decode, 168, 12, 99, // Opcode: EE_VLDBC_8_XP
1703
/* 2856 */    MCD_OPC_FilterValue, 1, 40, 5, 0, // Skip to: 4181
1704
/* 2861 */    MCD_OPC_CheckPredicate, 22, 35, 5, 0, // Skip to: 4181
1705
/* 2866 */    MCD_OPC_CheckField, 0, 4, 4, 28, 5, 0, // Skip to: 4181
1706
/* 2873 */    MCD_OPC_Decode, 129, 13, 101, // Opcode: EE_VRELU_S8
1707
/* 2877 */    MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 2905
1708
/* 2882 */    MCD_OPC_CheckPredicate, 22, 14, 5, 0, // Skip to: 4181
1709
/* 2887 */    MCD_OPC_CheckField, 22, 1, 0, 7, 5, 0, // Skip to: 4181
1710
/* 2894 */    MCD_OPC_CheckField, 0, 4, 4, 0, 5, 0, // Skip to: 4181
1711
/* 2901 */    MCD_OPC_Decode, 173, 12, 99, // Opcode: EE_VLD_H_64_XP
1712
/* 2905 */    MCD_OPC_FilterValue, 7, 247, 4, 0, // Skip to: 4181
1713
/* 2910 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
1714
/* 2913 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2934
1715
/* 2918 */    MCD_OPC_CheckPredicate, 22, 234, 4, 0, // Skip to: 4181
1716
/* 2923 */    MCD_OPC_CheckField, 0, 4, 4, 227, 4, 0, // Skip to: 4181
1717
/* 2930 */    MCD_OPC_Decode, 137, 13, 100, // Opcode: EE_VST_128_XP
1718
/* 2934 */    MCD_OPC_FilterValue, 1, 218, 4, 0, // Skip to: 4181
1719
/* 2939 */    MCD_OPC_ExtractField, 8, 2,  // Inst{9-8} ...
1720
/* 2942 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2963
1721
/* 2947 */    MCD_OPC_CheckPredicate, 22, 205, 4, 0, // Skip to: 4181
1722
/* 2952 */    MCD_OPC_CheckField, 0, 4, 4, 198, 4, 0, // Skip to: 4181
1723
/* 2959 */    MCD_OPC_Decode, 245, 11, 102, // Opcode: EE_ORQ
1724
/* 2963 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 2984
1725
/* 2968 */    MCD_OPC_CheckPredicate, 22, 184, 4, 0, // Skip to: 4181
1726
/* 2973 */    MCD_OPC_CheckField, 0, 4, 4, 177, 4, 0, // Skip to: 4181
1727
/* 2980 */    MCD_OPC_Decode, 238, 11, 107, // Opcode: EE_MOVI_32_A
1728
/* 2984 */    MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 3034
1729
/* 2989 */    MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
1730
/* 2992 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3013
1731
/* 2997 */    MCD_OPC_CheckPredicate, 22, 155, 4, 0, // Skip to: 4181
1732
/* 3002 */    MCD_OPC_CheckField, 0, 4, 4, 148, 4, 0, // Skip to: 4181
1733
/* 3009 */    MCD_OPC_Decode, 250, 11, 108, // Opcode: EE_SRCMB_S16_QACC
1734
/* 3013 */    MCD_OPC_FilterValue, 1, 139, 4, 0, // Skip to: 4181
1735
/* 3018 */    MCD_OPC_CheckPredicate, 22, 134, 4, 0, // Skip to: 4181
1736
/* 3023 */    MCD_OPC_CheckField, 0, 4, 4, 127, 4, 0, // Skip to: 4181
1737
/* 3030 */    MCD_OPC_Decode, 251, 11, 108, // Opcode: EE_SRCMB_S8_QACC
1738
/* 3034 */    MCD_OPC_FilterValue, 3, 118, 4, 0, // Skip to: 4181
1739
/* 3039 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
1740
/* 3042 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3063
1741
/* 3047 */    MCD_OPC_CheckPredicate, 22, 105, 4, 0, // Skip to: 4181
1742
/* 3052 */    MCD_OPC_CheckField, 0, 4, 4, 98, 4, 0, // Skip to: 4181
1743
/* 3059 */    MCD_OPC_Decode, 160, 12, 105, // Opcode: EE_VLDBC_16
1744
/* 3063 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3084
1745
/* 3068 */    MCD_OPC_CheckPredicate, 22, 84, 4, 0, // Skip to: 4181
1746
/* 3073 */    MCD_OPC_CheckField, 0, 4, 4, 77, 4, 0, // Skip to: 4181
1747
/* 3080 */    MCD_OPC_Decode, 163, 12, 105, // Opcode: EE_VLDBC_32
1748
/* 3084 */    MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 3105
1749
/* 3089 */    MCD_OPC_CheckPredicate, 22, 63, 4, 0, // Skip to: 4181
1750
/* 3094 */    MCD_OPC_CheckField, 0, 4, 4, 56, 4, 0, // Skip to: 4181
1751
/* 3101 */    MCD_OPC_Decode, 202, 11, 109, // Opcode: EE_BITREV
1752
/* 3105 */    MCD_OPC_FilterValue, 3, 47, 4, 0, // Skip to: 4181
1753
/* 3110 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
1754
/* 3113 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3134
1755
/* 3118 */    MCD_OPC_CheckPredicate, 22, 34, 4, 0, // Skip to: 4181
1756
/* 3123 */    MCD_OPC_CheckField, 0, 4, 4, 27, 4, 0, // Skip to: 4181
1757
/* 3130 */    MCD_OPC_Decode, 244, 11, 110, // Opcode: EE_NOTQ
1758
/* 3134 */    MCD_OPC_FilterValue, 1, 18, 4, 0, // Skip to: 4181
1759
/* 3139 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
1760
/* 3142 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 3178
1761
/* 3147 */    MCD_OPC_ExtractField, 0, 5,  // Inst{4-0} ...
1762
/* 3150 */    MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3164
1763
/* 3155 */    MCD_OPC_CheckPredicate, 22, 253, 3, 0, // Skip to: 4181
1764
/* 3160 */    MCD_OPC_Decode, 240, 11, 111, // Opcode: EE_MOV_S16_QACC
1765
/* 3164 */    MCD_OPC_FilterValue, 20, 244, 3, 0, // Skip to: 4181
1766
/* 3169 */    MCD_OPC_CheckPredicate, 22, 239, 3, 0, // Skip to: 4181
1767
/* 3174 */    MCD_OPC_Decode, 241, 11, 111, // Opcode: EE_MOV_S8_QACC
1768
/* 3178 */    MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 3214
1769
/* 3183 */    MCD_OPC_ExtractField, 0, 5,  // Inst{4-0} ...
1770
/* 3186 */    MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3200
1771
/* 3191 */    MCD_OPC_CheckPredicate, 22, 217, 3, 0, // Skip to: 4181
1772
/* 3196 */    MCD_OPC_Decode, 242, 11, 111, // Opcode: EE_MOV_U16_QACC
1773
/* 3200 */    MCD_OPC_FilterValue, 20, 208, 3, 0, // Skip to: 4181
1774
/* 3205 */    MCD_OPC_CheckPredicate, 22, 203, 3, 0, // Skip to: 4181
1775
/* 3210 */    MCD_OPC_Decode, 243, 11, 111, // Opcode: EE_MOV_U8_QACC
1776
/* 3214 */    MCD_OPC_FilterValue, 2, 194, 3, 0, // Skip to: 4181
1777
/* 3219 */    MCD_OPC_CheckPredicate, 22, 189, 3, 0, // Skip to: 4181
1778
/* 3224 */    MCD_OPC_CheckField, 0, 5, 4, 182, 3, 0, // Skip to: 4181
1779
/* 3231 */    MCD_OPC_Decode, 160, 13, 111, // Opcode: EE_ZERO_Q
1780
/* 3235 */    MCD_OPC_FilterValue, 14, 131, 3, 0, // Skip to: 4139
1781
/* 3240 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
1782
/* 3243 */    MCD_OPC_FilterValue, 0, 137, 0, 0, // Skip to: 3385
1783
/* 3248 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
1784
/* 3251 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 3279
1785
/* 3256 */    MCD_OPC_CheckPredicate, 22, 152, 3, 0, // Skip to: 4181
1786
/* 3261 */    MCD_OPC_CheckField, 15, 1, 0, 145, 3, 0, // Skip to: 4181
1787
/* 3268 */    MCD_OPC_CheckField, 0, 4, 4, 138, 3, 0, // Skip to: 4181
1788
/* 3275 */    MCD_OPC_Decode, 232, 11, 77, // Opcode: EE_LD_ACCX_IP
1789
/* 3279 */    MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 3307
1790
/* 3284 */    MCD_OPC_CheckPredicate, 22, 124, 3, 0, // Skip to: 4181
1791
/* 3289 */    MCD_OPC_CheckField, 15, 1, 0, 117, 3, 0, // Skip to: 4181
1792
/* 3296 */    MCD_OPC_CheckField, 0, 4, 4, 110, 3, 0, // Skip to: 4181
1793
/* 3303 */    MCD_OPC_Decode, 233, 11, 78, // Opcode: EE_LD_QACC_H_H_32_IP
1794
/* 3307 */    MCD_OPC_FilterValue, 3, 101, 3, 0, // Skip to: 4181
1795
/* 3312 */    MCD_OPC_ExtractField, 12, 2,  // Inst{13-12} ...
1796
/* 3315 */    MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 3350
1797
/* 3320 */    MCD_OPC_CheckPredicate, 22, 88, 3, 0, // Skip to: 4181
1798
/* 3325 */    MCD_OPC_CheckField, 22, 1, 1, 81, 3, 0, // Skip to: 4181
1799
/* 3332 */    MCD_OPC_CheckField, 14, 2, 1, 74, 3, 0, // Skip to: 4181
1800
/* 3339 */    MCD_OPC_CheckField, 0, 4, 4, 67, 3, 0, // Skip to: 4181
1801
/* 3346 */    MCD_OPC_Decode, 222, 11, 75, // Opcode: EE_LDQA_S16_128_XP
1802
/* 3350 */    MCD_OPC_FilterValue, 1, 58, 3, 0, // Skip to: 4181
1803
/* 3355 */    MCD_OPC_CheckPredicate, 22, 53, 3, 0, // Skip to: 4181
1804
/* 3360 */    MCD_OPC_CheckField, 22, 1, 1, 46, 3, 0, // Skip to: 4181
1805
/* 3367 */    MCD_OPC_CheckField, 15, 1, 0, 39, 3, 0, // Skip to: 4181
1806
/* 3374 */    MCD_OPC_CheckField, 0, 4, 4, 32, 3, 0, // Skip to: 4181
1807
/* 3381 */    MCD_OPC_Decode, 130, 12, 112, // Opcode: EE_SRS_ACCX
1808
/* 3385 */    MCD_OPC_FilterValue, 1, 23, 3, 0, // Skip to: 4181
1809
/* 3390 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
1810
/* 3393 */    MCD_OPC_FilterValue, 0, 123, 0, 0, // Skip to: 3521
1811
/* 3398 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1812
/* 3401 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 3429
1813
/* 3406 */    MCD_OPC_CheckPredicate, 22, 2, 3, 0, // Skip to: 4181
1814
/* 3411 */    MCD_OPC_CheckField, 22, 1, 0, 251, 2, 0, // Skip to: 4181
1815
/* 3418 */    MCD_OPC_CheckField, 0, 4, 4, 244, 2, 0, // Skip to: 4181
1816
/* 3425 */    MCD_OPC_Decode, 204, 11, 113, // Opcode: EE_CMUL_S16
1817
/* 3429 */    MCD_OPC_FilterValue, 1, 235, 2, 0, // Skip to: 4181
1818
/* 3434 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
1819
/* 3437 */    MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 3458
1820
/* 3442 */    MCD_OPC_CheckPredicate, 22, 222, 2, 0, // Skip to: 4181
1821
/* 3447 */    MCD_OPC_CheckField, 22, 1, 0, 215, 2, 0, // Skip to: 4181
1822
/* 3454 */    MCD_OPC_Decode, 158, 12, 114, // Opcode: EE_VCMP_LT_S32
1823
/* 3458 */    MCD_OPC_FilterValue, 20, 16, 0, 0, // Skip to: 3479
1824
/* 3463 */    MCD_OPC_CheckPredicate, 22, 201, 2, 0, // Skip to: 4181
1825
/* 3468 */    MCD_OPC_CheckField, 22, 1, 0, 194, 2, 0, // Skip to: 4181
1826
/* 3475 */    MCD_OPC_Decode, 159, 12, 114, // Opcode: EE_VCMP_LT_S8
1827
/* 3479 */    MCD_OPC_FilterValue, 36, 16, 0, 0, // Skip to: 3500
1828
/* 3484 */    MCD_OPC_CheckPredicate, 22, 180, 2, 0, // Skip to: 4181
1829
/* 3489 */    MCD_OPC_CheckField, 22, 1, 0, 173, 2, 0, // Skip to: 4181
1830
/* 3496 */    MCD_OPC_Decode, 176, 12, 114, // Opcode: EE_VMAX_S16
1831
/* 3500 */    MCD_OPC_FilterValue, 52, 164, 2, 0, // Skip to: 4181
1832
/* 3505 */    MCD_OPC_CheckPredicate, 22, 159, 2, 0, // Skip to: 4181
1833
/* 3510 */    MCD_OPC_CheckField, 22, 1, 0, 152, 2, 0, // Skip to: 4181
1834
/* 3517 */    MCD_OPC_Decode, 179, 12, 114, // Opcode: EE_VMAX_S32
1835
/* 3521 */    MCD_OPC_FilterValue, 1, 197, 0, 0, // Skip to: 3723
1836
/* 3526 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
1837
/* 3529 */    MCD_OPC_FilterValue, 0, 81, 0, 0, // Skip to: 3615
1838
/* 3534 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1839
/* 3537 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 3565
1840
/* 3542 */    MCD_OPC_CheckPredicate, 22, 122, 2, 0, // Skip to: 4181
1841
/* 3547 */    MCD_OPC_CheckField, 22, 1, 0, 115, 2, 0, // Skip to: 4181
1842
/* 3554 */    MCD_OPC_CheckField, 0, 4, 4, 108, 2, 0, // Skip to: 4181
1843
/* 3561 */    MCD_OPC_Decode, 133, 13, 115, // Opcode: EE_VSMULAS_S8_QACC
1844
/* 3565 */    MCD_OPC_FilterValue, 1, 99, 2, 0, // Skip to: 4181
1845
/* 3570 */    MCD_OPC_ExtractField, 0, 5,  // Inst{4-0} ...
1846
/* 3573 */    MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 3594
1847
/* 3578 */    MCD_OPC_CheckPredicate, 22, 86, 2, 0, // Skip to: 4181
1848
/* 3583 */    MCD_OPC_CheckField, 22, 1, 0, 79, 2, 0, // Skip to: 4181
1849
/* 3590 */    MCD_OPC_Decode, 182, 12, 114, // Opcode: EE_VMAX_S8
1850
/* 3594 */    MCD_OPC_FilterValue, 20, 70, 2, 0, // Skip to: 4181
1851
/* 3599 */    MCD_OPC_CheckPredicate, 22, 65, 2, 0, // Skip to: 4181
1852
/* 3604 */    MCD_OPC_CheckField, 22, 1, 0, 58, 2, 0, // Skip to: 4181
1853
/* 3611 */    MCD_OPC_Decode, 185, 12, 114, // Opcode: EE_VMIN_S16
1854
/* 3615 */    MCD_OPC_FilterValue, 1, 49, 2, 0, // Skip to: 4181
1855
/* 3620 */    MCD_OPC_ExtractField, 0, 5,  // Inst{4-0} ...
1856
/* 3623 */    MCD_OPC_FilterValue, 4, 45, 0, 0, // Skip to: 3673
1857
/* 3628 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1858
/* 3631 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3652
1859
/* 3636 */    MCD_OPC_CheckPredicate, 22, 28, 2, 0, // Skip to: 4181
1860
/* 3641 */    MCD_OPC_CheckField, 22, 1, 0, 21, 2, 0, // Skip to: 4181
1861
/* 3648 */    MCD_OPC_Decode, 142, 12, 114, // Opcode: EE_VADDS_S16
1862
/* 3652 */    MCD_OPC_FilterValue, 1, 12, 2, 0, // Skip to: 4181
1863
/* 3657 */    MCD_OPC_CheckPredicate, 22, 7, 2, 0, // Skip to: 4181
1864
/* 3662 */    MCD_OPC_CheckField, 22, 1, 0, 0, 2, 0, // Skip to: 4181
1865
/* 3669 */    MCD_OPC_Decode, 188, 12, 114, // Opcode: EE_VMIN_S32
1866
/* 3673 */    MCD_OPC_FilterValue, 20, 247, 1, 0, // Skip to: 4181
1867
/* 3678 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1868
/* 3681 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3702
1869
/* 3686 */    MCD_OPC_CheckPredicate, 22, 234, 1, 0, // Skip to: 4181
1870
/* 3691 */    MCD_OPC_CheckField, 22, 1, 0, 227, 1, 0, // Skip to: 4181
1871
/* 3698 */    MCD_OPC_Decode, 145, 12, 114, // Opcode: EE_VADDS_S32
1872
/* 3702 */    MCD_OPC_FilterValue, 1, 218, 1, 0, // Skip to: 4181
1873
/* 3707 */    MCD_OPC_CheckPredicate, 22, 213, 1, 0, // Skip to: 4181
1874
/* 3712 */    MCD_OPC_CheckField, 22, 1, 0, 206, 1, 0, // Skip to: 4181
1875
/* 3719 */    MCD_OPC_Decode, 191, 12, 114, // Opcode: EE_VMIN_S8
1876
/* 3723 */    MCD_OPC_FilterValue, 2, 203, 0, 0, // Skip to: 3931
1877
/* 3728 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
1878
/* 3731 */    MCD_OPC_FilterValue, 4, 45, 0, 0, // Skip to: 3781
1879
/* 3736 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1880
/* 3739 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3760
1881
/* 3744 */    MCD_OPC_CheckPredicate, 22, 176, 1, 0, // Skip to: 4181
1882
/* 3749 */    MCD_OPC_CheckField, 22, 1, 0, 169, 1, 0, // Skip to: 4181
1883
/* 3756 */    MCD_OPC_Decode, 148, 12, 114, // Opcode: EE_VADDS_S8
1884
/* 3760 */    MCD_OPC_FilterValue, 1, 160, 1, 0, // Skip to: 4181
1885
/* 3765 */    MCD_OPC_CheckPredicate, 22, 155, 1, 0, // Skip to: 4181
1886
/* 3770 */    MCD_OPC_CheckField, 22, 1, 0, 148, 1, 0, // Skip to: 4181
1887
/* 3777 */    MCD_OPC_Decode, 242, 12, 114, // Opcode: EE_VMUL_S16
1888
/* 3781 */    MCD_OPC_FilterValue, 20, 45, 0, 0, // Skip to: 3831
1889
/* 3786 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1890
/* 3789 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3810
1891
/* 3794 */    MCD_OPC_CheckPredicate, 22, 126, 1, 0, // Skip to: 4181
1892
/* 3799 */    MCD_OPC_CheckField, 22, 1, 0, 119, 1, 0, // Skip to: 4181
1893
/* 3806 */    MCD_OPC_Decode, 151, 12, 114, // Opcode: EE_VCMP_EQ_S16
1894
/* 3810 */    MCD_OPC_FilterValue, 1, 110, 1, 0, // Skip to: 4181
1895
/* 3815 */    MCD_OPC_CheckPredicate, 22, 105, 1, 0, // Skip to: 4181
1896
/* 3820 */    MCD_OPC_CheckField, 22, 1, 0, 98, 1, 0, // Skip to: 4181
1897
/* 3827 */    MCD_OPC_Decode, 245, 12, 114, // Opcode: EE_VMUL_S8
1898
/* 3831 */    MCD_OPC_FilterValue, 36, 45, 0, 0, // Skip to: 3881
1899
/* 3836 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1900
/* 3839 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3860
1901
/* 3844 */    MCD_OPC_CheckPredicate, 22, 76, 1, 0, // Skip to: 4181
1902
/* 3849 */    MCD_OPC_CheckField, 22, 1, 0, 69, 1, 0, // Skip to: 4181
1903
/* 3856 */    MCD_OPC_Decode, 152, 12, 114, // Opcode: EE_VCMP_EQ_S32
1904
/* 3860 */    MCD_OPC_FilterValue, 1, 60, 1, 0, // Skip to: 4181
1905
/* 3865 */    MCD_OPC_CheckPredicate, 22, 55, 1, 0, // Skip to: 4181
1906
/* 3870 */    MCD_OPC_CheckField, 22, 1, 0, 48, 1, 0, // Skip to: 4181
1907
/* 3877 */    MCD_OPC_Decode, 248, 12, 114, // Opcode: EE_VMUL_U16
1908
/* 3881 */    MCD_OPC_FilterValue, 52, 39, 1, 0, // Skip to: 4181
1909
/* 3886 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1910
/* 3889 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3910
1911
/* 3894 */    MCD_OPC_CheckPredicate, 22, 26, 1, 0, // Skip to: 4181
1912
/* 3899 */    MCD_OPC_CheckField, 22, 1, 0, 19, 1, 0, // Skip to: 4181
1913
/* 3906 */    MCD_OPC_Decode, 153, 12, 114, // Opcode: EE_VCMP_EQ_S8
1914
/* 3910 */    MCD_OPC_FilterValue, 1, 10, 1, 0, // Skip to: 4181
1915
/* 3915 */    MCD_OPC_CheckPredicate, 22, 5, 1, 0, // Skip to: 4181
1916
/* 3920 */    MCD_OPC_CheckField, 22, 1, 0, 254, 0, 0, // Skip to: 4181
1917
/* 3927 */    MCD_OPC_Decode, 251, 12, 114, // Opcode: EE_VMUL_U8
1918
/* 3931 */    MCD_OPC_FilterValue, 3, 245, 0, 0, // Skip to: 4181
1919
/* 3936 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
1920
/* 3939 */    MCD_OPC_FilterValue, 4, 45, 0, 0, // Skip to: 3989
1921
/* 3944 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1922
/* 3947 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3968
1923
/* 3952 */    MCD_OPC_CheckPredicate, 22, 224, 0, 0, // Skip to: 4181
1924
/* 3957 */    MCD_OPC_CheckField, 22, 1, 0, 217, 0, 0, // Skip to: 4181
1925
/* 3964 */    MCD_OPC_Decode, 154, 12, 114, // Opcode: EE_VCMP_GT_S16
1926
/* 3968 */    MCD_OPC_FilterValue, 1, 208, 0, 0, // Skip to: 4181
1927
/* 3973 */    MCD_OPC_CheckPredicate, 22, 203, 0, 0, // Skip to: 4181
1928
/* 3978 */    MCD_OPC_CheckField, 22, 1, 0, 196, 0, 0, // Skip to: 4181
1929
/* 3985 */    MCD_OPC_Decode, 131, 13, 116, // Opcode: EE_VSMULAS_S16_QACC
1930
/* 3989 */    MCD_OPC_FilterValue, 20, 45, 0, 0, // Skip to: 4039
1931
/* 3994 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1932
/* 3997 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4018
1933
/* 4002 */    MCD_OPC_CheckPredicate, 22, 174, 0, 0, // Skip to: 4181
1934
/* 4007 */    MCD_OPC_CheckField, 22, 1, 0, 167, 0, 0, // Skip to: 4181
1935
/* 4014 */    MCD_OPC_Decode, 155, 12, 114, // Opcode: EE_VCMP_GT_S32
1936
/* 4018 */    MCD_OPC_FilterValue, 1, 158, 0, 0, // Skip to: 4181
1937
/* 4023 */    MCD_OPC_CheckPredicate, 22, 153, 0, 0, // Skip to: 4181
1938
/* 4028 */    MCD_OPC_CheckField, 22, 1, 0, 146, 0, 0, // Skip to: 4181
1939
/* 4035 */    MCD_OPC_Decode, 142, 13, 114, // Opcode: EE_VSUBS_S16
1940
/* 4039 */    MCD_OPC_FilterValue, 36, 45, 0, 0, // Skip to: 4089
1941
/* 4044 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1942
/* 4047 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4068
1943
/* 4052 */    MCD_OPC_CheckPredicate, 22, 124, 0, 0, // Skip to: 4181
1944
/* 4057 */    MCD_OPC_CheckField, 22, 1, 0, 117, 0, 0, // Skip to: 4181
1945
/* 4064 */    MCD_OPC_Decode, 156, 12, 114, // Opcode: EE_VCMP_GT_S8
1946
/* 4068 */    MCD_OPC_FilterValue, 1, 108, 0, 0, // Skip to: 4181
1947
/* 4073 */    MCD_OPC_CheckPredicate, 22, 103, 0, 0, // Skip to: 4181
1948
/* 4078 */    MCD_OPC_CheckField, 22, 1, 0, 96, 0, 0, // Skip to: 4181
1949
/* 4085 */    MCD_OPC_Decode, 145, 13, 114, // Opcode: EE_VSUBS_S32
1950
/* 4089 */    MCD_OPC_FilterValue, 52, 87, 0, 0, // Skip to: 4181
1951
/* 4094 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
1952
/* 4097 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4118
1953
/* 4102 */    MCD_OPC_CheckPredicate, 22, 74, 0, 0, // Skip to: 4181
1954
/* 4107 */    MCD_OPC_CheckField, 22, 1, 0, 67, 0, 0, // Skip to: 4181
1955
/* 4114 */    MCD_OPC_Decode, 157, 12, 114, // Opcode: EE_VCMP_LT_S16
1956
/* 4118 */    MCD_OPC_FilterValue, 1, 58, 0, 0, // Skip to: 4181
1957
/* 4123 */    MCD_OPC_CheckPredicate, 22, 53, 0, 0, // Skip to: 4181
1958
/* 4128 */    MCD_OPC_CheckField, 22, 1, 0, 46, 0, 0, // Skip to: 4181
1959
/* 4135 */    MCD_OPC_Decode, 148, 13, 114, // Opcode: EE_VSUBS_S8
1960
/* 4139 */    MCD_OPC_FilterValue, 15, 37, 0, 0, // Skip to: 4181
1961
/* 4144 */    MCD_OPC_CheckPredicate, 22, 32, 0, 0, // Skip to: 4181
1962
/* 4149 */    MCD_OPC_CheckField, 22, 2, 2, 25, 0, 0, // Skip to: 4181
1963
/* 4156 */    MCD_OPC_CheckField, 12, 3, 0, 18, 0, 0, // Skip to: 4181
1964
/* 4163 */    MCD_OPC_CheckField, 6, 4, 0, 11, 0, 0, // Skip to: 4181
1965
/* 4170 */    MCD_OPC_CheckField, 0, 5, 4, 4, 0, 0, // Skip to: 4181
1966
/* 4177 */    MCD_OPC_Decode, 198, 15, 117, // Opcode: mv_QR
1967
/* 4181 */    MCD_OPC_Fail,
1968
  0
1969
};
1970
1971
static const uint8_t DecoderTableESP32S332[] = {
1972
/* 0 */       MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
1973
/* 3 */       MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 24
1974
/* 8 */       MCD_OPC_CheckPredicate, 22, 102, 9, 0, // Skip to: 2419
1975
/* 13 */      MCD_OPC_CheckField, 1, 3, 7, 95, 9, 0, // Skip to: 2419
1976
/* 20 */      MCD_OPC_Decode, 196, 12, 118, // Opcode: EE_VMULAS_S16_ACCX_LD_IP_QUP
1977
/* 24 */      MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 45
1978
/* 29 */      MCD_OPC_CheckPredicate, 22, 81, 9, 0, // Skip to: 2419
1979
/* 34 */      MCD_OPC_CheckField, 1, 3, 7, 74, 9, 0, // Skip to: 2419
1980
/* 41 */      MCD_OPC_Decode, 203, 12, 118, // Opcode: EE_VMULAS_S16_QACC_LD_IP_QUP
1981
/* 45 */      MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 66
1982
/* 50 */      MCD_OPC_CheckPredicate, 22, 60, 9, 0, // Skip to: 2419
1983
/* 55 */      MCD_OPC_CheckField, 1, 3, 7, 53, 9, 0, // Skip to: 2419
1984
/* 62 */      MCD_OPC_Decode, 208, 12, 118, // Opcode: EE_VMULAS_S8_ACCX_LD_IP_QUP
1985
/* 66 */      MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 87
1986
/* 71 */      MCD_OPC_CheckPredicate, 22, 39, 9, 0, // Skip to: 2419
1987
/* 76 */      MCD_OPC_CheckField, 1, 3, 7, 32, 9, 0, // Skip to: 2419
1988
/* 83 */      MCD_OPC_Decode, 215, 12, 118, // Opcode: EE_VMULAS_S8_QACC_LD_IP_QUP
1989
/* 87 */      MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 108
1990
/* 92 */      MCD_OPC_CheckPredicate, 22, 18, 9, 0, // Skip to: 2419
1991
/* 97 */      MCD_OPC_CheckField, 1, 3, 7, 11, 9, 0, // Skip to: 2419
1992
/* 104 */     MCD_OPC_Decode, 220, 12, 118, // Opcode: EE_VMULAS_U16_ACCX_LD_IP_QUP
1993
/* 108 */     MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 129
1994
/* 113 */     MCD_OPC_CheckPredicate, 22, 253, 8, 0, // Skip to: 2419
1995
/* 118 */     MCD_OPC_CheckField, 1, 3, 7, 246, 8, 0, // Skip to: 2419
1996
/* 125 */     MCD_OPC_Decode, 227, 12, 118, // Opcode: EE_VMULAS_U16_QACC_LD_IP_QUP
1997
/* 129 */     MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 150
1998
/* 134 */     MCD_OPC_CheckPredicate, 22, 232, 8, 0, // Skip to: 2419
1999
/* 139 */     MCD_OPC_CheckField, 1, 3, 7, 225, 8, 0, // Skip to: 2419
2000
/* 146 */     MCD_OPC_Decode, 232, 12, 118, // Opcode: EE_VMULAS_U8_ACCX_LD_IP_QUP
2001
/* 150 */     MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 171
2002
/* 155 */     MCD_OPC_CheckPredicate, 22, 211, 8, 0, // Skip to: 2419
2003
/* 160 */     MCD_OPC_CheckField, 1, 3, 7, 204, 8, 0, // Skip to: 2419
2004
/* 167 */     MCD_OPC_Decode, 239, 12, 118, // Opcode: EE_VMULAS_U8_QACC_LD_IP_QUP
2005
/* 171 */     MCD_OPC_FilterValue, 8, 45, 0, 0, // Skip to: 221
2006
/* 176 */     MCD_OPC_ExtractField, 27, 1,  // Inst{27} ...
2007
/* 179 */     MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 200
2008
/* 184 */     MCD_OPC_CheckPredicate, 22, 182, 8, 0, // Skip to: 2419
2009
/* 189 */     MCD_OPC_CheckField, 1, 3, 7, 175, 8, 0, // Skip to: 2419
2010
/* 196 */     MCD_OPC_Decode, 217, 11, 119, // Opcode: EE_LDF_128_IP
2011
/* 200 */     MCD_OPC_FilterValue, 1, 166, 8, 0, // Skip to: 2419
2012
/* 205 */     MCD_OPC_CheckPredicate, 22, 161, 8, 0, // Skip to: 2419
2013
/* 210 */     MCD_OPC_CheckField, 1, 3, 7, 154, 8, 0, // Skip to: 2419
2014
/* 217 */     MCD_OPC_Decode, 218, 11, 120, // Opcode: EE_LDF_128_XP
2015
/* 221 */     MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 271
2016
/* 226 */     MCD_OPC_ExtractField, 27, 1,  // Inst{27} ...
2017
/* 229 */     MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 250
2018
/* 234 */     MCD_OPC_CheckPredicate, 22, 132, 8, 0, // Skip to: 2419
2019
/* 239 */     MCD_OPC_CheckField, 1, 3, 7, 125, 8, 0, // Skip to: 2419
2020
/* 246 */     MCD_OPC_Decode, 131, 12, 121, // Opcode: EE_STF_128_IP
2021
/* 250 */     MCD_OPC_FilterValue, 1, 116, 8, 0, // Skip to: 2419
2022
/* 255 */     MCD_OPC_CheckPredicate, 22, 111, 8, 0, // Skip to: 2419
2023
/* 260 */     MCD_OPC_CheckField, 1, 3, 7, 104, 8, 0, // Skip to: 2419
2024
/* 267 */     MCD_OPC_Decode, 132, 12, 122, // Opcode: EE_STF_128_XP
2025
/* 271 */     MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 321
2026
/* 276 */     MCD_OPC_ExtractField, 27, 1,  // Inst{27} ...
2027
/* 279 */     MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 300
2028
/* 284 */     MCD_OPC_CheckPredicate, 22, 82, 8, 0, // Skip to: 2419
2029
/* 289 */     MCD_OPC_CheckField, 1, 3, 7, 75, 8, 0, // Skip to: 2419
2030
/* 296 */     MCD_OPC_Decode, 210, 11, 123, // Opcode: EE_FFT_AMS_S16_ST_INCP
2031
/* 300 */     MCD_OPC_FilterValue, 1, 66, 8, 0, // Skip to: 2419
2032
/* 305 */     MCD_OPC_CheckPredicate, 22, 61, 8, 0, // Skip to: 2419
2033
/* 310 */     MCD_OPC_CheckField, 1, 3, 7, 54, 8, 0, // Skip to: 2419
2034
/* 317 */     MCD_OPC_Decode, 212, 11, 124, // Opcode: EE_FFT_CMUL_S16_ST_XP
2035
/* 321 */     MCD_OPC_FilterValue, 11, 87, 0, 0, // Skip to: 413
2036
/* 326 */     MCD_OPC_ExtractField, 26, 2,  // Inst{27-26} ...
2037
/* 329 */     MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 350
2038
/* 334 */     MCD_OPC_CheckPredicate, 22, 32, 8, 0, // Skip to: 2419
2039
/* 339 */     MCD_OPC_CheckField, 1, 3, 7, 25, 8, 0, // Skip to: 2419
2040
/* 346 */     MCD_OPC_Decode, 198, 12, 125, // Opcode: EE_VMULAS_S16_ACCX_LD_XP_QUP
2041
/* 350 */     MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 371
2042
/* 355 */     MCD_OPC_CheckPredicate, 22, 11, 8, 0, // Skip to: 2419
2043
/* 360 */     MCD_OPC_CheckField, 1, 3, 7, 4, 8, 0, // Skip to: 2419
2044
/* 367 */     MCD_OPC_Decode, 205, 12, 125, // Opcode: EE_VMULAS_S16_QACC_LD_XP_QUP
2045
/* 371 */     MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 392
2046
/* 376 */     MCD_OPC_CheckPredicate, 22, 246, 7, 0, // Skip to: 2419
2047
/* 381 */     MCD_OPC_CheckField, 1, 3, 7, 239, 7, 0, // Skip to: 2419
2048
/* 388 */     MCD_OPC_Decode, 210, 12, 125, // Opcode: EE_VMULAS_S8_ACCX_LD_XP_QUP
2049
/* 392 */     MCD_OPC_FilterValue, 3, 230, 7, 0, // Skip to: 2419
2050
/* 397 */     MCD_OPC_CheckPredicate, 22, 225, 7, 0, // Skip to: 2419
2051
/* 402 */     MCD_OPC_CheckField, 1, 3, 7, 218, 7, 0, // Skip to: 2419
2052
/* 409 */     MCD_OPC_Decode, 217, 12, 125, // Opcode: EE_VMULAS_S8_QACC_LD_XP_QUP
2053
/* 413 */     MCD_OPC_FilterValue, 12, 87, 0, 0, // Skip to: 505
2054
/* 418 */     MCD_OPC_ExtractField, 26, 2,  // Inst{27-26} ...
2055
/* 421 */     MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 442
2056
/* 426 */     MCD_OPC_CheckPredicate, 22, 196, 7, 0, // Skip to: 2419
2057
/* 431 */     MCD_OPC_CheckField, 1, 3, 7, 189, 7, 0, // Skip to: 2419
2058
/* 438 */     MCD_OPC_Decode, 222, 12, 125, // Opcode: EE_VMULAS_U16_ACCX_LD_XP_QUP
2059
/* 442 */     MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 463
2060
/* 447 */     MCD_OPC_CheckPredicate, 22, 175, 7, 0, // Skip to: 2419
2061
/* 452 */     MCD_OPC_CheckField, 1, 3, 7, 168, 7, 0, // Skip to: 2419
2062
/* 459 */     MCD_OPC_Decode, 229, 12, 125, // Opcode: EE_VMULAS_U16_QACC_LD_XP_QUP
2063
/* 463 */     MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 484
2064
/* 468 */     MCD_OPC_CheckPredicate, 22, 154, 7, 0, // Skip to: 2419
2065
/* 473 */     MCD_OPC_CheckField, 1, 3, 7, 147, 7, 0, // Skip to: 2419
2066
/* 480 */     MCD_OPC_Decode, 234, 12, 125, // Opcode: EE_VMULAS_U8_ACCX_LD_XP_QUP
2067
/* 484 */     MCD_OPC_FilterValue, 3, 138, 7, 0, // Skip to: 2419
2068
/* 489 */     MCD_OPC_CheckPredicate, 22, 133, 7, 0, // Skip to: 2419
2069
/* 494 */     MCD_OPC_CheckField, 1, 3, 7, 126, 7, 0, // Skip to: 2419
2070
/* 501 */     MCD_OPC_Decode, 241, 12, 125, // Opcode: EE_VMULAS_U8_QACC_LD_XP_QUP
2071
/* 505 */     MCD_OPC_FilterValue, 13, 87, 0, 0, // Skip to: 597
2072
/* 510 */     MCD_OPC_ExtractField, 26, 2,  // Inst{27-26} ...
2073
/* 513 */     MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 534
2074
/* 518 */     MCD_OPC_CheckPredicate, 22, 104, 7, 0, // Skip to: 2419
2075
/* 523 */     MCD_OPC_CheckField, 1, 3, 7, 97, 7, 0, // Skip to: 2419
2076
/* 530 */     MCD_OPC_Decode, 207, 11, 126, // Opcode: EE_FFT_AMS_S16_LD_INCP
2077
/* 534 */     MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 555
2078
/* 539 */     MCD_OPC_CheckPredicate, 22, 83, 7, 0, // Skip to: 2419
2079
/* 544 */     MCD_OPC_CheckField, 1, 3, 7, 76, 7, 0, // Skip to: 2419
2080
/* 551 */     MCD_OPC_Decode, 208, 11, 126, // Opcode: EE_FFT_AMS_S16_LD_INCP_UAUP
2081
/* 555 */     MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 576
2082
/* 560 */     MCD_OPC_CheckPredicate, 22, 62, 7, 0, // Skip to: 2419
2083
/* 565 */     MCD_OPC_CheckField, 1, 3, 7, 55, 7, 0, // Skip to: 2419
2084
/* 572 */     MCD_OPC_Decode, 209, 11, 126, // Opcode: EE_FFT_AMS_S16_LD_R32_DECP
2085
/* 576 */     MCD_OPC_FilterValue, 3, 46, 7, 0, // Skip to: 2419
2086
/* 581 */     MCD_OPC_CheckPredicate, 22, 41, 7, 0, // Skip to: 2419
2087
/* 586 */     MCD_OPC_CheckField, 1, 3, 7, 34, 7, 0, // Skip to: 2419
2088
/* 593 */     MCD_OPC_Decode, 211, 11, 127, // Opcode: EE_FFT_CMUL_S16_LD_XP
2089
/* 597 */     MCD_OPC_FilterValue, 14, 57, 5, 0, // Skip to: 1939
2090
/* 602 */     MCD_OPC_ExtractField, 26, 2,  // Inst{27-26} ...
2091
/* 605 */     MCD_OPC_FilterValue, 0, 212, 2, 0, // Skip to: 1334
2092
/* 610 */     MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
2093
/* 613 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 635
2094
/* 618 */     MCD_OPC_CheckPredicate, 22, 4, 7, 0, // Skip to: 2419
2095
/* 623 */     MCD_OPC_CheckField, 1, 3, 7, 253, 6, 0, // Skip to: 2419
2096
/* 630 */     MCD_OPC_Decode, 255, 11, 128, 1, // Opcode: EE_SRC_Q_LD_IP
2097
/* 635 */     MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 687
2098
/* 640 */     MCD_OPC_ExtractField, 9, 1,  // Inst{9} ...
2099
/* 643 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 665
2100
/* 648 */     MCD_OPC_CheckPredicate, 22, 230, 6, 0, // Skip to: 2419
2101
/* 653 */     MCD_OPC_CheckField, 1, 3, 7, 223, 6, 0, // Skip to: 2419
2102
/* 660 */     MCD_OPC_Decode, 219, 11, 129, 1, // Opcode: EE_LDF_64_IP
2103
/* 665 */     MCD_OPC_FilterValue, 1, 213, 6, 0, // Skip to: 2419
2104
/* 670 */     MCD_OPC_CheckPredicate, 22, 208, 6, 0, // Skip to: 2419
2105
/* 675 */     MCD_OPC_CheckField, 1, 3, 7, 201, 6, 0, // Skip to: 2419
2106
/* 682 */     MCD_OPC_Decode, 133, 12, 130, 1, // Opcode: EE_STF_64_IP
2107
/* 687 */     MCD_OPC_FilterValue, 2, 91, 0, 0, // Skip to: 783
2108
/* 692 */     MCD_OPC_ExtractField, 8, 2,  // Inst{9-8} ...
2109
/* 695 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 717
2110
/* 700 */     MCD_OPC_CheckPredicate, 22, 178, 6, 0, // Skip to: 2419
2111
/* 705 */     MCD_OPC_CheckField, 1, 3, 7, 171, 6, 0, // Skip to: 2419
2112
/* 712 */     MCD_OPC_Decode, 201, 12, 131, 1, // Opcode: EE_VMULAS_S16_QACC_LDBC_INCP_QUP
2113
/* 717 */     MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 739
2114
/* 722 */     MCD_OPC_CheckPredicate, 22, 156, 6, 0, // Skip to: 2419
2115
/* 727 */     MCD_OPC_CheckField, 1, 3, 7, 149, 6, 0, // Skip to: 2419
2116
/* 734 */     MCD_OPC_Decode, 213, 12, 131, 1, // Opcode: EE_VMULAS_S8_QACC_LDBC_INCP_QUP
2117
/* 739 */     MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 761
2118
/* 744 */     MCD_OPC_CheckPredicate, 22, 134, 6, 0, // Skip to: 2419
2119
/* 749 */     MCD_OPC_CheckField, 1, 3, 7, 127, 6, 0, // Skip to: 2419
2120
/* 756 */     MCD_OPC_Decode, 225, 12, 131, 1, // Opcode: EE_VMULAS_U16_QACC_LDBC_INCP_QUP
2121
/* 761 */     MCD_OPC_FilterValue, 3, 117, 6, 0, // Skip to: 2419
2122
/* 766 */     MCD_OPC_CheckPredicate, 22, 112, 6, 0, // Skip to: 2419
2123
/* 771 */     MCD_OPC_CheckField, 1, 3, 7, 105, 6, 0, // Skip to: 2419
2124
/* 778 */     MCD_OPC_Decode, 237, 12, 131, 1, // Opcode: EE_VMULAS_U8_QACC_LDBC_INCP_QUP
2125
/* 783 */     MCD_OPC_FilterValue, 3, 95, 6, 0, // Skip to: 2419
2126
/* 788 */     MCD_OPC_ExtractField, 21, 2,  // Inst{22-21} ...
2127
/* 791 */     MCD_OPC_FilterValue, 0, 121, 0, 0, // Skip to: 917
2128
/* 796 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
2129
/* 799 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 821
2130
/* 804 */     MCD_OPC_CheckPredicate, 22, 74, 6, 0, // Skip to: 2419
2131
/* 809 */     MCD_OPC_CheckField, 1, 3, 7, 67, 6, 0, // Skip to: 2419
2132
/* 816 */     MCD_OPC_Decode, 205, 11, 132, 1, // Opcode: EE_CMUL_S16_LD_INCP
2133
/* 821 */     MCD_OPC_FilterValue, 1, 57, 6, 0, // Skip to: 2419
2134
/* 826 */     MCD_OPC_ExtractField, 8, 2,  // Inst{9-8} ...
2135
/* 829 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 851
2136
/* 834 */     MCD_OPC_CheckPredicate, 22, 44, 6, 0, // Skip to: 2419
2137
/* 839 */     MCD_OPC_CheckField, 1, 3, 7, 37, 6, 0, // Skip to: 2419
2138
/* 846 */     MCD_OPC_Decode, 149, 12, 133, 1, // Opcode: EE_VADDS_S8_LD_INCP
2139
/* 851 */     MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 873
2140
/* 856 */     MCD_OPC_CheckPredicate, 22, 22, 6, 0, // Skip to: 2419
2141
/* 861 */     MCD_OPC_CheckField, 1, 3, 7, 15, 6, 0, // Skip to: 2419
2142
/* 868 */     MCD_OPC_Decode, 177, 12, 133, 1, // Opcode: EE_VMAX_S16_LD_INCP
2143
/* 873 */     MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 895
2144
/* 878 */     MCD_OPC_CheckPredicate, 22, 0, 6, 0, // Skip to: 2419
2145
/* 883 */     MCD_OPC_CheckField, 1, 3, 7, 249, 5, 0, // Skip to: 2419
2146
/* 890 */     MCD_OPC_Decode, 180, 12, 133, 1, // Opcode: EE_VMAX_S32_LD_INCP
2147
/* 895 */     MCD_OPC_FilterValue, 3, 239, 5, 0, // Skip to: 2419
2148
/* 900 */     MCD_OPC_CheckPredicate, 22, 234, 5, 0, // Skip to: 2419
2149
/* 905 */     MCD_OPC_CheckField, 1, 3, 7, 227, 5, 0, // Skip to: 2419
2150
/* 912 */     MCD_OPC_Decode, 183, 12, 133, 1, // Opcode: EE_VMAX_S8_LD_INCP
2151
/* 917 */     MCD_OPC_FilterValue, 1, 181, 0, 0, // Skip to: 1103
2152
/* 922 */     MCD_OPC_ExtractField, 8, 2,  // Inst{9-8} ...
2153
/* 925 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 947
2154
/* 930 */     MCD_OPC_CheckPredicate, 22, 204, 5, 0, // Skip to: 2419
2155
/* 935 */     MCD_OPC_CheckField, 1, 3, 7, 197, 5, 0, // Skip to: 2419
2156
/* 942 */     MCD_OPC_Decode, 134, 13, 134, 1, // Opcode: EE_VSMULAS_S8_QACC_LD_INCP
2157
/* 947 */     MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 999
2158
/* 952 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
2159
/* 955 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 977
2160
/* 960 */     MCD_OPC_CheckPredicate, 22, 174, 5, 0, // Skip to: 2419
2161
/* 965 */     MCD_OPC_CheckField, 1, 3, 7, 167, 5, 0, // Skip to: 2419
2162
/* 972 */     MCD_OPC_Decode, 143, 12, 133, 1, // Opcode: EE_VADDS_S16_LD_INCP
2163
/* 977 */     MCD_OPC_FilterValue, 1, 157, 5, 0, // Skip to: 2419
2164
/* 982 */     MCD_OPC_CheckPredicate, 22, 152, 5, 0, // Skip to: 2419
2165
/* 987 */     MCD_OPC_CheckField, 1, 3, 7, 145, 5, 0, // Skip to: 2419
2166
/* 994 */     MCD_OPC_Decode, 146, 12, 133, 1, // Opcode: EE_VADDS_S32_LD_INCP
2167
/* 999 */     MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 1051
2168
/* 1004 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
2169
/* 1007 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1029
2170
/* 1012 */    MCD_OPC_CheckPredicate, 22, 122, 5, 0, // Skip to: 2419
2171
/* 1017 */    MCD_OPC_CheckField, 1, 3, 7, 115, 5, 0, // Skip to: 2419
2172
/* 1024 */    MCD_OPC_Decode, 186, 12, 133, 1, // Opcode: EE_VMIN_S16_LD_INCP
2173
/* 1029 */    MCD_OPC_FilterValue, 1, 105, 5, 0, // Skip to: 2419
2174
/* 1034 */    MCD_OPC_CheckPredicate, 22, 100, 5, 0, // Skip to: 2419
2175
/* 1039 */    MCD_OPC_CheckField, 1, 3, 7, 93, 5, 0, // Skip to: 2419
2176
/* 1046 */    MCD_OPC_Decode, 189, 12, 133, 1, // Opcode: EE_VMIN_S32_LD_INCP
2177
/* 1051 */    MCD_OPC_FilterValue, 3, 83, 5, 0, // Skip to: 2419
2178
/* 1056 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
2179
/* 1059 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1081
2180
/* 1064 */    MCD_OPC_CheckPredicate, 22, 70, 5, 0, // Skip to: 2419
2181
/* 1069 */    MCD_OPC_CheckField, 1, 3, 7, 63, 5, 0, // Skip to: 2419
2182
/* 1076 */    MCD_OPC_Decode, 192, 12, 133, 1, // Opcode: EE_VMIN_S8_LD_INCP
2183
/* 1081 */    MCD_OPC_FilterValue, 1, 53, 5, 0, // Skip to: 2419
2184
/* 1086 */    MCD_OPC_CheckPredicate, 22, 48, 5, 0, // Skip to: 2419
2185
/* 1091 */    MCD_OPC_CheckField, 1, 3, 7, 41, 5, 0, // Skip to: 2419
2186
/* 1098 */    MCD_OPC_Decode, 243, 12, 133, 1, // Opcode: EE_VMUL_S16_LD_INCP
2187
/* 1103 */    MCD_OPC_FilterValue, 2, 107, 0, 0, // Skip to: 1215
2188
/* 1108 */    MCD_OPC_ExtractField, 8, 2,  // Inst{9-8} ...
2189
/* 1111 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 1163
2190
/* 1116 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
2191
/* 1119 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1141
2192
/* 1124 */    MCD_OPC_CheckPredicate, 22, 10, 5, 0, // Skip to: 2419
2193
/* 1129 */    MCD_OPC_CheckField, 1, 3, 7, 3, 5, 0, // Skip to: 2419
2194
/* 1136 */    MCD_OPC_Decode, 246, 12, 133, 1, // Opcode: EE_VMUL_S8_LD_INCP
2195
/* 1141 */    MCD_OPC_FilterValue, 1, 249, 4, 0, // Skip to: 2419
2196
/* 1146 */    MCD_OPC_CheckPredicate, 22, 244, 4, 0, // Skip to: 2419
2197
/* 1151 */    MCD_OPC_CheckField, 1, 3, 7, 237, 4, 0, // Skip to: 2419
2198
/* 1158 */    MCD_OPC_Decode, 249, 12, 133, 1, // Opcode: EE_VMUL_U16_LD_INCP
2199
/* 1163 */    MCD_OPC_FilterValue, 1, 227, 4, 0, // Skip to: 2419
2200
/* 1168 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
2201
/* 1171 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1193
2202
/* 1176 */    MCD_OPC_CheckPredicate, 22, 214, 4, 0, // Skip to: 2419
2203
/* 1181 */    MCD_OPC_CheckField, 1, 3, 7, 207, 4, 0, // Skip to: 2419
2204
/* 1188 */    MCD_OPC_Decode, 143, 13, 133, 1, // Opcode: EE_VSUBS_S16_LD_INCP
2205
/* 1193 */    MCD_OPC_FilterValue, 1, 197, 4, 0, // Skip to: 2419
2206
/* 1198 */    MCD_OPC_CheckPredicate, 22, 192, 4, 0, // Skip to: 2419
2207
/* 1203 */    MCD_OPC_CheckField, 1, 3, 7, 185, 4, 0, // Skip to: 2419
2208
/* 1210 */    MCD_OPC_Decode, 146, 13, 133, 1, // Opcode: EE_VSUBS_S32_LD_INCP
2209
/* 1215 */    MCD_OPC_FilterValue, 3, 175, 4, 0, // Skip to: 2419
2210
/* 1220 */    MCD_OPC_ExtractField, 8, 2,  // Inst{9-8} ...
2211
/* 1223 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 1275
2212
/* 1228 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
2213
/* 1231 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1253
2214
/* 1236 */    MCD_OPC_CheckPredicate, 22, 154, 4, 0, // Skip to: 2419
2215
/* 1241 */    MCD_OPC_CheckField, 1, 3, 7, 147, 4, 0, // Skip to: 2419
2216
/* 1248 */    MCD_OPC_Decode, 252, 12, 133, 1, // Opcode: EE_VMUL_U8_LD_INCP
2217
/* 1253 */    MCD_OPC_FilterValue, 1, 137, 4, 0, // Skip to: 2419
2218
/* 1258 */    MCD_OPC_CheckPredicate, 22, 132, 4, 0, // Skip to: 2419
2219
/* 1263 */    MCD_OPC_CheckField, 1, 3, 7, 125, 4, 0, // Skip to: 2419
2220
/* 1270 */    MCD_OPC_Decode, 132, 13, 135, 1, // Opcode: EE_VSMULAS_S16_QACC_LD_INCP
2221
/* 1275 */    MCD_OPC_FilterValue, 1, 115, 4, 0, // Skip to: 2419
2222
/* 1280 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
2223
/* 1283 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1305
2224
/* 1288 */    MCD_OPC_CheckPredicate, 22, 102, 4, 0, // Skip to: 2419
2225
/* 1293 */    MCD_OPC_CheckField, 1, 3, 7, 95, 4, 0, // Skip to: 2419
2226
/* 1300 */    MCD_OPC_Decode, 149, 13, 133, 1, // Opcode: EE_VSUBS_S8_LD_INCP
2227
/* 1305 */    MCD_OPC_FilterValue, 1, 85, 4, 0, // Skip to: 2419
2228
/* 1310 */    MCD_OPC_CheckPredicate, 22, 80, 4, 0, // Skip to: 2419
2229
/* 1315 */    MCD_OPC_CheckField, 25, 1, 0, 73, 4, 0, // Skip to: 2419
2230
/* 1322 */    MCD_OPC_CheckField, 1, 3, 7, 66, 4, 0, // Skip to: 2419
2231
/* 1329 */    MCD_OPC_Decode, 229, 11, 136, 1, // Opcode: EE_LDXQ_32
2232
/* 1334 */    MCD_OPC_FilterValue, 1, 140, 1, 0, // Skip to: 1735
2233
/* 1339 */    MCD_OPC_ExtractField, 25, 1,  // Inst{25} ...
2234
/* 1342 */    MCD_OPC_FilterValue, 0, 96, 1, 0, // Skip to: 1699
2235
/* 1347 */    MCD_OPC_ExtractField, 19, 1,  // Inst{19} ...
2236
/* 1350 */    MCD_OPC_FilterValue, 0, 128, 0, 0, // Skip to: 1483
2237
/* 1355 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
2238
/* 1358 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1387
2239
/* 1363 */    MCD_OPC_CheckPredicate, 22, 27, 4, 0, // Skip to: 2419
2240
/* 1368 */    MCD_OPC_CheckField, 10, 2, 0, 20, 4, 0, // Skip to: 2419
2241
/* 1375 */    MCD_OPC_CheckField, 1, 3, 7, 13, 4, 0, // Skip to: 2419
2242
/* 1382 */    MCD_OPC_Decode, 206, 11, 137, 1, // Opcode: EE_CMUL_S16_ST_INCP
2243
/* 1387 */    MCD_OPC_FilterValue, 1, 3, 4, 0, // Skip to: 2419
2244
/* 1392 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
2245
/* 1395 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1417
2246
/* 1400 */    MCD_OPC_CheckPredicate, 22, 246, 3, 0, // Skip to: 2419
2247
/* 1405 */    MCD_OPC_CheckField, 1, 3, 7, 239, 3, 0, // Skip to: 2419
2248
/* 1412 */    MCD_OPC_Decode, 181, 12, 138, 1, // Opcode: EE_VMAX_S32_ST_INCP
2249
/* 1417 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1439
2250
/* 1422 */    MCD_OPC_CheckPredicate, 22, 224, 3, 0, // Skip to: 2419
2251
/* 1427 */    MCD_OPC_CheckField, 1, 3, 7, 217, 3, 0, // Skip to: 2419
2252
/* 1434 */    MCD_OPC_Decode, 187, 12, 138, 1, // Opcode: EE_VMIN_S16_ST_INCP
2253
/* 1439 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1461
2254
/* 1444 */    MCD_OPC_CheckPredicate, 22, 202, 3, 0, // Skip to: 2419
2255
/* 1449 */    MCD_OPC_CheckField, 1, 3, 7, 195, 3, 0, // Skip to: 2419
2256
/* 1456 */    MCD_OPC_Decode, 193, 12, 138, 1, // Opcode: EE_VMIN_S8_ST_INCP
2257
/* 1461 */    MCD_OPC_FilterValue, 3, 185, 3, 0, // Skip to: 2419
2258
/* 1466 */    MCD_OPC_CheckPredicate, 22, 180, 3, 0, // Skip to: 2419
2259
/* 1471 */    MCD_OPC_CheckField, 1, 3, 7, 173, 3, 0, // Skip to: 2419
2260
/* 1478 */    MCD_OPC_Decode, 247, 12, 138, 1, // Opcode: EE_VMUL_S8_ST_INCP
2261
/* 1483 */    MCD_OPC_FilterValue, 1, 163, 3, 0, // Skip to: 2419
2262
/* 1488 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
2263
/* 1491 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 1543
2264
/* 1496 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
2265
/* 1499 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1521
2266
/* 1504 */    MCD_OPC_CheckPredicate, 22, 142, 3, 0, // Skip to: 2419
2267
/* 1509 */    MCD_OPC_CheckField, 1, 3, 7, 135, 3, 0, // Skip to: 2419
2268
/* 1516 */    MCD_OPC_Decode, 144, 12, 138, 1, // Opcode: EE_VADDS_S16_ST_INCP
2269
/* 1521 */    MCD_OPC_FilterValue, 1, 125, 3, 0, // Skip to: 2419
2270
/* 1526 */    MCD_OPC_CheckPredicate, 22, 120, 3, 0, // Skip to: 2419
2271
/* 1531 */    MCD_OPC_CheckField, 1, 3, 7, 113, 3, 0, // Skip to: 2419
2272
/* 1538 */    MCD_OPC_Decode, 184, 12, 138, 1, // Opcode: EE_VMAX_S8_ST_INCP
2273
/* 1543 */    MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 1595
2274
/* 1548 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
2275
/* 1551 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1573
2276
/* 1556 */    MCD_OPC_CheckPredicate, 22, 90, 3, 0, // Skip to: 2419
2277
/* 1561 */    MCD_OPC_CheckField, 1, 3, 7, 83, 3, 0, // Skip to: 2419
2278
/* 1568 */    MCD_OPC_Decode, 147, 12, 138, 1, // Opcode: EE_VADDS_S32_ST_INCP
2279
/* 1573 */    MCD_OPC_FilterValue, 1, 73, 3, 0, // Skip to: 2419
2280
/* 1578 */    MCD_OPC_CheckPredicate, 22, 68, 3, 0, // Skip to: 2419
2281
/* 1583 */    MCD_OPC_CheckField, 1, 3, 7, 61, 3, 0, // Skip to: 2419
2282
/* 1590 */    MCD_OPC_Decode, 190, 12, 138, 1, // Opcode: EE_VMIN_S32_ST_INCP
2283
/* 1595 */    MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 1647
2284
/* 1600 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
2285
/* 1603 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1625
2286
/* 1608 */    MCD_OPC_CheckPredicate, 22, 38, 3, 0, // Skip to: 2419
2287
/* 1613 */    MCD_OPC_CheckField, 1, 3, 7, 31, 3, 0, // Skip to: 2419
2288
/* 1620 */    MCD_OPC_Decode, 150, 12, 138, 1, // Opcode: EE_VADDS_S8_ST_INCP
2289
/* 1625 */    MCD_OPC_FilterValue, 1, 21, 3, 0, // Skip to: 2419
2290
/* 1630 */    MCD_OPC_CheckPredicate, 22, 16, 3, 0, // Skip to: 2419
2291
/* 1635 */    MCD_OPC_CheckField, 1, 3, 7, 9, 3, 0, // Skip to: 2419
2292
/* 1642 */    MCD_OPC_Decode, 244, 12, 138, 1, // Opcode: EE_VMUL_S16_ST_INCP
2293
/* 1647 */    MCD_OPC_FilterValue, 3, 255, 2, 0, // Skip to: 2419
2294
/* 1652 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
2295
/* 1655 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1677
2296
/* 1660 */    MCD_OPC_CheckPredicate, 22, 242, 2, 0, // Skip to: 2419
2297
/* 1665 */    MCD_OPC_CheckField, 1, 3, 7, 235, 2, 0, // Skip to: 2419
2298
/* 1672 */    MCD_OPC_Decode, 178, 12, 138, 1, // Opcode: EE_VMAX_S16_ST_INCP
2299
/* 1677 */    MCD_OPC_FilterValue, 1, 225, 2, 0, // Skip to: 2419
2300
/* 1682 */    MCD_OPC_CheckPredicate, 22, 220, 2, 0, // Skip to: 2419
2301
/* 1687 */    MCD_OPC_CheckField, 1, 3, 7, 213, 2, 0, // Skip to: 2419
2302
/* 1694 */    MCD_OPC_Decode, 250, 12, 138, 1, // Opcode: EE_VMUL_U16_ST_INCP
2303
/* 1699 */    MCD_OPC_FilterValue, 1, 203, 2, 0, // Skip to: 2419
2304
/* 1704 */    MCD_OPC_CheckPredicate, 22, 198, 2, 0, // Skip to: 2419
2305
/* 1709 */    MCD_OPC_CheckField, 16, 3, 0, 191, 2, 0, // Skip to: 2419
2306
/* 1716 */    MCD_OPC_CheckField, 8, 4, 0, 184, 2, 0, // Skip to: 2419
2307
/* 1723 */    MCD_OPC_CheckField, 1, 3, 7, 177, 2, 0, // Skip to: 2419
2308
/* 1730 */    MCD_OPC_Decode, 135, 12, 139, 1, // Opcode: EE_STXQ_32
2309
/* 1735 */    MCD_OPC_FilterValue, 2, 167, 2, 0, // Skip to: 2419
2310
/* 1740 */    MCD_OPC_ExtractField, 19, 1,  // Inst{19} ...
2311
/* 1743 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 1779
2312
/* 1748 */    MCD_OPC_CheckPredicate, 22, 154, 2, 0, // Skip to: 2419
2313
/* 1753 */    MCD_OPC_CheckField, 23, 3, 0, 147, 2, 0, // Skip to: 2419
2314
/* 1760 */    MCD_OPC_CheckField, 12, 2, 0, 140, 2, 0, // Skip to: 2419
2315
/* 1767 */    MCD_OPC_CheckField, 1, 3, 7, 133, 2, 0, // Skip to: 2419
2316
/* 1774 */    MCD_OPC_Decode, 128, 12, 140, 1, // Opcode: EE_SRC_Q_LD_XP
2317
/* 1779 */    MCD_OPC_FilterValue, 1, 123, 2, 0, // Skip to: 2419
2318
/* 1784 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
2319
/* 1787 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1816
2320
/* 1792 */    MCD_OPC_CheckPredicate, 22, 110, 2, 0, // Skip to: 2419
2321
/* 1797 */    MCD_OPC_CheckField, 24, 2, 0, 103, 2, 0, // Skip to: 2419
2322
/* 1804 */    MCD_OPC_CheckField, 1, 3, 7, 96, 2, 0, // Skip to: 2419
2323
/* 1811 */    MCD_OPC_Decode, 253, 12, 138, 1, // Opcode: EE_VMUL_U8_ST_INCP
2324
/* 1816 */    MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 1845
2325
/* 1821 */    MCD_OPC_CheckPredicate, 22, 81, 2, 0, // Skip to: 2419
2326
/* 1826 */    MCD_OPC_CheckField, 24, 2, 0, 74, 2, 0, // Skip to: 2419
2327
/* 1833 */    MCD_OPC_CheckField, 1, 3, 7, 67, 2, 0, // Skip to: 2419
2328
/* 1840 */    MCD_OPC_Decode, 144, 13, 138, 1, // Opcode: EE_VSUBS_S16_ST_INCP
2329
/* 1845 */    MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 1874
2330
/* 1850 */    MCD_OPC_CheckPredicate, 22, 52, 2, 0, // Skip to: 2419
2331
/* 1855 */    MCD_OPC_CheckField, 24, 2, 0, 45, 2, 0, // Skip to: 2419
2332
/* 1862 */    MCD_OPC_CheckField, 1, 3, 7, 38, 2, 0, // Skip to: 2419
2333
/* 1869 */    MCD_OPC_Decode, 147, 13, 138, 1, // Opcode: EE_VSUBS_S32_ST_INCP
2334
/* 1874 */    MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 1903
2335
/* 1879 */    MCD_OPC_CheckPredicate, 22, 23, 2, 0, // Skip to: 2419
2336
/* 1884 */    MCD_OPC_CheckField, 24, 2, 0, 16, 2, 0, // Skip to: 2419
2337
/* 1891 */    MCD_OPC_CheckField, 1, 3, 7, 9, 2, 0, // Skip to: 2419
2338
/* 1898 */    MCD_OPC_Decode, 150, 13, 138, 1, // Opcode: EE_VSUBS_S8_ST_INCP
2339
/* 1903 */    MCD_OPC_FilterValue, 4, 255, 1, 0, // Skip to: 2419
2340
/* 1908 */    MCD_OPC_CheckPredicate, 22, 250, 1, 0, // Skip to: 2419
2341
/* 1913 */    MCD_OPC_CheckField, 24, 2, 0, 243, 1, 0, // Skip to: 2419
2342
/* 1920 */    MCD_OPC_CheckField, 13, 1, 0, 236, 1, 0, // Skip to: 2419
2343
/* 1927 */    MCD_OPC_CheckField, 1, 3, 7, 229, 1, 0, // Skip to: 2419
2344
/* 1934 */    MCD_OPC_Decode, 214, 11, 141, 1, // Opcode: EE_FFT_R2BF_S16_ST_INCP
2345
/* 1939 */    MCD_OPC_FilterValue, 15, 219, 1, 0, // Skip to: 2419
2346
/* 1944 */    MCD_OPC_ExtractField, 16, 3,  // Inst{18-16} ...
2347
/* 1947 */    MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 2006
2348
/* 1952 */    MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
2349
/* 1955 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1977
2350
/* 1960 */    MCD_OPC_CheckPredicate, 22, 198, 1, 0, // Skip to: 2419
2351
/* 1965 */    MCD_OPC_CheckField, 1, 3, 7, 191, 1, 0, // Skip to: 2419
2352
/* 1972 */    MCD_OPC_Decode, 195, 12, 142, 1, // Opcode: EE_VMULAS_S16_ACCX_LD_IP
2353
/* 1977 */    MCD_OPC_FilterValue, 1, 181, 1, 0, // Skip to: 2419
2354
/* 1982 */    MCD_OPC_CheckPredicate, 22, 176, 1, 0, // Skip to: 2419
2355
/* 1987 */    MCD_OPC_CheckField, 26, 2, 0, 169, 1, 0, // Skip to: 2419
2356
/* 1994 */    MCD_OPC_CheckField, 1, 3, 7, 162, 1, 0, // Skip to: 2419
2357
/* 2001 */    MCD_OPC_Decode, 197, 12, 143, 1, // Opcode: EE_VMULAS_S16_ACCX_LD_XP
2358
/* 2006 */    MCD_OPC_FilterValue, 1, 54, 0, 0, // Skip to: 2065
2359
/* 2011 */    MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
2360
/* 2014 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2036
2361
/* 2019 */    MCD_OPC_CheckPredicate, 22, 139, 1, 0, // Skip to: 2419
2362
/* 2024 */    MCD_OPC_CheckField, 1, 3, 7, 132, 1, 0, // Skip to: 2419
2363
/* 2031 */    MCD_OPC_Decode, 202, 12, 142, 1, // Opcode: EE_VMULAS_S16_QACC_LD_IP
2364
/* 2036 */    MCD_OPC_FilterValue, 1, 122, 1, 0, // Skip to: 2419
2365
/* 2041 */    MCD_OPC_CheckPredicate, 22, 117, 1, 0, // Skip to: 2419
2366
/* 2046 */    MCD_OPC_CheckField, 26, 2, 0, 110, 1, 0, // Skip to: 2419
2367
/* 2053 */    MCD_OPC_CheckField, 1, 3, 7, 103, 1, 0, // Skip to: 2419
2368
/* 2060 */    MCD_OPC_Decode, 204, 12, 143, 1, // Opcode: EE_VMULAS_S16_QACC_LD_XP
2369
/* 2065 */    MCD_OPC_FilterValue, 2, 54, 0, 0, // Skip to: 2124
2370
/* 2070 */    MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
2371
/* 2073 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2095
2372
/* 2078 */    MCD_OPC_CheckPredicate, 22, 80, 1, 0, // Skip to: 2419
2373
/* 2083 */    MCD_OPC_CheckField, 1, 3, 7, 73, 1, 0, // Skip to: 2419
2374
/* 2090 */    MCD_OPC_Decode, 207, 12, 142, 1, // Opcode: EE_VMULAS_S8_ACCX_LD_IP
2375
/* 2095 */    MCD_OPC_FilterValue, 1, 63, 1, 0, // Skip to: 2419
2376
/* 2100 */    MCD_OPC_CheckPredicate, 22, 58, 1, 0, // Skip to: 2419
2377
/* 2105 */    MCD_OPC_CheckField, 26, 2, 0, 51, 1, 0, // Skip to: 2419
2378
/* 2112 */    MCD_OPC_CheckField, 1, 3, 7, 44, 1, 0, // Skip to: 2419
2379
/* 2119 */    MCD_OPC_Decode, 209, 12, 143, 1, // Opcode: EE_VMULAS_S8_ACCX_LD_XP
2380
/* 2124 */    MCD_OPC_FilterValue, 3, 54, 0, 0, // Skip to: 2183
2381
/* 2129 */    MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
2382
/* 2132 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2154
2383
/* 2137 */    MCD_OPC_CheckPredicate, 22, 21, 1, 0, // Skip to: 2419
2384
/* 2142 */    MCD_OPC_CheckField, 1, 3, 7, 14, 1, 0, // Skip to: 2419
2385
/* 2149 */    MCD_OPC_Decode, 214, 12, 142, 1, // Opcode: EE_VMULAS_S8_QACC_LD_IP
2386
/* 2154 */    MCD_OPC_FilterValue, 1, 4, 1, 0, // Skip to: 2419
2387
/* 2159 */    MCD_OPC_CheckPredicate, 22, 255, 0, 0, // Skip to: 2419
2388
/* 2164 */    MCD_OPC_CheckField, 26, 2, 0, 248, 0, 0, // Skip to: 2419
2389
/* 2171 */    MCD_OPC_CheckField, 1, 3, 7, 241, 0, 0, // Skip to: 2419
2390
/* 2178 */    MCD_OPC_Decode, 216, 12, 143, 1, // Opcode: EE_VMULAS_S8_QACC_LD_XP
2391
/* 2183 */    MCD_OPC_FilterValue, 4, 54, 0, 0, // Skip to: 2242
2392
/* 2188 */    MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
2393
/* 2191 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2213
2394
/* 2196 */    MCD_OPC_CheckPredicate, 22, 218, 0, 0, // Skip to: 2419
2395
/* 2201 */    MCD_OPC_CheckField, 1, 3, 7, 211, 0, 0, // Skip to: 2419
2396
/* 2208 */    MCD_OPC_Decode, 219, 12, 142, 1, // Opcode: EE_VMULAS_U16_ACCX_LD_IP
2397
/* 2213 */    MCD_OPC_FilterValue, 1, 201, 0, 0, // Skip to: 2419
2398
/* 2218 */    MCD_OPC_CheckPredicate, 22, 196, 0, 0, // Skip to: 2419
2399
/* 2223 */    MCD_OPC_CheckField, 26, 2, 0, 189, 0, 0, // Skip to: 2419
2400
/* 2230 */    MCD_OPC_CheckField, 1, 3, 7, 182, 0, 0, // Skip to: 2419
2401
/* 2237 */    MCD_OPC_Decode, 221, 12, 143, 1, // Opcode: EE_VMULAS_U16_ACCX_LD_XP
2402
/* 2242 */    MCD_OPC_FilterValue, 5, 54, 0, 0, // Skip to: 2301
2403
/* 2247 */    MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
2404
/* 2250 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2272
2405
/* 2255 */    MCD_OPC_CheckPredicate, 22, 159, 0, 0, // Skip to: 2419
2406
/* 2260 */    MCD_OPC_CheckField, 1, 3, 7, 152, 0, 0, // Skip to: 2419
2407
/* 2267 */    MCD_OPC_Decode, 226, 12, 142, 1, // Opcode: EE_VMULAS_U16_QACC_LD_IP
2408
/* 2272 */    MCD_OPC_FilterValue, 1, 142, 0, 0, // Skip to: 2419
2409
/* 2277 */    MCD_OPC_CheckPredicate, 22, 137, 0, 0, // Skip to: 2419
2410
/* 2282 */    MCD_OPC_CheckField, 26, 2, 0, 130, 0, 0, // Skip to: 2419
2411
/* 2289 */    MCD_OPC_CheckField, 1, 3, 7, 123, 0, 0, // Skip to: 2419
2412
/* 2296 */    MCD_OPC_Decode, 228, 12, 143, 1, // Opcode: EE_VMULAS_U16_QACC_LD_XP
2413
/* 2301 */    MCD_OPC_FilterValue, 6, 54, 0, 0, // Skip to: 2360
2414
/* 2306 */    MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
2415
/* 2309 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2331
2416
/* 2314 */    MCD_OPC_CheckPredicate, 22, 100, 0, 0, // Skip to: 2419
2417
/* 2319 */    MCD_OPC_CheckField, 1, 3, 7, 93, 0, 0, // Skip to: 2419
2418
/* 2326 */    MCD_OPC_Decode, 231, 12, 142, 1, // Opcode: EE_VMULAS_U8_ACCX_LD_IP
2419
/* 2331 */    MCD_OPC_FilterValue, 1, 83, 0, 0, // Skip to: 2419
2420
/* 2336 */    MCD_OPC_CheckPredicate, 22, 78, 0, 0, // Skip to: 2419
2421
/* 2341 */    MCD_OPC_CheckField, 26, 2, 0, 71, 0, 0, // Skip to: 2419
2422
/* 2348 */    MCD_OPC_CheckField, 1, 3, 7, 64, 0, 0, // Skip to: 2419
2423
/* 2355 */    MCD_OPC_Decode, 233, 12, 143, 1, // Opcode: EE_VMULAS_U8_ACCX_LD_XP
2424
/* 2360 */    MCD_OPC_FilterValue, 7, 54, 0, 0, // Skip to: 2419
2425
/* 2365 */    MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
2426
/* 2368 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2390
2427
/* 2373 */    MCD_OPC_CheckPredicate, 22, 41, 0, 0, // Skip to: 2419
2428
/* 2378 */    MCD_OPC_CheckField, 1, 3, 7, 34, 0, 0, // Skip to: 2419
2429
/* 2385 */    MCD_OPC_Decode, 238, 12, 142, 1, // Opcode: EE_VMULAS_U8_QACC_LD_IP
2430
/* 2390 */    MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 2419
2431
/* 2395 */    MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 2419
2432
/* 2400 */    MCD_OPC_CheckField, 26, 2, 0, 12, 0, 0, // Skip to: 2419
2433
/* 2407 */    MCD_OPC_CheckField, 1, 3, 7, 5, 0, 0, // Skip to: 2419
2434
/* 2414 */    MCD_OPC_Decode, 240, 12, 143, 1, // Opcode: EE_VMULAS_U8_QACC_LD_XP
2435
/* 2419 */    MCD_OPC_Fail,
2436
  0
2437
};
2438
2439
static const uint8_t DecoderTableFallback16[] = {
2440
/* 0 */       MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
2441
/* 3 */       MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 17
2442
/* 8 */       MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 31
2443
/* 13 */      MCD_OPC_Decode, 192, 15, 0, // Opcode: _L32I_N
2444
/* 17 */      MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 31
2445
/* 22 */      MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 31
2446
/* 27 */      MCD_OPC_Decode, 195, 15, 0, // Opcode: _S32I_N
2447
/* 31 */      MCD_OPC_Fail,
2448
  0
2449
};
2450
2451
static const uint8_t DecoderTableFallback24[] = {
2452
/* 0 */       MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
2453
/* 3 */       MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 44
2454
/* 8 */       MCD_OPC_ExtractField, 21, 3,  // Inst{23-21} ...
2455
/* 11 */      MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 27
2456
/* 16 */      MCD_OPC_CheckField, 16, 4, 1, 56, 0, 0, // Skip to: 79
2457
/* 23 */      MCD_OPC_Decode, 196, 15, 11, // Opcode: _SLLI
2458
/* 27 */      MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 79
2459
/* 32 */      MCD_OPC_CheckField, 16, 5, 1, 40, 0, 0, // Skip to: 79
2460
/* 39 */      MCD_OPC_Decode, 197, 15, 144, 1, // Opcode: _SRLI
2461
/* 44 */      MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 79
2462
/* 49 */      MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
2463
/* 52 */      MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 61
2464
/* 57 */      MCD_OPC_Decode, 191, 15, 49, // Opcode: _L32I
2465
/* 61 */      MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 70
2466
/* 66 */      MCD_OPC_Decode, 194, 15, 49, // Opcode: _S32I
2467
/* 70 */      MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 79
2468
/* 75 */      MCD_OPC_Decode, 193, 15, 50, // Opcode: _MOVI
2469
/* 79 */      MCD_OPC_Fail,
2470
  0
2471
};
2472
2473
static const uint8_t DecoderTableHIFI324[] = {
2474
/* 0 */       MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
2475
/* 3 */       MCD_OPC_FilterValue, 0, 137, 1, 0, // Skip to: 401
2476
/* 8 */       MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
2477
/* 11 */      MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 33
2478
/* 16 */      MCD_OPC_CheckPredicate, 24, 188, 20, 0, // Skip to: 5329
2479
/* 21 */      MCD_OPC_CheckField, 0, 4, 4, 181, 20, 0, // Skip to: 5329
2480
/* 28 */      MCD_OPC_Decode, 146, 10, 145, 1, // Opcode: AE_S32X2RA64S_IP
2481
/* 33 */      MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 55
2482
/* 38 */      MCD_OPC_CheckPredicate, 24, 166, 20, 0, // Skip to: 5329
2483
/* 43 */      MCD_OPC_CheckField, 0, 4, 4, 159, 20, 0, // Skip to: 5329
2484
/* 50 */      MCD_OPC_Decode, 159, 10, 146, 1, // Opcode: AE_S64_I
2485
/* 55 */      MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 77
2486
/* 60 */      MCD_OPC_CheckPredicate, 24, 144, 20, 0, // Skip to: 5329
2487
/* 65 */      MCD_OPC_CheckField, 0, 4, 4, 137, 20, 0, // Skip to: 5329
2488
/* 72 */      MCD_OPC_Decode, 160, 10, 147, 1, // Opcode: AE_S64_IP
2489
/* 77 */      MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 99
2490
/* 82 */      MCD_OPC_CheckPredicate, 24, 122, 20, 0, // Skip to: 5329
2491
/* 87 */      MCD_OPC_CheckField, 0, 4, 4, 115, 20, 0, // Skip to: 5329
2492
/* 94 */      MCD_OPC_Decode, 251, 9, 145, 1, // Opcode: AE_S24X2RA64S_IP
2493
/* 99 */      MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 121
2494
/* 104 */     MCD_OPC_CheckPredicate, 24, 100, 20, 0, // Skip to: 5329
2495
/* 109 */     MCD_OPC_CheckField, 0, 4, 4, 93, 20, 0, // Skip to: 5329
2496
/* 116 */     MCD_OPC_Decode, 138, 10, 148, 1, // Opcode: AE_S32RA64S_XP
2497
/* 121 */     MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 143
2498
/* 126 */     MCD_OPC_CheckPredicate, 24, 78, 20, 0, // Skip to: 5329
2499
/* 131 */     MCD_OPC_CheckField, 0, 4, 4, 71, 20, 0, // Skip to: 5329
2500
/* 138 */     MCD_OPC_Decode, 209, 10, 149, 1, // Opcode: AE_SLAA32S
2501
/* 143 */     MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 165
2502
/* 148 */     MCD_OPC_CheckPredicate, 24, 56, 20, 0, // Skip to: 5329
2503
/* 153 */     MCD_OPC_CheckField, 0, 4, 4, 49, 20, 0, // Skip to: 5329
2504
/* 160 */     MCD_OPC_Decode, 232, 10, 149, 1, // Opcode: AE_SRAA32
2505
/* 165 */     MCD_OPC_FilterValue, 12, 91, 0, 0, // Skip to: 261
2506
/* 170 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
2507
/* 173 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 195
2508
/* 178 */     MCD_OPC_CheckPredicate, 24, 26, 20, 0, // Skip to: 5329
2509
/* 183 */     MCD_OPC_CheckField, 0, 4, 4, 19, 20, 0, // Skip to: 5329
2510
/* 190 */     MCD_OPC_Decode, 195, 5, 150, 1, // Opcode: AE_LA32X2F24_IC
2511
/* 195 */     MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 217
2512
/* 200 */     MCD_OPC_CheckPredicate, 24, 4, 20, 0, // Skip to: 5329
2513
/* 205 */     MCD_OPC_CheckField, 0, 4, 4, 253, 19, 0, // Skip to: 5329
2514
/* 212 */     MCD_OPC_Decode, 196, 5, 150, 1, // Opcode: AE_LA32X2F24_IP
2515
/* 217 */     MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 239
2516
/* 222 */     MCD_OPC_CheckPredicate, 24, 238, 19, 0, // Skip to: 5329
2517
/* 227 */     MCD_OPC_CheckField, 0, 4, 4, 231, 19, 0, // Skip to: 5329
2518
/* 234 */     MCD_OPC_Decode, 165, 10, 151, 1, // Opcode: AE_SA16X4_IP
2519
/* 239 */     MCD_OPC_FilterValue, 3, 221, 19, 0, // Skip to: 5329
2520
/* 244 */     MCD_OPC_CheckPredicate, 24, 216, 19, 0, // Skip to: 5329
2521
/* 249 */     MCD_OPC_CheckField, 0, 4, 4, 209, 19, 0, // Skip to: 5329
2522
/* 256 */     MCD_OPC_Decode, 181, 10, 151, 1, // Opcode: AE_SA32X2_IP
2523
/* 261 */     MCD_OPC_FilterValue, 13, 91, 0, 0, // Skip to: 357
2524
/* 266 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
2525
/* 269 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 291
2526
/* 274 */     MCD_OPC_CheckPredicate, 24, 186, 19, 0, // Skip to: 5329
2527
/* 279 */     MCD_OPC_CheckField, 0, 4, 4, 179, 19, 0, // Skip to: 5329
2528
/* 286 */     MCD_OPC_Decode, 187, 5, 150, 1, // Opcode: AE_LA24X2_IC
2529
/* 291 */     MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 313
2530
/* 296 */     MCD_OPC_CheckPredicate, 24, 164, 19, 0, // Skip to: 5329
2531
/* 301 */     MCD_OPC_CheckField, 0, 4, 4, 157, 19, 0, // Skip to: 5329
2532
/* 308 */     MCD_OPC_Decode, 188, 5, 150, 1, // Opcode: AE_LA24X2_IP
2533
/* 313 */     MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 335
2534
/* 318 */     MCD_OPC_CheckPredicate, 24, 142, 19, 0, // Skip to: 5329
2535
/* 323 */     MCD_OPC_CheckField, 0, 4, 4, 135, 19, 0, // Skip to: 5329
2536
/* 330 */     MCD_OPC_Decode, 201, 5, 150, 1, // Opcode: AE_LA32X2_IC
2537
/* 335 */     MCD_OPC_FilterValue, 3, 125, 19, 0, // Skip to: 5329
2538
/* 340 */     MCD_OPC_CheckPredicate, 24, 120, 19, 0, // Skip to: 5329
2539
/* 345 */     MCD_OPC_CheckField, 0, 4, 4, 113, 19, 0, // Skip to: 5329
2540
/* 352 */     MCD_OPC_Decode, 202, 5, 150, 1, // Opcode: AE_LA32X2_IP
2541
/* 357 */     MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 379
2542
/* 362 */     MCD_OPC_CheckPredicate, 24, 98, 19, 0, // Skip to: 5329
2543
/* 367 */     MCD_OPC_CheckField, 0, 4, 4, 91, 19, 0, // Skip to: 5329
2544
/* 374 */     MCD_OPC_Decode, 142, 11, 152, 1, // Opcode: AE_VLDL32T
2545
/* 379 */     MCD_OPC_FilterValue, 15, 81, 19, 0, // Skip to: 5329
2546
/* 384 */     MCD_OPC_CheckPredicate, 24, 76, 19, 0, // Skip to: 5329
2547
/* 389 */     MCD_OPC_CheckField, 0, 4, 4, 69, 19, 0, // Skip to: 5329
2548
/* 396 */     MCD_OPC_Decode, 141, 11, 152, 1, // Opcode: AE_VLDL16T
2549
/* 401 */     MCD_OPC_FilterValue, 1, 135, 0, 0, // Skip to: 541
2550
/* 406 */     MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
2551
/* 409 */     MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 431
2552
/* 414 */     MCD_OPC_CheckPredicate, 24, 46, 19, 0, // Skip to: 5329
2553
/* 419 */     MCD_OPC_CheckField, 0, 4, 4, 39, 19, 0, // Skip to: 5329
2554
/* 426 */     MCD_OPC_Decode, 236, 5, 153, 1, // Opcode: AE_MOVDA16X2
2555
/* 431 */     MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 453
2556
/* 436 */     MCD_OPC_CheckPredicate, 24, 24, 19, 0, // Skip to: 5329
2557
/* 441 */     MCD_OPC_CheckField, 0, 4, 4, 17, 19, 0, // Skip to: 5329
2558
/* 448 */     MCD_OPC_Decode, 238, 5, 153, 1, // Opcode: AE_MOVDA32X2
2559
/* 453 */     MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 475
2560
/* 458 */     MCD_OPC_CheckPredicate, 24, 2, 19, 0, // Skip to: 5329
2561
/* 463 */     MCD_OPC_CheckField, 0, 4, 4, 251, 18, 0, // Skip to: 5329
2562
/* 470 */     MCD_OPC_Decode, 207, 9, 154, 1, // Opcode: AE_OR
2563
/* 475 */     MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 497
2564
/* 480 */     MCD_OPC_CheckPredicate, 24, 236, 18, 0, // Skip to: 5329
2565
/* 485 */     MCD_OPC_CheckField, 0, 4, 4, 229, 18, 0, // Skip to: 5329
2566
/* 492 */     MCD_OPC_Decode, 202, 10, 155, 1, // Opcode: AE_SEXT32
2567
/* 497 */     MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 519
2568
/* 502 */     MCD_OPC_CheckPredicate, 24, 214, 18, 0, // Skip to: 5329
2569
/* 507 */     MCD_OPC_CheckField, 0, 8, 20, 207, 18, 0, // Skip to: 5329
2570
/* 514 */     MCD_OPC_Decode, 204, 10, 156, 1, // Opcode: AE_SEXT32X2D16_32
2571
/* 519 */     MCD_OPC_FilterValue, 14, 197, 18, 0, // Skip to: 5329
2572
/* 524 */     MCD_OPC_CheckPredicate, 24, 192, 18, 0, // Skip to: 5329
2573
/* 529 */     MCD_OPC_CheckField, 0, 4, 4, 185, 18, 0, // Skip to: 5329
2574
/* 536 */     MCD_OPC_Decode, 149, 11, 154, 1, // Opcode: AE_XOR
2575
/* 541 */     MCD_OPC_FilterValue, 2, 208, 2, 0, // Skip to: 1266
2576
/* 546 */     MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
2577
/* 549 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 571
2578
/* 554 */     MCD_OPC_CheckPredicate, 24, 162, 18, 0, // Skip to: 5329
2579
/* 559 */     MCD_OPC_CheckField, 0, 4, 4, 155, 18, 0, // Skip to: 5329
2580
/* 566 */     MCD_OPC_Decode, 208, 10, 149, 1, // Opcode: AE_SLAA32
2581
/* 571 */     MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 593
2582
/* 576 */     MCD_OPC_CheckPredicate, 24, 140, 18, 0, // Skip to: 5329
2583
/* 581 */     MCD_OPC_CheckField, 0, 4, 4, 133, 18, 0, // Skip to: 5329
2584
/* 588 */     MCD_OPC_Decode, 212, 10, 149, 1, // Opcode: AE_SLAAQ56
2585
/* 593 */     MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 615
2586
/* 598 */     MCD_OPC_CheckPredicate, 24, 118, 18, 0, // Skip to: 5329
2587
/* 603 */     MCD_OPC_CheckField, 0, 4, 4, 111, 18, 0, // Skip to: 5329
2588
/* 610 */     MCD_OPC_Decode, 210, 10, 149, 1, // Opcode: AE_SLAA64
2589
/* 615 */     MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 637
2590
/* 620 */     MCD_OPC_CheckPredicate, 24, 96, 18, 0, // Skip to: 5329
2591
/* 625 */     MCD_OPC_CheckField, 0, 4, 4, 89, 18, 0, // Skip to: 5329
2592
/* 632 */     MCD_OPC_Decode, 207, 10, 149, 1, // Opcode: AE_SLAA16S
2593
/* 637 */     MCD_OPC_FilterValue, 4, 91, 0, 0, // Skip to: 733
2594
/* 642 */     MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
2595
/* 645 */     MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 667
2596
/* 650 */     MCD_OPC_CheckPredicate, 24, 66, 18, 0, // Skip to: 5329
2597
/* 655 */     MCD_OPC_CheckField, 0, 4, 4, 59, 18, 0, // Skip to: 5329
2598
/* 662 */     MCD_OPC_Decode, 221, 10, 157, 1, // Opcode: AE_SLAS24
2599
/* 667 */     MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 689
2600
/* 672 */     MCD_OPC_CheckPredicate, 24, 44, 18, 0, // Skip to: 5329
2601
/* 677 */     MCD_OPC_CheckField, 0, 4, 4, 37, 18, 0, // Skip to: 5329
2602
/* 684 */     MCD_OPC_Decode, 227, 10, 157, 1, // Opcode: AE_SLASQ56
2603
/* 689 */     MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 711
2604
/* 694 */     MCD_OPC_CheckPredicate, 24, 22, 18, 0, // Skip to: 5329
2605
/* 699 */     MCD_OPC_CheckField, 0, 4, 4, 15, 18, 0, // Skip to: 5329
2606
/* 706 */     MCD_OPC_Decode, 226, 10, 157, 1, // Opcode: AE_SLAS64S
2607
/* 711 */     MCD_OPC_FilterValue, 14, 5, 18, 0, // Skip to: 5329
2608
/* 716 */     MCD_OPC_CheckPredicate, 24, 0, 18, 0, // Skip to: 5329
2609
/* 721 */     MCD_OPC_CheckField, 0, 4, 4, 249, 17, 0, // Skip to: 5329
2610
/* 728 */     MCD_OPC_Decode, 242, 10, 157, 1, // Opcode: AE_SRAS24
2611
/* 733 */     MCD_OPC_FilterValue, 5, 131, 0, 0, // Skip to: 869
2612
/* 738 */     MCD_OPC_ExtractField, 0, 8,  // Inst{7-0} ...
2613
/* 741 */     MCD_OPC_FilterValue, 132, 1, 10, 0, 0, // Skip to: 757
2614
/* 747 */     MCD_OPC_CheckPredicate, 24, 225, 17, 0, // Skip to: 5329
2615
/* 752 */     MCD_OPC_Decode, 228, 5, 158, 1, // Opcode: AE_MOVAD16_0
2616
/* 757 */     MCD_OPC_FilterValue, 148, 1, 10, 0, 0, // Skip to: 773
2617
/* 763 */     MCD_OPC_CheckPredicate, 24, 209, 17, 0, // Skip to: 5329
2618
/* 768 */     MCD_OPC_Decode, 230, 5, 158, 1, // Opcode: AE_MOVAD16_2
2619
/* 773 */     MCD_OPC_FilterValue, 164, 1, 10, 0, 0, // Skip to: 789
2620
/* 779 */     MCD_OPC_CheckPredicate, 24, 193, 17, 0, // Skip to: 5329
2621
/* 784 */     MCD_OPC_Decode, 231, 5, 158, 1, // Opcode: AE_MOVAD16_3
2622
/* 789 */     MCD_OPC_FilterValue, 180, 1, 10, 0, 0, // Skip to: 805
2623
/* 795 */     MCD_OPC_CheckPredicate, 24, 177, 17, 0, // Skip to: 5329
2624
/* 800 */     MCD_OPC_Decode, 232, 5, 158, 1, // Opcode: AE_MOVAD32_H
2625
/* 805 */     MCD_OPC_FilterValue, 196, 1, 10, 0, 0, // Skip to: 821
2626
/* 811 */     MCD_OPC_CheckPredicate, 24, 161, 17, 0, // Skip to: 5329
2627
/* 816 */     MCD_OPC_Decode, 233, 5, 158, 1, // Opcode: AE_MOVAD32_L
2628
/* 821 */     MCD_OPC_FilterValue, 212, 1, 10, 0, 0, // Skip to: 837
2629
/* 827 */     MCD_OPC_CheckPredicate, 24, 145, 17, 0, // Skip to: 5329
2630
/* 832 */     MCD_OPC_Decode, 204, 9, 158, 1, // Opcode: AE_NSA64
2631
/* 837 */     MCD_OPC_FilterValue, 228, 1, 10, 0, 0, // Skip to: 853
2632
/* 843 */     MCD_OPC_CheckPredicate, 24, 129, 17, 0, // Skip to: 5329
2633
/* 848 */     MCD_OPC_Decode, 205, 9, 158, 1, // Opcode: AE_NSAZ16_0
2634
/* 853 */     MCD_OPC_FilterValue, 244, 1, 118, 17, 0, // Skip to: 5329
2635
/* 859 */     MCD_OPC_CheckPredicate, 24, 113, 17, 0, // Skip to: 5329
2636
/* 864 */     MCD_OPC_Decode, 206, 9, 158, 1, // Opcode: AE_NSAZ32_L
2637
/* 869 */     MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 898
2638
/* 874 */     MCD_OPC_CheckPredicate, 24, 98, 17, 0, // Skip to: 5329
2639
/* 879 */     MCD_OPC_CheckField, 8, 2, 2, 91, 17, 0, // Skip to: 5329
2640
/* 886 */     MCD_OPC_CheckField, 0, 4, 4, 84, 17, 0, // Skip to: 5329
2641
/* 893 */     MCD_OPC_Decode, 208, 9, 159, 1, // Opcode: AE_PKSR24
2642
/* 898 */     MCD_OPC_FilterValue, 7, 54, 0, 0, // Skip to: 957
2643
/* 903 */     MCD_OPC_ExtractField, 8, 2,  // Inst{9-8} ...
2644
/* 906 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 935
2645
/* 911 */     MCD_OPC_CheckPredicate, 24, 61, 17, 0, // Skip to: 5329
2646
/* 916 */     MCD_OPC_CheckField, 10, 2, 2, 54, 17, 0, // Skip to: 5329
2647
/* 923 */     MCD_OPC_CheckField, 0, 4, 4, 47, 17, 0, // Skip to: 5329
2648
/* 930 */     MCD_OPC_Decode, 214, 4, 157, 1, // Opcode: AE_ABS64
2649
/* 935 */     MCD_OPC_FilterValue, 2, 37, 17, 0, // Skip to: 5329
2650
/* 940 */     MCD_OPC_CheckPredicate, 24, 32, 17, 0, // Skip to: 5329
2651
/* 945 */     MCD_OPC_CheckField, 0, 4, 4, 25, 17, 0, // Skip to: 5329
2652
/* 952 */     MCD_OPC_Decode, 209, 9, 159, 1, // Opcode: AE_PKSR32
2653
/* 957 */     MCD_OPC_FilterValue, 8, 47, 0, 0, // Skip to: 1009
2654
/* 962 */     MCD_OPC_ExtractField, 8, 8,  // Inst{15-8} ...
2655
/* 965 */     MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 987
2656
/* 970 */     MCD_OPC_CheckPredicate, 24, 2, 17, 0, // Skip to: 5329
2657
/* 975 */     MCD_OPC_CheckField, 0, 4, 4, 251, 16, 0, // Skip to: 5329
2658
/* 982 */     MCD_OPC_Decode, 234, 5, 160, 1, // Opcode: AE_MOVALIGN
2659
/* 987 */     MCD_OPC_FilterValue, 19, 241, 16, 0, // Skip to: 5329
2660
/* 992 */     MCD_OPC_CheckPredicate, 24, 236, 16, 0, // Skip to: 5329
2661
/* 997 */     MCD_OPC_CheckField, 0, 6, 4, 229, 16, 0, // Skip to: 5329
2662
/* 1004 */    MCD_OPC_Decode, 150, 11, 161, 1, // Opcode: AE_ZALIGN64
2663
/* 1009 */    MCD_OPC_FilterValue, 11, 223, 0, 0, // Skip to: 1237
2664
/* 1014 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
2665
/* 1017 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1039
2666
/* 1022 */    MCD_OPC_CheckPredicate, 24, 206, 16, 0, // Skip to: 5329
2667
/* 1027 */    MCD_OPC_CheckField, 0, 4, 4, 199, 16, 0, // Skip to: 5329
2668
/* 1034 */    MCD_OPC_Decode, 211, 4, 157, 1, // Opcode: AE_ABS24S
2669
/* 1039 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1061
2670
/* 1044 */    MCD_OPC_CheckPredicate, 24, 184, 16, 0, // Skip to: 5329
2671
/* 1049 */    MCD_OPC_CheckField, 0, 4, 4, 177, 16, 0, // Skip to: 5329
2672
/* 1056 */    MCD_OPC_Decode, 210, 4, 157, 1, // Opcode: AE_ABS16S
2673
/* 1061 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 1083
2674
/* 1066 */    MCD_OPC_CheckPredicate, 24, 162, 16, 0, // Skip to: 5329
2675
/* 1071 */    MCD_OPC_CheckField, 0, 4, 4, 155, 16, 0, // Skip to: 5329
2676
/* 1078 */    MCD_OPC_Decode, 213, 4, 157, 1, // Opcode: AE_ABS32S
2677
/* 1083 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1105
2678
/* 1088 */    MCD_OPC_CheckPredicate, 24, 140, 16, 0, // Skip to: 5329
2679
/* 1093 */    MCD_OPC_CheckField, 0, 4, 4, 133, 16, 0, // Skip to: 5329
2680
/* 1100 */    MCD_OPC_Decode, 245, 4, 162, 1, // Opcode: AE_DIV64D32_L
2681
/* 1105 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 1127
2682
/* 1110 */    MCD_OPC_CheckPredicate, 24, 118, 16, 0, // Skip to: 5329
2683
/* 1115 */    MCD_OPC_CheckField, 0, 4, 4, 111, 16, 0, // Skip to: 5329
2684
/* 1122 */    MCD_OPC_Decode, 202, 9, 157, 1, // Opcode: AE_NEG64
2685
/* 1127 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 1149
2686
/* 1132 */    MCD_OPC_CheckPredicate, 24, 96, 16, 0, // Skip to: 5329
2687
/* 1137 */    MCD_OPC_CheckField, 0, 4, 4, 89, 16, 0, // Skip to: 5329
2688
/* 1144 */    MCD_OPC_Decode, 198, 9, 157, 1, // Opcode: AE_NEG16S
2689
/* 1149 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 1171
2690
/* 1154 */    MCD_OPC_CheckPredicate, 24, 74, 16, 0, // Skip to: 5329
2691
/* 1159 */    MCD_OPC_CheckField, 0, 4, 4, 67, 16, 0, // Skip to: 5329
2692
/* 1166 */    MCD_OPC_Decode, 201, 9, 157, 1, // Opcode: AE_NEG32S
2693
/* 1171 */    MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 1193
2694
/* 1176 */    MCD_OPC_CheckPredicate, 24, 52, 16, 0, // Skip to: 5329
2695
/* 1181 */    MCD_OPC_CheckField, 0, 4, 4, 45, 16, 0, // Skip to: 5329
2696
/* 1188 */    MCD_OPC_Decode, 222, 9, 157, 1, // Opcode: AE_ROUNDSQ32F48ASYM
2697
/* 1193 */    MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 1215
2698
/* 1198 */    MCD_OPC_CheckPredicate, 24, 30, 16, 0, // Skip to: 5329
2699
/* 1203 */    MCD_OPC_CheckField, 0, 4, 4, 23, 16, 0, // Skip to: 5329
2700
/* 1210 */    MCD_OPC_Decode, 223, 9, 157, 1, // Opcode: AE_ROUNDSQ32F48SYM
2701
/* 1215 */    MCD_OPC_FilterValue, 10, 13, 16, 0, // Skip to: 5329
2702
/* 1220 */    MCD_OPC_CheckPredicate, 24, 8, 16, 0, // Skip to: 5329
2703
/* 1225 */    MCD_OPC_CheckField, 0, 4, 4, 1, 16, 0, // Skip to: 5329
2704
/* 1232 */    MCD_OPC_Decode, 189, 10, 157, 1, // Opcode: AE_SAT48S
2705
/* 1237 */    MCD_OPC_FilterValue, 12, 247, 15, 0, // Skip to: 5329
2706
/* 1242 */    MCD_OPC_CheckPredicate, 24, 242, 15, 0, // Skip to: 5329
2707
/* 1247 */    MCD_OPC_CheckField, 7, 1, 1, 235, 15, 0, // Skip to: 5329
2708
/* 1254 */    MCD_OPC_CheckField, 0, 4, 4, 228, 15, 0, // Skip to: 5329
2709
/* 1261 */    MCD_OPC_Decode, 154, 5, 163, 1, // Opcode: AE_L32X2F24_IP
2710
/* 1266 */    MCD_OPC_FilterValue, 3, 243, 1, 0, // Skip to: 1770
2711
/* 1271 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
2712
/* 1274 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1296
2713
/* 1279 */    MCD_OPC_CheckPredicate, 24, 205, 15, 0, // Skip to: 5329
2714
/* 1284 */    MCD_OPC_CheckField, 0, 4, 4, 198, 15, 0, // Skip to: 5329
2715
/* 1291 */    MCD_OPC_Decode, 219, 4, 154, 1, // Opcode: AE_ADD32
2716
/* 1296 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1318
2717
/* 1301 */    MCD_OPC_CheckPredicate, 24, 183, 15, 0, // Skip to: 5329
2718
/* 1306 */    MCD_OPC_CheckField, 0, 4, 4, 176, 15, 0, // Skip to: 5329
2719
/* 1313 */    MCD_OPC_Decode, 222, 4, 154, 1, // Opcode: AE_ADD64
2720
/* 1318 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1340
2721
/* 1323 */    MCD_OPC_CheckPredicate, 24, 161, 15, 0, // Skip to: 5329
2722
/* 1328 */    MCD_OPC_CheckField, 0, 4, 4, 154, 15, 0, // Skip to: 5329
2723
/* 1335 */    MCD_OPC_Decode, 218, 4, 154, 1, // Opcode: AE_ADD24S
2724
/* 1340 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 1362
2725
/* 1345 */    MCD_OPC_CheckPredicate, 24, 139, 15, 0, // Skip to: 5329
2726
/* 1350 */    MCD_OPC_CheckField, 0, 4, 4, 132, 15, 0, // Skip to: 5329
2727
/* 1357 */    MCD_OPC_Decode, 217, 4, 154, 1, // Opcode: AE_ADD16S
2728
/* 1362 */    MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 1390
2729
/* 1367 */    MCD_OPC_CheckPredicate, 24, 117, 15, 0, // Skip to: 5329
2730
/* 1372 */    MCD_OPC_CheckField, 8, 8, 16, 110, 15, 0, // Skip to: 5329
2731
/* 1379 */    MCD_OPC_CheckField, 0, 4, 4, 103, 15, 0, // Skip to: 5329
2732
/* 1386 */    MCD_OPC_Decode, 143, 11, 25, // Opcode: AE_VLDSHT
2733
/* 1390 */    MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 1419
2734
/* 1395 */    MCD_OPC_CheckPredicate, 24, 89, 15, 0, // Skip to: 5329
2735
/* 1400 */    MCD_OPC_CheckField, 6, 2, 2, 82, 15, 0, // Skip to: 5329
2736
/* 1407 */    MCD_OPC_CheckField, 0, 4, 4, 75, 15, 0, // Skip to: 5329
2737
/* 1414 */    MCD_OPC_Decode, 182, 5, 150, 1, // Opcode: AE_LA16X4_RIP
2738
/* 1419 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 1441
2739
/* 1424 */    MCD_OPC_CheckPredicate, 24, 60, 15, 0, // Skip to: 5329
2740
/* 1429 */    MCD_OPC_CheckField, 0, 8, 132, 1, 52, 15, 0, // Skip to: 5329
2741
/* 1437 */    MCD_OPC_Decode, 205, 10, 18, // Opcode: AE_SHA32
2742
/* 1441 */    MCD_OPC_FilterValue, 7, 47, 0, 0, // Skip to: 1493
2743
/* 1446 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
2744
/* 1449 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1471
2745
/* 1454 */    MCD_OPC_CheckPredicate, 24, 30, 15, 0, // Skip to: 5329
2746
/* 1459 */    MCD_OPC_CheckField, 0, 4, 4, 23, 15, 0, // Skip to: 5329
2747
/* 1466 */    MCD_OPC_Decode, 179, 5, 150, 1, // Opcode: AE_LA16X4_IC
2748
/* 1471 */    MCD_OPC_FilterValue, 3, 13, 15, 0, // Skip to: 5329
2749
/* 1476 */    MCD_OPC_CheckPredicate, 24, 8, 15, 0, // Skip to: 5329
2750
/* 1481 */    MCD_OPC_CheckField, 0, 4, 4, 1, 15, 0, // Skip to: 5329
2751
/* 1488 */    MCD_OPC_Decode, 180, 5, 150, 1, // Opcode: AE_LA16X4_IP
2752
/* 1493 */    MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 1515
2753
/* 1498 */    MCD_OPC_CheckPredicate, 24, 242, 14, 0, // Skip to: 5329
2754
/* 1503 */    MCD_OPC_CheckField, 0, 5, 20, 235, 14, 0, // Skip to: 5329
2755
/* 1510 */    MCD_OPC_Decode, 240, 5, 164, 1, // Opcode: AE_MOVF32X2
2756
/* 1515 */    MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 1537
2757
/* 1520 */    MCD_OPC_CheckPredicate, 24, 220, 14, 0, // Skip to: 5329
2758
/* 1525 */    MCD_OPC_CheckField, 0, 5, 20, 213, 14, 0, // Skip to: 5329
2759
/* 1532 */    MCD_OPC_Decode, 244, 5, 164, 1, // Opcode: AE_MOVT32X2
2760
/* 1537 */    MCD_OPC_FilterValue, 12, 48, 0, 0, // Skip to: 1590
2761
/* 1542 */    MCD_OPC_ExtractField, 0, 8,  // Inst{7-0} ...
2762
/* 1545 */    MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 1560
2763
/* 1550 */    MCD_OPC_CheckPredicate, 24, 190, 14, 0, // Skip to: 5329
2764
/* 1555 */    MCD_OPC_Decode, 230, 4, 165, 1, // Opcode: AE_CVT48A32
2765
/* 1560 */    MCD_OPC_FilterValue, 36, 10, 0, 0, // Skip to: 1575
2766
/* 1565 */    MCD_OPC_CheckPredicate, 24, 175, 14, 0, // Skip to: 5329
2767
/* 1570 */    MCD_OPC_Decode, 235, 5, 165, 1, // Opcode: AE_MOVDA16
2768
/* 1575 */    MCD_OPC_FilterValue, 52, 165, 14, 0, // Skip to: 5329
2769
/* 1580 */    MCD_OPC_CheckPredicate, 24, 160, 14, 0, // Skip to: 5329
2770
/* 1585 */    MCD_OPC_Decode, 237, 5, 165, 1, // Opcode: AE_MOVDA32
2771
/* 1590 */    MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 1658
2772
/* 1595 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
2773
/* 1598 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1636
2774
/* 1603 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
2775
/* 1606 */    MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 1621
2776
/* 1611 */    MCD_OPC_CheckPredicate, 24, 129, 14, 0, // Skip to: 5329
2777
/* 1616 */    MCD_OPC_Decode, 163, 5, 166, 1, // Opcode: AE_L32X2_RIP
2778
/* 1621 */    MCD_OPC_FilterValue, 36, 119, 14, 0, // Skip to: 5329
2779
/* 1626 */    MCD_OPC_CheckPredicate, 24, 114, 14, 0, // Skip to: 5329
2780
/* 1631 */    MCD_OPC_Decode, 156, 5, 166, 1, // Opcode: AE_L32X2F24_RIP
2781
/* 1636 */    MCD_OPC_FilterValue, 2, 104, 14, 0, // Skip to: 5329
2782
/* 1641 */    MCD_OPC_CheckPredicate, 24, 99, 14, 0, // Skip to: 5329
2783
/* 1646 */    MCD_OPC_CheckField, 0, 4, 4, 92, 14, 0, // Skip to: 5329
2784
/* 1653 */    MCD_OPC_Decode, 242, 5, 167, 1, // Opcode: AE_MOVI
2785
/* 1658 */    MCD_OPC_FilterValue, 14, 78, 0, 0, // Skip to: 1741
2786
/* 1663 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
2787
/* 1666 */    MCD_OPC_FilterValue, 0, 48, 0, 0, // Skip to: 1719
2788
/* 1671 */    MCD_OPC_ExtractField, 0, 7,  // Inst{6-0} ...
2789
/* 1674 */    MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 1689
2790
/* 1679 */    MCD_OPC_CheckPredicate, 24, 61, 14, 0, // Skip to: 5329
2791
/* 1684 */    MCD_OPC_Decode, 227, 5, 156, 1, // Opcode: AE_MOV
2792
/* 1689 */    MCD_OPC_FilterValue, 36, 10, 0, 0, // Skip to: 1704
2793
/* 1694 */    MCD_OPC_CheckPredicate, 24, 46, 14, 0, // Skip to: 5329
2794
/* 1699 */    MCD_OPC_Decode, 236, 4, 156, 1, // Opcode: AE_CVTQ56P32S_H
2795
/* 1704 */    MCD_OPC_FilterValue, 52, 36, 14, 0, // Skip to: 5329
2796
/* 1709 */    MCD_OPC_CheckPredicate, 24, 31, 14, 0, // Skip to: 5329
2797
/* 1714 */    MCD_OPC_Decode, 237, 4, 156, 1, // Opcode: AE_CVTQ56P32S_L
2798
/* 1719 */    MCD_OPC_FilterValue, 1, 21, 14, 0, // Skip to: 5329
2799
/* 1724 */    MCD_OPC_CheckPredicate, 24, 16, 14, 0, // Skip to: 5329
2800
/* 1729 */    MCD_OPC_CheckField, 0, 4, 4, 9, 14, 0, // Skip to: 5329
2801
/* 1736 */    MCD_OPC_Decode, 161, 5, 163, 1, // Opcode: AE_L32X2_IP
2802
/* 1741 */    MCD_OPC_FilterValue, 15, 255, 13, 0, // Skip to: 5329
2803
/* 1746 */    MCD_OPC_CheckPredicate, 24, 250, 13, 0, // Skip to: 5329
2804
/* 1751 */    MCD_OPC_CheckField, 6, 2, 3, 243, 13, 0, // Skip to: 5329
2805
/* 1758 */    MCD_OPC_CheckField, 0, 4, 4, 236, 13, 0, // Skip to: 5329
2806
/* 1765 */    MCD_OPC_Decode, 177, 10, 151, 1, // Opcode: AE_SA32X2F24_IP
2807
/* 1770 */    MCD_OPC_FilterValue, 4, 11, 1, 0, // Skip to: 2042
2808
/* 1775 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
2809
/* 1778 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1800
2810
/* 1783 */    MCD_OPC_CheckPredicate, 24, 213, 13, 0, // Skip to: 5329
2811
/* 1788 */    MCD_OPC_CheckField, 0, 4, 4, 206, 13, 0, // Skip to: 5329
2812
/* 1795 */    MCD_OPC_Decode, 220, 4, 154, 1, // Opcode: AE_ADD32S
2813
/* 1800 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1822
2814
/* 1805 */    MCD_OPC_CheckPredicate, 24, 191, 13, 0, // Skip to: 5329
2815
/* 1810 */    MCD_OPC_CheckField, 0, 4, 4, 184, 13, 0, // Skip to: 5329
2816
/* 1817 */    MCD_OPC_Decode, 227, 4, 154, 1, // Opcode: AE_AND
2817
/* 1822 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1844
2818
/* 1827 */    MCD_OPC_CheckPredicate, 24, 169, 13, 0, // Skip to: 5329
2819
/* 1832 */    MCD_OPC_CheckField, 0, 4, 4, 162, 13, 0, // Skip to: 5329
2820
/* 1839 */    MCD_OPC_Decode, 210, 9, 168, 1, // Opcode: AE_ROUND16X4F32SASYM
2821
/* 1844 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 1866
2822
/* 1849 */    MCD_OPC_CheckPredicate, 24, 147, 13, 0, // Skip to: 5329
2823
/* 1854 */    MCD_OPC_CheckField, 0, 4, 4, 140, 13, 0, // Skip to: 5329
2824
/* 1861 */    MCD_OPC_Decode, 220, 9, 154, 1, // Opcode: AE_ROUNDSP16Q48X2ASYM
2825
/* 1866 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1888
2826
/* 1871 */    MCD_OPC_CheckPredicate, 24, 125, 13, 0, // Skip to: 5329
2827
/* 1876 */    MCD_OPC_CheckField, 0, 4, 4, 118, 13, 0, // Skip to: 5329
2828
/* 1883 */    MCD_OPC_Decode, 212, 9, 154, 1, // Opcode: AE_ROUND24X2F48SASYM
2829
/* 1888 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 1910
2830
/* 1893 */    MCD_OPC_CheckPredicate, 24, 103, 13, 0, // Skip to: 5329
2831
/* 1898 */    MCD_OPC_CheckField, 0, 4, 4, 96, 13, 0, // Skip to: 5329
2832
/* 1905 */    MCD_OPC_Decode, 213, 9, 154, 1, // Opcode: AE_ROUND24X2F48SSYM
2833
/* 1910 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 1932
2834
/* 1915 */    MCD_OPC_CheckPredicate, 24, 81, 13, 0, // Skip to: 5329
2835
/* 1920 */    MCD_OPC_CheckField, 0, 4, 4, 74, 13, 0, // Skip to: 5329
2836
/* 1927 */    MCD_OPC_Decode, 173, 5, 169, 1, // Opcode: AE_L64_IP
2837
/* 1932 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 1954
2838
/* 1937 */    MCD_OPC_CheckPredicate, 24, 59, 13, 0, // Skip to: 5329
2839
/* 1942 */    MCD_OPC_CheckField, 0, 4, 4, 52, 13, 0, // Skip to: 5329
2840
/* 1949 */    MCD_OPC_Decode, 216, 9, 154, 1, // Opcode: AE_ROUND32X2F64SASYM
2841
/* 1954 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 1976
2842
/* 1959 */    MCD_OPC_CheckPredicate, 24, 37, 13, 0, // Skip to: 5329
2843
/* 1964 */    MCD_OPC_CheckField, 0, 4, 4, 30, 13, 0, // Skip to: 5329
2844
/* 1971 */    MCD_OPC_Decode, 128, 11, 154, 1, // Opcode: AE_SUB32
2845
/* 1976 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 1998
2846
/* 1981 */    MCD_OPC_CheckPredicate, 24, 15, 13, 0, // Skip to: 5329
2847
/* 1986 */    MCD_OPC_CheckField, 0, 4, 4, 8, 13, 0, // Skip to: 5329
2848
/* 1993 */    MCD_OPC_Decode, 130, 11, 154, 1, // Opcode: AE_SUB64
2849
/* 1998 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 2020
2850
/* 2003 */    MCD_OPC_CheckPredicate, 24, 249, 12, 0, // Skip to: 5329
2851
/* 2008 */    MCD_OPC_CheckField, 0, 4, 4, 242, 12, 0, // Skip to: 5329
2852
/* 2015 */    MCD_OPC_Decode, 254, 10, 154, 1, // Opcode: AE_SUB16S
2853
/* 2020 */    MCD_OPC_FilterValue, 15, 232, 12, 0, // Skip to: 5329
2854
/* 2025 */    MCD_OPC_CheckPredicate, 24, 227, 12, 0, // Skip to: 5329
2855
/* 2030 */    MCD_OPC_CheckField, 0, 4, 4, 220, 12, 0, // Skip to: 5329
2856
/* 2037 */    MCD_OPC_Decode, 129, 11, 154, 1, // Opcode: AE_SUB32S
2857
/* 2042 */    MCD_OPC_FilterValue, 5, 187, 0, 0, // Skip to: 2234
2858
/* 2047 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
2859
/* 2050 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2072
2860
/* 2055 */    MCD_OPC_CheckPredicate, 24, 197, 12, 0, // Skip to: 5329
2861
/* 2060 */    MCD_OPC_CheckField, 0, 4, 4, 190, 12, 0, // Skip to: 5329
2862
/* 2067 */    MCD_OPC_Decode, 215, 5, 170, 1, // Opcode: AE_LE64
2863
/* 2072 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2094
2864
/* 2077 */    MCD_OPC_CheckPredicate, 24, 175, 12, 0, // Skip to: 5329
2865
/* 2082 */    MCD_OPC_CheckField, 0, 4, 4, 168, 12, 0, // Skip to: 5329
2866
/* 2089 */    MCD_OPC_Decode, 218, 5, 170, 1, // Opcode: AE_LT64
2867
/* 2094 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 2116
2868
/* 2099 */    MCD_OPC_CheckPredicate, 24, 153, 12, 0, // Skip to: 5329
2869
/* 2104 */    MCD_OPC_CheckField, 0, 4, 4, 146, 12, 0, // Skip to: 5329
2870
/* 2111 */    MCD_OPC_Decode, 219, 5, 154, 1, // Opcode: AE_MAX32
2871
/* 2116 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 2138
2872
/* 2121 */    MCD_OPC_CheckPredicate, 24, 131, 12, 0, // Skip to: 5329
2873
/* 2126 */    MCD_OPC_CheckField, 0, 4, 4, 124, 12, 0, // Skip to: 5329
2874
/* 2133 */    MCD_OPC_Decode, 223, 5, 154, 1, // Opcode: AE_MIN32
2875
/* 2138 */    MCD_OPC_FilterValue, 4, 47, 0, 0, // Skip to: 2190
2876
/* 2143 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
2877
/* 2146 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2168
2878
/* 2151 */    MCD_OPC_CheckPredicate, 24, 101, 12, 0, // Skip to: 5329
2879
/* 2156 */    MCD_OPC_CheckField, 0, 4, 4, 94, 12, 0, // Skip to: 5329
2880
/* 2163 */    MCD_OPC_Decode, 247, 4, 171, 1, // Opcode: AE_EQ32
2881
/* 2168 */    MCD_OPC_FilterValue, 1, 84, 12, 0, // Skip to: 5329
2882
/* 2173 */    MCD_OPC_CheckPredicate, 24, 79, 12, 0, // Skip to: 5329
2883
/* 2178 */    MCD_OPC_CheckField, 0, 4, 4, 72, 12, 0, // Skip to: 5329
2884
/* 2185 */    MCD_OPC_Decode, 217, 5, 171, 1, // Opcode: AE_LT32
2885
/* 2190 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2212
2886
/* 2195 */    MCD_OPC_CheckPredicate, 24, 57, 12, 0, // Skip to: 5329
2887
/* 2200 */    MCD_OPC_CheckField, 0, 4, 4, 50, 12, 0, // Skip to: 5329
2888
/* 2207 */    MCD_OPC_Decode, 196, 10, 172, 1, // Opcode: AE_SBI_IC
2889
/* 2212 */    MCD_OPC_FilterValue, 7, 40, 12, 0, // Skip to: 5329
2890
/* 2217 */    MCD_OPC_CheckPredicate, 24, 35, 12, 0, // Skip to: 5329
2891
/* 2222 */    MCD_OPC_CheckField, 0, 4, 4, 28, 12, 0, // Skip to: 5329
2892
/* 2229 */    MCD_OPC_Decode, 197, 10, 172, 1, // Opcode: AE_SBI_IP
2893
/* 2234 */    MCD_OPC_FilterValue, 6, 85, 2, 0, // Skip to: 2836
2894
/* 2239 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
2895
/* 2242 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2264
2896
/* 2247 */    MCD_OPC_CheckPredicate, 24, 5, 12, 0, // Skip to: 5329
2897
/* 2252 */    MCD_OPC_CheckField, 0, 4, 4, 254, 11, 0, // Skip to: 5329
2898
/* 2259 */    MCD_OPC_Decode, 245, 5, 173, 1, // Opcode: AE_MOVT64
2899
/* 2264 */    MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 2316
2900
/* 2269 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
2901
/* 2272 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2294
2902
/* 2277 */    MCD_OPC_CheckPredicate, 24, 231, 11, 0, // Skip to: 5329
2903
/* 2282 */    MCD_OPC_CheckField, 0, 4, 4, 224, 11, 0, // Skip to: 5329
2904
/* 2289 */    MCD_OPC_Decode, 148, 10, 174, 1, // Opcode: AE_S32X2_IP
2905
/* 2294 */    MCD_OPC_FilterValue, 1, 214, 11, 0, // Skip to: 5329
2906
/* 2299 */    MCD_OPC_CheckPredicate, 24, 209, 11, 0, // Skip to: 5329
2907
/* 2304 */    MCD_OPC_CheckField, 0, 4, 4, 202, 11, 0, // Skip to: 5329
2908
/* 2311 */    MCD_OPC_Decode, 140, 10, 174, 1, // Opcode: AE_S32X2F24_IP
2909
/* 2316 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 2338
2910
/* 2321 */    MCD_OPC_CheckPredicate, 24, 187, 11, 0, // Skip to: 5329
2911
/* 2326 */    MCD_OPC_CheckField, 0, 4, 4, 180, 11, 0, // Skip to: 5329
2912
/* 2333 */    MCD_OPC_Decode, 195, 10, 172, 1, // Opcode: AE_SBI
2913
/* 2338 */    MCD_OPC_FilterValue, 7, 143, 1, 0, // Skip to: 2742
2914
/* 2343 */    MCD_OPC_ExtractField, 8, 8,  // Inst{15-8} ...
2915
/* 2346 */    MCD_OPC_FilterValue, 234, 1, 16, 0, 0, // Skip to: 2368
2916
/* 2352 */    MCD_OPC_CheckPredicate, 24, 156, 11, 0, // Skip to: 5329
2917
/* 2357 */    MCD_OPC_CheckField, 0, 4, 4, 149, 11, 0, // Skip to: 5329
2918
/* 2364 */    MCD_OPC_Decode, 207, 14, 25, // Opcode: RUR_AE_OVERFLOW
2919
/* 2368 */    MCD_OPC_FilterValue, 235, 1, 16, 0, 0, // Skip to: 2390
2920
/* 2374 */    MCD_OPC_CheckPredicate, 24, 134, 11, 0, // Skip to: 5329
2921
/* 2379 */    MCD_OPC_CheckField, 0, 4, 4, 127, 11, 0, // Skip to: 5329
2922
/* 2386 */    MCD_OPC_Decode, 163, 15, 25, // Opcode: WUR_AE_OVERFLOW
2923
/* 2390 */    MCD_OPC_FilterValue, 236, 1, 16, 0, 0, // Skip to: 2412
2924
/* 2396 */    MCD_OPC_CheckPredicate, 24, 112, 11, 0, // Skip to: 5329
2925
/* 2401 */    MCD_OPC_CheckField, 0, 4, 4, 105, 11, 0, // Skip to: 5329
2926
/* 2408 */    MCD_OPC_Decode, 209, 14, 25, // Opcode: RUR_AE_SAR
2927
/* 2412 */    MCD_OPC_FilterValue, 237, 1, 16, 0, 0, // Skip to: 2434
2928
/* 2418 */    MCD_OPC_CheckPredicate, 24, 90, 11, 0, // Skip to: 5329
2929
/* 2423 */    MCD_OPC_CheckField, 0, 4, 4, 83, 11, 0, // Skip to: 5329
2930
/* 2430 */    MCD_OPC_Decode, 165, 15, 25, // Opcode: WUR_AE_SAR
2931
/* 2434 */    MCD_OPC_FilterValue, 238, 1, 16, 0, 0, // Skip to: 2456
2932
/* 2440 */    MCD_OPC_CheckPredicate, 24, 68, 11, 0, // Skip to: 5329
2933
/* 2445 */    MCD_OPC_CheckField, 0, 4, 4, 61, 11, 0, // Skip to: 5329
2934
/* 2452 */    MCD_OPC_Decode, 199, 14, 25, // Opcode: RUR_AE_BITPTR
2935
/* 2456 */    MCD_OPC_FilterValue, 239, 1, 16, 0, 0, // Skip to: 2478
2936
/* 2462 */    MCD_OPC_CheckPredicate, 24, 46, 11, 0, // Skip to: 5329
2937
/* 2467 */    MCD_OPC_CheckField, 0, 4, 4, 39, 11, 0, // Skip to: 5329
2938
/* 2474 */    MCD_OPC_Decode, 155, 15, 25, // Opcode: WUR_AE_BITPTR
2939
/* 2478 */    MCD_OPC_FilterValue, 240, 1, 16, 0, 0, // Skip to: 2500
2940
/* 2484 */    MCD_OPC_CheckPredicate, 24, 24, 11, 0, // Skip to: 5329
2941
/* 2489 */    MCD_OPC_CheckField, 0, 4, 4, 17, 11, 0, // Skip to: 5329
2942
/* 2496 */    MCD_OPC_Decode, 200, 14, 25, // Opcode: RUR_AE_BITSUSED
2943
/* 2500 */    MCD_OPC_FilterValue, 241, 1, 16, 0, 0, // Skip to: 2522
2944
/* 2506 */    MCD_OPC_CheckPredicate, 24, 2, 11, 0, // Skip to: 5329
2945
/* 2511 */    MCD_OPC_CheckField, 0, 4, 4, 251, 10, 0, // Skip to: 5329
2946
/* 2518 */    MCD_OPC_Decode, 156, 15, 25, // Opcode: WUR_AE_BITSUSED
2947
/* 2522 */    MCD_OPC_FilterValue, 242, 1, 16, 0, 0, // Skip to: 2544
2948
/* 2528 */    MCD_OPC_CheckPredicate, 24, 236, 10, 0, // Skip to: 5329
2949
/* 2533 */    MCD_OPC_CheckField, 0, 4, 4, 229, 10, 0, // Skip to: 5329
2950
/* 2540 */    MCD_OPC_Decode, 211, 14, 25, // Opcode: RUR_AE_TABLESIZE
2951
/* 2544 */    MCD_OPC_FilterValue, 243, 1, 16, 0, 0, // Skip to: 2566
2952
/* 2550 */    MCD_OPC_CheckPredicate, 24, 214, 10, 0, // Skip to: 5329
2953
/* 2555 */    MCD_OPC_CheckField, 0, 4, 4, 207, 10, 0, // Skip to: 5329
2954
/* 2562 */    MCD_OPC_Decode, 167, 15, 25, // Opcode: WUR_AE_TABLESIZE
2955
/* 2566 */    MCD_OPC_FilterValue, 244, 1, 16, 0, 0, // Skip to: 2588
2956
/* 2572 */    MCD_OPC_CheckPredicate, 24, 192, 10, 0, // Skip to: 5329
2957
/* 2577 */    MCD_OPC_CheckField, 0, 4, 4, 185, 10, 0, // Skip to: 5329
2958
/* 2584 */    MCD_OPC_Decode, 205, 14, 25, // Opcode: RUR_AE_FIRST_TS
2959
/* 2588 */    MCD_OPC_FilterValue, 245, 1, 16, 0, 0, // Skip to: 2610
2960
/* 2594 */    MCD_OPC_CheckPredicate, 24, 170, 10, 0, // Skip to: 5329
2961
/* 2599 */    MCD_OPC_CheckField, 0, 4, 4, 163, 10, 0, // Skip to: 5329
2962
/* 2606 */    MCD_OPC_Decode, 161, 15, 25, // Opcode: WUR_AE_FIRST_TS
2963
/* 2610 */    MCD_OPC_FilterValue, 246, 1, 16, 0, 0, // Skip to: 2632
2964
/* 2616 */    MCD_OPC_CheckPredicate, 24, 148, 10, 0, // Skip to: 5329
2965
/* 2621 */    MCD_OPC_CheckField, 0, 4, 4, 141, 10, 0, // Skip to: 5329
2966
/* 2628 */    MCD_OPC_Decode, 206, 14, 25, // Opcode: RUR_AE_NEXTOFFSET
2967
/* 2632 */    MCD_OPC_FilterValue, 247, 1, 16, 0, 0, // Skip to: 2654
2968
/* 2638 */    MCD_OPC_CheckPredicate, 24, 126, 10, 0, // Skip to: 5329
2969
/* 2643 */    MCD_OPC_CheckField, 0, 4, 4, 119, 10, 0, // Skip to: 5329
2970
/* 2650 */    MCD_OPC_Decode, 162, 15, 25, // Opcode: WUR_AE_NEXTOFFSET
2971
/* 2654 */    MCD_OPC_FilterValue, 248, 1, 16, 0, 0, // Skip to: 2676
2972
/* 2660 */    MCD_OPC_CheckPredicate, 24, 104, 10, 0, // Skip to: 5329
2973
/* 2665 */    MCD_OPC_CheckField, 0, 4, 4, 97, 10, 0, // Skip to: 5329
2974
/* 2672 */    MCD_OPC_Decode, 210, 14, 25, // Opcode: RUR_AE_SEARCHDONE
2975
/* 2676 */    MCD_OPC_FilterValue, 249, 1, 16, 0, 0, // Skip to: 2698
2976
/* 2682 */    MCD_OPC_CheckPredicate, 24, 82, 10, 0, // Skip to: 5329
2977
/* 2687 */    MCD_OPC_CheckField, 0, 4, 4, 75, 10, 0, // Skip to: 5329
2978
/* 2694 */    MCD_OPC_Decode, 166, 15, 25, // Opcode: WUR_AE_SEARCHDONE
2979
/* 2698 */    MCD_OPC_FilterValue, 250, 1, 16, 0, 0, // Skip to: 2720
2980
/* 2704 */    MCD_OPC_CheckPredicate, 24, 60, 10, 0, // Skip to: 5329
2981
/* 2709 */    MCD_OPC_CheckField, 0, 4, 4, 53, 10, 0, // Skip to: 5329
2982
/* 2716 */    MCD_OPC_Decode, 203, 14, 25, // Opcode: RUR_AE_CWRAP
2983
/* 2720 */    MCD_OPC_FilterValue, 251, 1, 43, 10, 0, // Skip to: 5329
2984
/* 2726 */    MCD_OPC_CheckPredicate, 24, 38, 10, 0, // Skip to: 5329
2985
/* 2731 */    MCD_OPC_CheckField, 0, 4, 4, 31, 10, 0, // Skip to: 5329
2986
/* 2738 */    MCD_OPC_Decode, 159, 15, 25, // Opcode: WUR_AE_CWRAP
2987
/* 2742 */    MCD_OPC_FilterValue, 9, 22, 10, 0, // Skip to: 5329
2988
/* 2747 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
2989
/* 2750 */    MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 2771
2990
/* 2755 */    MCD_OPC_CheckPredicate, 24, 9, 10, 0, // Skip to: 5329
2991
/* 2760 */    MCD_OPC_CheckField, 0, 4, 4, 2, 10, 0, // Skip to: 5329
2992
/* 2767 */    MCD_OPC_Decode, 207, 5, 16, // Opcode: AE_LB
2993
/* 2771 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 2793
2994
/* 2776 */    MCD_OPC_CheckPredicate, 24, 244, 9, 0, // Skip to: 5329
2995
/* 2781 */    MCD_OPC_CheckField, 0, 4, 4, 237, 9, 0, // Skip to: 5329
2996
/* 2788 */    MCD_OPC_Decode, 208, 5, 175, 1, // Opcode: AE_LBI
2997
/* 2793 */    MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2814
2998
/* 2798 */    MCD_OPC_CheckPredicate, 24, 222, 9, 0, // Skip to: 5329
2999
/* 2803 */    MCD_OPC_CheckField, 0, 4, 4, 215, 9, 0, // Skip to: 5329
3000
/* 2810 */    MCD_OPC_Decode, 211, 5, 16, // Opcode: AE_LBS
3001
/* 2814 */    MCD_OPC_FilterValue, 7, 206, 9, 0, // Skip to: 5329
3002
/* 2819 */    MCD_OPC_CheckPredicate, 24, 201, 9, 0, // Skip to: 5329
3003
/* 2824 */    MCD_OPC_CheckField, 0, 4, 4, 194, 9, 0, // Skip to: 5329
3004
/* 2831 */    MCD_OPC_Decode, 212, 5, 175, 1, // Opcode: AE_LBSI
3005
/* 2836 */    MCD_OPC_FilterValue, 7, 176, 1, 0, // Skip to: 3273
3006
/* 2841 */    MCD_OPC_ExtractField, 12, 8,  // Inst{19-12} ...
3007
/* 2844 */    MCD_OPC_FilterValue, 113, 24, 0, 0, // Skip to: 2873
3008
/* 2849 */    MCD_OPC_CheckPredicate, 24, 171, 9, 0, // Skip to: 5329
3009
/* 2854 */    MCD_OPC_CheckField, 6, 2, 3, 164, 9, 0, // Skip to: 5329
3010
/* 2861 */    MCD_OPC_CheckField, 0, 4, 4, 157, 9, 0, // Skip to: 5329
3011
/* 2868 */    MCD_OPC_Decode, 200, 5, 176, 1, // Opcode: AE_LA32X2POS_PC
3012
/* 2873 */    MCD_OPC_FilterValue, 114, 24, 0, 0, // Skip to: 2902
3013
/* 2878 */    MCD_OPC_CheckPredicate, 24, 142, 9, 0, // Skip to: 5329
3014
/* 2883 */    MCD_OPC_CheckField, 6, 2, 3, 135, 9, 0, // Skip to: 5329
3015
/* 2890 */    MCD_OPC_CheckField, 0, 4, 4, 128, 9, 0, // Skip to: 5329
3016
/* 2897 */    MCD_OPC_Decode, 205, 5, 177, 1, // Opcode: AE_LA64_PP
3017
/* 2902 */    MCD_OPC_FilterValue, 115, 24, 0, 0, // Skip to: 2931
3018
/* 2907 */    MCD_OPC_CheckPredicate, 24, 113, 9, 0, // Skip to: 5329
3019
/* 2912 */    MCD_OPC_CheckField, 6, 2, 3, 106, 9, 0, // Skip to: 5329
3020
/* 2919 */    MCD_OPC_CheckField, 0, 4, 4, 99, 9, 0, // Skip to: 5329
3021
/* 2926 */    MCD_OPC_Decode, 185, 10, 178, 1, // Opcode: AE_SA64POS_FP
3022
/* 2931 */    MCD_OPC_FilterValue, 116, 17, 0, 0, // Skip to: 2953
3023
/* 2936 */    MCD_OPC_CheckPredicate, 24, 84, 9, 0, // Skip to: 5329
3024
/* 2941 */    MCD_OPC_CheckField, 0, 4, 4, 77, 9, 0, // Skip to: 5329
3025
/* 2948 */    MCD_OPC_Decode, 238, 4, 179, 1, // Opcode: AE_DB
3026
/* 2953 */    MCD_OPC_FilterValue, 117, 17, 0, 0, // Skip to: 2975
3027
/* 2958 */    MCD_OPC_CheckPredicate, 24, 62, 9, 0, // Skip to: 5329
3028
/* 2963 */    MCD_OPC_CheckField, 0, 4, 4, 55, 9, 0, // Skip to: 5329
3029
/* 2970 */    MCD_OPC_Decode, 239, 4, 180, 1, // Opcode: AE_DBI
3030
/* 2975 */    MCD_OPC_FilterValue, 118, 17, 0, 0, // Skip to: 2997
3031
/* 2980 */    MCD_OPC_CheckPredicate, 24, 40, 9, 0, // Skip to: 5329
3032
/* 2985 */    MCD_OPC_CheckField, 0, 4, 4, 33, 9, 0, // Skip to: 5329
3033
/* 2992 */    MCD_OPC_Decode, 242, 4, 179, 1, // Opcode: AE_DB_IC
3034
/* 2997 */    MCD_OPC_FilterValue, 119, 17, 0, 0, // Skip to: 3019
3035
/* 3002 */    MCD_OPC_CheckPredicate, 24, 18, 9, 0, // Skip to: 5329
3036
/* 3007 */    MCD_OPC_CheckField, 0, 4, 4, 11, 9, 0, // Skip to: 5329
3037
/* 3014 */    MCD_OPC_Decode, 240, 4, 180, 1, // Opcode: AE_DBI_IC
3038
/* 3019 */    MCD_OPC_FilterValue, 120, 17, 0, 0, // Skip to: 3041
3039
/* 3024 */    MCD_OPC_CheckPredicate, 24, 252, 8, 0, // Skip to: 5329
3040
/* 3029 */    MCD_OPC_CheckField, 0, 4, 4, 245, 8, 0, // Skip to: 5329
3041
/* 3036 */    MCD_OPC_Decode, 243, 4, 179, 1, // Opcode: AE_DB_IP
3042
/* 3041 */    MCD_OPC_FilterValue, 121, 17, 0, 0, // Skip to: 3063
3043
/* 3046 */    MCD_OPC_CheckPredicate, 24, 230, 8, 0, // Skip to: 5329
3044
/* 3051 */    MCD_OPC_CheckField, 0, 4, 4, 223, 8, 0, // Skip to: 5329
3045
/* 3058 */    MCD_OPC_Decode, 241, 4, 180, 1, // Opcode: AE_DBI_IP
3046
/* 3063 */    MCD_OPC_FilterValue, 122, 17, 0, 0, // Skip to: 3085
3047
/* 3068 */    MCD_OPC_CheckPredicate, 24, 208, 8, 0, // Skip to: 5329
3048
/* 3073 */    MCD_OPC_CheckField, 0, 4, 4, 201, 8, 0, // Skip to: 5329
3049
/* 3080 */    MCD_OPC_Decode, 191, 10, 179, 1, // Opcode: AE_SB
3050
/* 3085 */    MCD_OPC_FilterValue, 123, 17, 0, 0, // Skip to: 3107
3051
/* 3090 */    MCD_OPC_CheckPredicate, 24, 186, 8, 0, // Skip to: 5329
3052
/* 3095 */    MCD_OPC_CheckField, 0, 4, 4, 179, 8, 0, // Skip to: 5329
3053
/* 3102 */    MCD_OPC_Decode, 198, 10, 179, 1, // Opcode: AE_SB_IC
3054
/* 3107 */    MCD_OPC_FilterValue, 124, 17, 0, 0, // Skip to: 3129
3055
/* 3112 */    MCD_OPC_CheckPredicate, 24, 164, 8, 0, // Skip to: 5329
3056
/* 3117 */    MCD_OPC_CheckField, 0, 4, 4, 157, 8, 0, // Skip to: 5329
3057
/* 3124 */    MCD_OPC_Decode, 199, 10, 179, 1, // Opcode: AE_SB_IP
3058
/* 3129 */    MCD_OPC_FilterValue, 126, 147, 8, 0, // Skip to: 5329
3059
/* 3134 */    MCD_OPC_ExtractField, 0, 8,  // Inst{7-0} ...
3060
/* 3137 */    MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 3152
3061
/* 3142 */    MCD_OPC_CheckPredicate, 24, 134, 8, 0, // Skip to: 5329
3062
/* 3147 */    MCD_OPC_Decode, 146, 11, 181, 1, // Opcode: AE_VLES16C
3063
/* 3152 */    MCD_OPC_FilterValue, 20, 10, 0, 0, // Skip to: 3167
3064
/* 3157 */    MCD_OPC_CheckPredicate, 24, 119, 8, 0, // Skip to: 5329
3065
/* 3162 */    MCD_OPC_Decode, 192, 10, 181, 1, // Opcode: AE_SBF
3066
/* 3167 */    MCD_OPC_FilterValue, 36, 10, 0, 0, // Skip to: 3182
3067
/* 3172 */    MCD_OPC_CheckPredicate, 24, 104, 8, 0, // Skip to: 5329
3068
/* 3177 */    MCD_OPC_Decode, 147, 11, 181, 1, // Opcode: AE_VLES16C_IC
3069
/* 3182 */    MCD_OPC_FilterValue, 52, 10, 0, 0, // Skip to: 3197
3070
/* 3187 */    MCD_OPC_CheckPredicate, 24, 89, 8, 0, // Skip to: 5329
3071
/* 3192 */    MCD_OPC_Decode, 193, 10, 181, 1, // Opcode: AE_SBF_IC
3072
/* 3197 */    MCD_OPC_FilterValue, 68, 10, 0, 0, // Skip to: 3212
3073
/* 3202 */    MCD_OPC_CheckPredicate, 24, 74, 8, 0, // Skip to: 5329
3074
/* 3207 */    MCD_OPC_Decode, 148, 11, 181, 1, // Opcode: AE_VLES16C_IP
3075
/* 3212 */    MCD_OPC_FilterValue, 84, 10, 0, 0, // Skip to: 3227
3076
/* 3217 */    MCD_OPC_CheckPredicate, 24, 59, 8, 0, // Skip to: 5329
3077
/* 3222 */    MCD_OPC_Decode, 194, 10, 181, 1, // Opcode: AE_SBF_IP
3078
/* 3227 */    MCD_OPC_FilterValue, 100, 10, 0, 0, // Skip to: 3242
3079
/* 3232 */    MCD_OPC_CheckPredicate, 24, 44, 8, 0, // Skip to: 5329
3080
/* 3237 */    MCD_OPC_Decode, 138, 11, 181, 1, // Opcode: AE_VLDL16C
3081
/* 3242 */    MCD_OPC_FilterValue, 116, 10, 0, 0, // Skip to: 3257
3082
/* 3247 */    MCD_OPC_CheckPredicate, 24, 29, 8, 0, // Skip to: 5329
3083
/* 3252 */    MCD_OPC_Decode, 139, 11, 181, 1, // Opcode: AE_VLDL16C_IC
3084
/* 3257 */    MCD_OPC_FilterValue, 132, 1, 18, 8, 0, // Skip to: 5329
3085
/* 3263 */    MCD_OPC_CheckPredicate, 24, 13, 8, 0, // Skip to: 5329
3086
/* 3268 */    MCD_OPC_Decode, 140, 11, 181, 1, // Opcode: AE_VLDL16C_IP
3087
/* 3273 */    MCD_OPC_FilterValue, 8, 171, 0, 0, // Skip to: 3449
3088
/* 3278 */    MCD_OPC_ExtractField, 18, 2,  // Inst{19-18} ...
3089
/* 3281 */    MCD_OPC_FilterValue, 0, 97, 0, 0, // Skip to: 3383
3090
/* 3286 */    MCD_OPC_ExtractField, 16, 2,  // Inst{17-16} ...
3091
/* 3289 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 3318
3092
/* 3294 */    MCD_OPC_CheckPredicate, 24, 238, 7, 0, // Skip to: 5329
3093
/* 3299 */    MCD_OPC_CheckField, 7, 1, 1, 231, 7, 0, // Skip to: 5329
3094
/* 3306 */    MCD_OPC_CheckField, 0, 4, 4, 224, 7, 0, // Skip to: 5329
3095
/* 3313 */    MCD_OPC_Decode, 235, 9, 174, 1, // Opcode: AE_S16X4_IP
3096
/* 3318 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3340
3097
/* 3323 */    MCD_OPC_CheckPredicate, 24, 209, 7, 0, // Skip to: 5329
3098
/* 3328 */    MCD_OPC_CheckField, 0, 4, 4, 202, 7, 0, // Skip to: 5329
3099
/* 3335 */    MCD_OPC_Decode, 235, 10, 149, 1, // Opcode: AE_SRAA64
3100
/* 3340 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3362
3101
/* 3345 */    MCD_OPC_CheckPredicate, 24, 187, 7, 0, // Skip to: 5329
3102
/* 3350 */    MCD_OPC_CheckField, 0, 4, 4, 180, 7, 0, // Skip to: 5329
3103
/* 3357 */    MCD_OPC_Decode, 234, 10, 149, 1, // Opcode: AE_SRAA32S
3104
/* 3362 */    MCD_OPC_FilterValue, 3, 170, 7, 0, // Skip to: 5329
3105
/* 3367 */    MCD_OPC_CheckPredicate, 24, 165, 7, 0, // Skip to: 5329
3106
/* 3372 */    MCD_OPC_CheckField, 0, 4, 4, 158, 7, 0, // Skip to: 5329
3107
/* 3379 */    MCD_OPC_Decode, 209, 5, 1, // Opcode: AE_LBK
3108
/* 3383 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3405
3109
/* 3388 */    MCD_OPC_CheckPredicate, 24, 144, 7, 0, // Skip to: 5329
3110
/* 3393 */    MCD_OPC_CheckField, 0, 4, 4, 137, 7, 0, // Skip to: 5329
3111
/* 3400 */    MCD_OPC_Decode, 220, 10, 182, 1, // Opcode: AE_SLAISQ56S
3112
/* 3405 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3427
3113
/* 3410 */    MCD_OPC_CheckPredicate, 24, 122, 7, 0, // Skip to: 5329
3114
/* 3415 */    MCD_OPC_CheckField, 0, 4, 4, 115, 7, 0, // Skip to: 5329
3115
/* 3422 */    MCD_OPC_Decode, 218, 10, 182, 1, // Opcode: AE_SLAI64
3116
/* 3427 */    MCD_OPC_FilterValue, 3, 105, 7, 0, // Skip to: 5329
3117
/* 3432 */    MCD_OPC_CheckPredicate, 24, 100, 7, 0, // Skip to: 5329
3118
/* 3437 */    MCD_OPC_CheckField, 0, 4, 4, 93, 7, 0, // Skip to: 5329
3119
/* 3444 */    MCD_OPC_Decode, 241, 10, 182, 1, // Opcode: AE_SRAI64
3120
/* 3449 */    MCD_OPC_FilterValue, 9, 193, 0, 0, // Skip to: 3647
3121
/* 3454 */    MCD_OPC_ExtractField, 17, 3,  // Inst{19-17} ...
3122
/* 3457 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 3493
3123
/* 3462 */    MCD_OPC_CheckPredicate, 24, 70, 7, 0, // Skip to: 5329
3124
/* 3467 */    MCD_OPC_CheckField, 16, 1, 0, 63, 7, 0, // Skip to: 5329
3125
/* 3474 */    MCD_OPC_CheckField, 7, 1, 1, 56, 7, 0, // Skip to: 5329
3126
/* 3481 */    MCD_OPC_CheckField, 0, 4, 4, 49, 7, 0, // Skip to: 5329
3127
/* 3488 */    MCD_OPC_Decode, 132, 5, 163, 1, // Opcode: AE_L16X4_IP
3128
/* 3493 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3515
3129
/* 3498 */    MCD_OPC_CheckPredicate, 24, 34, 7, 0, // Skip to: 5329
3130
/* 3503 */    MCD_OPC_CheckField, 0, 4, 4, 27, 7, 0, // Skip to: 5329
3131
/* 3510 */    MCD_OPC_Decode, 248, 10, 183, 1, // Opcode: AE_SRLI32
3132
/* 3515 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3537
3133
/* 3520 */    MCD_OPC_CheckPredicate, 24, 12, 7, 0, // Skip to: 5329
3134
/* 3525 */    MCD_OPC_CheckField, 0, 4, 4, 5, 7, 0, // Skip to: 5329
3135
/* 3532 */    MCD_OPC_Decode, 214, 10, 183, 1, // Opcode: AE_SLAI24
3136
/* 3537 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3559
3137
/* 3542 */    MCD_OPC_CheckPredicate, 24, 246, 6, 0, // Skip to: 5329
3138
/* 3547 */    MCD_OPC_CheckField, 0, 4, 4, 239, 6, 0, // Skip to: 5329
3139
/* 3554 */    MCD_OPC_Decode, 216, 10, 183, 1, // Opcode: AE_SLAI32
3140
/* 3559 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3581
3141
/* 3564 */    MCD_OPC_CheckPredicate, 24, 224, 6, 0, // Skip to: 5329
3142
/* 3569 */    MCD_OPC_CheckField, 0, 4, 4, 217, 6, 0, // Skip to: 5329
3143
/* 3576 */    MCD_OPC_Decode, 215, 10, 183, 1, // Opcode: AE_SLAI24S
3144
/* 3581 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3603
3145
/* 3586 */    MCD_OPC_CheckPredicate, 24, 202, 6, 0, // Skip to: 5329
3146
/* 3591 */    MCD_OPC_CheckField, 0, 4, 4, 195, 6, 0, // Skip to: 5329
3147
/* 3598 */    MCD_OPC_Decode, 217, 10, 183, 1, // Opcode: AE_SLAI32S
3148
/* 3603 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3625
3149
/* 3608 */    MCD_OPC_CheckPredicate, 24, 180, 6, 0, // Skip to: 5329
3150
/* 3613 */    MCD_OPC_CheckField, 0, 4, 4, 173, 6, 0, // Skip to: 5329
3151
/* 3620 */    MCD_OPC_Decode, 238, 10, 183, 1, // Opcode: AE_SRAI24
3152
/* 3625 */    MCD_OPC_FilterValue, 7, 163, 6, 0, // Skip to: 5329
3153
/* 3630 */    MCD_OPC_CheckPredicate, 24, 158, 6, 0, // Skip to: 5329
3154
/* 3635 */    MCD_OPC_CheckField, 0, 4, 4, 151, 6, 0, // Skip to: 5329
3155
/* 3642 */    MCD_OPC_Decode, 239, 10, 183, 1, // Opcode: AE_SRAI32
3156
/* 3647 */    MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3669
3157
/* 3652 */    MCD_OPC_CheckPredicate, 24, 136, 6, 0, // Skip to: 5329
3158
/* 3657 */    MCD_OPC_CheckField, 0, 4, 4, 129, 6, 0, // Skip to: 5329
3159
/* 3664 */    MCD_OPC_Decode, 200, 10, 184, 1, // Opcode: AE_SEL16I
3160
/* 3669 */    MCD_OPC_FilterValue, 11, 99, 1, 0, // Skip to: 4029
3161
/* 3674 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
3162
/* 3677 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3699
3163
/* 3682 */    MCD_OPC_CheckPredicate, 24, 106, 6, 0, // Skip to: 5329
3164
/* 3687 */    MCD_OPC_CheckField, 0, 4, 4, 99, 6, 0, // Skip to: 5329
3165
/* 3694 */    MCD_OPC_Decode, 138, 5, 146, 1, // Opcode: AE_L16_I
3166
/* 3699 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3721
3167
/* 3704 */    MCD_OPC_CheckPredicate, 24, 84, 6, 0, // Skip to: 5329
3168
/* 3709 */    MCD_OPC_CheckField, 0, 4, 4, 77, 6, 0, // Skip to: 5329
3169
/* 3716 */    MCD_OPC_Decode, 249, 4, 146, 1, // Opcode: AE_L16M_I
3170
/* 3721 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3743
3171
/* 3726 */    MCD_OPC_CheckPredicate, 24, 62, 6, 0, // Skip to: 5329
3172
/* 3731 */    MCD_OPC_CheckField, 0, 4, 4, 55, 6, 0, // Skip to: 5329
3173
/* 3738 */    MCD_OPC_Decode, 250, 4, 169, 1, // Opcode: AE_L16M_IU
3174
/* 3743 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3765
3175
/* 3748 */    MCD_OPC_CheckPredicate, 24, 40, 6, 0, // Skip to: 5329
3176
/* 3753 */    MCD_OPC_CheckField, 0, 4, 4, 33, 6, 0, // Skip to: 5329
3177
/* 3760 */    MCD_OPC_Decode, 253, 4, 185, 1, // Opcode: AE_L16M_XU
3178
/* 3765 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3787
3179
/* 3770 */    MCD_OPC_CheckPredicate, 24, 18, 6, 0, // Skip to: 5329
3180
/* 3775 */    MCD_OPC_CheckField, 0, 4, 4, 11, 6, 0, // Skip to: 5329
3181
/* 3782 */    MCD_OPC_Decode, 139, 5, 169, 1, // Opcode: AE_L16_IP
3182
/* 3787 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3809
3183
/* 3792 */    MCD_OPC_CheckPredicate, 24, 252, 5, 0, // Skip to: 5329
3184
/* 3797 */    MCD_OPC_CheckField, 0, 4, 4, 245, 5, 0, // Skip to: 5329
3185
/* 3804 */    MCD_OPC_Decode, 146, 5, 185, 1, // Opcode: AE_L32F24_XC
3186
/* 3809 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3831
3187
/* 3814 */    MCD_OPC_CheckPredicate, 24, 230, 5, 0, // Skip to: 5329
3188
/* 3819 */    MCD_OPC_CheckField, 0, 4, 4, 223, 5, 0, // Skip to: 5329
3189
/* 3826 */    MCD_OPC_Decode, 143, 5, 146, 1, // Opcode: AE_L32F24_I
3190
/* 3831 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3853
3191
/* 3836 */    MCD_OPC_CheckPredicate, 24, 208, 5, 0, // Skip to: 5329
3192
/* 3841 */    MCD_OPC_CheckField, 0, 4, 4, 201, 5, 0, // Skip to: 5329
3193
/* 3848 */    MCD_OPC_Decode, 144, 5, 169, 1, // Opcode: AE_L32F24_IP
3194
/* 3853 */    MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 3875
3195
/* 3858 */    MCD_OPC_CheckPredicate, 24, 186, 5, 0, // Skip to: 5329
3196
/* 3863 */    MCD_OPC_CheckField, 0, 4, 4, 179, 5, 0, // Skip to: 5329
3197
/* 3870 */    MCD_OPC_Decode, 254, 4, 146, 1, // Opcode: AE_L16X2M_I
3198
/* 3875 */    MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 3897
3199
/* 3880 */    MCD_OPC_CheckPredicate, 24, 164, 5, 0, // Skip to: 5329
3200
/* 3885 */    MCD_OPC_CheckField, 0, 4, 4, 157, 5, 0, // Skip to: 5329
3201
/* 3892 */    MCD_OPC_Decode, 255, 4, 169, 1, // Opcode: AE_L16X2M_IU
3202
/* 3897 */    MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3919
3203
/* 3902 */    MCD_OPC_CheckPredicate, 24, 142, 5, 0, // Skip to: 5329
3204
/* 3907 */    MCD_OPC_CheckField, 0, 4, 4, 135, 5, 0, // Skip to: 5329
3205
/* 3914 */    MCD_OPC_Decode, 128, 5, 153, 1, // Opcode: AE_L16X2M_X
3206
/* 3919 */    MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 3941
3207
/* 3924 */    MCD_OPC_CheckPredicate, 24, 120, 5, 0, // Skip to: 5329
3208
/* 3929 */    MCD_OPC_CheckField, 0, 4, 4, 113, 5, 0, // Skip to: 5329
3209
/* 3936 */    MCD_OPC_Decode, 130, 5, 185, 1, // Opcode: AE_L16X2M_XU
3210
/* 3941 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3963
3211
/* 3946 */    MCD_OPC_CheckPredicate, 24, 98, 5, 0, // Skip to: 5329
3212
/* 3951 */    MCD_OPC_CheckField, 0, 4, 4, 91, 5, 0, // Skip to: 5329
3213
/* 3958 */    MCD_OPC_Decode, 170, 5, 185, 1, // Opcode: AE_L32_XC
3214
/* 3963 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3985
3215
/* 3968 */    MCD_OPC_CheckPredicate, 24, 76, 5, 0, // Skip to: 5329
3216
/* 3973 */    MCD_OPC_CheckField, 0, 4, 4, 69, 5, 0, // Skip to: 5329
3217
/* 3980 */    MCD_OPC_Decode, 167, 5, 146, 1, // Opcode: AE_L32_I
3218
/* 3985 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 4007
3219
/* 3990 */    MCD_OPC_CheckPredicate, 24, 54, 5, 0, // Skip to: 5329
3220
/* 3995 */    MCD_OPC_CheckField, 0, 4, 4, 47, 5, 0, // Skip to: 5329
3221
/* 4002 */    MCD_OPC_Decode, 168, 5, 169, 1, // Opcode: AE_L32_IP
3222
/* 4007 */    MCD_OPC_FilterValue, 15, 37, 5, 0, // Skip to: 5329
3223
/* 4012 */    MCD_OPC_CheckPredicate, 24, 32, 5, 0, // Skip to: 5329
3224
/* 4017 */    MCD_OPC_CheckField, 0, 4, 4, 25, 5, 0, // Skip to: 5329
3225
/* 4024 */    MCD_OPC_Decode, 169, 5, 153, 1, // Opcode: AE_L32_X
3226
/* 4029 */    MCD_OPC_FilterValue, 12, 99, 1, 0, // Skip to: 4389
3227
/* 4034 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
3228
/* 4037 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4059
3229
/* 4042 */    MCD_OPC_CheckPredicate, 24, 2, 5, 0, // Skip to: 5329
3230
/* 4047 */    MCD_OPC_CheckField, 0, 4, 4, 251, 4, 0, // Skip to: 5329
3231
/* 4054 */    MCD_OPC_Decode, 165, 5, 185, 1, // Opcode: AE_L32X2_XC
3232
/* 4059 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4081
3233
/* 4064 */    MCD_OPC_CheckPredicate, 24, 236, 4, 0, // Skip to: 5329
3234
/* 4069 */    MCD_OPC_CheckField, 0, 4, 4, 229, 4, 0, // Skip to: 5329
3235
/* 4076 */    MCD_OPC_Decode, 160, 5, 146, 1, // Opcode: AE_L32X2_I
3236
/* 4081 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4103
3237
/* 4086 */    MCD_OPC_CheckPredicate, 24, 214, 4, 0, // Skip to: 5329
3238
/* 4091 */    MCD_OPC_CheckField, 0, 4, 4, 207, 4, 0, // Skip to: 5329
3239
/* 4098 */    MCD_OPC_Decode, 164, 5, 153, 1, // Opcode: AE_L32X2_X
3240
/* 4103 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 4125
3241
/* 4108 */    MCD_OPC_CheckPredicate, 24, 192, 4, 0, // Skip to: 5329
3242
/* 4113 */    MCD_OPC_CheckField, 0, 4, 4, 185, 4, 0, // Skip to: 5329
3243
/* 4120 */    MCD_OPC_Decode, 166, 5, 185, 1, // Opcode: AE_L32X2_XP
3244
/* 4125 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 4147
3245
/* 4130 */    MCD_OPC_CheckPredicate, 24, 170, 4, 0, // Skip to: 5329
3246
/* 4135 */    MCD_OPC_CheckField, 0, 4, 4, 163, 4, 0, // Skip to: 5329
3247
/* 4142 */    MCD_OPC_Decode, 158, 5, 185, 1, // Opcode: AE_L32X2F24_XC
3248
/* 4147 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 4169
3249
/* 4152 */    MCD_OPC_CheckPredicate, 24, 148, 4, 0, // Skip to: 5329
3250
/* 4157 */    MCD_OPC_CheckField, 0, 4, 4, 141, 4, 0, // Skip to: 5329
3251
/* 4164 */    MCD_OPC_Decode, 153, 5, 146, 1, // Opcode: AE_L32X2F24_I
3252
/* 4169 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 4191
3253
/* 4174 */    MCD_OPC_CheckPredicate, 24, 126, 4, 0, // Skip to: 5329
3254
/* 4179 */    MCD_OPC_CheckField, 0, 4, 4, 119, 4, 0, // Skip to: 5329
3255
/* 4186 */    MCD_OPC_Decode, 157, 5, 153, 1, // Opcode: AE_L32X2F24_X
3256
/* 4191 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 4213
3257
/* 4196 */    MCD_OPC_CheckPredicate, 24, 104, 4, 0, // Skip to: 5329
3258
/* 4201 */    MCD_OPC_CheckField, 0, 4, 4, 97, 4, 0, // Skip to: 5329
3259
/* 4208 */    MCD_OPC_Decode, 159, 5, 185, 1, // Opcode: AE_L32X2F24_XP
3260
/* 4213 */    MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 4235
3261
/* 4218 */    MCD_OPC_CheckPredicate, 24, 82, 4, 0, // Skip to: 5329
3262
/* 4223 */    MCD_OPC_CheckField, 0, 4, 4, 75, 4, 0, // Skip to: 5329
3263
/* 4230 */    MCD_OPC_Decode, 148, 5, 146, 1, // Opcode: AE_L32M_I
3264
/* 4235 */    MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 4257
3265
/* 4240 */    MCD_OPC_CheckPredicate, 24, 60, 4, 0, // Skip to: 5329
3266
/* 4245 */    MCD_OPC_CheckField, 0, 4, 4, 53, 4, 0, // Skip to: 5329
3267
/* 4252 */    MCD_OPC_Decode, 149, 5, 169, 1, // Opcode: AE_L32M_IU
3268
/* 4257 */    MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 4279
3269
/* 4262 */    MCD_OPC_CheckPredicate, 24, 38, 4, 0, // Skip to: 5329
3270
/* 4267 */    MCD_OPC_CheckField, 0, 4, 4, 31, 4, 0, // Skip to: 5329
3271
/* 4274 */    MCD_OPC_Decode, 150, 5, 153, 1, // Opcode: AE_L32M_X
3272
/* 4279 */    MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 4301
3273
/* 4284 */    MCD_OPC_CheckPredicate, 24, 16, 4, 0, // Skip to: 5329
3274
/* 4289 */    MCD_OPC_CheckField, 0, 4, 4, 9, 4, 0, // Skip to: 5329
3275
/* 4296 */    MCD_OPC_Decode, 152, 5, 185, 1, // Opcode: AE_L32M_XU
3276
/* 4301 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 4323
3277
/* 4306 */    MCD_OPC_CheckPredicate, 24, 250, 3, 0, // Skip to: 5329
3278
/* 4311 */    MCD_OPC_CheckField, 0, 4, 4, 243, 3, 0, // Skip to: 5329
3279
/* 4318 */    MCD_OPC_Decode, 131, 5, 146, 1, // Opcode: AE_L16X4_I
3280
/* 4323 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 4345
3281
/* 4328 */    MCD_OPC_CheckPredicate, 24, 228, 3, 0, // Skip to: 5329
3282
/* 4333 */    MCD_OPC_CheckField, 0, 4, 4, 221, 3, 0, // Skip to: 5329
3283
/* 4340 */    MCD_OPC_Decode, 137, 5, 185, 1, // Opcode: AE_L16X4_XP
3284
/* 4345 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 4367
3285
/* 4350 */    MCD_OPC_CheckPredicate, 24, 206, 3, 0, // Skip to: 5329
3286
/* 4355 */    MCD_OPC_CheckField, 0, 4, 4, 199, 3, 0, // Skip to: 5329
3287
/* 4362 */    MCD_OPC_Decode, 210, 5, 186, 1, // Opcode: AE_LBKI
3288
/* 4367 */    MCD_OPC_FilterValue, 15, 189, 3, 0, // Skip to: 5329
3289
/* 4372 */    MCD_OPC_CheckPredicate, 24, 184, 3, 0, // Skip to: 5329
3290
/* 4377 */    MCD_OPC_CheckField, 0, 4, 4, 177, 3, 0, // Skip to: 5329
3291
/* 4384 */    MCD_OPC_Decode, 172, 5, 146, 1, // Opcode: AE_L64_I
3292
/* 4389 */    MCD_OPC_FilterValue, 13, 99, 1, 0, // Skip to: 4749
3293
/* 4394 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
3294
/* 4397 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4419
3295
/* 4402 */    MCD_OPC_CheckPredicate, 24, 154, 3, 0, // Skip to: 5329
3296
/* 4407 */    MCD_OPC_CheckField, 0, 4, 4, 147, 3, 0, // Skip to: 5329
3297
/* 4414 */    MCD_OPC_Decode, 145, 11, 187, 1, // Opcode: AE_VLEL32T
3298
/* 4419 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4441
3299
/* 4424 */    MCD_OPC_CheckPredicate, 24, 132, 3, 0, // Skip to: 5329
3300
/* 4429 */    MCD_OPC_CheckField, 0, 4, 4, 125, 3, 0, // Skip to: 5329
3301
/* 4436 */    MCD_OPC_Decode, 144, 11, 187, 1, // Opcode: AE_VLEL16T
3302
/* 4441 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4463
3303
/* 4446 */    MCD_OPC_CheckPredicate, 24, 110, 3, 0, // Skip to: 5329
3304
/* 4451 */    MCD_OPC_CheckField, 0, 4, 4, 103, 3, 0, // Skip to: 5329
3305
/* 4458 */    MCD_OPC_Decode, 241, 9, 146, 1, // Opcode: AE_S16_0_I
3306
/* 4463 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 4485
3307
/* 4468 */    MCD_OPC_CheckPredicate, 24, 88, 3, 0, // Skip to: 5329
3308
/* 4473 */    MCD_OPC_CheckField, 0, 4, 4, 81, 3, 0, // Skip to: 5329
3309
/* 4480 */    MCD_OPC_Decode, 242, 9, 147, 1, // Opcode: AE_S16_0_IP
3310
/* 4485 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 4507
3311
/* 4490 */    MCD_OPC_CheckPredicate, 24, 66, 3, 0, // Skip to: 5329
3312
/* 4495 */    MCD_OPC_CheckField, 0, 4, 4, 59, 3, 0, // Skip to: 5329
3313
/* 4502 */    MCD_OPC_Decode, 245, 9, 148, 1, // Opcode: AE_S16_0_XP
3314
/* 4507 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 4529
3315
/* 4512 */    MCD_OPC_CheckPredicate, 24, 44, 3, 0, // Skip to: 5329
3316
/* 4517 */    MCD_OPC_CheckField, 0, 4, 4, 37, 3, 0, // Skip to: 5329
3317
/* 4524 */    MCD_OPC_Decode, 224, 9, 146, 1, // Opcode: AE_S16M_L_I
3318
/* 4529 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 4551
3319
/* 4534 */    MCD_OPC_CheckPredicate, 24, 22, 3, 0, // Skip to: 5329
3320
/* 4539 */    MCD_OPC_CheckField, 0, 4, 4, 15, 3, 0, // Skip to: 5329
3321
/* 4546 */    MCD_OPC_Decode, 225, 9, 147, 1, // Opcode: AE_S16M_L_IU
3322
/* 4551 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 4573
3323
/* 4556 */    MCD_OPC_CheckPredicate, 24, 0, 3, 0, // Skip to: 5329
3324
/* 4561 */    MCD_OPC_CheckField, 0, 4, 4, 249, 2, 0, // Skip to: 5329
3325
/* 4568 */    MCD_OPC_Decode, 226, 9, 153, 1, // Opcode: AE_S16M_L_X
3326
/* 4573 */    MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 4595
3327
/* 4578 */    MCD_OPC_CheckPredicate, 24, 234, 2, 0, // Skip to: 5329
3328
/* 4583 */    MCD_OPC_CheckField, 0, 4, 4, 227, 2, 0, // Skip to: 5329
3329
/* 4590 */    MCD_OPC_Decode, 229, 9, 146, 1, // Opcode: AE_S16X2M_I
3330
/* 4595 */    MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 4617
3331
/* 4600 */    MCD_OPC_CheckPredicate, 24, 212, 2, 0, // Skip to: 5329
3332
/* 4605 */    MCD_OPC_CheckField, 0, 4, 4, 205, 2, 0, // Skip to: 5329
3333
/* 4612 */    MCD_OPC_Decode, 230, 9, 147, 1, // Opcode: AE_S16X2M_IU
3334
/* 4617 */    MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 4639
3335
/* 4622 */    MCD_OPC_CheckPredicate, 24, 190, 2, 0, // Skip to: 5329
3336
/* 4627 */    MCD_OPC_CheckField, 0, 4, 4, 183, 2, 0, // Skip to: 5329
3337
/* 4634 */    MCD_OPC_Decode, 231, 9, 153, 1, // Opcode: AE_S16X2M_X
3338
/* 4639 */    MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 4661
3339
/* 4644 */    MCD_OPC_CheckPredicate, 24, 168, 2, 0, // Skip to: 5329
3340
/* 4649 */    MCD_OPC_CheckField, 0, 4, 4, 161, 2, 0, // Skip to: 5329
3341
/* 4656 */    MCD_OPC_Decode, 233, 9, 148, 1, // Opcode: AE_S16X2M_XU
3342
/* 4661 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 4683
3343
/* 4666 */    MCD_OPC_CheckPredicate, 24, 146, 2, 0, // Skip to: 5329
3344
/* 4671 */    MCD_OPC_CheckField, 0, 4, 4, 139, 2, 0, // Skip to: 5329
3345
/* 4678 */    MCD_OPC_Decode, 234, 9, 146, 1, // Opcode: AE_S16X4_I
3346
/* 4683 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 4705
3347
/* 4688 */    MCD_OPC_CheckPredicate, 24, 124, 2, 0, // Skip to: 5329
3348
/* 4693 */    MCD_OPC_CheckField, 0, 4, 4, 117, 2, 0, // Skip to: 5329
3349
/* 4700 */    MCD_OPC_Decode, 250, 9, 148, 1, // Opcode: AE_S24RA64S_XP
3350
/* 4705 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 4727
3351
/* 4710 */    MCD_OPC_CheckPredicate, 24, 102, 2, 0, // Skip to: 5329
3352
/* 4715 */    MCD_OPC_CheckField, 0, 4, 4, 95, 2, 0, // Skip to: 5329
3353
/* 4722 */    MCD_OPC_Decode, 252, 9, 146, 1, // Opcode: AE_S32F24_L_I
3354
/* 4727 */    MCD_OPC_FilterValue, 15, 85, 2, 0, // Skip to: 5329
3355
/* 4732 */    MCD_OPC_CheckPredicate, 24, 80, 2, 0, // Skip to: 5329
3356
/* 4737 */    MCD_OPC_CheckField, 0, 4, 4, 73, 2, 0, // Skip to: 5329
3357
/* 4744 */    MCD_OPC_Decode, 253, 9, 147, 1, // Opcode: AE_S32F24_L_IP
3358
/* 4749 */    MCD_OPC_FilterValue, 14, 198, 1, 0, // Skip to: 5208
3359
/* 4754 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
3360
/* 4757 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4779
3361
/* 4762 */    MCD_OPC_CheckPredicate, 24, 50, 2, 0, // Skip to: 5329
3362
/* 4767 */    MCD_OPC_CheckField, 0, 4, 4, 43, 2, 0, // Skip to: 5329
3363
/* 4774 */    MCD_OPC_Decode, 154, 10, 146, 1, // Opcode: AE_S32_L_I
3364
/* 4779 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4801
3365
/* 4784 */    MCD_OPC_CheckPredicate, 24, 28, 2, 0, // Skip to: 5329
3366
/* 4789 */    MCD_OPC_CheckField, 0, 4, 4, 21, 2, 0, // Skip to: 5329
3367
/* 4796 */    MCD_OPC_Decode, 155, 10, 147, 1, // Opcode: AE_S32_L_IP
3368
/* 4801 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4823
3369
/* 4806 */    MCD_OPC_CheckPredicate, 24, 6, 2, 0, // Skip to: 5329
3370
/* 4811 */    MCD_OPC_CheckField, 0, 4, 4, 255, 1, 0, // Skip to: 5329
3371
/* 4818 */    MCD_OPC_Decode, 156, 10, 153, 1, // Opcode: AE_S32_L_X
3372
/* 4823 */    MCD_OPC_FilterValue, 3, 116, 0, 0, // Skip to: 4944
3373
/* 4828 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
3374
/* 4831 */    MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 4929
3375
/* 4836 */    MCD_OPC_ExtractField, 4, 8,  // Inst{11-4} ...
3376
/* 4839 */    MCD_OPC_FilterValue, 240, 1, 9, 0, 0, // Skip to: 4854
3377
/* 4845 */    MCD_OPC_CheckPredicate, 24, 223, 1, 0, // Skip to: 5329
3378
/* 4850 */    MCD_OPC_Decode, 208, 14, 80, // Opcode: RUR_AE_OVF_SAR
3379
/* 4854 */    MCD_OPC_FilterValue, 241, 1, 9, 0, 0, // Skip to: 4869
3380
/* 4860 */    MCD_OPC_CheckPredicate, 24, 208, 1, 0, // Skip to: 5329
3381
/* 4865 */    MCD_OPC_Decode, 198, 14, 80, // Opcode: RUR_AE_BITHEAD
3382
/* 4869 */    MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 4884
3383
/* 4875 */    MCD_OPC_CheckPredicate, 24, 193, 1, 0, // Skip to: 5329
3384
/* 4880 */    MCD_OPC_Decode, 212, 14, 80, // Opcode: RUR_AE_TS_FTS_BU_BP
3385
/* 4884 */    MCD_OPC_FilterValue, 243, 1, 9, 0, 0, // Skip to: 4899
3386
/* 4890 */    MCD_OPC_CheckPredicate, 24, 178, 1, 0, // Skip to: 5329
3387
/* 4895 */    MCD_OPC_Decode, 204, 14, 80, // Opcode: RUR_AE_CW_SD_NO
3388
/* 4899 */    MCD_OPC_FilterValue, 246, 1, 9, 0, 0, // Skip to: 4914
3389
/* 4905 */    MCD_OPC_CheckPredicate, 24, 163, 1, 0, // Skip to: 5329
3390
/* 4910 */    MCD_OPC_Decode, 201, 14, 80, // Opcode: RUR_AE_CBEGIN0
3391
/* 4914 */    MCD_OPC_FilterValue, 247, 1, 153, 1, 0, // Skip to: 5329
3392
/* 4920 */    MCD_OPC_CheckPredicate, 24, 148, 1, 0, // Skip to: 5329
3393
/* 4925 */    MCD_OPC_Decode, 202, 14, 80, // Opcode: RUR_AE_CEND0
3394
/* 4929 */    MCD_OPC_FilterValue, 4, 139, 1, 0, // Skip to: 5329
3395
/* 4934 */    MCD_OPC_CheckPredicate, 24, 134, 1, 0, // Skip to: 5329
3396
/* 4939 */    MCD_OPC_Decode, 158, 10, 148, 1, // Opcode: AE_S32_L_XP
3397
/* 4944 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 4966
3398
/* 4949 */    MCD_OPC_CheckPredicate, 24, 119, 1, 0, // Skip to: 5329
3399
/* 4954 */    MCD_OPC_CheckField, 0, 4, 4, 112, 1, 0, // Skip to: 5329
3400
/* 4961 */    MCD_OPC_Decode, 129, 10, 146, 1, // Opcode: AE_S32M_I
3401
/* 4966 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 4988
3402
/* 4971 */    MCD_OPC_CheckPredicate, 24, 97, 1, 0, // Skip to: 5329
3403
/* 4976 */    MCD_OPC_CheckField, 0, 4, 4, 90, 1, 0, // Skip to: 5329
3404
/* 4983 */    MCD_OPC_Decode, 130, 10, 147, 1, // Opcode: AE_S32M_IU
3405
/* 4988 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 5010
3406
/* 4993 */    MCD_OPC_CheckPredicate, 24, 75, 1, 0, // Skip to: 5329
3407
/* 4998 */    MCD_OPC_CheckField, 0, 4, 4, 68, 1, 0, // Skip to: 5329
3408
/* 5005 */    MCD_OPC_Decode, 131, 10, 153, 1, // Opcode: AE_S32M_X
3409
/* 5010 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 5032
3410
/* 5015 */    MCD_OPC_CheckPredicate, 24, 53, 1, 0, // Skip to: 5329
3411
/* 5020 */    MCD_OPC_CheckField, 0, 4, 4, 46, 1, 0, // Skip to: 5329
3412
/* 5027 */    MCD_OPC_Decode, 133, 10, 148, 1, // Opcode: AE_S32M_XU
3413
/* 5032 */    MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 5054
3414
/* 5037 */    MCD_OPC_CheckPredicate, 24, 31, 1, 0, // Skip to: 5329
3415
/* 5042 */    MCD_OPC_CheckField, 0, 4, 4, 24, 1, 0, // Skip to: 5329
3416
/* 5049 */    MCD_OPC_Decode, 152, 10, 148, 1, // Opcode: AE_S32X2_XC
3417
/* 5054 */    MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 5076
3418
/* 5059 */    MCD_OPC_CheckPredicate, 24, 9, 1, 0, // Skip to: 5329
3419
/* 5064 */    MCD_OPC_CheckField, 0, 4, 4, 2, 1, 0, // Skip to: 5329
3420
/* 5071 */    MCD_OPC_Decode, 147, 10, 146, 1, // Opcode: AE_S32X2_I
3421
/* 5076 */    MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 5098
3422
/* 5081 */    MCD_OPC_CheckPredicate, 24, 243, 0, 0, // Skip to: 5329
3423
/* 5086 */    MCD_OPC_CheckField, 0, 4, 4, 236, 0, 0, // Skip to: 5329
3424
/* 5093 */    MCD_OPC_Decode, 151, 10, 153, 1, // Opcode: AE_S32X2_X
3425
/* 5098 */    MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 5120
3426
/* 5103 */    MCD_OPC_CheckPredicate, 24, 221, 0, 0, // Skip to: 5329
3427
/* 5108 */    MCD_OPC_CheckField, 0, 4, 4, 214, 0, 0, // Skip to: 5329
3428
/* 5115 */    MCD_OPC_Decode, 153, 10, 148, 1, // Opcode: AE_S32X2_XP
3429
/* 5120 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 5142
3430
/* 5125 */    MCD_OPC_CheckPredicate, 24, 199, 0, 0, // Skip to: 5329
3431
/* 5130 */    MCD_OPC_CheckField, 0, 4, 4, 192, 0, 0, // Skip to: 5329
3432
/* 5137 */    MCD_OPC_Decode, 144, 10, 148, 1, // Opcode: AE_S32X2F24_XC
3433
/* 5142 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 5164
3434
/* 5147 */    MCD_OPC_CheckPredicate, 24, 177, 0, 0, // Skip to: 5329
3435
/* 5152 */    MCD_OPC_CheckField, 0, 4, 4, 170, 0, 0, // Skip to: 5329
3436
/* 5159 */    MCD_OPC_Decode, 139, 10, 146, 1, // Opcode: AE_S32X2F24_I
3437
/* 5164 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 5186
3438
/* 5169 */    MCD_OPC_CheckPredicate, 24, 155, 0, 0, // Skip to: 5329
3439
/* 5174 */    MCD_OPC_CheckField, 0, 4, 4, 148, 0, 0, // Skip to: 5329
3440
/* 5181 */    MCD_OPC_Decode, 143, 10, 153, 1, // Opcode: AE_S32X2F24_X
3441
/* 5186 */    MCD_OPC_FilterValue, 15, 138, 0, 0, // Skip to: 5329
3442
/* 5191 */    MCD_OPC_CheckPredicate, 24, 133, 0, 0, // Skip to: 5329
3443
/* 5196 */    MCD_OPC_CheckField, 0, 4, 4, 126, 0, 0, // Skip to: 5329
3444
/* 5203 */    MCD_OPC_Decode, 145, 10, 148, 1, // Opcode: AE_S32X2F24_XP
3445
/* 5208 */    MCD_OPC_FilterValue, 15, 116, 0, 0, // Skip to: 5329
3446
/* 5213 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
3447
/* 5216 */    MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 5314
3448
/* 5221 */    MCD_OPC_ExtractField, 8, 12,  // Inst{19-8} ...
3449
/* 5224 */    MCD_OPC_FilterValue, 240, 7, 9, 0, 0, // Skip to: 5239
3450
/* 5230 */    MCD_OPC_CheckPredicate, 24, 94, 0, 0, // Skip to: 5329
3451
/* 5235 */    MCD_OPC_Decode, 164, 15, 25, // Opcode: WUR_AE_OVF_SAR
3452
/* 5239 */    MCD_OPC_FilterValue, 241, 7, 9, 0, 0, // Skip to: 5254
3453
/* 5245 */    MCD_OPC_CheckPredicate, 24, 79, 0, 0, // Skip to: 5329
3454
/* 5250 */    MCD_OPC_Decode, 154, 15, 25, // Opcode: WUR_AE_BITHEAD
3455
/* 5254 */    MCD_OPC_FilterValue, 242, 7, 9, 0, 0, // Skip to: 5269
3456
/* 5260 */    MCD_OPC_CheckPredicate, 24, 64, 0, 0, // Skip to: 5329
3457
/* 5265 */    MCD_OPC_Decode, 168, 15, 25, // Opcode: WUR_AE_TS_FTS_BU_BP
3458
/* 5269 */    MCD_OPC_FilterValue, 243, 7, 9, 0, 0, // Skip to: 5284
3459
/* 5275 */    MCD_OPC_CheckPredicate, 24, 49, 0, 0, // Skip to: 5329
3460
/* 5280 */    MCD_OPC_Decode, 160, 15, 25, // Opcode: WUR_AE_CW_SD_NO
3461
/* 5284 */    MCD_OPC_FilterValue, 246, 7, 9, 0, 0, // Skip to: 5299
3462
/* 5290 */    MCD_OPC_CheckPredicate, 24, 34, 0, 0, // Skip to: 5329
3463
/* 5295 */    MCD_OPC_Decode, 157, 15, 25, // Opcode: WUR_AE_CBEGIN0
3464
/* 5299 */    MCD_OPC_FilterValue, 247, 7, 24, 0, 0, // Skip to: 5329
3465
/* 5305 */    MCD_OPC_CheckPredicate, 24, 19, 0, 0, // Skip to: 5329
3466
/* 5310 */    MCD_OPC_Decode, 158, 15, 25, // Opcode: WUR_AE_CEND0
3467
/* 5314 */    MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 5329
3468
/* 5319 */    MCD_OPC_CheckPredicate, 24, 5, 0, 0, // Skip to: 5329
3469
/* 5324 */    MCD_OPC_Decode, 135, 11, 188, 1, // Opcode: AE_TRUNCA32X2F64S
3470
/* 5329 */    MCD_OPC_Fail,
3471
  0
3472
};
3473
3474
static const uint8_t DecoderTableHIFI348[] = {
3475
/* 0 */       MCD_OPC_ExtractField, 30, 18,  // Inst{47-30} ...
3476
/* 3 */       MCD_OPC_FilterValue, 128, 4, 24, 0, 0, // Skip to: 33
3477
/* 9 */       MCD_OPC_CheckPredicate, 24, 176, 30, 0, // Skip to: 7870
3478
/* 14 */      MCD_OPC_CheckField, 28, 2, 0, 169, 30, 0, // Skip to: 7870
3479
/* 21 */      MCD_OPC_CheckField, 0, 16, 14, 162, 30, 0, // Skip to: 7870
3480
/* 28 */      MCD_OPC_Decode, 247, 5, 189, 1, // Opcode: AE_MUL32U_LL
3481
/* 33 */      MCD_OPC_FilterValue, 128, 8, 24, 0, 0, // Skip to: 63
3482
/* 39 */      MCD_OPC_CheckPredicate, 24, 146, 30, 0, // Skip to: 7870
3483
/* 44 */      MCD_OPC_CheckField, 28, 2, 0, 139, 30, 0, // Skip to: 7870
3484
/* 51 */      MCD_OPC_CheckField, 0, 16, 14, 132, 30, 0, // Skip to: 7870
3485
/* 58 */      MCD_OPC_Decode, 248, 5, 189, 1, // Opcode: AE_MUL32X16_H0
3486
/* 63 */      MCD_OPC_FilterValue, 128, 12, 24, 0, 0, // Skip to: 93
3487
/* 69 */      MCD_OPC_CheckPredicate, 24, 116, 30, 0, // Skip to: 7870
3488
/* 74 */      MCD_OPC_CheckField, 28, 2, 0, 109, 30, 0, // Skip to: 7870
3489
/* 81 */      MCD_OPC_CheckField, 0, 16, 14, 102, 30, 0, // Skip to: 7870
3490
/* 88 */      MCD_OPC_Decode, 250, 5, 189, 1, // Opcode: AE_MUL32X16_H1
3491
/* 93 */      MCD_OPC_FilterValue, 128, 16, 24, 0, 0, // Skip to: 123
3492
/* 99 */      MCD_OPC_CheckPredicate, 24, 86, 30, 0, // Skip to: 7870
3493
/* 104 */     MCD_OPC_CheckField, 28, 2, 0, 79, 30, 0, // Skip to: 7870
3494
/* 111 */     MCD_OPC_CheckField, 0, 16, 14, 72, 30, 0, // Skip to: 7870
3495
/* 118 */     MCD_OPC_Decode, 252, 5, 189, 1, // Opcode: AE_MUL32X16_H2
3496
/* 123 */     MCD_OPC_FilterValue, 128, 20, 24, 0, 0, // Skip to: 153
3497
/* 129 */     MCD_OPC_CheckPredicate, 24, 56, 30, 0, // Skip to: 7870
3498
/* 134 */     MCD_OPC_CheckField, 28, 2, 0, 49, 30, 0, // Skip to: 7870
3499
/* 141 */     MCD_OPC_CheckField, 0, 16, 14, 42, 30, 0, // Skip to: 7870
3500
/* 148 */     MCD_OPC_Decode, 254, 5, 189, 1, // Opcode: AE_MUL32X16_H3
3501
/* 153 */     MCD_OPC_FilterValue, 128, 24, 24, 0, 0, // Skip to: 183
3502
/* 159 */     MCD_OPC_CheckPredicate, 24, 26, 30, 0, // Skip to: 7870
3503
/* 164 */     MCD_OPC_CheckField, 28, 2, 0, 19, 30, 0, // Skip to: 7870
3504
/* 171 */     MCD_OPC_CheckField, 0, 16, 14, 12, 30, 0, // Skip to: 7870
3505
/* 178 */     MCD_OPC_Decode, 128, 6, 189, 1, // Opcode: AE_MUL32X16_L0
3506
/* 183 */     MCD_OPC_FilterValue, 128, 28, 24, 0, 0, // Skip to: 213
3507
/* 189 */     MCD_OPC_CheckPredicate, 24, 252, 29, 0, // Skip to: 7870
3508
/* 194 */     MCD_OPC_CheckField, 28, 2, 0, 245, 29, 0, // Skip to: 7870
3509
/* 201 */     MCD_OPC_CheckField, 0, 16, 14, 238, 29, 0, // Skip to: 7870
3510
/* 208 */     MCD_OPC_Decode, 130, 6, 189, 1, // Opcode: AE_MUL32X16_L1
3511
/* 213 */     MCD_OPC_FilterValue, 128, 32, 24, 0, 0, // Skip to: 243
3512
/* 219 */     MCD_OPC_CheckPredicate, 24, 222, 29, 0, // Skip to: 7870
3513
/* 224 */     MCD_OPC_CheckField, 28, 2, 0, 215, 29, 0, // Skip to: 7870
3514
/* 231 */     MCD_OPC_CheckField, 0, 16, 14, 208, 29, 0, // Skip to: 7870
3515
/* 238 */     MCD_OPC_Decode, 132, 6, 189, 1, // Opcode: AE_MUL32X16_L2
3516
/* 243 */     MCD_OPC_FilterValue, 128, 36, 24, 0, 0, // Skip to: 273
3517
/* 249 */     MCD_OPC_CheckPredicate, 24, 192, 29, 0, // Skip to: 7870
3518
/* 254 */     MCD_OPC_CheckField, 28, 2, 0, 185, 29, 0, // Skip to: 7870
3519
/* 261 */     MCD_OPC_CheckField, 0, 16, 14, 178, 29, 0, // Skip to: 7870
3520
/* 268 */     MCD_OPC_Decode, 134, 6, 189, 1, // Opcode: AE_MUL32X16_L3
3521
/* 273 */     MCD_OPC_FilterValue, 128, 40, 24, 0, 0, // Skip to: 303
3522
/* 279 */     MCD_OPC_CheckPredicate, 24, 162, 29, 0, // Skip to: 7870
3523
/* 284 */     MCD_OPC_CheckField, 28, 2, 0, 155, 29, 0, // Skip to: 7870
3524
/* 291 */     MCD_OPC_CheckField, 0, 16, 14, 148, 29, 0, // Skip to: 7870
3525
/* 298 */     MCD_OPC_Decode, 136, 6, 189, 1, // Opcode: AE_MUL32_HH
3526
/* 303 */     MCD_OPC_FilterValue, 128, 44, 24, 0, 0, // Skip to: 333
3527
/* 309 */     MCD_OPC_CheckPredicate, 24, 132, 29, 0, // Skip to: 7870
3528
/* 314 */     MCD_OPC_CheckField, 28, 2, 0, 125, 29, 0, // Skip to: 7870
3529
/* 321 */     MCD_OPC_CheckField, 0, 16, 14, 118, 29, 0, // Skip to: 7870
3530
/* 328 */     MCD_OPC_Decode, 137, 6, 189, 1, // Opcode: AE_MUL32_LH
3531
/* 333 */     MCD_OPC_FilterValue, 128, 48, 24, 0, 0, // Skip to: 363
3532
/* 339 */     MCD_OPC_CheckPredicate, 24, 102, 29, 0, // Skip to: 7870
3533
/* 344 */     MCD_OPC_CheckField, 28, 2, 0, 95, 29, 0, // Skip to: 7870
3534
/* 351 */     MCD_OPC_CheckField, 0, 16, 14, 88, 29, 0, // Skip to: 7870
3535
/* 358 */     MCD_OPC_Decode, 138, 6, 189, 1, // Opcode: AE_MUL32_LL
3536
/* 363 */     MCD_OPC_FilterValue, 128, 56, 24, 0, 0, // Skip to: 393
3537
/* 369 */     MCD_OPC_CheckPredicate, 24, 72, 29, 0, // Skip to: 7870
3538
/* 374 */     MCD_OPC_CheckField, 28, 2, 0, 65, 29, 0, // Skip to: 7870
3539
/* 381 */     MCD_OPC_CheckField, 0, 16, 14, 58, 29, 0, // Skip to: 7870
3540
/* 388 */     MCD_OPC_Decode, 141, 6, 190, 1, // Opcode: AE_MULA32U_LL
3541
/* 393 */     MCD_OPC_FilterValue, 128, 60, 24, 0, 0, // Skip to: 423
3542
/* 399 */     MCD_OPC_CheckPredicate, 24, 42, 29, 0, // Skip to: 7870
3543
/* 404 */     MCD_OPC_CheckField, 28, 2, 0, 35, 29, 0, // Skip to: 7870
3544
/* 411 */     MCD_OPC_CheckField, 0, 16, 14, 28, 29, 0, // Skip to: 7870
3545
/* 418 */     MCD_OPC_Decode, 142, 6, 190, 1, // Opcode: AE_MULA32X16_H0
3546
/* 423 */     MCD_OPC_FilterValue, 128, 64, 24, 0, 0, // Skip to: 453
3547
/* 429 */     MCD_OPC_CheckPredicate, 24, 12, 29, 0, // Skip to: 7870
3548
/* 434 */     MCD_OPC_CheckField, 28, 2, 0, 5, 29, 0, // Skip to: 7870
3549
/* 441 */     MCD_OPC_CheckField, 0, 16, 14, 254, 28, 0, // Skip to: 7870
3550
/* 448 */     MCD_OPC_Decode, 144, 6, 190, 1, // Opcode: AE_MULA32X16_H1
3551
/* 453 */     MCD_OPC_FilterValue, 128, 68, 24, 0, 0, // Skip to: 483
3552
/* 459 */     MCD_OPC_CheckPredicate, 24, 238, 28, 0, // Skip to: 7870
3553
/* 464 */     MCD_OPC_CheckField, 28, 2, 0, 231, 28, 0, // Skip to: 7870
3554
/* 471 */     MCD_OPC_CheckField, 0, 16, 14, 224, 28, 0, // Skip to: 7870
3555
/* 478 */     MCD_OPC_Decode, 146, 6, 190, 1, // Opcode: AE_MULA32X16_H2
3556
/* 483 */     MCD_OPC_FilterValue, 128, 72, 24, 0, 0, // Skip to: 513
3557
/* 489 */     MCD_OPC_CheckPredicate, 24, 208, 28, 0, // Skip to: 7870
3558
/* 494 */     MCD_OPC_CheckField, 28, 2, 0, 201, 28, 0, // Skip to: 7870
3559
/* 501 */     MCD_OPC_CheckField, 0, 16, 14, 194, 28, 0, // Skip to: 7870
3560
/* 508 */     MCD_OPC_Decode, 148, 6, 190, 1, // Opcode: AE_MULA32X16_H3
3561
/* 513 */     MCD_OPC_FilterValue, 128, 76, 24, 0, 0, // Skip to: 543
3562
/* 519 */     MCD_OPC_CheckPredicate, 24, 178, 28, 0, // Skip to: 7870
3563
/* 524 */     MCD_OPC_CheckField, 28, 2, 0, 171, 28, 0, // Skip to: 7870
3564
/* 531 */     MCD_OPC_CheckField, 0, 16, 14, 164, 28, 0, // Skip to: 7870
3565
/* 538 */     MCD_OPC_Decode, 150, 6, 190, 1, // Opcode: AE_MULA32X16_L0
3566
/* 543 */     MCD_OPC_FilterValue, 128, 80, 24, 0, 0, // Skip to: 573
3567
/* 549 */     MCD_OPC_CheckPredicate, 24, 148, 28, 0, // Skip to: 7870
3568
/* 554 */     MCD_OPC_CheckField, 28, 2, 0, 141, 28, 0, // Skip to: 7870
3569
/* 561 */     MCD_OPC_CheckField, 0, 16, 14, 134, 28, 0, // Skip to: 7870
3570
/* 568 */     MCD_OPC_Decode, 152, 6, 190, 1, // Opcode: AE_MULA32X16_L1
3571
/* 573 */     MCD_OPC_FilterValue, 128, 84, 24, 0, 0, // Skip to: 603
3572
/* 579 */     MCD_OPC_CheckPredicate, 24, 118, 28, 0, // Skip to: 7870
3573
/* 584 */     MCD_OPC_CheckField, 28, 2, 0, 111, 28, 0, // Skip to: 7870
3574
/* 591 */     MCD_OPC_CheckField, 0, 16, 14, 104, 28, 0, // Skip to: 7870
3575
/* 598 */     MCD_OPC_Decode, 154, 6, 190, 1, // Opcode: AE_MULA32X16_L2
3576
/* 603 */     MCD_OPC_FilterValue, 128, 88, 24, 0, 0, // Skip to: 633
3577
/* 609 */     MCD_OPC_CheckPredicate, 24, 88, 28, 0, // Skip to: 7870
3578
/* 614 */     MCD_OPC_CheckField, 28, 2, 0, 81, 28, 0, // Skip to: 7870
3579
/* 621 */     MCD_OPC_CheckField, 0, 16, 14, 74, 28, 0, // Skip to: 7870
3580
/* 628 */     MCD_OPC_Decode, 156, 6, 190, 1, // Opcode: AE_MULA32X16_L3
3581
/* 633 */     MCD_OPC_FilterValue, 128, 92, 24, 0, 0, // Skip to: 663
3582
/* 639 */     MCD_OPC_CheckPredicate, 24, 58, 28, 0, // Skip to: 7870
3583
/* 644 */     MCD_OPC_CheckField, 28, 2, 0, 51, 28, 0, // Skip to: 7870
3584
/* 651 */     MCD_OPC_CheckField, 0, 16, 14, 44, 28, 0, // Skip to: 7870
3585
/* 658 */     MCD_OPC_Decode, 158, 6, 190, 1, // Opcode: AE_MULA32_HH
3586
/* 663 */     MCD_OPC_FilterValue, 128, 96, 24, 0, 0, // Skip to: 693
3587
/* 669 */     MCD_OPC_CheckPredicate, 24, 28, 28, 0, // Skip to: 7870
3588
/* 674 */     MCD_OPC_CheckField, 28, 2, 0, 21, 28, 0, // Skip to: 7870
3589
/* 681 */     MCD_OPC_CheckField, 0, 16, 14, 14, 28, 0, // Skip to: 7870
3590
/* 688 */     MCD_OPC_Decode, 159, 6, 190, 1, // Opcode: AE_MULA32_LH
3591
/* 693 */     MCD_OPC_FilterValue, 128, 100, 24, 0, 0, // Skip to: 723
3592
/* 699 */     MCD_OPC_CheckPredicate, 24, 254, 27, 0, // Skip to: 7870
3593
/* 704 */     MCD_OPC_CheckField, 28, 2, 0, 247, 27, 0, // Skip to: 7870
3594
/* 711 */     MCD_OPC_CheckField, 0, 16, 14, 240, 27, 0, // Skip to: 7870
3595
/* 718 */     MCD_OPC_Decode, 160, 6, 190, 1, // Opcode: AE_MULA32_LL
3596
/* 723 */     MCD_OPC_FilterValue, 128, 108, 24, 0, 0, // Skip to: 753
3597
/* 729 */     MCD_OPC_CheckPredicate, 24, 224, 27, 0, // Skip to: 7870
3598
/* 734 */     MCD_OPC_CheckField, 28, 2, 0, 217, 27, 0, // Skip to: 7870
3599
/* 741 */     MCD_OPC_CheckField, 0, 16, 14, 210, 27, 0, // Skip to: 7870
3600
/* 748 */     MCD_OPC_Decode, 166, 6, 190, 1, // Opcode: AE_MULAAD32X16_H0_L1
3601
/* 753 */     MCD_OPC_FilterValue, 128, 112, 24, 0, 0, // Skip to: 783
3602
/* 759 */     MCD_OPC_CheckPredicate, 24, 194, 27, 0, // Skip to: 7870
3603
/* 764 */     MCD_OPC_CheckField, 28, 2, 0, 187, 27, 0, // Skip to: 7870
3604
/* 771 */     MCD_OPC_CheckField, 0, 16, 14, 180, 27, 0, // Skip to: 7870
3605
/* 778 */     MCD_OPC_Decode, 168, 6, 190, 1, // Opcode: AE_MULAAD32X16_H1_L0
3606
/* 783 */     MCD_OPC_FilterValue, 128, 116, 24, 0, 0, // Skip to: 813
3607
/* 789 */     MCD_OPC_CheckPredicate, 24, 164, 27, 0, // Skip to: 7870
3608
/* 794 */     MCD_OPC_CheckField, 28, 2, 0, 157, 27, 0, // Skip to: 7870
3609
/* 801 */     MCD_OPC_CheckField, 0, 16, 14, 150, 27, 0, // Skip to: 7870
3610
/* 808 */     MCD_OPC_Decode, 170, 6, 190, 1, // Opcode: AE_MULAAD32X16_H2_L3
3611
/* 813 */     MCD_OPC_FilterValue, 128, 120, 24, 0, 0, // Skip to: 843
3612
/* 819 */     MCD_OPC_CheckPredicate, 24, 134, 27, 0, // Skip to: 7870
3613
/* 824 */     MCD_OPC_CheckField, 28, 2, 0, 127, 27, 0, // Skip to: 7870
3614
/* 831 */     MCD_OPC_CheckField, 0, 16, 14, 120, 27, 0, // Skip to: 7870
3615
/* 838 */     MCD_OPC_Decode, 172, 6, 190, 1, // Opcode: AE_MULAAD32X16_H3_L2
3616
/* 843 */     MCD_OPC_FilterValue, 128, 132, 1, 24, 0, 0, // Skip to: 874
3617
/* 850 */     MCD_OPC_CheckPredicate, 24, 103, 27, 0, // Skip to: 7870
3618
/* 855 */     MCD_OPC_CheckField, 28, 2, 0, 96, 27, 0, // Skip to: 7870
3619
/* 862 */     MCD_OPC_CheckField, 0, 16, 14, 89, 27, 0, // Skip to: 7870
3620
/* 869 */     MCD_OPC_Decode, 174, 6, 190, 1, // Opcode: AE_MULAAFD16SS_11_00
3621
/* 874 */     MCD_OPC_FilterValue, 128, 136, 1, 24, 0, 0, // Skip to: 905
3622
/* 881 */     MCD_OPC_CheckPredicate, 24, 72, 27, 0, // Skip to: 7870
3623
/* 886 */     MCD_OPC_CheckField, 28, 2, 0, 65, 27, 0, // Skip to: 7870
3624
/* 893 */     MCD_OPC_CheckField, 0, 16, 14, 58, 27, 0, // Skip to: 7870
3625
/* 900 */     MCD_OPC_Decode, 176, 6, 190, 1, // Opcode: AE_MULAAFD16SS_13_02
3626
/* 905 */     MCD_OPC_FilterValue, 128, 140, 1, 24, 0, 0, // Skip to: 936
3627
/* 912 */     MCD_OPC_CheckPredicate, 24, 41, 27, 0, // Skip to: 7870
3628
/* 917 */     MCD_OPC_CheckField, 28, 2, 0, 34, 27, 0, // Skip to: 7870
3629
/* 924 */     MCD_OPC_CheckField, 0, 16, 14, 27, 27, 0, // Skip to: 7870
3630
/* 931 */     MCD_OPC_Decode, 178, 6, 190, 1, // Opcode: AE_MULAAFD16SS_33_22
3631
/* 936 */     MCD_OPC_FilterValue, 128, 160, 1, 24, 0, 0, // Skip to: 967
3632
/* 943 */     MCD_OPC_CheckPredicate, 24, 10, 27, 0, // Skip to: 7870
3633
/* 948 */     MCD_OPC_CheckField, 28, 2, 0, 3, 27, 0, // Skip to: 7870
3634
/* 955 */     MCD_OPC_CheckField, 0, 16, 14, 252, 26, 0, // Skip to: 7870
3635
/* 962 */     MCD_OPC_Decode, 184, 6, 190, 1, // Opcode: AE_MULAAFD32X16_H0_L1
3636
/* 967 */     MCD_OPC_FilterValue, 128, 164, 1, 24, 0, 0, // Skip to: 998
3637
/* 974 */     MCD_OPC_CheckPredicate, 24, 235, 26, 0, // Skip to: 7870
3638
/* 979 */     MCD_OPC_CheckField, 28, 2, 0, 228, 26, 0, // Skip to: 7870
3639
/* 986 */     MCD_OPC_CheckField, 0, 16, 14, 221, 26, 0, // Skip to: 7870
3640
/* 993 */     MCD_OPC_Decode, 186, 6, 190, 1, // Opcode: AE_MULAAFD32X16_H1_L0
3641
/* 998 */     MCD_OPC_FilterValue, 128, 168, 1, 24, 0, 0, // Skip to: 1029
3642
/* 1005 */    MCD_OPC_CheckPredicate, 24, 204, 26, 0, // Skip to: 7870
3643
/* 1010 */    MCD_OPC_CheckField, 28, 2, 0, 197, 26, 0, // Skip to: 7870
3644
/* 1017 */    MCD_OPC_CheckField, 0, 16, 14, 190, 26, 0, // Skip to: 7870
3645
/* 1024 */    MCD_OPC_Decode, 188, 6, 190, 1, // Opcode: AE_MULAAFD32X16_H2_L3
3646
/* 1029 */    MCD_OPC_FilterValue, 128, 172, 1, 24, 0, 0, // Skip to: 1060
3647
/* 1036 */    MCD_OPC_CheckPredicate, 24, 173, 26, 0, // Skip to: 7870
3648
/* 1041 */    MCD_OPC_CheckField, 28, 2, 0, 166, 26, 0, // Skip to: 7870
3649
/* 1048 */    MCD_OPC_CheckField, 0, 16, 14, 159, 26, 0, // Skip to: 7870
3650
/* 1055 */    MCD_OPC_Decode, 190, 6, 190, 1, // Opcode: AE_MULAAFD32X16_H3_L2
3651
/* 1060 */    MCD_OPC_FilterValue, 128, 176, 1, 24, 0, 0, // Skip to: 1091
3652
/* 1067 */    MCD_OPC_CheckPredicate, 24, 142, 26, 0, // Skip to: 7870
3653
/* 1072 */    MCD_OPC_CheckField, 28, 2, 0, 135, 26, 0, // Skip to: 7870
3654
/* 1079 */    MCD_OPC_CheckField, 0, 16, 14, 128, 26, 0, // Skip to: 7870
3655
/* 1086 */    MCD_OPC_Decode, 195, 6, 190, 1, // Opcode: AE_MULAF16SS_00
3656
/* 1091 */    MCD_OPC_FilterValue, 128, 180, 1, 24, 0, 0, // Skip to: 1122
3657
/* 1098 */    MCD_OPC_CheckPredicate, 24, 111, 26, 0, // Skip to: 7870
3658
/* 1103 */    MCD_OPC_CheckField, 28, 2, 0, 104, 26, 0, // Skip to: 7870
3659
/* 1110 */    MCD_OPC_CheckField, 0, 16, 14, 97, 26, 0, // Skip to: 7870
3660
/* 1117 */    MCD_OPC_Decode, 207, 6, 190, 1, // Opcode: AE_MULAF32R_HH
3661
/* 1122 */    MCD_OPC_FilterValue, 128, 184, 1, 24, 0, 0, // Skip to: 1153
3662
/* 1129 */    MCD_OPC_CheckPredicate, 24, 80, 26, 0, // Skip to: 7870
3663
/* 1134 */    MCD_OPC_CheckField, 28, 2, 0, 73, 26, 0, // Skip to: 7870
3664
/* 1141 */    MCD_OPC_CheckField, 0, 16, 14, 66, 26, 0, // Skip to: 7870
3665
/* 1148 */    MCD_OPC_Decode, 208, 6, 190, 1, // Opcode: AE_MULAF32R_LH
3666
/* 1153 */    MCD_OPC_FilterValue, 128, 188, 1, 24, 0, 0, // Skip to: 1184
3667
/* 1160 */    MCD_OPC_CheckPredicate, 24, 49, 26, 0, // Skip to: 7870
3668
/* 1165 */    MCD_OPC_CheckField, 28, 2, 0, 42, 26, 0, // Skip to: 7870
3669
/* 1172 */    MCD_OPC_CheckField, 0, 16, 14, 35, 26, 0, // Skip to: 7870
3670
/* 1179 */    MCD_OPC_Decode, 209, 6, 190, 1, // Opcode: AE_MULAF32R_LL
3671
/* 1184 */    MCD_OPC_FilterValue, 128, 192, 1, 24, 0, 0, // Skip to: 1215
3672
/* 1191 */    MCD_OPC_CheckPredicate, 24, 18, 26, 0, // Skip to: 7870
3673
/* 1196 */    MCD_OPC_CheckField, 28, 2, 0, 11, 26, 0, // Skip to: 7870
3674
/* 1203 */    MCD_OPC_CheckField, 0, 16, 14, 4, 26, 0, // Skip to: 7870
3675
/* 1210 */    MCD_OPC_Decode, 211, 6, 190, 1, // Opcode: AE_MULAF32S_HH
3676
/* 1215 */    MCD_OPC_FilterValue, 128, 196, 1, 24, 0, 0, // Skip to: 1246
3677
/* 1222 */    MCD_OPC_CheckPredicate, 24, 243, 25, 0, // Skip to: 7870
3678
/* 1227 */    MCD_OPC_CheckField, 28, 2, 0, 236, 25, 0, // Skip to: 7870
3679
/* 1234 */    MCD_OPC_CheckField, 0, 16, 14, 229, 25, 0, // Skip to: 7870
3680
/* 1241 */    MCD_OPC_Decode, 212, 6, 190, 1, // Opcode: AE_MULAF32S_LH
3681
/* 1246 */    MCD_OPC_FilterValue, 128, 200, 1, 24, 0, 0, // Skip to: 1277
3682
/* 1253 */    MCD_OPC_CheckPredicate, 24, 212, 25, 0, // Skip to: 7870
3683
/* 1258 */    MCD_OPC_CheckField, 28, 2, 0, 205, 25, 0, // Skip to: 7870
3684
/* 1265 */    MCD_OPC_CheckField, 0, 16, 14, 198, 25, 0, // Skip to: 7870
3685
/* 1272 */    MCD_OPC_Decode, 213, 6, 190, 1, // Opcode: AE_MULAF32S_LL
3686
/* 1277 */    MCD_OPC_FilterValue, 128, 204, 1, 24, 0, 0, // Skip to: 1308
3687
/* 1284 */    MCD_OPC_CheckPredicate, 24, 181, 25, 0, // Skip to: 7870
3688
/* 1289 */    MCD_OPC_CheckField, 28, 2, 0, 174, 25, 0, // Skip to: 7870
3689
/* 1296 */    MCD_OPC_CheckField, 0, 16, 14, 167, 25, 0, // Skip to: 7870
3690
/* 1303 */    MCD_OPC_Decode, 215, 6, 190, 1, // Opcode: AE_MULAF32X16_H0
3691
/* 1308 */    MCD_OPC_FilterValue, 128, 208, 1, 24, 0, 0, // Skip to: 1339
3692
/* 1315 */    MCD_OPC_CheckPredicate, 24, 150, 25, 0, // Skip to: 7870
3693
/* 1320 */    MCD_OPC_CheckField, 28, 2, 0, 143, 25, 0, // Skip to: 7870
3694
/* 1327 */    MCD_OPC_CheckField, 0, 16, 14, 136, 25, 0, // Skip to: 7870
3695
/* 1334 */    MCD_OPC_Decode, 217, 6, 190, 1, // Opcode: AE_MULAF32X16_H1
3696
/* 1339 */    MCD_OPC_FilterValue, 128, 212, 1, 24, 0, 0, // Skip to: 1370
3697
/* 1346 */    MCD_OPC_CheckPredicate, 24, 119, 25, 0, // Skip to: 7870
3698
/* 1351 */    MCD_OPC_CheckField, 28, 2, 0, 112, 25, 0, // Skip to: 7870
3699
/* 1358 */    MCD_OPC_CheckField, 0, 16, 14, 105, 25, 0, // Skip to: 7870
3700
/* 1365 */    MCD_OPC_Decode, 219, 6, 190, 1, // Opcode: AE_MULAF32X16_H2
3701
/* 1370 */    MCD_OPC_FilterValue, 128, 216, 1, 24, 0, 0, // Skip to: 1401
3702
/* 1377 */    MCD_OPC_CheckPredicate, 24, 88, 25, 0, // Skip to: 7870
3703
/* 1382 */    MCD_OPC_CheckField, 28, 2, 0, 81, 25, 0, // Skip to: 7870
3704
/* 1389 */    MCD_OPC_CheckField, 0, 16, 14, 74, 25, 0, // Skip to: 7870
3705
/* 1396 */    MCD_OPC_Decode, 221, 6, 190, 1, // Opcode: AE_MULAF32X16_H3
3706
/* 1401 */    MCD_OPC_FilterValue, 128, 220, 1, 24, 0, 0, // Skip to: 1432
3707
/* 1408 */    MCD_OPC_CheckPredicate, 24, 57, 25, 0, // Skip to: 7870
3708
/* 1413 */    MCD_OPC_CheckField, 28, 2, 0, 50, 25, 0, // Skip to: 7870
3709
/* 1420 */    MCD_OPC_CheckField, 0, 16, 14, 43, 25, 0, // Skip to: 7870
3710
/* 1427 */    MCD_OPC_Decode, 223, 6, 190, 1, // Opcode: AE_MULAF32X16_L0
3711
/* 1432 */    MCD_OPC_FilterValue, 128, 224, 1, 24, 0, 0, // Skip to: 1463
3712
/* 1439 */    MCD_OPC_CheckPredicate, 24, 26, 25, 0, // Skip to: 7870
3713
/* 1444 */    MCD_OPC_CheckField, 28, 2, 0, 19, 25, 0, // Skip to: 7870
3714
/* 1451 */    MCD_OPC_CheckField, 0, 16, 14, 12, 25, 0, // Skip to: 7870
3715
/* 1458 */    MCD_OPC_Decode, 225, 6, 190, 1, // Opcode: AE_MULAF32X16_L1
3716
/* 1463 */    MCD_OPC_FilterValue, 128, 228, 1, 24, 0, 0, // Skip to: 1494
3717
/* 1470 */    MCD_OPC_CheckPredicate, 24, 251, 24, 0, // Skip to: 7870
3718
/* 1475 */    MCD_OPC_CheckField, 28, 2, 0, 244, 24, 0, // Skip to: 7870
3719
/* 1482 */    MCD_OPC_CheckField, 0, 16, 14, 237, 24, 0, // Skip to: 7870
3720
/* 1489 */    MCD_OPC_Decode, 227, 6, 190, 1, // Opcode: AE_MULAF32X16_L2
3721
/* 1494 */    MCD_OPC_FilterValue, 128, 232, 1, 24, 0, 0, // Skip to: 1525
3722
/* 1501 */    MCD_OPC_CheckPredicate, 24, 220, 24, 0, // Skip to: 7870
3723
/* 1506 */    MCD_OPC_CheckField, 28, 2, 0, 213, 24, 0, // Skip to: 7870
3724
/* 1513 */    MCD_OPC_CheckField, 0, 16, 14, 206, 24, 0, // Skip to: 7870
3725
/* 1520 */    MCD_OPC_Decode, 229, 6, 190, 1, // Opcode: AE_MULAF32X16_L3
3726
/* 1525 */    MCD_OPC_FilterValue, 128, 236, 1, 24, 0, 0, // Skip to: 1556
3727
/* 1532 */    MCD_OPC_CheckPredicate, 24, 189, 24, 0, // Skip to: 7870
3728
/* 1537 */    MCD_OPC_CheckField, 28, 2, 0, 182, 24, 0, // Skip to: 7870
3729
/* 1544 */    MCD_OPC_CheckField, 0, 16, 14, 175, 24, 0, // Skip to: 7870
3730
/* 1551 */    MCD_OPC_Decode, 231, 6, 190, 1, // Opcode: AE_MULAF48Q32SP16S_L
3731
/* 1556 */    MCD_OPC_FilterValue, 128, 240, 1, 24, 0, 0, // Skip to: 1587
3732
/* 1563 */    MCD_OPC_CheckPredicate, 24, 158, 24, 0, // Skip to: 7870
3733
/* 1568 */    MCD_OPC_CheckField, 28, 2, 0, 151, 24, 0, // Skip to: 7870
3734
/* 1575 */    MCD_OPC_CheckField, 0, 16, 14, 144, 24, 0, // Skip to: 7870
3735
/* 1582 */    MCD_OPC_Decode, 233, 6, 190, 1, // Opcode: AE_MULAF48Q32SP16U_L
3736
/* 1587 */    MCD_OPC_FilterValue, 128, 244, 1, 24, 0, 0, // Skip to: 1618
3737
/* 1594 */    MCD_OPC_CheckPredicate, 24, 127, 24, 0, // Skip to: 7870
3738
/* 1599 */    MCD_OPC_CheckField, 28, 2, 0, 120, 24, 0, // Skip to: 7870
3739
/* 1606 */    MCD_OPC_CheckField, 0, 16, 14, 113, 24, 0, // Skip to: 7870
3740
/* 1613 */    MCD_OPC_Decode, 244, 6, 190, 1, // Opcode: AE_MULAFP24X2R
3741
/* 1618 */    MCD_OPC_FilterValue, 128, 248, 1, 24, 0, 0, // Skip to: 1649
3742
/* 1625 */    MCD_OPC_CheckPredicate, 24, 96, 24, 0, // Skip to: 7870
3743
/* 1630 */    MCD_OPC_CheckField, 28, 2, 0, 89, 24, 0, // Skip to: 7870
3744
/* 1637 */    MCD_OPC_CheckField, 0, 16, 14, 82, 24, 0, // Skip to: 7870
3745
/* 1644 */    MCD_OPC_Decode, 245, 6, 190, 1, // Opcode: AE_MULAFP24X2RA
3746
/* 1649 */    MCD_OPC_FilterValue, 128, 252, 1, 24, 0, 0, // Skip to: 1680
3747
/* 1656 */    MCD_OPC_CheckPredicate, 24, 65, 24, 0, // Skip to: 7870
3748
/* 1661 */    MCD_OPC_CheckField, 28, 2, 0, 58, 24, 0, // Skip to: 7870
3749
/* 1668 */    MCD_OPC_CheckField, 0, 16, 14, 51, 24, 0, // Skip to: 7870
3750
/* 1675 */    MCD_OPC_Decode, 248, 6, 190, 1, // Opcode: AE_MULAFP32X16X2RAS_H
3751
/* 1680 */    MCD_OPC_FilterValue, 128, 128, 2, 24, 0, 0, // Skip to: 1711
3752
/* 1687 */    MCD_OPC_CheckPredicate, 24, 34, 24, 0, // Skip to: 7870
3753
/* 1692 */    MCD_OPC_CheckField, 28, 2, 0, 27, 24, 0, // Skip to: 7870
3754
/* 1699 */    MCD_OPC_CheckField, 0, 16, 14, 20, 24, 0, // Skip to: 7870
3755
/* 1706 */    MCD_OPC_Decode, 250, 6, 190, 1, // Opcode: AE_MULAFP32X16X2RAS_L
3756
/* 1711 */    MCD_OPC_FilterValue, 128, 132, 2, 24, 0, 0, // Skip to: 1742
3757
/* 1718 */    MCD_OPC_CheckPredicate, 24, 3, 24, 0, // Skip to: 7870
3758
/* 1723 */    MCD_OPC_CheckField, 28, 2, 0, 252, 23, 0, // Skip to: 7870
3759
/* 1730 */    MCD_OPC_CheckField, 0, 16, 14, 245, 23, 0, // Skip to: 7870
3760
/* 1737 */    MCD_OPC_Decode, 252, 6, 190, 1, // Opcode: AE_MULAFP32X16X2RS_H
3761
/* 1742 */    MCD_OPC_FilterValue, 128, 136, 2, 24, 0, 0, // Skip to: 1773
3762
/* 1749 */    MCD_OPC_CheckPredicate, 24, 228, 23, 0, // Skip to: 7870
3763
/* 1754 */    MCD_OPC_CheckField, 28, 2, 0, 221, 23, 0, // Skip to: 7870
3764
/* 1761 */    MCD_OPC_CheckField, 0, 16, 14, 214, 23, 0, // Skip to: 7870
3765
/* 1768 */    MCD_OPC_Decode, 254, 6, 190, 1, // Opcode: AE_MULAFP32X16X2RS_L
3766
/* 1773 */    MCD_OPC_FilterValue, 128, 148, 2, 24, 0, 0, // Skip to: 1804
3767
/* 1780 */    MCD_OPC_CheckPredicate, 24, 197, 23, 0, // Skip to: 7870
3768
/* 1785 */    MCD_OPC_CheckField, 28, 2, 0, 190, 23, 0, // Skip to: 7870
3769
/* 1792 */    MCD_OPC_CheckField, 0, 16, 14, 183, 23, 0, // Skip to: 7870
3770
/* 1799 */    MCD_OPC_Decode, 128, 7, 190, 1, // Opcode: AE_MULAFP32X2RAS
3771
/* 1804 */    MCD_OPC_FilterValue, 128, 152, 2, 24, 0, 0, // Skip to: 1835
3772
/* 1811 */    MCD_OPC_CheckPredicate, 24, 166, 23, 0, // Skip to: 7870
3773
/* 1816 */    MCD_OPC_CheckField, 28, 2, 0, 159, 23, 0, // Skip to: 7870
3774
/* 1823 */    MCD_OPC_CheckField, 0, 16, 14, 152, 23, 0, // Skip to: 7870
3775
/* 1830 */    MCD_OPC_Decode, 129, 7, 190, 1, // Opcode: AE_MULAFP32X2RS
3776
/* 1835 */    MCD_OPC_FilterValue, 128, 156, 2, 24, 0, 0, // Skip to: 1866
3777
/* 1842 */    MCD_OPC_CheckPredicate, 24, 135, 23, 0, // Skip to: 7870
3778
/* 1847 */    MCD_OPC_CheckField, 28, 2, 0, 128, 23, 0, // Skip to: 7870
3779
/* 1854 */    MCD_OPC_CheckField, 0, 16, 14, 121, 23, 0, // Skip to: 7870
3780
/* 1861 */    MCD_OPC_Decode, 134, 7, 190, 1, // Opcode: AE_MULAP32X16X2_H
3781
/* 1866 */    MCD_OPC_FilterValue, 128, 160, 2, 24, 0, 0, // Skip to: 1897
3782
/* 1873 */    MCD_OPC_CheckPredicate, 24, 104, 23, 0, // Skip to: 7870
3783
/* 1878 */    MCD_OPC_CheckField, 28, 2, 0, 97, 23, 0, // Skip to: 7870
3784
/* 1885 */    MCD_OPC_CheckField, 0, 16, 14, 90, 23, 0, // Skip to: 7870
3785
/* 1892 */    MCD_OPC_Decode, 135, 7, 190, 1, // Opcode: AE_MULAP32X16X2_L
3786
/* 1897 */    MCD_OPC_FilterValue, 128, 164, 2, 24, 0, 0, // Skip to: 1928
3787
/* 1904 */    MCD_OPC_CheckPredicate, 24, 73, 23, 0, // Skip to: 7870
3788
/* 1909 */    MCD_OPC_CheckField, 28, 2, 0, 66, 23, 0, // Skip to: 7870
3789
/* 1916 */    MCD_OPC_CheckField, 0, 16, 14, 59, 23, 0, // Skip to: 7870
3790
/* 1923 */    MCD_OPC_Decode, 136, 7, 190, 1, // Opcode: AE_MULAP32X2
3791
/* 1928 */    MCD_OPC_FilterValue, 128, 176, 2, 24, 0, 0, // Skip to: 1959
3792
/* 1935 */    MCD_OPC_CheckPredicate, 24, 42, 23, 0, // Skip to: 7870
3793
/* 1940 */    MCD_OPC_CheckField, 28, 2, 0, 35, 23, 0, // Skip to: 7870
3794
/* 1947 */    MCD_OPC_CheckField, 0, 16, 14, 28, 23, 0, // Skip to: 7870
3795
/* 1954 */    MCD_OPC_Decode, 141, 7, 190, 1, // Opcode: AE_MULAS32F48P16S_HH
3796
/* 1959 */    MCD_OPC_FilterValue, 128, 180, 2, 24, 0, 0, // Skip to: 1990
3797
/* 1966 */    MCD_OPC_CheckPredicate, 24, 11, 23, 0, // Skip to: 7870
3798
/* 1971 */    MCD_OPC_CheckField, 28, 2, 0, 4, 23, 0, // Skip to: 7870
3799
/* 1978 */    MCD_OPC_CheckField, 0, 16, 14, 253, 22, 0, // Skip to: 7870
3800
/* 1985 */    MCD_OPC_Decode, 143, 7, 190, 1, // Opcode: AE_MULAS32F48P16S_LH
3801
/* 1990 */    MCD_OPC_FilterValue, 128, 184, 2, 24, 0, 0, // Skip to: 2021
3802
/* 1997 */    MCD_OPC_CheckPredicate, 24, 236, 22, 0, // Skip to: 7870
3803
/* 2002 */    MCD_OPC_CheckField, 28, 2, 0, 229, 22, 0, // Skip to: 7870
3804
/* 2009 */    MCD_OPC_CheckField, 0, 16, 14, 222, 22, 0, // Skip to: 7870
3805
/* 2016 */    MCD_OPC_Decode, 145, 7, 190, 1, // Opcode: AE_MULAS32F48P16S_LL
3806
/* 2021 */    MCD_OPC_FilterValue, 128, 188, 2, 24, 0, 0, // Skip to: 2052
3807
/* 2028 */    MCD_OPC_CheckPredicate, 24, 205, 22, 0, // Skip to: 7870
3808
/* 2033 */    MCD_OPC_CheckField, 28, 2, 0, 198, 22, 0, // Skip to: 7870
3809
/* 2040 */    MCD_OPC_CheckField, 0, 16, 14, 191, 22, 0, // Skip to: 7870
3810
/* 2047 */    MCD_OPC_Decode, 151, 7, 190, 1, // Opcode: AE_MULASD32X16_H1_L0
3811
/* 2052 */    MCD_OPC_FilterValue, 128, 192, 2, 24, 0, 0, // Skip to: 2083
3812
/* 2059 */    MCD_OPC_CheckPredicate, 24, 174, 22, 0, // Skip to: 7870
3813
/* 2064 */    MCD_OPC_CheckField, 28, 2, 0, 167, 22, 0, // Skip to: 7870
3814
/* 2071 */    MCD_OPC_CheckField, 0, 16, 14, 160, 22, 0, // Skip to: 7870
3815
/* 2078 */    MCD_OPC_Decode, 153, 7, 190, 1, // Opcode: AE_MULASD32X16_H3_L2
3816
/* 2083 */    MCD_OPC_FilterValue, 128, 220, 2, 24, 0, 0, // Skip to: 2114
3817
/* 2090 */    MCD_OPC_CheckPredicate, 24, 143, 22, 0, // Skip to: 7870
3818
/* 2095 */    MCD_OPC_CheckField, 28, 2, 0, 136, 22, 0, // Skip to: 7870
3819
/* 2102 */    MCD_OPC_CheckField, 0, 16, 14, 129, 22, 0, // Skip to: 7870
3820
/* 2109 */    MCD_OPC_Decode, 159, 7, 190, 1, // Opcode: AE_MULASFD32X16_H1_L0
3821
/* 2114 */    MCD_OPC_FilterValue, 128, 224, 2, 24, 0, 0, // Skip to: 2145
3822
/* 2121 */    MCD_OPC_CheckPredicate, 24, 112, 22, 0, // Skip to: 7870
3823
/* 2126 */    MCD_OPC_CheckField, 28, 2, 0, 105, 22, 0, // Skip to: 7870
3824
/* 2133 */    MCD_OPC_CheckField, 0, 16, 14, 98, 22, 0, // Skip to: 7870
3825
/* 2140 */    MCD_OPC_Decode, 161, 7, 190, 1, // Opcode: AE_MULASFD32X16_H3_L2
3826
/* 2145 */    MCD_OPC_FilterValue, 128, 228, 2, 24, 0, 0, // Skip to: 2176
3827
/* 2152 */    MCD_OPC_CheckPredicate, 24, 81, 22, 0, // Skip to: 7870
3828
/* 2157 */    MCD_OPC_CheckField, 28, 2, 0, 74, 22, 0, // Skip to: 7870
3829
/* 2164 */    MCD_OPC_CheckField, 0, 16, 14, 67, 22, 0, // Skip to: 7870
3830
/* 2171 */    MCD_OPC_Decode, 166, 7, 189, 1, // Opcode: AE_MULF16SS_00
3831
/* 2176 */    MCD_OPC_FilterValue, 128, 232, 2, 24, 0, 0, // Skip to: 2207
3832
/* 2183 */    MCD_OPC_CheckPredicate, 24, 50, 22, 0, // Skip to: 7870
3833
/* 2188 */    MCD_OPC_CheckField, 28, 2, 0, 43, 22, 0, // Skip to: 7870
3834
/* 2195 */    MCD_OPC_CheckField, 0, 16, 14, 36, 22, 0, // Skip to: 7870
3835
/* 2202 */    MCD_OPC_Decode, 178, 7, 189, 1, // Opcode: AE_MULF32R_HH
3836
/* 2207 */    MCD_OPC_FilterValue, 128, 236, 2, 24, 0, 0, // Skip to: 2238
3837
/* 2214 */    MCD_OPC_CheckPredicate, 24, 19, 22, 0, // Skip to: 7870
3838
/* 2219 */    MCD_OPC_CheckField, 28, 2, 0, 12, 22, 0, // Skip to: 7870
3839
/* 2226 */    MCD_OPC_CheckField, 0, 16, 14, 5, 22, 0, // Skip to: 7870
3840
/* 2233 */    MCD_OPC_Decode, 179, 7, 189, 1, // Opcode: AE_MULF32R_LH
3841
/* 2238 */    MCD_OPC_FilterValue, 128, 240, 2, 24, 0, 0, // Skip to: 2269
3842
/* 2245 */    MCD_OPC_CheckPredicate, 24, 244, 21, 0, // Skip to: 7870
3843
/* 2250 */    MCD_OPC_CheckField, 28, 2, 0, 237, 21, 0, // Skip to: 7870
3844
/* 2257 */    MCD_OPC_CheckField, 0, 16, 14, 230, 21, 0, // Skip to: 7870
3845
/* 2264 */    MCD_OPC_Decode, 180, 7, 189, 1, // Opcode: AE_MULF32R_LL
3846
/* 2269 */    MCD_OPC_FilterValue, 128, 244, 2, 24, 0, 0, // Skip to: 2300
3847
/* 2276 */    MCD_OPC_CheckPredicate, 24, 213, 21, 0, // Skip to: 7870
3848
/* 2281 */    MCD_OPC_CheckField, 28, 2, 0, 206, 21, 0, // Skip to: 7870
3849
/* 2288 */    MCD_OPC_CheckField, 0, 16, 14, 199, 21, 0, // Skip to: 7870
3850
/* 2295 */    MCD_OPC_Decode, 182, 7, 189, 1, // Opcode: AE_MULF32S_HH
3851
/* 2300 */    MCD_OPC_FilterValue, 128, 248, 2, 24, 0, 0, // Skip to: 2331
3852
/* 2307 */    MCD_OPC_CheckPredicate, 24, 182, 21, 0, // Skip to: 7870
3853
/* 2312 */    MCD_OPC_CheckField, 28, 2, 0, 175, 21, 0, // Skip to: 7870
3854
/* 2319 */    MCD_OPC_CheckField, 0, 16, 14, 168, 21, 0, // Skip to: 7870
3855
/* 2326 */    MCD_OPC_Decode, 183, 7, 189, 1, // Opcode: AE_MULF32S_LH
3856
/* 2331 */    MCD_OPC_FilterValue, 128, 252, 2, 24, 0, 0, // Skip to: 2362
3857
/* 2338 */    MCD_OPC_CheckPredicate, 24, 151, 21, 0, // Skip to: 7870
3858
/* 2343 */    MCD_OPC_CheckField, 28, 2, 0, 144, 21, 0, // Skip to: 7870
3859
/* 2350 */    MCD_OPC_CheckField, 0, 16, 14, 137, 21, 0, // Skip to: 7870
3860
/* 2357 */    MCD_OPC_Decode, 184, 7, 189, 1, // Opcode: AE_MULF32S_LL
3861
/* 2362 */    MCD_OPC_FilterValue, 128, 128, 3, 24, 0, 0, // Skip to: 2393
3862
/* 2369 */    MCD_OPC_CheckPredicate, 24, 120, 21, 0, // Skip to: 7870
3863
/* 2374 */    MCD_OPC_CheckField, 28, 2, 0, 113, 21, 0, // Skip to: 7870
3864
/* 2381 */    MCD_OPC_CheckField, 0, 16, 14, 106, 21, 0, // Skip to: 7870
3865
/* 2388 */    MCD_OPC_Decode, 186, 7, 189, 1, // Opcode: AE_MULF32X16_H0
3866
/* 2393 */    MCD_OPC_FilterValue, 128, 132, 3, 24, 0, 0, // Skip to: 2424
3867
/* 2400 */    MCD_OPC_CheckPredicate, 24, 89, 21, 0, // Skip to: 7870
3868
/* 2405 */    MCD_OPC_CheckField, 28, 2, 0, 82, 21, 0, // Skip to: 7870
3869
/* 2412 */    MCD_OPC_CheckField, 0, 16, 14, 75, 21, 0, // Skip to: 7870
3870
/* 2419 */    MCD_OPC_Decode, 188, 7, 189, 1, // Opcode: AE_MULF32X16_H1
3871
/* 2424 */    MCD_OPC_FilterValue, 128, 136, 3, 24, 0, 0, // Skip to: 2455
3872
/* 2431 */    MCD_OPC_CheckPredicate, 24, 58, 21, 0, // Skip to: 7870
3873
/* 2436 */    MCD_OPC_CheckField, 28, 2, 0, 51, 21, 0, // Skip to: 7870
3874
/* 2443 */    MCD_OPC_CheckField, 0, 16, 14, 44, 21, 0, // Skip to: 7870
3875
/* 2450 */    MCD_OPC_Decode, 190, 7, 189, 1, // Opcode: AE_MULF32X16_H2
3876
/* 2455 */    MCD_OPC_FilterValue, 128, 140, 3, 24, 0, 0, // Skip to: 2486
3877
/* 2462 */    MCD_OPC_CheckPredicate, 24, 27, 21, 0, // Skip to: 7870
3878
/* 2467 */    MCD_OPC_CheckField, 28, 2, 0, 20, 21, 0, // Skip to: 7870
3879
/* 2474 */    MCD_OPC_CheckField, 0, 16, 14, 13, 21, 0, // Skip to: 7870
3880
/* 2481 */    MCD_OPC_Decode, 192, 7, 189, 1, // Opcode: AE_MULF32X16_H3
3881
/* 2486 */    MCD_OPC_FilterValue, 128, 144, 3, 24, 0, 0, // Skip to: 2517
3882
/* 2493 */    MCD_OPC_CheckPredicate, 24, 252, 20, 0, // Skip to: 7870
3883
/* 2498 */    MCD_OPC_CheckField, 28, 2, 0, 245, 20, 0, // Skip to: 7870
3884
/* 2505 */    MCD_OPC_CheckField, 0, 16, 14, 238, 20, 0, // Skip to: 7870
3885
/* 2512 */    MCD_OPC_Decode, 194, 7, 189, 1, // Opcode: AE_MULF32X16_L0
3886
/* 2517 */    MCD_OPC_FilterValue, 128, 148, 3, 24, 0, 0, // Skip to: 2548
3887
/* 2524 */    MCD_OPC_CheckPredicate, 24, 221, 20, 0, // Skip to: 7870
3888
/* 2529 */    MCD_OPC_CheckField, 28, 2, 0, 214, 20, 0, // Skip to: 7870
3889
/* 2536 */    MCD_OPC_CheckField, 0, 16, 14, 207, 20, 0, // Skip to: 7870
3890
/* 2543 */    MCD_OPC_Decode, 196, 7, 189, 1, // Opcode: AE_MULF32X16_L1
3891
/* 2548 */    MCD_OPC_FilterValue, 128, 152, 3, 24, 0, 0, // Skip to: 2579
3892
/* 2555 */    MCD_OPC_CheckPredicate, 24, 190, 20, 0, // Skip to: 7870
3893
/* 2560 */    MCD_OPC_CheckField, 28, 2, 0, 183, 20, 0, // Skip to: 7870
3894
/* 2567 */    MCD_OPC_CheckField, 0, 16, 14, 176, 20, 0, // Skip to: 7870
3895
/* 2574 */    MCD_OPC_Decode, 198, 7, 189, 1, // Opcode: AE_MULF32X16_L2
3896
/* 2579 */    MCD_OPC_FilterValue, 128, 156, 3, 24, 0, 0, // Skip to: 2610
3897
/* 2586 */    MCD_OPC_CheckPredicate, 24, 159, 20, 0, // Skip to: 7870
3898
/* 2591 */    MCD_OPC_CheckField, 28, 2, 0, 152, 20, 0, // Skip to: 7870
3899
/* 2598 */    MCD_OPC_CheckField, 0, 16, 14, 145, 20, 0, // Skip to: 7870
3900
/* 2605 */    MCD_OPC_Decode, 200, 7, 189, 1, // Opcode: AE_MULF32X16_L3
3901
/* 2610 */    MCD_OPC_FilterValue, 128, 160, 3, 24, 0, 0, // Skip to: 2641
3902
/* 2617 */    MCD_OPC_CheckPredicate, 24, 128, 20, 0, // Skip to: 7870
3903
/* 2622 */    MCD_OPC_CheckField, 28, 2, 0, 121, 20, 0, // Skip to: 7870
3904
/* 2629 */    MCD_OPC_CheckField, 0, 16, 14, 114, 20, 0, // Skip to: 7870
3905
/* 2636 */    MCD_OPC_Decode, 202, 7, 189, 1, // Opcode: AE_MULF48Q32SP16S_L
3906
/* 2641 */    MCD_OPC_FilterValue, 128, 164, 3, 24, 0, 0, // Skip to: 2672
3907
/* 2648 */    MCD_OPC_CheckPredicate, 24, 97, 20, 0, // Skip to: 7870
3908
/* 2653 */    MCD_OPC_CheckField, 28, 2, 0, 90, 20, 0, // Skip to: 7870
3909
/* 2660 */    MCD_OPC_CheckField, 0, 16, 14, 83, 20, 0, // Skip to: 7870
3910
/* 2667 */    MCD_OPC_Decode, 204, 7, 189, 1, // Opcode: AE_MULF48Q32SP16U_L
3911
/* 2672 */    MCD_OPC_FilterValue, 128, 168, 3, 24, 0, 0, // Skip to: 2703
3912
/* 2679 */    MCD_OPC_CheckPredicate, 24, 66, 20, 0, // Skip to: 7870
3913
/* 2684 */    MCD_OPC_CheckField, 28, 2, 0, 59, 20, 0, // Skip to: 7870
3914
/* 2691 */    MCD_OPC_CheckField, 0, 16, 14, 52, 20, 0, // Skip to: 7870
3915
/* 2698 */    MCD_OPC_Decode, 217, 7, 189, 1, // Opcode: AE_MULFP24X2R
3916
/* 2703 */    MCD_OPC_FilterValue, 128, 172, 3, 24, 0, 0, // Skip to: 2734
3917
/* 2710 */    MCD_OPC_CheckPredicate, 24, 35, 20, 0, // Skip to: 7870
3918
/* 2715 */    MCD_OPC_CheckField, 28, 2, 0, 28, 20, 0, // Skip to: 7870
3919
/* 2722 */    MCD_OPC_CheckField, 0, 16, 14, 21, 20, 0, // Skip to: 7870
3920
/* 2729 */    MCD_OPC_Decode, 218, 7, 189, 1, // Opcode: AE_MULFP24X2RA
3921
/* 2734 */    MCD_OPC_FilterValue, 128, 176, 3, 24, 0, 0, // Skip to: 2765
3922
/* 2741 */    MCD_OPC_CheckPredicate, 24, 4, 20, 0, // Skip to: 7870
3923
/* 2746 */    MCD_OPC_CheckField, 28, 2, 0, 253, 19, 0, // Skip to: 7870
3924
/* 2753 */    MCD_OPC_CheckField, 0, 16, 14, 246, 19, 0, // Skip to: 7870
3925
/* 2760 */    MCD_OPC_Decode, 221, 7, 189, 1, // Opcode: AE_MULFP32X16X2RAS_H
3926
/* 2765 */    MCD_OPC_FilterValue, 128, 180, 3, 24, 0, 0, // Skip to: 2796
3927
/* 2772 */    MCD_OPC_CheckPredicate, 24, 229, 19, 0, // Skip to: 7870
3928
/* 2777 */    MCD_OPC_CheckField, 28, 2, 0, 222, 19, 0, // Skip to: 7870
3929
/* 2784 */    MCD_OPC_CheckField, 0, 16, 14, 215, 19, 0, // Skip to: 7870
3930
/* 2791 */    MCD_OPC_Decode, 223, 7, 189, 1, // Opcode: AE_MULFP32X16X2RAS_L
3931
/* 2796 */    MCD_OPC_FilterValue, 128, 184, 3, 24, 0, 0, // Skip to: 2827
3932
/* 2803 */    MCD_OPC_CheckPredicate, 24, 198, 19, 0, // Skip to: 7870
3933
/* 2808 */    MCD_OPC_CheckField, 28, 2, 0, 191, 19, 0, // Skip to: 7870
3934
/* 2815 */    MCD_OPC_CheckField, 0, 16, 14, 184, 19, 0, // Skip to: 7870
3935
/* 2822 */    MCD_OPC_Decode, 225, 7, 189, 1, // Opcode: AE_MULFP32X16X2RS_H
3936
/* 2827 */    MCD_OPC_FilterValue, 128, 188, 3, 24, 0, 0, // Skip to: 2858
3937
/* 2834 */    MCD_OPC_CheckPredicate, 24, 167, 19, 0, // Skip to: 7870
3938
/* 2839 */    MCD_OPC_CheckField, 28, 2, 0, 160, 19, 0, // Skip to: 7870
3939
/* 2846 */    MCD_OPC_CheckField, 0, 16, 14, 153, 19, 0, // Skip to: 7870
3940
/* 2853 */    MCD_OPC_Decode, 227, 7, 189, 1, // Opcode: AE_MULFP32X16X2RS_L
3941
/* 2858 */    MCD_OPC_FilterValue, 128, 200, 3, 24, 0, 0, // Skip to: 2889
3942
/* 2865 */    MCD_OPC_CheckPredicate, 24, 136, 19, 0, // Skip to: 7870
3943
/* 2870 */    MCD_OPC_CheckField, 28, 2, 0, 129, 19, 0, // Skip to: 7870
3944
/* 2877 */    MCD_OPC_CheckField, 0, 16, 14, 122, 19, 0, // Skip to: 7870
3945
/* 2884 */    MCD_OPC_Decode, 229, 7, 189, 1, // Opcode: AE_MULFP32X2RAS
3946
/* 2889 */    MCD_OPC_FilterValue, 128, 204, 3, 24, 0, 0, // Skip to: 2920
3947
/* 2896 */    MCD_OPC_CheckPredicate, 24, 105, 19, 0, // Skip to: 7870
3948
/* 2901 */    MCD_OPC_CheckField, 28, 2, 0, 98, 19, 0, // Skip to: 7870
3949
/* 2908 */    MCD_OPC_CheckField, 0, 16, 14, 91, 19, 0, // Skip to: 7870
3950
/* 2915 */    MCD_OPC_Decode, 230, 7, 189, 1, // Opcode: AE_MULFP32X2RS
3951
/* 2920 */    MCD_OPC_FilterValue, 128, 208, 3, 24, 0, 0, // Skip to: 2951
3952
/* 2927 */    MCD_OPC_CheckPredicate, 24, 74, 19, 0, // Skip to: 7870
3953
/* 2932 */    MCD_OPC_CheckField, 28, 2, 0, 67, 19, 0, // Skip to: 7870
3954
/* 2939 */    MCD_OPC_CheckField, 0, 16, 14, 60, 19, 0, // Skip to: 7870
3955
/* 2946 */    MCD_OPC_Decode, 235, 7, 189, 1, // Opcode: AE_MULP32X16X2_H
3956
/* 2951 */    MCD_OPC_FilterValue, 128, 212, 3, 24, 0, 0, // Skip to: 2982
3957
/* 2958 */    MCD_OPC_CheckPredicate, 24, 43, 19, 0, // Skip to: 7870
3958
/* 2963 */    MCD_OPC_CheckField, 28, 2, 0, 36, 19, 0, // Skip to: 7870
3959
/* 2970 */    MCD_OPC_CheckField, 0, 16, 14, 29, 19, 0, // Skip to: 7870
3960
/* 2977 */    MCD_OPC_Decode, 236, 7, 189, 1, // Opcode: AE_MULP32X16X2_L
3961
/* 2982 */    MCD_OPC_FilterValue, 128, 216, 3, 24, 0, 0, // Skip to: 3013
3962
/* 2989 */    MCD_OPC_CheckPredicate, 24, 12, 19, 0, // Skip to: 7870
3963
/* 2994 */    MCD_OPC_CheckField, 28, 2, 0, 5, 19, 0, // Skip to: 7870
3964
/* 3001 */    MCD_OPC_CheckField, 0, 16, 14, 254, 18, 0, // Skip to: 7870
3965
/* 3008 */    MCD_OPC_Decode, 237, 7, 189, 1, // Opcode: AE_MULP32X2
3966
/* 3013 */    MCD_OPC_FilterValue, 128, 228, 3, 24, 0, 0, // Skip to: 3044
3967
/* 3020 */    MCD_OPC_CheckPredicate, 24, 237, 18, 0, // Skip to: 7870
3968
/* 3025 */    MCD_OPC_CheckField, 28, 2, 0, 230, 18, 0, // Skip to: 7870
3969
/* 3032 */    MCD_OPC_CheckField, 0, 16, 14, 223, 18, 0, // Skip to: 7870
3970
/* 3039 */    MCD_OPC_Decode, 243, 7, 189, 1, // Opcode: AE_MULS32F48P16S_HH
3971
/* 3044 */    MCD_OPC_FilterValue, 128, 232, 3, 24, 0, 0, // Skip to: 3075
3972
/* 3051 */    MCD_OPC_CheckPredicate, 24, 206, 18, 0, // Skip to: 7870
3973
/* 3056 */    MCD_OPC_CheckField, 28, 2, 0, 199, 18, 0, // Skip to: 7870
3974
/* 3063 */    MCD_OPC_CheckField, 0, 16, 14, 192, 18, 0, // Skip to: 7870
3975
/* 3070 */    MCD_OPC_Decode, 245, 7, 189, 1, // Opcode: AE_MULS32F48P16S_LH
3976
/* 3075 */    MCD_OPC_FilterValue, 128, 236, 3, 24, 0, 0, // Skip to: 3106
3977
/* 3082 */    MCD_OPC_CheckPredicate, 24, 175, 18, 0, // Skip to: 7870
3978
/* 3087 */    MCD_OPC_CheckField, 28, 2, 0, 168, 18, 0, // Skip to: 7870
3979
/* 3094 */    MCD_OPC_CheckField, 0, 16, 14, 161, 18, 0, // Skip to: 7870
3980
/* 3101 */    MCD_OPC_Decode, 247, 7, 189, 1, // Opcode: AE_MULS32F48P16S_LL
3981
/* 3106 */    MCD_OPC_FilterValue, 128, 240, 3, 24, 0, 0, // Skip to: 3137
3982
/* 3113 */    MCD_OPC_CheckPredicate, 24, 144, 18, 0, // Skip to: 7870
3983
/* 3118 */    MCD_OPC_CheckField, 28, 2, 0, 137, 18, 0, // Skip to: 7870
3984
/* 3125 */    MCD_OPC_CheckField, 0, 16, 14, 130, 18, 0, // Skip to: 7870
3985
/* 3132 */    MCD_OPC_Decode, 249, 7, 190, 1, // Opcode: AE_MULS32U_LL
3986
/* 3137 */    MCD_OPC_FilterValue, 128, 244, 3, 24, 0, 0, // Skip to: 3168
3987
/* 3144 */    MCD_OPC_CheckPredicate, 24, 113, 18, 0, // Skip to: 7870
3988
/* 3149 */    MCD_OPC_CheckField, 28, 2, 0, 106, 18, 0, // Skip to: 7870
3989
/* 3156 */    MCD_OPC_CheckField, 0, 16, 14, 99, 18, 0, // Skip to: 7870
3990
/* 3163 */    MCD_OPC_Decode, 250, 7, 190, 1, // Opcode: AE_MULS32X16_H0
3991
/* 3168 */    MCD_OPC_FilterValue, 128, 248, 3, 24, 0, 0, // Skip to: 3199
3992
/* 3175 */    MCD_OPC_CheckPredicate, 24, 82, 18, 0, // Skip to: 7870
3993
/* 3180 */    MCD_OPC_CheckField, 28, 2, 0, 75, 18, 0, // Skip to: 7870
3994
/* 3187 */    MCD_OPC_CheckField, 0, 16, 14, 68, 18, 0, // Skip to: 7870
3995
/* 3194 */    MCD_OPC_Decode, 252, 7, 190, 1, // Opcode: AE_MULS32X16_H1
3996
/* 3199 */    MCD_OPC_FilterValue, 128, 252, 3, 24, 0, 0, // Skip to: 3230
3997
/* 3206 */    MCD_OPC_CheckPredicate, 24, 51, 18, 0, // Skip to: 7870
3998
/* 3211 */    MCD_OPC_CheckField, 28, 2, 0, 44, 18, 0, // Skip to: 7870
3999
/* 3218 */    MCD_OPC_CheckField, 0, 16, 14, 37, 18, 0, // Skip to: 7870
4000
/* 3225 */    MCD_OPC_Decode, 254, 7, 190, 1, // Opcode: AE_MULS32X16_H2
4001
/* 3230 */    MCD_OPC_FilterValue, 128, 128, 4, 24, 0, 0, // Skip to: 3261
4002
/* 3237 */    MCD_OPC_CheckPredicate, 24, 20, 18, 0, // Skip to: 7870
4003
/* 3242 */    MCD_OPC_CheckField, 28, 2, 0, 13, 18, 0, // Skip to: 7870
4004
/* 3249 */    MCD_OPC_CheckField, 0, 16, 14, 6, 18, 0, // Skip to: 7870
4005
/* 3256 */    MCD_OPC_Decode, 128, 8, 190, 1, // Opcode: AE_MULS32X16_H3
4006
/* 3261 */    MCD_OPC_FilterValue, 128, 132, 4, 24, 0, 0, // Skip to: 3292
4007
/* 3268 */    MCD_OPC_CheckPredicate, 24, 245, 17, 0, // Skip to: 7870
4008
/* 3273 */    MCD_OPC_CheckField, 28, 2, 0, 238, 17, 0, // Skip to: 7870
4009
/* 3280 */    MCD_OPC_CheckField, 0, 16, 14, 231, 17, 0, // Skip to: 7870
4010
/* 3287 */    MCD_OPC_Decode, 130, 8, 190, 1, // Opcode: AE_MULS32X16_L0
4011
/* 3292 */    MCD_OPC_FilterValue, 128, 136, 4, 24, 0, 0, // Skip to: 3323
4012
/* 3299 */    MCD_OPC_CheckPredicate, 24, 214, 17, 0, // Skip to: 7870
4013
/* 3304 */    MCD_OPC_CheckField, 28, 2, 0, 207, 17, 0, // Skip to: 7870
4014
/* 3311 */    MCD_OPC_CheckField, 0, 16, 14, 200, 17, 0, // Skip to: 7870
4015
/* 3318 */    MCD_OPC_Decode, 132, 8, 190, 1, // Opcode: AE_MULS32X16_L1
4016
/* 3323 */    MCD_OPC_FilterValue, 128, 140, 4, 24, 0, 0, // Skip to: 3354
4017
/* 3330 */    MCD_OPC_CheckPredicate, 24, 183, 17, 0, // Skip to: 7870
4018
/* 3335 */    MCD_OPC_CheckField, 28, 2, 0, 176, 17, 0, // Skip to: 7870
4019
/* 3342 */    MCD_OPC_CheckField, 0, 16, 14, 169, 17, 0, // Skip to: 7870
4020
/* 3349 */    MCD_OPC_Decode, 134, 8, 190, 1, // Opcode: AE_MULS32X16_L2
4021
/* 3354 */    MCD_OPC_FilterValue, 128, 144, 4, 24, 0, 0, // Skip to: 3385
4022
/* 3361 */    MCD_OPC_CheckPredicate, 24, 152, 17, 0, // Skip to: 7870
4023
/* 3366 */    MCD_OPC_CheckField, 28, 2, 0, 145, 17, 0, // Skip to: 7870
4024
/* 3373 */    MCD_OPC_CheckField, 0, 16, 14, 138, 17, 0, // Skip to: 7870
4025
/* 3380 */    MCD_OPC_Decode, 136, 8, 190, 1, // Opcode: AE_MULS32X16_L3
4026
/* 3385 */    MCD_OPC_FilterValue, 128, 148, 4, 24, 0, 0, // Skip to: 3416
4027
/* 3392 */    MCD_OPC_CheckPredicate, 24, 121, 17, 0, // Skip to: 7870
4028
/* 3397 */    MCD_OPC_CheckField, 28, 2, 0, 114, 17, 0, // Skip to: 7870
4029
/* 3404 */    MCD_OPC_CheckField, 0, 16, 14, 107, 17, 0, // Skip to: 7870
4030
/* 3411 */    MCD_OPC_Decode, 138, 8, 190, 1, // Opcode: AE_MULS32_HH
4031
/* 3416 */    MCD_OPC_FilterValue, 128, 152, 4, 24, 0, 0, // Skip to: 3447
4032
/* 3423 */    MCD_OPC_CheckPredicate, 24, 90, 17, 0, // Skip to: 7870
4033
/* 3428 */    MCD_OPC_CheckField, 28, 2, 0, 83, 17, 0, // Skip to: 7870
4034
/* 3435 */    MCD_OPC_CheckField, 0, 16, 14, 76, 17, 0, // Skip to: 7870
4035
/* 3442 */    MCD_OPC_Decode, 139, 8, 190, 1, // Opcode: AE_MULS32_LH
4036
/* 3447 */    MCD_OPC_FilterValue, 128, 156, 4, 24, 0, 0, // Skip to: 3478
4037
/* 3454 */    MCD_OPC_CheckPredicate, 24, 59, 17, 0, // Skip to: 7870
4038
/* 3459 */    MCD_OPC_CheckField, 28, 2, 0, 52, 17, 0, // Skip to: 7870
4039
/* 3466 */    MCD_OPC_CheckField, 0, 16, 14, 45, 17, 0, // Skip to: 7870
4040
/* 3473 */    MCD_OPC_Decode, 140, 8, 190, 1, // Opcode: AE_MULS32_LL
4041
/* 3478 */    MCD_OPC_FilterValue, 128, 172, 4, 24, 0, 0, // Skip to: 3509
4042
/* 3485 */    MCD_OPC_CheckPredicate, 24, 28, 17, 0, // Skip to: 7870
4043
/* 3490 */    MCD_OPC_CheckField, 28, 2, 0, 21, 17, 0, // Skip to: 7870
4044
/* 3497 */    MCD_OPC_CheckField, 0, 16, 14, 14, 17, 0, // Skip to: 7870
4045
/* 3504 */    MCD_OPC_Decode, 149, 8, 190, 1, // Opcode: AE_MULSAFD32X16_H1_L0
4046
/* 3509 */    MCD_OPC_FilterValue, 128, 176, 4, 24, 0, 0, // Skip to: 3540
4047
/* 3516 */    MCD_OPC_CheckPredicate, 24, 253, 16, 0, // Skip to: 7870
4048
/* 3521 */    MCD_OPC_CheckField, 28, 2, 0, 246, 16, 0, // Skip to: 7870
4049
/* 3528 */    MCD_OPC_CheckField, 0, 16, 14, 239, 16, 0, // Skip to: 7870
4050
/* 3535 */    MCD_OPC_Decode, 151, 8, 190, 1, // Opcode: AE_MULSAFD32X16_H3_L2
4051
/* 3540 */    MCD_OPC_FilterValue, 128, 180, 4, 24, 0, 0, // Skip to: 3571
4052
/* 3547 */    MCD_OPC_CheckPredicate, 24, 222, 16, 0, // Skip to: 7870
4053
/* 3552 */    MCD_OPC_CheckField, 28, 2, 0, 215, 16, 0, // Skip to: 7870
4054
/* 3559 */    MCD_OPC_CheckField, 0, 16, 14, 208, 16, 0, // Skip to: 7870
4055
/* 3566 */    MCD_OPC_Decode, 153, 8, 190, 1, // Opcode: AE_MULSF16SS_00
4056
/* 3571 */    MCD_OPC_FilterValue, 128, 184, 4, 24, 0, 0, // Skip to: 3602
4057
/* 3578 */    MCD_OPC_CheckPredicate, 24, 191, 16, 0, // Skip to: 7870
4058
/* 3583 */    MCD_OPC_CheckField, 28, 2, 0, 184, 16, 0, // Skip to: 7870
4059
/* 3590 */    MCD_OPC_CheckField, 0, 16, 14, 177, 16, 0, // Skip to: 7870
4060
/* 3597 */    MCD_OPC_Decode, 165, 8, 190, 1, // Opcode: AE_MULSF32R_HH
4061
/* 3602 */    MCD_OPC_FilterValue, 128, 188, 4, 24, 0, 0, // Skip to: 3633
4062
/* 3609 */    MCD_OPC_CheckPredicate, 24, 160, 16, 0, // Skip to: 7870
4063
/* 3614 */    MCD_OPC_CheckField, 28, 2, 0, 153, 16, 0, // Skip to: 7870
4064
/* 3621 */    MCD_OPC_CheckField, 0, 16, 14, 146, 16, 0, // Skip to: 7870
4065
/* 3628 */    MCD_OPC_Decode, 166, 8, 190, 1, // Opcode: AE_MULSF32R_LH
4066
/* 3633 */    MCD_OPC_FilterValue, 128, 192, 4, 24, 0, 0, // Skip to: 3664
4067
/* 3640 */    MCD_OPC_CheckPredicate, 24, 129, 16, 0, // Skip to: 7870
4068
/* 3645 */    MCD_OPC_CheckField, 28, 2, 0, 122, 16, 0, // Skip to: 7870
4069
/* 3652 */    MCD_OPC_CheckField, 0, 16, 14, 115, 16, 0, // Skip to: 7870
4070
/* 3659 */    MCD_OPC_Decode, 167, 8, 190, 1, // Opcode: AE_MULSF32R_LL
4071
/* 3664 */    MCD_OPC_FilterValue, 128, 196, 4, 24, 0, 0, // Skip to: 3695
4072
/* 3671 */    MCD_OPC_CheckPredicate, 24, 98, 16, 0, // Skip to: 7870
4073
/* 3676 */    MCD_OPC_CheckField, 28, 2, 0, 91, 16, 0, // Skip to: 7870
4074
/* 3683 */    MCD_OPC_CheckField, 0, 16, 14, 84, 16, 0, // Skip to: 7870
4075
/* 3690 */    MCD_OPC_Decode, 169, 8, 190, 1, // Opcode: AE_MULSF32S_HH
4076
/* 3695 */    MCD_OPC_FilterValue, 128, 200, 4, 24, 0, 0, // Skip to: 3726
4077
/* 3702 */    MCD_OPC_CheckPredicate, 24, 67, 16, 0, // Skip to: 7870
4078
/* 3707 */    MCD_OPC_CheckField, 28, 2, 0, 60, 16, 0, // Skip to: 7870
4079
/* 3714 */    MCD_OPC_CheckField, 0, 16, 14, 53, 16, 0, // Skip to: 7870
4080
/* 3721 */    MCD_OPC_Decode, 170, 8, 190, 1, // Opcode: AE_MULSF32S_LH
4081
/* 3726 */    MCD_OPC_FilterValue, 128, 204, 4, 24, 0, 0, // Skip to: 3757
4082
/* 3733 */    MCD_OPC_CheckPredicate, 24, 36, 16, 0, // Skip to: 7870
4083
/* 3738 */    MCD_OPC_CheckField, 28, 2, 0, 29, 16, 0, // Skip to: 7870
4084
/* 3745 */    MCD_OPC_CheckField, 0, 16, 14, 22, 16, 0, // Skip to: 7870
4085
/* 3752 */    MCD_OPC_Decode, 171, 8, 190, 1, // Opcode: AE_MULSF32S_LL
4086
/* 3757 */    MCD_OPC_FilterValue, 128, 208, 4, 24, 0, 0, // Skip to: 3788
4087
/* 3764 */    MCD_OPC_CheckPredicate, 24, 5, 16, 0, // Skip to: 7870
4088
/* 3769 */    MCD_OPC_CheckField, 28, 2, 0, 254, 15, 0, // Skip to: 7870
4089
/* 3776 */    MCD_OPC_CheckField, 0, 16, 14, 247, 15, 0, // Skip to: 7870
4090
/* 3783 */    MCD_OPC_Decode, 172, 8, 190, 1, // Opcode: AE_MULSF32X16_H0
4091
/* 3788 */    MCD_OPC_FilterValue, 128, 212, 4, 24, 0, 0, // Skip to: 3819
4092
/* 3795 */    MCD_OPC_CheckPredicate, 24, 230, 15, 0, // Skip to: 7870
4093
/* 3800 */    MCD_OPC_CheckField, 28, 2, 0, 223, 15, 0, // Skip to: 7870
4094
/* 3807 */    MCD_OPC_CheckField, 0, 16, 14, 216, 15, 0, // Skip to: 7870
4095
/* 3814 */    MCD_OPC_Decode, 174, 8, 190, 1, // Opcode: AE_MULSF32X16_H1
4096
/* 3819 */    MCD_OPC_FilterValue, 128, 216, 4, 24, 0, 0, // Skip to: 3850
4097
/* 3826 */    MCD_OPC_CheckPredicate, 24, 199, 15, 0, // Skip to: 7870
4098
/* 3831 */    MCD_OPC_CheckField, 28, 2, 0, 192, 15, 0, // Skip to: 7870
4099
/* 3838 */    MCD_OPC_CheckField, 0, 16, 14, 185, 15, 0, // Skip to: 7870
4100
/* 3845 */    MCD_OPC_Decode, 176, 8, 190, 1, // Opcode: AE_MULSF32X16_H2
4101
/* 3850 */    MCD_OPC_FilterValue, 128, 220, 4, 24, 0, 0, // Skip to: 3881
4102
/* 3857 */    MCD_OPC_CheckPredicate, 24, 168, 15, 0, // Skip to: 7870
4103
/* 3862 */    MCD_OPC_CheckField, 28, 2, 0, 161, 15, 0, // Skip to: 7870
4104
/* 3869 */    MCD_OPC_CheckField, 0, 16, 14, 154, 15, 0, // Skip to: 7870
4105
/* 3876 */    MCD_OPC_Decode, 178, 8, 190, 1, // Opcode: AE_MULSF32X16_H3
4106
/* 3881 */    MCD_OPC_FilterValue, 128, 224, 4, 24, 0, 0, // Skip to: 3912
4107
/* 3888 */    MCD_OPC_CheckPredicate, 24, 137, 15, 0, // Skip to: 7870
4108
/* 3893 */    MCD_OPC_CheckField, 28, 2, 0, 130, 15, 0, // Skip to: 7870
4109
/* 3900 */    MCD_OPC_CheckField, 0, 16, 14, 123, 15, 0, // Skip to: 7870
4110
/* 3907 */    MCD_OPC_Decode, 180, 8, 190, 1, // Opcode: AE_MULSF32X16_L0
4111
/* 3912 */    MCD_OPC_FilterValue, 128, 228, 4, 24, 0, 0, // Skip to: 3943
4112
/* 3919 */    MCD_OPC_CheckPredicate, 24, 106, 15, 0, // Skip to: 7870
4113
/* 3924 */    MCD_OPC_CheckField, 28, 2, 0, 99, 15, 0, // Skip to: 7870
4114
/* 3931 */    MCD_OPC_CheckField, 0, 16, 14, 92, 15, 0, // Skip to: 7870
4115
/* 3938 */    MCD_OPC_Decode, 182, 8, 190, 1, // Opcode: AE_MULSF32X16_L1
4116
/* 3943 */    MCD_OPC_FilterValue, 128, 232, 4, 24, 0, 0, // Skip to: 3974
4117
/* 3950 */    MCD_OPC_CheckPredicate, 24, 75, 15, 0, // Skip to: 7870
4118
/* 3955 */    MCD_OPC_CheckField, 28, 2, 0, 68, 15, 0, // Skip to: 7870
4119
/* 3962 */    MCD_OPC_CheckField, 0, 16, 14, 61, 15, 0, // Skip to: 7870
4120
/* 3969 */    MCD_OPC_Decode, 184, 8, 190, 1, // Opcode: AE_MULSF32X16_L2
4121
/* 3974 */    MCD_OPC_FilterValue, 128, 236, 4, 24, 0, 0, // Skip to: 4005
4122
/* 3981 */    MCD_OPC_CheckPredicate, 24, 44, 15, 0, // Skip to: 7870
4123
/* 3986 */    MCD_OPC_CheckField, 28, 2, 0, 37, 15, 0, // Skip to: 7870
4124
/* 3993 */    MCD_OPC_CheckField, 0, 16, 14, 30, 15, 0, // Skip to: 7870
4125
/* 4000 */    MCD_OPC_Decode, 186, 8, 190, 1, // Opcode: AE_MULSF32X16_L3
4126
/* 4005 */    MCD_OPC_FilterValue, 128, 240, 4, 24, 0, 0, // Skip to: 4036
4127
/* 4012 */    MCD_OPC_CheckPredicate, 24, 13, 15, 0, // Skip to: 7870
4128
/* 4017 */    MCD_OPC_CheckField, 28, 2, 0, 6, 15, 0, // Skip to: 7870
4129
/* 4024 */    MCD_OPC_CheckField, 0, 16, 14, 255, 14, 0, // Skip to: 7870
4130
/* 4031 */    MCD_OPC_Decode, 188, 8, 190, 1, // Opcode: AE_MULSF48Q32SP16S_L
4131
/* 4036 */    MCD_OPC_FilterValue, 128, 244, 4, 24, 0, 0, // Skip to: 4067
4132
/* 4043 */    MCD_OPC_CheckPredicate, 24, 238, 14, 0, // Skip to: 7870
4133
/* 4048 */    MCD_OPC_CheckField, 28, 2, 0, 231, 14, 0, // Skip to: 7870
4134
/* 4055 */    MCD_OPC_CheckField, 0, 16, 14, 224, 14, 0, // Skip to: 7870
4135
/* 4062 */    MCD_OPC_Decode, 190, 8, 190, 1, // Opcode: AE_MULSF48Q32SP16U_L
4136
/* 4067 */    MCD_OPC_FilterValue, 128, 248, 4, 24, 0, 0, // Skip to: 4098
4137
/* 4074 */    MCD_OPC_CheckPredicate, 24, 207, 14, 0, // Skip to: 7870
4138
/* 4079 */    MCD_OPC_CheckField, 28, 2, 0, 200, 14, 0, // Skip to: 7870
4139
/* 4086 */    MCD_OPC_CheckField, 0, 16, 14, 193, 14, 0, // Skip to: 7870
4140
/* 4093 */    MCD_OPC_Decode, 192, 8, 190, 1, // Opcode: AE_MULSFP24X2R
4141
/* 4098 */    MCD_OPC_FilterValue, 128, 252, 4, 24, 0, 0, // Skip to: 4129
4142
/* 4105 */    MCD_OPC_CheckPredicate, 24, 176, 14, 0, // Skip to: 7870
4143
/* 4110 */    MCD_OPC_CheckField, 28, 2, 0, 169, 14, 0, // Skip to: 7870
4144
/* 4117 */    MCD_OPC_CheckField, 0, 16, 14, 162, 14, 0, // Skip to: 7870
4145
/* 4124 */    MCD_OPC_Decode, 193, 8, 190, 1, // Opcode: AE_MULSFP24X2RA
4146
/* 4129 */    MCD_OPC_FilterValue, 128, 128, 5, 24, 0, 0, // Skip to: 4160
4147
/* 4136 */    MCD_OPC_CheckPredicate, 24, 145, 14, 0, // Skip to: 7870
4148
/* 4141 */    MCD_OPC_CheckField, 28, 2, 0, 138, 14, 0, // Skip to: 7870
4149
/* 4148 */    MCD_OPC_CheckField, 0, 16, 14, 131, 14, 0, // Skip to: 7870
4150
/* 4155 */    MCD_OPC_Decode, 196, 8, 190, 1, // Opcode: AE_MULSFP32X16X2RAS_H
4151
/* 4160 */    MCD_OPC_FilterValue, 128, 132, 5, 24, 0, 0, // Skip to: 4191
4152
/* 4167 */    MCD_OPC_CheckPredicate, 24, 114, 14, 0, // Skip to: 7870
4153
/* 4172 */    MCD_OPC_CheckField, 28, 2, 0, 107, 14, 0, // Skip to: 7870
4154
/* 4179 */    MCD_OPC_CheckField, 0, 16, 14, 100, 14, 0, // Skip to: 7870
4155
/* 4186 */    MCD_OPC_Decode, 198, 8, 190, 1, // Opcode: AE_MULSFP32X16X2RAS_L
4156
/* 4191 */    MCD_OPC_FilterValue, 128, 136, 5, 24, 0, 0, // Skip to: 4222
4157
/* 4198 */    MCD_OPC_CheckPredicate, 24, 83, 14, 0, // Skip to: 7870
4158
/* 4203 */    MCD_OPC_CheckField, 28, 2, 0, 76, 14, 0, // Skip to: 7870
4159
/* 4210 */    MCD_OPC_CheckField, 0, 16, 14, 69, 14, 0, // Skip to: 7870
4160
/* 4217 */    MCD_OPC_Decode, 200, 8, 190, 1, // Opcode: AE_MULSFP32X16X2RS_H
4161
/* 4222 */    MCD_OPC_FilterValue, 128, 140, 5, 24, 0, 0, // Skip to: 4253
4162
/* 4229 */    MCD_OPC_CheckPredicate, 24, 52, 14, 0, // Skip to: 7870
4163
/* 4234 */    MCD_OPC_CheckField, 28, 2, 0, 45, 14, 0, // Skip to: 7870
4164
/* 4241 */    MCD_OPC_CheckField, 0, 16, 14, 38, 14, 0, // Skip to: 7870
4165
/* 4248 */    MCD_OPC_Decode, 202, 8, 190, 1, // Opcode: AE_MULSFP32X16X2RS_L
4166
/* 4253 */    MCD_OPC_FilterValue, 128, 152, 5, 24, 0, 0, // Skip to: 4284
4167
/* 4260 */    MCD_OPC_CheckPredicate, 24, 21, 14, 0, // Skip to: 7870
4168
/* 4265 */    MCD_OPC_CheckField, 28, 2, 0, 14, 14, 0, // Skip to: 7870
4169
/* 4272 */    MCD_OPC_CheckField, 0, 16, 14, 7, 14, 0, // Skip to: 7870
4170
/* 4279 */    MCD_OPC_Decode, 204, 8, 190, 1, // Opcode: AE_MULSFP32X2RAS
4171
/* 4284 */    MCD_OPC_FilterValue, 128, 156, 5, 24, 0, 0, // Skip to: 4315
4172
/* 4291 */    MCD_OPC_CheckPredicate, 24, 246, 13, 0, // Skip to: 7870
4173
/* 4296 */    MCD_OPC_CheckField, 28, 2, 0, 239, 13, 0, // Skip to: 7870
4174
/* 4303 */    MCD_OPC_CheckField, 0, 16, 14, 232, 13, 0, // Skip to: 7870
4175
/* 4310 */    MCD_OPC_Decode, 205, 8, 190, 1, // Opcode: AE_MULSFP32X2RS
4176
/* 4315 */    MCD_OPC_FilterValue, 128, 160, 5, 24, 0, 0, // Skip to: 4346
4177
/* 4322 */    MCD_OPC_CheckPredicate, 24, 215, 13, 0, // Skip to: 7870
4178
/* 4327 */    MCD_OPC_CheckField, 28, 2, 0, 208, 13, 0, // Skip to: 7870
4179
/* 4334 */    MCD_OPC_CheckField, 0, 16, 14, 201, 13, 0, // Skip to: 7870
4180
/* 4341 */    MCD_OPC_Decode, 210, 8, 190, 1, // Opcode: AE_MULSP32X16X2_H
4181
/* 4346 */    MCD_OPC_FilterValue, 128, 164, 5, 24, 0, 0, // Skip to: 4377
4182
/* 4353 */    MCD_OPC_CheckPredicate, 24, 184, 13, 0, // Skip to: 7870
4183
/* 4358 */    MCD_OPC_CheckField, 28, 2, 0, 177, 13, 0, // Skip to: 7870
4184
/* 4365 */    MCD_OPC_CheckField, 0, 16, 14, 170, 13, 0, // Skip to: 7870
4185
/* 4372 */    MCD_OPC_Decode, 211, 8, 190, 1, // Opcode: AE_MULSP32X16X2_L
4186
/* 4377 */    MCD_OPC_FilterValue, 128, 168, 5, 24, 0, 0, // Skip to: 4408
4187
/* 4384 */    MCD_OPC_CheckPredicate, 24, 153, 13, 0, // Skip to: 7870
4188
/* 4389 */    MCD_OPC_CheckField, 28, 2, 0, 146, 13, 0, // Skip to: 7870
4189
/* 4396 */    MCD_OPC_CheckField, 0, 16, 14, 139, 13, 0, // Skip to: 7870
4190
/* 4403 */    MCD_OPC_Decode, 212, 8, 190, 1, // Opcode: AE_MULSP32X2
4191
/* 4408 */    MCD_OPC_FilterValue, 128, 180, 5, 24, 0, 0, // Skip to: 4439
4192
/* 4415 */    MCD_OPC_CheckPredicate, 24, 122, 13, 0, // Skip to: 7870
4193
/* 4420 */    MCD_OPC_CheckField, 28, 2, 0, 115, 13, 0, // Skip to: 7870
4194
/* 4427 */    MCD_OPC_CheckField, 0, 16, 14, 108, 13, 0, // Skip to: 7870
4195
/* 4434 */    MCD_OPC_Decode, 217, 8, 190, 1, // Opcode: AE_MULSS32F48P16S_HH
4196
/* 4439 */    MCD_OPC_FilterValue, 128, 184, 5, 24, 0, 0, // Skip to: 4470
4197
/* 4446 */    MCD_OPC_CheckPredicate, 24, 91, 13, 0, // Skip to: 7870
4198
/* 4451 */    MCD_OPC_CheckField, 28, 2, 0, 84, 13, 0, // Skip to: 7870
4199
/* 4458 */    MCD_OPC_CheckField, 0, 16, 14, 77, 13, 0, // Skip to: 7870
4200
/* 4465 */    MCD_OPC_Decode, 219, 8, 190, 1, // Opcode: AE_MULSS32F48P16S_LH
4201
/* 4470 */    MCD_OPC_FilterValue, 128, 188, 5, 24, 0, 0, // Skip to: 4501
4202
/* 4477 */    MCD_OPC_CheckPredicate, 24, 60, 13, 0, // Skip to: 7870
4203
/* 4482 */    MCD_OPC_CheckField, 28, 2, 0, 53, 13, 0, // Skip to: 7870
4204
/* 4489 */    MCD_OPC_CheckField, 0, 16, 14, 46, 13, 0, // Skip to: 7870
4205
/* 4496 */    MCD_OPC_Decode, 221, 8, 190, 1, // Opcode: AE_MULSS32F48P16S_LL
4206
/* 4501 */    MCD_OPC_FilterValue, 128, 192, 5, 24, 0, 0, // Skip to: 4532
4207
/* 4508 */    MCD_OPC_CheckPredicate, 24, 29, 13, 0, // Skip to: 7870
4208
/* 4513 */    MCD_OPC_CheckField, 28, 2, 0, 22, 13, 0, // Skip to: 7870
4209
/* 4520 */    MCD_OPC_CheckField, 0, 16, 14, 15, 13, 0, // Skip to: 7870
4210
/* 4527 */    MCD_OPC_Decode, 227, 8, 190, 1, // Opcode: AE_MULSSD32X16_H1_L0
4211
/* 4532 */    MCD_OPC_FilterValue, 128, 196, 5, 24, 0, 0, // Skip to: 4563
4212
/* 4539 */    MCD_OPC_CheckPredicate, 24, 254, 12, 0, // Skip to: 7870
4213
/* 4544 */    MCD_OPC_CheckField, 28, 2, 0, 247, 12, 0, // Skip to: 7870
4214
/* 4551 */    MCD_OPC_CheckField, 0, 16, 14, 240, 12, 0, // Skip to: 7870
4215
/* 4558 */    MCD_OPC_Decode, 229, 8, 190, 1, // Opcode: AE_MULSSD32X16_H3_L2
4216
/* 4563 */    MCD_OPC_FilterValue, 128, 208, 5, 24, 0, 0, // Skip to: 4594
4217
/* 4570 */    MCD_OPC_CheckPredicate, 24, 223, 12, 0, // Skip to: 7870
4218
/* 4575 */    MCD_OPC_CheckField, 28, 2, 0, 216, 12, 0, // Skip to: 7870
4219
/* 4582 */    MCD_OPC_CheckField, 0, 16, 14, 209, 12, 0, // Skip to: 7870
4220
/* 4589 */    MCD_OPC_Decode, 231, 8, 190, 1, // Opcode: AE_MULSSFD16SS_11_00
4221
/* 4594 */    MCD_OPC_FilterValue, 128, 212, 5, 24, 0, 0, // Skip to: 4625
4222
/* 4601 */    MCD_OPC_CheckPredicate, 24, 192, 12, 0, // Skip to: 7870
4223
/* 4606 */    MCD_OPC_CheckField, 28, 2, 0, 185, 12, 0, // Skip to: 7870
4224
/* 4613 */    MCD_OPC_CheckField, 0, 16, 14, 178, 12, 0, // Skip to: 7870
4225
/* 4620 */    MCD_OPC_Decode, 233, 8, 190, 1, // Opcode: AE_MULSSFD16SS_13_02
4226
/* 4625 */    MCD_OPC_FilterValue, 128, 216, 5, 24, 0, 0, // Skip to: 4656
4227
/* 4632 */    MCD_OPC_CheckPredicate, 24, 161, 12, 0, // Skip to: 7870
4228
/* 4637 */    MCD_OPC_CheckField, 28, 2, 0, 154, 12, 0, // Skip to: 7870
4229
/* 4644 */    MCD_OPC_CheckField, 0, 16, 14, 147, 12, 0, // Skip to: 7870
4230
/* 4651 */    MCD_OPC_Decode, 235, 8, 190, 1, // Opcode: AE_MULSSFD16SS_33_22
4231
/* 4656 */    MCD_OPC_FilterValue, 128, 236, 5, 24, 0, 0, // Skip to: 4687
4232
/* 4663 */    MCD_OPC_CheckPredicate, 24, 130, 12, 0, // Skip to: 7870
4233
/* 4668 */    MCD_OPC_CheckField, 28, 2, 0, 123, 12, 0, // Skip to: 7870
4234
/* 4675 */    MCD_OPC_CheckField, 0, 16, 14, 116, 12, 0, // Skip to: 7870
4235
/* 4682 */    MCD_OPC_Decode, 241, 8, 190, 1, // Opcode: AE_MULSSFD32X16_H1_L0
4236
/* 4687 */    MCD_OPC_FilterValue, 128, 240, 5, 24, 0, 0, // Skip to: 4718
4237
/* 4694 */    MCD_OPC_CheckPredicate, 24, 99, 12, 0, // Skip to: 7870
4238
/* 4699 */    MCD_OPC_CheckField, 28, 2, 0, 92, 12, 0, // Skip to: 7870
4239
/* 4706 */    MCD_OPC_CheckField, 0, 16, 14, 85, 12, 0, // Skip to: 7870
4240
/* 4713 */    MCD_OPC_Decode, 243, 8, 190, 1, // Opcode: AE_MULSSFD32X16_H3_L2
4241
/* 4718 */    MCD_OPC_FilterValue, 128, 248, 5, 24, 0, 0, // Skip to: 4749
4242
/* 4725 */    MCD_OPC_CheckPredicate, 24, 68, 12, 0, // Skip to: 7870
4243
/* 4730 */    MCD_OPC_CheckField, 28, 2, 0, 61, 12, 0, // Skip to: 7870
4244
/* 4737 */    MCD_OPC_CheckField, 0, 16, 14, 54, 12, 0, // Skip to: 7870
4245
/* 4744 */    MCD_OPC_Decode, 249, 8, 189, 1, // Opcode: AE_MULZAAD32X16_H0_L1
4246
/* 4749 */    MCD_OPC_FilterValue, 128, 252, 5, 24, 0, 0, // Skip to: 4780
4247
/* 4756 */    MCD_OPC_CheckPredicate, 24, 37, 12, 0, // Skip to: 7870
4248
/* 4761 */    MCD_OPC_CheckField, 28, 2, 0, 30, 12, 0, // Skip to: 7870
4249
/* 4768 */    MCD_OPC_CheckField, 0, 16, 14, 23, 12, 0, // Skip to: 7870
4250
/* 4775 */    MCD_OPC_Decode, 251, 8, 189, 1, // Opcode: AE_MULZAAD32X16_H1_L0
4251
/* 4780 */    MCD_OPC_FilterValue, 128, 128, 6, 24, 0, 0, // Skip to: 4811
4252
/* 4787 */    MCD_OPC_CheckPredicate, 24, 6, 12, 0, // Skip to: 7870
4253
/* 4792 */    MCD_OPC_CheckField, 28, 2, 0, 255, 11, 0, // Skip to: 7870
4254
/* 4799 */    MCD_OPC_CheckField, 0, 16, 14, 248, 11, 0, // Skip to: 7870
4255
/* 4806 */    MCD_OPC_Decode, 253, 8, 189, 1, // Opcode: AE_MULZAAD32X16_H2_L3
4256
/* 4811 */    MCD_OPC_FilterValue, 128, 132, 6, 24, 0, 0, // Skip to: 4842
4257
/* 4818 */    MCD_OPC_CheckPredicate, 24, 231, 11, 0, // Skip to: 7870
4258
/* 4823 */    MCD_OPC_CheckField, 28, 2, 0, 224, 11, 0, // Skip to: 7870
4259
/* 4830 */    MCD_OPC_CheckField, 0, 16, 14, 217, 11, 0, // Skip to: 7870
4260
/* 4837 */    MCD_OPC_Decode, 255, 8, 189, 1, // Opcode: AE_MULZAAD32X16_H3_L2
4261
/* 4842 */    MCD_OPC_FilterValue, 128, 144, 6, 24, 0, 0, // Skip to: 4873
4262
/* 4849 */    MCD_OPC_CheckPredicate, 24, 200, 11, 0, // Skip to: 7870
4263
/* 4854 */    MCD_OPC_CheckField, 28, 2, 0, 193, 11, 0, // Skip to: 7870
4264
/* 4861 */    MCD_OPC_CheckField, 0, 16, 14, 186, 11, 0, // Skip to: 7870
4265
/* 4868 */    MCD_OPC_Decode, 129, 9, 189, 1, // Opcode: AE_MULZAAFD16SS_11_00
4266
/* 4873 */    MCD_OPC_FilterValue, 128, 148, 6, 24, 0, 0, // Skip to: 4904
4267
/* 4880 */    MCD_OPC_CheckPredicate, 24, 169, 11, 0, // Skip to: 7870
4268
/* 4885 */    MCD_OPC_CheckField, 28, 2, 0, 162, 11, 0, // Skip to: 7870
4269
/* 4892 */    MCD_OPC_CheckField, 0, 16, 14, 155, 11, 0, // Skip to: 7870
4270
/* 4899 */    MCD_OPC_Decode, 131, 9, 189, 1, // Opcode: AE_MULZAAFD16SS_13_02
4271
/* 4904 */    MCD_OPC_FilterValue, 128, 152, 6, 24, 0, 0, // Skip to: 4935
4272
/* 4911 */    MCD_OPC_CheckPredicate, 24, 138, 11, 0, // Skip to: 7870
4273
/* 4916 */    MCD_OPC_CheckField, 28, 2, 0, 131, 11, 0, // Skip to: 7870
4274
/* 4923 */    MCD_OPC_CheckField, 0, 16, 14, 124, 11, 0, // Skip to: 7870
4275
/* 4930 */    MCD_OPC_Decode, 133, 9, 189, 1, // Opcode: AE_MULZAAFD16SS_33_22
4276
/* 4935 */    MCD_OPC_FilterValue, 128, 172, 6, 24, 0, 0, // Skip to: 4966
4277
/* 4942 */    MCD_OPC_CheckPredicate, 24, 107, 11, 0, // Skip to: 7870
4278
/* 4947 */    MCD_OPC_CheckField, 28, 2, 0, 100, 11, 0, // Skip to: 7870
4279
/* 4954 */    MCD_OPC_CheckField, 0, 16, 14, 93, 11, 0, // Skip to: 7870
4280
/* 4961 */    MCD_OPC_Decode, 139, 9, 189, 1, // Opcode: AE_MULZAAFD32X16_H0_L1
4281
/* 4966 */    MCD_OPC_FilterValue, 128, 176, 6, 24, 0, 0, // Skip to: 4997
4282
/* 4973 */    MCD_OPC_CheckPredicate, 24, 76, 11, 0, // Skip to: 7870
4283
/* 4978 */    MCD_OPC_CheckField, 28, 2, 0, 69, 11, 0, // Skip to: 7870
4284
/* 4985 */    MCD_OPC_CheckField, 0, 16, 14, 62, 11, 0, // Skip to: 7870
4285
/* 4992 */    MCD_OPC_Decode, 141, 9, 189, 1, // Opcode: AE_MULZAAFD32X16_H1_L0
4286
/* 4997 */    MCD_OPC_FilterValue, 128, 180, 6, 24, 0, 0, // Skip to: 5028
4287
/* 5004 */    MCD_OPC_CheckPredicate, 24, 45, 11, 0, // Skip to: 7870
4288
/* 5009 */    MCD_OPC_CheckField, 28, 2, 0, 38, 11, 0, // Skip to: 7870
4289
/* 5016 */    MCD_OPC_CheckField, 0, 16, 14, 31, 11, 0, // Skip to: 7870
4290
/* 5023 */    MCD_OPC_Decode, 143, 9, 189, 1, // Opcode: AE_MULZAAFD32X16_H2_L3
4291
/* 5028 */    MCD_OPC_FilterValue, 128, 184, 6, 24, 0, 0, // Skip to: 5059
4292
/* 5035 */    MCD_OPC_CheckPredicate, 24, 14, 11, 0, // Skip to: 7870
4293
/* 5040 */    MCD_OPC_CheckField, 28, 2, 0, 7, 11, 0, // Skip to: 7870
4294
/* 5047 */    MCD_OPC_CheckField, 0, 16, 14, 0, 11, 0, // Skip to: 7870
4295
/* 5054 */    MCD_OPC_Decode, 145, 9, 189, 1, // Opcode: AE_MULZAAFD32X16_H3_L2
4296
/* 5059 */    MCD_OPC_FilterValue, 128, 188, 6, 24, 0, 0, // Skip to: 5090
4297
/* 5066 */    MCD_OPC_CheckPredicate, 24, 239, 10, 0, // Skip to: 7870
4298
/* 5071 */    MCD_OPC_CheckField, 28, 2, 0, 232, 10, 0, // Skip to: 7870
4299
/* 5078 */    MCD_OPC_CheckField, 0, 16, 14, 225, 10, 0, // Skip to: 7870
4300
/* 5085 */    MCD_OPC_Decode, 151, 9, 189, 1, // Opcode: AE_MULZASD32X16_H1_L0
4301
/* 5090 */    MCD_OPC_FilterValue, 128, 192, 6, 24, 0, 0, // Skip to: 5121
4302
/* 5097 */    MCD_OPC_CheckPredicate, 24, 208, 10, 0, // Skip to: 7870
4303
/* 5102 */    MCD_OPC_CheckField, 28, 2, 0, 201, 10, 0, // Skip to: 7870
4304
/* 5109 */    MCD_OPC_CheckField, 0, 16, 14, 194, 10, 0, // Skip to: 7870
4305
/* 5116 */    MCD_OPC_Decode, 153, 9, 189, 1, // Opcode: AE_MULZASD32X16_H3_L2
4306
/* 5121 */    MCD_OPC_FilterValue, 128, 220, 6, 24, 0, 0, // Skip to: 5152
4307
/* 5128 */    MCD_OPC_CheckPredicate, 24, 177, 10, 0, // Skip to: 7870
4308
/* 5133 */    MCD_OPC_CheckField, 28, 2, 0, 170, 10, 0, // Skip to: 7870
4309
/* 5140 */    MCD_OPC_CheckField, 0, 16, 14, 163, 10, 0, // Skip to: 7870
4310
/* 5147 */    MCD_OPC_Decode, 159, 9, 189, 1, // Opcode: AE_MULZASFD32X16_H1_L0
4311
/* 5152 */    MCD_OPC_FilterValue, 128, 224, 6, 24, 0, 0, // Skip to: 5183
4312
/* 5159 */    MCD_OPC_CheckPredicate, 24, 146, 10, 0, // Skip to: 7870
4313
/* 5164 */    MCD_OPC_CheckField, 28, 2, 0, 139, 10, 0, // Skip to: 7870
4314
/* 5171 */    MCD_OPC_CheckField, 0, 16, 14, 132, 10, 0, // Skip to: 7870
4315
/* 5178 */    MCD_OPC_Decode, 161, 9, 189, 1, // Opcode: AE_MULZASFD32X16_H3_L2
4316
/* 5183 */    MCD_OPC_FilterValue, 128, 240, 6, 24, 0, 0, // Skip to: 5214
4317
/* 5190 */    MCD_OPC_CheckPredicate, 24, 115, 10, 0, // Skip to: 7870
4318
/* 5195 */    MCD_OPC_CheckField, 28, 2, 0, 108, 10, 0, // Skip to: 7870
4319
/* 5202 */    MCD_OPC_CheckField, 0, 16, 14, 101, 10, 0, // Skip to: 7870
4320
/* 5209 */    MCD_OPC_Decode, 171, 9, 189, 1, // Opcode: AE_MULZSAFD32X16_H1_L0
4321
/* 5214 */    MCD_OPC_FilterValue, 128, 244, 6, 24, 0, 0, // Skip to: 5245
4322
/* 5221 */    MCD_OPC_CheckPredicate, 24, 84, 10, 0, // Skip to: 7870
4323
/* 5226 */    MCD_OPC_CheckField, 28, 2, 0, 77, 10, 0, // Skip to: 7870
4324
/* 5233 */    MCD_OPC_CheckField, 0, 16, 14, 70, 10, 0, // Skip to: 7870
4325
/* 5240 */    MCD_OPC_Decode, 173, 9, 189, 1, // Opcode: AE_MULZSAFD32X16_H3_L2
4326
/* 5245 */    MCD_OPC_FilterValue, 128, 248, 6, 24, 0, 0, // Skip to: 5276
4327
/* 5252 */    MCD_OPC_CheckPredicate, 24, 53, 10, 0, // Skip to: 7870
4328
/* 5257 */    MCD_OPC_CheckField, 28, 2, 0, 46, 10, 0, // Skip to: 7870
4329
/* 5264 */    MCD_OPC_CheckField, 0, 16, 14, 39, 10, 0, // Skip to: 7870
4330
/* 5271 */    MCD_OPC_Decode, 179, 9, 189, 1, // Opcode: AE_MULZSSD32X16_H1_L0
4331
/* 5276 */    MCD_OPC_FilterValue, 128, 252, 6, 24, 0, 0, // Skip to: 5307
4332
/* 5283 */    MCD_OPC_CheckPredicate, 24, 22, 10, 0, // Skip to: 7870
4333
/* 5288 */    MCD_OPC_CheckField, 28, 2, 0, 15, 10, 0, // Skip to: 7870
4334
/* 5295 */    MCD_OPC_CheckField, 0, 16, 14, 8, 10, 0, // Skip to: 7870
4335
/* 5302 */    MCD_OPC_Decode, 181, 9, 189, 1, // Opcode: AE_MULZSSD32X16_H3_L2
4336
/* 5307 */    MCD_OPC_FilterValue, 128, 136, 7, 24, 0, 0, // Skip to: 5338
4337
/* 5314 */    MCD_OPC_CheckPredicate, 24, 247, 9, 0, // Skip to: 7870
4338
/* 5319 */    MCD_OPC_CheckField, 28, 2, 0, 240, 9, 0, // Skip to: 7870
4339
/* 5326 */    MCD_OPC_CheckField, 0, 16, 14, 233, 9, 0, // Skip to: 7870
4340
/* 5333 */    MCD_OPC_Decode, 183, 9, 189, 1, // Opcode: AE_MULZSSFD16SS_11_00
4341
/* 5338 */    MCD_OPC_FilterValue, 128, 140, 7, 24, 0, 0, // Skip to: 5369
4342
/* 5345 */    MCD_OPC_CheckPredicate, 24, 216, 9, 0, // Skip to: 7870
4343
/* 5350 */    MCD_OPC_CheckField, 28, 2, 0, 209, 9, 0, // Skip to: 7870
4344
/* 5357 */    MCD_OPC_CheckField, 0, 16, 14, 202, 9, 0, // Skip to: 7870
4345
/* 5364 */    MCD_OPC_Decode, 185, 9, 189, 1, // Opcode: AE_MULZSSFD16SS_13_02
4346
/* 5369 */    MCD_OPC_FilterValue, 128, 144, 7, 24, 0, 0, // Skip to: 5400
4347
/* 5376 */    MCD_OPC_CheckPredicate, 24, 185, 9, 0, // Skip to: 7870
4348
/* 5381 */    MCD_OPC_CheckField, 28, 2, 0, 178, 9, 0, // Skip to: 7870
4349
/* 5388 */    MCD_OPC_CheckField, 0, 16, 14, 171, 9, 0, // Skip to: 7870
4350
/* 5395 */    MCD_OPC_Decode, 187, 9, 189, 1, // Opcode: AE_MULZSSFD16SS_33_22
4351
/* 5400 */    MCD_OPC_FilterValue, 128, 164, 7, 24, 0, 0, // Skip to: 5431
4352
/* 5407 */    MCD_OPC_CheckPredicate, 24, 154, 9, 0, // Skip to: 7870
4353
/* 5412 */    MCD_OPC_CheckField, 28, 2, 0, 147, 9, 0, // Skip to: 7870
4354
/* 5419 */    MCD_OPC_CheckField, 0, 16, 14, 140, 9, 0, // Skip to: 7870
4355
/* 5426 */    MCD_OPC_Decode, 193, 9, 189, 1, // Opcode: AE_MULZSSFD32X16_H1_L0
4356
/* 5431 */    MCD_OPC_FilterValue, 128, 168, 7, 24, 0, 0, // Skip to: 5462
4357
/* 5438 */    MCD_OPC_CheckPredicate, 24, 123, 9, 0, // Skip to: 7870
4358
/* 5443 */    MCD_OPC_CheckField, 28, 2, 0, 116, 9, 0, // Skip to: 7870
4359
/* 5450 */    MCD_OPC_CheckField, 0, 16, 14, 109, 9, 0, // Skip to: 7870
4360
/* 5457 */    MCD_OPC_Decode, 195, 9, 189, 1, // Opcode: AE_MULZSSFD32X16_H3_L2
4361
/* 5462 */    MCD_OPC_FilterValue, 128, 176, 7, 24, 0, 0, // Skip to: 5493
4362
/* 5469 */    MCD_OPC_CheckPredicate, 24, 92, 9, 0, // Skip to: 7870
4363
/* 5474 */    MCD_OPC_CheckField, 28, 2, 0, 85, 9, 0, // Skip to: 7870
4364
/* 5481 */    MCD_OPC_CheckField, 0, 16, 14, 78, 9, 0, // Skip to: 7870
4365
/* 5488 */    MCD_OPC_Decode, 193, 6, 191, 1, // Opcode: AE_MULAC32X16_H
4366
/* 5493 */    MCD_OPC_FilterValue, 128, 180, 7, 24, 0, 0, // Skip to: 5524
4367
/* 5500 */    MCD_OPC_CheckPredicate, 24, 61, 9, 0, // Skip to: 7870
4368
/* 5505 */    MCD_OPC_CheckField, 28, 2, 0, 54, 9, 0, // Skip to: 7870
4369
/* 5512 */    MCD_OPC_CheckField, 0, 16, 14, 47, 9, 0, // Skip to: 7870
4370
/* 5519 */    MCD_OPC_Decode, 194, 6, 191, 1, // Opcode: AE_MULAC32X16_L
4371
/* 5524 */    MCD_OPC_FilterValue, 128, 184, 7, 24, 0, 0, // Skip to: 5555
4372
/* 5531 */    MCD_OPC_CheckPredicate, 24, 30, 9, 0, // Skip to: 7870
4373
/* 5536 */    MCD_OPC_CheckField, 28, 2, 0, 23, 9, 0, // Skip to: 7870
4374
/* 5543 */    MCD_OPC_CheckField, 0, 16, 14, 16, 9, 0, // Skip to: 7870
4375
/* 5550 */    MCD_OPC_Decode, 235, 6, 191, 1, // Opcode: AE_MULAFC24RA
4376
/* 5555 */    MCD_OPC_FilterValue, 128, 192, 7, 24, 0, 0, // Skip to: 5586
4377
/* 5562 */    MCD_OPC_CheckPredicate, 24, 255, 8, 0, // Skip to: 7870
4378
/* 5567 */    MCD_OPC_CheckField, 28, 2, 0, 248, 8, 0, // Skip to: 7870
4379
/* 5574 */    MCD_OPC_CheckField, 0, 16, 14, 241, 8, 0, // Skip to: 7870
4380
/* 5581 */    MCD_OPC_Decode, 236, 6, 191, 1, // Opcode: AE_MULAFC32X16RAS_H
4381
/* 5586 */    MCD_OPC_FilterValue, 128, 196, 7, 24, 0, 0, // Skip to: 5617
4382
/* 5593 */    MCD_OPC_CheckPredicate, 24, 224, 8, 0, // Skip to: 7870
4383
/* 5598 */    MCD_OPC_CheckField, 28, 2, 0, 217, 8, 0, // Skip to: 7870
4384
/* 5605 */    MCD_OPC_CheckField, 0, 16, 14, 210, 8, 0, // Skip to: 7870
4385
/* 5612 */    MCD_OPC_Decode, 237, 6, 191, 1, // Opcode: AE_MULAFC32X16RAS_L
4386
/* 5617 */    MCD_OPC_FilterValue, 128, 204, 7, 24, 0, 0, // Skip to: 5648
4387
/* 5624 */    MCD_OPC_CheckPredicate, 24, 193, 8, 0, // Skip to: 7870
4388
/* 5629 */    MCD_OPC_CheckField, 28, 2, 0, 186, 8, 0, // Skip to: 7870
4389
/* 5636 */    MCD_OPC_CheckField, 0, 16, 14, 179, 8, 0, // Skip to: 7870
4390
/* 5643 */    MCD_OPC_Decode, 164, 7, 192, 1, // Opcode: AE_MULC32X16_H
4391
/* 5648 */    MCD_OPC_FilterValue, 128, 208, 7, 24, 0, 0, // Skip to: 5679
4392
/* 5655 */    MCD_OPC_CheckPredicate, 24, 162, 8, 0, // Skip to: 7870
4393
/* 5660 */    MCD_OPC_CheckField, 28, 2, 0, 155, 8, 0, // Skip to: 7870
4394
/* 5667 */    MCD_OPC_CheckField, 0, 16, 14, 148, 8, 0, // Skip to: 7870
4395
/* 5674 */    MCD_OPC_Decode, 165, 7, 192, 1, // Opcode: AE_MULC32X16_L
4396
/* 5679 */    MCD_OPC_FilterValue, 128, 212, 7, 24, 0, 0, // Skip to: 5710
4397
/* 5686 */    MCD_OPC_CheckPredicate, 24, 131, 8, 0, // Skip to: 7870
4398
/* 5691 */    MCD_OPC_CheckField, 28, 2, 0, 124, 8, 0, // Skip to: 7870
4399
/* 5698 */    MCD_OPC_CheckField, 0, 16, 14, 117, 8, 0, // Skip to: 7870
4400
/* 5705 */    MCD_OPC_Decode, 206, 7, 192, 1, // Opcode: AE_MULFC24RA
4401
/* 5710 */    MCD_OPC_FilterValue, 128, 220, 7, 24, 0, 0, // Skip to: 5741
4402
/* 5717 */    MCD_OPC_CheckPredicate, 24, 100, 8, 0, // Skip to: 7870
4403
/* 5722 */    MCD_OPC_CheckField, 28, 2, 0, 93, 8, 0, // Skip to: 7870
4404
/* 5729 */    MCD_OPC_CheckField, 0, 16, 14, 86, 8, 0, // Skip to: 7870
4405
/* 5736 */    MCD_OPC_Decode, 207, 7, 192, 1, // Opcode: AE_MULFC32X16RAS_H
4406
/* 5741 */    MCD_OPC_FilterValue, 128, 224, 7, 24, 0, 0, // Skip to: 5772
4407
/* 5748 */    MCD_OPC_CheckPredicate, 24, 69, 8, 0, // Skip to: 7870
4408
/* 5753 */    MCD_OPC_CheckField, 28, 2, 0, 62, 8, 0, // Skip to: 7870
4409
/* 5760 */    MCD_OPC_CheckField, 0, 16, 14, 55, 8, 0, // Skip to: 7870
4410
/* 5767 */    MCD_OPC_Decode, 208, 7, 192, 1, // Opcode: AE_MULFC32X16RAS_L
4411
/* 5772 */    MCD_OPC_FilterValue, 246, 128, 12, 25, 0, 0, // Skip to: 5804
4412
/* 5779 */    MCD_OPC_CheckPredicate, 24, 38, 8, 0, // Skip to: 7870
4413
/* 5784 */    MCD_OPC_CheckField, 16, 14, 128, 96, 30, 8, 0, // Skip to: 7870
4414
/* 5792 */    MCD_OPC_CheckField, 0, 4, 14, 23, 8, 0, // Skip to: 7870
4415
/* 5799 */    MCD_OPC_Decode, 251, 4, 153, 1, // Opcode: AE_L16M_X
4416
/* 5804 */    MCD_OPC_FilterValue, 247, 128, 12, 48, 0, 0, // Skip to: 5859
4417
/* 5811 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4418
/* 5814 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5836
4419
/* 5819 */    MCD_OPC_CheckPredicate, 24, 254, 7, 0, // Skip to: 7870
4420
/* 5824 */    MCD_OPC_CheckField, 0, 4, 14, 247, 7, 0, // Skip to: 7870
4421
/* 5831 */    MCD_OPC_Decode, 252, 4, 185, 1, // Opcode: AE_L16M_XC
4422
/* 5836 */    MCD_OPC_FilterValue, 128, 96, 236, 7, 0, // Skip to: 7870
4423
/* 5842 */    MCD_OPC_CheckPredicate, 24, 231, 7, 0, // Skip to: 7870
4424
/* 5847 */    MCD_OPC_CheckField, 0, 4, 14, 224, 7, 0, // Skip to: 7870
4425
/* 5854 */    MCD_OPC_Decode, 129, 5, 185, 1, // Opcode: AE_L16X2M_XC
4426
/* 5859 */    MCD_OPC_FilterValue, 248, 128, 12, 49, 0, 0, // Skip to: 5915
4427
/* 5866 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4428
/* 5869 */    MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 5892
4429
/* 5875 */    MCD_OPC_CheckPredicate, 24, 198, 7, 0, // Skip to: 7870
4430
/* 5880 */    MCD_OPC_CheckField, 0, 4, 14, 191, 7, 0, // Skip to: 7870
4431
/* 5887 */    MCD_OPC_Decode, 135, 5, 153, 1, // Opcode: AE_L16X4_X
4432
/* 5892 */    MCD_OPC_FilterValue, 128, 64, 180, 7, 0, // Skip to: 7870
4433
/* 5898 */    MCD_OPC_CheckPredicate, 24, 175, 7, 0, // Skip to: 7870
4434
/* 5903 */    MCD_OPC_CheckField, 0, 4, 14, 168, 7, 0, // Skip to: 7870
4435
/* 5910 */    MCD_OPC_Decode, 136, 5, 185, 1, // Opcode: AE_L16X4_XC
4436
/* 5915 */    MCD_OPC_FilterValue, 249, 128, 12, 94, 0, 0, // Skip to: 6016
4437
/* 5922 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4438
/* 5925 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5947
4439
/* 5930 */    MCD_OPC_CheckPredicate, 24, 143, 7, 0, // Skip to: 7870
4440
/* 5935 */    MCD_OPC_CheckField, 0, 4, 14, 136, 7, 0, // Skip to: 7870
4441
/* 5942 */    MCD_OPC_Decode, 140, 5, 153, 1, // Opcode: AE_L16_X
4442
/* 5947 */    MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 5970
4443
/* 5953 */    MCD_OPC_CheckPredicate, 24, 120, 7, 0, // Skip to: 7870
4444
/* 5958 */    MCD_OPC_CheckField, 0, 4, 14, 113, 7, 0, // Skip to: 7870
4445
/* 5965 */    MCD_OPC_Decode, 141, 5, 185, 1, // Opcode: AE_L16_XC
4446
/* 5970 */    MCD_OPC_FilterValue, 128, 64, 17, 0, 0, // Skip to: 5993
4447
/* 5976 */    MCD_OPC_CheckPredicate, 24, 97, 7, 0, // Skip to: 7870
4448
/* 5981 */    MCD_OPC_CheckField, 0, 4, 14, 90, 7, 0, // Skip to: 7870
4449
/* 5988 */    MCD_OPC_Decode, 142, 5, 185, 1, // Opcode: AE_L16_XP
4450
/* 5993 */    MCD_OPC_FilterValue, 128, 96, 79, 7, 0, // Skip to: 7870
4451
/* 5999 */    MCD_OPC_CheckPredicate, 24, 74, 7, 0, // Skip to: 7870
4452
/* 6004 */    MCD_OPC_CheckField, 0, 4, 14, 67, 7, 0, // Skip to: 7870
4453
/* 6011 */    MCD_OPC_Decode, 145, 5, 153, 1, // Opcode: AE_L32F24_X
4454
/* 6016 */    MCD_OPC_FilterValue, 250, 128, 12, 49, 0, 0, // Skip to: 6072
4455
/* 6023 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4456
/* 6026 */    MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6049
4457
/* 6032 */    MCD_OPC_CheckPredicate, 24, 41, 7, 0, // Skip to: 7870
4458
/* 6037 */    MCD_OPC_CheckField, 0, 4, 14, 34, 7, 0, // Skip to: 7870
4459
/* 6044 */    MCD_OPC_Decode, 147, 5, 185, 1, // Opcode: AE_L32F24_XP
4460
/* 6049 */    MCD_OPC_FilterValue, 128, 96, 23, 7, 0, // Skip to: 7870
4461
/* 6055 */    MCD_OPC_CheckPredicate, 24, 18, 7, 0, // Skip to: 7870
4462
/* 6060 */    MCD_OPC_CheckField, 0, 4, 14, 11, 7, 0, // Skip to: 7870
4463
/* 6067 */    MCD_OPC_Decode, 151, 5, 185, 1, // Opcode: AE_L32M_XC
4464
/* 6072 */    MCD_OPC_FilterValue, 253, 128, 12, 72, 0, 0, // Skip to: 6151
4465
/* 6079 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4466
/* 6082 */    MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6105
4467
/* 6088 */    MCD_OPC_CheckPredicate, 24, 241, 6, 0, // Skip to: 7870
4468
/* 6093 */    MCD_OPC_CheckField, 0, 4, 14, 234, 6, 0, // Skip to: 7870
4469
/* 6100 */    MCD_OPC_Decode, 171, 5, 185, 1, // Opcode: AE_L32_XP
4470
/* 6105 */    MCD_OPC_FilterValue, 128, 64, 17, 0, 0, // Skip to: 6128
4471
/* 6111 */    MCD_OPC_CheckPredicate, 24, 218, 6, 0, // Skip to: 7870
4472
/* 6116 */    MCD_OPC_CheckField, 0, 4, 14, 211, 6, 0, // Skip to: 7870
4473
/* 6123 */    MCD_OPC_Decode, 174, 5, 153, 1, // Opcode: AE_L64_X
4474
/* 6128 */    MCD_OPC_FilterValue, 128, 96, 200, 6, 0, // Skip to: 7870
4475
/* 6134 */    MCD_OPC_CheckPredicate, 24, 195, 6, 0, // Skip to: 7870
4476
/* 6139 */    MCD_OPC_CheckField, 0, 4, 14, 188, 6, 0, // Skip to: 7870
4477
/* 6146 */    MCD_OPC_Decode, 175, 5, 185, 1, // Opcode: AE_L64_XC
4478
/* 6151 */    MCD_OPC_FilterValue, 254, 128, 12, 71, 0, 0, // Skip to: 6229
4479
/* 6158 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4480
/* 6161 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6183
4481
/* 6166 */    MCD_OPC_CheckPredicate, 24, 163, 6, 0, // Skip to: 7870
4482
/* 6171 */    MCD_OPC_CheckField, 0, 4, 14, 156, 6, 0, // Skip to: 7870
4483
/* 6178 */    MCD_OPC_Decode, 176, 5, 185, 1, // Opcode: AE_L64_XP
4484
/* 6183 */    MCD_OPC_FilterValue, 128, 64, 17, 0, 0, // Skip to: 6206
4485
/* 6189 */    MCD_OPC_CheckPredicate, 24, 140, 6, 0, // Skip to: 7870
4486
/* 6194 */    MCD_OPC_CheckField, 0, 4, 14, 133, 6, 0, // Skip to: 7870
4487
/* 6201 */    MCD_OPC_Decode, 227, 9, 148, 1, // Opcode: AE_S16M_L_XC
4488
/* 6206 */    MCD_OPC_FilterValue, 128, 96, 122, 6, 0, // Skip to: 7870
4489
/* 6212 */    MCD_OPC_CheckPredicate, 24, 117, 6, 0, // Skip to: 7870
4490
/* 6217 */    MCD_OPC_CheckField, 0, 4, 14, 110, 6, 0, // Skip to: 7870
4491
/* 6224 */    MCD_OPC_Decode, 228, 9, 148, 1, // Opcode: AE_S16M_L_XU
4492
/* 6229 */    MCD_OPC_FilterValue, 255, 128, 12, 49, 0, 0, // Skip to: 6285
4493
/* 6236 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4494
/* 6239 */    MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6262
4495
/* 6245 */    MCD_OPC_CheckPredicate, 24, 84, 6, 0, // Skip to: 7870
4496
/* 6250 */    MCD_OPC_CheckField, 0, 4, 14, 77, 6, 0, // Skip to: 7870
4497
/* 6257 */    MCD_OPC_Decode, 232, 9, 148, 1, // Opcode: AE_S16X2M_XC
4498
/* 6262 */    MCD_OPC_FilterValue, 128, 96, 66, 6, 0, // Skip to: 7870
4499
/* 6268 */    MCD_OPC_CheckPredicate, 24, 61, 6, 0, // Skip to: 7870
4500
/* 6273 */    MCD_OPC_CheckField, 0, 4, 14, 54, 6, 0, // Skip to: 7870
4501
/* 6280 */    MCD_OPC_Decode, 238, 9, 153, 1, // Opcode: AE_S16X4_X
4502
/* 6285 */    MCD_OPC_FilterValue, 128, 129, 12, 94, 0, 0, // Skip to: 6386
4503
/* 6292 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4504
/* 6295 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6317
4505
/* 6300 */    MCD_OPC_CheckPredicate, 24, 29, 6, 0, // Skip to: 7870
4506
/* 6305 */    MCD_OPC_CheckField, 0, 4, 14, 22, 6, 0, // Skip to: 7870
4507
/* 6312 */    MCD_OPC_Decode, 239, 9, 148, 1, // Opcode: AE_S16X4_XC
4508
/* 6317 */    MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6340
4509
/* 6323 */    MCD_OPC_CheckPredicate, 24, 6, 6, 0, // Skip to: 7870
4510
/* 6328 */    MCD_OPC_CheckField, 0, 4, 14, 255, 5, 0, // Skip to: 7870
4511
/* 6335 */    MCD_OPC_Decode, 240, 9, 148, 1, // Opcode: AE_S16X4_XP
4512
/* 6340 */    MCD_OPC_FilterValue, 128, 64, 17, 0, 0, // Skip to: 6363
4513
/* 6346 */    MCD_OPC_CheckPredicate, 24, 239, 5, 0, // Skip to: 7870
4514
/* 6351 */    MCD_OPC_CheckField, 0, 4, 14, 232, 5, 0, // Skip to: 7870
4515
/* 6358 */    MCD_OPC_Decode, 243, 9, 153, 1, // Opcode: AE_S16_0_X
4516
/* 6363 */    MCD_OPC_FilterValue, 128, 96, 221, 5, 0, // Skip to: 7870
4517
/* 6369 */    MCD_OPC_CheckPredicate, 24, 216, 5, 0, // Skip to: 7870
4518
/* 6374 */    MCD_OPC_CheckField, 0, 4, 14, 209, 5, 0, // Skip to: 7870
4519
/* 6381 */    MCD_OPC_Decode, 244, 9, 148, 1, // Opcode: AE_S16_0_XC
4520
/* 6386 */    MCD_OPC_FilterValue, 129, 129, 12, 49, 0, 0, // Skip to: 6442
4521
/* 6393 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4522
/* 6396 */    MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6419
4523
/* 6402 */    MCD_OPC_CheckPredicate, 24, 183, 5, 0, // Skip to: 7870
4524
/* 6407 */    MCD_OPC_CheckField, 0, 4, 14, 176, 5, 0, // Skip to: 7870
4525
/* 6414 */    MCD_OPC_Decode, 248, 9, 153, 1, // Opcode: AE_S24RA64S_X
4526
/* 6419 */    MCD_OPC_FilterValue, 128, 64, 165, 5, 0, // Skip to: 7870
4527
/* 6425 */    MCD_OPC_CheckPredicate, 24, 160, 5, 0, // Skip to: 7870
4528
/* 6430 */    MCD_OPC_CheckField, 0, 4, 14, 153, 5, 0, // Skip to: 7870
4529
/* 6437 */    MCD_OPC_Decode, 249, 9, 148, 1, // Opcode: AE_S24RA64S_XC
4530
/* 6442 */    MCD_OPC_FilterValue, 130, 129, 12, 71, 0, 0, // Skip to: 6520
4531
/* 6449 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4532
/* 6452 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6474
4533
/* 6457 */    MCD_OPC_CheckPredicate, 24, 128, 5, 0, // Skip to: 7870
4534
/* 6462 */    MCD_OPC_CheckField, 0, 4, 14, 121, 5, 0, // Skip to: 7870
4535
/* 6469 */    MCD_OPC_Decode, 254, 9, 153, 1, // Opcode: AE_S32F24_L_X
4536
/* 6474 */    MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6497
4537
/* 6480 */    MCD_OPC_CheckPredicate, 24, 105, 5, 0, // Skip to: 7870
4538
/* 6485 */    MCD_OPC_CheckField, 0, 4, 14, 98, 5, 0, // Skip to: 7870
4539
/* 6492 */    MCD_OPC_Decode, 255, 9, 148, 1, // Opcode: AE_S32F24_L_XC
4540
/* 6497 */    MCD_OPC_FilterValue, 128, 64, 87, 5, 0, // Skip to: 7870
4541
/* 6503 */    MCD_OPC_CheckPredicate, 24, 82, 5, 0, // Skip to: 7870
4542
/* 6508 */    MCD_OPC_CheckField, 0, 4, 14, 75, 5, 0, // Skip to: 7870
4543
/* 6515 */    MCD_OPC_Decode, 128, 10, 148, 1, // Opcode: AE_S32F24_L_XP
4544
/* 6520 */    MCD_OPC_FilterValue, 131, 129, 12, 71, 0, 0, // Skip to: 6598
4545
/* 6527 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4546
/* 6530 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6552
4547
/* 6535 */    MCD_OPC_CheckPredicate, 24, 50, 5, 0, // Skip to: 7870
4548
/* 6540 */    MCD_OPC_CheckField, 0, 4, 14, 43, 5, 0, // Skip to: 7870
4549
/* 6547 */    MCD_OPC_Decode, 132, 10, 148, 1, // Opcode: AE_S32M_XC
4550
/* 6552 */    MCD_OPC_FilterValue, 128, 64, 17, 0, 0, // Skip to: 6575
4551
/* 6558 */    MCD_OPC_CheckPredicate, 24, 27, 5, 0, // Skip to: 7870
4552
/* 6563 */    MCD_OPC_CheckField, 0, 4, 14, 20, 5, 0, // Skip to: 7870
4553
/* 6570 */    MCD_OPC_Decode, 136, 10, 153, 1, // Opcode: AE_S32RA64S_X
4554
/* 6575 */    MCD_OPC_FilterValue, 128, 96, 9, 5, 0, // Skip to: 7870
4555
/* 6581 */    MCD_OPC_CheckPredicate, 24, 4, 5, 0, // Skip to: 7870
4556
/* 6586 */    MCD_OPC_CheckField, 0, 4, 14, 253, 4, 0, // Skip to: 7870
4557
/* 6593 */    MCD_OPC_Decode, 137, 10, 148, 1, // Opcode: AE_S32RA64S_XC
4558
/* 6598 */    MCD_OPC_FilterValue, 134, 129, 12, 25, 0, 0, // Skip to: 6630
4559
/* 6605 */    MCD_OPC_CheckPredicate, 24, 236, 4, 0, // Skip to: 7870
4560
/* 6610 */    MCD_OPC_CheckField, 16, 14, 128, 64, 228, 4, 0, // Skip to: 7870
4561
/* 6618 */    MCD_OPC_CheckField, 0, 4, 14, 221, 4, 0, // Skip to: 7870
4562
/* 6625 */    MCD_OPC_Decode, 157, 10, 148, 1, // Opcode: AE_S32_L_XC
4563
/* 6630 */    MCD_OPC_FilterValue, 135, 129, 12, 71, 0, 0, // Skip to: 6708
4564
/* 6637 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4565
/* 6640 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6662
4566
/* 6645 */    MCD_OPC_CheckPredicate, 24, 196, 4, 0, // Skip to: 7870
4567
/* 6650 */    MCD_OPC_CheckField, 0, 4, 14, 189, 4, 0, // Skip to: 7870
4568
/* 6657 */    MCD_OPC_Decode, 161, 10, 153, 1, // Opcode: AE_S64_X
4569
/* 6662 */    MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6685
4570
/* 6668 */    MCD_OPC_CheckPredicate, 24, 173, 4, 0, // Skip to: 7870
4571
/* 6673 */    MCD_OPC_CheckField, 0, 4, 14, 166, 4, 0, // Skip to: 7870
4572
/* 6680 */    MCD_OPC_Decode, 162, 10, 148, 1, // Opcode: AE_S64_XC
4573
/* 6685 */    MCD_OPC_FilterValue, 128, 64, 155, 4, 0, // Skip to: 7870
4574
/* 6691 */    MCD_OPC_CheckPredicate, 24, 150, 4, 0, // Skip to: 7870
4575
/* 6696 */    MCD_OPC_CheckField, 0, 4, 14, 143, 4, 0, // Skip to: 7870
4576
/* 6703 */    MCD_OPC_Decode, 163, 10, 148, 1, // Opcode: AE_S64_XP
4577
/* 6708 */    MCD_OPC_FilterValue, 141, 129, 12, 49, 0, 0, // Skip to: 6764
4578
/* 6715 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4579
/* 6718 */    MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6741
4580
/* 6724 */    MCD_OPC_CheckPredicate, 24, 117, 4, 0, // Skip to: 7870
4581
/* 6729 */    MCD_OPC_CheckField, 0, 4, 14, 110, 4, 0, // Skip to: 7870
4582
/* 6736 */    MCD_OPC_Decode, 246, 9, 146, 1, // Opcode: AE_S24RA64S_I
4583
/* 6741 */    MCD_OPC_FilterValue, 128, 64, 99, 4, 0, // Skip to: 7870
4584
/* 6747 */    MCD_OPC_CheckPredicate, 24, 94, 4, 0, // Skip to: 7870
4585
/* 6752 */    MCD_OPC_CheckField, 0, 4, 14, 87, 4, 0, // Skip to: 7870
4586
/* 6759 */    MCD_OPC_Decode, 247, 9, 147, 1, // Opcode: AE_S24RA64S_IP
4587
/* 6764 */    MCD_OPC_FilterValue, 143, 129, 12, 48, 0, 0, // Skip to: 6819
4588
/* 6771 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4589
/* 6774 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6796
4590
/* 6779 */    MCD_OPC_CheckPredicate, 24, 62, 4, 0, // Skip to: 7870
4591
/* 6784 */    MCD_OPC_CheckField, 0, 4, 14, 55, 4, 0, // Skip to: 7870
4592
/* 6791 */    MCD_OPC_Decode, 134, 10, 146, 1, // Opcode: AE_S32RA64S_I
4593
/* 6796 */    MCD_OPC_FilterValue, 128, 32, 44, 4, 0, // Skip to: 7870
4594
/* 6802 */    MCD_OPC_CheckPredicate, 24, 39, 4, 0, // Skip to: 7870
4595
/* 6807 */    MCD_OPC_CheckField, 0, 4, 14, 32, 4, 0, // Skip to: 7870
4596
/* 6814 */    MCD_OPC_Decode, 135, 10, 147, 1, // Opcode: AE_S32RA64S_IP
4597
/* 6819 */    MCD_OPC_FilterValue, 148, 129, 12, 71, 0, 0, // Skip to: 6897
4598
/* 6826 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4599
/* 6829 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6851
4600
/* 6834 */    MCD_OPC_CheckPredicate, 24, 7, 4, 0, // Skip to: 7870
4601
/* 6839 */    MCD_OPC_CheckField, 0, 6, 30, 0, 4, 0, // Skip to: 7870
4602
/* 6846 */    MCD_OPC_Decode, 179, 10, 193, 1, // Opcode: AE_SA32X2F24_RIP
4603
/* 6851 */    MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6874
4604
/* 6857 */    MCD_OPC_CheckPredicate, 24, 240, 3, 0, // Skip to: 7870
4605
/* 6862 */    MCD_OPC_CheckField, 0, 6, 30, 233, 3, 0, // Skip to: 7870
4606
/* 6869 */    MCD_OPC_Decode, 180, 10, 193, 1, // Opcode: AE_SA32X2_IC
4607
/* 6874 */    MCD_OPC_FilterValue, 128, 96, 222, 3, 0, // Skip to: 7870
4608
/* 6880 */    MCD_OPC_CheckPredicate, 24, 217, 3, 0, // Skip to: 7870
4609
/* 6885 */    MCD_OPC_CheckField, 0, 6, 30, 210, 3, 0, // Skip to: 7870
4610
/* 6892 */    MCD_OPC_Decode, 182, 10, 193, 1, // Opcode: AE_SA32X2_RIC
4611
/* 6897 */    MCD_OPC_FilterValue, 149, 129, 12, 202, 0, 0, // Skip to: 7106
4612
/* 6904 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4613
/* 6907 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 6945
4614
/* 6912 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
4615
/* 6915 */    MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 6930
4616
/* 6920 */    MCD_OPC_CheckPredicate, 24, 177, 3, 0, // Skip to: 7870
4617
/* 6925 */    MCD_OPC_Decode, 183, 10, 193, 1, // Opcode: AE_SA32X2_RIP
4618
/* 6930 */    MCD_OPC_FilterValue, 46, 167, 3, 0, // Skip to: 7870
4619
/* 6935 */    MCD_OPC_CheckPredicate, 24, 162, 3, 0, // Skip to: 7870
4620
/* 6940 */    MCD_OPC_Decode, 194, 5, 194, 1, // Opcode: AE_LA24_RIP
4621
/* 6945 */    MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 6968
4622
/* 6951 */    MCD_OPC_CheckPredicate, 24, 146, 3, 0, // Skip to: 7870
4623
/* 6956 */    MCD_OPC_CheckField, 0, 6, 62, 139, 3, 0, // Skip to: 7870
4624
/* 6963 */    MCD_OPC_Decode, 197, 5, 194, 1, // Opcode: AE_LA32X2F24_RIC
4625
/* 6968 */    MCD_OPC_FilterValue, 128, 64, 40, 0, 0, // Skip to: 7014
4626
/* 6974 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
4627
/* 6977 */    MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 6999
4628
/* 6982 */    MCD_OPC_CheckPredicate, 24, 115, 3, 0, // Skip to: 7870
4629
/* 6987 */    MCD_OPC_CheckField, 6, 2, 3, 108, 3, 0, // Skip to: 7870
4630
/* 6994 */    MCD_OPC_Decode, 155, 5, 166, 1, // Opcode: AE_L32X2F24_RIC
4631
/* 6999 */    MCD_OPC_FilterValue, 46, 98, 3, 0, // Skip to: 7870
4632
/* 7004 */    MCD_OPC_CheckPredicate, 24, 93, 3, 0, // Skip to: 7870
4633
/* 7009 */    MCD_OPC_Decode, 198, 5, 194, 1, // Opcode: AE_LA32X2F24_RIP
4634
/* 7014 */    MCD_OPC_FilterValue, 128, 96, 82, 3, 0, // Skip to: 7870
4635
/* 7020 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
4636
/* 7023 */    MCD_OPC_FilterValue, 30, 63, 0, 0, // Skip to: 7091
4637
/* 7028 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
4638
/* 7031 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7046
4639
/* 7036 */    MCD_OPC_CheckPredicate, 24, 61, 3, 0, // Skip to: 7870
4640
/* 7041 */    MCD_OPC_Decode, 162, 5, 166, 1, // Opcode: AE_L32X2_RIC
4641
/* 7046 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7061
4642
/* 7051 */    MCD_OPC_CheckPredicate, 24, 46, 3, 0, // Skip to: 7870
4643
/* 7056 */    MCD_OPC_Decode, 141, 10, 195, 1, // Opcode: AE_S32X2F24_RIC
4644
/* 7061 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7076
4645
/* 7066 */    MCD_OPC_CheckPredicate, 24, 31, 3, 0, // Skip to: 7870
4646
/* 7071 */    MCD_OPC_Decode, 142, 10, 195, 1, // Opcode: AE_S32X2F24_RIP
4647
/* 7076 */    MCD_OPC_FilterValue, 3, 21, 3, 0, // Skip to: 7870
4648
/* 7081 */    MCD_OPC_CheckPredicate, 24, 16, 3, 0, // Skip to: 7870
4649
/* 7086 */    MCD_OPC_Decode, 149, 10, 195, 1, // Opcode: AE_S32X2_RIC
4650
/* 7091 */    MCD_OPC_FilterValue, 62, 6, 3, 0, // Skip to: 7870
4651
/* 7096 */    MCD_OPC_CheckPredicate, 24, 1, 3, 0, // Skip to: 7870
4652
/* 7101 */    MCD_OPC_Decode, 203, 5, 194, 1, // Opcode: AE_LA32X2_RIC
4653
/* 7106 */    MCD_OPC_FilterValue, 150, 129, 12, 142, 0, 0, // Skip to: 7255
4654
/* 7113 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4655
/* 7116 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 7154
4656
/* 7121 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
4657
/* 7124 */    MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 7139
4658
/* 7129 */    MCD_OPC_CheckPredicate, 24, 224, 2, 0, // Skip to: 7870
4659
/* 7134 */    MCD_OPC_Decode, 204, 5, 194, 1, // Opcode: AE_LA32X2_RIP
4660
/* 7139 */    MCD_OPC_FilterValue, 62, 214, 2, 0, // Skip to: 7870
4661
/* 7144 */    MCD_OPC_CheckPredicate, 24, 209, 2, 0, // Skip to: 7870
4662
/* 7149 */    MCD_OPC_Decode, 164, 10, 193, 1, // Opcode: AE_SA16X4_IC
4663
/* 7154 */    MCD_OPC_FilterValue, 128, 32, 17, 0, 0, // Skip to: 7177
4664
/* 7160 */    MCD_OPC_CheckPredicate, 24, 193, 2, 0, // Skip to: 7870
4665
/* 7165 */    MCD_OPC_CheckField, 0, 6, 62, 186, 2, 0, // Skip to: 7870
4666
/* 7172 */    MCD_OPC_Decode, 166, 10, 193, 1, // Opcode: AE_SA16X4_RIC
4667
/* 7177 */    MCD_OPC_FilterValue, 128, 64, 33, 0, 0, // Skip to: 7216
4668
/* 7183 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
4669
/* 7186 */    MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 7201
4670
/* 7191 */    MCD_OPC_CheckPredicate, 24, 162, 2, 0, // Skip to: 7870
4671
/* 7196 */    MCD_OPC_Decode, 167, 10, 193, 1, // Opcode: AE_SA16X4_RIP
4672
/* 7201 */    MCD_OPC_FilterValue, 62, 152, 2, 0, // Skip to: 7870
4673
/* 7206 */    MCD_OPC_CheckPredicate, 24, 147, 2, 0, // Skip to: 7870
4674
/* 7211 */    MCD_OPC_Decode, 168, 10, 193, 1, // Opcode: AE_SA24X2_IC
4675
/* 7216 */    MCD_OPC_FilterValue, 128, 96, 136, 2, 0, // Skip to: 7870
4676
/* 7222 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
4677
/* 7225 */    MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 7240
4678
/* 7230 */    MCD_OPC_CheckPredicate, 24, 123, 2, 0, // Skip to: 7870
4679
/* 7235 */    MCD_OPC_Decode, 169, 10, 193, 1, // Opcode: AE_SA24X2_IP
4680
/* 7240 */    MCD_OPC_FilterValue, 62, 113, 2, 0, // Skip to: 7870
4681
/* 7245 */    MCD_OPC_CheckPredicate, 24, 108, 2, 0, // Skip to: 7870
4682
/* 7250 */    MCD_OPC_Decode, 170, 10, 193, 1, // Opcode: AE_SA24X2_RIC
4683
/* 7255 */    MCD_OPC_FilterValue, 151, 129, 12, 142, 0, 0, // Skip to: 7404
4684
/* 7262 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4685
/* 7265 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 7303
4686
/* 7270 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
4687
/* 7273 */    MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 7288
4688
/* 7278 */    MCD_OPC_CheckPredicate, 24, 75, 2, 0, // Skip to: 7870
4689
/* 7283 */    MCD_OPC_Decode, 171, 10, 193, 1, // Opcode: AE_SA24X2_RIP
4690
/* 7288 */    MCD_OPC_FilterValue, 62, 65, 2, 0, // Skip to: 7870
4691
/* 7293 */    MCD_OPC_CheckPredicate, 24, 60, 2, 0, // Skip to: 7870
4692
/* 7298 */    MCD_OPC_Decode, 172, 10, 193, 1, // Opcode: AE_SA24_L_IC
4693
/* 7303 */    MCD_OPC_FilterValue, 128, 32, 33, 0, 0, // Skip to: 7342
4694
/* 7309 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
4695
/* 7312 */    MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 7327
4696
/* 7317 */    MCD_OPC_CheckPredicate, 24, 36, 2, 0, // Skip to: 7870
4697
/* 7322 */    MCD_OPC_Decode, 173, 10, 193, 1, // Opcode: AE_SA24_L_IP
4698
/* 7327 */    MCD_OPC_FilterValue, 62, 26, 2, 0, // Skip to: 7870
4699
/* 7332 */    MCD_OPC_CheckPredicate, 24, 21, 2, 0, // Skip to: 7870
4700
/* 7337 */    MCD_OPC_Decode, 174, 10, 193, 1, // Opcode: AE_SA24_L_RIC
4701
/* 7342 */    MCD_OPC_FilterValue, 128, 64, 33, 0, 0, // Skip to: 7381
4702
/* 7348 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
4703
/* 7351 */    MCD_OPC_FilterValue, 46, 10, 0, 0, // Skip to: 7366
4704
/* 7356 */    MCD_OPC_CheckPredicate, 24, 253, 1, 0, // Skip to: 7870
4705
/* 7361 */    MCD_OPC_Decode, 175, 10, 193, 1, // Opcode: AE_SA24_L_RIP
4706
/* 7366 */    MCD_OPC_FilterValue, 62, 243, 1, 0, // Skip to: 7870
4707
/* 7371 */    MCD_OPC_CheckPredicate, 24, 238, 1, 0, // Skip to: 7870
4708
/* 7376 */    MCD_OPC_Decode, 176, 10, 193, 1, // Opcode: AE_SA32X2F24_IC
4709
/* 7381 */    MCD_OPC_FilterValue, 128, 96, 227, 1, 0, // Skip to: 7870
4710
/* 7387 */    MCD_OPC_CheckPredicate, 24, 222, 1, 0, // Skip to: 7870
4711
/* 7392 */    MCD_OPC_CheckField, 0, 6, 62, 215, 1, 0, // Skip to: 7870
4712
/* 7399 */    MCD_OPC_Decode, 178, 10, 193, 1, // Opcode: AE_SA32X2F24_RIC
4713
/* 7404 */    MCD_OPC_FilterValue, 152, 129, 12, 26, 1, 0, // Skip to: 7693
4714
/* 7411 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
4715
/* 7414 */    MCD_OPC_FilterValue, 14, 57, 0, 0, // Skip to: 7476
4716
/* 7419 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4717
/* 7422 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 7460
4718
/* 7427 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
4719
/* 7430 */    MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7445
4720
/* 7435 */    MCD_OPC_CheckPredicate, 24, 174, 1, 0, // Skip to: 7870
4721
/* 7440 */    MCD_OPC_Decode, 177, 5, 196, 1, // Opcode: AE_LA16X4NEG_PC
4722
/* 7445 */    MCD_OPC_FilterValue, 7, 164, 1, 0, // Skip to: 7870
4723
/* 7450 */    MCD_OPC_CheckPredicate, 24, 159, 1, 0, // Skip to: 7870
4724
/* 7455 */    MCD_OPC_Decode, 185, 5, 196, 1, // Opcode: AE_LA24X2NEG_PC
4725
/* 7460 */    MCD_OPC_FilterValue, 128, 96, 148, 1, 0, // Skip to: 7870
4726
/* 7466 */    MCD_OPC_CheckPredicate, 24, 143, 1, 0, // Skip to: 7870
4727
/* 7471 */    MCD_OPC_Decode, 190, 5, 194, 1, // Opcode: AE_LA24X2_RIP
4728
/* 7476 */    MCD_OPC_FilterValue, 30, 57, 0, 0, // Skip to: 7538
4729
/* 7481 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4730
/* 7484 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 7522
4731
/* 7489 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
4732
/* 7492 */    MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7507
4733
/* 7497 */    MCD_OPC_CheckPredicate, 24, 112, 1, 0, // Skip to: 7870
4734
/* 7502 */    MCD_OPC_Decode, 183, 5, 196, 1, // Opcode: AE_LA24NEG_PC
4735
/* 7507 */    MCD_OPC_FilterValue, 7, 102, 1, 0, // Skip to: 7870
4736
/* 7512 */    MCD_OPC_CheckPredicate, 24, 97, 1, 0, // Skip to: 7870
4737
/* 7517 */    MCD_OPC_Decode, 199, 5, 196, 1, // Opcode: AE_LA32X2NEG_PC
4738
/* 7522 */    MCD_OPC_FilterValue, 128, 96, 86, 1, 0, // Skip to: 7870
4739
/* 7528 */    MCD_OPC_CheckPredicate, 24, 81, 1, 0, // Skip to: 7870
4740
/* 7533 */    MCD_OPC_Decode, 192, 5, 194, 1, // Opcode: AE_LA24_IP
4741
/* 7538 */    MCD_OPC_FilterValue, 46, 72, 0, 0, // Skip to: 7615
4742
/* 7543 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4743
/* 7546 */    MCD_OPC_FilterValue, 0, 48, 0, 0, // Skip to: 7599
4744
/* 7551 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
4745
/* 7554 */    MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7569
4746
/* 7559 */    MCD_OPC_CheckPredicate, 24, 50, 1, 0, // Skip to: 7870
4747
/* 7564 */    MCD_OPC_Decode, 178, 5, 196, 1, // Opcode: AE_LA16X4POS_PC
4748
/* 7569 */    MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 7584
4749
/* 7574 */    MCD_OPC_CheckPredicate, 24, 35, 1, 0, // Skip to: 7870
4750
/* 7579 */    MCD_OPC_Decode, 186, 5, 196, 1, // Opcode: AE_LA24X2POS_PC
4751
/* 7584 */    MCD_OPC_FilterValue, 11, 25, 1, 0, // Skip to: 7870
4752
/* 7589 */    MCD_OPC_CheckPredicate, 24, 20, 1, 0, // Skip to: 7870
4753
/* 7594 */    MCD_OPC_Decode, 184, 10, 197, 1, // Opcode: AE_SA64NEG_FP
4754
/* 7599 */    MCD_OPC_FilterValue, 128, 96, 9, 1, 0, // Skip to: 7870
4755
/* 7605 */    MCD_OPC_CheckPredicate, 24, 4, 1, 0, // Skip to: 7870
4756
/* 7610 */    MCD_OPC_Decode, 191, 5, 194, 1, // Opcode: AE_LA24_IC
4757
/* 7615 */    MCD_OPC_FilterValue, 62, 250, 0, 0, // Skip to: 7870
4758
/* 7620 */    MCD_OPC_ExtractField, 16, 14,  // Inst{29-16} ...
4759
/* 7623 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7645
4760
/* 7628 */    MCD_OPC_CheckPredicate, 24, 237, 0, 0, // Skip to: 7870
4761
/* 7633 */    MCD_OPC_CheckField, 12, 4, 3, 230, 0, 0, // Skip to: 7870
4762
/* 7640 */    MCD_OPC_Decode, 184, 5, 196, 1, // Opcode: AE_LA24POS_PC
4763
/* 7645 */    MCD_OPC_FilterValue, 128, 32, 10, 0, 0, // Skip to: 7661
4764
/* 7651 */    MCD_OPC_CheckPredicate, 24, 214, 0, 0, // Skip to: 7870
4765
/* 7656 */    MCD_OPC_Decode, 181, 5, 194, 1, // Opcode: AE_LA16X4_RIC
4766
/* 7661 */    MCD_OPC_FilterValue, 128, 64, 10, 0, 0, // Skip to: 7677
4767
/* 7667 */    MCD_OPC_CheckPredicate, 24, 198, 0, 0, // Skip to: 7870
4768
/* 7672 */    MCD_OPC_Decode, 189, 5, 194, 1, // Opcode: AE_LA24X2_RIC
4769
/* 7677 */    MCD_OPC_FilterValue, 128, 96, 187, 0, 0, // Skip to: 7870
4770
/* 7683 */    MCD_OPC_CheckPredicate, 24, 182, 0, 0, // Skip to: 7870
4771
/* 7688 */    MCD_OPC_Decode, 193, 5, 194, 1, // Opcode: AE_LA24_RIC
4772
/* 7693 */    MCD_OPC_FilterValue, 153, 129, 12, 47, 0, 0, // Skip to: 7747
4773
/* 7700 */    MCD_OPC_ExtractField, 12, 16,  // Inst{27-12} ...
4774
/* 7703 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7725
4775
/* 7708 */    MCD_OPC_CheckPredicate, 24, 157, 0, 0, // Skip to: 7870
4776
/* 7713 */    MCD_OPC_CheckField, 0, 4, 14, 150, 0, 0, // Skip to: 7870
4777
/* 7720 */    MCD_OPC_Decode, 206, 5, 198, 1, // Opcode: AE_LALIGN64_I
4778
/* 7725 */    MCD_OPC_FilterValue, 4, 140, 0, 0, // Skip to: 7870
4779
/* 7730 */    MCD_OPC_CheckPredicate, 24, 135, 0, 0, // Skip to: 7870
4780
/* 7735 */    MCD_OPC_CheckField, 0, 4, 14, 128, 0, 0, // Skip to: 7870
4781
/* 7742 */    MCD_OPC_Decode, 186, 10, 198, 1, // Opcode: AE_SALIGN64_I
4782
/* 7747 */    MCD_OPC_FilterValue, 154, 129, 12, 31, 0, 0, // Skip to: 7785
4783
/* 7754 */    MCD_OPC_CheckPredicate, 24, 111, 0, 0, // Skip to: 7870
4784
/* 7759 */    MCD_OPC_CheckField, 16, 14, 0, 104, 0, 0, // Skip to: 7870
4785
/* 7766 */    MCD_OPC_CheckField, 8, 4, 8, 97, 0, 0, // Skip to: 7870
4786
/* 7773 */    MCD_OPC_CheckField, 0, 4, 14, 90, 0, 0, // Skip to: 7870
4787
/* 7780 */    MCD_OPC_Decode, 229, 5, 199, 1, // Opcode: AE_MOVAD16_1
4788
/* 7785 */    MCD_OPC_FilterValue, 128, 208, 14, 24, 0, 0, // Skip to: 7816
4789
/* 7792 */    MCD_OPC_CheckPredicate, 24, 73, 0, 0, // Skip to: 7870
4790
/* 7797 */    MCD_OPC_CheckField, 28, 2, 0, 66, 0, 0, // Skip to: 7870
4791
/* 7804 */    MCD_OPC_CheckField, 0, 16, 14, 59, 0, 0, // Skip to: 7870
4792
/* 7811 */    MCD_OPC_Decode, 224, 4, 200, 1, // Opcode: AE_ADDBRBA32
4793
/* 7816 */    MCD_OPC_FilterValue, 128, 226, 15, 47, 0, 0, // Skip to: 7870
4794
/* 7823 */    MCD_OPC_ExtractField, 24, 6,  // Inst{29-24} ...
4795
/* 7826 */    MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 7848
4796
/* 7831 */    MCD_OPC_CheckPredicate, 24, 34, 0, 0, // Skip to: 7870
4797
/* 7836 */    MCD_OPC_CheckField, 0, 16, 14, 27, 0, 0, // Skip to: 7870
4798
/* 7843 */    MCD_OPC_Decode, 231, 4, 201, 1, // Opcode: AE_CVT64A32
4799
/* 7848 */    MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 7870
4800
/* 7853 */    MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 7870
4801
/* 7858 */    MCD_OPC_CheckField, 0, 16, 14, 5, 0, 0, // Skip to: 7870
4802
/* 7865 */    MCD_OPC_Decode, 235, 4, 201, 1, // Opcode: AE_CVTQ56A32S
4803
/* 7870 */    MCD_OPC_Fail,
4804
  0
4805
};
4806
4807
static const uint8_t DecoderTableHIFI364[] = {
4808
/* 0 */       MCD_OPC_ExtractField, 58, 6,  // Inst{63-58} ...
4809
/* 3 */       MCD_OPC_FilterValue, 0, 98, 10, 0, // Skip to: 2666
4810
/* 8 */       MCD_OPC_ExtractField, 50, 8,  // Inst{57-50} ...
4811
/* 11 */      MCD_OPC_FilterValue, 0, 70, 1, 0, // Skip to: 342
4812
/* 16 */      MCD_OPC_ExtractField, 0, 8,  // Inst{7-0} ...
4813
/* 19 */      MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 55
4814
/* 24 */      MCD_OPC_CheckPredicate, 24, 76, 51, 0, // Skip to: 13161
4815
/* 29 */      MCD_OPC_CheckField, 40, 10, 0, 69, 51, 0, // Skip to: 13161
4816
/* 36 */      MCD_OPC_CheckField, 28, 4, 0, 62, 51, 0, // Skip to: 13161
4817
/* 43 */      MCD_OPC_CheckField, 8, 8, 0, 55, 51, 0, // Skip to: 13161
4818
/* 50 */      MCD_OPC_Decode, 238, 6, 202, 1, // Opcode: AE_MULAFD24X2_FIR_H
4819
/* 55 */      MCD_OPC_FilterValue, 15, 38, 0, 0, // Skip to: 98
4820
/* 60 */      MCD_OPC_CheckPredicate, 24, 40, 51, 0, // Skip to: 13161
4821
/* 65 */      MCD_OPC_CheckField, 36, 12, 0, 33, 51, 0, // Skip to: 13161
4822
/* 72 */      MCD_OPC_CheckField, 28, 4, 0, 26, 51, 0, // Skip to: 13161
4823
/* 79 */      MCD_OPC_CheckField, 20, 4, 0, 19, 51, 0, // Skip to: 13161
4824
/* 86 */      MCD_OPC_CheckField, 8, 8, 0, 12, 51, 0, // Skip to: 13161
4825
/* 93 */      MCD_OPC_Decode, 201, 10, 203, 1, // Opcode: AE_SEL16I_N
4826
/* 98 */      MCD_OPC_FilterValue, 47, 41, 0, 0, // Skip to: 144
4827
/* 103 */     MCD_OPC_ExtractField, 16, 34,  // Inst{49-16} ...
4828
/* 106 */     MCD_OPC_FilterValue, 128, 128, 128, 192, 12, 10, 0, 0, // Skip to: 125
4829
/* 115 */     MCD_OPC_CheckPredicate, 24, 241, 50, 0, // Skip to: 13161
4830
/* 120 */     MCD_OPC_Decode, 233, 4, 158, 1, // Opcode: AE_CVTA32F24S_H
4831
/* 125 */     MCD_OPC_FilterValue, 128, 128, 128, 200, 13, 227, 50, 0, // Skip to: 13161
4832
/* 134 */     MCD_OPC_CheckPredicate, 24, 222, 50, 0, // Skip to: 13161
4833
/* 139 */     MCD_OPC_Decode, 133, 5, 166, 1, // Opcode: AE_L16X4_RIC
4834
/* 144 */     MCD_OPC_FilterValue, 63, 21, 0, 0, // Skip to: 170
4835
/* 149 */     MCD_OPC_CheckPredicate, 24, 207, 50, 0, // Skip to: 13161
4836
/* 154 */     MCD_OPC_CheckField, 16, 34, 128, 128, 128, 200, 12, 196, 50, 0, // Skip to: 13161
4837
/* 165 */     MCD_OPC_Decode, 228, 4, 156, 1, // Opcode: AE_CVT32X2F16_10
4838
/* 170 */     MCD_OPC_FilterValue, 95, 21, 0, 0, // Skip to: 196
4839
/* 175 */     MCD_OPC_CheckPredicate, 24, 181, 50, 0, // Skip to: 13161
4840
/* 180 */     MCD_OPC_CheckField, 16, 34, 128, 128, 128, 200, 13, 170, 50, 0, // Skip to: 13161
4841
/* 191 */     MCD_OPC_Decode, 236, 9, 195, 1, // Opcode: AE_S16X4_RIC
4842
/* 196 */     MCD_OPC_FilterValue, 111, 41, 0, 0, // Skip to: 242
4843
/* 201 */     MCD_OPC_ExtractField, 16, 34,  // Inst{49-16} ...
4844
/* 204 */     MCD_OPC_FilterValue, 128, 128, 128, 192, 12, 10, 0, 0, // Skip to: 223
4845
/* 213 */     MCD_OPC_CheckPredicate, 24, 143, 50, 0, // Skip to: 13161
4846
/* 218 */     MCD_OPC_Decode, 234, 4, 158, 1, // Opcode: AE_CVTA32F24S_L
4847
/* 223 */     MCD_OPC_FilterValue, 128, 128, 128, 200, 13, 129, 50, 0, // Skip to: 13161
4848
/* 232 */     MCD_OPC_CheckPredicate, 24, 124, 50, 0, // Skip to: 13161
4849
/* 237 */     MCD_OPC_Decode, 134, 5, 166, 1, // Opcode: AE_L16X4_RIP
4850
/* 242 */     MCD_OPC_FilterValue, 127, 41, 0, 0, // Skip to: 288
4851
/* 247 */     MCD_OPC_ExtractField, 16, 34,  // Inst{49-16} ...
4852
/* 250 */     MCD_OPC_FilterValue, 128, 128, 128, 200, 12, 10, 0, 0, // Skip to: 269
4853
/* 259 */     MCD_OPC_CheckPredicate, 24, 97, 50, 0, // Skip to: 13161
4854
/* 264 */     MCD_OPC_Decode, 229, 4, 156, 1, // Opcode: AE_CVT32X2F16_32
4855
/* 269 */     MCD_OPC_FilterValue, 128, 128, 128, 200, 13, 83, 50, 0, // Skip to: 13161
4856
/* 278 */     MCD_OPC_CheckPredicate, 24, 78, 50, 0, // Skip to: 13161
4857
/* 283 */     MCD_OPC_Decode, 237, 9, 195, 1, // Opcode: AE_S16X4_RIP
4858
/* 288 */     MCD_OPC_FilterValue, 239, 1, 21, 0, 0, // Skip to: 315
4859
/* 294 */     MCD_OPC_CheckPredicate, 24, 62, 50, 0, // Skip to: 13161
4860
/* 299 */     MCD_OPC_CheckField, 16, 34, 128, 128, 128, 200, 12, 51, 50, 0, // Skip to: 13161
4861
/* 310 */     MCD_OPC_Decode, 203, 10, 156, 1, // Opcode: AE_SEXT32X2D16_10
4862
/* 315 */     MCD_OPC_FilterValue, 255, 1, 40, 50, 0, // Skip to: 13161
4863
/* 321 */     MCD_OPC_CheckPredicate, 24, 35, 50, 0, // Skip to: 13161
4864
/* 326 */     MCD_OPC_CheckField, 16, 34, 128, 128, 128, 200, 13, 24, 50, 0, // Skip to: 13161
4865
/* 337 */     MCD_OPC_Decode, 150, 10, 195, 1, // Opcode: AE_S32X2_RIP
4866
/* 342 */     MCD_OPC_FilterValue, 7, 76, 0, 0, // Skip to: 423
4867
/* 347 */     MCD_OPC_ExtractField, 36, 14,  // Inst{49-36} ...
4868
/* 350 */     MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 386
4869
/* 355 */     MCD_OPC_CheckPredicate, 24, 1, 50, 0, // Skip to: 13161
4870
/* 360 */     MCD_OPC_CheckField, 28, 4, 0, 250, 49, 0, // Skip to: 13161
4871
/* 367 */     MCD_OPC_CheckField, 20, 4, 0, 243, 49, 0, // Skip to: 13161
4872
/* 374 */     MCD_OPC_CheckField, 0, 16, 15, 236, 49, 0, // Skip to: 13161
4873
/* 381 */     MCD_OPC_Decode, 162, 6, 204, 1, // Opcode: AE_MULAAD24_HH_LL
4874
/* 386 */     MCD_OPC_FilterValue, 128, 32, 225, 49, 0, // Skip to: 13161
4875
/* 392 */     MCD_OPC_CheckPredicate, 24, 220, 49, 0, // Skip to: 13161
4876
/* 397 */     MCD_OPC_CheckField, 28, 4, 0, 213, 49, 0, // Skip to: 13161
4877
/* 404 */     MCD_OPC_CheckField, 20, 4, 0, 206, 49, 0, // Skip to: 13161
4878
/* 411 */     MCD_OPC_CheckField, 0, 16, 15, 199, 49, 0, // Skip to: 13161
4879
/* 418 */     MCD_OPC_Decode, 164, 6, 204, 1, // Opcode: AE_MULAAD24_HL_LH
4880
/* 423 */     MCD_OPC_FilterValue, 9, 77, 0, 0, // Skip to: 505
4881
/* 428 */     MCD_OPC_ExtractField, 36, 14,  // Inst{49-36} ...
4882
/* 431 */     MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 468
4883
/* 437 */     MCD_OPC_CheckPredicate, 24, 175, 49, 0, // Skip to: 13161
4884
/* 442 */     MCD_OPC_CheckField, 28, 4, 0, 168, 49, 0, // Skip to: 13161
4885
/* 449 */     MCD_OPC_CheckField, 20, 4, 0, 161, 49, 0, // Skip to: 13161
4886
/* 456 */     MCD_OPC_CheckField, 0, 16, 15, 154, 49, 0, // Skip to: 13161
4887
/* 463 */     MCD_OPC_Decode, 180, 6, 204, 1, // Opcode: AE_MULAAFD24_HH_LL
4888
/* 468 */     MCD_OPC_FilterValue, 128, 64, 143, 49, 0, // Skip to: 13161
4889
/* 474 */     MCD_OPC_CheckPredicate, 24, 138, 49, 0, // Skip to: 13161
4890
/* 479 */     MCD_OPC_CheckField, 28, 4, 0, 131, 49, 0, // Skip to: 13161
4891
/* 486 */     MCD_OPC_CheckField, 20, 4, 0, 124, 49, 0, // Skip to: 13161
4892
/* 493 */     MCD_OPC_CheckField, 0, 16, 15, 117, 49, 0, // Skip to: 13161
4893
/* 500 */     MCD_OPC_Decode, 182, 6, 204, 1, // Opcode: AE_MULAAFD24_HL_LH
4894
/* 505 */     MCD_OPC_FilterValue, 10, 39, 0, 0, // Skip to: 549
4895
/* 510 */     MCD_OPC_CheckPredicate, 24, 102, 49, 0, // Skip to: 13161
4896
/* 515 */     MCD_OPC_CheckField, 36, 14, 128, 96, 94, 49, 0, // Skip to: 13161
4897
/* 523 */     MCD_OPC_CheckField, 28, 4, 0, 87, 49, 0, // Skip to: 13161
4898
/* 530 */     MCD_OPC_CheckField, 20, 4, 0, 80, 49, 0, // Skip to: 13161
4899
/* 537 */     MCD_OPC_CheckField, 0, 16, 15, 73, 49, 0, // Skip to: 13161
4900
/* 544 */     MCD_OPC_Decode, 192, 6, 204, 1, // Opcode: AE_MULAC24
4901
/* 549 */     MCD_OPC_FilterValue, 18, 39, 0, 0, // Skip to: 593
4902
/* 554 */     MCD_OPC_CheckPredicate, 24, 58, 49, 0, // Skip to: 13161
4903
/* 559 */     MCD_OPC_CheckField, 36, 14, 128, 64, 50, 49, 0, // Skip to: 13161
4904
/* 567 */     MCD_OPC_CheckField, 28, 4, 0, 43, 49, 0, // Skip to: 13161
4905
/* 574 */     MCD_OPC_CheckField, 20, 4, 0, 36, 49, 0, // Skip to: 13161
4906
/* 581 */     MCD_OPC_CheckField, 0, 16, 15, 29, 49, 0, // Skip to: 13161
4907
/* 588 */     MCD_OPC_Decode, 132, 7, 204, 1, // Opcode: AE_MULAP24X2
4908
/* 593 */     MCD_OPC_FilterValue, 20, 77, 0, 0, // Skip to: 675
4909
/* 598 */     MCD_OPC_ExtractField, 36, 14,  // Inst{49-36} ...
4910
/* 601 */     MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 638
4911
/* 607 */     MCD_OPC_CheckPredicate, 24, 5, 49, 0, // Skip to: 13161
4912
/* 612 */     MCD_OPC_CheckField, 28, 4, 0, 254, 48, 0, // Skip to: 13161
4913
/* 619 */     MCD_OPC_CheckField, 20, 4, 0, 247, 48, 0, // Skip to: 13161
4914
/* 626 */     MCD_OPC_CheckField, 0, 16, 15, 240, 48, 0, // Skip to: 13161
4915
/* 633 */     MCD_OPC_Decode, 147, 7, 204, 1, // Opcode: AE_MULASD24_HH_LL
4916
/* 638 */     MCD_OPC_FilterValue, 128, 64, 229, 48, 0, // Skip to: 13161
4917
/* 644 */     MCD_OPC_CheckPredicate, 24, 224, 48, 0, // Skip to: 13161
4918
/* 649 */     MCD_OPC_CheckField, 28, 4, 0, 217, 48, 0, // Skip to: 13161
4919
/* 656 */     MCD_OPC_CheckField, 20, 4, 0, 210, 48, 0, // Skip to: 13161
4920
/* 663 */     MCD_OPC_CheckField, 0, 16, 15, 203, 48, 0, // Skip to: 13161
4921
/* 670 */     MCD_OPC_Decode, 149, 7, 204, 1, // Opcode: AE_MULASD24_HL_LH
4922
/* 675 */     MCD_OPC_FilterValue, 21, 77, 0, 0, // Skip to: 757
4923
/* 680 */     MCD_OPC_ExtractField, 36, 14,  // Inst{49-36} ...
4924
/* 683 */     MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 720
4925
/* 689 */     MCD_OPC_CheckPredicate, 24, 179, 48, 0, // Skip to: 13161
4926
/* 694 */     MCD_OPC_CheckField, 28, 4, 0, 172, 48, 0, // Skip to: 13161
4927
/* 701 */     MCD_OPC_CheckField, 20, 4, 0, 165, 48, 0, // Skip to: 13161
4928
/* 708 */     MCD_OPC_CheckField, 0, 16, 15, 158, 48, 0, // Skip to: 13161
4929
/* 715 */     MCD_OPC_Decode, 155, 7, 204, 1, // Opcode: AE_MULASFD24_HH_LL
4930
/* 720 */     MCD_OPC_FilterValue, 128, 64, 147, 48, 0, // Skip to: 13161
4931
/* 726 */     MCD_OPC_CheckPredicate, 24, 142, 48, 0, // Skip to: 13161
4932
/* 731 */     MCD_OPC_CheckField, 28, 4, 0, 135, 48, 0, // Skip to: 13161
4933
/* 738 */     MCD_OPC_CheckField, 20, 4, 0, 128, 48, 0, // Skip to: 13161
4934
/* 745 */     MCD_OPC_CheckField, 0, 16, 15, 121, 48, 0, // Skip to: 13161
4935
/* 752 */     MCD_OPC_Decode, 157, 7, 204, 1, // Opcode: AE_MULASFD24_HL_LH
4936
/* 757 */     MCD_OPC_FilterValue, 22, 39, 0, 0, // Skip to: 801
4937
/* 762 */     MCD_OPC_CheckPredicate, 24, 106, 48, 0, // Skip to: 13161
4938
/* 767 */     MCD_OPC_CheckField, 36, 14, 128, 32, 98, 48, 0, // Skip to: 13161
4939
/* 775 */     MCD_OPC_CheckField, 28, 4, 0, 91, 48, 0, // Skip to: 13161
4940
/* 782 */     MCD_OPC_CheckField, 20, 4, 0, 84, 48, 0, // Skip to: 13161
4941
/* 789 */     MCD_OPC_CheckField, 0, 16, 15, 77, 48, 0, // Skip to: 13161
4942
/* 796 */     MCD_OPC_Decode, 163, 7, 205, 1, // Opcode: AE_MULC24
4943
/* 801 */     MCD_OPC_FilterValue, 30, 39, 0, 0, // Skip to: 845
4944
/* 806 */     MCD_OPC_CheckPredicate, 24, 62, 48, 0, // Skip to: 13161
4945
/* 811 */     MCD_OPC_CheckField, 36, 14, 128, 64, 54, 48, 0, // Skip to: 13161
4946
/* 819 */     MCD_OPC_CheckField, 28, 4, 0, 47, 48, 0, // Skip to: 13161
4947
/* 826 */     MCD_OPC_CheckField, 20, 4, 0, 40, 48, 0, // Skip to: 13161
4948
/* 833 */     MCD_OPC_CheckField, 0, 16, 15, 33, 48, 0, // Skip to: 13161
4949
/* 840 */     MCD_OPC_Decode, 233, 7, 205, 1, // Opcode: AE_MULP24X2
4950
/* 845 */     MCD_OPC_FilterValue, 32, 9, 1, 0, // Skip to: 1115
4951
/* 850 */     MCD_OPC_ExtractField, 32, 18,  // Inst{49-32} ...
4952
/* 853 */     MCD_OPC_FilterValue, 128, 4, 24, 0, 0, // Skip to: 883
4953
/* 859 */     MCD_OPC_CheckPredicate, 24, 9, 48, 0, // Skip to: 13161
4954
/* 864 */     MCD_OPC_CheckField, 16, 12, 0, 2, 48, 0, // Skip to: 13161
4955
/* 871 */     MCD_OPC_CheckField, 0, 4, 14, 251, 47, 0, // Skip to: 13161
4956
/* 878 */     MCD_OPC_Decode, 134, 11, 206, 1, // Opcode: AE_TRUNCA32F64S_L
4957
/* 883 */     MCD_OPC_FilterValue, 128, 14, 24, 0, 0, // Skip to: 913
4958
/* 889 */     MCD_OPC_CheckPredicate, 24, 235, 47, 0, // Skip to: 13161
4959
/* 894 */     MCD_OPC_CheckField, 16, 12, 0, 228, 47, 0, // Skip to: 13161
4960
/* 901 */     MCD_OPC_CheckField, 0, 4, 14, 221, 47, 0, // Skip to: 13161
4961
/* 908 */     MCD_OPC_Decode, 136, 11, 207, 1, // Opcode: AE_TRUNCI32F64S_L
4962
/* 913 */     MCD_OPC_FilterValue, 128, 16, 24, 0, 0, // Skip to: 943
4963
/* 919 */     MCD_OPC_CheckPredicate, 24, 205, 47, 0, // Skip to: 13161
4964
/* 924 */     MCD_OPC_CheckField, 16, 12, 0, 198, 47, 0, // Skip to: 13161
4965
/* 931 */     MCD_OPC_CheckField, 0, 4, 14, 191, 47, 0, // Skip to: 13161
4966
/* 938 */     MCD_OPC_Decode, 137, 11, 207, 1, // Opcode: AE_TRUNCI32X2F64S
4967
/* 943 */     MCD_OPC_FilterValue, 128, 24, 47, 0, 0, // Skip to: 996
4968
/* 949 */     MCD_OPC_ExtractField, 12, 16,  // Inst{27-12} ...
4969
/* 952 */     MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 974
4970
/* 957 */     MCD_OPC_CheckPredicate, 24, 167, 47, 0, // Skip to: 13161
4971
/* 962 */     MCD_OPC_CheckField, 0, 4, 14, 160, 47, 0, // Skip to: 13161
4972
/* 969 */     MCD_OPC_Decode, 211, 10, 208, 1, // Opcode: AE_SLAA64S
4973
/* 974 */     MCD_OPC_FilterValue, 15, 150, 47, 0, // Skip to: 13161
4974
/* 979 */     MCD_OPC_CheckPredicate, 24, 145, 47, 0, // Skip to: 13161
4975
/* 984 */     MCD_OPC_CheckField, 0, 4, 14, 138, 47, 0, // Skip to: 13161
4976
/* 991 */     MCD_OPC_Decode, 229, 10, 208, 1, // Opcode: AE_SRA64_32
4977
/* 996 */     MCD_OPC_FilterValue, 128, 50, 127, 47, 0, // Skip to: 13161
4978
/* 1002 */    MCD_OPC_ExtractField, 12, 16,  // Inst{27-12} ...
4979
/* 1005 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1027
4980
/* 1010 */    MCD_OPC_CheckPredicate, 24, 114, 47, 0, // Skip to: 13161
4981
/* 1015 */    MCD_OPC_CheckField, 0, 4, 14, 107, 47, 0, // Skip to: 13161
4982
/* 1022 */    MCD_OPC_Decode, 230, 10, 208, 1, // Opcode: AE_SRAA16RS
4983
/* 1027 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1049
4984
/* 1032 */    MCD_OPC_CheckPredicate, 24, 92, 47, 0, // Skip to: 13161
4985
/* 1037 */    MCD_OPC_CheckField, 0, 4, 14, 85, 47, 0, // Skip to: 13161
4986
/* 1044 */    MCD_OPC_Decode, 246, 10, 208, 1, // Opcode: AE_SRLA64
4987
/* 1049 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1071
4988
/* 1054 */    MCD_OPC_CheckPredicate, 24, 70, 47, 0, // Skip to: 13161
4989
/* 1059 */    MCD_OPC_CheckField, 0, 4, 14, 63, 47, 0, // Skip to: 13161
4990
/* 1066 */    MCD_OPC_Decode, 231, 10, 208, 1, // Opcode: AE_SRAA16S
4991
/* 1071 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 1093
4992
/* 1076 */    MCD_OPC_CheckPredicate, 24, 48, 47, 0, // Skip to: 13161
4993
/* 1081 */    MCD_OPC_CheckField, 0, 4, 14, 41, 47, 0, // Skip to: 13161
4994
/* 1088 */    MCD_OPC_Decode, 233, 10, 208, 1, // Opcode: AE_SRAA32RS
4995
/* 1093 */    MCD_OPC_FilterValue, 14, 31, 47, 0, // Skip to: 13161
4996
/* 1098 */    MCD_OPC_CheckPredicate, 24, 26, 47, 0, // Skip to: 13161
4997
/* 1103 */    MCD_OPC_CheckField, 0, 4, 14, 19, 47, 0, // Skip to: 13161
4998
/* 1110 */    MCD_OPC_Decode, 245, 10, 208, 1, // Opcode: AE_SRLA32
4999
/* 1115 */    MCD_OPC_FilterValue, 35, 77, 0, 0, // Skip to: 1197
5000
/* 1120 */    MCD_OPC_ExtractField, 36, 14,  // Inst{49-36} ...
5001
/* 1123 */    MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 1160
5002
/* 1129 */    MCD_OPC_CheckPredicate, 24, 251, 46, 0, // Skip to: 13161
5003
/* 1134 */    MCD_OPC_CheckField, 28, 4, 0, 244, 46, 0, // Skip to: 13161
5004
/* 1141 */    MCD_OPC_CheckField, 20, 4, 0, 237, 46, 0, // Skip to: 13161
5005
/* 1148 */    MCD_OPC_CheckField, 0, 16, 15, 230, 46, 0, // Skip to: 13161
5006
/* 1155 */    MCD_OPC_Decode, 141, 8, 204, 1, // Opcode: AE_MULSAD24_HH_LL
5007
/* 1160 */    MCD_OPC_FilterValue, 128, 64, 219, 46, 0, // Skip to: 13161
5008
/* 1166 */    MCD_OPC_CheckPredicate, 24, 214, 46, 0, // Skip to: 13161
5009
/* 1171 */    MCD_OPC_CheckField, 28, 4, 0, 207, 46, 0, // Skip to: 13161
5010
/* 1178 */    MCD_OPC_CheckField, 20, 4, 0, 200, 46, 0, // Skip to: 13161
5011
/* 1185 */    MCD_OPC_CheckField, 0, 16, 15, 193, 46, 0, // Skip to: 13161
5012
/* 1192 */    MCD_OPC_Decode, 147, 8, 204, 1, // Opcode: AE_MULSAFD24_HH_LL
5013
/* 1197 */    MCD_OPC_FilterValue, 42, 39, 0, 0, // Skip to: 1241
5014
/* 1202 */    MCD_OPC_CheckPredicate, 24, 178, 46, 0, // Skip to: 13161
5015
/* 1207 */    MCD_OPC_CheckField, 36, 14, 128, 64, 170, 46, 0, // Skip to: 13161
5016
/* 1215 */    MCD_OPC_CheckField, 28, 4, 0, 163, 46, 0, // Skip to: 13161
5017
/* 1222 */    MCD_OPC_CheckField, 20, 4, 0, 156, 46, 0, // Skip to: 13161
5018
/* 1229 */    MCD_OPC_CheckField, 0, 16, 15, 149, 46, 0, // Skip to: 13161
5019
/* 1236 */    MCD_OPC_Decode, 208, 8, 204, 1, // Opcode: AE_MULSP24X2
5020
/* 1241 */    MCD_OPC_FilterValue, 44, 39, 0, 0, // Skip to: 1285
5021
/* 1246 */    MCD_OPC_CheckPredicate, 24, 134, 46, 0, // Skip to: 13161
5022
/* 1251 */    MCD_OPC_CheckField, 36, 14, 128, 96, 126, 46, 0, // Skip to: 13161
5023
/* 1259 */    MCD_OPC_CheckField, 28, 4, 0, 119, 46, 0, // Skip to: 13161
5024
/* 1266 */    MCD_OPC_CheckField, 20, 4, 0, 112, 46, 0, // Skip to: 13161
5025
/* 1273 */    MCD_OPC_CheckField, 0, 16, 15, 105, 46, 0, // Skip to: 13161
5026
/* 1280 */    MCD_OPC_Decode, 223, 8, 204, 1, // Opcode: AE_MULSSD24_HH_LL
5027
/* 1285 */    MCD_OPC_FilterValue, 45, 38, 0, 0, // Skip to: 1328
5028
/* 1290 */    MCD_OPC_CheckPredicate, 24, 90, 46, 0, // Skip to: 13161
5029
/* 1295 */    MCD_OPC_CheckField, 36, 14, 0, 83, 46, 0, // Skip to: 13161
5030
/* 1302 */    MCD_OPC_CheckField, 28, 4, 0, 76, 46, 0, // Skip to: 13161
5031
/* 1309 */    MCD_OPC_CheckField, 20, 4, 0, 69, 46, 0, // Skip to: 13161
5032
/* 1316 */    MCD_OPC_CheckField, 0, 16, 15, 62, 46, 0, // Skip to: 13161
5033
/* 1323 */    MCD_OPC_Decode, 225, 8, 204, 1, // Opcode: AE_MULSSD24_HL_LH
5034
/* 1328 */    MCD_OPC_FilterValue, 46, 77, 0, 0, // Skip to: 1410
5035
/* 1333 */    MCD_OPC_ExtractField, 36, 14,  // Inst{49-36} ...
5036
/* 1336 */    MCD_OPC_FilterValue, 128, 64, 31, 0, 0, // Skip to: 1373
5037
/* 1342 */    MCD_OPC_CheckPredicate, 24, 38, 46, 0, // Skip to: 13161
5038
/* 1347 */    MCD_OPC_CheckField, 28, 4, 0, 31, 46, 0, // Skip to: 13161
5039
/* 1354 */    MCD_OPC_CheckField, 20, 4, 0, 24, 46, 0, // Skip to: 13161
5040
/* 1361 */    MCD_OPC_CheckField, 0, 16, 15, 17, 46, 0, // Skip to: 13161
5041
/* 1368 */    MCD_OPC_Decode, 237, 8, 204, 1, // Opcode: AE_MULSSFD24_HH_LL
5042
/* 1373 */    MCD_OPC_FilterValue, 128, 96, 6, 46, 0, // Skip to: 13161
5043
/* 1379 */    MCD_OPC_CheckPredicate, 24, 1, 46, 0, // Skip to: 13161
5044
/* 1384 */    MCD_OPC_CheckField, 28, 4, 0, 250, 45, 0, // Skip to: 13161
5045
/* 1391 */    MCD_OPC_CheckField, 20, 4, 0, 243, 45, 0, // Skip to: 13161
5046
/* 1398 */    MCD_OPC_CheckField, 0, 16, 15, 236, 45, 0, // Skip to: 13161
5047
/* 1405 */    MCD_OPC_Decode, 239, 8, 204, 1, // Opcode: AE_MULSSFD24_HL_LH
5048
/* 1410 */    MCD_OPC_FilterValue, 47, 77, 0, 0, // Skip to: 1492
5049
/* 1415 */    MCD_OPC_ExtractField, 36, 14,  // Inst{49-36} ...
5050
/* 1418 */    MCD_OPC_FilterValue, 128, 64, 31, 0, 0, // Skip to: 1455
5051
/* 1424 */    MCD_OPC_CheckPredicate, 24, 212, 45, 0, // Skip to: 13161
5052
/* 1429 */    MCD_OPC_CheckField, 28, 4, 0, 205, 45, 0, // Skip to: 13161
5053
/* 1436 */    MCD_OPC_CheckField, 20, 4, 0, 198, 45, 0, // Skip to: 13161
5054
/* 1443 */    MCD_OPC_CheckField, 0, 16, 15, 191, 45, 0, // Skip to: 13161
5055
/* 1450 */    MCD_OPC_Decode, 245, 8, 205, 1, // Opcode: AE_MULZAAD24_HH_LL
5056
/* 1455 */    MCD_OPC_FilterValue, 128, 96, 180, 45, 0, // Skip to: 13161
5057
/* 1461 */    MCD_OPC_CheckPredicate, 24, 175, 45, 0, // Skip to: 13161
5058
/* 1466 */    MCD_OPC_CheckField, 28, 4, 0, 168, 45, 0, // Skip to: 13161
5059
/* 1473 */    MCD_OPC_CheckField, 20, 4, 0, 161, 45, 0, // Skip to: 13161
5060
/* 1480 */    MCD_OPC_CheckField, 0, 16, 15, 154, 45, 0, // Skip to: 13161
5061
/* 1487 */    MCD_OPC_Decode, 247, 8, 205, 1, // Opcode: AE_MULZAAD24_HL_LH
5062
/* 1492 */    MCD_OPC_FilterValue, 49, 39, 0, 0, // Skip to: 1536
5063
/* 1497 */    MCD_OPC_CheckPredicate, 24, 139, 45, 0, // Skip to: 13161
5064
/* 1502 */    MCD_OPC_CheckField, 36, 14, 128, 96, 131, 45, 0, // Skip to: 13161
5065
/* 1510 */    MCD_OPC_CheckField, 28, 4, 0, 124, 45, 0, // Skip to: 13161
5066
/* 1517 */    MCD_OPC_CheckField, 20, 4, 0, 117, 45, 0, // Skip to: 13161
5067
/* 1524 */    MCD_OPC_CheckField, 0, 16, 15, 110, 45, 0, // Skip to: 13161
5068
/* 1531 */    MCD_OPC_Decode, 135, 9, 205, 1, // Opcode: AE_MULZAAFD24_HH_LL
5069
/* 1536 */    MCD_OPC_FilterValue, 50, 38, 0, 0, // Skip to: 1579
5070
/* 1541 */    MCD_OPC_CheckPredicate, 24, 95, 45, 0, // Skip to: 13161
5071
/* 1546 */    MCD_OPC_CheckField, 36, 14, 0, 88, 45, 0, // Skip to: 13161
5072
/* 1553 */    MCD_OPC_CheckField, 28, 4, 0, 81, 45, 0, // Skip to: 13161
5073
/* 1560 */    MCD_OPC_CheckField, 20, 4, 0, 74, 45, 0, // Skip to: 13161
5074
/* 1567 */    MCD_OPC_CheckField, 0, 16, 15, 67, 45, 0, // Skip to: 13161
5075
/* 1574 */    MCD_OPC_Decode, 137, 9, 205, 1, // Opcode: AE_MULZAAFD24_HL_LH
5076
/* 1579 */    MCD_OPC_FilterValue, 51, 77, 0, 0, // Skip to: 1661
5077
/* 1584 */    MCD_OPC_ExtractField, 36, 14,  // Inst{49-36} ...
5078
/* 1587 */    MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 1624
5079
/* 1593 */    MCD_OPC_CheckPredicate, 24, 43, 45, 0, // Skip to: 13161
5080
/* 1598 */    MCD_OPC_CheckField, 28, 4, 0, 36, 45, 0, // Skip to: 13161
5081
/* 1605 */    MCD_OPC_CheckField, 20, 4, 0, 29, 45, 0, // Skip to: 13161
5082
/* 1612 */    MCD_OPC_CheckField, 0, 16, 15, 22, 45, 0, // Skip to: 13161
5083
/* 1619 */    MCD_OPC_Decode, 147, 9, 205, 1, // Opcode: AE_MULZASD24_HH_LL
5084
/* 1624 */    MCD_OPC_FilterValue, 128, 64, 11, 45, 0, // Skip to: 13161
5085
/* 1630 */    MCD_OPC_CheckPredicate, 24, 6, 45, 0, // Skip to: 13161
5086
/* 1635 */    MCD_OPC_CheckField, 28, 4, 0, 255, 44, 0, // Skip to: 13161
5087
/* 1642 */    MCD_OPC_CheckField, 20, 4, 0, 248, 44, 0, // Skip to: 13161
5088
/* 1649 */    MCD_OPC_CheckField, 0, 16, 15, 241, 44, 0, // Skip to: 13161
5089
/* 1656 */    MCD_OPC_Decode, 149, 9, 205, 1, // Opcode: AE_MULZASD24_HL_LH
5090
/* 1661 */    MCD_OPC_FilterValue, 52, 77, 0, 0, // Skip to: 1743
5091
/* 1666 */    MCD_OPC_ExtractField, 36, 14,  // Inst{49-36} ...
5092
/* 1669 */    MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 1706
5093
/* 1675 */    MCD_OPC_CheckPredicate, 24, 217, 44, 0, // Skip to: 13161
5094
/* 1680 */    MCD_OPC_CheckField, 28, 4, 0, 210, 44, 0, // Skip to: 13161
5095
/* 1687 */    MCD_OPC_CheckField, 20, 4, 0, 203, 44, 0, // Skip to: 13161
5096
/* 1694 */    MCD_OPC_CheckField, 0, 16, 15, 196, 44, 0, // Skip to: 13161
5097
/* 1701 */    MCD_OPC_Decode, 155, 9, 205, 1, // Opcode: AE_MULZASFD24_HH_LL
5098
/* 1706 */    MCD_OPC_FilterValue, 128, 64, 185, 44, 0, // Skip to: 13161
5099
/* 1712 */    MCD_OPC_CheckPredicate, 24, 180, 44, 0, // Skip to: 13161
5100
/* 1717 */    MCD_OPC_CheckField, 28, 4, 0, 173, 44, 0, // Skip to: 13161
5101
/* 1724 */    MCD_OPC_CheckField, 20, 4, 0, 166, 44, 0, // Skip to: 13161
5102
/* 1731 */    MCD_OPC_CheckField, 0, 16, 15, 159, 44, 0, // Skip to: 13161
5103
/* 1738 */    MCD_OPC_Decode, 157, 9, 205, 1, // Opcode: AE_MULZASFD24_HL_LH
5104
/* 1743 */    MCD_OPC_FilterValue, 53, 77, 0, 0, // Skip to: 1825
5105
/* 1748 */    MCD_OPC_ExtractField, 36, 14,  // Inst{49-36} ...
5106
/* 1751 */    MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 1788
5107
/* 1757 */    MCD_OPC_CheckPredicate, 24, 135, 44, 0, // Skip to: 13161
5108
/* 1762 */    MCD_OPC_CheckField, 28, 4, 0, 128, 44, 0, // Skip to: 13161
5109
/* 1769 */    MCD_OPC_CheckField, 20, 4, 0, 121, 44, 0, // Skip to: 13161
5110
/* 1776 */    MCD_OPC_CheckField, 0, 16, 15, 114, 44, 0, // Skip to: 13161
5111
/* 1783 */    MCD_OPC_Decode, 163, 9, 205, 1, // Opcode: AE_MULZSAD24_HH_LL
5112
/* 1788 */    MCD_OPC_FilterValue, 128, 64, 103, 44, 0, // Skip to: 13161
5113
/* 1794 */    MCD_OPC_CheckPredicate, 24, 98, 44, 0, // Skip to: 13161
5114
/* 1799 */    MCD_OPC_CheckField, 28, 4, 0, 91, 44, 0, // Skip to: 13161
5115
/* 1806 */    MCD_OPC_CheckField, 20, 4, 0, 84, 44, 0, // Skip to: 13161
5116
/* 1813 */    MCD_OPC_CheckField, 0, 16, 15, 77, 44, 0, // Skip to: 13161
5117
/* 1820 */    MCD_OPC_Decode, 169, 9, 205, 1, // Opcode: AE_MULZSAFD24_HH_LL
5118
/* 1825 */    MCD_OPC_FilterValue, 54, 77, 0, 0, // Skip to: 1907
5119
/* 1830 */    MCD_OPC_ExtractField, 36, 14,  // Inst{49-36} ...
5120
/* 1833 */    MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 1870
5121
/* 1839 */    MCD_OPC_CheckPredicate, 24, 53, 44, 0, // Skip to: 13161
5122
/* 1844 */    MCD_OPC_CheckField, 28, 4, 0, 46, 44, 0, // Skip to: 13161
5123
/* 1851 */    MCD_OPC_CheckField, 20, 4, 0, 39, 44, 0, // Skip to: 13161
5124
/* 1858 */    MCD_OPC_CheckField, 0, 16, 15, 32, 44, 0, // Skip to: 13161
5125
/* 1865 */    MCD_OPC_Decode, 175, 9, 205, 1, // Opcode: AE_MULZSSD24_HH_LL
5126
/* 1870 */    MCD_OPC_FilterValue, 128, 64, 21, 44, 0, // Skip to: 13161
5127
/* 1876 */    MCD_OPC_CheckPredicate, 24, 16, 44, 0, // Skip to: 13161
5128
/* 1881 */    MCD_OPC_CheckField, 28, 4, 0, 9, 44, 0, // Skip to: 13161
5129
/* 1888 */    MCD_OPC_CheckField, 20, 4, 0, 2, 44, 0, // Skip to: 13161
5130
/* 1895 */    MCD_OPC_CheckField, 0, 16, 15, 251, 43, 0, // Skip to: 13161
5131
/* 1902 */    MCD_OPC_Decode, 177, 9, 205, 1, // Opcode: AE_MULZSSD24_HL_LH
5132
/* 1907 */    MCD_OPC_FilterValue, 56, 76, 0, 0, // Skip to: 1988
5133
/* 1912 */    MCD_OPC_ExtractField, 36, 14,  // Inst{49-36} ...
5134
/* 1915 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 1951
5135
/* 1920 */    MCD_OPC_CheckPredicate, 24, 228, 43, 0, // Skip to: 13161
5136
/* 1925 */    MCD_OPC_CheckField, 28, 4, 0, 221, 43, 0, // Skip to: 13161
5137
/* 1932 */    MCD_OPC_CheckField, 20, 4, 0, 214, 43, 0, // Skip to: 13161
5138
/* 1939 */    MCD_OPC_CheckField, 0, 16, 15, 207, 43, 0, // Skip to: 13161
5139
/* 1946 */    MCD_OPC_Decode, 189, 9, 205, 1, // Opcode: AE_MULZSSFD24_HH_LL
5140
/* 1951 */    MCD_OPC_FilterValue, 128, 32, 196, 43, 0, // Skip to: 13161
5141
/* 1957 */    MCD_OPC_CheckPredicate, 24, 191, 43, 0, // Skip to: 13161
5142
/* 1962 */    MCD_OPC_CheckField, 28, 4, 0, 184, 43, 0, // Skip to: 13161
5143
/* 1969 */    MCD_OPC_CheckField, 20, 4, 0, 177, 43, 0, // Skip to: 13161
5144
/* 1976 */    MCD_OPC_CheckField, 0, 16, 15, 170, 43, 0, // Skip to: 13161
5145
/* 1983 */    MCD_OPC_Decode, 191, 9, 205, 1, // Opcode: AE_MULZSSFD24_HL_LH
5146
/* 1988 */    MCD_OPC_FilterValue, 57, 38, 0, 0, // Skip to: 2031
5147
/* 1993 */    MCD_OPC_CheckPredicate, 24, 155, 43, 0, // Skip to: 13161
5148
/* 1998 */    MCD_OPC_CheckField, 36, 14, 0, 148, 43, 0, // Skip to: 13161
5149
/* 2005 */    MCD_OPC_CheckField, 28, 4, 0, 141, 43, 0, // Skip to: 13161
5150
/* 2012 */    MCD_OPC_CheckField, 20, 4, 0, 134, 43, 0, // Skip to: 13161
5151
/* 2019 */    MCD_OPC_CheckField, 0, 16, 15, 127, 43, 0, // Skip to: 13161
5152
/* 2026 */    MCD_OPC_Decode, 216, 4, 205, 1, // Opcode: AE_ADD16
5153
/* 2031 */    MCD_OPC_FilterValue, 58, 77, 0, 0, // Skip to: 2113
5154
/* 2036 */    MCD_OPC_ExtractField, 36, 14,  // Inst{49-36} ...
5155
/* 2039 */    MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 2076
5156
/* 2045 */    MCD_OPC_CheckPredicate, 24, 103, 43, 0, // Skip to: 13161
5157
/* 2050 */    MCD_OPC_CheckField, 28, 4, 0, 96, 43, 0, // Skip to: 13161
5158
/* 2057 */    MCD_OPC_CheckField, 20, 4, 0, 89, 43, 0, // Skip to: 13161
5159
/* 2064 */    MCD_OPC_CheckField, 0, 16, 15, 82, 43, 0, // Skip to: 13161
5160
/* 2071 */    MCD_OPC_Decode, 221, 4, 205, 1, // Opcode: AE_ADD32_HL_LH
5161
/* 2076 */    MCD_OPC_FilterValue, 128, 96, 71, 43, 0, // Skip to: 13161
5162
/* 2082 */    MCD_OPC_CheckPredicate, 24, 66, 43, 0, // Skip to: 13161
5163
/* 2087 */    MCD_OPC_CheckField, 28, 4, 0, 59, 43, 0, // Skip to: 13161
5164
/* 2094 */    MCD_OPC_CheckField, 20, 4, 0, 52, 43, 0, // Skip to: 13161
5165
/* 2101 */    MCD_OPC_CheckField, 0, 16, 15, 45, 43, 0, // Skip to: 13161
5166
/* 2108 */    MCD_OPC_Decode, 223, 4, 205, 1, // Opcode: AE_ADD64S
5167
/* 2113 */    MCD_OPC_FilterValue, 59, 114, 0, 0, // Skip to: 2232
5168
/* 2118 */    MCD_OPC_ExtractField, 36, 14,  // Inst{49-36} ...
5169
/* 2121 */    MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 2158
5170
/* 2127 */    MCD_OPC_CheckPredicate, 24, 21, 43, 0, // Skip to: 13161
5171
/* 2132 */    MCD_OPC_CheckField, 28, 4, 0, 14, 43, 0, // Skip to: 13161
5172
/* 2139 */    MCD_OPC_CheckField, 20, 4, 0, 7, 43, 0, // Skip to: 13161
5173
/* 2146 */    MCD_OPC_CheckField, 0, 16, 15, 0, 43, 0, // Skip to: 13161
5174
/* 2153 */    MCD_OPC_Decode, 225, 4, 205, 1, // Opcode: AE_ADDSUB32
5175
/* 2158 */    MCD_OPC_FilterValue, 128, 64, 31, 0, 0, // Skip to: 2195
5176
/* 2164 */    MCD_OPC_CheckPredicate, 24, 240, 42, 0, // Skip to: 13161
5177
/* 2169 */    MCD_OPC_CheckField, 28, 4, 0, 233, 42, 0, // Skip to: 13161
5178
/* 2176 */    MCD_OPC_CheckField, 20, 4, 0, 226, 42, 0, // Skip to: 13161
5179
/* 2183 */    MCD_OPC_CheckField, 0, 16, 15, 219, 42, 0, // Skip to: 13161
5180
/* 2190 */    MCD_OPC_Decode, 226, 4, 205, 1, // Opcode: AE_ADDSUB32S
5181
/* 2195 */    MCD_OPC_FilterValue, 128, 96, 208, 42, 0, // Skip to: 13161
5182
/* 2201 */    MCD_OPC_CheckPredicate, 24, 203, 42, 0, // Skip to: 13161
5183
/* 2206 */    MCD_OPC_CheckField, 28, 4, 0, 196, 42, 0, // Skip to: 13161
5184
/* 2213 */    MCD_OPC_CheckField, 20, 4, 0, 189, 42, 0, // Skip to: 13161
5185
/* 2220 */    MCD_OPC_CheckField, 0, 16, 15, 182, 42, 0, // Skip to: 13161
5186
/* 2227 */    MCD_OPC_Decode, 253, 10, 205, 1, // Opcode: AE_SUB16
5187
/* 2232 */    MCD_OPC_FilterValue, 60, 39, 0, 0, // Skip to: 2276
5188
/* 2237 */    MCD_OPC_CheckPredicate, 24, 167, 42, 0, // Skip to: 13161
5189
/* 2242 */    MCD_OPC_CheckField, 36, 14, 128, 32, 159, 42, 0, // Skip to: 13161
5190
/* 2250 */    MCD_OPC_CheckField, 28, 4, 0, 152, 42, 0, // Skip to: 13161
5191
/* 2257 */    MCD_OPC_CheckField, 20, 4, 0, 145, 42, 0, // Skip to: 13161
5192
/* 2264 */    MCD_OPC_CheckField, 0, 16, 15, 138, 42, 0, // Skip to: 13161
5193
/* 2271 */    MCD_OPC_Decode, 255, 10, 205, 1, // Opcode: AE_SUB24S
5194
/* 2276 */    MCD_OPC_FilterValue, 61, 114, 0, 0, // Skip to: 2395
5195
/* 2281 */    MCD_OPC_ExtractField, 36, 14,  // Inst{49-36} ...
5196
/* 2284 */    MCD_OPC_FilterValue, 128, 32, 31, 0, 0, // Skip to: 2321
5197
/* 2290 */    MCD_OPC_CheckPredicate, 24, 114, 42, 0, // Skip to: 13161
5198
/* 2295 */    MCD_OPC_CheckField, 28, 4, 0, 107, 42, 0, // Skip to: 13161
5199
/* 2302 */    MCD_OPC_CheckField, 20, 4, 0, 100, 42, 0, // Skip to: 13161
5200
/* 2309 */    MCD_OPC_CheckField, 0, 16, 15, 93, 42, 0, // Skip to: 13161
5201
/* 2316 */    MCD_OPC_Decode, 131, 11, 205, 1, // Opcode: AE_SUB64S
5202
/* 2321 */    MCD_OPC_FilterValue, 128, 64, 31, 0, 0, // Skip to: 2358
5203
/* 2327 */    MCD_OPC_CheckPredicate, 24, 77, 42, 0, // Skip to: 13161
5204
/* 2332 */    MCD_OPC_CheckField, 28, 4, 0, 70, 42, 0, // Skip to: 13161
5205
/* 2339 */    MCD_OPC_CheckField, 20, 4, 0, 63, 42, 0, // Skip to: 13161
5206
/* 2346 */    MCD_OPC_CheckField, 0, 16, 15, 56, 42, 0, // Skip to: 13161
5207
/* 2353 */    MCD_OPC_Decode, 132, 11, 205, 1, // Opcode: AE_SUBADD32
5208
/* 2358 */    MCD_OPC_FilterValue, 128, 96, 45, 42, 0, // Skip to: 13161
5209
/* 2364 */    MCD_OPC_CheckPredicate, 24, 40, 42, 0, // Skip to: 13161
5210
/* 2369 */    MCD_OPC_CheckField, 28, 4, 0, 33, 42, 0, // Skip to: 13161
5211
/* 2376 */    MCD_OPC_CheckField, 20, 4, 0, 26, 42, 0, // Skip to: 13161
5212
/* 2383 */    MCD_OPC_CheckField, 0, 16, 15, 19, 42, 0, // Skip to: 13161
5213
/* 2390 */    MCD_OPC_Decode, 133, 11, 205, 1, // Opcode: AE_SUBADD32S
5214
/* 2395 */    MCD_OPC_FilterValue, 62, 156, 0, 0, // Skip to: 2556
5215
/* 2400 */    MCD_OPC_ExtractField, 20, 12,  // Inst{31-20} ...
5216
/* 2403 */    MCD_OPC_FilterValue, 32, 25, 0, 0, // Skip to: 2433
5217
/* 2408 */    MCD_OPC_CheckPredicate, 24, 252, 41, 0, // Skip to: 13161
5218
/* 2413 */    MCD_OPC_CheckField, 36, 14, 128, 96, 244, 41, 0, // Skip to: 13161
5219
/* 2421 */    MCD_OPC_CheckField, 0, 16, 15, 237, 41, 0, // Skip to: 13161
5220
/* 2428 */    MCD_OPC_Decode, 212, 4, 209, 1, // Opcode: AE_ABS32
5221
/* 2433 */    MCD_OPC_FilterValue, 80, 25, 0, 0, // Skip to: 2463
5222
/* 2438 */    MCD_OPC_CheckPredicate, 24, 222, 41, 0, // Skip to: 13161
5223
/* 2443 */    MCD_OPC_CheckField, 36, 14, 128, 96, 214, 41, 0, // Skip to: 13161
5224
/* 2451 */    MCD_OPC_CheckField, 0, 16, 15, 207, 41, 0, // Skip to: 13161
5225
/* 2458 */    MCD_OPC_Decode, 215, 4, 209, 1, // Opcode: AE_ABS64S
5226
/* 2463 */    MCD_OPC_FilterValue, 128, 1, 25, 0, 0, // Skip to: 2494
5227
/* 2469 */    MCD_OPC_CheckPredicate, 24, 191, 41, 0, // Skip to: 13161
5228
/* 2474 */    MCD_OPC_CheckField, 36, 14, 128, 96, 183, 41, 0, // Skip to: 13161
5229
/* 2482 */    MCD_OPC_CheckField, 0, 16, 15, 176, 41, 0, // Skip to: 13161
5230
/* 2489 */    MCD_OPC_Decode, 199, 9, 209, 1, // Opcode: AE_NEG24S
5231
/* 2494 */    MCD_OPC_FilterValue, 144, 1, 25, 0, 0, // Skip to: 2525
5232
/* 2500 */    MCD_OPC_CheckPredicate, 24, 160, 41, 0, // Skip to: 13161
5233
/* 2505 */    MCD_OPC_CheckField, 36, 14, 128, 96, 152, 41, 0, // Skip to: 13161
5234
/* 2513 */    MCD_OPC_CheckField, 0, 16, 15, 145, 41, 0, // Skip to: 13161
5235
/* 2520 */    MCD_OPC_Decode, 200, 9, 209, 1, // Opcode: AE_NEG32
5236
/* 2525 */    MCD_OPC_FilterValue, 192, 1, 134, 41, 0, // Skip to: 13161
5237
/* 2531 */    MCD_OPC_CheckPredicate, 24, 129, 41, 0, // Skip to: 13161
5238
/* 2536 */    MCD_OPC_CheckField, 36, 14, 128, 96, 121, 41, 0, // Skip to: 13161
5239
/* 2544 */    MCD_OPC_CheckField, 0, 16, 15, 114, 41, 0, // Skip to: 13161
5240
/* 2551 */    MCD_OPC_Decode, 203, 9, 209, 1, // Opcode: AE_NEG64S
5241
/* 2556 */    MCD_OPC_FilterValue, 64, 31, 0, 0, // Skip to: 2592
5242
/* 2561 */    MCD_OPC_CheckPredicate, 24, 99, 41, 0, // Skip to: 13161
5243
/* 2566 */    MCD_OPC_CheckField, 40, 10, 0, 92, 41, 0, // Skip to: 13161
5244
/* 2573 */    MCD_OPC_CheckField, 28, 4, 0, 85, 41, 0, // Skip to: 13161
5245
/* 2580 */    MCD_OPC_CheckField, 0, 16, 14, 78, 41, 0, // Skip to: 13161
5246
/* 2587 */    MCD_OPC_Decode, 239, 6, 202, 1, // Opcode: AE_MULAFD24X2_FIR_L
5247
/* 2592 */    MCD_OPC_FilterValue, 128, 1, 31, 0, 0, // Skip to: 2629
5248
/* 2598 */    MCD_OPC_CheckPredicate, 24, 62, 41, 0, // Skip to: 13161
5249
/* 2603 */    MCD_OPC_CheckField, 40, 10, 0, 55, 41, 0, // Skip to: 13161
5250
/* 2610 */    MCD_OPC_CheckField, 28, 4, 0, 48, 41, 0, // Skip to: 13161
5251
/* 2617 */    MCD_OPC_CheckField, 0, 16, 14, 41, 41, 0, // Skip to: 13161
5252
/* 2624 */    MCD_OPC_Decode, 240, 6, 202, 1, // Opcode: AE_MULAFD32X16X2_FIR_HH
5253
/* 2629 */    MCD_OPC_FilterValue, 192, 1, 30, 41, 0, // Skip to: 13161
5254
/* 2635 */    MCD_OPC_CheckPredicate, 24, 25, 41, 0, // Skip to: 13161
5255
/* 2640 */    MCD_OPC_CheckField, 40, 10, 0, 18, 41, 0, // Skip to: 13161
5256
/* 2647 */    MCD_OPC_CheckField, 28, 4, 0, 11, 41, 0, // Skip to: 13161
5257
/* 2654 */    MCD_OPC_CheckField, 0, 16, 14, 4, 41, 0, // Skip to: 13161
5258
/* 2661 */    MCD_OPC_Decode, 241, 6, 202, 1, // Opcode: AE_MULAFD32X16X2_FIR_HL
5259
/* 2666 */    MCD_OPC_FilterValue, 1, 148, 0, 0, // Skip to: 2819
5260
/* 2671 */    MCD_OPC_ExtractField, 0, 16,  // Inst{15-0} ...
5261
/* 2674 */    MCD_OPC_FilterValue, 14, 97, 0, 0, // Skip to: 2776
5262
/* 2679 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5263
/* 2682 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2704
5264
/* 2687 */    MCD_OPC_CheckPredicate, 24, 229, 40, 0, // Skip to: 13161
5265
/* 2692 */    MCD_OPC_CheckField, 28, 4, 0, 222, 40, 0, // Skip to: 13161
5266
/* 2699 */    MCD_OPC_Decode, 242, 6, 202, 1, // Opcode: AE_MULAFD32X16X2_FIR_LH
5267
/* 2704 */    MCD_OPC_FilterValue, 128, 128, 4, 17, 0, 0, // Skip to: 2728
5268
/* 2711 */    MCD_OPC_CheckPredicate, 24, 205, 40, 0, // Skip to: 13161
5269
/* 2716 */    MCD_OPC_CheckField, 28, 4, 0, 198, 40, 0, // Skip to: 13161
5270
/* 2723 */    MCD_OPC_Decode, 243, 6, 202, 1, // Opcode: AE_MULAFD32X16X2_FIR_LL
5271
/* 2728 */    MCD_OPC_FilterValue, 128, 128, 8, 17, 0, 0, // Skip to: 2752
5272
/* 2735 */    MCD_OPC_CheckPredicate, 24, 181, 40, 0, // Skip to: 13161
5273
/* 2740 */    MCD_OPC_CheckField, 28, 4, 0, 174, 40, 0, // Skip to: 13161
5274
/* 2747 */    MCD_OPC_Decode, 209, 7, 210, 1, // Opcode: AE_MULFD24X2_FIR_H
5275
/* 2752 */    MCD_OPC_FilterValue, 128, 128, 12, 162, 40, 0, // Skip to: 13161
5276
/* 2759 */    MCD_OPC_CheckPredicate, 24, 157, 40, 0, // Skip to: 13161
5277
/* 2764 */    MCD_OPC_CheckField, 28, 4, 0, 150, 40, 0, // Skip to: 13161
5278
/* 2771 */    MCD_OPC_Decode, 210, 7, 210, 1, // Opcode: AE_MULFD24X2_FIR_L
5279
/* 2776 */    MCD_OPC_FilterValue, 15, 140, 40, 0, // Skip to: 13161
5280
/* 2781 */    MCD_OPC_CheckPredicate, 24, 135, 40, 0, // Skip to: 13161
5281
/* 2786 */    MCD_OPC_CheckField, 40, 16, 0, 128, 40, 0, // Skip to: 13161
5282
/* 2793 */    MCD_OPC_CheckField, 32, 4, 0, 121, 40, 0, // Skip to: 13161
5283
/* 2800 */    MCD_OPC_CheckField, 24, 4, 0, 114, 40, 0, // Skip to: 13161
5284
/* 2807 */    MCD_OPC_CheckField, 16, 4, 0, 107, 40, 0, // Skip to: 13161
5285
/* 2814 */    MCD_OPC_Decode, 219, 10, 211, 1, // Opcode: AE_SLAI64S
5286
/* 2819 */    MCD_OPC_FilterValue, 2, 125, 0, 0, // Skip to: 2949
5287
/* 2824 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5288
/* 2827 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2856
5289
/* 2832 */    MCD_OPC_CheckPredicate, 24, 84, 40, 0, // Skip to: 13161
5290
/* 2837 */    MCD_OPC_CheckField, 28, 4, 0, 77, 40, 0, // Skip to: 13161
5291
/* 2844 */    MCD_OPC_CheckField, 0, 16, 14, 70, 40, 0, // Skip to: 13161
5292
/* 2851 */    MCD_OPC_Decode, 211, 7, 210, 1, // Opcode: AE_MULFD32X16X2_FIR_HH
5293
/* 2856 */    MCD_OPC_FilterValue, 128, 128, 4, 24, 0, 0, // Skip to: 2887
5294
/* 2863 */    MCD_OPC_CheckPredicate, 24, 53, 40, 0, // Skip to: 13161
5295
/* 2868 */    MCD_OPC_CheckField, 28, 4, 0, 46, 40, 0, // Skip to: 13161
5296
/* 2875 */    MCD_OPC_CheckField, 0, 16, 14, 39, 40, 0, // Skip to: 13161
5297
/* 2882 */    MCD_OPC_Decode, 212, 7, 210, 1, // Opcode: AE_MULFD32X16X2_FIR_HL
5298
/* 2887 */    MCD_OPC_FilterValue, 128, 128, 8, 24, 0, 0, // Skip to: 2918
5299
/* 2894 */    MCD_OPC_CheckPredicate, 24, 22, 40, 0, // Skip to: 13161
5300
/* 2899 */    MCD_OPC_CheckField, 28, 4, 0, 15, 40, 0, // Skip to: 13161
5301
/* 2906 */    MCD_OPC_CheckField, 0, 16, 14, 8, 40, 0, // Skip to: 13161
5302
/* 2913 */    MCD_OPC_Decode, 213, 7, 210, 1, // Opcode: AE_MULFD32X16X2_FIR_LH
5303
/* 2918 */    MCD_OPC_FilterValue, 128, 128, 12, 252, 39, 0, // Skip to: 13161
5304
/* 2925 */    MCD_OPC_CheckPredicate, 24, 247, 39, 0, // Skip to: 13161
5305
/* 2930 */    MCD_OPC_CheckField, 28, 4, 0, 240, 39, 0, // Skip to: 13161
5306
/* 2937 */    MCD_OPC_CheckField, 0, 16, 14, 233, 39, 0, // Skip to: 13161
5307
/* 2944 */    MCD_OPC_Decode, 214, 7, 210, 1, // Opcode: AE_MULFD32X16X2_FIR_LL
5308
/* 2949 */    MCD_OPC_FilterValue, 3, 231, 4, 0, // Skip to: 4209
5309
/* 2954 */    MCD_OPC_ExtractField, 36, 22,  // Inst{57-36} ...
5310
/* 2957 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2986
5311
/* 2962 */    MCD_OPC_CheckPredicate, 24, 210, 39, 0, // Skip to: 13161
5312
/* 2967 */    MCD_OPC_CheckField, 28, 4, 0, 203, 39, 0, // Skip to: 13161
5313
/* 2974 */    MCD_OPC_CheckField, 0, 16, 14, 196, 39, 0, // Skip to: 13161
5314
/* 2981 */    MCD_OPC_Decode, 246, 5, 212, 1, // Opcode: AE_MUL16X4
5315
/* 2986 */    MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 3015
5316
/* 2991 */    MCD_OPC_CheckPredicate, 24, 181, 39, 0, // Skip to: 13161
5317
/* 2996 */    MCD_OPC_CheckField, 28, 4, 0, 174, 39, 0, // Skip to: 13161
5318
/* 3003 */    MCD_OPC_CheckField, 0, 16, 14, 167, 39, 0, // Skip to: 13161
5319
/* 3010 */    MCD_OPC_Decode, 206, 6, 213, 1, // Opcode: AE_MULAF16X4SS
5320
/* 3015 */    MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 3044
5321
/* 3020 */    MCD_OPC_CheckPredicate, 24, 152, 39, 0, // Skip to: 13161
5322
/* 3025 */    MCD_OPC_CheckField, 28, 4, 0, 145, 39, 0, // Skip to: 13161
5323
/* 3032 */    MCD_OPC_CheckField, 0, 16, 14, 138, 39, 0, // Skip to: 13161
5324
/* 3039 */    MCD_OPC_Decode, 242, 7, 213, 1, // Opcode: AE_MULS16X4
5325
/* 3044 */    MCD_OPC_FilterValue, 4, 61, 0, 0, // Skip to: 3110
5326
/* 3049 */    MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
5327
/* 3052 */    MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 3081
5328
/* 3057 */    MCD_OPC_CheckPredicate, 24, 115, 39, 0, // Skip to: 13161
5329
/* 3062 */    MCD_OPC_CheckField, 28, 4, 0, 108, 39, 0, // Skip to: 13161
5330
/* 3069 */    MCD_OPC_CheckField, 0, 16, 14, 101, 39, 0, // Skip to: 13161
5331
/* 3076 */    MCD_OPC_Decode, 198, 6, 204, 1, // Opcode: AE_MULAF16SS_11
5332
/* 3081 */    MCD_OPC_FilterValue, 15, 91, 39, 0, // Skip to: 13161
5333
/* 3086 */    MCD_OPC_CheckPredicate, 24, 86, 39, 0, // Skip to: 13161
5334
/* 3091 */    MCD_OPC_CheckField, 28, 4, 0, 79, 39, 0, // Skip to: 13161
5335
/* 3098 */    MCD_OPC_CheckField, 0, 16, 14, 72, 39, 0, // Skip to: 13161
5336
/* 3105 */    MCD_OPC_Decode, 200, 6, 204, 1, // Opcode: AE_MULAF16SS_21
5337
/* 3110 */    MCD_OPC_FilterValue, 5, 61, 0, 0, // Skip to: 3176
5338
/* 3115 */    MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
5339
/* 3118 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 3147
5340
/* 3123 */    MCD_OPC_CheckPredicate, 24, 49, 39, 0, // Skip to: 13161
5341
/* 3128 */    MCD_OPC_CheckField, 28, 4, 0, 42, 39, 0, // Skip to: 13161
5342
/* 3135 */    MCD_OPC_CheckField, 0, 16, 14, 35, 39, 0, // Skip to: 13161
5343
/* 3142 */    MCD_OPC_Decode, 202, 6, 204, 1, // Opcode: AE_MULAF16SS_30
5344
/* 3147 */    MCD_OPC_FilterValue, 1, 25, 39, 0, // Skip to: 13161
5345
/* 3152 */    MCD_OPC_CheckPredicate, 24, 20, 39, 0, // Skip to: 13161
5346
/* 3157 */    MCD_OPC_CheckField, 28, 4, 0, 13, 39, 0, // Skip to: 13161
5347
/* 3164 */    MCD_OPC_CheckField, 0, 16, 14, 6, 39, 0, // Skip to: 13161
5348
/* 3171 */    MCD_OPC_Decode, 204, 6, 204, 1, // Opcode: AE_MULAF16SS_32
5349
/* 3176 */    MCD_OPC_FilterValue, 6, 119, 0, 0, // Skip to: 3300
5350
/* 3181 */    MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
5351
/* 3184 */    MCD_OPC_FilterValue, 12, 24, 0, 0, // Skip to: 3213
5352
/* 3189 */    MCD_OPC_CheckPredicate, 24, 239, 38, 0, // Skip to: 13161
5353
/* 3194 */    MCD_OPC_CheckField, 28, 4, 0, 232, 38, 0, // Skip to: 13161
5354
/* 3201 */    MCD_OPC_CheckField, 0, 16, 14, 225, 38, 0, // Skip to: 13161
5355
/* 3208 */    MCD_OPC_Decode, 168, 7, 205, 1, // Opcode: AE_MULF16SS_10
5356
/* 3213 */    MCD_OPC_FilterValue, 13, 24, 0, 0, // Skip to: 3242
5357
/* 3218 */    MCD_OPC_CheckPredicate, 24, 210, 38, 0, // Skip to: 13161
5358
/* 3223 */    MCD_OPC_CheckField, 28, 4, 0, 203, 38, 0, // Skip to: 13161
5359
/* 3230 */    MCD_OPC_CheckField, 0, 16, 14, 196, 38, 0, // Skip to: 13161
5360
/* 3237 */    MCD_OPC_Decode, 170, 7, 205, 1, // Opcode: AE_MULF16SS_20
5361
/* 3242 */    MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 3271
5362
/* 3247 */    MCD_OPC_CheckPredicate, 24, 181, 38, 0, // Skip to: 13161
5363
/* 3252 */    MCD_OPC_CheckField, 28, 4, 0, 174, 38, 0, // Skip to: 13161
5364
/* 3259 */    MCD_OPC_CheckField, 0, 16, 14, 167, 38, 0, // Skip to: 13161
5365
/* 3266 */    MCD_OPC_Decode, 172, 7, 205, 1, // Opcode: AE_MULF16SS_22
5366
/* 3271 */    MCD_OPC_FilterValue, 15, 157, 38, 0, // Skip to: 13161
5367
/* 3276 */    MCD_OPC_CheckPredicate, 24, 152, 38, 0, // Skip to: 13161
5368
/* 3281 */    MCD_OPC_CheckField, 28, 4, 0, 145, 38, 0, // Skip to: 13161
5369
/* 3288 */    MCD_OPC_CheckField, 0, 16, 14, 138, 38, 0, // Skip to: 13161
5370
/* 3295 */    MCD_OPC_Decode, 174, 7, 205, 1, // Opcode: AE_MULF16SS_31
5371
/* 3300 */    MCD_OPC_FilterValue, 7, 61, 0, 0, // Skip to: 3366
5372
/* 3305 */    MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
5373
/* 3308 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 3337
5374
/* 3313 */    MCD_OPC_CheckPredicate, 24, 115, 38, 0, // Skip to: 13161
5375
/* 3318 */    MCD_OPC_CheckField, 28, 4, 0, 108, 38, 0, // Skip to: 13161
5376
/* 3325 */    MCD_OPC_CheckField, 0, 16, 14, 101, 38, 0, // Skip to: 13161
5377
/* 3332 */    MCD_OPC_Decode, 176, 7, 205, 1, // Opcode: AE_MULF16SS_33
5378
/* 3337 */    MCD_OPC_FilterValue, 10, 91, 38, 0, // Skip to: 13161
5379
/* 3342 */    MCD_OPC_CheckPredicate, 24, 86, 38, 0, // Skip to: 13161
5380
/* 3347 */    MCD_OPC_CheckField, 28, 4, 0, 79, 38, 0, // Skip to: 13161
5381
/* 3354 */    MCD_OPC_CheckField, 0, 16, 14, 72, 38, 0, // Skip to: 13161
5382
/* 3361 */    MCD_OPC_Decode, 215, 7, 205, 1, // Opcode: AE_MULFP16X4RAS
5383
/* 3366 */    MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 3395
5384
/* 3371 */    MCD_OPC_CheckPredicate, 24, 57, 38, 0, // Skip to: 13161
5385
/* 3376 */    MCD_OPC_CheckField, 28, 4, 0, 50, 38, 0, // Skip to: 13161
5386
/* 3383 */    MCD_OPC_CheckField, 0, 16, 14, 43, 38, 0, // Skip to: 13161
5387
/* 3390 */    MCD_OPC_Decode, 140, 6, 213, 1, // Opcode: AE_MULA16X4
5388
/* 3395 */    MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 3424
5389
/* 3400 */    MCD_OPC_CheckPredicate, 24, 28, 38, 0, // Skip to: 13161
5390
/* 3405 */    MCD_OPC_CheckField, 28, 4, 0, 21, 38, 0, // Skip to: 13161
5391
/* 3412 */    MCD_OPC_CheckField, 0, 16, 14, 14, 38, 0, // Skip to: 13161
5392
/* 3419 */    MCD_OPC_Decode, 177, 7, 212, 1, // Opcode: AE_MULF16X4SS
5393
/* 3424 */    MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 3453
5394
/* 3429 */    MCD_OPC_CheckPredicate, 24, 255, 37, 0, // Skip to: 13161
5395
/* 3434 */    MCD_OPC_CheckField, 28, 4, 0, 248, 37, 0, // Skip to: 13161
5396
/* 3441 */    MCD_OPC_CheckField, 0, 16, 14, 241, 37, 0, // Skip to: 13161
5397
/* 3448 */    MCD_OPC_Decode, 164, 8, 213, 1, // Opcode: AE_MULSF16X4SS
5398
/* 3453 */    MCD_OPC_FilterValue, 12, 90, 0, 0, // Skip to: 3548
5399
/* 3458 */    MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
5400
/* 3461 */    MCD_OPC_FilterValue, 13, 24, 0, 0, // Skip to: 3490
5401
/* 3466 */    MCD_OPC_CheckPredicate, 24, 218, 37, 0, // Skip to: 13161
5402
/* 3471 */    MCD_OPC_CheckField, 28, 4, 0, 211, 37, 0, // Skip to: 13161
5403
/* 3478 */    MCD_OPC_CheckField, 0, 16, 14, 204, 37, 0, // Skip to: 13161
5404
/* 3485 */    MCD_OPC_Decode, 197, 6, 204, 1, // Opcode: AE_MULAF16SS_10
5405
/* 3490 */    MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 3519
5406
/* 3495 */    MCD_OPC_CheckPredicate, 24, 189, 37, 0, // Skip to: 13161
5407
/* 3500 */    MCD_OPC_CheckField, 28, 4, 0, 182, 37, 0, // Skip to: 13161
5408
/* 3507 */    MCD_OPC_CheckField, 0, 16, 14, 175, 37, 0, // Skip to: 13161
5409
/* 3514 */    MCD_OPC_Decode, 199, 6, 204, 1, // Opcode: AE_MULAF16SS_20
5410
/* 3519 */    MCD_OPC_FilterValue, 15, 165, 37, 0, // Skip to: 13161
5411
/* 3524 */    MCD_OPC_CheckPredicate, 24, 160, 37, 0, // Skip to: 13161
5412
/* 3529 */    MCD_OPC_CheckField, 28, 4, 0, 153, 37, 0, // Skip to: 13161
5413
/* 3536 */    MCD_OPC_CheckField, 0, 16, 14, 146, 37, 0, // Skip to: 13161
5414
/* 3543 */    MCD_OPC_Decode, 201, 6, 204, 1, // Opcode: AE_MULAF16SS_22
5415
/* 3548 */    MCD_OPC_FilterValue, 13, 61, 0, 0, // Skip to: 3614
5416
/* 3553 */    MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
5417
/* 3556 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 3585
5418
/* 3561 */    MCD_OPC_CheckPredicate, 24, 123, 37, 0, // Skip to: 13161
5419
/* 3566 */    MCD_OPC_CheckField, 28, 4, 0, 116, 37, 0, // Skip to: 13161
5420
/* 3573 */    MCD_OPC_CheckField, 0, 16, 14, 109, 37, 0, // Skip to: 13161
5421
/* 3580 */    MCD_OPC_Decode, 203, 6, 204, 1, // Opcode: AE_MULAF16SS_31
5422
/* 3585 */    MCD_OPC_FilterValue, 1, 99, 37, 0, // Skip to: 13161
5423
/* 3590 */    MCD_OPC_CheckPredicate, 24, 94, 37, 0, // Skip to: 13161
5424
/* 3595 */    MCD_OPC_CheckField, 28, 4, 0, 87, 37, 0, // Skip to: 13161
5425
/* 3602 */    MCD_OPC_CheckField, 0, 16, 14, 80, 37, 0, // Skip to: 13161
5426
/* 3609 */    MCD_OPC_Decode, 205, 6, 204, 1, // Opcode: AE_MULAF16SS_33
5427
/* 3614 */    MCD_OPC_FilterValue, 14, 119, 0, 0, // Skip to: 3738
5428
/* 3619 */    MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
5429
/* 3622 */    MCD_OPC_FilterValue, 12, 24, 0, 0, // Skip to: 3651
5430
/* 3627 */    MCD_OPC_CheckPredicate, 24, 57, 37, 0, // Skip to: 13161
5431
/* 3632 */    MCD_OPC_CheckField, 28, 4, 0, 50, 37, 0, // Skip to: 13161
5432
/* 3639 */    MCD_OPC_CheckField, 0, 16, 14, 43, 37, 0, // Skip to: 13161
5433
/* 3646 */    MCD_OPC_Decode, 169, 7, 205, 1, // Opcode: AE_MULF16SS_11
5434
/* 3651 */    MCD_OPC_FilterValue, 13, 24, 0, 0, // Skip to: 3680
5435
/* 3656 */    MCD_OPC_CheckPredicate, 24, 28, 37, 0, // Skip to: 13161
5436
/* 3661 */    MCD_OPC_CheckField, 28, 4, 0, 21, 37, 0, // Skip to: 13161
5437
/* 3668 */    MCD_OPC_CheckField, 0, 16, 14, 14, 37, 0, // Skip to: 13161
5438
/* 3675 */    MCD_OPC_Decode, 171, 7, 205, 1, // Opcode: AE_MULF16SS_21
5439
/* 3680 */    MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 3709
5440
/* 3685 */    MCD_OPC_CheckPredicate, 24, 255, 36, 0, // Skip to: 13161
5441
/* 3690 */    MCD_OPC_CheckField, 28, 4, 0, 248, 36, 0, // Skip to: 13161
5442
/* 3697 */    MCD_OPC_CheckField, 0, 16, 14, 241, 36, 0, // Skip to: 13161
5443
/* 3704 */    MCD_OPC_Decode, 173, 7, 205, 1, // Opcode: AE_MULF16SS_30
5444
/* 3709 */    MCD_OPC_FilterValue, 15, 231, 36, 0, // Skip to: 13161
5445
/* 3714 */    MCD_OPC_CheckPredicate, 24, 226, 36, 0, // Skip to: 13161
5446
/* 3719 */    MCD_OPC_CheckField, 28, 4, 0, 219, 36, 0, // Skip to: 13161
5447
/* 3726 */    MCD_OPC_CheckField, 0, 16, 14, 212, 36, 0, // Skip to: 13161
5448
/* 3733 */    MCD_OPC_Decode, 175, 7, 205, 1, // Opcode: AE_MULF16SS_32
5449
/* 3738 */    MCD_OPC_FilterValue, 15, 31, 0, 0, // Skip to: 3774
5450
/* 3743 */    MCD_OPC_CheckPredicate, 24, 197, 36, 0, // Skip to: 13161
5451
/* 3748 */    MCD_OPC_CheckField, 28, 4, 0, 190, 36, 0, // Skip to: 13161
5452
/* 3755 */    MCD_OPC_CheckField, 20, 4, 10, 183, 36, 0, // Skip to: 13161
5453
/* 3762 */    MCD_OPC_CheckField, 0, 16, 14, 176, 36, 0, // Skip to: 13161
5454
/* 3769 */    MCD_OPC_Decode, 216, 7, 205, 1, // Opcode: AE_MULFP16X4S
5455
/* 3774 */    MCD_OPC_FilterValue, 128, 128, 64, 61, 0, 0, // Skip to: 3842
5456
/* 3781 */    MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
5457
/* 3784 */    MCD_OPC_FilterValue, 12, 24, 0, 0, // Skip to: 3813
5458
/* 3789 */    MCD_OPC_CheckPredicate, 24, 151, 36, 0, // Skip to: 13161
5459
/* 3794 */    MCD_OPC_CheckField, 28, 4, 0, 144, 36, 0, // Skip to: 13161
5460
/* 3801 */    MCD_OPC_CheckField, 0, 16, 14, 137, 36, 0, // Skip to: 13161
5461
/* 3808 */    MCD_OPC_Decode, 143, 8, 204, 1, // Opcode: AE_MULSAD32X16_H1_L0
5462
/* 3813 */    MCD_OPC_FilterValue, 15, 127, 36, 0, // Skip to: 13161
5463
/* 3818 */    MCD_OPC_CheckPredicate, 24, 122, 36, 0, // Skip to: 13161
5464
/* 3823 */    MCD_OPC_CheckField, 28, 4, 0, 115, 36, 0, // Skip to: 13161
5465
/* 3830 */    MCD_OPC_CheckField, 0, 16, 14, 108, 36, 0, // Skip to: 13161
5466
/* 3837 */    MCD_OPC_Decode, 155, 8, 204, 1, // Opcode: AE_MULSF16SS_10
5467
/* 3842 */    MCD_OPC_FilterValue, 129, 128, 64, 119, 0, 0, // Skip to: 3968
5468
/* 3849 */    MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
5469
/* 3852 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 3881
5470
/* 3857 */    MCD_OPC_CheckPredicate, 24, 83, 36, 0, // Skip to: 13161
5471
/* 3862 */    MCD_OPC_CheckField, 28, 4, 0, 76, 36, 0, // Skip to: 13161
5472
/* 3869 */    MCD_OPC_CheckField, 0, 16, 14, 69, 36, 0, // Skip to: 13161
5473
/* 3876 */    MCD_OPC_Decode, 157, 8, 204, 1, // Opcode: AE_MULSF16SS_20
5474
/* 3881 */    MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 3910
5475
/* 3886 */    MCD_OPC_CheckPredicate, 24, 54, 36, 0, // Skip to: 13161
5476
/* 3891 */    MCD_OPC_CheckField, 28, 4, 0, 47, 36, 0, // Skip to: 13161
5477
/* 3898 */    MCD_OPC_CheckField, 0, 16, 14, 40, 36, 0, // Skip to: 13161
5478
/* 3905 */    MCD_OPC_Decode, 159, 8, 204, 1, // Opcode: AE_MULSF16SS_22
5479
/* 3910 */    MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 3939
5480
/* 3915 */    MCD_OPC_CheckPredicate, 24, 25, 36, 0, // Skip to: 13161
5481
/* 3920 */    MCD_OPC_CheckField, 28, 4, 0, 18, 36, 0, // Skip to: 13161
5482
/* 3927 */    MCD_OPC_CheckField, 0, 16, 14, 11, 36, 0, // Skip to: 13161
5483
/* 3934 */    MCD_OPC_Decode, 161, 8, 204, 1, // Opcode: AE_MULSF16SS_31
5484
/* 3939 */    MCD_OPC_FilterValue, 3, 1, 36, 0, // Skip to: 13161
5485
/* 3944 */    MCD_OPC_CheckPredicate, 24, 252, 35, 0, // Skip to: 13161
5486
/* 3949 */    MCD_OPC_CheckField, 28, 4, 0, 245, 35, 0, // Skip to: 13161
5487
/* 3956 */    MCD_OPC_CheckField, 0, 16, 14, 238, 35, 0, // Skip to: 13161
5488
/* 3963 */    MCD_OPC_Decode, 163, 8, 204, 1, // Opcode: AE_MULSF16SS_33
5489
/* 3968 */    MCD_OPC_FilterValue, 131, 128, 64, 31, 0, 0, // Skip to: 4006
5490
/* 3975 */    MCD_OPC_CheckPredicate, 24, 221, 35, 0, // Skip to: 13161
5491
/* 3980 */    MCD_OPC_CheckField, 28, 4, 0, 214, 35, 0, // Skip to: 13161
5492
/* 3987 */    MCD_OPC_CheckField, 20, 4, 8, 207, 35, 0, // Skip to: 13161
5493
/* 3994 */    MCD_OPC_CheckField, 0, 16, 14, 200, 35, 0, // Skip to: 13161
5494
/* 4001 */    MCD_OPC_Decode, 167, 9, 205, 1, // Opcode: AE_MULZSAD32X16_H3_L2
5495
/* 4006 */    MCD_OPC_FilterValue, 136, 128, 64, 61, 0, 0, // Skip to: 4074
5496
/* 4013 */    MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
5497
/* 4016 */    MCD_OPC_FilterValue, 12, 24, 0, 0, // Skip to: 4045
5498
/* 4021 */    MCD_OPC_CheckPredicate, 24, 175, 35, 0, // Skip to: 13161
5499
/* 4026 */    MCD_OPC_CheckField, 28, 4, 0, 168, 35, 0, // Skip to: 13161
5500
/* 4033 */    MCD_OPC_CheckField, 0, 16, 14, 161, 35, 0, // Skip to: 13161
5501
/* 4040 */    MCD_OPC_Decode, 145, 8, 204, 1, // Opcode: AE_MULSAD32X16_H3_L2
5502
/* 4045 */    MCD_OPC_FilterValue, 15, 151, 35, 0, // Skip to: 13161
5503
/* 4050 */    MCD_OPC_CheckPredicate, 24, 146, 35, 0, // Skip to: 13161
5504
/* 4055 */    MCD_OPC_CheckField, 28, 4, 0, 139, 35, 0, // Skip to: 13161
5505
/* 4062 */    MCD_OPC_CheckField, 0, 16, 14, 132, 35, 0, // Skip to: 13161
5506
/* 4069 */    MCD_OPC_Decode, 156, 8, 204, 1, // Opcode: AE_MULSF16SS_11
5507
/* 4074 */    MCD_OPC_FilterValue, 137, 128, 64, 90, 0, 0, // Skip to: 4171
5508
/* 4081 */    MCD_OPC_ExtractField, 20, 4,  // Inst{23-20} ...
5509
/* 4084 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4113
5510
/* 4089 */    MCD_OPC_CheckPredicate, 24, 107, 35, 0, // Skip to: 13161
5511
/* 4094 */    MCD_OPC_CheckField, 28, 4, 0, 100, 35, 0, // Skip to: 13161
5512
/* 4101 */    MCD_OPC_CheckField, 0, 16, 14, 93, 35, 0, // Skip to: 13161
5513
/* 4108 */    MCD_OPC_Decode, 158, 8, 204, 1, // Opcode: AE_MULSF16SS_21
5514
/* 4113 */    MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 4142
5515
/* 4118 */    MCD_OPC_CheckPredicate, 24, 78, 35, 0, // Skip to: 13161
5516
/* 4123 */    MCD_OPC_CheckField, 28, 4, 0, 71, 35, 0, // Skip to: 13161
5517
/* 4130 */    MCD_OPC_CheckField, 0, 16, 14, 64, 35, 0, // Skip to: 13161
5518
/* 4137 */    MCD_OPC_Decode, 160, 8, 204, 1, // Opcode: AE_MULSF16SS_30
5519
/* 4142 */    MCD_OPC_FilterValue, 2, 54, 35, 0, // Skip to: 13161
5520
/* 4147 */    MCD_OPC_CheckPredicate, 24, 49, 35, 0, // Skip to: 13161
5521
/* 4152 */    MCD_OPC_CheckField, 28, 4, 0, 42, 35, 0, // Skip to: 13161
5522
/* 4159 */    MCD_OPC_CheckField, 0, 16, 14, 35, 35, 0, // Skip to: 13161
5523
/* 4166 */    MCD_OPC_Decode, 162, 8, 204, 1, // Opcode: AE_MULSF16SS_32
5524
/* 4171 */    MCD_OPC_FilterValue, 139, 128, 64, 23, 35, 0, // Skip to: 13161
5525
/* 4178 */    MCD_OPC_CheckPredicate, 24, 18, 35, 0, // Skip to: 13161
5526
/* 4183 */    MCD_OPC_CheckField, 28, 4, 0, 11, 35, 0, // Skip to: 13161
5527
/* 4190 */    MCD_OPC_CheckField, 20, 4, 7, 4, 35, 0, // Skip to: 13161
5528
/* 4197 */    MCD_OPC_CheckField, 0, 16, 14, 253, 34, 0, // Skip to: 13161
5529
/* 4204 */    MCD_OPC_Decode, 165, 9, 205, 1, // Opcode: AE_MULZSAD32X16_H1_L0
5530
/* 4209 */    MCD_OPC_FilterValue, 4, 38, 0, 0, // Skip to: 4252
5531
/* 4214 */    MCD_OPC_CheckPredicate, 24, 238, 34, 0, // Skip to: 13161
5532
/* 4219 */    MCD_OPC_CheckField, 40, 16, 0, 231, 34, 0, // Skip to: 13161
5533
/* 4226 */    MCD_OPC_CheckField, 32, 4, 0, 224, 34, 0, // Skip to: 13161
5534
/* 4233 */    MCD_OPC_CheckField, 24, 4, 0, 217, 34, 0, // Skip to: 13161
5535
/* 4240 */    MCD_OPC_CheckField, 0, 20, 15, 210, 34, 0, // Skip to: 13161
5536
/* 4247 */    MCD_OPC_Decode, 249, 10, 211, 1, // Opcode: AE_SRLI64
5537
/* 4252 */    MCD_OPC_FilterValue, 8, 89, 0, 0, // Skip to: 4346
5538
/* 4257 */    MCD_OPC_ExtractField, 57, 1,  // Inst{57} ...
5539
/* 4260 */    MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 4303
5540
/* 4265 */    MCD_OPC_CheckPredicate, 24, 187, 34, 0, // Skip to: 13161
5541
/* 4270 */    MCD_OPC_CheckField, 40, 16, 0, 180, 34, 0, // Skip to: 13161
5542
/* 4277 */    MCD_OPC_CheckField, 32, 4, 0, 173, 34, 0, // Skip to: 13161
5543
/* 4284 */    MCD_OPC_CheckField, 24, 4, 0, 166, 34, 0, // Skip to: 13161
5544
/* 4291 */    MCD_OPC_CheckField, 0, 20, 15, 159, 34, 0, // Skip to: 13161
5545
/* 4298 */    MCD_OPC_Decode, 240, 10, 214, 1, // Opcode: AE_SRAI32R
5546
/* 4303 */    MCD_OPC_FilterValue, 1, 149, 34, 0, // Skip to: 13161
5547
/* 4308 */    MCD_OPC_CheckPredicate, 24, 144, 34, 0, // Skip to: 13161
5548
/* 4313 */    MCD_OPC_CheckField, 40, 16, 0, 137, 34, 0, // Skip to: 13161
5549
/* 4320 */    MCD_OPC_CheckField, 32, 4, 0, 130, 34, 0, // Skip to: 13161
5550
/* 4327 */    MCD_OPC_CheckField, 24, 4, 0, 123, 34, 0, // Skip to: 13161
5551
/* 4334 */    MCD_OPC_CheckField, 0, 20, 15, 116, 34, 0, // Skip to: 13161
5552
/* 4341 */    MCD_OPC_Decode, 247, 10, 214, 1, // Opcode: AE_SRLI24
5553
/* 4346 */    MCD_OPC_FilterValue, 9, 79, 0, 0, // Skip to: 4430
5554
/* 4351 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5555
/* 4354 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 4392
5556
/* 4361 */    MCD_OPC_CheckPredicate, 24, 91, 34, 0, // Skip to: 13161
5557
/* 4366 */    MCD_OPC_CheckField, 32, 4, 0, 84, 34, 0, // Skip to: 13161
5558
/* 4373 */    MCD_OPC_CheckField, 24, 4, 0, 77, 34, 0, // Skip to: 13161
5559
/* 4380 */    MCD_OPC_CheckField, 0, 20, 15, 70, 34, 0, // Skip to: 13161
5560
/* 4387 */    MCD_OPC_Decode, 249, 5, 215, 1, // Opcode: AE_MUL32X16_H0_S2
5561
/* 4392 */    MCD_OPC_FilterValue, 128, 128, 12, 58, 34, 0, // Skip to: 13161
5562
/* 4399 */    MCD_OPC_CheckPredicate, 24, 53, 34, 0, // Skip to: 13161
5563
/* 4404 */    MCD_OPC_CheckField, 32, 4, 0, 46, 34, 0, // Skip to: 13161
5564
/* 4411 */    MCD_OPC_CheckField, 24, 4, 0, 39, 34, 0, // Skip to: 13161
5565
/* 4418 */    MCD_OPC_CheckField, 0, 20, 15, 32, 34, 0, // Skip to: 13161
5566
/* 4425 */    MCD_OPC_Decode, 251, 5, 215, 1, // Opcode: AE_MUL32X16_H1_S2
5567
/* 4430 */    MCD_OPC_FilterValue, 10, 153, 0, 0, // Skip to: 4588
5568
/* 4435 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5569
/* 4438 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4474
5570
/* 4443 */    MCD_OPC_CheckPredicate, 24, 9, 34, 0, // Skip to: 13161
5571
/* 4448 */    MCD_OPC_CheckField, 32, 4, 0, 2, 34, 0, // Skip to: 13161
5572
/* 4455 */    MCD_OPC_CheckField, 24, 4, 0, 251, 33, 0, // Skip to: 13161
5573
/* 4462 */    MCD_OPC_CheckField, 0, 20, 15, 244, 33, 0, // Skip to: 13161
5574
/* 4469 */    MCD_OPC_Decode, 253, 5, 215, 1, // Opcode: AE_MUL32X16_H2_S2
5575
/* 4474 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 4512
5576
/* 4481 */    MCD_OPC_CheckPredicate, 24, 227, 33, 0, // Skip to: 13161
5577
/* 4486 */    MCD_OPC_CheckField, 32, 4, 0, 220, 33, 0, // Skip to: 13161
5578
/* 4493 */    MCD_OPC_CheckField, 24, 4, 0, 213, 33, 0, // Skip to: 13161
5579
/* 4500 */    MCD_OPC_CheckField, 0, 20, 15, 206, 33, 0, // Skip to: 13161
5580
/* 4507 */    MCD_OPC_Decode, 255, 5, 215, 1, // Opcode: AE_MUL32X16_H3_S2
5581
/* 4512 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 4550
5582
/* 4519 */    MCD_OPC_CheckPredicate, 24, 189, 33, 0, // Skip to: 13161
5583
/* 4524 */    MCD_OPC_CheckField, 32, 4, 0, 182, 33, 0, // Skip to: 13161
5584
/* 4531 */    MCD_OPC_CheckField, 24, 4, 0, 175, 33, 0, // Skip to: 13161
5585
/* 4538 */    MCD_OPC_CheckField, 0, 20, 15, 168, 33, 0, // Skip to: 13161
5586
/* 4545 */    MCD_OPC_Decode, 129, 6, 215, 1, // Opcode: AE_MUL32X16_L0_S2
5587
/* 4550 */    MCD_OPC_FilterValue, 128, 128, 12, 156, 33, 0, // Skip to: 13161
5588
/* 4557 */    MCD_OPC_CheckPredicate, 24, 151, 33, 0, // Skip to: 13161
5589
/* 4562 */    MCD_OPC_CheckField, 32, 4, 0, 144, 33, 0, // Skip to: 13161
5590
/* 4569 */    MCD_OPC_CheckField, 24, 4, 0, 137, 33, 0, // Skip to: 13161
5591
/* 4576 */    MCD_OPC_CheckField, 0, 20, 15, 130, 33, 0, // Skip to: 13161
5592
/* 4583 */    MCD_OPC_Decode, 131, 6, 215, 1, // Opcode: AE_MUL32X16_L1_S2
5593
/* 4588 */    MCD_OPC_FilterValue, 11, 153, 0, 0, // Skip to: 4746
5594
/* 4593 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5595
/* 4596 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4632
5596
/* 4601 */    MCD_OPC_CheckPredicate, 24, 107, 33, 0, // Skip to: 13161
5597
/* 4606 */    MCD_OPC_CheckField, 32, 4, 0, 100, 33, 0, // Skip to: 13161
5598
/* 4613 */    MCD_OPC_CheckField, 24, 4, 0, 93, 33, 0, // Skip to: 13161
5599
/* 4620 */    MCD_OPC_CheckField, 0, 20, 15, 86, 33, 0, // Skip to: 13161
5600
/* 4627 */    MCD_OPC_Decode, 133, 6, 215, 1, // Opcode: AE_MUL32X16_L2_S2
5601
/* 4632 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 4670
5602
/* 4639 */    MCD_OPC_CheckPredicate, 24, 69, 33, 0, // Skip to: 13161
5603
/* 4644 */    MCD_OPC_CheckField, 32, 4, 0, 62, 33, 0, // Skip to: 13161
5604
/* 4651 */    MCD_OPC_CheckField, 24, 4, 0, 55, 33, 0, // Skip to: 13161
5605
/* 4658 */    MCD_OPC_CheckField, 0, 20, 15, 48, 33, 0, // Skip to: 13161
5606
/* 4665 */    MCD_OPC_Decode, 135, 6, 215, 1, // Opcode: AE_MUL32X16_L3_S2
5607
/* 4670 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 4708
5608
/* 4677 */    MCD_OPC_CheckPredicate, 24, 31, 33, 0, // Skip to: 13161
5609
/* 4682 */    MCD_OPC_CheckField, 32, 4, 0, 24, 33, 0, // Skip to: 13161
5610
/* 4689 */    MCD_OPC_CheckField, 24, 4, 0, 17, 33, 0, // Skip to: 13161
5611
/* 4696 */    MCD_OPC_CheckField, 0, 20, 15, 10, 33, 0, // Skip to: 13161
5612
/* 4703 */    MCD_OPC_Decode, 139, 6, 215, 1, // Opcode: AE_MUL32_LL_S2
5613
/* 4708 */    MCD_OPC_FilterValue, 128, 128, 12, 254, 32, 0, // Skip to: 13161
5614
/* 4715 */    MCD_OPC_CheckPredicate, 24, 249, 32, 0, // Skip to: 13161
5615
/* 4720 */    MCD_OPC_CheckField, 32, 4, 0, 242, 32, 0, // Skip to: 13161
5616
/* 4727 */    MCD_OPC_CheckField, 24, 4, 0, 235, 32, 0, // Skip to: 13161
5617
/* 4734 */    MCD_OPC_CheckField, 0, 20, 15, 228, 32, 0, // Skip to: 13161
5618
/* 4741 */    MCD_OPC_Decode, 143, 6, 216, 1, // Opcode: AE_MULA32X16_H0_S2
5619
/* 4746 */    MCD_OPC_FilterValue, 12, 153, 0, 0, // Skip to: 4904
5620
/* 4751 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5621
/* 4754 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4790
5622
/* 4759 */    MCD_OPC_CheckPredicate, 24, 205, 32, 0, // Skip to: 13161
5623
/* 4764 */    MCD_OPC_CheckField, 32, 4, 0, 198, 32, 0, // Skip to: 13161
5624
/* 4771 */    MCD_OPC_CheckField, 24, 4, 0, 191, 32, 0, // Skip to: 13161
5625
/* 4778 */    MCD_OPC_CheckField, 0, 20, 15, 184, 32, 0, // Skip to: 13161
5626
/* 4785 */    MCD_OPC_Decode, 145, 6, 216, 1, // Opcode: AE_MULA32X16_H1_S2
5627
/* 4790 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 4828
5628
/* 4797 */    MCD_OPC_CheckPredicate, 24, 167, 32, 0, // Skip to: 13161
5629
/* 4802 */    MCD_OPC_CheckField, 32, 4, 0, 160, 32, 0, // Skip to: 13161
5630
/* 4809 */    MCD_OPC_CheckField, 24, 4, 0, 153, 32, 0, // Skip to: 13161
5631
/* 4816 */    MCD_OPC_CheckField, 0, 20, 15, 146, 32, 0, // Skip to: 13161
5632
/* 4823 */    MCD_OPC_Decode, 147, 6, 216, 1, // Opcode: AE_MULA32X16_H2_S2
5633
/* 4828 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 4866
5634
/* 4835 */    MCD_OPC_CheckPredicate, 24, 129, 32, 0, // Skip to: 13161
5635
/* 4840 */    MCD_OPC_CheckField, 32, 4, 0, 122, 32, 0, // Skip to: 13161
5636
/* 4847 */    MCD_OPC_CheckField, 24, 4, 0, 115, 32, 0, // Skip to: 13161
5637
/* 4854 */    MCD_OPC_CheckField, 0, 20, 15, 108, 32, 0, // Skip to: 13161
5638
/* 4861 */    MCD_OPC_Decode, 149, 6, 216, 1, // Opcode: AE_MULA32X16_H3_S2
5639
/* 4866 */    MCD_OPC_FilterValue, 128, 128, 12, 96, 32, 0, // Skip to: 13161
5640
/* 4873 */    MCD_OPC_CheckPredicate, 24, 91, 32, 0, // Skip to: 13161
5641
/* 4878 */    MCD_OPC_CheckField, 32, 4, 0, 84, 32, 0, // Skip to: 13161
5642
/* 4885 */    MCD_OPC_CheckField, 24, 4, 0, 77, 32, 0, // Skip to: 13161
5643
/* 4892 */    MCD_OPC_CheckField, 0, 20, 15, 70, 32, 0, // Skip to: 13161
5644
/* 4899 */    MCD_OPC_Decode, 151, 6, 216, 1, // Opcode: AE_MULA32X16_L0_S2
5645
/* 4904 */    MCD_OPC_FilterValue, 13, 153, 0, 0, // Skip to: 5062
5646
/* 4909 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5647
/* 4912 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4948
5648
/* 4917 */    MCD_OPC_CheckPredicate, 24, 47, 32, 0, // Skip to: 13161
5649
/* 4922 */    MCD_OPC_CheckField, 32, 4, 0, 40, 32, 0, // Skip to: 13161
5650
/* 4929 */    MCD_OPC_CheckField, 24, 4, 0, 33, 32, 0, // Skip to: 13161
5651
/* 4936 */    MCD_OPC_CheckField, 0, 20, 15, 26, 32, 0, // Skip to: 13161
5652
/* 4943 */    MCD_OPC_Decode, 153, 6, 216, 1, // Opcode: AE_MULA32X16_L1_S2
5653
/* 4948 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 4986
5654
/* 4955 */    MCD_OPC_CheckPredicate, 24, 9, 32, 0, // Skip to: 13161
5655
/* 4960 */    MCD_OPC_CheckField, 32, 4, 0, 2, 32, 0, // Skip to: 13161
5656
/* 4967 */    MCD_OPC_CheckField, 24, 4, 0, 251, 31, 0, // Skip to: 13161
5657
/* 4974 */    MCD_OPC_CheckField, 0, 20, 15, 244, 31, 0, // Skip to: 13161
5658
/* 4981 */    MCD_OPC_Decode, 155, 6, 216, 1, // Opcode: AE_MULA32X16_L2_S2
5659
/* 4986 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 5024
5660
/* 4993 */    MCD_OPC_CheckPredicate, 24, 227, 31, 0, // Skip to: 13161
5661
/* 4998 */    MCD_OPC_CheckField, 32, 4, 0, 220, 31, 0, // Skip to: 13161
5662
/* 5005 */    MCD_OPC_CheckField, 24, 4, 0, 213, 31, 0, // Skip to: 13161
5663
/* 5012 */    MCD_OPC_CheckField, 0, 20, 15, 206, 31, 0, // Skip to: 13161
5664
/* 5019 */    MCD_OPC_Decode, 157, 6, 216, 1, // Opcode: AE_MULA32X16_L3_S2
5665
/* 5024 */    MCD_OPC_FilterValue, 128, 128, 12, 194, 31, 0, // Skip to: 13161
5666
/* 5031 */    MCD_OPC_CheckPredicate, 24, 189, 31, 0, // Skip to: 13161
5667
/* 5036 */    MCD_OPC_CheckField, 32, 4, 0, 182, 31, 0, // Skip to: 13161
5668
/* 5043 */    MCD_OPC_CheckField, 24, 4, 0, 175, 31, 0, // Skip to: 13161
5669
/* 5050 */    MCD_OPC_CheckField, 0, 20, 15, 168, 31, 0, // Skip to: 13161
5670
/* 5057 */    MCD_OPC_Decode, 161, 6, 216, 1, // Opcode: AE_MULA32_LL_S2
5671
/* 5062 */    MCD_OPC_FilterValue, 14, 153, 0, 0, // Skip to: 5220
5672
/* 5067 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5673
/* 5070 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5106
5674
/* 5075 */    MCD_OPC_CheckPredicate, 24, 145, 31, 0, // Skip to: 13161
5675
/* 5080 */    MCD_OPC_CheckField, 32, 4, 0, 138, 31, 0, // Skip to: 13161
5676
/* 5087 */    MCD_OPC_CheckField, 24, 4, 0, 131, 31, 0, // Skip to: 13161
5677
/* 5094 */    MCD_OPC_CheckField, 0, 20, 15, 124, 31, 0, // Skip to: 13161
5678
/* 5101 */    MCD_OPC_Decode, 163, 6, 216, 1, // Opcode: AE_MULAAD24_HH_LL_S2
5679
/* 5106 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 5144
5680
/* 5113 */    MCD_OPC_CheckPredicate, 24, 107, 31, 0, // Skip to: 13161
5681
/* 5118 */    MCD_OPC_CheckField, 32, 4, 0, 100, 31, 0, // Skip to: 13161
5682
/* 5125 */    MCD_OPC_CheckField, 24, 4, 0, 93, 31, 0, // Skip to: 13161
5683
/* 5132 */    MCD_OPC_CheckField, 0, 20, 15, 86, 31, 0, // Skip to: 13161
5684
/* 5139 */    MCD_OPC_Decode, 165, 6, 216, 1, // Opcode: AE_MULAAD24_HL_LH_S2
5685
/* 5144 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 5182
5686
/* 5151 */    MCD_OPC_CheckPredicate, 24, 69, 31, 0, // Skip to: 13161
5687
/* 5156 */    MCD_OPC_CheckField, 32, 4, 0, 62, 31, 0, // Skip to: 13161
5688
/* 5163 */    MCD_OPC_CheckField, 24, 4, 0, 55, 31, 0, // Skip to: 13161
5689
/* 5170 */    MCD_OPC_CheckField, 0, 20, 15, 48, 31, 0, // Skip to: 13161
5690
/* 5177 */    MCD_OPC_Decode, 167, 6, 216, 1, // Opcode: AE_MULAAD32X16_H0_L1_S2
5691
/* 5182 */    MCD_OPC_FilterValue, 128, 128, 12, 36, 31, 0, // Skip to: 13161
5692
/* 5189 */    MCD_OPC_CheckPredicate, 24, 31, 31, 0, // Skip to: 13161
5693
/* 5194 */    MCD_OPC_CheckField, 32, 4, 0, 24, 31, 0, // Skip to: 13161
5694
/* 5201 */    MCD_OPC_CheckField, 24, 4, 0, 17, 31, 0, // Skip to: 13161
5695
/* 5208 */    MCD_OPC_CheckField, 0, 20, 15, 10, 31, 0, // Skip to: 13161
5696
/* 5215 */    MCD_OPC_Decode, 169, 6, 216, 1, // Opcode: AE_MULAAD32X16_H1_L0_S2
5697
/* 5220 */    MCD_OPC_FilterValue, 15, 153, 0, 0, // Skip to: 5378
5698
/* 5225 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5699
/* 5228 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5264
5700
/* 5233 */    MCD_OPC_CheckPredicate, 24, 243, 30, 0, // Skip to: 13161
5701
/* 5238 */    MCD_OPC_CheckField, 32, 4, 0, 236, 30, 0, // Skip to: 13161
5702
/* 5245 */    MCD_OPC_CheckField, 24, 4, 0, 229, 30, 0, // Skip to: 13161
5703
/* 5252 */    MCD_OPC_CheckField, 0, 20, 15, 222, 30, 0, // Skip to: 13161
5704
/* 5259 */    MCD_OPC_Decode, 171, 6, 216, 1, // Opcode: AE_MULAAD32X16_H2_L3_S2
5705
/* 5264 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 5302
5706
/* 5271 */    MCD_OPC_CheckPredicate, 24, 205, 30, 0, // Skip to: 13161
5707
/* 5276 */    MCD_OPC_CheckField, 32, 4, 0, 198, 30, 0, // Skip to: 13161
5708
/* 5283 */    MCD_OPC_CheckField, 24, 4, 0, 191, 30, 0, // Skip to: 13161
5709
/* 5290 */    MCD_OPC_CheckField, 0, 20, 15, 184, 30, 0, // Skip to: 13161
5710
/* 5297 */    MCD_OPC_Decode, 173, 6, 216, 1, // Opcode: AE_MULAAD32X16_H3_L2_S2
5711
/* 5302 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 5340
5712
/* 5309 */    MCD_OPC_CheckPredicate, 24, 167, 30, 0, // Skip to: 13161
5713
/* 5314 */    MCD_OPC_CheckField, 32, 4, 0, 160, 30, 0, // Skip to: 13161
5714
/* 5321 */    MCD_OPC_CheckField, 24, 4, 0, 153, 30, 0, // Skip to: 13161
5715
/* 5328 */    MCD_OPC_CheckField, 0, 20, 15, 146, 30, 0, // Skip to: 13161
5716
/* 5335 */    MCD_OPC_Decode, 175, 6, 216, 1, // Opcode: AE_MULAAFD16SS_11_00_S2
5717
/* 5340 */    MCD_OPC_FilterValue, 128, 128, 12, 134, 30, 0, // Skip to: 13161
5718
/* 5347 */    MCD_OPC_CheckPredicate, 24, 129, 30, 0, // Skip to: 13161
5719
/* 5352 */    MCD_OPC_CheckField, 32, 4, 0, 122, 30, 0, // Skip to: 13161
5720
/* 5359 */    MCD_OPC_CheckField, 24, 4, 0, 115, 30, 0, // Skip to: 13161
5721
/* 5366 */    MCD_OPC_CheckField, 0, 20, 15, 108, 30, 0, // Skip to: 13161
5722
/* 5373 */    MCD_OPC_Decode, 177, 6, 216, 1, // Opcode: AE_MULAAFD16SS_13_02_S2
5723
/* 5378 */    MCD_OPC_FilterValue, 16, 153, 0, 0, // Skip to: 5536
5724
/* 5383 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5725
/* 5386 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5422
5726
/* 5391 */    MCD_OPC_CheckPredicate, 24, 85, 30, 0, // Skip to: 13161
5727
/* 5396 */    MCD_OPC_CheckField, 32, 4, 0, 78, 30, 0, // Skip to: 13161
5728
/* 5403 */    MCD_OPC_CheckField, 24, 4, 0, 71, 30, 0, // Skip to: 13161
5729
/* 5410 */    MCD_OPC_CheckField, 0, 20, 15, 64, 30, 0, // Skip to: 13161
5730
/* 5417 */    MCD_OPC_Decode, 179, 6, 216, 1, // Opcode: AE_MULAAFD16SS_33_22_S2
5731
/* 5422 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 5460
5732
/* 5429 */    MCD_OPC_CheckPredicate, 24, 47, 30, 0, // Skip to: 13161
5733
/* 5434 */    MCD_OPC_CheckField, 32, 4, 0, 40, 30, 0, // Skip to: 13161
5734
/* 5441 */    MCD_OPC_CheckField, 24, 4, 0, 33, 30, 0, // Skip to: 13161
5735
/* 5448 */    MCD_OPC_CheckField, 0, 20, 15, 26, 30, 0, // Skip to: 13161
5736
/* 5455 */    MCD_OPC_Decode, 181, 6, 216, 1, // Opcode: AE_MULAAFD24_HH_LL_S2
5737
/* 5460 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 5498
5738
/* 5467 */    MCD_OPC_CheckPredicate, 24, 9, 30, 0, // Skip to: 13161
5739
/* 5472 */    MCD_OPC_CheckField, 32, 4, 0, 2, 30, 0, // Skip to: 13161
5740
/* 5479 */    MCD_OPC_CheckField, 24, 4, 0, 251, 29, 0, // Skip to: 13161
5741
/* 5486 */    MCD_OPC_CheckField, 0, 20, 15, 244, 29, 0, // Skip to: 13161
5742
/* 5493 */    MCD_OPC_Decode, 183, 6, 216, 1, // Opcode: AE_MULAAFD24_HL_LH_S2
5743
/* 5498 */    MCD_OPC_FilterValue, 128, 128, 12, 232, 29, 0, // Skip to: 13161
5744
/* 5505 */    MCD_OPC_CheckPredicate, 24, 227, 29, 0, // Skip to: 13161
5745
/* 5510 */    MCD_OPC_CheckField, 32, 4, 0, 220, 29, 0, // Skip to: 13161
5746
/* 5517 */    MCD_OPC_CheckField, 24, 4, 0, 213, 29, 0, // Skip to: 13161
5747
/* 5524 */    MCD_OPC_CheckField, 0, 20, 15, 206, 29, 0, // Skip to: 13161
5748
/* 5531 */    MCD_OPC_Decode, 185, 6, 216, 1, // Opcode: AE_MULAAFD32X16_H0_L1_S2
5749
/* 5536 */    MCD_OPC_FilterValue, 17, 153, 0, 0, // Skip to: 5694
5750
/* 5541 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5751
/* 5544 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5580
5752
/* 5549 */    MCD_OPC_CheckPredicate, 24, 183, 29, 0, // Skip to: 13161
5753
/* 5554 */    MCD_OPC_CheckField, 32, 4, 0, 176, 29, 0, // Skip to: 13161
5754
/* 5561 */    MCD_OPC_CheckField, 24, 4, 0, 169, 29, 0, // Skip to: 13161
5755
/* 5568 */    MCD_OPC_CheckField, 0, 20, 15, 162, 29, 0, // Skip to: 13161
5756
/* 5575 */    MCD_OPC_Decode, 187, 6, 216, 1, // Opcode: AE_MULAAFD32X16_H1_L0_S2
5757
/* 5580 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 5618
5758
/* 5587 */    MCD_OPC_CheckPredicate, 24, 145, 29, 0, // Skip to: 13161
5759
/* 5592 */    MCD_OPC_CheckField, 32, 4, 0, 138, 29, 0, // Skip to: 13161
5760
/* 5599 */    MCD_OPC_CheckField, 24, 4, 0, 131, 29, 0, // Skip to: 13161
5761
/* 5606 */    MCD_OPC_CheckField, 0, 20, 15, 124, 29, 0, // Skip to: 13161
5762
/* 5613 */    MCD_OPC_Decode, 189, 6, 216, 1, // Opcode: AE_MULAAFD32X16_H2_L3_S2
5763
/* 5618 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 5656
5764
/* 5625 */    MCD_OPC_CheckPredicate, 24, 107, 29, 0, // Skip to: 13161
5765
/* 5630 */    MCD_OPC_CheckField, 32, 4, 0, 100, 29, 0, // Skip to: 13161
5766
/* 5637 */    MCD_OPC_CheckField, 24, 4, 0, 93, 29, 0, // Skip to: 13161
5767
/* 5644 */    MCD_OPC_CheckField, 0, 20, 15, 86, 29, 0, // Skip to: 13161
5768
/* 5651 */    MCD_OPC_Decode, 191, 6, 216, 1, // Opcode: AE_MULAAFD32X16_H3_L2_S2
5769
/* 5656 */    MCD_OPC_FilterValue, 128, 128, 12, 74, 29, 0, // Skip to: 13161
5770
/* 5663 */    MCD_OPC_CheckPredicate, 24, 69, 29, 0, // Skip to: 13161
5771
/* 5668 */    MCD_OPC_CheckField, 32, 4, 0, 62, 29, 0, // Skip to: 13161
5772
/* 5675 */    MCD_OPC_CheckField, 24, 4, 0, 55, 29, 0, // Skip to: 13161
5773
/* 5682 */    MCD_OPC_CheckField, 0, 20, 15, 48, 29, 0, // Skip to: 13161
5774
/* 5689 */    MCD_OPC_Decode, 196, 6, 216, 1, // Opcode: AE_MULAF16SS_00_S2
5775
/* 5694 */    MCD_OPC_FilterValue, 18, 153, 0, 0, // Skip to: 5852
5776
/* 5699 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5777
/* 5702 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5738
5778
/* 5707 */    MCD_OPC_CheckPredicate, 24, 25, 29, 0, // Skip to: 13161
5779
/* 5712 */    MCD_OPC_CheckField, 32, 4, 0, 18, 29, 0, // Skip to: 13161
5780
/* 5719 */    MCD_OPC_CheckField, 24, 4, 0, 11, 29, 0, // Skip to: 13161
5781
/* 5726 */    MCD_OPC_CheckField, 0, 20, 15, 4, 29, 0, // Skip to: 13161
5782
/* 5733 */    MCD_OPC_Decode, 210, 6, 216, 1, // Opcode: AE_MULAF32R_LL_S2
5783
/* 5738 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 5776
5784
/* 5745 */    MCD_OPC_CheckPredicate, 24, 243, 28, 0, // Skip to: 13161
5785
/* 5750 */    MCD_OPC_CheckField, 32, 4, 0, 236, 28, 0, // Skip to: 13161
5786
/* 5757 */    MCD_OPC_CheckField, 24, 4, 0, 229, 28, 0, // Skip to: 13161
5787
/* 5764 */    MCD_OPC_CheckField, 0, 20, 15, 222, 28, 0, // Skip to: 13161
5788
/* 5771 */    MCD_OPC_Decode, 214, 6, 216, 1, // Opcode: AE_MULAF32S_LL_S2
5789
/* 5776 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 5814
5790
/* 5783 */    MCD_OPC_CheckPredicate, 24, 205, 28, 0, // Skip to: 13161
5791
/* 5788 */    MCD_OPC_CheckField, 32, 4, 0, 198, 28, 0, // Skip to: 13161
5792
/* 5795 */    MCD_OPC_CheckField, 24, 4, 0, 191, 28, 0, // Skip to: 13161
5793
/* 5802 */    MCD_OPC_CheckField, 0, 20, 15, 184, 28, 0, // Skip to: 13161
5794
/* 5809 */    MCD_OPC_Decode, 216, 6, 216, 1, // Opcode: AE_MULAF32X16_H0_S2
5795
/* 5814 */    MCD_OPC_FilterValue, 128, 128, 12, 172, 28, 0, // Skip to: 13161
5796
/* 5821 */    MCD_OPC_CheckPredicate, 24, 167, 28, 0, // Skip to: 13161
5797
/* 5826 */    MCD_OPC_CheckField, 32, 4, 0, 160, 28, 0, // Skip to: 13161
5798
/* 5833 */    MCD_OPC_CheckField, 24, 4, 0, 153, 28, 0, // Skip to: 13161
5799
/* 5840 */    MCD_OPC_CheckField, 0, 20, 15, 146, 28, 0, // Skip to: 13161
5800
/* 5847 */    MCD_OPC_Decode, 218, 6, 216, 1, // Opcode: AE_MULAF32X16_H1_S2
5801
/* 5852 */    MCD_OPC_FilterValue, 19, 153, 0, 0, // Skip to: 6010
5802
/* 5857 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5803
/* 5860 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5896
5804
/* 5865 */    MCD_OPC_CheckPredicate, 24, 123, 28, 0, // Skip to: 13161
5805
/* 5870 */    MCD_OPC_CheckField, 32, 4, 0, 116, 28, 0, // Skip to: 13161
5806
/* 5877 */    MCD_OPC_CheckField, 24, 4, 0, 109, 28, 0, // Skip to: 13161
5807
/* 5884 */    MCD_OPC_CheckField, 0, 20, 15, 102, 28, 0, // Skip to: 13161
5808
/* 5891 */    MCD_OPC_Decode, 220, 6, 216, 1, // Opcode: AE_MULAF32X16_H2_S2
5809
/* 5896 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 5934
5810
/* 5903 */    MCD_OPC_CheckPredicate, 24, 85, 28, 0, // Skip to: 13161
5811
/* 5908 */    MCD_OPC_CheckField, 32, 4, 0, 78, 28, 0, // Skip to: 13161
5812
/* 5915 */    MCD_OPC_CheckField, 24, 4, 0, 71, 28, 0, // Skip to: 13161
5813
/* 5922 */    MCD_OPC_CheckField, 0, 20, 15, 64, 28, 0, // Skip to: 13161
5814
/* 5929 */    MCD_OPC_Decode, 222, 6, 216, 1, // Opcode: AE_MULAF32X16_H3_S2
5815
/* 5934 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 5972
5816
/* 5941 */    MCD_OPC_CheckPredicate, 24, 47, 28, 0, // Skip to: 13161
5817
/* 5946 */    MCD_OPC_CheckField, 32, 4, 0, 40, 28, 0, // Skip to: 13161
5818
/* 5953 */    MCD_OPC_CheckField, 24, 4, 0, 33, 28, 0, // Skip to: 13161
5819
/* 5960 */    MCD_OPC_CheckField, 0, 20, 15, 26, 28, 0, // Skip to: 13161
5820
/* 5967 */    MCD_OPC_Decode, 224, 6, 216, 1, // Opcode: AE_MULAF32X16_L0_S2
5821
/* 5972 */    MCD_OPC_FilterValue, 128, 128, 12, 14, 28, 0, // Skip to: 13161
5822
/* 5979 */    MCD_OPC_CheckPredicate, 24, 9, 28, 0, // Skip to: 13161
5823
/* 5984 */    MCD_OPC_CheckField, 32, 4, 0, 2, 28, 0, // Skip to: 13161
5824
/* 5991 */    MCD_OPC_CheckField, 24, 4, 0, 251, 27, 0, // Skip to: 13161
5825
/* 5998 */    MCD_OPC_CheckField, 0, 20, 15, 244, 27, 0, // Skip to: 13161
5826
/* 6005 */    MCD_OPC_Decode, 226, 6, 216, 1, // Opcode: AE_MULAF32X16_L1_S2
5827
/* 6010 */    MCD_OPC_FilterValue, 20, 153, 0, 0, // Skip to: 6168
5828
/* 6015 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5829
/* 6018 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6054
5830
/* 6023 */    MCD_OPC_CheckPredicate, 24, 221, 27, 0, // Skip to: 13161
5831
/* 6028 */    MCD_OPC_CheckField, 32, 4, 0, 214, 27, 0, // Skip to: 13161
5832
/* 6035 */    MCD_OPC_CheckField, 24, 4, 0, 207, 27, 0, // Skip to: 13161
5833
/* 6042 */    MCD_OPC_CheckField, 0, 20, 15, 200, 27, 0, // Skip to: 13161
5834
/* 6049 */    MCD_OPC_Decode, 228, 6, 216, 1, // Opcode: AE_MULAF32X16_L2_S2
5835
/* 6054 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 6092
5836
/* 6061 */    MCD_OPC_CheckPredicate, 24, 183, 27, 0, // Skip to: 13161
5837
/* 6066 */    MCD_OPC_CheckField, 32, 4, 0, 176, 27, 0, // Skip to: 13161
5838
/* 6073 */    MCD_OPC_CheckField, 24, 4, 0, 169, 27, 0, // Skip to: 13161
5839
/* 6080 */    MCD_OPC_CheckField, 0, 20, 15, 162, 27, 0, // Skip to: 13161
5840
/* 6087 */    MCD_OPC_Decode, 230, 6, 216, 1, // Opcode: AE_MULAF32X16_L3_S2
5841
/* 6092 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 6130
5842
/* 6099 */    MCD_OPC_CheckPredicate, 24, 145, 27, 0, // Skip to: 13161
5843
/* 6104 */    MCD_OPC_CheckField, 32, 4, 0, 138, 27, 0, // Skip to: 13161
5844
/* 6111 */    MCD_OPC_CheckField, 24, 4, 0, 131, 27, 0, // Skip to: 13161
5845
/* 6118 */    MCD_OPC_CheckField, 0, 20, 15, 124, 27, 0, // Skip to: 13161
5846
/* 6125 */    MCD_OPC_Decode, 232, 6, 216, 1, // Opcode: AE_MULAF48Q32SP16S_L_S2
5847
/* 6130 */    MCD_OPC_FilterValue, 128, 128, 12, 112, 27, 0, // Skip to: 13161
5848
/* 6137 */    MCD_OPC_CheckPredicate, 24, 107, 27, 0, // Skip to: 13161
5849
/* 6142 */    MCD_OPC_CheckField, 32, 4, 0, 100, 27, 0, // Skip to: 13161
5850
/* 6149 */    MCD_OPC_CheckField, 24, 4, 0, 93, 27, 0, // Skip to: 13161
5851
/* 6156 */    MCD_OPC_CheckField, 0, 20, 15, 86, 27, 0, // Skip to: 13161
5852
/* 6163 */    MCD_OPC_Decode, 234, 6, 216, 1, // Opcode: AE_MULAF48Q32SP16U_L_S2
5853
/* 6168 */    MCD_OPC_FilterValue, 21, 153, 0, 0, // Skip to: 6326
5854
/* 6173 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5855
/* 6176 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6212
5856
/* 6181 */    MCD_OPC_CheckPredicate, 24, 63, 27, 0, // Skip to: 13161
5857
/* 6186 */    MCD_OPC_CheckField, 32, 4, 0, 56, 27, 0, // Skip to: 13161
5858
/* 6193 */    MCD_OPC_CheckField, 24, 4, 0, 49, 27, 0, // Skip to: 13161
5859
/* 6200 */    MCD_OPC_CheckField, 0, 20, 15, 42, 27, 0, // Skip to: 13161
5860
/* 6207 */    MCD_OPC_Decode, 246, 6, 216, 1, // Opcode: AE_MULAFP24X2RA_S2
5861
/* 6212 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 6250
5862
/* 6219 */    MCD_OPC_CheckPredicate, 24, 25, 27, 0, // Skip to: 13161
5863
/* 6224 */    MCD_OPC_CheckField, 32, 4, 0, 18, 27, 0, // Skip to: 13161
5864
/* 6231 */    MCD_OPC_CheckField, 24, 4, 0, 11, 27, 0, // Skip to: 13161
5865
/* 6238 */    MCD_OPC_CheckField, 0, 20, 15, 4, 27, 0, // Skip to: 13161
5866
/* 6245 */    MCD_OPC_Decode, 247, 6, 216, 1, // Opcode: AE_MULAFP24X2R_S2
5867
/* 6250 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 6288
5868
/* 6257 */    MCD_OPC_CheckPredicate, 24, 243, 26, 0, // Skip to: 13161
5869
/* 6262 */    MCD_OPC_CheckField, 32, 4, 0, 236, 26, 0, // Skip to: 13161
5870
/* 6269 */    MCD_OPC_CheckField, 24, 4, 0, 229, 26, 0, // Skip to: 13161
5871
/* 6276 */    MCD_OPC_CheckField, 0, 20, 15, 222, 26, 0, // Skip to: 13161
5872
/* 6283 */    MCD_OPC_Decode, 249, 6, 216, 1, // Opcode: AE_MULAFP32X16X2RAS_H_S2
5873
/* 6288 */    MCD_OPC_FilterValue, 128, 128, 12, 210, 26, 0, // Skip to: 13161
5874
/* 6295 */    MCD_OPC_CheckPredicate, 24, 205, 26, 0, // Skip to: 13161
5875
/* 6300 */    MCD_OPC_CheckField, 32, 4, 0, 198, 26, 0, // Skip to: 13161
5876
/* 6307 */    MCD_OPC_CheckField, 24, 4, 0, 191, 26, 0, // Skip to: 13161
5877
/* 6314 */    MCD_OPC_CheckField, 0, 20, 15, 184, 26, 0, // Skip to: 13161
5878
/* 6321 */    MCD_OPC_Decode, 251, 6, 216, 1, // Opcode: AE_MULAFP32X16X2RAS_L_S2
5879
/* 6326 */    MCD_OPC_FilterValue, 22, 153, 0, 0, // Skip to: 6484
5880
/* 6331 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5881
/* 6334 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6370
5882
/* 6339 */    MCD_OPC_CheckPredicate, 24, 161, 26, 0, // Skip to: 13161
5883
/* 6344 */    MCD_OPC_CheckField, 32, 4, 0, 154, 26, 0, // Skip to: 13161
5884
/* 6351 */    MCD_OPC_CheckField, 24, 4, 0, 147, 26, 0, // Skip to: 13161
5885
/* 6358 */    MCD_OPC_CheckField, 0, 20, 15, 140, 26, 0, // Skip to: 13161
5886
/* 6365 */    MCD_OPC_Decode, 253, 6, 216, 1, // Opcode: AE_MULAFP32X16X2RS_H_S2
5887
/* 6370 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 6408
5888
/* 6377 */    MCD_OPC_CheckPredicate, 24, 123, 26, 0, // Skip to: 13161
5889
/* 6382 */    MCD_OPC_CheckField, 32, 4, 0, 116, 26, 0, // Skip to: 13161
5890
/* 6389 */    MCD_OPC_CheckField, 24, 4, 0, 109, 26, 0, // Skip to: 13161
5891
/* 6396 */    MCD_OPC_CheckField, 0, 20, 15, 102, 26, 0, // Skip to: 13161
5892
/* 6403 */    MCD_OPC_Decode, 255, 6, 216, 1, // Opcode: AE_MULAFP32X16X2RS_L_S2
5893
/* 6408 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 6446
5894
/* 6415 */    MCD_OPC_CheckPredicate, 24, 85, 26, 0, // Skip to: 13161
5895
/* 6420 */    MCD_OPC_CheckField, 32, 4, 0, 78, 26, 0, // Skip to: 13161
5896
/* 6427 */    MCD_OPC_CheckField, 24, 4, 0, 71, 26, 0, // Skip to: 13161
5897
/* 6434 */    MCD_OPC_CheckField, 0, 20, 15, 64, 26, 0, // Skip to: 13161
5898
/* 6441 */    MCD_OPC_Decode, 130, 7, 216, 1, // Opcode: AE_MULAFQ32SP24S_H_S2
5899
/* 6446 */    MCD_OPC_FilterValue, 128, 128, 12, 52, 26, 0, // Skip to: 13161
5900
/* 6453 */    MCD_OPC_CheckPredicate, 24, 47, 26, 0, // Skip to: 13161
5901
/* 6458 */    MCD_OPC_CheckField, 32, 4, 0, 40, 26, 0, // Skip to: 13161
5902
/* 6465 */    MCD_OPC_CheckField, 24, 4, 0, 33, 26, 0, // Skip to: 13161
5903
/* 6472 */    MCD_OPC_CheckField, 0, 20, 15, 26, 26, 0, // Skip to: 13161
5904
/* 6479 */    MCD_OPC_Decode, 131, 7, 216, 1, // Opcode: AE_MULAFQ32SP24S_L_S2
5905
/* 6484 */    MCD_OPC_FilterValue, 23, 153, 0, 0, // Skip to: 6642
5906
/* 6489 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5907
/* 6492 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6528
5908
/* 6497 */    MCD_OPC_CheckPredicate, 24, 3, 26, 0, // Skip to: 13161
5909
/* 6502 */    MCD_OPC_CheckField, 32, 4, 0, 252, 25, 0, // Skip to: 13161
5910
/* 6509 */    MCD_OPC_CheckField, 24, 4, 0, 245, 25, 0, // Skip to: 13161
5911
/* 6516 */    MCD_OPC_CheckField, 0, 20, 15, 238, 25, 0, // Skip to: 13161
5912
/* 6523 */    MCD_OPC_Decode, 133, 7, 216, 1, // Opcode: AE_MULAP24X2_S2
5913
/* 6528 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 6566
5914
/* 6535 */    MCD_OPC_CheckPredicate, 24, 221, 25, 0, // Skip to: 13161
5915
/* 6540 */    MCD_OPC_CheckField, 32, 4, 0, 214, 25, 0, // Skip to: 13161
5916
/* 6547 */    MCD_OPC_CheckField, 24, 4, 0, 207, 25, 0, // Skip to: 13161
5917
/* 6554 */    MCD_OPC_CheckField, 0, 20, 15, 200, 25, 0, // Skip to: 13161
5918
/* 6561 */    MCD_OPC_Decode, 137, 7, 216, 1, // Opcode: AE_MULAQ32SP16S_L_S2
5919
/* 6566 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 6604
5920
/* 6573 */    MCD_OPC_CheckPredicate, 24, 183, 25, 0, // Skip to: 13161
5921
/* 6578 */    MCD_OPC_CheckField, 32, 4, 0, 176, 25, 0, // Skip to: 13161
5922
/* 6585 */    MCD_OPC_CheckField, 24, 4, 0, 169, 25, 0, // Skip to: 13161
5923
/* 6592 */    MCD_OPC_CheckField, 0, 20, 15, 162, 25, 0, // Skip to: 13161
5924
/* 6599 */    MCD_OPC_Decode, 138, 7, 216, 1, // Opcode: AE_MULAQ32SP16U_L_S2
5925
/* 6604 */    MCD_OPC_FilterValue, 128, 128, 12, 150, 25, 0, // Skip to: 13161
5926
/* 6611 */    MCD_OPC_CheckPredicate, 24, 145, 25, 0, // Skip to: 13161
5927
/* 6616 */    MCD_OPC_CheckField, 32, 4, 0, 138, 25, 0, // Skip to: 13161
5928
/* 6623 */    MCD_OPC_CheckField, 24, 4, 0, 131, 25, 0, // Skip to: 13161
5929
/* 6630 */    MCD_OPC_CheckField, 0, 20, 15, 124, 25, 0, // Skip to: 13161
5930
/* 6637 */    MCD_OPC_Decode, 139, 7, 216, 1, // Opcode: AE_MULARFQ32SP24S_H_S2
5931
/* 6642 */    MCD_OPC_FilterValue, 24, 153, 0, 0, // Skip to: 6800
5932
/* 6647 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5933
/* 6650 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6686
5934
/* 6655 */    MCD_OPC_CheckPredicate, 24, 101, 25, 0, // Skip to: 13161
5935
/* 6660 */    MCD_OPC_CheckField, 32, 4, 0, 94, 25, 0, // Skip to: 13161
5936
/* 6667 */    MCD_OPC_CheckField, 24, 4, 0, 87, 25, 0, // Skip to: 13161
5937
/* 6674 */    MCD_OPC_CheckField, 0, 20, 15, 80, 25, 0, // Skip to: 13161
5938
/* 6681 */    MCD_OPC_Decode, 140, 7, 216, 1, // Opcode: AE_MULARFQ32SP24S_L_S2
5939
/* 6686 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 6724
5940
/* 6693 */    MCD_OPC_CheckPredicate, 24, 63, 25, 0, // Skip to: 13161
5941
/* 6698 */    MCD_OPC_CheckField, 32, 4, 0, 56, 25, 0, // Skip to: 13161
5942
/* 6705 */    MCD_OPC_CheckField, 24, 4, 0, 49, 25, 0, // Skip to: 13161
5943
/* 6712 */    MCD_OPC_CheckField, 0, 20, 15, 42, 25, 0, // Skip to: 13161
5944
/* 6719 */    MCD_OPC_Decode, 142, 7, 216, 1, // Opcode: AE_MULAS32F48P16S_HH_S2
5945
/* 6724 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 6762
5946
/* 6731 */    MCD_OPC_CheckPredicate, 24, 25, 25, 0, // Skip to: 13161
5947
/* 6736 */    MCD_OPC_CheckField, 32, 4, 0, 18, 25, 0, // Skip to: 13161
5948
/* 6743 */    MCD_OPC_CheckField, 24, 4, 0, 11, 25, 0, // Skip to: 13161
5949
/* 6750 */    MCD_OPC_CheckField, 0, 20, 15, 4, 25, 0, // Skip to: 13161
5950
/* 6757 */    MCD_OPC_Decode, 144, 7, 216, 1, // Opcode: AE_MULAS32F48P16S_LH_S2
5951
/* 6762 */    MCD_OPC_FilterValue, 128, 128, 12, 248, 24, 0, // Skip to: 13161
5952
/* 6769 */    MCD_OPC_CheckPredicate, 24, 243, 24, 0, // Skip to: 13161
5953
/* 6774 */    MCD_OPC_CheckField, 32, 4, 0, 236, 24, 0, // Skip to: 13161
5954
/* 6781 */    MCD_OPC_CheckField, 24, 4, 0, 229, 24, 0, // Skip to: 13161
5955
/* 6788 */    MCD_OPC_CheckField, 0, 20, 15, 222, 24, 0, // Skip to: 13161
5956
/* 6795 */    MCD_OPC_Decode, 146, 7, 216, 1, // Opcode: AE_MULAS32F48P16S_LL_S2
5957
/* 6800 */    MCD_OPC_FilterValue, 25, 153, 0, 0, // Skip to: 6958
5958
/* 6805 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5959
/* 6808 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6844
5960
/* 6813 */    MCD_OPC_CheckPredicate, 24, 199, 24, 0, // Skip to: 13161
5961
/* 6818 */    MCD_OPC_CheckField, 32, 4, 0, 192, 24, 0, // Skip to: 13161
5962
/* 6825 */    MCD_OPC_CheckField, 24, 4, 0, 185, 24, 0, // Skip to: 13161
5963
/* 6832 */    MCD_OPC_CheckField, 0, 20, 15, 178, 24, 0, // Skip to: 13161
5964
/* 6839 */    MCD_OPC_Decode, 148, 7, 216, 1, // Opcode: AE_MULASD24_HH_LL_S2
5965
/* 6844 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 6882
5966
/* 6851 */    MCD_OPC_CheckPredicate, 24, 161, 24, 0, // Skip to: 13161
5967
/* 6856 */    MCD_OPC_CheckField, 32, 4, 0, 154, 24, 0, // Skip to: 13161
5968
/* 6863 */    MCD_OPC_CheckField, 24, 4, 0, 147, 24, 0, // Skip to: 13161
5969
/* 6870 */    MCD_OPC_CheckField, 0, 20, 15, 140, 24, 0, // Skip to: 13161
5970
/* 6877 */    MCD_OPC_Decode, 150, 7, 216, 1, // Opcode: AE_MULASD24_HL_LH_S2
5971
/* 6882 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 6920
5972
/* 6889 */    MCD_OPC_CheckPredicate, 24, 123, 24, 0, // Skip to: 13161
5973
/* 6894 */    MCD_OPC_CheckField, 32, 4, 0, 116, 24, 0, // Skip to: 13161
5974
/* 6901 */    MCD_OPC_CheckField, 24, 4, 0, 109, 24, 0, // Skip to: 13161
5975
/* 6908 */    MCD_OPC_CheckField, 0, 20, 15, 102, 24, 0, // Skip to: 13161
5976
/* 6915 */    MCD_OPC_Decode, 152, 7, 216, 1, // Opcode: AE_MULASD32X16_H1_L0_S2
5977
/* 6920 */    MCD_OPC_FilterValue, 128, 128, 12, 90, 24, 0, // Skip to: 13161
5978
/* 6927 */    MCD_OPC_CheckPredicate, 24, 85, 24, 0, // Skip to: 13161
5979
/* 6932 */    MCD_OPC_CheckField, 32, 4, 0, 78, 24, 0, // Skip to: 13161
5980
/* 6939 */    MCD_OPC_CheckField, 24, 4, 0, 71, 24, 0, // Skip to: 13161
5981
/* 6946 */    MCD_OPC_CheckField, 0, 20, 15, 64, 24, 0, // Skip to: 13161
5982
/* 6953 */    MCD_OPC_Decode, 154, 7, 216, 1, // Opcode: AE_MULASD32X16_H3_L2_S2
5983
/* 6958 */    MCD_OPC_FilterValue, 26, 153, 0, 0, // Skip to: 7116
5984
/* 6963 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
5985
/* 6966 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7002
5986
/* 6971 */    MCD_OPC_CheckPredicate, 24, 41, 24, 0, // Skip to: 13161
5987
/* 6976 */    MCD_OPC_CheckField, 32, 4, 0, 34, 24, 0, // Skip to: 13161
5988
/* 6983 */    MCD_OPC_CheckField, 24, 4, 0, 27, 24, 0, // Skip to: 13161
5989
/* 6990 */    MCD_OPC_CheckField, 0, 20, 15, 20, 24, 0, // Skip to: 13161
5990
/* 6997 */    MCD_OPC_Decode, 156, 7, 216, 1, // Opcode: AE_MULASFD24_HH_LL_S2
5991
/* 7002 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 7040
5992
/* 7009 */    MCD_OPC_CheckPredicate, 24, 3, 24, 0, // Skip to: 13161
5993
/* 7014 */    MCD_OPC_CheckField, 32, 4, 0, 252, 23, 0, // Skip to: 13161
5994
/* 7021 */    MCD_OPC_CheckField, 24, 4, 0, 245, 23, 0, // Skip to: 13161
5995
/* 7028 */    MCD_OPC_CheckField, 0, 20, 15, 238, 23, 0, // Skip to: 13161
5996
/* 7035 */    MCD_OPC_Decode, 158, 7, 216, 1, // Opcode: AE_MULASFD24_HL_LH_S2
5997
/* 7040 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 7078
5998
/* 7047 */    MCD_OPC_CheckPredicate, 24, 221, 23, 0, // Skip to: 13161
5999
/* 7052 */    MCD_OPC_CheckField, 32, 4, 0, 214, 23, 0, // Skip to: 13161
6000
/* 7059 */    MCD_OPC_CheckField, 24, 4, 0, 207, 23, 0, // Skip to: 13161
6001
/* 7066 */    MCD_OPC_CheckField, 0, 20, 15, 200, 23, 0, // Skip to: 13161
6002
/* 7073 */    MCD_OPC_Decode, 160, 7, 216, 1, // Opcode: AE_MULASFD32X16_H1_L0_S2
6003
/* 7078 */    MCD_OPC_FilterValue, 128, 128, 12, 188, 23, 0, // Skip to: 13161
6004
/* 7085 */    MCD_OPC_CheckPredicate, 24, 183, 23, 0, // Skip to: 13161
6005
/* 7090 */    MCD_OPC_CheckField, 32, 4, 0, 176, 23, 0, // Skip to: 13161
6006
/* 7097 */    MCD_OPC_CheckField, 24, 4, 0, 169, 23, 0, // Skip to: 13161
6007
/* 7104 */    MCD_OPC_CheckField, 0, 20, 15, 162, 23, 0, // Skip to: 13161
6008
/* 7111 */    MCD_OPC_Decode, 162, 7, 216, 1, // Opcode: AE_MULASFD32X16_H3_L2_S2
6009
/* 7116 */    MCD_OPC_FilterValue, 27, 153, 0, 0, // Skip to: 7274
6010
/* 7121 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6011
/* 7124 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7160
6012
/* 7129 */    MCD_OPC_CheckPredicate, 24, 139, 23, 0, // Skip to: 13161
6013
/* 7134 */    MCD_OPC_CheckField, 32, 4, 0, 132, 23, 0, // Skip to: 13161
6014
/* 7141 */    MCD_OPC_CheckField, 24, 4, 0, 125, 23, 0, // Skip to: 13161
6015
/* 7148 */    MCD_OPC_CheckField, 0, 20, 15, 118, 23, 0, // Skip to: 13161
6016
/* 7155 */    MCD_OPC_Decode, 167, 7, 215, 1, // Opcode: AE_MULF16SS_00_S2
6017
/* 7160 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 7198
6018
/* 7167 */    MCD_OPC_CheckPredicate, 24, 101, 23, 0, // Skip to: 13161
6019
/* 7172 */    MCD_OPC_CheckField, 32, 4, 0, 94, 23, 0, // Skip to: 13161
6020
/* 7179 */    MCD_OPC_CheckField, 24, 4, 0, 87, 23, 0, // Skip to: 13161
6021
/* 7186 */    MCD_OPC_CheckField, 0, 20, 15, 80, 23, 0, // Skip to: 13161
6022
/* 7193 */    MCD_OPC_Decode, 181, 7, 215, 1, // Opcode: AE_MULF32R_LL_S2
6023
/* 7198 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 7236
6024
/* 7205 */    MCD_OPC_CheckPredicate, 24, 63, 23, 0, // Skip to: 13161
6025
/* 7210 */    MCD_OPC_CheckField, 32, 4, 0, 56, 23, 0, // Skip to: 13161
6026
/* 7217 */    MCD_OPC_CheckField, 24, 4, 0, 49, 23, 0, // Skip to: 13161
6027
/* 7224 */    MCD_OPC_CheckField, 0, 20, 15, 42, 23, 0, // Skip to: 13161
6028
/* 7231 */    MCD_OPC_Decode, 185, 7, 215, 1, // Opcode: AE_MULF32S_LL_S2
6029
/* 7236 */    MCD_OPC_FilterValue, 128, 128, 12, 30, 23, 0, // Skip to: 13161
6030
/* 7243 */    MCD_OPC_CheckPredicate, 24, 25, 23, 0, // Skip to: 13161
6031
/* 7248 */    MCD_OPC_CheckField, 32, 4, 0, 18, 23, 0, // Skip to: 13161
6032
/* 7255 */    MCD_OPC_CheckField, 24, 4, 0, 11, 23, 0, // Skip to: 13161
6033
/* 7262 */    MCD_OPC_CheckField, 0, 20, 15, 4, 23, 0, // Skip to: 13161
6034
/* 7269 */    MCD_OPC_Decode, 187, 7, 215, 1, // Opcode: AE_MULF32X16_H0_S2
6035
/* 7274 */    MCD_OPC_FilterValue, 28, 153, 0, 0, // Skip to: 7432
6036
/* 7279 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6037
/* 7282 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7318
6038
/* 7287 */    MCD_OPC_CheckPredicate, 24, 237, 22, 0, // Skip to: 13161
6039
/* 7292 */    MCD_OPC_CheckField, 32, 4, 0, 230, 22, 0, // Skip to: 13161
6040
/* 7299 */    MCD_OPC_CheckField, 24, 4, 0, 223, 22, 0, // Skip to: 13161
6041
/* 7306 */    MCD_OPC_CheckField, 0, 20, 15, 216, 22, 0, // Skip to: 13161
6042
/* 7313 */    MCD_OPC_Decode, 189, 7, 215, 1, // Opcode: AE_MULF32X16_H1_S2
6043
/* 7318 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 7356
6044
/* 7325 */    MCD_OPC_CheckPredicate, 24, 199, 22, 0, // Skip to: 13161
6045
/* 7330 */    MCD_OPC_CheckField, 32, 4, 0, 192, 22, 0, // Skip to: 13161
6046
/* 7337 */    MCD_OPC_CheckField, 24, 4, 0, 185, 22, 0, // Skip to: 13161
6047
/* 7344 */    MCD_OPC_CheckField, 0, 20, 15, 178, 22, 0, // Skip to: 13161
6048
/* 7351 */    MCD_OPC_Decode, 191, 7, 215, 1, // Opcode: AE_MULF32X16_H2_S2
6049
/* 7356 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 7394
6050
/* 7363 */    MCD_OPC_CheckPredicate, 24, 161, 22, 0, // Skip to: 13161
6051
/* 7368 */    MCD_OPC_CheckField, 32, 4, 0, 154, 22, 0, // Skip to: 13161
6052
/* 7375 */    MCD_OPC_CheckField, 24, 4, 0, 147, 22, 0, // Skip to: 13161
6053
/* 7382 */    MCD_OPC_CheckField, 0, 20, 15, 140, 22, 0, // Skip to: 13161
6054
/* 7389 */    MCD_OPC_Decode, 193, 7, 215, 1, // Opcode: AE_MULF32X16_H3_S2
6055
/* 7394 */    MCD_OPC_FilterValue, 128, 128, 12, 128, 22, 0, // Skip to: 13161
6056
/* 7401 */    MCD_OPC_CheckPredicate, 24, 123, 22, 0, // Skip to: 13161
6057
/* 7406 */    MCD_OPC_CheckField, 32, 4, 0, 116, 22, 0, // Skip to: 13161
6058
/* 7413 */    MCD_OPC_CheckField, 24, 4, 0, 109, 22, 0, // Skip to: 13161
6059
/* 7420 */    MCD_OPC_CheckField, 0, 20, 15, 102, 22, 0, // Skip to: 13161
6060
/* 7427 */    MCD_OPC_Decode, 195, 7, 215, 1, // Opcode: AE_MULF32X16_L0_S2
6061
/* 7432 */    MCD_OPC_FilterValue, 29, 153, 0, 0, // Skip to: 7590
6062
/* 7437 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6063
/* 7440 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7476
6064
/* 7445 */    MCD_OPC_CheckPredicate, 24, 79, 22, 0, // Skip to: 13161
6065
/* 7450 */    MCD_OPC_CheckField, 32, 4, 0, 72, 22, 0, // Skip to: 13161
6066
/* 7457 */    MCD_OPC_CheckField, 24, 4, 0, 65, 22, 0, // Skip to: 13161
6067
/* 7464 */    MCD_OPC_CheckField, 0, 20, 15, 58, 22, 0, // Skip to: 13161
6068
/* 7471 */    MCD_OPC_Decode, 197, 7, 215, 1, // Opcode: AE_MULF32X16_L1_S2
6069
/* 7476 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 7514
6070
/* 7483 */    MCD_OPC_CheckPredicate, 24, 41, 22, 0, // Skip to: 13161
6071
/* 7488 */    MCD_OPC_CheckField, 32, 4, 0, 34, 22, 0, // Skip to: 13161
6072
/* 7495 */    MCD_OPC_CheckField, 24, 4, 0, 27, 22, 0, // Skip to: 13161
6073
/* 7502 */    MCD_OPC_CheckField, 0, 20, 15, 20, 22, 0, // Skip to: 13161
6074
/* 7509 */    MCD_OPC_Decode, 199, 7, 215, 1, // Opcode: AE_MULF32X16_L2_S2
6075
/* 7514 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 7552
6076
/* 7521 */    MCD_OPC_CheckPredicate, 24, 3, 22, 0, // Skip to: 13161
6077
/* 7526 */    MCD_OPC_CheckField, 32, 4, 0, 252, 21, 0, // Skip to: 13161
6078
/* 7533 */    MCD_OPC_CheckField, 24, 4, 0, 245, 21, 0, // Skip to: 13161
6079
/* 7540 */    MCD_OPC_CheckField, 0, 20, 15, 238, 21, 0, // Skip to: 13161
6080
/* 7547 */    MCD_OPC_Decode, 201, 7, 215, 1, // Opcode: AE_MULF32X16_L3_S2
6081
/* 7552 */    MCD_OPC_FilterValue, 128, 128, 12, 226, 21, 0, // Skip to: 13161
6082
/* 7559 */    MCD_OPC_CheckPredicate, 24, 221, 21, 0, // Skip to: 13161
6083
/* 7564 */    MCD_OPC_CheckField, 32, 4, 0, 214, 21, 0, // Skip to: 13161
6084
/* 7571 */    MCD_OPC_CheckField, 24, 4, 0, 207, 21, 0, // Skip to: 13161
6085
/* 7578 */    MCD_OPC_CheckField, 0, 20, 15, 200, 21, 0, // Skip to: 13161
6086
/* 7585 */    MCD_OPC_Decode, 203, 7, 215, 1, // Opcode: AE_MULF48Q32SP16S_L_S2
6087
/* 7590 */    MCD_OPC_FilterValue, 30, 153, 0, 0, // Skip to: 7748
6088
/* 7595 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6089
/* 7598 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7634
6090
/* 7603 */    MCD_OPC_CheckPredicate, 24, 177, 21, 0, // Skip to: 13161
6091
/* 7608 */    MCD_OPC_CheckField, 32, 4, 0, 170, 21, 0, // Skip to: 13161
6092
/* 7615 */    MCD_OPC_CheckField, 24, 4, 0, 163, 21, 0, // Skip to: 13161
6093
/* 7622 */    MCD_OPC_CheckField, 0, 20, 15, 156, 21, 0, // Skip to: 13161
6094
/* 7629 */    MCD_OPC_Decode, 205, 7, 215, 1, // Opcode: AE_MULF48Q32SP16U_L_S2
6095
/* 7634 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 7672
6096
/* 7641 */    MCD_OPC_CheckPredicate, 24, 139, 21, 0, // Skip to: 13161
6097
/* 7646 */    MCD_OPC_CheckField, 32, 4, 0, 132, 21, 0, // Skip to: 13161
6098
/* 7653 */    MCD_OPC_CheckField, 24, 4, 0, 125, 21, 0, // Skip to: 13161
6099
/* 7660 */    MCD_OPC_CheckField, 0, 20, 15, 118, 21, 0, // Skip to: 13161
6100
/* 7667 */    MCD_OPC_Decode, 219, 7, 215, 1, // Opcode: AE_MULFP24X2RA_S2
6101
/* 7672 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 7710
6102
/* 7679 */    MCD_OPC_CheckPredicate, 24, 101, 21, 0, // Skip to: 13161
6103
/* 7684 */    MCD_OPC_CheckField, 32, 4, 0, 94, 21, 0, // Skip to: 13161
6104
/* 7691 */    MCD_OPC_CheckField, 24, 4, 0, 87, 21, 0, // Skip to: 13161
6105
/* 7698 */    MCD_OPC_CheckField, 0, 20, 15, 80, 21, 0, // Skip to: 13161
6106
/* 7705 */    MCD_OPC_Decode, 220, 7, 215, 1, // Opcode: AE_MULFP24X2R_S2
6107
/* 7710 */    MCD_OPC_FilterValue, 128, 128, 12, 68, 21, 0, // Skip to: 13161
6108
/* 7717 */    MCD_OPC_CheckPredicate, 24, 63, 21, 0, // Skip to: 13161
6109
/* 7722 */    MCD_OPC_CheckField, 32, 4, 0, 56, 21, 0, // Skip to: 13161
6110
/* 7729 */    MCD_OPC_CheckField, 24, 4, 0, 49, 21, 0, // Skip to: 13161
6111
/* 7736 */    MCD_OPC_CheckField, 0, 20, 15, 42, 21, 0, // Skip to: 13161
6112
/* 7743 */    MCD_OPC_Decode, 222, 7, 215, 1, // Opcode: AE_MULFP32X16X2RAS_H_S2
6113
/* 7748 */    MCD_OPC_FilterValue, 31, 153, 0, 0, // Skip to: 7906
6114
/* 7753 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6115
/* 7756 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7792
6116
/* 7761 */    MCD_OPC_CheckPredicate, 24, 19, 21, 0, // Skip to: 13161
6117
/* 7766 */    MCD_OPC_CheckField, 32, 4, 0, 12, 21, 0, // Skip to: 13161
6118
/* 7773 */    MCD_OPC_CheckField, 24, 4, 0, 5, 21, 0, // Skip to: 13161
6119
/* 7780 */    MCD_OPC_CheckField, 0, 20, 15, 254, 20, 0, // Skip to: 13161
6120
/* 7787 */    MCD_OPC_Decode, 224, 7, 215, 1, // Opcode: AE_MULFP32X16X2RAS_L_S2
6121
/* 7792 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 7830
6122
/* 7799 */    MCD_OPC_CheckPredicate, 24, 237, 20, 0, // Skip to: 13161
6123
/* 7804 */    MCD_OPC_CheckField, 32, 4, 0, 230, 20, 0, // Skip to: 13161
6124
/* 7811 */    MCD_OPC_CheckField, 24, 4, 0, 223, 20, 0, // Skip to: 13161
6125
/* 7818 */    MCD_OPC_CheckField, 0, 20, 15, 216, 20, 0, // Skip to: 13161
6126
/* 7825 */    MCD_OPC_Decode, 226, 7, 215, 1, // Opcode: AE_MULFP32X16X2RS_H_S2
6127
/* 7830 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 7868
6128
/* 7837 */    MCD_OPC_CheckPredicate, 24, 199, 20, 0, // Skip to: 13161
6129
/* 7842 */    MCD_OPC_CheckField, 32, 4, 0, 192, 20, 0, // Skip to: 13161
6130
/* 7849 */    MCD_OPC_CheckField, 24, 4, 0, 185, 20, 0, // Skip to: 13161
6131
/* 7856 */    MCD_OPC_CheckField, 0, 20, 15, 178, 20, 0, // Skip to: 13161
6132
/* 7863 */    MCD_OPC_Decode, 228, 7, 215, 1, // Opcode: AE_MULFP32X16X2RS_L_S2
6133
/* 7868 */    MCD_OPC_FilterValue, 128, 128, 12, 166, 20, 0, // Skip to: 13161
6134
/* 7875 */    MCD_OPC_CheckPredicate, 24, 161, 20, 0, // Skip to: 13161
6135
/* 7880 */    MCD_OPC_CheckField, 32, 4, 0, 154, 20, 0, // Skip to: 13161
6136
/* 7887 */    MCD_OPC_CheckField, 24, 4, 0, 147, 20, 0, // Skip to: 13161
6137
/* 7894 */    MCD_OPC_CheckField, 0, 20, 15, 140, 20, 0, // Skip to: 13161
6138
/* 7901 */    MCD_OPC_Decode, 231, 7, 215, 1, // Opcode: AE_MULFQ32SP24S_H_S2
6139
/* 7906 */    MCD_OPC_FilterValue, 32, 153, 0, 0, // Skip to: 8064
6140
/* 7911 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6141
/* 7914 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7950
6142
/* 7919 */    MCD_OPC_CheckPredicate, 24, 117, 20, 0, // Skip to: 13161
6143
/* 7924 */    MCD_OPC_CheckField, 32, 4, 0, 110, 20, 0, // Skip to: 13161
6144
/* 7931 */    MCD_OPC_CheckField, 24, 4, 0, 103, 20, 0, // Skip to: 13161
6145
/* 7938 */    MCD_OPC_CheckField, 0, 20, 15, 96, 20, 0, // Skip to: 13161
6146
/* 7945 */    MCD_OPC_Decode, 232, 7, 215, 1, // Opcode: AE_MULFQ32SP24S_L_S2
6147
/* 7950 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 7988
6148
/* 7957 */    MCD_OPC_CheckPredicate, 24, 79, 20, 0, // Skip to: 13161
6149
/* 7962 */    MCD_OPC_CheckField, 32, 4, 0, 72, 20, 0, // Skip to: 13161
6150
/* 7969 */    MCD_OPC_CheckField, 24, 4, 0, 65, 20, 0, // Skip to: 13161
6151
/* 7976 */    MCD_OPC_CheckField, 0, 20, 15, 58, 20, 0, // Skip to: 13161
6152
/* 7983 */    MCD_OPC_Decode, 234, 7, 215, 1, // Opcode: AE_MULP24X2_S2
6153
/* 7988 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 8026
6154
/* 7995 */    MCD_OPC_CheckPredicate, 24, 41, 20, 0, // Skip to: 13161
6155
/* 8000 */    MCD_OPC_CheckField, 32, 4, 0, 34, 20, 0, // Skip to: 13161
6156
/* 8007 */    MCD_OPC_CheckField, 24, 4, 0, 27, 20, 0, // Skip to: 13161
6157
/* 8014 */    MCD_OPC_CheckField, 0, 20, 15, 20, 20, 0, // Skip to: 13161
6158
/* 8021 */    MCD_OPC_Decode, 238, 7, 215, 1, // Opcode: AE_MULQ32SP16S_L_S2
6159
/* 8026 */    MCD_OPC_FilterValue, 128, 128, 12, 8, 20, 0, // Skip to: 13161
6160
/* 8033 */    MCD_OPC_CheckPredicate, 24, 3, 20, 0, // Skip to: 13161
6161
/* 8038 */    MCD_OPC_CheckField, 32, 4, 0, 252, 19, 0, // Skip to: 13161
6162
/* 8045 */    MCD_OPC_CheckField, 24, 4, 0, 245, 19, 0, // Skip to: 13161
6163
/* 8052 */    MCD_OPC_CheckField, 0, 20, 15, 238, 19, 0, // Skip to: 13161
6164
/* 8059 */    MCD_OPC_Decode, 239, 7, 215, 1, // Opcode: AE_MULQ32SP16U_L_S2
6165
/* 8064 */    MCD_OPC_FilterValue, 33, 153, 0, 0, // Skip to: 8222
6166
/* 8069 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6167
/* 8072 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8108
6168
/* 8077 */    MCD_OPC_CheckPredicate, 24, 215, 19, 0, // Skip to: 13161
6169
/* 8082 */    MCD_OPC_CheckField, 32, 4, 0, 208, 19, 0, // Skip to: 13161
6170
/* 8089 */    MCD_OPC_CheckField, 24, 4, 0, 201, 19, 0, // Skip to: 13161
6171
/* 8096 */    MCD_OPC_CheckField, 0, 20, 15, 194, 19, 0, // Skip to: 13161
6172
/* 8103 */    MCD_OPC_Decode, 240, 7, 215, 1, // Opcode: AE_MULRFQ32SP24S_H_S2
6173
/* 8108 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 8146
6174
/* 8115 */    MCD_OPC_CheckPredicate, 24, 177, 19, 0, // Skip to: 13161
6175
/* 8120 */    MCD_OPC_CheckField, 32, 4, 0, 170, 19, 0, // Skip to: 13161
6176
/* 8127 */    MCD_OPC_CheckField, 24, 4, 0, 163, 19, 0, // Skip to: 13161
6177
/* 8134 */    MCD_OPC_CheckField, 0, 20, 15, 156, 19, 0, // Skip to: 13161
6178
/* 8141 */    MCD_OPC_Decode, 241, 7, 215, 1, // Opcode: AE_MULRFQ32SP24S_L_S2
6179
/* 8146 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 8184
6180
/* 8153 */    MCD_OPC_CheckPredicate, 24, 139, 19, 0, // Skip to: 13161
6181
/* 8158 */    MCD_OPC_CheckField, 32, 4, 0, 132, 19, 0, // Skip to: 13161
6182
/* 8165 */    MCD_OPC_CheckField, 24, 4, 0, 125, 19, 0, // Skip to: 13161
6183
/* 8172 */    MCD_OPC_CheckField, 0, 20, 15, 118, 19, 0, // Skip to: 13161
6184
/* 8179 */    MCD_OPC_Decode, 244, 7, 215, 1, // Opcode: AE_MULS32F48P16S_HH_S2
6185
/* 8184 */    MCD_OPC_FilterValue, 128, 128, 12, 106, 19, 0, // Skip to: 13161
6186
/* 8191 */    MCD_OPC_CheckPredicate, 24, 101, 19, 0, // Skip to: 13161
6187
/* 8196 */    MCD_OPC_CheckField, 32, 4, 0, 94, 19, 0, // Skip to: 13161
6188
/* 8203 */    MCD_OPC_CheckField, 24, 4, 0, 87, 19, 0, // Skip to: 13161
6189
/* 8210 */    MCD_OPC_CheckField, 0, 20, 15, 80, 19, 0, // Skip to: 13161
6190
/* 8217 */    MCD_OPC_Decode, 246, 7, 215, 1, // Opcode: AE_MULS32F48P16S_LH_S2
6191
/* 8222 */    MCD_OPC_FilterValue, 34, 153, 0, 0, // Skip to: 8380
6192
/* 8227 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6193
/* 8230 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8266
6194
/* 8235 */    MCD_OPC_CheckPredicate, 24, 57, 19, 0, // Skip to: 13161
6195
/* 8240 */    MCD_OPC_CheckField, 32, 4, 0, 50, 19, 0, // Skip to: 13161
6196
/* 8247 */    MCD_OPC_CheckField, 24, 4, 0, 43, 19, 0, // Skip to: 13161
6197
/* 8254 */    MCD_OPC_CheckField, 0, 20, 15, 36, 19, 0, // Skip to: 13161
6198
/* 8261 */    MCD_OPC_Decode, 248, 7, 215, 1, // Opcode: AE_MULS32F48P16S_LL_S2
6199
/* 8266 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 8304
6200
/* 8273 */    MCD_OPC_CheckPredicate, 24, 19, 19, 0, // Skip to: 13161
6201
/* 8278 */    MCD_OPC_CheckField, 32, 4, 0, 12, 19, 0, // Skip to: 13161
6202
/* 8285 */    MCD_OPC_CheckField, 24, 4, 0, 5, 19, 0, // Skip to: 13161
6203
/* 8292 */    MCD_OPC_CheckField, 0, 20, 15, 254, 18, 0, // Skip to: 13161
6204
/* 8299 */    MCD_OPC_Decode, 251, 7, 216, 1, // Opcode: AE_MULS32X16_H0_S2
6205
/* 8304 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 8342
6206
/* 8311 */    MCD_OPC_CheckPredicate, 24, 237, 18, 0, // Skip to: 13161
6207
/* 8316 */    MCD_OPC_CheckField, 32, 4, 0, 230, 18, 0, // Skip to: 13161
6208
/* 8323 */    MCD_OPC_CheckField, 24, 4, 0, 223, 18, 0, // Skip to: 13161
6209
/* 8330 */    MCD_OPC_CheckField, 0, 20, 15, 216, 18, 0, // Skip to: 13161
6210
/* 8337 */    MCD_OPC_Decode, 253, 7, 216, 1, // Opcode: AE_MULS32X16_H1_S2
6211
/* 8342 */    MCD_OPC_FilterValue, 128, 128, 12, 204, 18, 0, // Skip to: 13161
6212
/* 8349 */    MCD_OPC_CheckPredicate, 24, 199, 18, 0, // Skip to: 13161
6213
/* 8354 */    MCD_OPC_CheckField, 32, 4, 0, 192, 18, 0, // Skip to: 13161
6214
/* 8361 */    MCD_OPC_CheckField, 24, 4, 0, 185, 18, 0, // Skip to: 13161
6215
/* 8368 */    MCD_OPC_CheckField, 0, 20, 15, 178, 18, 0, // Skip to: 13161
6216
/* 8375 */    MCD_OPC_Decode, 255, 7, 216, 1, // Opcode: AE_MULS32X16_H2_S2
6217
/* 8380 */    MCD_OPC_FilterValue, 35, 153, 0, 0, // Skip to: 8538
6218
/* 8385 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6219
/* 8388 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8424
6220
/* 8393 */    MCD_OPC_CheckPredicate, 24, 155, 18, 0, // Skip to: 13161
6221
/* 8398 */    MCD_OPC_CheckField, 32, 4, 0, 148, 18, 0, // Skip to: 13161
6222
/* 8405 */    MCD_OPC_CheckField, 24, 4, 0, 141, 18, 0, // Skip to: 13161
6223
/* 8412 */    MCD_OPC_CheckField, 0, 20, 15, 134, 18, 0, // Skip to: 13161
6224
/* 8419 */    MCD_OPC_Decode, 129, 8, 216, 1, // Opcode: AE_MULS32X16_H3_S2
6225
/* 8424 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 8462
6226
/* 8431 */    MCD_OPC_CheckPredicate, 24, 117, 18, 0, // Skip to: 13161
6227
/* 8436 */    MCD_OPC_CheckField, 32, 4, 0, 110, 18, 0, // Skip to: 13161
6228
/* 8443 */    MCD_OPC_CheckField, 24, 4, 0, 103, 18, 0, // Skip to: 13161
6229
/* 8450 */    MCD_OPC_CheckField, 0, 20, 15, 96, 18, 0, // Skip to: 13161
6230
/* 8457 */    MCD_OPC_Decode, 131, 8, 216, 1, // Opcode: AE_MULS32X16_L0_S2
6231
/* 8462 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 8500
6232
/* 8469 */    MCD_OPC_CheckPredicate, 24, 79, 18, 0, // Skip to: 13161
6233
/* 8474 */    MCD_OPC_CheckField, 32, 4, 0, 72, 18, 0, // Skip to: 13161
6234
/* 8481 */    MCD_OPC_CheckField, 24, 4, 0, 65, 18, 0, // Skip to: 13161
6235
/* 8488 */    MCD_OPC_CheckField, 0, 20, 15, 58, 18, 0, // Skip to: 13161
6236
/* 8495 */    MCD_OPC_Decode, 133, 8, 216, 1, // Opcode: AE_MULS32X16_L1_S2
6237
/* 8500 */    MCD_OPC_FilterValue, 128, 128, 12, 46, 18, 0, // Skip to: 13161
6238
/* 8507 */    MCD_OPC_CheckPredicate, 24, 41, 18, 0, // Skip to: 13161
6239
/* 8512 */    MCD_OPC_CheckField, 32, 4, 0, 34, 18, 0, // Skip to: 13161
6240
/* 8519 */    MCD_OPC_CheckField, 24, 4, 0, 27, 18, 0, // Skip to: 13161
6241
/* 8526 */    MCD_OPC_CheckField, 0, 20, 15, 20, 18, 0, // Skip to: 13161
6242
/* 8533 */    MCD_OPC_Decode, 135, 8, 216, 1, // Opcode: AE_MULS32X16_L2_S2
6243
/* 8538 */    MCD_OPC_FilterValue, 36, 153, 0, 0, // Skip to: 8696
6244
/* 8543 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6245
/* 8546 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8582
6246
/* 8551 */    MCD_OPC_CheckPredicate, 24, 253, 17, 0, // Skip to: 13161
6247
/* 8556 */    MCD_OPC_CheckField, 32, 4, 0, 246, 17, 0, // Skip to: 13161
6248
/* 8563 */    MCD_OPC_CheckField, 24, 4, 0, 239, 17, 0, // Skip to: 13161
6249
/* 8570 */    MCD_OPC_CheckField, 0, 20, 15, 232, 17, 0, // Skip to: 13161
6250
/* 8577 */    MCD_OPC_Decode, 137, 8, 216, 1, // Opcode: AE_MULS32X16_L3_S2
6251
/* 8582 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 8620
6252
/* 8589 */    MCD_OPC_CheckPredicate, 24, 215, 17, 0, // Skip to: 13161
6253
/* 8594 */    MCD_OPC_CheckField, 32, 4, 0, 208, 17, 0, // Skip to: 13161
6254
/* 8601 */    MCD_OPC_CheckField, 24, 4, 0, 201, 17, 0, // Skip to: 13161
6255
/* 8608 */    MCD_OPC_CheckField, 0, 20, 15, 194, 17, 0, // Skip to: 13161
6256
/* 8615 */    MCD_OPC_Decode, 142, 8, 216, 1, // Opcode: AE_MULSAD24_HH_LL_S2
6257
/* 8620 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 8658
6258
/* 8627 */    MCD_OPC_CheckPredicate, 24, 177, 17, 0, // Skip to: 13161
6259
/* 8632 */    MCD_OPC_CheckField, 32, 4, 0, 170, 17, 0, // Skip to: 13161
6260
/* 8639 */    MCD_OPC_CheckField, 24, 4, 0, 163, 17, 0, // Skip to: 13161
6261
/* 8646 */    MCD_OPC_CheckField, 0, 20, 15, 156, 17, 0, // Skip to: 13161
6262
/* 8653 */    MCD_OPC_Decode, 144, 8, 216, 1, // Opcode: AE_MULSAD32X16_H1_L0_S2
6263
/* 8658 */    MCD_OPC_FilterValue, 128, 128, 12, 144, 17, 0, // Skip to: 13161
6264
/* 8665 */    MCD_OPC_CheckPredicate, 24, 139, 17, 0, // Skip to: 13161
6265
/* 8670 */    MCD_OPC_CheckField, 32, 4, 0, 132, 17, 0, // Skip to: 13161
6266
/* 8677 */    MCD_OPC_CheckField, 24, 4, 0, 125, 17, 0, // Skip to: 13161
6267
/* 8684 */    MCD_OPC_CheckField, 0, 20, 15, 118, 17, 0, // Skip to: 13161
6268
/* 8691 */    MCD_OPC_Decode, 146, 8, 216, 1, // Opcode: AE_MULSAD32X16_H3_L2_S2
6269
/* 8696 */    MCD_OPC_FilterValue, 37, 153, 0, 0, // Skip to: 8854
6270
/* 8701 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6271
/* 8704 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8740
6272
/* 8709 */    MCD_OPC_CheckPredicate, 24, 95, 17, 0, // Skip to: 13161
6273
/* 8714 */    MCD_OPC_CheckField, 32, 4, 0, 88, 17, 0, // Skip to: 13161
6274
/* 8721 */    MCD_OPC_CheckField, 24, 4, 0, 81, 17, 0, // Skip to: 13161
6275
/* 8728 */    MCD_OPC_CheckField, 0, 20, 15, 74, 17, 0, // Skip to: 13161
6276
/* 8735 */    MCD_OPC_Decode, 148, 8, 216, 1, // Opcode: AE_MULSAFD24_HH_LL_S2
6277
/* 8740 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 8778
6278
/* 8747 */    MCD_OPC_CheckPredicate, 24, 57, 17, 0, // Skip to: 13161
6279
/* 8752 */    MCD_OPC_CheckField, 32, 4, 0, 50, 17, 0, // Skip to: 13161
6280
/* 8759 */    MCD_OPC_CheckField, 24, 4, 0, 43, 17, 0, // Skip to: 13161
6281
/* 8766 */    MCD_OPC_CheckField, 0, 20, 15, 36, 17, 0, // Skip to: 13161
6282
/* 8773 */    MCD_OPC_Decode, 150, 8, 216, 1, // Opcode: AE_MULSAFD32X16_H1_L0_S2
6283
/* 8778 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 8816
6284
/* 8785 */    MCD_OPC_CheckPredicate, 24, 19, 17, 0, // Skip to: 13161
6285
/* 8790 */    MCD_OPC_CheckField, 32, 4, 0, 12, 17, 0, // Skip to: 13161
6286
/* 8797 */    MCD_OPC_CheckField, 24, 4, 0, 5, 17, 0, // Skip to: 13161
6287
/* 8804 */    MCD_OPC_CheckField, 0, 20, 15, 254, 16, 0, // Skip to: 13161
6288
/* 8811 */    MCD_OPC_Decode, 152, 8, 216, 1, // Opcode: AE_MULSAFD32X16_H3_L2_S2
6289
/* 8816 */    MCD_OPC_FilterValue, 128, 128, 12, 242, 16, 0, // Skip to: 13161
6290
/* 8823 */    MCD_OPC_CheckPredicate, 24, 237, 16, 0, // Skip to: 13161
6291
/* 8828 */    MCD_OPC_CheckField, 32, 4, 0, 230, 16, 0, // Skip to: 13161
6292
/* 8835 */    MCD_OPC_CheckField, 24, 4, 0, 223, 16, 0, // Skip to: 13161
6293
/* 8842 */    MCD_OPC_CheckField, 0, 20, 15, 216, 16, 0, // Skip to: 13161
6294
/* 8849 */    MCD_OPC_Decode, 154, 8, 216, 1, // Opcode: AE_MULSF16SS_00_S2
6295
/* 8854 */    MCD_OPC_FilterValue, 38, 153, 0, 0, // Skip to: 9012
6296
/* 8859 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6297
/* 8862 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8898
6298
/* 8867 */    MCD_OPC_CheckPredicate, 24, 193, 16, 0, // Skip to: 13161
6299
/* 8872 */    MCD_OPC_CheckField, 32, 4, 0, 186, 16, 0, // Skip to: 13161
6300
/* 8879 */    MCD_OPC_CheckField, 24, 4, 0, 179, 16, 0, // Skip to: 13161
6301
/* 8886 */    MCD_OPC_CheckField, 0, 20, 15, 172, 16, 0, // Skip to: 13161
6302
/* 8893 */    MCD_OPC_Decode, 168, 8, 216, 1, // Opcode: AE_MULSF32R_LL_S2
6303
/* 8898 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 8936
6304
/* 8905 */    MCD_OPC_CheckPredicate, 24, 155, 16, 0, // Skip to: 13161
6305
/* 8910 */    MCD_OPC_CheckField, 32, 4, 0, 148, 16, 0, // Skip to: 13161
6306
/* 8917 */    MCD_OPC_CheckField, 24, 4, 0, 141, 16, 0, // Skip to: 13161
6307
/* 8924 */    MCD_OPC_CheckField, 0, 20, 15, 134, 16, 0, // Skip to: 13161
6308
/* 8931 */    MCD_OPC_Decode, 173, 8, 216, 1, // Opcode: AE_MULSF32X16_H0_S2
6309
/* 8936 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 8974
6310
/* 8943 */    MCD_OPC_CheckPredicate, 24, 117, 16, 0, // Skip to: 13161
6311
/* 8948 */    MCD_OPC_CheckField, 32, 4, 0, 110, 16, 0, // Skip to: 13161
6312
/* 8955 */    MCD_OPC_CheckField, 24, 4, 0, 103, 16, 0, // Skip to: 13161
6313
/* 8962 */    MCD_OPC_CheckField, 0, 20, 15, 96, 16, 0, // Skip to: 13161
6314
/* 8969 */    MCD_OPC_Decode, 175, 8, 216, 1, // Opcode: AE_MULSF32X16_H1_S2
6315
/* 8974 */    MCD_OPC_FilterValue, 128, 128, 12, 84, 16, 0, // Skip to: 13161
6316
/* 8981 */    MCD_OPC_CheckPredicate, 24, 79, 16, 0, // Skip to: 13161
6317
/* 8986 */    MCD_OPC_CheckField, 32, 4, 0, 72, 16, 0, // Skip to: 13161
6318
/* 8993 */    MCD_OPC_CheckField, 24, 4, 0, 65, 16, 0, // Skip to: 13161
6319
/* 9000 */    MCD_OPC_CheckField, 0, 20, 15, 58, 16, 0, // Skip to: 13161
6320
/* 9007 */    MCD_OPC_Decode, 177, 8, 216, 1, // Opcode: AE_MULSF32X16_H2_S2
6321
/* 9012 */    MCD_OPC_FilterValue, 39, 213, 0, 0, // Skip to: 9230
6322
/* 9017 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6323
/* 9020 */    MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 9086
6324
/* 9025 */    MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6325
/* 9028 */    MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 9057
6326
/* 9033 */    MCD_OPC_CheckPredicate, 24, 27, 16, 0, // Skip to: 13161
6327
/* 9038 */    MCD_OPC_CheckField, 32, 4, 0, 20, 16, 0, // Skip to: 13161
6328
/* 9045 */    MCD_OPC_CheckField, 24, 4, 0, 13, 16, 0, // Skip to: 13161
6329
/* 9052 */    MCD_OPC_Decode, 211, 9, 215, 1, // Opcode: AE_ROUND16X4F32SSYM
6330
/* 9057 */    MCD_OPC_FilterValue, 15, 3, 16, 0, // Skip to: 13161
6331
/* 9062 */    MCD_OPC_CheckPredicate, 24, 254, 15, 0, // Skip to: 13161
6332
/* 9067 */    MCD_OPC_CheckField, 32, 4, 0, 247, 15, 0, // Skip to: 13161
6333
/* 9074 */    MCD_OPC_CheckField, 24, 4, 0, 240, 15, 0, // Skip to: 13161
6334
/* 9081 */    MCD_OPC_Decode, 179, 8, 216, 1, // Opcode: AE_MULSF32X16_H3_S2
6335
/* 9086 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 9124
6336
/* 9093 */    MCD_OPC_CheckPredicate, 24, 223, 15, 0, // Skip to: 13161
6337
/* 9098 */    MCD_OPC_CheckField, 32, 4, 0, 216, 15, 0, // Skip to: 13161
6338
/* 9105 */    MCD_OPC_CheckField, 24, 4, 0, 209, 15, 0, // Skip to: 13161
6339
/* 9112 */    MCD_OPC_CheckField, 0, 20, 15, 202, 15, 0, // Skip to: 13161
6340
/* 9119 */    MCD_OPC_Decode, 181, 8, 216, 1, // Opcode: AE_MULSF32X16_L0_S2
6341
/* 9124 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 9162
6342
/* 9131 */    MCD_OPC_CheckPredicate, 24, 185, 15, 0, // Skip to: 13161
6343
/* 9136 */    MCD_OPC_CheckField, 32, 4, 0, 178, 15, 0, // Skip to: 13161
6344
/* 9143 */    MCD_OPC_CheckField, 24, 4, 0, 171, 15, 0, // Skip to: 13161
6345
/* 9150 */    MCD_OPC_CheckField, 0, 20, 15, 164, 15, 0, // Skip to: 13161
6346
/* 9157 */    MCD_OPC_Decode, 183, 8, 216, 1, // Opcode: AE_MULSF32X16_L1_S2
6347
/* 9162 */    MCD_OPC_FilterValue, 128, 128, 12, 152, 15, 0, // Skip to: 13161
6348
/* 9169 */    MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6349
/* 9172 */    MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 9201
6350
/* 9177 */    MCD_OPC_CheckPredicate, 24, 139, 15, 0, // Skip to: 13161
6351
/* 9182 */    MCD_OPC_CheckField, 32, 4, 0, 132, 15, 0, // Skip to: 13161
6352
/* 9189 */    MCD_OPC_CheckField, 24, 4, 0, 125, 15, 0, // Skip to: 13161
6353
/* 9196 */    MCD_OPC_Decode, 214, 9, 217, 1, // Opcode: AE_ROUND32X2F48SASYM
6354
/* 9201 */    MCD_OPC_FilterValue, 15, 115, 15, 0, // Skip to: 13161
6355
/* 9206 */    MCD_OPC_CheckPredicate, 24, 110, 15, 0, // Skip to: 13161
6356
/* 9211 */    MCD_OPC_CheckField, 32, 4, 0, 103, 15, 0, // Skip to: 13161
6357
/* 9218 */    MCD_OPC_CheckField, 24, 4, 0, 96, 15, 0, // Skip to: 13161
6358
/* 9225 */    MCD_OPC_Decode, 185, 8, 216, 1, // Opcode: AE_MULSF32X16_L2_S2
6359
/* 9230 */    MCD_OPC_FilterValue, 40, 213, 0, 0, // Skip to: 9448
6360
/* 9235 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6361
/* 9238 */    MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 9304
6362
/* 9243 */    MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6363
/* 9246 */    MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 9275
6364
/* 9251 */    MCD_OPC_CheckPredicate, 24, 65, 15, 0, // Skip to: 13161
6365
/* 9256 */    MCD_OPC_CheckField, 32, 4, 0, 58, 15, 0, // Skip to: 13161
6366
/* 9263 */    MCD_OPC_CheckField, 24, 4, 0, 51, 15, 0, // Skip to: 13161
6367
/* 9270 */    MCD_OPC_Decode, 215, 9, 217, 1, // Opcode: AE_ROUND32X2F48SSYM
6368
/* 9275 */    MCD_OPC_FilterValue, 15, 41, 15, 0, // Skip to: 13161
6369
/* 9280 */    MCD_OPC_CheckPredicate, 24, 36, 15, 0, // Skip to: 13161
6370
/* 9285 */    MCD_OPC_CheckField, 32, 4, 0, 29, 15, 0, // Skip to: 13161
6371
/* 9292 */    MCD_OPC_CheckField, 24, 4, 0, 22, 15, 0, // Skip to: 13161
6372
/* 9299 */    MCD_OPC_Decode, 187, 8, 216, 1, // Opcode: AE_MULSF32X16_L3_S2
6373
/* 9304 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 9342
6374
/* 9311 */    MCD_OPC_CheckPredicate, 24, 5, 15, 0, // Skip to: 13161
6375
/* 9316 */    MCD_OPC_CheckField, 32, 4, 0, 254, 14, 0, // Skip to: 13161
6376
/* 9323 */    MCD_OPC_CheckField, 24, 4, 0, 247, 14, 0, // Skip to: 13161
6377
/* 9330 */    MCD_OPC_CheckField, 0, 20, 15, 240, 14, 0, // Skip to: 13161
6378
/* 9337 */    MCD_OPC_Decode, 189, 8, 216, 1, // Opcode: AE_MULSF48Q32SP16S_L_S2
6379
/* 9342 */    MCD_OPC_FilterValue, 128, 128, 8, 61, 0, 0, // Skip to: 9410
6380
/* 9349 */    MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6381
/* 9352 */    MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 9381
6382
/* 9357 */    MCD_OPC_CheckPredicate, 24, 215, 14, 0, // Skip to: 13161
6383
/* 9362 */    MCD_OPC_CheckField, 32, 4, 0, 208, 14, 0, // Skip to: 13161
6384
/* 9369 */    MCD_OPC_CheckField, 24, 4, 0, 201, 14, 0, // Skip to: 13161
6385
/* 9376 */    MCD_OPC_Decode, 217, 9, 217, 1, // Opcode: AE_ROUND32X2F64SSYM
6386
/* 9381 */    MCD_OPC_FilterValue, 15, 191, 14, 0, // Skip to: 13161
6387
/* 9386 */    MCD_OPC_CheckPredicate, 24, 186, 14, 0, // Skip to: 13161
6388
/* 9391 */    MCD_OPC_CheckField, 32, 4, 0, 179, 14, 0, // Skip to: 13161
6389
/* 9398 */    MCD_OPC_CheckField, 24, 4, 0, 172, 14, 0, // Skip to: 13161
6390
/* 9405 */    MCD_OPC_Decode, 191, 8, 216, 1, // Opcode: AE_MULSF48Q32SP16U_L_S2
6391
/* 9410 */    MCD_OPC_FilterValue, 128, 128, 12, 160, 14, 0, // Skip to: 13161
6392
/* 9417 */    MCD_OPC_CheckPredicate, 24, 155, 14, 0, // Skip to: 13161
6393
/* 9422 */    MCD_OPC_CheckField, 32, 4, 0, 148, 14, 0, // Skip to: 13161
6394
/* 9429 */    MCD_OPC_CheckField, 24, 4, 0, 141, 14, 0, // Skip to: 13161
6395
/* 9436 */    MCD_OPC_CheckField, 0, 20, 15, 134, 14, 0, // Skip to: 13161
6396
/* 9443 */    MCD_OPC_Decode, 194, 8, 216, 1, // Opcode: AE_MULSFP24X2RA_S2
6397
/* 9448 */    MCD_OPC_FilterValue, 41, 213, 0, 0, // Skip to: 9666
6398
/* 9453 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6399
/* 9456 */    MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 9522
6400
/* 9461 */    MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6401
/* 9464 */    MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 9493
6402
/* 9469 */    MCD_OPC_CheckPredicate, 24, 103, 14, 0, // Skip to: 13161
6403
/* 9474 */    MCD_OPC_CheckField, 32, 4, 0, 96, 14, 0, // Skip to: 13161
6404
/* 9481 */    MCD_OPC_CheckField, 24, 4, 0, 89, 14, 0, // Skip to: 13161
6405
/* 9488 */    MCD_OPC_Decode, 221, 9, 217, 1, // Opcode: AE_ROUNDSP16Q48X2SYM
6406
/* 9493 */    MCD_OPC_FilterValue, 15, 79, 14, 0, // Skip to: 13161
6407
/* 9498 */    MCD_OPC_CheckPredicate, 24, 74, 14, 0, // Skip to: 13161
6408
/* 9503 */    MCD_OPC_CheckField, 32, 4, 0, 67, 14, 0, // Skip to: 13161
6409
/* 9510 */    MCD_OPC_CheckField, 24, 4, 0, 60, 14, 0, // Skip to: 13161
6410
/* 9517 */    MCD_OPC_Decode, 195, 8, 216, 1, // Opcode: AE_MULSFP24X2R_S2
6411
/* 9522 */    MCD_OPC_FilterValue, 128, 128, 4, 61, 0, 0, // Skip to: 9590
6412
/* 9529 */    MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6413
/* 9532 */    MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 9561
6414
/* 9537 */    MCD_OPC_CheckPredicate, 24, 35, 14, 0, // Skip to: 13161
6415
/* 9542 */    MCD_OPC_CheckField, 32, 4, 0, 28, 14, 0, // Skip to: 13161
6416
/* 9549 */    MCD_OPC_CheckField, 24, 4, 0, 21, 14, 0, // Skip to: 13161
6417
/* 9556 */    MCD_OPC_Decode, 187, 10, 217, 1, // Opcode: AE_SAT16X4
6418
/* 9561 */    MCD_OPC_FilterValue, 15, 11, 14, 0, // Skip to: 13161
6419
/* 9566 */    MCD_OPC_CheckPredicate, 24, 6, 14, 0, // Skip to: 13161
6420
/* 9571 */    MCD_OPC_CheckField, 32, 4, 0, 255, 13, 0, // Skip to: 13161
6421
/* 9578 */    MCD_OPC_CheckField, 24, 4, 0, 248, 13, 0, // Skip to: 13161
6422
/* 9585 */    MCD_OPC_Decode, 197, 8, 216, 1, // Opcode: AE_MULSFP32X16X2RAS_H_S2
6423
/* 9590 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 9628
6424
/* 9597 */    MCD_OPC_CheckPredicate, 24, 231, 13, 0, // Skip to: 13161
6425
/* 9602 */    MCD_OPC_CheckField, 32, 4, 0, 224, 13, 0, // Skip to: 13161
6426
/* 9609 */    MCD_OPC_CheckField, 24, 4, 0, 217, 13, 0, // Skip to: 13161
6427
/* 9616 */    MCD_OPC_CheckField, 0, 20, 15, 210, 13, 0, // Skip to: 13161
6428
/* 9623 */    MCD_OPC_Decode, 199, 8, 216, 1, // Opcode: AE_MULSFP32X16X2RAS_L_S2
6429
/* 9628 */    MCD_OPC_FilterValue, 128, 128, 12, 198, 13, 0, // Skip to: 13161
6430
/* 9635 */    MCD_OPC_CheckPredicate, 24, 193, 13, 0, // Skip to: 13161
6431
/* 9640 */    MCD_OPC_CheckField, 32, 4, 0, 186, 13, 0, // Skip to: 13161
6432
/* 9647 */    MCD_OPC_CheckField, 24, 4, 0, 179, 13, 0, // Skip to: 13161
6433
/* 9654 */    MCD_OPC_CheckField, 0, 20, 15, 172, 13, 0, // Skip to: 13161
6434
/* 9661 */    MCD_OPC_Decode, 201, 8, 216, 1, // Opcode: AE_MULSFP32X16X2RS_H_S2
6435
/* 9666 */    MCD_OPC_FilterValue, 42, 153, 0, 0, // Skip to: 9824
6436
/* 9671 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6437
/* 9674 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 9710
6438
/* 9679 */    MCD_OPC_CheckPredicate, 24, 149, 13, 0, // Skip to: 13161
6439
/* 9684 */    MCD_OPC_CheckField, 32, 4, 0, 142, 13, 0, // Skip to: 13161
6440
/* 9691 */    MCD_OPC_CheckField, 24, 4, 0, 135, 13, 0, // Skip to: 13161
6441
/* 9698 */    MCD_OPC_CheckField, 0, 20, 15, 128, 13, 0, // Skip to: 13161
6442
/* 9705 */    MCD_OPC_Decode, 203, 8, 216, 1, // Opcode: AE_MULSFP32X16X2RS_L_S2
6443
/* 9710 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 9748
6444
/* 9717 */    MCD_OPC_CheckPredicate, 24, 111, 13, 0, // Skip to: 13161
6445
/* 9722 */    MCD_OPC_CheckField, 32, 4, 0, 104, 13, 0, // Skip to: 13161
6446
/* 9729 */    MCD_OPC_CheckField, 24, 4, 0, 97, 13, 0, // Skip to: 13161
6447
/* 9736 */    MCD_OPC_CheckField, 0, 20, 15, 90, 13, 0, // Skip to: 13161
6448
/* 9743 */    MCD_OPC_Decode, 206, 8, 216, 1, // Opcode: AE_MULSFQ32SP24S_H_S2
6449
/* 9748 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 9786
6450
/* 9755 */    MCD_OPC_CheckPredicate, 24, 73, 13, 0, // Skip to: 13161
6451
/* 9760 */    MCD_OPC_CheckField, 32, 4, 0, 66, 13, 0, // Skip to: 13161
6452
/* 9767 */    MCD_OPC_CheckField, 24, 4, 0, 59, 13, 0, // Skip to: 13161
6453
/* 9774 */    MCD_OPC_CheckField, 0, 20, 15, 52, 13, 0, // Skip to: 13161
6454
/* 9781 */    MCD_OPC_Decode, 207, 8, 216, 1, // Opcode: AE_MULSFQ32SP24S_L_S2
6455
/* 9786 */    MCD_OPC_FilterValue, 128, 128, 12, 40, 13, 0, // Skip to: 13161
6456
/* 9793 */    MCD_OPC_CheckPredicate, 24, 35, 13, 0, // Skip to: 13161
6457
/* 9798 */    MCD_OPC_CheckField, 32, 4, 0, 28, 13, 0, // Skip to: 13161
6458
/* 9805 */    MCD_OPC_CheckField, 24, 4, 0, 21, 13, 0, // Skip to: 13161
6459
/* 9812 */    MCD_OPC_CheckField, 0, 20, 15, 14, 13, 0, // Skip to: 13161
6460
/* 9819 */    MCD_OPC_Decode, 209, 8, 216, 1, // Opcode: AE_MULSP24X2_S2
6461
/* 9824 */    MCD_OPC_FilterValue, 43, 153, 0, 0, // Skip to: 9982
6462
/* 9829 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6463
/* 9832 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 9868
6464
/* 9837 */    MCD_OPC_CheckPredicate, 24, 247, 12, 0, // Skip to: 13161
6465
/* 9842 */    MCD_OPC_CheckField, 32, 4, 0, 240, 12, 0, // Skip to: 13161
6466
/* 9849 */    MCD_OPC_CheckField, 24, 4, 0, 233, 12, 0, // Skip to: 13161
6467
/* 9856 */    MCD_OPC_CheckField, 0, 20, 15, 226, 12, 0, // Skip to: 13161
6468
/* 9863 */    MCD_OPC_Decode, 213, 8, 216, 1, // Opcode: AE_MULSQ32SP16S_L_S2
6469
/* 9868 */    MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 9906
6470
/* 9875 */    MCD_OPC_CheckPredicate, 24, 209, 12, 0, // Skip to: 13161
6471
/* 9880 */    MCD_OPC_CheckField, 32, 4, 0, 202, 12, 0, // Skip to: 13161
6472
/* 9887 */    MCD_OPC_CheckField, 24, 4, 0, 195, 12, 0, // Skip to: 13161
6473
/* 9894 */    MCD_OPC_CheckField, 0, 20, 15, 188, 12, 0, // Skip to: 13161
6474
/* 9901 */    MCD_OPC_Decode, 214, 8, 216, 1, // Opcode: AE_MULSQ32SP16U_L_S2
6475
/* 9906 */    MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 9944
6476
/* 9913 */    MCD_OPC_CheckPredicate, 24, 171, 12, 0, // Skip to: 13161
6477
/* 9918 */    MCD_OPC_CheckField, 32, 4, 0, 164, 12, 0, // Skip to: 13161
6478
/* 9925 */    MCD_OPC_CheckField, 24, 4, 0, 157, 12, 0, // Skip to: 13161
6479
/* 9932 */    MCD_OPC_CheckField, 0, 20, 15, 150, 12, 0, // Skip to: 13161
6480
/* 9939 */    MCD_OPC_Decode, 215, 8, 216, 1, // Opcode: AE_MULSRFQ32SP24S_H_S2
6481
/* 9944 */    MCD_OPC_FilterValue, 128, 128, 12, 138, 12, 0, // Skip to: 13161
6482
/* 9951 */    MCD_OPC_CheckPredicate, 24, 133, 12, 0, // Skip to: 13161
6483
/* 9956 */    MCD_OPC_CheckField, 32, 4, 0, 126, 12, 0, // Skip to: 13161
6484
/* 9963 */    MCD_OPC_CheckField, 24, 4, 0, 119, 12, 0, // Skip to: 13161
6485
/* 9970 */    MCD_OPC_CheckField, 0, 20, 15, 112, 12, 0, // Skip to: 13161
6486
/* 9977 */    MCD_OPC_Decode, 216, 8, 216, 1, // Opcode: AE_MULSRFQ32SP24S_L_S2
6487
/* 9982 */    MCD_OPC_FilterValue, 44, 183, 0, 0, // Skip to: 10170
6488
/* 9987 */    MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6489
/* 9990 */    MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 10056
6490
/* 9995 */    MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6491
/* 9998 */    MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10027
6492
/* 10003 */   MCD_OPC_CheckPredicate, 24, 81, 12, 0, // Skip to: 13161
6493
/* 10008 */   MCD_OPC_CheckField, 32, 4, 0, 74, 12, 0, // Skip to: 13161
6494
/* 10015 */   MCD_OPC_CheckField, 24, 4, 0, 67, 12, 0, // Skip to: 13161
6495
/* 10022 */   MCD_OPC_Decode, 248, 4, 218, 1, // Opcode: AE_EQ64
6496
/* 10027 */   MCD_OPC_FilterValue, 15, 57, 12, 0, // Skip to: 13161
6497
/* 10032 */   MCD_OPC_CheckPredicate, 24, 52, 12, 0, // Skip to: 13161
6498
/* 10037 */   MCD_OPC_CheckField, 32, 4, 0, 45, 12, 0, // Skip to: 13161
6499
/* 10044 */   MCD_OPC_CheckField, 24, 4, 0, 38, 12, 0, // Skip to: 13161
6500
/* 10051 */   MCD_OPC_Decode, 218, 8, 216, 1, // Opcode: AE_MULSS32F48P16S_HH_S2
6501
/* 10056 */   MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 10094
6502
/* 10063 */   MCD_OPC_CheckPredicate, 24, 21, 12, 0, // Skip to: 13161
6503
/* 10068 */   MCD_OPC_CheckField, 32, 4, 0, 14, 12, 0, // Skip to: 13161
6504
/* 10075 */   MCD_OPC_CheckField, 24, 4, 0, 7, 12, 0, // Skip to: 13161
6505
/* 10082 */   MCD_OPC_CheckField, 0, 20, 15, 0, 12, 0, // Skip to: 13161
6506
/* 10089 */   MCD_OPC_Decode, 220, 8, 216, 1, // Opcode: AE_MULSS32F48P16S_LH_S2
6507
/* 10094 */   MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 10132
6508
/* 10101 */   MCD_OPC_CheckPredicate, 24, 239, 11, 0, // Skip to: 13161
6509
/* 10106 */   MCD_OPC_CheckField, 32, 4, 0, 232, 11, 0, // Skip to: 13161
6510
/* 10113 */   MCD_OPC_CheckField, 24, 4, 0, 225, 11, 0, // Skip to: 13161
6511
/* 10120 */   MCD_OPC_CheckField, 0, 20, 15, 218, 11, 0, // Skip to: 13161
6512
/* 10127 */   MCD_OPC_Decode, 222, 8, 216, 1, // Opcode: AE_MULSS32F48P16S_LL_S2
6513
/* 10132 */   MCD_OPC_FilterValue, 128, 128, 12, 206, 11, 0, // Skip to: 13161
6514
/* 10139 */   MCD_OPC_CheckPredicate, 24, 201, 11, 0, // Skip to: 13161
6515
/* 10144 */   MCD_OPC_CheckField, 32, 4, 0, 194, 11, 0, // Skip to: 13161
6516
/* 10151 */   MCD_OPC_CheckField, 24, 4, 0, 187, 11, 0, // Skip to: 13161
6517
/* 10158 */   MCD_OPC_CheckField, 0, 20, 15, 180, 11, 0, // Skip to: 13161
6518
/* 10165 */   MCD_OPC_Decode, 224, 8, 216, 1, // Opcode: AE_MULSSD24_HH_LL_S2
6519
/* 10170 */   MCD_OPC_FilterValue, 45, 243, 0, 0, // Skip to: 10418
6520
/* 10175 */   MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6521
/* 10178 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 10244
6522
/* 10183 */   MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6523
/* 10186 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10215
6524
/* 10191 */   MCD_OPC_CheckPredicate, 24, 149, 11, 0, // Skip to: 13161
6525
/* 10196 */   MCD_OPC_CheckField, 32, 4, 0, 142, 11, 0, // Skip to: 13161
6526
/* 10203 */   MCD_OPC_CheckField, 24, 4, 0, 135, 11, 0, // Skip to: 13161
6527
/* 10210 */   MCD_OPC_Decode, 220, 5, 215, 1, // Opcode: AE_MAX64
6528
/* 10215 */   MCD_OPC_FilterValue, 15, 125, 11, 0, // Skip to: 13161
6529
/* 10220 */   MCD_OPC_CheckPredicate, 24, 120, 11, 0, // Skip to: 13161
6530
/* 10225 */   MCD_OPC_CheckField, 32, 4, 0, 113, 11, 0, // Skip to: 13161
6531
/* 10232 */   MCD_OPC_CheckField, 24, 4, 0, 106, 11, 0, // Skip to: 13161
6532
/* 10239 */   MCD_OPC_Decode, 226, 8, 216, 1, // Opcode: AE_MULSSD24_HL_LH_S2
6533
/* 10244 */   MCD_OPC_FilterValue, 128, 128, 4, 61, 0, 0, // Skip to: 10312
6534
/* 10251 */   MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6535
/* 10254 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10283
6536
/* 10259 */   MCD_OPC_CheckPredicate, 24, 81, 11, 0, // Skip to: 13161
6537
/* 10264 */   MCD_OPC_CheckField, 32, 4, 0, 74, 11, 0, // Skip to: 13161
6538
/* 10271 */   MCD_OPC_CheckField, 24, 4, 0, 67, 11, 0, // Skip to: 13161
6539
/* 10278 */   MCD_OPC_Decode, 221, 5, 215, 1, // Opcode: AE_MAXABS32S
6540
/* 10283 */   MCD_OPC_FilterValue, 15, 57, 11, 0, // Skip to: 13161
6541
/* 10288 */   MCD_OPC_CheckPredicate, 24, 52, 11, 0, // Skip to: 13161
6542
/* 10293 */   MCD_OPC_CheckField, 32, 4, 0, 45, 11, 0, // Skip to: 13161
6543
/* 10300 */   MCD_OPC_CheckField, 24, 4, 0, 38, 11, 0, // Skip to: 13161
6544
/* 10307 */   MCD_OPC_Decode, 228, 8, 216, 1, // Opcode: AE_MULSSD32X16_H1_L0_S2
6545
/* 10312 */   MCD_OPC_FilterValue, 128, 128, 8, 61, 0, 0, // Skip to: 10380
6546
/* 10319 */   MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6547
/* 10322 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10351
6548
/* 10327 */   MCD_OPC_CheckPredicate, 24, 13, 11, 0, // Skip to: 13161
6549
/* 10332 */   MCD_OPC_CheckField, 32, 4, 0, 6, 11, 0, // Skip to: 13161
6550
/* 10339 */   MCD_OPC_CheckField, 24, 4, 0, 255, 10, 0, // Skip to: 13161
6551
/* 10346 */   MCD_OPC_Decode, 222, 5, 215, 1, // Opcode: AE_MAXABS64S
6552
/* 10351 */   MCD_OPC_FilterValue, 15, 245, 10, 0, // Skip to: 13161
6553
/* 10356 */   MCD_OPC_CheckPredicate, 24, 240, 10, 0, // Skip to: 13161
6554
/* 10361 */   MCD_OPC_CheckField, 32, 4, 0, 233, 10, 0, // Skip to: 13161
6555
/* 10368 */   MCD_OPC_CheckField, 24, 4, 0, 226, 10, 0, // Skip to: 13161
6556
/* 10375 */   MCD_OPC_Decode, 230, 8, 216, 1, // Opcode: AE_MULSSD32X16_H3_L2_S2
6557
/* 10380 */   MCD_OPC_FilterValue, 128, 128, 12, 214, 10, 0, // Skip to: 13161
6558
/* 10387 */   MCD_OPC_CheckPredicate, 24, 209, 10, 0, // Skip to: 13161
6559
/* 10392 */   MCD_OPC_CheckField, 32, 4, 0, 202, 10, 0, // Skip to: 13161
6560
/* 10399 */   MCD_OPC_CheckField, 24, 4, 0, 195, 10, 0, // Skip to: 13161
6561
/* 10406 */   MCD_OPC_CheckField, 0, 20, 15, 188, 10, 0, // Skip to: 13161
6562
/* 10413 */   MCD_OPC_Decode, 232, 8, 216, 1, // Opcode: AE_MULSSFD16SS_11_00_S2
6563
/* 10418 */   MCD_OPC_FilterValue, 46, 243, 0, 0, // Skip to: 10666
6564
/* 10423 */   MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6565
/* 10426 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 10492
6566
/* 10431 */   MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6567
/* 10434 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10463
6568
/* 10439 */   MCD_OPC_CheckPredicate, 24, 157, 10, 0, // Skip to: 13161
6569
/* 10444 */   MCD_OPC_CheckField, 32, 4, 0, 150, 10, 0, // Skip to: 13161
6570
/* 10451 */   MCD_OPC_CheckField, 24, 4, 0, 143, 10, 0, // Skip to: 13161
6571
/* 10458 */   MCD_OPC_Decode, 224, 5, 215, 1, // Opcode: AE_MIN64
6572
/* 10463 */   MCD_OPC_FilterValue, 15, 133, 10, 0, // Skip to: 13161
6573
/* 10468 */   MCD_OPC_CheckPredicate, 24, 128, 10, 0, // Skip to: 13161
6574
/* 10473 */   MCD_OPC_CheckField, 32, 4, 0, 121, 10, 0, // Skip to: 13161
6575
/* 10480 */   MCD_OPC_CheckField, 24, 4, 0, 114, 10, 0, // Skip to: 13161
6576
/* 10487 */   MCD_OPC_Decode, 234, 8, 216, 1, // Opcode: AE_MULSSFD16SS_13_02_S2
6577
/* 10492 */   MCD_OPC_FilterValue, 128, 128, 4, 61, 0, 0, // Skip to: 10560
6578
/* 10499 */   MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6579
/* 10502 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10531
6580
/* 10507 */   MCD_OPC_CheckPredicate, 24, 89, 10, 0, // Skip to: 13161
6581
/* 10512 */   MCD_OPC_CheckField, 32, 4, 0, 82, 10, 0, // Skip to: 13161
6582
/* 10519 */   MCD_OPC_CheckField, 24, 4, 0, 75, 10, 0, // Skip to: 13161
6583
/* 10526 */   MCD_OPC_Decode, 225, 5, 215, 1, // Opcode: AE_MINABS32S
6584
/* 10531 */   MCD_OPC_FilterValue, 15, 65, 10, 0, // Skip to: 13161
6585
/* 10536 */   MCD_OPC_CheckPredicate, 24, 60, 10, 0, // Skip to: 13161
6586
/* 10541 */   MCD_OPC_CheckField, 32, 4, 0, 53, 10, 0, // Skip to: 13161
6587
/* 10548 */   MCD_OPC_CheckField, 24, 4, 0, 46, 10, 0, // Skip to: 13161
6588
/* 10555 */   MCD_OPC_Decode, 236, 8, 216, 1, // Opcode: AE_MULSSFD16SS_33_22_S2
6589
/* 10560 */   MCD_OPC_FilterValue, 128, 128, 8, 61, 0, 0, // Skip to: 10628
6590
/* 10567 */   MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6591
/* 10570 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10599
6592
/* 10575 */   MCD_OPC_CheckPredicate, 24, 21, 10, 0, // Skip to: 13161
6593
/* 10580 */   MCD_OPC_CheckField, 32, 4, 0, 14, 10, 0, // Skip to: 13161
6594
/* 10587 */   MCD_OPC_CheckField, 24, 4, 0, 7, 10, 0, // Skip to: 13161
6595
/* 10594 */   MCD_OPC_Decode, 226, 5, 215, 1, // Opcode: AE_MINABS64S
6596
/* 10599 */   MCD_OPC_FilterValue, 15, 253, 9, 0, // Skip to: 13161
6597
/* 10604 */   MCD_OPC_CheckPredicate, 24, 248, 9, 0, // Skip to: 13161
6598
/* 10609 */   MCD_OPC_CheckField, 32, 4, 0, 241, 9, 0, // Skip to: 13161
6599
/* 10616 */   MCD_OPC_CheckField, 24, 4, 0, 234, 9, 0, // Skip to: 13161
6600
/* 10623 */   MCD_OPC_Decode, 238, 8, 216, 1, // Opcode: AE_MULSSFD24_HH_LL_S2
6601
/* 10628 */   MCD_OPC_FilterValue, 128, 128, 12, 222, 9, 0, // Skip to: 13161
6602
/* 10635 */   MCD_OPC_CheckPredicate, 24, 217, 9, 0, // Skip to: 13161
6603
/* 10640 */   MCD_OPC_CheckField, 32, 4, 0, 210, 9, 0, // Skip to: 13161
6604
/* 10647 */   MCD_OPC_CheckField, 24, 4, 0, 203, 9, 0, // Skip to: 13161
6605
/* 10654 */   MCD_OPC_CheckField, 0, 20, 15, 196, 9, 0, // Skip to: 13161
6606
/* 10661 */   MCD_OPC_Decode, 240, 8, 216, 1, // Opcode: AE_MULSSFD24_HL_LH_S2
6607
/* 10666 */   MCD_OPC_FilterValue, 47, 183, 0, 0, // Skip to: 10854
6608
/* 10671 */   MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6609
/* 10674 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 10740
6610
/* 10679 */   MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6611
/* 10682 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10711
6612
/* 10687 */   MCD_OPC_CheckPredicate, 24, 165, 9, 0, // Skip to: 13161
6613
/* 10692 */   MCD_OPC_CheckField, 32, 4, 0, 158, 9, 0, // Skip to: 13161
6614
/* 10699 */   MCD_OPC_CheckField, 24, 4, 0, 151, 9, 0, // Skip to: 13161
6615
/* 10706 */   MCD_OPC_Decode, 197, 9, 215, 1, // Opcode: AE_NAND
6616
/* 10711 */   MCD_OPC_FilterValue, 15, 141, 9, 0, // Skip to: 13161
6617
/* 10716 */   MCD_OPC_CheckPredicate, 24, 136, 9, 0, // Skip to: 13161
6618
/* 10721 */   MCD_OPC_CheckField, 32, 4, 0, 129, 9, 0, // Skip to: 13161
6619
/* 10728 */   MCD_OPC_CheckField, 24, 4, 0, 122, 9, 0, // Skip to: 13161
6620
/* 10735 */   MCD_OPC_Decode, 242, 8, 216, 1, // Opcode: AE_MULSSFD32X16_H1_L0_S2
6621
/* 10740 */   MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 10778
6622
/* 10747 */   MCD_OPC_CheckPredicate, 24, 105, 9, 0, // Skip to: 13161
6623
/* 10752 */   MCD_OPC_CheckField, 32, 4, 0, 98, 9, 0, // Skip to: 13161
6624
/* 10759 */   MCD_OPC_CheckField, 24, 4, 0, 91, 9, 0, // Skip to: 13161
6625
/* 10766 */   MCD_OPC_CheckField, 0, 20, 15, 84, 9, 0, // Skip to: 13161
6626
/* 10773 */   MCD_OPC_Decode, 244, 8, 216, 1, // Opcode: AE_MULSSFD32X16_H3_L2_S2
6627
/* 10778 */   MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 10816
6628
/* 10785 */   MCD_OPC_CheckPredicate, 24, 67, 9, 0, // Skip to: 13161
6629
/* 10790 */   MCD_OPC_CheckField, 32, 4, 0, 60, 9, 0, // Skip to: 13161
6630
/* 10797 */   MCD_OPC_CheckField, 24, 4, 0, 53, 9, 0, // Skip to: 13161
6631
/* 10804 */   MCD_OPC_CheckField, 0, 20, 15, 46, 9, 0, // Skip to: 13161
6632
/* 10811 */   MCD_OPC_Decode, 246, 8, 215, 1, // Opcode: AE_MULZAAD24_HH_LL_S2
6633
/* 10816 */   MCD_OPC_FilterValue, 128, 128, 12, 34, 9, 0, // Skip to: 13161
6634
/* 10823 */   MCD_OPC_CheckPredicate, 24, 29, 9, 0, // Skip to: 13161
6635
/* 10828 */   MCD_OPC_CheckField, 32, 4, 0, 22, 9, 0, // Skip to: 13161
6636
/* 10835 */   MCD_OPC_CheckField, 24, 4, 0, 15, 9, 0, // Skip to: 13161
6637
/* 10842 */   MCD_OPC_CheckField, 0, 20, 15, 8, 9, 0, // Skip to: 13161
6638
/* 10849 */   MCD_OPC_Decode, 248, 8, 215, 1, // Opcode: AE_MULZAAD24_HL_LH_S2
6639
/* 10854 */   MCD_OPC_FilterValue, 48, 31, 1, 0, // Skip to: 11146
6640
/* 10859 */   MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6641
/* 10862 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 10928
6642
/* 10867 */   MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6643
/* 10870 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10899
6644
/* 10875 */   MCD_OPC_CheckPredicate, 24, 233, 8, 0, // Skip to: 13161
6645
/* 10880 */   MCD_OPC_CheckField, 32, 4, 0, 226, 8, 0, // Skip to: 13161
6646
/* 10887 */   MCD_OPC_CheckField, 24, 4, 0, 219, 8, 0, // Skip to: 13161
6647
/* 10894 */   MCD_OPC_Decode, 241, 5, 219, 1, // Opcode: AE_MOVF64
6648
/* 10899 */   MCD_OPC_FilterValue, 15, 209, 8, 0, // Skip to: 13161
6649
/* 10904 */   MCD_OPC_CheckPredicate, 24, 204, 8, 0, // Skip to: 13161
6650
/* 10909 */   MCD_OPC_CheckField, 32, 4, 0, 197, 8, 0, // Skip to: 13161
6651
/* 10916 */   MCD_OPC_CheckField, 24, 4, 0, 190, 8, 0, // Skip to: 13161
6652
/* 10923 */   MCD_OPC_Decode, 250, 8, 215, 1, // Opcode: AE_MULZAAD32X16_H0_L1_S2
6653
/* 10928 */   MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 10966
6654
/* 10935 */   MCD_OPC_CheckPredicate, 24, 173, 8, 0, // Skip to: 13161
6655
/* 10940 */   MCD_OPC_CheckField, 32, 4, 0, 166, 8, 0, // Skip to: 13161
6656
/* 10947 */   MCD_OPC_CheckField, 24, 4, 0, 159, 8, 0, // Skip to: 13161
6657
/* 10954 */   MCD_OPC_CheckField, 0, 20, 15, 152, 8, 0, // Skip to: 13161
6658
/* 10961 */   MCD_OPC_Decode, 252, 8, 215, 1, // Opcode: AE_MULZAAD32X16_H1_L0_S2
6659
/* 10966 */   MCD_OPC_FilterValue, 128, 128, 8, 68, 0, 0, // Skip to: 11041
6660
/* 10973 */   MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6661
/* 10976 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 11012
6662
/* 10981 */   MCD_OPC_CheckPredicate, 24, 127, 8, 0, // Skip to: 13161
6663
/* 10986 */   MCD_OPC_CheckField, 32, 4, 0, 120, 8, 0, // Skip to: 13161
6664
/* 10993 */   MCD_OPC_CheckField, 24, 4, 0, 113, 8, 0, // Skip to: 13161
6665
/* 11000 */   MCD_OPC_CheckField, 20, 1, 1, 106, 8, 0, // Skip to: 13161
6666
/* 11007 */   MCD_OPC_Decode, 214, 5, 220, 1, // Opcode: AE_LE32
6667
/* 11012 */   MCD_OPC_FilterValue, 15, 96, 8, 0, // Skip to: 13161
6668
/* 11017 */   MCD_OPC_CheckPredicate, 24, 91, 8, 0, // Skip to: 13161
6669
/* 11022 */   MCD_OPC_CheckField, 32, 4, 0, 84, 8, 0, // Skip to: 13161
6670
/* 11029 */   MCD_OPC_CheckField, 24, 4, 0, 77, 8, 0, // Skip to: 13161
6671
/* 11036 */   MCD_OPC_Decode, 254, 8, 215, 1, // Opcode: AE_MULZAAD32X16_H2_L3_S2
6672
/* 11041 */   MCD_OPC_FilterValue, 128, 128, 12, 65, 8, 0, // Skip to: 13161
6673
/* 11048 */   MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6674
/* 11051 */   MCD_OPC_FilterValue, 14, 61, 0, 0, // Skip to: 11117
6675
/* 11056 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
6676
/* 11059 */   MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 11088
6677
/* 11064 */   MCD_OPC_CheckPredicate, 24, 44, 8, 0, // Skip to: 13161
6678
/* 11069 */   MCD_OPC_CheckField, 32, 4, 0, 37, 8, 0, // Skip to: 13161
6679
/* 11076 */   MCD_OPC_CheckField, 24, 4, 0, 30, 8, 0, // Skip to: 13161
6680
/* 11083 */   MCD_OPC_Decode, 246, 4, 221, 1, // Opcode: AE_EQ16
6681
/* 11088 */   MCD_OPC_FilterValue, 3, 20, 8, 0, // Skip to: 13161
6682
/* 11093 */   MCD_OPC_CheckPredicate, 24, 15, 8, 0, // Skip to: 13161
6683
/* 11098 */   MCD_OPC_CheckField, 32, 4, 0, 8, 8, 0, // Skip to: 13161
6684
/* 11105 */   MCD_OPC_CheckField, 24, 4, 0, 1, 8, 0, // Skip to: 13161
6685
/* 11112 */   MCD_OPC_Decode, 213, 5, 221, 1, // Opcode: AE_LE16
6686
/* 11117 */   MCD_OPC_FilterValue, 15, 247, 7, 0, // Skip to: 13161
6687
/* 11122 */   MCD_OPC_CheckPredicate, 24, 242, 7, 0, // Skip to: 13161
6688
/* 11127 */   MCD_OPC_CheckField, 32, 4, 0, 235, 7, 0, // Skip to: 13161
6689
/* 11134 */   MCD_OPC_CheckField, 24, 4, 0, 228, 7, 0, // Skip to: 13161
6690
/* 11141 */   MCD_OPC_Decode, 128, 9, 215, 1, // Opcode: AE_MULZAAD32X16_H3_L2_S2
6691
/* 11146 */   MCD_OPC_FilterValue, 49, 27, 1, 0, // Skip to: 11434
6692
/* 11151 */   MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6693
/* 11154 */   MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11190
6694
/* 11159 */   MCD_OPC_CheckPredicate, 24, 205, 7, 0, // Skip to: 13161
6695
/* 11164 */   MCD_OPC_CheckField, 32, 4, 0, 198, 7, 0, // Skip to: 13161
6696
/* 11171 */   MCD_OPC_CheckField, 24, 4, 0, 191, 7, 0, // Skip to: 13161
6697
/* 11178 */   MCD_OPC_CheckField, 0, 20, 15, 184, 7, 0, // Skip to: 13161
6698
/* 11185 */   MCD_OPC_Decode, 130, 9, 215, 1, // Opcode: AE_MULZAAFD16SS_11_00_S2
6699
/* 11190 */   MCD_OPC_FilterValue, 128, 128, 4, 84, 0, 0, // Skip to: 11281
6700
/* 11197 */   MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6701
/* 11200 */   MCD_OPC_FilterValue, 14, 47, 0, 0, // Skip to: 11252
6702
/* 11205 */   MCD_OPC_ExtractField, 24, 6,  // Inst{29-24} ...
6703
/* 11208 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 11230
6704
/* 11213 */   MCD_OPC_CheckPredicate, 24, 151, 7, 0, // Skip to: 13161
6705
/* 11218 */   MCD_OPC_CheckField, 32, 4, 0, 144, 7, 0, // Skip to: 13161
6706
/* 11225 */   MCD_OPC_Decode, 239, 5, 222, 1, // Opcode: AE_MOVF16X4
6707
/* 11230 */   MCD_OPC_FilterValue, 16, 134, 7, 0, // Skip to: 13161
6708
/* 11235 */   MCD_OPC_CheckPredicate, 24, 129, 7, 0, // Skip to: 13161
6709
/* 11240 */   MCD_OPC_CheckField, 32, 4, 0, 122, 7, 0, // Skip to: 13161
6710
/* 11247 */   MCD_OPC_Decode, 243, 5, 222, 1, // Opcode: AE_MOVT16X4
6711
/* 11252 */   MCD_OPC_FilterValue, 15, 112, 7, 0, // Skip to: 13161
6712
/* 11257 */   MCD_OPC_CheckPredicate, 24, 107, 7, 0, // Skip to: 13161
6713
/* 11262 */   MCD_OPC_CheckField, 32, 4, 0, 100, 7, 0, // Skip to: 13161
6714
/* 11269 */   MCD_OPC_CheckField, 24, 4, 0, 93, 7, 0, // Skip to: 13161
6715
/* 11276 */   MCD_OPC_Decode, 132, 9, 215, 1, // Opcode: AE_MULZAAFD16SS_13_02_S2
6716
/* 11281 */   MCD_OPC_FilterValue, 128, 128, 8, 68, 0, 0, // Skip to: 11356
6717
/* 11288 */   MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6718
/* 11291 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 11327
6719
/* 11296 */   MCD_OPC_CheckPredicate, 24, 68, 7, 0, // Skip to: 13161
6720
/* 11301 */   MCD_OPC_CheckField, 32, 4, 0, 61, 7, 0, // Skip to: 13161
6721
/* 11308 */   MCD_OPC_CheckField, 24, 4, 0, 54, 7, 0, // Skip to: 13161
6722
/* 11315 */   MCD_OPC_CheckField, 20, 2, 0, 47, 7, 0, // Skip to: 13161
6723
/* 11322 */   MCD_OPC_Decode, 216, 5, 221, 1, // Opcode: AE_LT16
6724
/* 11327 */   MCD_OPC_FilterValue, 15, 37, 7, 0, // Skip to: 13161
6725
/* 11332 */   MCD_OPC_CheckPredicate, 24, 32, 7, 0, // Skip to: 13161
6726
/* 11337 */   MCD_OPC_CheckField, 32, 4, 0, 25, 7, 0, // Skip to: 13161
6727
/* 11344 */   MCD_OPC_CheckField, 24, 4, 0, 18, 7, 0, // Skip to: 13161
6728
/* 11351 */   MCD_OPC_Decode, 134, 9, 215, 1, // Opcode: AE_MULZAAFD16SS_33_22_S2
6729
/* 11356 */   MCD_OPC_FilterValue, 128, 128, 12, 6, 7, 0, // Skip to: 13161
6730
/* 11363 */   MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6731
/* 11366 */   MCD_OPC_FilterValue, 14, 34, 0, 0, // Skip to: 11405
6732
/* 11371 */   MCD_OPC_ExtractField, 24, 12,  // Inst{35-24} ...
6733
/* 11374 */   MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 11389
6734
/* 11379 */   MCD_OPC_CheckPredicate, 24, 241, 6, 0, // Skip to: 13161
6735
/* 11384 */   MCD_OPC_Decode, 244, 4, 223, 1, // Opcode: AE_DIV64D32_H
6736
/* 11389 */   MCD_OPC_FilterValue, 224, 1, 230, 6, 0, // Skip to: 13161
6737
/* 11395 */   MCD_OPC_CheckPredicate, 24, 225, 6, 0, // Skip to: 13161
6738
/* 11400 */   MCD_OPC_Decode, 188, 10, 224, 1, // Opcode: AE_SAT24S
6739
/* 11405 */   MCD_OPC_FilterValue, 15, 215, 6, 0, // Skip to: 13161
6740
/* 11410 */   MCD_OPC_CheckPredicate, 24, 210, 6, 0, // Skip to: 13161
6741
/* 11415 */   MCD_OPC_CheckField, 32, 4, 0, 203, 6, 0, // Skip to: 13161
6742
/* 11422 */   MCD_OPC_CheckField, 24, 4, 0, 196, 6, 0, // Skip to: 13161
6743
/* 11429 */   MCD_OPC_Decode, 136, 9, 215, 1, // Opcode: AE_MULZAAFD24_HH_LL_S2
6744
/* 11434 */   MCD_OPC_FilterValue, 50, 11, 1, 0, // Skip to: 11706
6745
/* 11439 */   MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6746
/* 11442 */   MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 11517
6747
/* 11447 */   MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6748
/* 11450 */   MCD_OPC_FilterValue, 14, 33, 0, 0, // Skip to: 11488
6749
/* 11455 */   MCD_OPC_ExtractField, 24, 12,  // Inst{35-24} ...
6750
/* 11458 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11473
6751
/* 11463 */   MCD_OPC_CheckPredicate, 24, 157, 6, 0, // Skip to: 13161
6752
/* 11468 */   MCD_OPC_Decode, 190, 10, 224, 1, // Opcode: AE_SATQ56S
6753
/* 11473 */   MCD_OPC_FilterValue, 16, 147, 6, 0, // Skip to: 13161
6754
/* 11478 */   MCD_OPC_CheckPredicate, 24, 142, 6, 0, // Skip to: 13161
6755
/* 11483 */   MCD_OPC_Decode, 232, 4, 224, 1, // Opcode: AE_CVT64F32_H
6756
/* 11488 */   MCD_OPC_FilterValue, 15, 132, 6, 0, // Skip to: 13161
6757
/* 11493 */   MCD_OPC_CheckPredicate, 24, 127, 6, 0, // Skip to: 13161
6758
/* 11498 */   MCD_OPC_CheckField, 32, 4, 0, 120, 6, 0, // Skip to: 13161
6759
/* 11505 */   MCD_OPC_CheckField, 24, 4, 0, 113, 6, 0, // Skip to: 13161
6760
/* 11512 */   MCD_OPC_Decode, 138, 9, 215, 1, // Opcode: AE_MULZAAFD24_HL_LH_S2
6761
/* 11517 */   MCD_OPC_FilterValue, 128, 128, 4, 106, 0, 0, // Skip to: 11630
6762
/* 11524 */   MCD_OPC_ExtractField, 0, 20,  // Inst{19-0} ...
6763
/* 11527 */   MCD_OPC_FilterValue, 14, 69, 0, 0, // Skip to: 11601
6764
/* 11532 */   MCD_OPC_ExtractField, 32, 8,  // Inst{39-32} ...
6765
/* 11535 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 11557
6766
/* 11540 */   MCD_OPC_CheckPredicate, 24, 80, 6, 0, // Skip to: 13161
6767
/* 11545 */   MCD_OPC_CheckField, 24, 4, 0, 73, 6, 0, // Skip to: 13161
6768
/* 11552 */   MCD_OPC_Decode, 218, 9, 225, 1, // Opcode: AE_ROUNDSP16F24ASYM
6769
/* 11557 */   MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 11579
6770
/* 11562 */   MCD_OPC_CheckPredicate, 24, 58, 6, 0, // Skip to: 13161
6771
/* 11567 */   MCD_OPC_CheckField, 24, 4, 0, 51, 6, 0, // Skip to: 13161
6772
/* 11574 */   MCD_OPC_Decode, 219, 9, 225, 1, // Opcode: AE_ROUNDSP16F24SYM
6773
/* 11579 */   MCD_OPC_FilterValue, 112, 41, 6, 0, // Skip to: 13161
6774
/* 11584 */   MCD_OPC_CheckPredicate, 24, 36, 6, 0, // Skip to: 13161
6775
/* 11589 */   MCD_OPC_CheckField, 24, 4, 0, 29, 6, 0, // Skip to: 13161
6776
/* 11596 */   MCD_OPC_Decode, 206, 10, 225, 1, // Opcode: AE_SHORTSWAP
6777
/* 11601 */   MCD_OPC_FilterValue, 15, 19, 6, 0, // Skip to: 13161
6778
/* 11606 */   MCD_OPC_CheckPredicate, 24, 14, 6, 0, // Skip to: 13161
6779
/* 11611 */   MCD_OPC_CheckField, 32, 4, 0, 7, 6, 0, // Skip to: 13161
6780
/* 11618 */   MCD_OPC_CheckField, 24, 4, 0, 0, 6, 0, // Skip to: 13161
6781
/* 11625 */   MCD_OPC_Decode, 140, 9, 215, 1, // Opcode: AE_MULZAAFD32X16_H0_L1_S2
6782
/* 11630 */   MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 11668
6783
/* 11637 */   MCD_OPC_CheckPredicate, 24, 239, 5, 0, // Skip to: 13161
6784
/* 11642 */   MCD_OPC_CheckField, 32, 4, 0, 232, 5, 0, // Skip to: 13161
6785
/* 11649 */   MCD_OPC_CheckField, 24, 4, 0, 225, 5, 0, // Skip to: 13161
6786
/* 11656 */   MCD_OPC_CheckField, 0, 20, 15, 218, 5, 0, // Skip to: 13161
6787
/* 11663 */   MCD_OPC_Decode, 142, 9, 215, 1, // Opcode: AE_MULZAAFD32X16_H1_L0_S2
6788
/* 11668 */   MCD_OPC_FilterValue, 128, 128, 12, 206, 5, 0, // Skip to: 13161
6789
/* 11675 */   MCD_OPC_CheckPredicate, 24, 201, 5, 0, // Skip to: 13161
6790
/* 11680 */   MCD_OPC_CheckField, 32, 4, 0, 194, 5, 0, // Skip to: 13161
6791
/* 11687 */   MCD_OPC_CheckField, 24, 4, 0, 187, 5, 0, // Skip to: 13161
6792
/* 11694 */   MCD_OPC_CheckField, 0, 20, 15, 180, 5, 0, // Skip to: 13161
6793
/* 11701 */   MCD_OPC_Decode, 144, 9, 215, 1, // Opcode: AE_MULZAAFD32X16_H2_L3_S2
6794
/* 11706 */   MCD_OPC_FilterValue, 51, 153, 0, 0, // Skip to: 11864
6795
/* 11711 */   MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6796
/* 11714 */   MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11750
6797
/* 11719 */   MCD_OPC_CheckPredicate, 24, 157, 5, 0, // Skip to: 13161
6798
/* 11724 */   MCD_OPC_CheckField, 32, 4, 0, 150, 5, 0, // Skip to: 13161
6799
/* 11731 */   MCD_OPC_CheckField, 24, 4, 0, 143, 5, 0, // Skip to: 13161
6800
/* 11738 */   MCD_OPC_CheckField, 0, 20, 15, 136, 5, 0, // Skip to: 13161
6801
/* 11745 */   MCD_OPC_Decode, 146, 9, 215, 1, // Opcode: AE_MULZAAFD32X16_H3_L2_S2
6802
/* 11750 */   MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 11788
6803
/* 11757 */   MCD_OPC_CheckPredicate, 24, 119, 5, 0, // Skip to: 13161
6804
/* 11762 */   MCD_OPC_CheckField, 32, 4, 0, 112, 5, 0, // Skip to: 13161
6805
/* 11769 */   MCD_OPC_CheckField, 24, 4, 0, 105, 5, 0, // Skip to: 13161
6806
/* 11776 */   MCD_OPC_CheckField, 0, 20, 15, 98, 5, 0, // Skip to: 13161
6807
/* 11783 */   MCD_OPC_Decode, 148, 9, 215, 1, // Opcode: AE_MULZASD24_HH_LL_S2
6808
/* 11788 */   MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 11826
6809
/* 11795 */   MCD_OPC_CheckPredicate, 24, 81, 5, 0, // Skip to: 13161
6810
/* 11800 */   MCD_OPC_CheckField, 32, 4, 0, 74, 5, 0, // Skip to: 13161
6811
/* 11807 */   MCD_OPC_CheckField, 24, 4, 0, 67, 5, 0, // Skip to: 13161
6812
/* 11814 */   MCD_OPC_CheckField, 0, 20, 15, 60, 5, 0, // Skip to: 13161
6813
/* 11821 */   MCD_OPC_Decode, 150, 9, 215, 1, // Opcode: AE_MULZASD24_HL_LH_S2
6814
/* 11826 */   MCD_OPC_FilterValue, 128, 128, 12, 48, 5, 0, // Skip to: 13161
6815
/* 11833 */   MCD_OPC_CheckPredicate, 24, 43, 5, 0, // Skip to: 13161
6816
/* 11838 */   MCD_OPC_CheckField, 32, 4, 0, 36, 5, 0, // Skip to: 13161
6817
/* 11845 */   MCD_OPC_CheckField, 24, 4, 0, 29, 5, 0, // Skip to: 13161
6818
/* 11852 */   MCD_OPC_CheckField, 0, 20, 15, 22, 5, 0, // Skip to: 13161
6819
/* 11859 */   MCD_OPC_Decode, 152, 9, 215, 1, // Opcode: AE_MULZASD32X16_H1_L0_S2
6820
/* 11864 */   MCD_OPC_FilterValue, 52, 153, 0, 0, // Skip to: 12022
6821
/* 11869 */   MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6822
/* 11872 */   MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11908
6823
/* 11877 */   MCD_OPC_CheckPredicate, 24, 255, 4, 0, // Skip to: 13161
6824
/* 11882 */   MCD_OPC_CheckField, 32, 4, 0, 248, 4, 0, // Skip to: 13161
6825
/* 11889 */   MCD_OPC_CheckField, 24, 4, 0, 241, 4, 0, // Skip to: 13161
6826
/* 11896 */   MCD_OPC_CheckField, 0, 20, 15, 234, 4, 0, // Skip to: 13161
6827
/* 11903 */   MCD_OPC_Decode, 154, 9, 215, 1, // Opcode: AE_MULZASD32X16_H3_L2_S2
6828
/* 11908 */   MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 11946
6829
/* 11915 */   MCD_OPC_CheckPredicate, 24, 217, 4, 0, // Skip to: 13161
6830
/* 11920 */   MCD_OPC_CheckField, 32, 4, 0, 210, 4, 0, // Skip to: 13161
6831
/* 11927 */   MCD_OPC_CheckField, 24, 4, 0, 203, 4, 0, // Skip to: 13161
6832
/* 11934 */   MCD_OPC_CheckField, 0, 20, 15, 196, 4, 0, // Skip to: 13161
6833
/* 11941 */   MCD_OPC_Decode, 156, 9, 215, 1, // Opcode: AE_MULZASFD24_HH_LL_S2
6834
/* 11946 */   MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 11984
6835
/* 11953 */   MCD_OPC_CheckPredicate, 24, 179, 4, 0, // Skip to: 13161
6836
/* 11958 */   MCD_OPC_CheckField, 32, 4, 0, 172, 4, 0, // Skip to: 13161
6837
/* 11965 */   MCD_OPC_CheckField, 24, 4, 0, 165, 4, 0, // Skip to: 13161
6838
/* 11972 */   MCD_OPC_CheckField, 0, 20, 15, 158, 4, 0, // Skip to: 13161
6839
/* 11979 */   MCD_OPC_Decode, 158, 9, 215, 1, // Opcode: AE_MULZASFD24_HL_LH_S2
6840
/* 11984 */   MCD_OPC_FilterValue, 128, 128, 12, 146, 4, 0, // Skip to: 13161
6841
/* 11991 */   MCD_OPC_CheckPredicate, 24, 141, 4, 0, // Skip to: 13161
6842
/* 11996 */   MCD_OPC_CheckField, 32, 4, 0, 134, 4, 0, // Skip to: 13161
6843
/* 12003 */   MCD_OPC_CheckField, 24, 4, 0, 127, 4, 0, // Skip to: 13161
6844
/* 12010 */   MCD_OPC_CheckField, 0, 20, 15, 120, 4, 0, // Skip to: 13161
6845
/* 12017 */   MCD_OPC_Decode, 160, 9, 215, 1, // Opcode: AE_MULZASFD32X16_H1_L0_S2
6846
/* 12022 */   MCD_OPC_FilterValue, 53, 153, 0, 0, // Skip to: 12180
6847
/* 12027 */   MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6848
/* 12030 */   MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12066
6849
/* 12035 */   MCD_OPC_CheckPredicate, 24, 97, 4, 0, // Skip to: 13161
6850
/* 12040 */   MCD_OPC_CheckField, 32, 4, 0, 90, 4, 0, // Skip to: 13161
6851
/* 12047 */   MCD_OPC_CheckField, 24, 4, 0, 83, 4, 0, // Skip to: 13161
6852
/* 12054 */   MCD_OPC_CheckField, 0, 20, 15, 76, 4, 0, // Skip to: 13161
6853
/* 12061 */   MCD_OPC_Decode, 162, 9, 215, 1, // Opcode: AE_MULZASFD32X16_H3_L2_S2
6854
/* 12066 */   MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 12104
6855
/* 12073 */   MCD_OPC_CheckPredicate, 24, 59, 4, 0, // Skip to: 13161
6856
/* 12078 */   MCD_OPC_CheckField, 32, 4, 0, 52, 4, 0, // Skip to: 13161
6857
/* 12085 */   MCD_OPC_CheckField, 24, 4, 0, 45, 4, 0, // Skip to: 13161
6858
/* 12092 */   MCD_OPC_CheckField, 0, 20, 15, 38, 4, 0, // Skip to: 13161
6859
/* 12099 */   MCD_OPC_Decode, 164, 9, 215, 1, // Opcode: AE_MULZSAD24_HH_LL_S2
6860
/* 12104 */   MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 12142
6861
/* 12111 */   MCD_OPC_CheckPredicate, 24, 21, 4, 0, // Skip to: 13161
6862
/* 12116 */   MCD_OPC_CheckField, 32, 4, 0, 14, 4, 0, // Skip to: 13161
6863
/* 12123 */   MCD_OPC_CheckField, 24, 4, 0, 7, 4, 0, // Skip to: 13161
6864
/* 12130 */   MCD_OPC_CheckField, 0, 20, 15, 0, 4, 0, // Skip to: 13161
6865
/* 12137 */   MCD_OPC_Decode, 166, 9, 215, 1, // Opcode: AE_MULZSAD32X16_H1_L0_S2
6866
/* 12142 */   MCD_OPC_FilterValue, 128, 128, 12, 244, 3, 0, // Skip to: 13161
6867
/* 12149 */   MCD_OPC_CheckPredicate, 24, 239, 3, 0, // Skip to: 13161
6868
/* 12154 */   MCD_OPC_CheckField, 32, 4, 0, 232, 3, 0, // Skip to: 13161
6869
/* 12161 */   MCD_OPC_CheckField, 24, 4, 0, 225, 3, 0, // Skip to: 13161
6870
/* 12168 */   MCD_OPC_CheckField, 0, 20, 15, 218, 3, 0, // Skip to: 13161
6871
/* 12175 */   MCD_OPC_Decode, 168, 9, 215, 1, // Opcode: AE_MULZSAD32X16_H3_L2_S2
6872
/* 12180 */   MCD_OPC_FilterValue, 54, 153, 0, 0, // Skip to: 12338
6873
/* 12185 */   MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6874
/* 12188 */   MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12224
6875
/* 12193 */   MCD_OPC_CheckPredicate, 24, 195, 3, 0, // Skip to: 13161
6876
/* 12198 */   MCD_OPC_CheckField, 32, 4, 0, 188, 3, 0, // Skip to: 13161
6877
/* 12205 */   MCD_OPC_CheckField, 24, 4, 0, 181, 3, 0, // Skip to: 13161
6878
/* 12212 */   MCD_OPC_CheckField, 0, 20, 15, 174, 3, 0, // Skip to: 13161
6879
/* 12219 */   MCD_OPC_Decode, 170, 9, 215, 1, // Opcode: AE_MULZSAFD24_HH_LL_S2
6880
/* 12224 */   MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 12262
6881
/* 12231 */   MCD_OPC_CheckPredicate, 24, 157, 3, 0, // Skip to: 13161
6882
/* 12236 */   MCD_OPC_CheckField, 32, 4, 0, 150, 3, 0, // Skip to: 13161
6883
/* 12243 */   MCD_OPC_CheckField, 24, 4, 0, 143, 3, 0, // Skip to: 13161
6884
/* 12250 */   MCD_OPC_CheckField, 0, 20, 15, 136, 3, 0, // Skip to: 13161
6885
/* 12257 */   MCD_OPC_Decode, 172, 9, 215, 1, // Opcode: AE_MULZSAFD32X16_H1_L0_S2
6886
/* 12262 */   MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 12300
6887
/* 12269 */   MCD_OPC_CheckPredicate, 24, 119, 3, 0, // Skip to: 13161
6888
/* 12274 */   MCD_OPC_CheckField, 32, 4, 0, 112, 3, 0, // Skip to: 13161
6889
/* 12281 */   MCD_OPC_CheckField, 24, 4, 0, 105, 3, 0, // Skip to: 13161
6890
/* 12288 */   MCD_OPC_CheckField, 0, 20, 15, 98, 3, 0, // Skip to: 13161
6891
/* 12295 */   MCD_OPC_Decode, 174, 9, 215, 1, // Opcode: AE_MULZSAFD32X16_H3_L2_S2
6892
/* 12300 */   MCD_OPC_FilterValue, 128, 128, 12, 86, 3, 0, // Skip to: 13161
6893
/* 12307 */   MCD_OPC_CheckPredicate, 24, 81, 3, 0, // Skip to: 13161
6894
/* 12312 */   MCD_OPC_CheckField, 32, 4, 0, 74, 3, 0, // Skip to: 13161
6895
/* 12319 */   MCD_OPC_CheckField, 24, 4, 0, 67, 3, 0, // Skip to: 13161
6896
/* 12326 */   MCD_OPC_CheckField, 0, 20, 15, 60, 3, 0, // Skip to: 13161
6897
/* 12333 */   MCD_OPC_Decode, 176, 9, 215, 1, // Opcode: AE_MULZSSD24_HH_LL_S2
6898
/* 12338 */   MCD_OPC_FilterValue, 55, 153, 0, 0, // Skip to: 12496
6899
/* 12343 */   MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6900
/* 12346 */   MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12382
6901
/* 12351 */   MCD_OPC_CheckPredicate, 24, 37, 3, 0, // Skip to: 13161
6902
/* 12356 */   MCD_OPC_CheckField, 32, 4, 0, 30, 3, 0, // Skip to: 13161
6903
/* 12363 */   MCD_OPC_CheckField, 24, 4, 0, 23, 3, 0, // Skip to: 13161
6904
/* 12370 */   MCD_OPC_CheckField, 0, 20, 15, 16, 3, 0, // Skip to: 13161
6905
/* 12377 */   MCD_OPC_Decode, 178, 9, 215, 1, // Opcode: AE_MULZSSD24_HL_LH_S2
6906
/* 12382 */   MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 12420
6907
/* 12389 */   MCD_OPC_CheckPredicate, 24, 255, 2, 0, // Skip to: 13161
6908
/* 12394 */   MCD_OPC_CheckField, 32, 4, 0, 248, 2, 0, // Skip to: 13161
6909
/* 12401 */   MCD_OPC_CheckField, 24, 4, 0, 241, 2, 0, // Skip to: 13161
6910
/* 12408 */   MCD_OPC_CheckField, 0, 20, 15, 234, 2, 0, // Skip to: 13161
6911
/* 12415 */   MCD_OPC_Decode, 180, 9, 215, 1, // Opcode: AE_MULZSSD32X16_H1_L0_S2
6912
/* 12420 */   MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 12458
6913
/* 12427 */   MCD_OPC_CheckPredicate, 24, 217, 2, 0, // Skip to: 13161
6914
/* 12432 */   MCD_OPC_CheckField, 32, 4, 0, 210, 2, 0, // Skip to: 13161
6915
/* 12439 */   MCD_OPC_CheckField, 24, 4, 0, 203, 2, 0, // Skip to: 13161
6916
/* 12446 */   MCD_OPC_CheckField, 0, 20, 15, 196, 2, 0, // Skip to: 13161
6917
/* 12453 */   MCD_OPC_Decode, 182, 9, 215, 1, // Opcode: AE_MULZSSD32X16_H3_L2_S2
6918
/* 12458 */   MCD_OPC_FilterValue, 128, 128, 12, 184, 2, 0, // Skip to: 13161
6919
/* 12465 */   MCD_OPC_CheckPredicate, 24, 179, 2, 0, // Skip to: 13161
6920
/* 12470 */   MCD_OPC_CheckField, 32, 4, 0, 172, 2, 0, // Skip to: 13161
6921
/* 12477 */   MCD_OPC_CheckField, 24, 4, 0, 165, 2, 0, // Skip to: 13161
6922
/* 12484 */   MCD_OPC_CheckField, 0, 20, 15, 158, 2, 0, // Skip to: 13161
6923
/* 12491 */   MCD_OPC_Decode, 184, 9, 215, 1, // Opcode: AE_MULZSSFD16SS_11_00_S2
6924
/* 12496 */   MCD_OPC_FilterValue, 56, 153, 0, 0, // Skip to: 12654
6925
/* 12501 */   MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6926
/* 12504 */   MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12540
6927
/* 12509 */   MCD_OPC_CheckPredicate, 24, 135, 2, 0, // Skip to: 13161
6928
/* 12514 */   MCD_OPC_CheckField, 32, 4, 0, 128, 2, 0, // Skip to: 13161
6929
/* 12521 */   MCD_OPC_CheckField, 24, 4, 0, 121, 2, 0, // Skip to: 13161
6930
/* 12528 */   MCD_OPC_CheckField, 0, 20, 15, 114, 2, 0, // Skip to: 13161
6931
/* 12535 */   MCD_OPC_Decode, 186, 9, 215, 1, // Opcode: AE_MULZSSFD16SS_13_02_S2
6932
/* 12540 */   MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 12578
6933
/* 12547 */   MCD_OPC_CheckPredicate, 24, 97, 2, 0, // Skip to: 13161
6934
/* 12552 */   MCD_OPC_CheckField, 32, 4, 0, 90, 2, 0, // Skip to: 13161
6935
/* 12559 */   MCD_OPC_CheckField, 24, 4, 0, 83, 2, 0, // Skip to: 13161
6936
/* 12566 */   MCD_OPC_CheckField, 0, 20, 15, 76, 2, 0, // Skip to: 13161
6937
/* 12573 */   MCD_OPC_Decode, 188, 9, 215, 1, // Opcode: AE_MULZSSFD16SS_33_22_S2
6938
/* 12578 */   MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 12616
6939
/* 12585 */   MCD_OPC_CheckPredicate, 24, 59, 2, 0, // Skip to: 13161
6940
/* 12590 */   MCD_OPC_CheckField, 32, 4, 0, 52, 2, 0, // Skip to: 13161
6941
/* 12597 */   MCD_OPC_CheckField, 24, 4, 0, 45, 2, 0, // Skip to: 13161
6942
/* 12604 */   MCD_OPC_CheckField, 0, 20, 15, 38, 2, 0, // Skip to: 13161
6943
/* 12611 */   MCD_OPC_Decode, 190, 9, 215, 1, // Opcode: AE_MULZSSFD24_HH_LL_S2
6944
/* 12616 */   MCD_OPC_FilterValue, 128, 128, 12, 26, 2, 0, // Skip to: 13161
6945
/* 12623 */   MCD_OPC_CheckPredicate, 24, 21, 2, 0, // Skip to: 13161
6946
/* 12628 */   MCD_OPC_CheckField, 32, 4, 0, 14, 2, 0, // Skip to: 13161
6947
/* 12635 */   MCD_OPC_CheckField, 24, 4, 0, 7, 2, 0, // Skip to: 13161
6948
/* 12642 */   MCD_OPC_CheckField, 0, 20, 15, 0, 2, 0, // Skip to: 13161
6949
/* 12649 */   MCD_OPC_Decode, 192, 9, 215, 1, // Opcode: AE_MULZSSFD24_HL_LH_S2
6950
/* 12654 */   MCD_OPC_FilterValue, 57, 153, 0, 0, // Skip to: 12812
6951
/* 12659 */   MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6952
/* 12662 */   MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12698
6953
/* 12667 */   MCD_OPC_CheckPredicate, 24, 233, 1, 0, // Skip to: 13161
6954
/* 12672 */   MCD_OPC_CheckField, 32, 4, 0, 226, 1, 0, // Skip to: 13161
6955
/* 12679 */   MCD_OPC_CheckField, 24, 4, 0, 219, 1, 0, // Skip to: 13161
6956
/* 12686 */   MCD_OPC_CheckField, 0, 20, 15, 212, 1, 0, // Skip to: 13161
6957
/* 12693 */   MCD_OPC_Decode, 194, 9, 215, 1, // Opcode: AE_MULZSSFD32X16_H1_L0_S2
6958
/* 12698 */   MCD_OPC_FilterValue, 128, 128, 4, 31, 0, 0, // Skip to: 12736
6959
/* 12705 */   MCD_OPC_CheckPredicate, 24, 195, 1, 0, // Skip to: 13161
6960
/* 12710 */   MCD_OPC_CheckField, 32, 4, 0, 188, 1, 0, // Skip to: 13161
6961
/* 12717 */   MCD_OPC_CheckField, 24, 4, 0, 181, 1, 0, // Skip to: 13161
6962
/* 12724 */   MCD_OPC_CheckField, 0, 20, 15, 174, 1, 0, // Skip to: 13161
6963
/* 12731 */   MCD_OPC_Decode, 196, 9, 215, 1, // Opcode: AE_MULZSSFD32X16_H3_L2_S2
6964
/* 12736 */   MCD_OPC_FilterValue, 128, 128, 8, 31, 0, 0, // Skip to: 12774
6965
/* 12743 */   MCD_OPC_CheckPredicate, 24, 157, 1, 0, // Skip to: 13161
6966
/* 12748 */   MCD_OPC_CheckField, 32, 4, 0, 150, 1, 0, // Skip to: 13161
6967
/* 12755 */   MCD_OPC_CheckField, 24, 4, 0, 143, 1, 0, // Skip to: 13161
6968
/* 12762 */   MCD_OPC_CheckField, 0, 20, 15, 136, 1, 0, // Skip to: 13161
6969
/* 12769 */   MCD_OPC_Decode, 213, 10, 226, 1, // Opcode: AE_SLAI16S
6970
/* 12774 */   MCD_OPC_FilterValue, 128, 128, 12, 124, 1, 0, // Skip to: 13161
6971
/* 12781 */   MCD_OPC_CheckPredicate, 24, 119, 1, 0, // Skip to: 13161
6972
/* 12786 */   MCD_OPC_CheckField, 32, 4, 0, 112, 1, 0, // Skip to: 13161
6973
/* 12793 */   MCD_OPC_CheckField, 24, 4, 0, 105, 1, 0, // Skip to: 13161
6974
/* 12800 */   MCD_OPC_CheckField, 0, 20, 15, 98, 1, 0, // Skip to: 13161
6975
/* 12807 */   MCD_OPC_Decode, 236, 10, 226, 1, // Opcode: AE_SRAI16
6976
/* 12812 */   MCD_OPC_FilterValue, 58, 88, 1, 0, // Skip to: 13161
6977
/* 12817 */   MCD_OPC_ExtractField, 40, 18,  // Inst{57-40} ...
6978
/* 12820 */   MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12856
6979
/* 12825 */   MCD_OPC_CheckPredicate, 24, 75, 1, 0, // Skip to: 13161
6980
/* 12830 */   MCD_OPC_CheckField, 32, 4, 0, 68, 1, 0, // Skip to: 13161
6981
/* 12837 */   MCD_OPC_CheckField, 24, 4, 0, 61, 1, 0, // Skip to: 13161
6982
/* 12844 */   MCD_OPC_CheckField, 0, 20, 15, 54, 1, 0, // Skip to: 13161
6983
/* 12851 */   MCD_OPC_Decode, 237, 10, 226, 1, // Opcode: AE_SRAI16R
6984
/* 12856 */   MCD_OPC_FilterValue, 128, 128, 8, 42, 1, 0, // Skip to: 13161
6985
/* 12863 */   MCD_OPC_ExtractField, 32, 8,  // Inst{39-32} ...
6986
/* 12866 */   MCD_OPC_FilterValue, 16, 24, 0, 0, // Skip to: 12895
6987
/* 12871 */   MCD_OPC_CheckPredicate, 24, 29, 1, 0, // Skip to: 13161
6988
/* 12876 */   MCD_OPC_CheckField, 24, 4, 0, 22, 1, 0, // Skip to: 13161
6989
/* 12883 */   MCD_OPC_CheckField, 0, 20, 15, 15, 1, 0, // Skip to: 13161
6990
/* 12890 */   MCD_OPC_Decode, 222, 10, 225, 1, // Opcode: AE_SLAS24S
6991
/* 12895 */   MCD_OPC_FilterValue, 32, 24, 0, 0, // Skip to: 12924
6992
/* 12900 */   MCD_OPC_CheckPredicate, 24, 0, 1, 0, // Skip to: 13161
6993
/* 12905 */   MCD_OPC_CheckField, 24, 4, 0, 249, 0, 0, // Skip to: 13161
6994
/* 12912 */   MCD_OPC_CheckField, 0, 20, 15, 242, 0, 0, // Skip to: 13161
6995
/* 12919 */   MCD_OPC_Decode, 223, 10, 225, 1, // Opcode: AE_SLAS32
6996
/* 12924 */   MCD_OPC_FilterValue, 48, 24, 0, 0, // Skip to: 12953
6997
/* 12929 */   MCD_OPC_CheckPredicate, 24, 227, 0, 0, // Skip to: 13161
6998
/* 12934 */   MCD_OPC_CheckField, 24, 4, 0, 220, 0, 0, // Skip to: 13161
6999
/* 12941 */   MCD_OPC_CheckField, 0, 20, 15, 213, 0, 0, // Skip to: 13161
7000
/* 12948 */   MCD_OPC_Decode, 224, 10, 225, 1, // Opcode: AE_SLAS32S
7001
/* 12953 */   MCD_OPC_FilterValue, 64, 24, 0, 0, // Skip to: 12982
7002
/* 12958 */   MCD_OPC_CheckPredicate, 24, 198, 0, 0, // Skip to: 13161
7003
/* 12963 */   MCD_OPC_CheckField, 24, 4, 0, 191, 0, 0, // Skip to: 13161
7004
/* 12970 */   MCD_OPC_CheckField, 0, 20, 15, 184, 0, 0, // Skip to: 13161
7005
/* 12977 */   MCD_OPC_Decode, 225, 10, 225, 1, // Opcode: AE_SLAS64
7006
/* 12982 */   MCD_OPC_FilterValue, 112, 24, 0, 0, // Skip to: 13011
7007
/* 12987 */   MCD_OPC_CheckPredicate, 24, 169, 0, 0, // Skip to: 13161
7008
/* 12992 */   MCD_OPC_CheckField, 24, 4, 0, 162, 0, 0, // Skip to: 13161
7009
/* 12999 */   MCD_OPC_CheckField, 0, 20, 15, 155, 0, 0, // Skip to: 13161
7010
/* 13006 */   MCD_OPC_Decode, 228, 10, 225, 1, // Opcode: AE_SLASSQ56S
7011
/* 13011 */   MCD_OPC_FilterValue, 144, 1, 24, 0, 0, // Skip to: 13041
7012
/* 13017 */   MCD_OPC_CheckPredicate, 24, 139, 0, 0, // Skip to: 13161
7013
/* 13022 */   MCD_OPC_CheckField, 24, 4, 0, 132, 0, 0, // Skip to: 13161
7014
/* 13029 */   MCD_OPC_CheckField, 0, 20, 15, 125, 0, 0, // Skip to: 13161
7015
/* 13036 */   MCD_OPC_Decode, 243, 10, 225, 1, // Opcode: AE_SRAS32
7016
/* 13041 */   MCD_OPC_FilterValue, 160, 1, 24, 0, 0, // Skip to: 13071
7017
/* 13047 */   MCD_OPC_CheckPredicate, 24, 109, 0, 0, // Skip to: 13161
7018
/* 13052 */   MCD_OPC_CheckField, 24, 4, 0, 102, 0, 0, // Skip to: 13161
7019
/* 13059 */   MCD_OPC_CheckField, 0, 20, 15, 95, 0, 0, // Skip to: 13161
7020
/* 13066 */   MCD_OPC_Decode, 244, 10, 225, 1, // Opcode: AE_SRAS64
7021
/* 13071 */   MCD_OPC_FilterValue, 192, 1, 24, 0, 0, // Skip to: 13101
7022
/* 13077 */   MCD_OPC_CheckPredicate, 24, 79, 0, 0, // Skip to: 13161
7023
/* 13082 */   MCD_OPC_CheckField, 24, 4, 0, 72, 0, 0, // Skip to: 13161
7024
/* 13089 */   MCD_OPC_CheckField, 0, 20, 15, 65, 0, 0, // Skip to: 13161
7025
/* 13096 */   MCD_OPC_Decode, 250, 10, 225, 1, // Opcode: AE_SRLS24
7026
/* 13101 */   MCD_OPC_FilterValue, 208, 1, 24, 0, 0, // Skip to: 13131
7027
/* 13107 */   MCD_OPC_CheckPredicate, 24, 49, 0, 0, // Skip to: 13161
7028
/* 13112 */   MCD_OPC_CheckField, 24, 4, 0, 42, 0, 0, // Skip to: 13161
7029
/* 13119 */   MCD_OPC_CheckField, 0, 20, 15, 35, 0, 0, // Skip to: 13161
7030
/* 13126 */   MCD_OPC_Decode, 251, 10, 225, 1, // Opcode: AE_SRLS32
7031
/* 13131 */   MCD_OPC_FilterValue, 224, 1, 24, 0, 0, // Skip to: 13161
7032
/* 13137 */   MCD_OPC_CheckPredicate, 24, 19, 0, 0, // Skip to: 13161
7033
/* 13142 */   MCD_OPC_CheckField, 24, 4, 0, 12, 0, 0, // Skip to: 13161
7034
/* 13149 */   MCD_OPC_CheckField, 0, 20, 15, 5, 0, 0, // Skip to: 13161
7035
/* 13156 */   MCD_OPC_Decode, 252, 10, 225, 1, // Opcode: AE_SRLS64
7036
/* 13161 */   MCD_OPC_Fail,
7037
  0
7038
};
7039
7040
38.2k
static bool checkDecoderPredicate(MCInst *Inst, unsigned Idx) {
7041
38.2k
  switch (Idx) {
7042
0
  default: CS_ASSERT_RET_VAL(0 && "Invalid index!", false);
7043
14.0k
  case 0:
7044
14.0k
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureDensity));
7045
1.79k
  case 1:
7046
1.79k
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureDensity) && Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureDebug));
7047
15
  case 2:
7048
15
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureWindowed) && Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureDensity));
7049
2.75k
  case 3:
7050
2.75k
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureWindowed));
7051
0
  case 4:
7052
0
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureException));
7053
345
  case 5:
7054
345
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureInterrupt));
7055
102
  case 6:
7056
102
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureDebug));
7057
573
  case 7:
7058
573
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureBoolean));
7059
0
  case 8:
7060
0
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureRegionProtection));
7061
1
  case 9:
7062
1
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureNSA));
7063
8
  case 10:
7064
8
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureMul16));
7065
43
  case 11:
7066
43
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureSEXT));
7067
1
  case 12:
7068
1
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureCLAMPS));
7069
72
  case 13:
7070
72
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureMINMAX));
7071
10
  case 14:
7072
10
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureMul32));
7073
14
  case 15:
7074
14
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureMul32High));
7075
171
  case 16:
7076
171
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureDiv32));
7077
379
  case 17:
7078
379
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureESP32S2Ops));
7079
4.08k
  case 18:
7080
4.08k
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureSingleFloat));
7081
14
  case 19:
7082
14
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureBoolean) && Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureSingleFloat));
7083
457
  case 20:
7084
457
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureS32C1I));
7085
649
  case 21:
7086
649
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureMAC16));
7087
12.5k
  case 22:
7088
12.5k
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureESP32S3Ops));
7089
17
  case 23:
7090
17
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureLoop));
7091
41
  case 24:
7092
41
    return (Xtensa_getFeatureBits(Inst->csh->mode, Xtensa_FeatureHIFI3));
7093
38.2k
  }
7094
38.2k
}
7095
7096
#define DecodeToMCInst(fname, fieldname, InsnType) \
7097
static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
7098
55.7k
    uint64_t Address, const void *Decoder, bool *DecodeComplete) \
7099
55.7k
{ \
7100
55.7k
  *DecodeComplete = true; \
7101
55.7k
  InsnType tmp; \
7102
55.7k
  switch (Idx) { \
7103
0
  default: CS_ASSERT_RET_VAL(0 && "Invalid index!", MCDisassembler_Fail); \
7104
3.83k
  case 0: \
7105
3.83k
    tmp = fieldname(insn, 4, 4); \
7106
3.83k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7107
3.83k
    tmp = fieldname(insn, 8, 8); \
7108
3.83k
    if (!Check(&S, decodeMem32nOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7109
3.83k
    return S; \
7110
6.05k
  case 1: \
7111
6.05k
    tmp = fieldname(insn, 12, 4); \
7112
6.05k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7113
6.05k
    tmp = fieldname(insn, 8, 4); \
7114
6.05k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7115
6.05k
    tmp = fieldname(insn, 4, 4); \
7116
6.05k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7117
6.05k
    return S; \
7118
6.05k
  case 2: \
7119
3.35k
    tmp = fieldname(insn, 12, 4); \
7120
3.35k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7121
3.35k
    tmp = fieldname(insn, 8, 4); \
7122
3.35k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7123
3.35k
    tmp = fieldname(insn, 4, 4); \
7124
3.35k
    if (!Check(&S, decodeImm1n_15Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7125
3.35k
    return S; \
7126
3.35k
  case 3: \
7127
462
    tmp = fieldname(insn, 8, 4); \
7128
462
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7129
462
    return S; \
7130
1.48k
  case 4: \
7131
1.48k
    tmp = fieldname(insn, 8, 4); \
7132
1.48k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7133
1.48k
    tmp = 0x0; \
7134
1.48k
    tmp |= fieldname(insn, 4, 3) << 4; \
7135
1.48k
    tmp |= fieldname(insn, 12, 4) << 0; \
7136
1.48k
    if (!Check(&S, decodeImm32n_95Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7137
1.48k
    return S; \
7138
1.48k
  case 5: \
7139
811
    tmp = fieldname(insn, 4, 4); \
7140
811
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7141
811
    tmp = fieldname(insn, 8, 4); \
7142
811
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7143
811
    return S; \
7144
2.48k
  case 6: \
7145
2.48k
    return S; \
7146
811
  case 7: \
7147
69
    tmp = fieldname(insn, 8, 4); \
7148
69
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7149
69
    return S; \
7150
102
  case 8: \
7151
102
    tmp = fieldname(insn, 8, 4); \
7152
102
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7153
102
    tmp = fieldname(insn, 4, 4); \
7154
102
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7155
102
    return S; \
7156
193
  case 9: \
7157
193
    tmp = fieldname(insn, 4, 4); \
7158
193
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7159
193
    tmp = fieldname(insn, 8, 4); \
7160
193
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7161
193
    return S; \
7162
218
  case 10: \
7163
218
    tmp = fieldname(insn, 4, 4); \
7164
218
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7165
218
    tmp = fieldname(insn, 8, 4); \
7166
218
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7167
218
    return S; \
7168
218
  case 11: \
7169
188
    tmp = fieldname(insn, 12, 4); \
7170
188
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7171
188
    tmp = fieldname(insn, 8, 4); \
7172
188
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7173
188
    tmp = 0x0; \
7174
188
    tmp |= fieldname(insn, 4, 4) << 0; \
7175
188
    tmp |= fieldname(insn, 20, 1) << 4; \
7176
188
    if (!Check(&S, decodeShimm1_31Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7177
188
    return S; \
7178
188
  case 12: \
7179
93
    tmp = fieldname(insn, 12, 4); \
7180
93
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7181
93
    tmp = fieldname(insn, 4, 4); \
7182
93
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7183
93
    tmp = 0x0; \
7184
93
    tmp |= fieldname(insn, 8, 4) << 0; \
7185
93
    tmp |= fieldname(insn, 20, 1) << 4; \
7186
93
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7187
93
    return S; \
7188
93
  case 13: \
7189
10
    tmp = 0x0; \
7190
10
    tmp |= fieldname(insn, 4, 1) << 4; \
7191
10
    tmp |= fieldname(insn, 8, 4) << 0; \
7192
10
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7193
10
    return S; \
7194
24
  case 14: \
7195
24
    tmp = fieldname(insn, 4, 4); \
7196
24
    if (!Check(&S, decodeImm8n_7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7197
24
    return S; \
7198
64
  case 15: \
7199
64
    tmp = fieldname(insn, 12, 4); \
7200
64
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7201
64
    tmp = fieldname(insn, 4, 4); \
7202
64
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7203
64
    tmp = fieldname(insn, 8, 4); \
7204
64
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7205
64
    return S; \
7206
286
  case 16: \
7207
286
    tmp = fieldname(insn, 12, 4); \
7208
286
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7209
286
    tmp = fieldname(insn, 4, 4); \
7210
286
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7211
286
    return S; \
7212
1.03k
  case 17: \
7213
1.03k
    tmp = fieldname(insn, 4, 4); \
7214
1.03k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7215
1.03k
    tmp = fieldname(insn, 8, 8); \
7216
1.03k
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7217
1.03k
    tmp = fieldname(insn, 4, 4); \
7218
1.02k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7219
1.02k
    tmp = fieldname(insn, 8, 8); \
7220
1.02k
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7221
1.02k
    return S; \
7222
1.02k
  case 18: \
7223
10
    tmp = fieldname(insn, 12, 4); \
7224
10
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7225
10
    tmp = fieldname(insn, 8, 4); \
7226
10
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7227
10
    return S; \
7228
228
  case 19: \
7229
228
    tmp = fieldname(insn, 12, 4); \
7230
228
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7231
228
    tmp = fieldname(insn, 8, 4); \
7232
228
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7233
228
    tmp = fieldname(insn, 4, 4); \
7234
228
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7235
228
    return S; \
7236
1.17k
  case 20: \
7237
1.17k
    tmp = fieldname(insn, 4, 4); \
7238
1.17k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7239
1.17k
    tmp = fieldname(insn, 8, 8); \
7240
1.17k
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7241
1.17k
    return S; \
7242
1.17k
  case 21: \
7243
519
    tmp = fieldname(insn, 8, 8); \
7244
519
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7245
519
    tmp = fieldname(insn, 4, 4); \
7246
517
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7247
517
    return S; \
7248
517
  case 22: \
7249
44
    tmp = fieldname(insn, 12, 4); \
7250
44
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7251
44
    tmp = fieldname(insn, 8, 4); \
7252
44
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7253
44
    tmp = fieldname(insn, 4, 4); \
7254
44
    if (!Check(&S, decodeImm7_22Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7255
44
    return S; \
7256
92
  case 23: \
7257
92
    tmp = fieldname(insn, 12, 4); \
7258
92
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7259
92
    tmp = fieldname(insn, 12, 4); \
7260
92
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7261
92
    tmp = fieldname(insn, 8, 4); \
7262
92
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7263
92
    tmp = fieldname(insn, 4, 4); \
7264
92
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7265
92
    return S; \
7266
224
  case 24: \
7267
224
    tmp = fieldname(insn, 12, 4); \
7268
224
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7269
224
    tmp = fieldname(insn, 4, 8); \
7270
224
    if (!Check(&S, DecodeURRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7271
224
    return S; \
7272
224
  case 25: \
7273
133
    tmp = fieldname(insn, 4, 4); \
7274
133
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7275
133
    return S; \
7276
311
  case 26: \
7277
311
    tmp = fieldname(insn, 8, 8); \
7278
311
    if (!Check(&S, DecodeURRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7279
311
    tmp = fieldname(insn, 4, 4); \
7280
174
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7281
174
    return S; \
7282
476
  case 27: \
7283
476
    tmp = fieldname(insn, 12, 4); \
7284
476
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7285
476
    tmp = fieldname(insn, 4, 4); \
7286
476
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7287
476
    tmp = 0x0; \
7288
476
    tmp |= fieldname(insn, 8, 4) << 0; \
7289
476
    tmp |= fieldname(insn, 16, 1) << 4; \
7290
476
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7291
476
    tmp = fieldname(insn, 20, 4); \
7292
476
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7293
476
    return S; \
7294
476
  case 28: \
7295
292
    tmp = fieldname(insn, 4, 8); \
7296
292
    if (!Check(&S, decodeSelect_256Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7297
292
    return S; \
7298
292
  case 29: \
7299
93
    tmp = fieldname(insn, 8, 4); \
7300
93
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7301
93
    tmp = fieldname(insn, 4, 4); \
7302
93
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7303
93
    return S; \
7304
93
  case 30: \
7305
57
    tmp = fieldname(insn, 12, 4); \
7306
57
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7307
57
    tmp = fieldname(insn, 8, 4); \
7308
57
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7309
57
    tmp = fieldname(insn, 4, 4); \
7310
57
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7311
57
    return S; \
7312
139
  case 31: \
7313
139
    tmp = fieldname(insn, 4, 4); \
7314
139
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7315
139
    tmp = fieldname(insn, 8, 4); \
7316
139
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7317
139
    tmp = fieldname(insn, 12, 4) << 2; \
7318
139
    if (!Check(&S, decodeImm64n_4nOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7319
139
    return S; \
7320
141
  case 32: \
7321
141
    tmp = fieldname(insn, 12, 4); \
7322
141
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7323
141
    tmp = fieldname(insn, 8, 4); \
7324
141
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7325
141
    tmp = fieldname(insn, 8, 4); \
7326
141
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7327
141
    tmp = fieldname(insn, 4, 4); \
7328
141
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7329
141
    return S; \
7330
183
  case 33: \
7331
183
    tmp = fieldname(insn, 8, 4); \
7332
183
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7333
183
    tmp = fieldname(insn, 12, 4); \
7334
183
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7335
183
    tmp = fieldname(insn, 8, 4); \
7336
183
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7337
183
    tmp = fieldname(insn, 4, 4); \
7338
183
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7339
183
    return S; \
7340
183
  case 34: \
7341
153
    tmp = fieldname(insn, 12, 4); \
7342
153
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7343
153
    tmp = fieldname(insn, 8, 4); \
7344
153
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7345
153
    tmp = fieldname(insn, 4, 4); \
7346
153
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7347
153
    return S; \
7348
338
  case 35: \
7349
338
    tmp = fieldname(insn, 12, 4); \
7350
338
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7351
338
    tmp = fieldname(insn, 8, 4); \
7352
338
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7353
338
    tmp = fieldname(insn, 4, 4); \
7354
338
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7355
338
    return S; \
7356
787
  case 36: \
7357
787
    tmp = fieldname(insn, 12, 4); \
7358
787
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7359
787
    tmp = fieldname(insn, 12, 4); \
7360
787
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7361
787
    tmp = fieldname(insn, 8, 4); \
7362
787
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7363
787
    tmp = fieldname(insn, 4, 4); \
7364
787
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7365
787
    return S; \
7366
787
  case 37: \
7367
131
    tmp = fieldname(insn, 12, 4); \
7368
131
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7369
131
    tmp = fieldname(insn, 8, 4); \
7370
131
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7371
131
    tmp = fieldname(insn, 4, 4); \
7372
131
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7373
131
    return S; \
7374
131
  case 38: \
7375
53
    tmp = fieldname(insn, 12, 4); \
7376
53
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7377
53
    tmp = fieldname(insn, 12, 4); \
7378
53
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7379
53
    tmp = fieldname(insn, 8, 4); \
7380
53
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7381
53
    tmp = fieldname(insn, 4, 4); \
7382
53
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7383
53
    return S; \
7384
154
  case 39: \
7385
154
    tmp = fieldname(insn, 12, 4); \
7386
154
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7387
154
    tmp = fieldname(insn, 8, 4); \
7388
154
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7389
154
    tmp = fieldname(insn, 4, 4); \
7390
154
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7391
154
    return S; \
7392
154
  case 40: \
7393
14
    tmp = fieldname(insn, 12, 4); \
7394
14
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7395
14
    tmp = fieldname(insn, 12, 4); \
7396
14
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7397
14
    tmp = fieldname(insn, 8, 4); \
7398
14
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7399
14
    tmp = fieldname(insn, 4, 4); \
7400
14
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7401
14
    return S; \
7402
267
  case 41: \
7403
267
    tmp = fieldname(insn, 12, 4); \
7404
267
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7405
267
    tmp = fieldname(insn, 8, 4); \
7406
267
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7407
267
    return S; \
7408
267
  case 42: \
7409
16
    tmp = fieldname(insn, 12, 4); \
7410
16
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7411
16
    tmp = fieldname(insn, 8, 4); \
7412
16
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7413
16
    return S; \
7414
16
  case 43: \
7415
7
    tmp = fieldname(insn, 12, 4); \
7416
7
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7417
7
    tmp = fieldname(insn, 8, 4); \
7418
7
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7419
7
    return S; \
7420
431
  case 44: \
7421
431
    tmp = fieldname(insn, 12, 4); \
7422
431
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7423
431
    tmp = fieldname(insn, 8, 4); \
7424
431
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7425
431
    return S; \
7426
431
  case 45: \
7427
36
    tmp = fieldname(insn, 12, 4); \
7428
36
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7429
36
    tmp = fieldname(insn, 12, 4); \
7430
36
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7431
36
    tmp = fieldname(insn, 8, 4); \
7432
36
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7433
36
    return S; \
7434
3.08k
  case 46: \
7435
3.08k
    tmp = fieldname(insn, 4, 4); \
7436
3.08k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7437
3.08k
    tmp = fieldname(insn, 8, 16); \
7438
3.08k
    if (!Check(&S, decodeL32ROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7439
3.08k
    return S; \
7440
3.08k
  case 47: \
7441
1.40k
    tmp = fieldname(insn, 4, 4); \
7442
1.40k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7443
1.40k
    tmp = 0x0; \
7444
1.40k
    tmp |= fieldname(insn, 8, 4) << 0; \
7445
1.40k
    tmp |= fieldname(insn, 16, 8) << 4; \
7446
1.40k
    if (!Check(&S, decodeMem8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7447
1.40k
    return S; \
7448
1.40k
  case 48: \
7449
419
    tmp = fieldname(insn, 4, 4); \
7450
419
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7451
419
    tmp = 0x0; \
7452
419
    tmp |= fieldname(insn, 8, 4) << 0; \
7453
419
    tmp |= fieldname(insn, 16, 8) << 4; \
7454
419
    if (!Check(&S, decodeMem16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7455
419
    return S; \
7456
419
  case 49: \
7457
294
    tmp = fieldname(insn, 4, 4); \
7458
294
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7459
294
    tmp = 0x0; \
7460
294
    tmp |= fieldname(insn, 8, 4) << 0; \
7461
294
    tmp |= fieldname(insn, 16, 8) << 4; \
7462
294
    if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7463
294
    return S; \
7464
308
  case 50: \
7465
308
    tmp = fieldname(insn, 4, 4); \
7466
308
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7467
308
    tmp = 0x0; \
7468
308
    tmp |= fieldname(insn, 8, 4) << 8; \
7469
308
    tmp |= fieldname(insn, 16, 8) << 0; \
7470
308
    if (!Check(&S, decodeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7471
308
    return S; \
7472
308
  case 51: \
7473
132
    tmp = fieldname(insn, 4, 4); \
7474
132
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7475
132
    tmp = fieldname(insn, 8, 4); \
7476
132
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7477
132
    tmp = fieldname(insn, 16, 8); \
7478
132
    if (!Check(&S, decodeImm8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7479
132
    return S; \
7480
256
  case 52: \
7481
256
    tmp = fieldname(insn, 4, 4); \
7482
256
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7483
256
    tmp = fieldname(insn, 8, 4); \
7484
256
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7485
256
    tmp = fieldname(insn, 16, 8) << 8; \
7486
256
    if (!Check(&S, decodeImm8_sh8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7487
256
    return S; \
7488
457
  case 53: \
7489
457
    tmp = fieldname(insn, 4, 4); \
7490
457
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7491
457
    tmp = fieldname(insn, 4, 4); \
7492
457
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7493
457
    tmp = 0x0; \
7494
457
    tmp |= fieldname(insn, 8, 4) << 0; \
7495
457
    tmp |= fieldname(insn, 16, 8) << 4; \
7496
457
    if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7497
457
    return S; \
7498
457
  case 54: \
7499
384
    tmp = fieldname(insn, 4, 4); \
7500
384
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7501
384
    tmp = 0x0; \
7502
384
    tmp |= fieldname(insn, 8, 4) << 0; \
7503
384
    tmp |= fieldname(insn, 16, 8) << 4; \
7504
384
    if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7505
384
    return S; \
7506
384
  case 55: \
7507
341
    tmp = fieldname(insn, 4, 4); \
7508
341
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7509
341
    tmp = fieldname(insn, 8, 4); \
7510
341
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7511
341
    tmp = fieldname(insn, 8, 4); \
7512
341
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7513
341
    tmp = fieldname(insn, 16, 8) << 2; \
7514
341
    if (!Check(&S, decodeOffset8m32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7515
341
    return S; \
7516
609
  case 56: \
7517
609
    tmp = fieldname(insn, 8, 4); \
7518
609
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7519
609
    tmp = fieldname(insn, 4, 4); \
7520
609
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7521
609
    tmp = fieldname(insn, 8, 4); \
7522
609
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7523
609
    tmp = fieldname(insn, 16, 8) << 2; \
7524
609
    if (!Check(&S, decodeOffset8m32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7525
609
    return S; \
7526
609
  case 57: \
7527
18
    tmp = fieldname(insn, 12, 2); \
7528
18
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7529
18
    tmp = fieldname(insn, 8, 4); \
7530
18
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7531
18
    tmp = fieldname(insn, 8, 4); \
7532
18
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7533
18
    tmp = fieldname(insn, 14, 1); \
7534
18
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7535
18
    tmp = fieldname(insn, 6, 1); \
7536
18
    if (!Check(&S, DecodeMR23RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7537
18
    return S; \
7538
18
  case 58: \
7539
12
    tmp = fieldname(insn, 14, 1); \
7540
12
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7541
12
    tmp = fieldname(insn, 6, 1); \
7542
12
    if (!Check(&S, DecodeMR23RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7543
12
    return S; \
7544
12
  case 59: \
7545
12
    tmp = fieldname(insn, 8, 4); \
7546
12
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7547
12
    tmp = fieldname(insn, 6, 1); \
7548
12
    if (!Check(&S, DecodeMR23RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7549
12
    return S; \
7550
234
  case 60: \
7551
234
    tmp = fieldname(insn, 12, 2); \
7552
234
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7553
234
    tmp = fieldname(insn, 8, 4); \
7554
234
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7555
234
    tmp = fieldname(insn, 8, 4); \
7556
234
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7557
234
    tmp = fieldname(insn, 14, 1); \
7558
234
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7559
234
    tmp = fieldname(insn, 4, 4); \
7560
234
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7561
234
    return S; \
7562
234
  case 61: \
7563
36
    tmp = fieldname(insn, 12, 2); \
7564
36
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7565
36
    tmp = fieldname(insn, 8, 4); \
7566
36
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7567
36
    tmp = fieldname(insn, 8, 4); \
7568
36
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7569
36
    tmp = fieldname(insn, 14, 1); \
7570
36
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7571
36
    tmp = fieldname(insn, 4, 4); \
7572
36
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7573
36
    return S; \
7574
36
  case 62: \
7575
15
    tmp = fieldname(insn, 14, 1); \
7576
15
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7577
15
    tmp = fieldname(insn, 4, 4); \
7578
15
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7579
15
    return S; \
7580
44
  case 63: \
7581
44
    tmp = fieldname(insn, 12, 2); \
7582
44
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7583
44
    tmp = fieldname(insn, 8, 4); \
7584
44
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7585
44
    tmp = fieldname(insn, 8, 4); \
7586
44
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7587
44
    return S; \
7588
2.56k
  case 64: \
7589
2.56k
    tmp = fieldname(insn, 6, 18); \
7590
2.56k
    if (!Check(&S, decodeCallOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7591
2.56k
    return S; \
7592
2.56k
  case 65: \
7593
1.04k
    tmp = fieldname(insn, 6, 18); \
7594
1.04k
    if (!Check(&S, decodeJumpOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7595
1.04k
    return S; \
7596
1.22k
  case 66: \
7597
1.22k
    tmp = fieldname(insn, 8, 4); \
7598
1.22k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7599
1.22k
    tmp = fieldname(insn, 12, 12); \
7600
1.22k
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7601
1.22k
    return S; \
7602
1.22k
  case 67: \
7603
779
    tmp = fieldname(insn, 8, 4); \
7604
779
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7605
779
    tmp = fieldname(insn, 12, 4); \
7606
779
    if (!Check(&S, decodeB4constOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7607
779
    tmp = fieldname(insn, 16, 8); \
7608
779
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7609
779
    return S; \
7610
779
  case 68: \
7611
326
    tmp = fieldname(insn, 8, 4); \
7612
326
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7613
326
    tmp = fieldname(insn, 12, 12) << 3; \
7614
326
    if (!Check(&S, decodeEntry_Imm12OpValue(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7615
326
    return S; \
7616
326
  case 69: \
7617
35
    tmp = fieldname(insn, 8, 4); \
7618
35
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7619
35
    tmp = fieldname(insn, 16, 8); \
7620
35
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7621
35
    return S; \
7622
35
  case 70: \
7623
17
    tmp = fieldname(insn, 8, 4); \
7624
17
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7625
17
    tmp = fieldname(insn, 16, 8); \
7626
17
    if (!Check(&S, decodeLoopOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7627
17
    return S; \
7628
398
  case 71: \
7629
398
    tmp = fieldname(insn, 8, 4); \
7630
398
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7631
398
    tmp = fieldname(insn, 12, 4); \
7632
398
    if (!Check(&S, decodeB4constuOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7633
398
    tmp = fieldname(insn, 16, 8); \
7634
398
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7635
398
    return S; \
7636
1.18k
  case 72: \
7637
1.18k
    tmp = fieldname(insn, 8, 4); \
7638
1.18k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7639
1.18k
    tmp = fieldname(insn, 4, 4); \
7640
1.18k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7641
1.18k
    tmp = fieldname(insn, 16, 8); \
7642
1.18k
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7643
1.18k
    return S; \
7644
1.18k
  case 73: \
7645
558
    tmp = fieldname(insn, 8, 4); \
7646
558
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7647
558
    tmp = 0x0; \
7648
558
    tmp |= fieldname(insn, 4, 4) << 0; \
7649
558
    tmp |= fieldname(insn, 12, 1) << 4; \
7650
558
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7651
558
    tmp = fieldname(insn, 16, 8); \
7652
558
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7653
558
    return S; \
7654
558
  case 74: \
7655
169
    tmp = fieldname(insn, 4, 4); \
7656
169
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7657
169
    tmp = fieldname(insn, 4, 4); \
7658
169
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7659
169
    tmp = 0x0; \
7660
169
    tmp |= fieldname(insn, 8, 7) << 0; \
7661
169
    tmp |= fieldname(insn, 22, 1) << 7; \
7662
169
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7663
169
    return S; \
7664
169
  case 75: \
7665
118
    tmp = fieldname(insn, 4, 4); \
7666
118
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7667
118
    tmp = fieldname(insn, 4, 4); \
7668
118
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7669
118
    tmp = fieldname(insn, 8, 4); \
7670
118
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7671
118
    return S; \
7672
295
  case 76: \
7673
295
    tmp = 0x0; \
7674
295
    tmp |= fieldname(insn, 15, 1) << 0; \
7675
295
    tmp |= fieldname(insn, 20, 2) << 1; \
7676
295
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7677
295
    tmp = fieldname(insn, 4, 4); \
7678
295
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7679
295
    tmp = fieldname(insn, 4, 4); \
7680
295
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7681
295
    tmp = 0x0; \
7682
295
    tmp |= fieldname(insn, 8, 7) << 0; \
7683
295
    tmp |= fieldname(insn, 22, 1) << 7; \
7684
295
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7685
295
    return S; \
7686
295
  case 77: \
7687
207
    tmp = fieldname(insn, 4, 4); \
7688
207
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7689
207
    tmp = fieldname(insn, 4, 4); \
7690
207
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7691
207
    tmp = 0x0; \
7692
207
    tmp |= fieldname(insn, 8, 7) << 0; \
7693
207
    tmp |= fieldname(insn, 22, 1) << 7; \
7694
207
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7695
207
    return S; \
7696
207
  case 78: \
7697
191
    tmp = fieldname(insn, 4, 4); \
7698
191
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7699
191
    tmp = fieldname(insn, 4, 4); \
7700
191
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7701
191
    tmp = 0x0; \
7702
191
    tmp |= fieldname(insn, 8, 7) << 0; \
7703
191
    tmp |= fieldname(insn, 22, 1) << 7; \
7704
191
    if (!Check(&S, decodeOffset_256_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7705
191
    return S; \
7706
300
  case 79: \
7707
300
    tmp = 0x0; \
7708
300
    tmp |= fieldname(insn, 15, 1) << 0; \
7709
300
    tmp |= fieldname(insn, 20, 2) << 1; \
7710
300
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7711
300
    tmp = fieldname(insn, 4, 4); \
7712
300
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7713
300
    tmp = fieldname(insn, 4, 4); \
7714
300
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7715
300
    tmp = 0x0; \
7716
300
    tmp |= fieldname(insn, 8, 7) << 0; \
7717
300
    tmp |= fieldname(insn, 22, 1) << 7; \
7718
300
    if (!Check(&S, decodeOffset_256_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7719
300
    return S; \
7720
300
  case 80: \
7721
207
    tmp = fieldname(insn, 12, 4); \
7722
207
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7723
207
    return S; \
7724
773
  case 81: \
7725
773
    tmp = fieldname(insn, 4, 4); \
7726
773
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7727
773
    tmp = 0x0; \
7728
773
    tmp |= fieldname(insn, 15, 1) << 0; \
7729
773
    tmp |= fieldname(insn, 20, 2) << 1; \
7730
773
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7731
773
    tmp = fieldname(insn, 4, 4); \
7732
773
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7733
773
    tmp = 0x0; \
7734
773
    tmp |= fieldname(insn, 8, 7) << 0; \
7735
773
    tmp |= fieldname(insn, 22, 1) << 7; \
7736
773
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7737
773
    return S; \
7738
773
  case 82: \
7739
261
    tmp = 0x0; \
7740
261
    tmp |= fieldname(insn, 15, 1) << 0; \
7741
261
    tmp |= fieldname(insn, 20, 2) << 1; \
7742
261
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7743
261
    tmp = fieldname(insn, 4, 4); \
7744
261
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7745
261
    tmp = fieldname(insn, 4, 4); \
7746
261
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7747
261
    tmp = fieldname(insn, 8, 7); \
7748
261
    if (!Check(&S, decodeOffset_128_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7749
261
    return S; \
7750
261
  case 83: \
7751
35
    tmp = 0x0; \
7752
35
    tmp |= fieldname(insn, 15, 1) << 0; \
7753
35
    tmp |= fieldname(insn, 20, 2) << 1; \
7754
35
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7755
35
    tmp = fieldname(insn, 4, 4); \
7756
35
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7757
35
    tmp = fieldname(insn, 4, 4); \
7758
35
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7759
35
    tmp = fieldname(insn, 8, 7); \
7760
35
    if (!Check(&S, decodeOffset_128_1Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7761
35
    return S; \
7762
295
  case 84: \
7763
295
    tmp = fieldname(insn, 12, 4); \
7764
295
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7765
295
    tmp = fieldname(insn, 20, 4); \
7766
295
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7767
295
    tmp = fieldname(insn, 4, 4); \
7768
295
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7769
295
    tmp = fieldname(insn, 4, 4); \
7770
295
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7771
295
    tmp = fieldname(insn, 8, 4); \
7772
295
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7773
295
    return S; \
7774
295
  case 85: \
7775
23
    tmp = 0x0; \
7776
23
    tmp |= fieldname(insn, 15, 1) << 0; \
7777
23
    tmp |= fieldname(insn, 20, 2) << 1; \
7778
23
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7779
23
    tmp = fieldname(insn, 12, 3); \
7780
23
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7781
23
    tmp = fieldname(insn, 4, 4); \
7782
23
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7783
23
    tmp = 0x0; \
7784
23
    tmp |= fieldname(insn, 15, 1) << 0; \
7785
23
    tmp |= fieldname(insn, 20, 2) << 1; \
7786
23
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7787
23
    tmp = fieldname(insn, 12, 3); \
7788
23
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7789
23
    tmp = fieldname(insn, 4, 4); \
7790
23
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7791
23
    tmp = fieldname(insn, 8, 4); \
7792
23
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7793
23
    return S; \
7794
507
  case 86: \
7795
507
    tmp = fieldname(insn, 4, 4); \
7796
507
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7797
507
    tmp = fieldname(insn, 12, 4); \
7798
507
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7799
507
    tmp = fieldname(insn, 20, 4); \
7800
507
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7801
507
    tmp = fieldname(insn, 4, 4); \
7802
507
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7803
507
    tmp = fieldname(insn, 8, 4); \
7804
507
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7805
507
    return S; \
7806
507
  case 87: \
7807
44
    tmp = 0x0; \
7808
44
    tmp |= fieldname(insn, 13, 1) << 0; \
7809
44
    tmp |= fieldname(insn, 15, 1) << 1; \
7810
44
    tmp |= fieldname(insn, 20, 1) << 2; \
7811
44
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7812
44
    tmp = fieldname(insn, 4, 4); \
7813
44
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7814
44
    tmp = fieldname(insn, 4, 4); \
7815
44
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7816
44
    tmp = fieldname(insn, 8, 3); \
7817
44
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7818
44
    tmp = 0x0; \
7819
44
    tmp |= fieldname(insn, 11, 2) << 0; \
7820
44
    tmp |= fieldname(insn, 14, 1) << 2; \
7821
44
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7822
44
    return S; \
7823
298
  case 88: \
7824
298
    tmp = 0x0; \
7825
298
    tmp |= fieldname(insn, 15, 1) << 0; \
7826
298
    tmp |= fieldname(insn, 20, 2) << 1; \
7827
298
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7828
298
    tmp = fieldname(insn, 4, 4); \
7829
298
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7830
298
    tmp = fieldname(insn, 4, 4); \
7831
298
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7832
298
    tmp = 0x0; \
7833
298
    tmp |= fieldname(insn, 8, 7) << 0; \
7834
298
    tmp |= fieldname(insn, 22, 1) << 7; \
7835
298
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7836
298
    return S; \
7837
298
  case 89: \
7838
7
    tmp = fieldname(insn, 8, 3); \
7839
7
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7840
7
    tmp = 0x0; \
7841
7
    tmp |= fieldname(insn, 11, 2) << 0; \
7842
7
    tmp |= fieldname(insn, 14, 1) << 2; \
7843
7
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7844
7
    return S; \
7845
98
  case 90: \
7846
98
    tmp = fieldname(insn, 4, 4); \
7847
98
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7848
98
    tmp = 0x0; \
7849
98
    tmp |= fieldname(insn, 15, 1) << 0; \
7850
98
    tmp |= fieldname(insn, 20, 2) << 1; \
7851
98
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7852
98
    tmp = fieldname(insn, 4, 4); \
7853
98
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7854
98
    tmp = 0x0; \
7855
98
    tmp |= fieldname(insn, 8, 7) << 0; \
7856
98
    tmp |= fieldname(insn, 22, 1) << 7; \
7857
98
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7858
98
    return S; \
7859
98
  case 91: \
7860
17
    tmp = 0x0; \
7861
17
    tmp |= fieldname(insn, 15, 1) << 0; \
7862
17
    tmp |= fieldname(insn, 20, 2) << 1; \
7863
17
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7864
17
    tmp = fieldname(insn, 8, 3); \
7865
17
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7866
17
    tmp = 0x0; \
7867
17
    tmp |= fieldname(insn, 11, 2) << 0; \
7868
17
    tmp |= fieldname(insn, 14, 1) << 2; \
7869
17
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7870
17
    tmp = fieldname(insn, 4, 4); \
7871
17
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7872
17
    return S; \
7873
163
  case 92: \
7874
163
    tmp = 0x0; \
7875
163
    tmp |= fieldname(insn, 15, 1) << 0; \
7876
163
    tmp |= fieldname(insn, 20, 2) << 1; \
7877
163
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7878
163
    tmp = fieldname(insn, 12, 3); \
7879
163
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7880
163
    tmp = 0x0; \
7881
163
    tmp |= fieldname(insn, 4, 1) << 0; \
7882
163
    tmp |= fieldname(insn, 6, 2) << 1; \
7883
163
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7884
163
    tmp = 0x0; \
7885
163
    tmp |= fieldname(insn, 5, 1) << 0; \
7886
163
    tmp |= fieldname(insn, 10, 2) << 1; \
7887
163
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7888
163
    tmp = fieldname(insn, 8, 1); \
7889
163
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7890
163
    return S; \
7891
163
  case 93: \
7892
10
    tmp = 0x0; \
7893
10
    tmp |= fieldname(insn, 15, 1) << 0; \
7894
10
    tmp |= fieldname(insn, 20, 2) << 1; \
7895
10
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7896
10
    tmp = fieldname(insn, 12, 3); \
7897
10
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7898
10
    tmp = fieldname(insn, 4, 4); \
7899
10
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7900
10
    tmp = fieldname(insn, 4, 4); \
7901
10
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7902
10
    return S; \
7903
34
  case 94: \
7904
34
    tmp = fieldname(insn, 4, 3); \
7905
34
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7906
34
    tmp = fieldname(insn, 12, 3); \
7907
34
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7908
34
    tmp = 0x0; \
7909
34
    tmp |= fieldname(insn, 15, 1) << 0; \
7910
34
    tmp |= fieldname(insn, 20, 2) << 1; \
7911
34
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7912
34
    return S; \
7913
34
  case 95: \
7914
8
    tmp = fieldname(insn, 12, 3); \
7915
8
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7916
8
    tmp = 0x0; \
7917
8
    tmp |= fieldname(insn, 15, 1) << 0; \
7918
8
    tmp |= fieldname(insn, 20, 2) << 1; \
7919
8
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7920
8
    tmp = fieldname(insn, 12, 3); \
7921
8
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7922
8
    tmp = 0x0; \
7923
8
    tmp |= fieldname(insn, 15, 1) << 0; \
7924
8
    tmp |= fieldname(insn, 20, 2) << 1; \
7925
8
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7926
8
    return S; \
7927
706
  case 96: \
7928
706
    tmp = 0x0; \
7929
706
    tmp |= fieldname(insn, 15, 1) << 0; \
7930
706
    tmp |= fieldname(insn, 20, 2) << 1; \
7931
706
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7932
706
    tmp = fieldname(insn, 12, 3); \
7933
706
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7934
706
    tmp = 0x0; \
7935
706
    tmp |= fieldname(insn, 15, 1) << 0; \
7936
706
    tmp |= fieldname(insn, 20, 2) << 1; \
7937
706
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7938
706
    tmp = fieldname(insn, 12, 3); \
7939
706
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7940
706
    tmp = fieldname(insn, 4, 4); \
7941
706
    if (!Check(&S, decodeSelect_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7942
706
    return S; \
7943
706
  case 97: \
7944
30
    tmp = fieldname(insn, 4, 3); \
7945
30
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7946
30
    tmp = fieldname(insn, 12, 3); \
7947
30
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7948
30
    tmp = fieldname(insn, 12, 3); \
7949
30
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7950
30
    tmp = 0x0; \
7951
30
    tmp |= fieldname(insn, 15, 1) << 0; \
7952
30
    tmp |= fieldname(insn, 20, 2) << 1; \
7953
30
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7954
30
    return S; \
7955
51
  case 98: \
7956
51
    tmp = fieldname(insn, 4, 4); \
7957
51
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7958
51
    tmp = fieldname(insn, 12, 3); \
7959
51
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7960
51
    tmp = 0x0; \
7961
51
    tmp |= fieldname(insn, 15, 1) << 0; \
7962
51
    tmp |= fieldname(insn, 20, 2) << 1; \
7963
51
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7964
51
    tmp = fieldname(insn, 4, 4); \
7965
51
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7966
51
    return S; \
7967
51
  case 99: \
7968
21
    tmp = 0x0; \
7969
21
    tmp |= fieldname(insn, 15, 1) << 0; \
7970
21
    tmp |= fieldname(insn, 20, 2) << 1; \
7971
21
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7972
21
    tmp = fieldname(insn, 4, 4); \
7973
21
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7974
21
    tmp = fieldname(insn, 4, 4); \
7975
21
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7976
21
    tmp = fieldname(insn, 8, 4); \
7977
21
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7978
21
    return S; \
7979
83
  case 100: \
7980
83
    tmp = fieldname(insn, 4, 4); \
7981
83
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7982
83
    tmp = 0x0; \
7983
83
    tmp |= fieldname(insn, 15, 1) << 0; \
7984
83
    tmp |= fieldname(insn, 20, 2) << 1; \
7985
83
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7986
83
    tmp = fieldname(insn, 4, 4); \
7987
83
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7988
83
    tmp = fieldname(insn, 8, 4); \
7989
83
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7990
83
    return S; \
7991
83
  case 101: \
7992
51
    tmp = 0x0; \
7993
51
    tmp |= fieldname(insn, 15, 1) << 0; \
7994
51
    tmp |= fieldname(insn, 20, 2) << 1; \
7995
51
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7996
51
    tmp = 0x0; \
7997
51
    tmp |= fieldname(insn, 15, 1) << 0; \
7998
51
    tmp |= fieldname(insn, 20, 2) << 1; \
7999
51
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8000
51
    tmp = fieldname(insn, 8, 4); \
8001
51
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8002
51
    tmp = fieldname(insn, 4, 4); \
8003
51
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8004
51
    return S; \
8005
51
  case 102: \
8006
45
    tmp = 0x0; \
8007
45
    tmp |= fieldname(insn, 15, 1) << 0; \
8008
45
    tmp |= fieldname(insn, 20, 2) << 1; \
8009
45
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8010
45
    tmp = 0x0; \
8011
45
    tmp |= fieldname(insn, 4, 1) << 0; \
8012
45
    tmp |= fieldname(insn, 6, 2) << 1; \
8013
45
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8014
45
    tmp = 0x0; \
8015
45
    tmp |= fieldname(insn, 5, 1) << 0; \
8016
45
    tmp |= fieldname(insn, 10, 2) << 1; \
8017
45
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8018
45
    return S; \
8019
45
  case 103: \
8020
6
    tmp = 0x0; \
8021
6
    tmp |= fieldname(insn, 15, 1) << 0; \
8022
6
    tmp |= fieldname(insn, 20, 2) << 1; \
8023
6
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8024
6
    tmp = fieldname(insn, 4, 4); \
8025
6
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8026
6
    tmp = fieldname(insn, 10, 2); \
8027
6
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8028
6
    return S; \
8029
20
  case 104: \
8030
20
    tmp = fieldname(insn, 4, 4); \
8031
20
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8032
20
    tmp = 0x0; \
8033
20
    tmp |= fieldname(insn, 15, 1) << 0; \
8034
20
    tmp |= fieldname(insn, 20, 2) << 1; \
8035
20
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8036
20
    tmp = fieldname(insn, 4, 4); \
8037
20
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8038
20
    tmp = fieldname(insn, 10, 1); \
8039
20
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8040
20
    return S; \
8041
162
  case 105: \
8042
162
    tmp = 0x0; \
8043
162
    tmp |= fieldname(insn, 15, 1) << 0; \
8044
162
    tmp |= fieldname(insn, 20, 2) << 1; \
8045
162
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8046
162
    tmp = fieldname(insn, 4, 4); \
8047
162
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8048
162
    return S; \
8049
162
  case 106: \
8050
126
    tmp = fieldname(insn, 4, 3); \
8051
126
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8052
126
    tmp = 0x0; \
8053
126
    tmp |= fieldname(insn, 15, 1) << 0; \
8054
126
    tmp |= fieldname(insn, 20, 2) << 1; \
8055
126
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8056
126
    return S; \
8057
126
  case 107: \
8058
59
    tmp = fieldname(insn, 4, 4); \
8059
59
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8060
59
    tmp = 0x0; \
8061
59
    tmp |= fieldname(insn, 15, 1) << 0; \
8062
59
    tmp |= fieldname(insn, 20, 2) << 1; \
8063
59
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8064
59
    tmp = fieldname(insn, 10, 2); \
8065
59
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8066
59
    return S; \
8067
59
  case 108: \
8068
52
    tmp = 0x0; \
8069
52
    tmp |= fieldname(insn, 15, 1) << 0; \
8070
52
    tmp |= fieldname(insn, 20, 2) << 1; \
8071
52
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8072
52
    tmp = fieldname(insn, 4, 4); \
8073
52
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8074
52
    tmp = fieldname(insn, 10, 1); \
8075
52
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8076
52
    return S; \
8077
52
  case 109: \
8078
23
    tmp = 0x0; \
8079
23
    tmp |= fieldname(insn, 15, 1) << 0; \
8080
23
    tmp |= fieldname(insn, 20, 2) << 1; \
8081
23
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8082
23
    tmp = fieldname(insn, 4, 4); \
8083
23
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8084
23
    tmp = fieldname(insn, 4, 4); \
8085
23
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8086
23
    return S; \
8087
42
  case 110: \
8088
42
    tmp = 0x0; \
8089
42
    tmp |= fieldname(insn, 15, 1) << 0; \
8090
42
    tmp |= fieldname(insn, 20, 2) << 1; \
8091
42
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8092
42
    tmp = 0x0; \
8093
42
    tmp |= fieldname(insn, 4, 1) << 0; \
8094
42
    tmp |= fieldname(insn, 6, 2) << 1; \
8095
42
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8096
42
    return S; \
8097
42
  case 111: \
8098
8
    tmp = 0x0; \
8099
8
    tmp |= fieldname(insn, 15, 1) << 0; \
8100
8
    tmp |= fieldname(insn, 20, 2) << 1; \
8101
8
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8102
8
    return S; \
8103
48
  case 112: \
8104
48
    tmp = fieldname(insn, 8, 4); \
8105
48
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8106
48
    tmp = fieldname(insn, 4, 4); \
8107
48
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8108
48
    tmp = fieldname(insn, 14, 1); \
8109
48
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8110
48
    return S; \
8111
49
  case 113: \
8112
49
    tmp = 0x0; \
8113
49
    tmp |= fieldname(insn, 15, 1) << 0; \
8114
49
    tmp |= fieldname(insn, 20, 2) << 1; \
8115
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8116
49
    tmp = fieldname(insn, 8, 3); \
8117
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8118
49
    tmp = 0x0; \
8119
49
    tmp |= fieldname(insn, 11, 2) << 0; \
8120
49
    tmp |= fieldname(insn, 14, 1) << 2; \
8121
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8122
49
    tmp = fieldname(insn, 4, 2); \
8123
49
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8124
49
    return S; \
8125
207
  case 114: \
8126
207
    tmp = 0x0; \
8127
207
    tmp |= fieldname(insn, 15, 1) << 0; \
8128
207
    tmp |= fieldname(insn, 20, 2) << 1; \
8129
207
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8130
207
    tmp = fieldname(insn, 8, 3); \
8131
207
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8132
207
    tmp = 0x0; \
8133
207
    tmp |= fieldname(insn, 11, 2) << 0; \
8134
207
    tmp |= fieldname(insn, 14, 1) << 2; \
8135
207
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8136
207
    return S; \
8137
207
  case 115: \
8138
48
    tmp = fieldname(insn, 8, 3); \
8139
48
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8140
48
    tmp = 0x0; \
8141
48
    tmp |= fieldname(insn, 11, 2) << 0; \
8142
48
    tmp |= fieldname(insn, 14, 1) << 2; \
8143
48
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8144
48
    tmp = 0x0; \
8145
48
    tmp |= fieldname(insn, 4, 1) << 0; \
8146
48
    tmp |= fieldname(insn, 15, 1) << 1; \
8147
48
    tmp |= fieldname(insn, 20, 2) << 2; \
8148
48
    if (!Check(&S, decodeSelect_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8149
48
    return S; \
8150
73
  case 116: \
8151
73
    tmp = fieldname(insn, 8, 3); \
8152
73
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8153
73
    tmp = 0x0; \
8154
73
    tmp |= fieldname(insn, 11, 2) << 0; \
8155
73
    tmp |= fieldname(insn, 14, 1) << 2; \
8156
73
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8157
73
    tmp = 0x0; \
8158
73
    tmp |= fieldname(insn, 15, 1) << 0; \
8159
73
    tmp |= fieldname(insn, 20, 2) << 1; \
8160
73
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8161
73
    return S; \
8162
73
  case 117: \
8163
21
    tmp = 0x0; \
8164
21
    tmp |= fieldname(insn, 15, 1) << 0; \
8165
21
    tmp |= fieldname(insn, 20, 2) << 1; \
8166
21
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8167
21
    tmp = 0x0; \
8168
21
    tmp |= fieldname(insn, 5, 1) << 0; \
8169
21
    tmp |= fieldname(insn, 10, 2) << 1; \
8170
21
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8171
21
    return S; \
8172
1.74k
  case 118: \
8173
1.74k
    tmp = 0x0; \
8174
1.74k
    tmp |= fieldname(insn, 19, 1) << 0; \
8175
1.74k
    tmp |= fieldname(insn, 24, 2) << 1; \
8176
1.74k
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8177
1.74k
    tmp = fieldname(insn, 4, 4); \
8178
1.74k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8179
1.74k
    tmp = fieldname(insn, 20, 3); \
8180
1.74k
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8181
1.74k
    tmp = fieldname(insn, 4, 4); \
8182
1.74k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8183
1.74k
    tmp = 0x0; \
8184
1.74k
    tmp |= fieldname(insn, 8, 4) << 0; \
8185
1.74k
    tmp |= fieldname(insn, 26, 2) << 4; \
8186
1.74k
    if (!Check(&S, decodeOffset_64_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8187
1.74k
    tmp = 0x0; \
8188
1.74k
    tmp |= fieldname(insn, 0, 1) << 2; \
8189
1.74k
    tmp |= fieldname(insn, 14, 2) << 0; \
8190
1.74k
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8191
1.74k
    tmp = 0x0; \
8192
1.74k
    tmp |= fieldname(insn, 12, 2) << 1; \
8193
1.74k
    tmp |= fieldname(insn, 23, 1) << 0; \
8194
1.74k
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8195
1.74k
    tmp = fieldname(insn, 20, 3); \
8196
1.74k
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8197
1.74k
    tmp = fieldname(insn, 16, 3); \
8198
1.74k
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8199
1.74k
    return S; \
8200
1.74k
  case 119: \
8201
241
    tmp = 0x0; \
8202
241
    tmp |= fieldname(insn, 19, 1) << 0; \
8203
241
    tmp |= fieldname(insn, 24, 3) << 1; \
8204
241
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8205
241
    tmp = 0x0; \
8206
241
    tmp |= fieldname(insn, 0, 1) << 0; \
8207
241
    tmp |= fieldname(insn, 16, 3) << 1; \
8208
241
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8209
241
    tmp = fieldname(insn, 12, 4); \
8210
241
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8211
241
    tmp = fieldname(insn, 20, 4); \
8212
241
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8213
241
    tmp = fieldname(insn, 4, 4); \
8214
241
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8215
241
    tmp = fieldname(insn, 4, 4); \
8216
241
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8217
241
    tmp = fieldname(insn, 8, 4); \
8218
241
    if (!Check(&S, decodeOffset_16_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8219
241
    return S; \
8220
241
  case 120: \
8221
196
    tmp = 0x0; \
8222
196
    tmp |= fieldname(insn, 19, 1) << 0; \
8223
196
    tmp |= fieldname(insn, 24, 3) << 1; \
8224
196
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8225
196
    tmp = 0x0; \
8226
196
    tmp |= fieldname(insn, 0, 1) << 0; \
8227
196
    tmp |= fieldname(insn, 16, 3) << 1; \
8228
196
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8229
196
    tmp = fieldname(insn, 12, 4); \
8230
196
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8231
196
    tmp = fieldname(insn, 20, 4); \
8232
196
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8233
196
    tmp = fieldname(insn, 4, 4); \
8234
196
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8235
196
    tmp = fieldname(insn, 4, 4); \
8236
196
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8237
196
    tmp = fieldname(insn, 8, 4); \
8238
196
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8239
196
    return S; \
8240
196
  case 121: \
8241
165
    tmp = fieldname(insn, 4, 4); \
8242
165
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8243
165
    tmp = 0x0; \
8244
165
    tmp |= fieldname(insn, 19, 1) << 0; \
8245
165
    tmp |= fieldname(insn, 24, 3) << 1; \
8246
165
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8247
165
    tmp = 0x0; \
8248
165
    tmp |= fieldname(insn, 0, 1) << 0; \
8249
165
    tmp |= fieldname(insn, 16, 3) << 1; \
8250
165
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8251
165
    tmp = fieldname(insn, 12, 4); \
8252
165
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8253
165
    tmp = fieldname(insn, 20, 4); \
8254
165
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8255
165
    tmp = fieldname(insn, 4, 4); \
8256
165
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8257
165
    tmp = fieldname(insn, 8, 4); \
8258
165
    if (!Check(&S, decodeOffset_16_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8259
165
    return S; \
8260
385
  case 122: \
8261
385
    tmp = fieldname(insn, 4, 4); \
8262
385
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8263
385
    tmp = 0x0; \
8264
385
    tmp |= fieldname(insn, 19, 1) << 0; \
8265
385
    tmp |= fieldname(insn, 24, 3) << 1; \
8266
385
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8267
385
    tmp = 0x0; \
8268
385
    tmp |= fieldname(insn, 0, 1) << 0; \
8269
385
    tmp |= fieldname(insn, 16, 3) << 1; \
8270
385
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8271
385
    tmp = fieldname(insn, 12, 4); \
8272
385
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8273
385
    tmp = fieldname(insn, 20, 4); \
8274
385
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8275
385
    tmp = fieldname(insn, 4, 4); \
8276
385
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8277
385
    tmp = fieldname(insn, 8, 4); \
8278
385
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8279
385
    return S; \
8280
385
  case 123: \
8281
270
    tmp = 0x0; \
8282
270
    tmp |= fieldname(insn, 19, 1) << 0; \
8283
270
    tmp |= fieldname(insn, 24, 2) << 1; \
8284
270
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8285
270
    tmp = fieldname(insn, 4, 4); \
8286
270
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8287
270
    tmp = fieldname(insn, 8, 4); \
8288
270
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8289
270
    tmp = fieldname(insn, 20, 3); \
8290
270
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8291
270
    tmp = fieldname(insn, 4, 4); \
8292
270
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8293
270
    tmp = fieldname(insn, 8, 4); \
8294
270
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8295
270
    tmp = fieldname(insn, 16, 3); \
8296
270
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8297
270
    tmp = 0x0; \
8298
270
    tmp |= fieldname(insn, 0, 1) << 2; \
8299
270
    tmp |= fieldname(insn, 14, 2) << 0; \
8300
270
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8301
270
    tmp = 0x0; \
8302
270
    tmp |= fieldname(insn, 12, 2) << 1; \
8303
270
    tmp |= fieldname(insn, 23, 1) << 0; \
8304
270
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8305
270
    tmp = fieldname(insn, 26, 1); \
8306
270
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8307
270
    return S; \
8308
775
  case 124: \
8309
775
    tmp = fieldname(insn, 4, 4); \
8310
775
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8311
775
    tmp = 0x0; \
8312
775
    tmp |= fieldname(insn, 0, 1) << 2; \
8313
775
    tmp |= fieldname(insn, 14, 2) << 0; \
8314
775
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8315
775
    tmp = fieldname(insn, 20, 3); \
8316
775
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8317
775
    tmp = fieldname(insn, 16, 3); \
8318
775
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8319
775
    tmp = fieldname(insn, 4, 4); \
8320
775
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8321
775
    tmp = fieldname(insn, 8, 4); \
8322
775
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8323
775
    tmp = 0x0; \
8324
775
    tmp |= fieldname(insn, 12, 2) << 1; \
8325
775
    tmp |= fieldname(insn, 23, 1) << 0; \
8326
775
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8327
775
    tmp = 0x0; \
8328
775
    tmp |= fieldname(insn, 19, 1) << 0; \
8329
775
    tmp |= fieldname(insn, 24, 1) << 1; \
8330
775
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8331
775
    tmp = fieldname(insn, 25, 2); \
8332
775
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8333
775
    return S; \
8334
775
  case 125: \
8335
729
    tmp = 0x0; \
8336
729
    tmp |= fieldname(insn, 19, 1) << 0; \
8337
729
    tmp |= fieldname(insn, 24, 2) << 1; \
8338
729
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8339
729
    tmp = fieldname(insn, 4, 4); \
8340
729
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8341
729
    tmp = fieldname(insn, 20, 3); \
8342
729
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8343
729
    tmp = fieldname(insn, 4, 4); \
8344
729
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8345
729
    tmp = fieldname(insn, 8, 4); \
8346
729
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8347
729
    tmp = 0x0; \
8348
729
    tmp |= fieldname(insn, 0, 1) << 2; \
8349
729
    tmp |= fieldname(insn, 14, 2) << 0; \
8350
729
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8351
729
    tmp = 0x0; \
8352
729
    tmp |= fieldname(insn, 12, 2) << 1; \
8353
729
    tmp |= fieldname(insn, 23, 1) << 0; \
8354
729
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8355
729
    tmp = fieldname(insn, 20, 3); \
8356
729
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8357
729
    tmp = fieldname(insn, 16, 3); \
8358
729
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8359
729
    return S; \
8360
729
  case 126: \
8361
147
    tmp = fieldname(insn, 8, 3); \
8362
147
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8363
147
    tmp = fieldname(insn, 4, 4); \
8364
147
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8365
147
    tmp = 0x0; \
8366
147
    tmp |= fieldname(insn, 12, 2) << 1; \
8367
147
    tmp |= fieldname(insn, 23, 1) << 0; \
8368
147
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8369
147
    tmp = 0x0; \
8370
147
    tmp |= fieldname(insn, 11, 1) << 0; \
8371
147
    tmp |= fieldname(insn, 19, 1) << 1; \
8372
147
    tmp |= fieldname(insn, 24, 1) << 2; \
8373
147
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8374
147
    tmp = fieldname(insn, 4, 4); \
8375
147
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8376
147
    tmp = 0x0; \
8377
147
    tmp |= fieldname(insn, 0, 1) << 2; \
8378
147
    tmp |= fieldname(insn, 14, 2) << 0; \
8379
147
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8380
147
    tmp = fieldname(insn, 20, 3); \
8381
147
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8382
147
    tmp = fieldname(insn, 16, 3); \
8383
147
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8384
147
    tmp = fieldname(insn, 25, 1); \
8385
147
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8386
147
    return S; \
8387
440
  case 127: \
8388
440
    tmp = 0x0; \
8389
440
    tmp |= fieldname(insn, 12, 2) << 1; \
8390
440
    tmp |= fieldname(insn, 23, 1) << 0; \
8391
440
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8392
440
    tmp = fieldname(insn, 4, 4); \
8393
440
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8394
440
    tmp = fieldname(insn, 16, 3); \
8395
440
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8396
440
    tmp = fieldname(insn, 4, 4); \
8397
440
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8398
440
    tmp = fieldname(insn, 8, 4); \
8399
440
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8400
440
    tmp = 0x0; \
8401
440
    tmp |= fieldname(insn, 0, 1) << 2; \
8402
440
    tmp |= fieldname(insn, 14, 2) << 0; \
8403
440
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8404
440
    tmp = fieldname(insn, 20, 3); \
8405
440
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8406
440
    tmp = 0x0; \
8407
440
    tmp |= fieldname(insn, 19, 1) << 0; \
8408
440
    tmp |= fieldname(insn, 24, 2) << 1; \
8409
440
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8410
440
    return S; \
8411
440
  case 128: \
8412
85
    tmp = fieldname(insn, 16, 3); \
8413
85
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8414
85
    tmp = fieldname(insn, 4, 4); \
8415
85
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8416
85
    tmp = 0x0; \
8417
85
    tmp |= fieldname(insn, 0, 1) << 2; \
8418
85
    tmp |= fieldname(insn, 14, 2) << 0; \
8419
85
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8420
85
    tmp = fieldname(insn, 4, 4); \
8421
85
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8422
85
    tmp = 0x0; \
8423
85
    tmp |= fieldname(insn, 8, 2) << 0; \
8424
85
    tmp |= fieldname(insn, 12, 2) << 3; \
8425
85
    tmp |= fieldname(insn, 19, 1) << 5; \
8426
85
    tmp |= fieldname(insn, 23, 1) << 2; \
8427
85
    tmp |= fieldname(insn, 24, 2) << 6; \
8428
85
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8429
85
    tmp = 0x0; \
8430
85
    tmp |= fieldname(insn, 0, 1) << 2; \
8431
85
    tmp |= fieldname(insn, 14, 2) << 0; \
8432
85
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8433
85
    tmp = fieldname(insn, 20, 3); \
8434
85
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8435
85
    return S; \
8436
85
  case 129: \
8437
23
    tmp = fieldname(insn, 12, 4); \
8438
23
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8439
23
    tmp = fieldname(insn, 20, 4); \
8440
23
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8441
23
    tmp = fieldname(insn, 4, 4); \
8442
23
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8443
23
    tmp = fieldname(insn, 4, 4); \
8444
23
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8445
23
    tmp = 0x0; \
8446
23
    tmp |= fieldname(insn, 0, 1) << 1; \
8447
23
    tmp |= fieldname(insn, 8, 1) << 0; \
8448
23
    tmp |= fieldname(insn, 16, 4) << 2; \
8449
23
    tmp |= fieldname(insn, 24, 2) << 6; \
8450
23
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8451
23
    return S; \
8452
182
  case 130: \
8453
182
    tmp = fieldname(insn, 4, 4); \
8454
182
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8455
182
    tmp = fieldname(insn, 12, 4); \
8456
182
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8457
182
    tmp = fieldname(insn, 20, 4); \
8458
182
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8459
182
    tmp = fieldname(insn, 4, 4); \
8460
182
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8461
182
    tmp = 0x0; \
8462
182
    tmp |= fieldname(insn, 0, 1) << 1; \
8463
182
    tmp |= fieldname(insn, 8, 1) << 0; \
8464
182
    tmp |= fieldname(insn, 16, 4) << 2; \
8465
182
    tmp |= fieldname(insn, 24, 2) << 6; \
8466
182
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8467
182
    return S; \
8468
182
  case 131: \
8469
41
    tmp = 0x0; \
8470
41
    tmp |= fieldname(insn, 19, 1) << 0; \
8471
41
    tmp |= fieldname(insn, 24, 2) << 1; \
8472
41
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8473
41
    tmp = fieldname(insn, 4, 4); \
8474
41
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8475
41
    tmp = fieldname(insn, 20, 3); \
8476
41
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8477
41
    tmp = fieldname(insn, 4, 4); \
8478
41
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8479
41
    tmp = 0x0; \
8480
41
    tmp |= fieldname(insn, 0, 1) << 2; \
8481
41
    tmp |= fieldname(insn, 14, 2) << 0; \
8482
41
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8483
41
    tmp = 0x0; \
8484
41
    tmp |= fieldname(insn, 12, 2) << 1; \
8485
41
    tmp |= fieldname(insn, 23, 1) << 0; \
8486
41
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8487
41
    tmp = fieldname(insn, 20, 3); \
8488
41
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8489
41
    tmp = fieldname(insn, 16, 3); \
8490
41
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8491
41
    return S; \
8492
41
  case 132: \
8493
9
    tmp = 0x0; \
8494
9
    tmp |= fieldname(insn, 19, 1) << 0; \
8495
9
    tmp |= fieldname(insn, 24, 2) << 1; \
8496
9
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8497
9
    tmp = fieldname(insn, 4, 4); \
8498
9
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8499
9
    tmp = fieldname(insn, 16, 3); \
8500
9
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8501
9
    tmp = fieldname(insn, 4, 4); \
8502
9
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8503
9
    tmp = 0x0; \
8504
9
    tmp |= fieldname(insn, 0, 1) << 2; \
8505
9
    tmp |= fieldname(insn, 14, 2) << 0; \
8506
9
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8507
9
    tmp = 0x0; \
8508
9
    tmp |= fieldname(insn, 12, 2) << 1; \
8509
9
    tmp |= fieldname(insn, 23, 1) << 0; \
8510
9
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8511
9
    tmp = fieldname(insn, 8, 2); \
8512
9
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8513
9
    return S; \
8514
49
  case 133: \
8515
49
    tmp = 0x0; \
8516
49
    tmp |= fieldname(insn, 19, 1) << 0; \
8517
49
    tmp |= fieldname(insn, 24, 2) << 1; \
8518
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8519
49
    tmp = fieldname(insn, 4, 4); \
8520
49
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8521
49
    tmp = fieldname(insn, 16, 3); \
8522
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8523
49
    tmp = fieldname(insn, 4, 4); \
8524
49
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8525
49
    tmp = 0x0; \
8526
49
    tmp |= fieldname(insn, 0, 1) << 2; \
8527
49
    tmp |= fieldname(insn, 14, 2) << 0; \
8528
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8529
49
    tmp = 0x0; \
8530
49
    tmp |= fieldname(insn, 12, 2) << 1; \
8531
49
    tmp |= fieldname(insn, 23, 1) << 0; \
8532
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8533
49
    return S; \
8534
49
  case 134: \
8535
18
    tmp = 0x0; \
8536
18
    tmp |= fieldname(insn, 19, 1) << 0; \
8537
18
    tmp |= fieldname(insn, 24, 2) << 1; \
8538
18
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8539
18
    tmp = fieldname(insn, 4, 4); \
8540
18
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8541
18
    tmp = fieldname(insn, 4, 4); \
8542
18
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8543
18
    tmp = 0x0; \
8544
18
    tmp |= fieldname(insn, 0, 1) << 2; \
8545
18
    tmp |= fieldname(insn, 14, 2) << 0; \
8546
18
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8547
18
    tmp = 0x0; \
8548
18
    tmp |= fieldname(insn, 12, 2) << 1; \
8549
18
    tmp |= fieldname(insn, 23, 1) << 0; \
8550
18
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8551
18
    tmp = 0x0; \
8552
18
    tmp |= fieldname(insn, 16, 3) << 1; \
8553
18
    tmp |= fieldname(insn, 20, 1) << 0; \
8554
18
    if (!Check(&S, decodeSelect_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8555
18
    return S; \
8556
60
  case 135: \
8557
60
    tmp = 0x0; \
8558
60
    tmp |= fieldname(insn, 19, 1) << 0; \
8559
60
    tmp |= fieldname(insn, 24, 2) << 1; \
8560
60
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8561
60
    tmp = fieldname(insn, 4, 4); \
8562
60
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8563
60
    tmp = fieldname(insn, 4, 4); \
8564
60
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8565
60
    tmp = 0x0; \
8566
60
    tmp |= fieldname(insn, 0, 1) << 2; \
8567
60
    tmp |= fieldname(insn, 14, 2) << 0; \
8568
60
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8569
60
    tmp = 0x0; \
8570
60
    tmp |= fieldname(insn, 12, 2) << 1; \
8571
60
    tmp |= fieldname(insn, 23, 1) << 0; \
8572
60
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8573
60
    tmp = fieldname(insn, 16, 3); \
8574
60
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8575
60
    return S; \
8576
60
  case 136: \
8577
49
    tmp = fieldname(insn, 16, 3); \
8578
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8579
49
    tmp = 0x0; \
8580
49
    tmp |= fieldname(insn, 0, 1) << 2; \
8581
49
    tmp |= fieldname(insn, 14, 2) << 0; \
8582
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8583
49
    tmp = fieldname(insn, 4, 4); \
8584
49
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8585
49
    tmp = 0x0; \
8586
49
    tmp |= fieldname(insn, 19, 1) << 0; \
8587
49
    tmp |= fieldname(insn, 24, 1) << 1; \
8588
49
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8589
49
    tmp = 0x0; \
8590
49
    tmp |= fieldname(insn, 12, 2) << 1; \
8591
49
    tmp |= fieldname(insn, 23, 1) << 0; \
8592
49
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8593
49
    return S; \
8594
49
  case 137: \
8595
15
    tmp = fieldname(insn, 4, 4); \
8596
15
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8597
15
    tmp = fieldname(insn, 16, 3); \
8598
15
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8599
15
    tmp = fieldname(insn, 20, 3); \
8600
15
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8601
15
    tmp = fieldname(insn, 4, 4); \
8602
15
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8603
15
    tmp = 0x0; \
8604
15
    tmp |= fieldname(insn, 0, 1) << 2; \
8605
15
    tmp |= fieldname(insn, 14, 2) << 0; \
8606
15
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8607
15
    tmp = 0x0; \
8608
15
    tmp |= fieldname(insn, 12, 2) << 1; \
8609
15
    tmp |= fieldname(insn, 23, 1) << 0; \
8610
15
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8611
15
    tmp = fieldname(insn, 8, 2); \
8612
15
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8613
15
    return S; \
8614
167
  case 138: \
8615
167
    tmp = fieldname(insn, 4, 4); \
8616
167
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8617
167
    tmp = fieldname(insn, 16, 3); \
8618
167
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8619
167
    tmp = fieldname(insn, 20, 3); \
8620
167
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8621
167
    tmp = fieldname(insn, 4, 4); \
8622
167
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8623
167
    tmp = 0x0; \
8624
167
    tmp |= fieldname(insn, 0, 1) << 2; \
8625
167
    tmp |= fieldname(insn, 14, 2) << 0; \
8626
167
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8627
167
    tmp = 0x0; \
8628
167
    tmp |= fieldname(insn, 12, 2) << 1; \
8629
167
    tmp |= fieldname(insn, 23, 1) << 0; \
8630
167
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8631
167
    return S; \
8632
167
  case 139: \
8633
50
    tmp = fieldname(insn, 20, 3); \
8634
50
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8635
50
    tmp = 0x0; \
8636
50
    tmp |= fieldname(insn, 0, 1) << 2; \
8637
50
    tmp |= fieldname(insn, 14, 2) << 0; \
8638
50
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8639
50
    tmp = fieldname(insn, 4, 4); \
8640
50
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8641
50
    tmp = 0x0; \
8642
50
    tmp |= fieldname(insn, 19, 1) << 0; \
8643
50
    tmp |= fieldname(insn, 24, 1) << 1; \
8644
50
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8645
50
    tmp = 0x0; \
8646
50
    tmp |= fieldname(insn, 12, 2) << 1; \
8647
50
    tmp |= fieldname(insn, 23, 1) << 0; \
8648
50
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8649
50
    return S; \
8650
50
  case 140: \
8651
7
    tmp = fieldname(insn, 16, 3); \
8652
7
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8653
7
    tmp = fieldname(insn, 4, 4); \
8654
7
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8655
7
    tmp = 0x0; \
8656
7
    tmp |= fieldname(insn, 0, 1) << 2; \
8657
7
    tmp |= fieldname(insn, 14, 2) << 0; \
8658
7
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8659
7
    tmp = fieldname(insn, 4, 4); \
8660
7
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8661
7
    tmp = fieldname(insn, 8, 4); \
8662
7
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8663
7
    tmp = 0x0; \
8664
7
    tmp |= fieldname(insn, 0, 1) << 2; \
8665
7
    tmp |= fieldname(insn, 14, 2) << 0; \
8666
7
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8667
7
    tmp = fieldname(insn, 20, 3); \
8668
7
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8669
7
    return S; \
8670
15
  case 141: \
8671
15
    tmp = fieldname(insn, 16, 3); \
8672
15
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8673
15
    tmp = fieldname(insn, 4, 4); \
8674
15
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8675
15
    tmp = 0x0; \
8676
15
    tmp |= fieldname(insn, 0, 1) << 2; \
8677
15
    tmp |= fieldname(insn, 14, 2) << 0; \
8678
15
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8679
15
    tmp = fieldname(insn, 20, 3); \
8680
15
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8681
15
    tmp = fieldname(insn, 4, 4); \
8682
15
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8683
15
    tmp = 0x0; \
8684
15
    tmp |= fieldname(insn, 12, 1) << 1; \
8685
15
    tmp |= fieldname(insn, 23, 1) << 0; \
8686
15
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8687
15
    return S; \
8688
251
  case 142: \
8689
251
    tmp = 0x0; \
8690
251
    tmp |= fieldname(insn, 19, 1) << 0; \
8691
251
    tmp |= fieldname(insn, 24, 2) << 1; \
8692
251
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8693
251
    tmp = fieldname(insn, 4, 4); \
8694
251
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8695
251
    tmp = fieldname(insn, 4, 4); \
8696
251
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8697
251
    tmp = 0x0; \
8698
251
    tmp |= fieldname(insn, 8, 4) << 0; \
8699
251
    tmp |= fieldname(insn, 26, 2) << 4; \
8700
251
    if (!Check(&S, decodeOffset_64_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8701
251
    tmp = 0x0; \
8702
251
    tmp |= fieldname(insn, 0, 1) << 2; \
8703
251
    tmp |= fieldname(insn, 14, 2) << 0; \
8704
251
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8705
251
    tmp = 0x0; \
8706
251
    tmp |= fieldname(insn, 12, 2) << 1; \
8707
251
    tmp |= fieldname(insn, 23, 1) << 0; \
8708
251
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8709
251
    return S; \
8710
251
  case 143: \
8711
197
    tmp = 0x0; \
8712
197
    tmp |= fieldname(insn, 19, 1) << 0; \
8713
197
    tmp |= fieldname(insn, 24, 2) << 1; \
8714
197
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8715
197
    tmp = fieldname(insn, 4, 4); \
8716
197
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8717
197
    tmp = fieldname(insn, 4, 4); \
8718
197
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8719
197
    tmp = fieldname(insn, 8, 4); \
8720
197
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8721
197
    tmp = 0x0; \
8722
197
    tmp |= fieldname(insn, 0, 1) << 2; \
8723
197
    tmp |= fieldname(insn, 14, 2) << 0; \
8724
197
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8725
197
    tmp = 0x0; \
8726
197
    tmp |= fieldname(insn, 12, 2) << 1; \
8727
197
    tmp |= fieldname(insn, 23, 1) << 0; \
8728
197
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8729
197
    return S; \
8730
197
  case 144: \
8731
0
    tmp = fieldname(insn, 12, 4); \
8732
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8733
0
    tmp = fieldname(insn, 4, 4); \
8734
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8735
0
    tmp = fieldname(insn, 8, 4); \
8736
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8737
0
    return S; \
8738
0
  case 145: \
8739
0
    tmp = fieldname(insn, 8, 4); \
8740
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8741
0
    tmp = fieldname(insn, 4, 4); \
8742
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8743
0
    tmp = fieldname(insn, 12, 4); \
8744
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8745
0
    tmp = fieldname(insn, 8, 4); \
8746
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8747
0
    return S; \
8748
0
  case 146: \
8749
0
    tmp = fieldname(insn, 12, 4); \
8750
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8751
0
    tmp = fieldname(insn, 8, 4); \
8752
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8753
0
    tmp = fieldname(insn, 4, 4); \
8754
0
    MCOperand_CreateImm0(MI, tmp); \
8755
0
    return S; \
8756
0
  case 147: \
8757
0
    tmp = fieldname(insn, 8, 4); \
8758
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8759
0
    tmp = fieldname(insn, 12, 4); \
8760
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8761
0
    tmp = fieldname(insn, 8, 4); \
8762
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8763
0
    tmp = fieldname(insn, 4, 4); \
8764
0
    MCOperand_CreateImm0(MI, tmp); \
8765
0
    return S; \
8766
0
  case 148: \
8767
0
    tmp = fieldname(insn, 8, 4); \
8768
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8769
0
    tmp = fieldname(insn, 12, 4); \
8770
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8771
0
    tmp = fieldname(insn, 8, 4); \
8772
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8773
0
    tmp = fieldname(insn, 4, 4); \
8774
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8775
0
    return S; \
8776
0
  case 149: \
8777
0
    tmp = fieldname(insn, 12, 4); \
8778
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8779
0
    tmp = fieldname(insn, 4, 4); \
8780
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8781
0
    tmp = fieldname(insn, 8, 4); \
8782
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8783
0
    return S; \
8784
0
  case 150: \
8785
0
    tmp = fieldname(insn, 12, 4); \
8786
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8787
0
    tmp = fieldname(insn, 4, 2); \
8788
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8789
0
    tmp = fieldname(insn, 8, 4); \
8790
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8791
0
    tmp = fieldname(insn, 4, 2); \
8792
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8793
0
    tmp = fieldname(insn, 8, 4); \
8794
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8795
0
    return S; \
8796
0
  case 151: \
8797
0
    tmp = fieldname(insn, 4, 2); \
8798
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8799
0
    tmp = fieldname(insn, 8, 4); \
8800
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8801
0
    tmp = fieldname(insn, 12, 4); \
8802
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8803
0
    tmp = fieldname(insn, 4, 2); \
8804
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8805
0
    tmp = fieldname(insn, 8, 4); \
8806
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8807
0
    return S; \
8808
0
  case 152: \
8809
0
    tmp = fieldname(insn, 12, 4); \
8810
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8811
0
    tmp = fieldname(insn, 4, 4); \
8812
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8813
0
    tmp = fieldname(insn, 8, 4); \
8814
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8815
0
    return S; \
8816
0
  case 153: \
8817
0
    tmp = fieldname(insn, 12, 4); \
8818
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8819
0
    tmp = fieldname(insn, 8, 4); \
8820
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8821
0
    tmp = fieldname(insn, 4, 4); \
8822
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8823
0
    return S; \
8824
0
  case 154: \
8825
0
    tmp = fieldname(insn, 12, 4); \
8826
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8827
0
    tmp = fieldname(insn, 8, 4); \
8828
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8829
0
    tmp = fieldname(insn, 4, 4); \
8830
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8831
0
    return S; \
8832
0
  case 155: \
8833
0
    tmp = fieldname(insn, 12, 4); \
8834
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8835
0
    tmp = fieldname(insn, 8, 4); \
8836
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8837
0
    tmp = fieldname(insn, 4, 4); \
8838
0
    if (!Check(&S, decodeImm7_22Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8839
0
    return S; \
8840
0
  case 156: \
8841
0
    tmp = fieldname(insn, 12, 4); \
8842
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8843
0
    tmp = fieldname(insn, 8, 4); \
8844
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8845
0
    return S; \
8846
0
  case 157: \
8847
0
    tmp = fieldname(insn, 12, 4); \
8848
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8849
0
    tmp = fieldname(insn, 4, 4); \
8850
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8851
0
    return S; \
8852
0
  case 158: \
8853
0
    tmp = fieldname(insn, 12, 4); \
8854
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8855
0
    tmp = fieldname(insn, 8, 4); \
8856
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8857
0
    return S; \
8858
0
  case 159: \
8859
0
    tmp = fieldname(insn, 12, 4); \
8860
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8861
0
    tmp = fieldname(insn, 12, 4); \
8862
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8863
0
    tmp = fieldname(insn, 4, 4); \
8864
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8865
0
    tmp = fieldname(insn, 10, 2); \
8866
0
    MCOperand_CreateImm0(MI, tmp); \
8867
0
    return S; \
8868
0
  case 160: \
8869
0
    tmp = fieldname(insn, 6, 2); \
8870
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8871
0
    tmp = fieldname(insn, 4, 2); \
8872
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8873
0
    return S; \
8874
0
  case 161: \
8875
0
    tmp = fieldname(insn, 6, 2); \
8876
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8877
0
    return S; \
8878
0
  case 162: \
8879
0
    tmp = fieldname(insn, 12, 4); \
8880
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8881
0
    tmp = fieldname(insn, 12, 4); \
8882
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8883
0
    tmp = fieldname(insn, 4, 4); \
8884
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8885
0
    return S; \
8886
0
  case 163: \
8887
0
    tmp = fieldname(insn, 12, 4); \
8888
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8889
0
    tmp = fieldname(insn, 8, 4); \
8890
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8891
0
    tmp = fieldname(insn, 8, 4); \
8892
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8893
0
    tmp = fieldname(insn, 4, 3); \
8894
0
    MCOperand_CreateImm0(MI, tmp); \
8895
0
    return S; \
8896
0
  case 164: \
8897
0
    tmp = fieldname(insn, 12, 4); \
8898
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8899
0
    tmp = fieldname(insn, 12, 4); \
8900
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8901
0
    tmp = fieldname(insn, 8, 4); \
8902
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8903
0
    tmp = fieldname(insn, 5, 3); \
8904
0
    if (!Check(&S, DecodeBR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8905
0
    return S; \
8906
0
  case 165: \
8907
0
    tmp = fieldname(insn, 12, 4); \
8908
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8909
0
    tmp = fieldname(insn, 8, 4); \
8910
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8911
0
    return S; \
8912
0
  case 166: \
8913
0
    tmp = fieldname(insn, 12, 4); \
8914
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8915
0
    tmp = fieldname(insn, 8, 4); \
8916
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8917
0
    tmp = fieldname(insn, 8, 4); \
8918
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8919
0
    return S; \
8920
0
  case 167: \
8921
0
    tmp = fieldname(insn, 12, 4); \
8922
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8923
0
    tmp = 0x0; \
8924
0
    tmp |= fieldname(insn, 4, 2) << 0; \
8925
0
    tmp |= fieldname(insn, 8, 4) << 2; \
8926
0
    MCOperand_CreateImm0(MI, tmp); \
8927
0
    return S; \
8928
0
  case 168: \
8929
0
    tmp = fieldname(insn, 12, 4); \
8930
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8931
0
    tmp = fieldname(insn, 4, 4); \
8932
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8933
0
    tmp = fieldname(insn, 8, 4); \
8934
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8935
0
    return S; \
8936
0
  case 169: \
8937
0
    tmp = fieldname(insn, 12, 4); \
8938
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8939
0
    tmp = fieldname(insn, 8, 4); \
8940
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8941
0
    tmp = fieldname(insn, 8, 4); \
8942
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8943
0
    tmp = fieldname(insn, 4, 4); \
8944
0
    MCOperand_CreateImm0(MI, tmp); \
8945
0
    return S; \
8946
0
  case 170: \
8947
0
    tmp = fieldname(insn, 12, 4); \
8948
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8949
0
    tmp = fieldname(insn, 8, 4); \
8950
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8951
0
    tmp = fieldname(insn, 4, 4); \
8952
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8953
0
    return S; \
8954
0
  case 171: \
8955
0
    tmp = fieldname(insn, 13, 3); \
8956
0
    if (!Check(&S, DecodeBR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8957
0
    tmp = fieldname(insn, 8, 4); \
8958
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8959
0
    tmp = fieldname(insn, 4, 4); \
8960
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8961
0
    return S; \
8962
0
  case 172: \
8963
0
    tmp = fieldname(insn, 8, 4); \
8964
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8965
0
    tmp = fieldname(insn, 8, 4); \
8966
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8967
0
    tmp = fieldname(insn, 4, 4); \
8968
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8969
0
    tmp = fieldname(insn, 12, 4); \
8970
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8971
0
    return S; \
8972
0
  case 173: \
8973
0
    tmp = fieldname(insn, 12, 4); \
8974
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8975
0
    tmp = fieldname(insn, 12, 4); \
8976
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8977
0
    tmp = fieldname(insn, 8, 4); \
8978
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8979
0
    tmp = fieldname(insn, 4, 4); \
8980
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8981
0
    return S; \
8982
0
  case 174: \
8983
0
    tmp = fieldname(insn, 8, 4); \
8984
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8985
0
    tmp = fieldname(insn, 12, 4); \
8986
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8987
0
    tmp = fieldname(insn, 8, 4); \
8988
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8989
0
    tmp = fieldname(insn, 4, 3); \
8990
0
    MCOperand_CreateImm0(MI, tmp); \
8991
0
    return S; \
8992
0
  case 175: \
8993
0
    tmp = fieldname(insn, 12, 4); \
8994
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8995
0
    tmp = fieldname(insn, 4, 4); \
8996
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8997
0
    return S; \
8998
0
  case 176: \
8999
0
    tmp = fieldname(insn, 4, 2); \
9000
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9001
0
    tmp = fieldname(insn, 8, 4); \
9002
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9003
0
    tmp = fieldname(insn, 8, 4); \
9004
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9005
0
    return S; \
9006
0
  case 177: \
9007
0
    tmp = fieldname(insn, 4, 2); \
9008
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9009
0
    tmp = fieldname(insn, 8, 4); \
9010
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9011
0
    return S; \
9012
0
  case 178: \
9013
0
    tmp = fieldname(insn, 4, 2); \
9014
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9015
0
    tmp = fieldname(insn, 4, 2); \
9016
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9017
0
    tmp = fieldname(insn, 8, 4); \
9018
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9019
0
    return S; \
9020
0
  case 179: \
9021
0
    tmp = fieldname(insn, 8, 4); \
9022
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9023
0
    tmp = fieldname(insn, 8, 4); \
9024
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9025
0
    tmp = fieldname(insn, 4, 4); \
9026
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9027
0
    return S; \
9028
0
  case 180: \
9029
0
    tmp = fieldname(insn, 8, 4); \
9030
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9031
0
    tmp = fieldname(insn, 8, 4); \
9032
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9033
0
    tmp = fieldname(insn, 4, 4); \
9034
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9035
0
    return S; \
9036
0
  case 181: \
9037
0
    tmp = fieldname(insn, 8, 4); \
9038
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9039
0
    tmp = fieldname(insn, 8, 4); \
9040
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9041
0
    return S; \
9042
0
  case 182: \
9043
0
    tmp = fieldname(insn, 12, 4); \
9044
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9045
0
    tmp = fieldname(insn, 4, 4); \
9046
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9047
0
    tmp = 0x0; \
9048
0
    tmp |= fieldname(insn, 8, 4) << 0; \
9049
0
    tmp |= fieldname(insn, 16, 2) << 4; \
9050
0
    MCOperand_CreateImm0(MI, tmp); \
9051
0
    return S; \
9052
0
  case 183: \
9053
0
    tmp = fieldname(insn, 12, 4); \
9054
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9055
0
    tmp = fieldname(insn, 4, 4); \
9056
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9057
0
    tmp = 0x0; \
9058
0
    tmp |= fieldname(insn, 8, 4) << 0; \
9059
0
    tmp |= fieldname(insn, 16, 1) << 4; \
9060
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9061
0
    return S; \
9062
0
  case 184: \
9063
0
    tmp = fieldname(insn, 12, 4); \
9064
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9065
0
    tmp = fieldname(insn, 8, 4); \
9066
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9067
0
    tmp = fieldname(insn, 4, 4); \
9068
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9069
0
    tmp = fieldname(insn, 16, 4); \
9070
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9071
0
    return S; \
9072
0
  case 185: \
9073
0
    tmp = fieldname(insn, 12, 4); \
9074
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9075
0
    tmp = fieldname(insn, 8, 4); \
9076
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9077
0
    tmp = fieldname(insn, 8, 4); \
9078
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9079
0
    tmp = fieldname(insn, 4, 4); \
9080
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9081
0
    return S; \
9082
0
  case 186: \
9083
0
    tmp = fieldname(insn, 12, 4); \
9084
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9085
0
    tmp = fieldname(insn, 8, 4); \
9086
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9087
0
    tmp = fieldname(insn, 4, 4); \
9088
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9089
0
    return S; \
9090
0
  case 187: \
9091
0
    tmp = fieldname(insn, 12, 4); \
9092
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9093
0
    tmp = fieldname(insn, 4, 4); \
9094
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9095
0
    tmp = fieldname(insn, 4, 4); \
9096
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9097
0
    tmp = fieldname(insn, 8, 4); \
9098
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9099
0
    return S; \
9100
0
  case 188: \
9101
0
    tmp = fieldname(insn, 12, 4); \
9102
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9103
0
    tmp = fieldname(insn, 4, 4); \
9104
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9105
0
    tmp = fieldname(insn, 16, 4); \
9106
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9107
0
    tmp = fieldname(insn, 8, 4); \
9108
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9109
0
    return S; \
9110
0
  case 189: \
9111
0
    tmp = fieldname(insn, 16, 4); \
9112
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9113
0
    tmp = fieldname(insn, 20, 4); \
9114
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9115
0
    tmp = fieldname(insn, 24, 4); \
9116
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9117
0
    return S; \
9118
0
  case 190: \
9119
0
    tmp = fieldname(insn, 16, 4); \
9120
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9121
0
    tmp = fieldname(insn, 16, 4); \
9122
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9123
0
    tmp = fieldname(insn, 20, 4); \
9124
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9125
0
    tmp = fieldname(insn, 24, 4); \
9126
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9127
0
    return S; \
9128
0
  case 191: \
9129
0
    tmp = fieldname(insn, 16, 4); \
9130
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9131
0
    tmp = fieldname(insn, 16, 4); \
9132
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9133
0
    tmp = fieldname(insn, 24, 4); \
9134
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9135
0
    tmp = fieldname(insn, 20, 4); \
9136
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9137
0
    return S; \
9138
0
  case 192: \
9139
0
    tmp = fieldname(insn, 16, 4); \
9140
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9141
0
    tmp = fieldname(insn, 24, 4); \
9142
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9143
0
    tmp = fieldname(insn, 20, 4); \
9144
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9145
0
    return S; \
9146
0
  case 193: \
9147
0
    tmp = fieldname(insn, 6, 2); \
9148
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9149
0
    tmp = fieldname(insn, 8, 4); \
9150
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9151
0
    tmp = fieldname(insn, 12, 4); \
9152
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9153
0
    tmp = fieldname(insn, 6, 2); \
9154
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9155
0
    tmp = fieldname(insn, 8, 4); \
9156
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9157
0
    return S; \
9158
0
  case 194: \
9159
0
    tmp = fieldname(insn, 12, 4); \
9160
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9161
0
    tmp = fieldname(insn, 6, 2); \
9162
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9163
0
    tmp = fieldname(insn, 8, 4); \
9164
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9165
0
    tmp = fieldname(insn, 6, 2); \
9166
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9167
0
    tmp = fieldname(insn, 8, 4); \
9168
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9169
0
    return S; \
9170
0
  case 195: \
9171
0
    tmp = fieldname(insn, 8, 4); \
9172
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9173
0
    tmp = fieldname(insn, 12, 4); \
9174
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9175
0
    tmp = fieldname(insn, 8, 4); \
9176
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9177
0
    return S; \
9178
0
  case 196: \
9179
0
    tmp = fieldname(insn, 6, 2); \
9180
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9181
0
    tmp = fieldname(insn, 8, 4); \
9182
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9183
0
    tmp = fieldname(insn, 8, 4); \
9184
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9185
0
    return S; \
9186
0
  case 197: \
9187
0
    tmp = fieldname(insn, 6, 2); \
9188
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9189
0
    tmp = fieldname(insn, 6, 2); \
9190
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9191
0
    tmp = fieldname(insn, 8, 4); \
9192
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9193
0
    return S; \
9194
0
  case 198: \
9195
0
    tmp = fieldname(insn, 6, 2); \
9196
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9197
0
    tmp = fieldname(insn, 8, 4); \
9198
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9199
0
    tmp = 0x0; \
9200
0
    tmp |= fieldname(insn, 4, 2) << 0; \
9201
0
    tmp |= fieldname(insn, 28, 2) << 2; \
9202
0
    MCOperand_CreateImm0(MI, tmp); \
9203
0
    return S; \
9204
0
  case 199: \
9205
0
    tmp = fieldname(insn, 12, 4); \
9206
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9207
0
    tmp = fieldname(insn, 4, 4); \
9208
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9209
0
    return S; \
9210
0
  case 200: \
9211
0
    tmp = fieldname(insn, 20, 4); \
9212
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9213
0
    tmp = fieldname(insn, 24, 4); \
9214
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9215
0
    tmp = fieldname(insn, 16, 4); \
9216
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9217
0
    return S; \
9218
0
  case 201: \
9219
0
    tmp = fieldname(insn, 20, 4); \
9220
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9221
0
    tmp = fieldname(insn, 16, 4); \
9222
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9223
0
    return S; \
9224
0
  case 202: \
9225
0
    tmp = fieldname(insn, 16, 4); \
9226
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9227
0
    tmp = fieldname(insn, 20, 4); \
9228
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9229
0
    tmp = fieldname(insn, 16, 4); \
9230
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9231
0
    tmp = fieldname(insn, 20, 4); \
9232
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9233
0
    tmp = fieldname(insn, 24, 4); \
9234
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9235
0
    tmp = fieldname(insn, 32, 4); \
9236
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9237
0
    tmp = fieldname(insn, 36, 4); \
9238
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9239
0
    return S; \
9240
0
  case 203: \
9241
0
    tmp = fieldname(insn, 16, 4); \
9242
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9243
0
    tmp = fieldname(insn, 24, 4); \
9244
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9245
0
    tmp = fieldname(insn, 32, 4); \
9246
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9247
0
    tmp = fieldname(insn, 48, 2); \
9248
0
    MCOperand_CreateImm0(MI, tmp); \
9249
0
    return S; \
9250
0
  case 204: \
9251
0
    tmp = fieldname(insn, 16, 4); \
9252
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9253
0
    tmp = fieldname(insn, 16, 4); \
9254
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9255
0
    tmp = fieldname(insn, 24, 4); \
9256
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9257
0
    tmp = fieldname(insn, 32, 4); \
9258
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9259
0
    return S; \
9260
0
  case 205: \
9261
0
    tmp = fieldname(insn, 16, 4); \
9262
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9263
0
    tmp = fieldname(insn, 24, 4); \
9264
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9265
0
    tmp = fieldname(insn, 32, 4); \
9266
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9267
0
    return S; \
9268
0
  case 206: \
9269
0
    tmp = fieldname(insn, 28, 4); \
9270
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9271
0
    tmp = fieldname(insn, 4, 4); \
9272
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9273
0
    tmp = fieldname(insn, 12, 4); \
9274
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9275
0
    tmp = fieldname(insn, 8, 4); \
9276
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9277
0
    return S; \
9278
0
  case 207: \
9279
0
    tmp = fieldname(insn, 28, 4); \
9280
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9281
0
    tmp = fieldname(insn, 4, 4); \
9282
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9283
0
    tmp = fieldname(insn, 12, 4); \
9284
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9285
0
    tmp = fieldname(insn, 8, 4); \
9286
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9287
0
    return S; \
9288
0
  case 208: \
9289
0
    tmp = fieldname(insn, 28, 4); \
9290
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9291
0
    tmp = fieldname(insn, 4, 4); \
9292
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9293
0
    tmp = fieldname(insn, 8, 4); \
9294
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9295
0
    return S; \
9296
0
  case 209: \
9297
0
    tmp = fieldname(insn, 16, 4); \
9298
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9299
0
    tmp = fieldname(insn, 32, 4); \
9300
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9301
0
    return S; \
9302
0
  case 210: \
9303
0
    tmp = fieldname(insn, 16, 4); \
9304
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9305
0
    tmp = fieldname(insn, 20, 4); \
9306
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9307
0
    tmp = fieldname(insn, 24, 4); \
9308
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9309
0
    tmp = fieldname(insn, 32, 4); \
9310
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9311
0
    tmp = fieldname(insn, 36, 4); \
9312
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9313
0
    return S; \
9314
0
  case 211: \
9315
0
    tmp = fieldname(insn, 20, 4); \
9316
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9317
0
    tmp = fieldname(insn, 28, 4); \
9318
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9319
0
    tmp = 0x0; \
9320
0
    tmp |= fieldname(insn, 36, 4) << 0; \
9321
0
    tmp |= fieldname(insn, 56, 2) << 4; \
9322
0
    MCOperand_CreateImm0(MI, tmp); \
9323
0
    return S; \
9324
0
  case 212: \
9325
0
    tmp = fieldname(insn, 20, 4); \
9326
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9327
0
    tmp = fieldname(insn, 16, 4); \
9328
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9329
0
    tmp = fieldname(insn, 32, 4); \
9330
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9331
0
    tmp = fieldname(insn, 24, 4); \
9332
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9333
0
    return S; \
9334
0
  case 213: \
9335
0
    tmp = fieldname(insn, 20, 4); \
9336
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9337
0
    tmp = fieldname(insn, 16, 4); \
9338
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9339
0
    tmp = fieldname(insn, 20, 4); \
9340
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9341
0
    tmp = fieldname(insn, 16, 4); \
9342
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9343
0
    tmp = fieldname(insn, 32, 4); \
9344
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9345
0
    tmp = fieldname(insn, 24, 4); \
9346
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9347
0
    return S; \
9348
0
  case 214: \
9349
0
    tmp = fieldname(insn, 20, 4); \
9350
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9351
0
    tmp = fieldname(insn, 28, 4); \
9352
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9353
0
    tmp = 0x0; \
9354
0
    tmp |= fieldname(insn, 36, 4) << 0; \
9355
0
    tmp |= fieldname(insn, 56, 1) << 4; \
9356
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9357
0
    return S; \
9358
0
  case 215: \
9359
0
    tmp = fieldname(insn, 20, 4); \
9360
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9361
0
    tmp = fieldname(insn, 36, 4); \
9362
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9363
0
    tmp = fieldname(insn, 28, 4); \
9364
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9365
0
    return S; \
9366
0
  case 216: \
9367
0
    tmp = fieldname(insn, 20, 4); \
9368
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9369
0
    tmp = fieldname(insn, 20, 4); \
9370
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9371
0
    tmp = fieldname(insn, 36, 4); \
9372
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9373
0
    tmp = fieldname(insn, 28, 4); \
9374
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9375
0
    return S; \
9376
0
  case 217: \
9377
0
    tmp = fieldname(insn, 20, 4); \
9378
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9379
0
    tmp = fieldname(insn, 28, 4); \
9380
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9381
0
    tmp = fieldname(insn, 36, 4); \
9382
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9383
0
    return S; \
9384
0
  case 218: \
9385
0
    tmp = fieldname(insn, 20, 4); \
9386
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9387
0
    tmp = fieldname(insn, 36, 4); \
9388
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9389
0
    tmp = fieldname(insn, 28, 4); \
9390
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9391
0
    return S; \
9392
0
  case 219: \
9393
0
    tmp = fieldname(insn, 20, 4); \
9394
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9395
0
    tmp = fieldname(insn, 20, 4); \
9396
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9397
0
    tmp = fieldname(insn, 36, 4); \
9398
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9399
0
    tmp = fieldname(insn, 28, 4); \
9400
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9401
0
    return S; \
9402
0
  case 220: \
9403
0
    tmp = fieldname(insn, 21, 3); \
9404
0
    if (!Check(&S, DecodeBR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9405
0
    tmp = fieldname(insn, 36, 4); \
9406
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9407
0
    tmp = fieldname(insn, 28, 4); \
9408
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9409
0
    return S; \
9410
0
  case 221: \
9411
0
    tmp = fieldname(insn, 22, 2); \
9412
0
    if (!Check(&S, DecodeBR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9413
0
    tmp = fieldname(insn, 36, 4); \
9414
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9415
0
    tmp = fieldname(insn, 28, 4); \
9416
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9417
0
    return S; \
9418
0
  case 222: \
9419
0
    tmp = fieldname(insn, 20, 4); \
9420
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9421
0
    tmp = fieldname(insn, 20, 4); \
9422
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9423
0
    tmp = fieldname(insn, 36, 4); \
9424
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9425
0
    tmp = fieldname(insn, 30, 2); \
9426
0
    if (!Check(&S, DecodeBR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9427
0
    return S; \
9428
0
  case 223: \
9429
0
    tmp = fieldname(insn, 20, 4); \
9430
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9431
0
    tmp = fieldname(insn, 20, 4); \
9432
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9433
0
    tmp = fieldname(insn, 36, 4); \
9434
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9435
0
    return S; \
9436
0
  case 224: \
9437
0
    tmp = fieldname(insn, 20, 4); \
9438
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9439
0
    tmp = fieldname(insn, 36, 4); \
9440
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9441
0
    return S; \
9442
0
  case 225: \
9443
0
    tmp = fieldname(insn, 20, 4); \
9444
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9445
0
    tmp = fieldname(insn, 28, 4); \
9446
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9447
0
    return S; \
9448
0
  case 226: \
9449
0
    tmp = fieldname(insn, 20, 4); \
9450
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9451
0
    tmp = fieldname(insn, 28, 4); \
9452
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9453
0
    tmp = fieldname(insn, 36, 4); \
9454
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9455
0
    return S; \
9456
55.7k
  } \
9457
55.7k
}
XtensaDisassembler.c:decodeToMCInst_2
Line
Count
Source
7098
14.4k
    uint64_t Address, const void *Decoder, bool *DecodeComplete) \
7099
14.4k
{ \
7100
14.4k
  *DecodeComplete = true; \
7101
14.4k
  InsnType tmp; \
7102
14.4k
  switch (Idx) { \
7103
0
  default: CS_ASSERT_RET_VAL(0 && "Invalid index!", MCDisassembler_Fail); \
7104
3.83k
  case 0: \
7105
3.83k
    tmp = fieldname(insn, 4, 4); \
7106
3.83k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7107
3.83k
    tmp = fieldname(insn, 8, 8); \
7108
3.83k
    if (!Check(&S, decodeMem32nOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7109
3.83k
    return S; \
7110
4.76k
  case 1: \
7111
4.76k
    tmp = fieldname(insn, 12, 4); \
7112
4.76k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7113
4.76k
    tmp = fieldname(insn, 8, 4); \
7114
4.76k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7115
4.76k
    tmp = fieldname(insn, 4, 4); \
7116
4.76k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7117
4.76k
    return S; \
7118
4.76k
  case 2: \
7119
3.35k
    tmp = fieldname(insn, 12, 4); \
7120
3.35k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7121
3.35k
    tmp = fieldname(insn, 8, 4); \
7122
3.35k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7123
3.35k
    tmp = fieldname(insn, 4, 4); \
7124
3.35k
    if (!Check(&S, decodeImm1n_15Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7125
3.35k
    return S; \
7126
3.35k
  case 3: \
7127
310
    tmp = fieldname(insn, 8, 4); \
7128
310
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7129
310
    return S; \
7130
1.48k
  case 4: \
7131
1.48k
    tmp = fieldname(insn, 8, 4); \
7132
1.48k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7133
1.48k
    tmp = 0x0; \
7134
1.48k
    tmp |= fieldname(insn, 4, 3) << 4; \
7135
1.48k
    tmp |= fieldname(insn, 12, 4) << 0; \
7136
1.48k
    if (!Check(&S, decodeImm32n_95Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7137
1.48k
    return S; \
7138
1.48k
  case 5: \
7139
630
    tmp = fieldname(insn, 4, 4); \
7140
630
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7141
630
    tmp = fieldname(insn, 8, 4); \
7142
630
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7143
630
    return S; \
7144
630
  case 6: \
7145
43
    return S; \
7146
630
  case 7: \
7147
0
    tmp = fieldname(insn, 8, 4); \
7148
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7149
0
    return S; \
7150
0
  case 8: \
7151
0
    tmp = fieldname(insn, 8, 4); \
7152
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7153
0
    tmp = fieldname(insn, 4, 4); \
7154
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7155
0
    return S; \
7156
0
  case 9: \
7157
0
    tmp = fieldname(insn, 4, 4); \
7158
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7159
0
    tmp = fieldname(insn, 8, 4); \
7160
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7161
0
    return S; \
7162
0
  case 10: \
7163
0
    tmp = fieldname(insn, 4, 4); \
7164
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7165
0
    tmp = fieldname(insn, 8, 4); \
7166
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7167
0
    return S; \
7168
0
  case 11: \
7169
0
    tmp = fieldname(insn, 12, 4); \
7170
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7171
0
    tmp = fieldname(insn, 8, 4); \
7172
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7173
0
    tmp = 0x0; \
7174
0
    tmp |= fieldname(insn, 4, 4) << 0; \
7175
0
    tmp |= fieldname(insn, 20, 1) << 4; \
7176
0
    if (!Check(&S, decodeShimm1_31Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7177
0
    return S; \
7178
0
  case 12: \
7179
0
    tmp = fieldname(insn, 12, 4); \
7180
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7181
0
    tmp = fieldname(insn, 4, 4); \
7182
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7183
0
    tmp = 0x0; \
7184
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7185
0
    tmp |= fieldname(insn, 20, 1) << 4; \
7186
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7187
0
    return S; \
7188
0
  case 13: \
7189
0
    tmp = 0x0; \
7190
0
    tmp |= fieldname(insn, 4, 1) << 4; \
7191
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7192
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7193
0
    return S; \
7194
0
  case 14: \
7195
0
    tmp = fieldname(insn, 4, 4); \
7196
0
    if (!Check(&S, decodeImm8n_7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7197
0
    return S; \
7198
0
  case 15: \
7199
0
    tmp = fieldname(insn, 12, 4); \
7200
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7201
0
    tmp = fieldname(insn, 4, 4); \
7202
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7203
0
    tmp = fieldname(insn, 8, 4); \
7204
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7205
0
    return S; \
7206
0
  case 16: \
7207
0
    tmp = fieldname(insn, 12, 4); \
7208
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7209
0
    tmp = fieldname(insn, 4, 4); \
7210
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7211
0
    return S; \
7212
0
  case 17: \
7213
0
    tmp = fieldname(insn, 4, 4); \
7214
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7215
0
    tmp = fieldname(insn, 8, 8); \
7216
0
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7217
0
    tmp = fieldname(insn, 4, 4); \
7218
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7219
0
    tmp = fieldname(insn, 8, 8); \
7220
0
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7221
0
    return S; \
7222
0
  case 18: \
7223
0
    tmp = fieldname(insn, 12, 4); \
7224
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7225
0
    tmp = fieldname(insn, 8, 4); \
7226
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7227
0
    return S; \
7228
0
  case 19: \
7229
0
    tmp = fieldname(insn, 12, 4); \
7230
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7231
0
    tmp = fieldname(insn, 8, 4); \
7232
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7233
0
    tmp = fieldname(insn, 4, 4); \
7234
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7235
0
    return S; \
7236
0
  case 20: \
7237
0
    tmp = fieldname(insn, 4, 4); \
7238
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7239
0
    tmp = fieldname(insn, 8, 8); \
7240
0
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7241
0
    return S; \
7242
0
  case 21: \
7243
0
    tmp = fieldname(insn, 8, 8); \
7244
0
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7245
0
    tmp = fieldname(insn, 4, 4); \
7246
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7247
0
    return S; \
7248
0
  case 22: \
7249
0
    tmp = fieldname(insn, 12, 4); \
7250
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7251
0
    tmp = fieldname(insn, 8, 4); \
7252
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7253
0
    tmp = fieldname(insn, 4, 4); \
7254
0
    if (!Check(&S, decodeImm7_22Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7255
0
    return S; \
7256
0
  case 23: \
7257
0
    tmp = fieldname(insn, 12, 4); \
7258
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7259
0
    tmp = fieldname(insn, 12, 4); \
7260
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7261
0
    tmp = fieldname(insn, 8, 4); \
7262
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7263
0
    tmp = fieldname(insn, 4, 4); \
7264
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7265
0
    return S; \
7266
0
  case 24: \
7267
0
    tmp = fieldname(insn, 12, 4); \
7268
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7269
0
    tmp = fieldname(insn, 4, 8); \
7270
0
    if (!Check(&S, DecodeURRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7271
0
    return S; \
7272
0
  case 25: \
7273
0
    tmp = fieldname(insn, 4, 4); \
7274
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7275
0
    return S; \
7276
0
  case 26: \
7277
0
    tmp = fieldname(insn, 8, 8); \
7278
0
    if (!Check(&S, DecodeURRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7279
0
    tmp = fieldname(insn, 4, 4); \
7280
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7281
0
    return S; \
7282
0
  case 27: \
7283
0
    tmp = fieldname(insn, 12, 4); \
7284
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7285
0
    tmp = fieldname(insn, 4, 4); \
7286
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7287
0
    tmp = 0x0; \
7288
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7289
0
    tmp |= fieldname(insn, 16, 1) << 4; \
7290
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7291
0
    tmp = fieldname(insn, 20, 4); \
7292
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7293
0
    return S; \
7294
0
  case 28: \
7295
0
    tmp = fieldname(insn, 4, 8); \
7296
0
    if (!Check(&S, decodeSelect_256Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7297
0
    return S; \
7298
0
  case 29: \
7299
0
    tmp = fieldname(insn, 8, 4); \
7300
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7301
0
    tmp = fieldname(insn, 4, 4); \
7302
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7303
0
    return S; \
7304
0
  case 30: \
7305
0
    tmp = fieldname(insn, 12, 4); \
7306
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7307
0
    tmp = fieldname(insn, 8, 4); \
7308
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7309
0
    tmp = fieldname(insn, 4, 4); \
7310
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7311
0
    return S; \
7312
0
  case 31: \
7313
0
    tmp = fieldname(insn, 4, 4); \
7314
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7315
0
    tmp = fieldname(insn, 8, 4); \
7316
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7317
0
    tmp = fieldname(insn, 12, 4) << 2; \
7318
0
    if (!Check(&S, decodeImm64n_4nOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7319
0
    return S; \
7320
0
  case 32: \
7321
0
    tmp = fieldname(insn, 12, 4); \
7322
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7323
0
    tmp = fieldname(insn, 8, 4); \
7324
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7325
0
    tmp = fieldname(insn, 8, 4); \
7326
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7327
0
    tmp = fieldname(insn, 4, 4); \
7328
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7329
0
    return S; \
7330
0
  case 33: \
7331
0
    tmp = fieldname(insn, 8, 4); \
7332
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7333
0
    tmp = fieldname(insn, 12, 4); \
7334
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7335
0
    tmp = fieldname(insn, 8, 4); \
7336
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7337
0
    tmp = fieldname(insn, 4, 4); \
7338
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7339
0
    return S; \
7340
0
  case 34: \
7341
0
    tmp = fieldname(insn, 12, 4); \
7342
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7343
0
    tmp = fieldname(insn, 8, 4); \
7344
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7345
0
    tmp = fieldname(insn, 4, 4); \
7346
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7347
0
    return S; \
7348
0
  case 35: \
7349
0
    tmp = fieldname(insn, 12, 4); \
7350
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7351
0
    tmp = fieldname(insn, 8, 4); \
7352
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7353
0
    tmp = fieldname(insn, 4, 4); \
7354
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7355
0
    return S; \
7356
0
  case 36: \
7357
0
    tmp = fieldname(insn, 12, 4); \
7358
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7359
0
    tmp = fieldname(insn, 12, 4); \
7360
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7361
0
    tmp = fieldname(insn, 8, 4); \
7362
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7363
0
    tmp = fieldname(insn, 4, 4); \
7364
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7365
0
    return S; \
7366
0
  case 37: \
7367
0
    tmp = fieldname(insn, 12, 4); \
7368
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7369
0
    tmp = fieldname(insn, 8, 4); \
7370
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7371
0
    tmp = fieldname(insn, 4, 4); \
7372
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7373
0
    return S; \
7374
0
  case 38: \
7375
0
    tmp = fieldname(insn, 12, 4); \
7376
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7377
0
    tmp = fieldname(insn, 12, 4); \
7378
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7379
0
    tmp = fieldname(insn, 8, 4); \
7380
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7381
0
    tmp = fieldname(insn, 4, 4); \
7382
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7383
0
    return S; \
7384
0
  case 39: \
7385
0
    tmp = fieldname(insn, 12, 4); \
7386
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7387
0
    tmp = fieldname(insn, 8, 4); \
7388
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7389
0
    tmp = fieldname(insn, 4, 4); \
7390
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7391
0
    return S; \
7392
0
  case 40: \
7393
0
    tmp = fieldname(insn, 12, 4); \
7394
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7395
0
    tmp = fieldname(insn, 12, 4); \
7396
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7397
0
    tmp = fieldname(insn, 8, 4); \
7398
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7399
0
    tmp = fieldname(insn, 4, 4); \
7400
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7401
0
    return S; \
7402
0
  case 41: \
7403
0
    tmp = fieldname(insn, 12, 4); \
7404
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7405
0
    tmp = fieldname(insn, 8, 4); \
7406
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7407
0
    return S; \
7408
0
  case 42: \
7409
0
    tmp = fieldname(insn, 12, 4); \
7410
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7411
0
    tmp = fieldname(insn, 8, 4); \
7412
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7413
0
    return S; \
7414
0
  case 43: \
7415
0
    tmp = fieldname(insn, 12, 4); \
7416
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7417
0
    tmp = fieldname(insn, 8, 4); \
7418
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7419
0
    return S; \
7420
0
  case 44: \
7421
0
    tmp = fieldname(insn, 12, 4); \
7422
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7423
0
    tmp = fieldname(insn, 8, 4); \
7424
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7425
0
    return S; \
7426
0
  case 45: \
7427
0
    tmp = fieldname(insn, 12, 4); \
7428
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7429
0
    tmp = fieldname(insn, 12, 4); \
7430
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7431
0
    tmp = fieldname(insn, 8, 4); \
7432
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7433
0
    return S; \
7434
0
  case 46: \
7435
0
    tmp = fieldname(insn, 4, 4); \
7436
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7437
0
    tmp = fieldname(insn, 8, 16); \
7438
0
    if (!Check(&S, decodeL32ROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7439
0
    return S; \
7440
0
  case 47: \
7441
0
    tmp = fieldname(insn, 4, 4); \
7442
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7443
0
    tmp = 0x0; \
7444
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7445
0
    tmp |= fieldname(insn, 16, 8) << 4; \
7446
0
    if (!Check(&S, decodeMem8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7447
0
    return S; \
7448
0
  case 48: \
7449
0
    tmp = fieldname(insn, 4, 4); \
7450
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7451
0
    tmp = 0x0; \
7452
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7453
0
    tmp |= fieldname(insn, 16, 8) << 4; \
7454
0
    if (!Check(&S, decodeMem16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7455
0
    return S; \
7456
0
  case 49: \
7457
0
    tmp = fieldname(insn, 4, 4); \
7458
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7459
0
    tmp = 0x0; \
7460
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7461
0
    tmp |= fieldname(insn, 16, 8) << 4; \
7462
0
    if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7463
0
    return S; \
7464
0
  case 50: \
7465
0
    tmp = fieldname(insn, 4, 4); \
7466
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7467
0
    tmp = 0x0; \
7468
0
    tmp |= fieldname(insn, 8, 4) << 8; \
7469
0
    tmp |= fieldname(insn, 16, 8) << 0; \
7470
0
    if (!Check(&S, decodeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7471
0
    return S; \
7472
0
  case 51: \
7473
0
    tmp = fieldname(insn, 4, 4); \
7474
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7475
0
    tmp = fieldname(insn, 8, 4); \
7476
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7477
0
    tmp = fieldname(insn, 16, 8); \
7478
0
    if (!Check(&S, decodeImm8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7479
0
    return S; \
7480
0
  case 52: \
7481
0
    tmp = fieldname(insn, 4, 4); \
7482
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7483
0
    tmp = fieldname(insn, 8, 4); \
7484
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7485
0
    tmp = fieldname(insn, 16, 8) << 8; \
7486
0
    if (!Check(&S, decodeImm8_sh8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7487
0
    return S; \
7488
0
  case 53: \
7489
0
    tmp = fieldname(insn, 4, 4); \
7490
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7491
0
    tmp = fieldname(insn, 4, 4); \
7492
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7493
0
    tmp = 0x0; \
7494
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7495
0
    tmp |= fieldname(insn, 16, 8) << 4; \
7496
0
    if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7497
0
    return S; \
7498
0
  case 54: \
7499
0
    tmp = fieldname(insn, 4, 4); \
7500
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7501
0
    tmp = 0x0; \
7502
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7503
0
    tmp |= fieldname(insn, 16, 8) << 4; \
7504
0
    if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7505
0
    return S; \
7506
0
  case 55: \
7507
0
    tmp = fieldname(insn, 4, 4); \
7508
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7509
0
    tmp = fieldname(insn, 8, 4); \
7510
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7511
0
    tmp = fieldname(insn, 8, 4); \
7512
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7513
0
    tmp = fieldname(insn, 16, 8) << 2; \
7514
0
    if (!Check(&S, decodeOffset8m32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7515
0
    return S; \
7516
0
  case 56: \
7517
0
    tmp = fieldname(insn, 8, 4); \
7518
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7519
0
    tmp = fieldname(insn, 4, 4); \
7520
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7521
0
    tmp = fieldname(insn, 8, 4); \
7522
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7523
0
    tmp = fieldname(insn, 16, 8) << 2; \
7524
0
    if (!Check(&S, decodeOffset8m32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7525
0
    return S; \
7526
0
  case 57: \
7527
0
    tmp = fieldname(insn, 12, 2); \
7528
0
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7529
0
    tmp = fieldname(insn, 8, 4); \
7530
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7531
0
    tmp = fieldname(insn, 8, 4); \
7532
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7533
0
    tmp = fieldname(insn, 14, 1); \
7534
0
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7535
0
    tmp = fieldname(insn, 6, 1); \
7536
0
    if (!Check(&S, DecodeMR23RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7537
0
    return S; \
7538
0
  case 58: \
7539
0
    tmp = fieldname(insn, 14, 1); \
7540
0
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7541
0
    tmp = fieldname(insn, 6, 1); \
7542
0
    if (!Check(&S, DecodeMR23RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7543
0
    return S; \
7544
0
  case 59: \
7545
0
    tmp = fieldname(insn, 8, 4); \
7546
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7547
0
    tmp = fieldname(insn, 6, 1); \
7548
0
    if (!Check(&S, DecodeMR23RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7549
0
    return S; \
7550
0
  case 60: \
7551
0
    tmp = fieldname(insn, 12, 2); \
7552
0
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7553
0
    tmp = fieldname(insn, 8, 4); \
7554
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7555
0
    tmp = fieldname(insn, 8, 4); \
7556
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7557
0
    tmp = fieldname(insn, 14, 1); \
7558
0
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7559
0
    tmp = fieldname(insn, 4, 4); \
7560
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7561
0
    return S; \
7562
0
  case 61: \
7563
0
    tmp = fieldname(insn, 12, 2); \
7564
0
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7565
0
    tmp = fieldname(insn, 8, 4); \
7566
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7567
0
    tmp = fieldname(insn, 8, 4); \
7568
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7569
0
    tmp = fieldname(insn, 14, 1); \
7570
0
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7571
0
    tmp = fieldname(insn, 4, 4); \
7572
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7573
0
    return S; \
7574
0
  case 62: \
7575
0
    tmp = fieldname(insn, 14, 1); \
7576
0
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7577
0
    tmp = fieldname(insn, 4, 4); \
7578
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7579
0
    return S; \
7580
0
  case 63: \
7581
0
    tmp = fieldname(insn, 12, 2); \
7582
0
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7583
0
    tmp = fieldname(insn, 8, 4); \
7584
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7585
0
    tmp = fieldname(insn, 8, 4); \
7586
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7587
0
    return S; \
7588
0
  case 64: \
7589
0
    tmp = fieldname(insn, 6, 18); \
7590
0
    if (!Check(&S, decodeCallOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7591
0
    return S; \
7592
0
  case 65: \
7593
0
    tmp = fieldname(insn, 6, 18); \
7594
0
    if (!Check(&S, decodeJumpOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7595
0
    return S; \
7596
0
  case 66: \
7597
0
    tmp = fieldname(insn, 8, 4); \
7598
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7599
0
    tmp = fieldname(insn, 12, 12); \
7600
0
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7601
0
    return S; \
7602
0
  case 67: \
7603
0
    tmp = fieldname(insn, 8, 4); \
7604
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7605
0
    tmp = fieldname(insn, 12, 4); \
7606
0
    if (!Check(&S, decodeB4constOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7607
0
    tmp = fieldname(insn, 16, 8); \
7608
0
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7609
0
    return S; \
7610
0
  case 68: \
7611
0
    tmp = fieldname(insn, 8, 4); \
7612
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7613
0
    tmp = fieldname(insn, 12, 12) << 3; \
7614
0
    if (!Check(&S, decodeEntry_Imm12OpValue(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7615
0
    return S; \
7616
0
  case 69: \
7617
0
    tmp = fieldname(insn, 8, 4); \
7618
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7619
0
    tmp = fieldname(insn, 16, 8); \
7620
0
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7621
0
    return S; \
7622
0
  case 70: \
7623
0
    tmp = fieldname(insn, 8, 4); \
7624
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7625
0
    tmp = fieldname(insn, 16, 8); \
7626
0
    if (!Check(&S, decodeLoopOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7627
0
    return S; \
7628
0
  case 71: \
7629
0
    tmp = fieldname(insn, 8, 4); \
7630
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7631
0
    tmp = fieldname(insn, 12, 4); \
7632
0
    if (!Check(&S, decodeB4constuOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7633
0
    tmp = fieldname(insn, 16, 8); \
7634
0
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7635
0
    return S; \
7636
0
  case 72: \
7637
0
    tmp = fieldname(insn, 8, 4); \
7638
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7639
0
    tmp = fieldname(insn, 4, 4); \
7640
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7641
0
    tmp = fieldname(insn, 16, 8); \
7642
0
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7643
0
    return S; \
7644
0
  case 73: \
7645
0
    tmp = fieldname(insn, 8, 4); \
7646
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7647
0
    tmp = 0x0; \
7648
0
    tmp |= fieldname(insn, 4, 4) << 0; \
7649
0
    tmp |= fieldname(insn, 12, 1) << 4; \
7650
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7651
0
    tmp = fieldname(insn, 16, 8); \
7652
0
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7653
0
    return S; \
7654
0
  case 74: \
7655
0
    tmp = fieldname(insn, 4, 4); \
7656
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7657
0
    tmp = fieldname(insn, 4, 4); \
7658
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7659
0
    tmp = 0x0; \
7660
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7661
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7662
0
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7663
0
    return S; \
7664
0
  case 75: \
7665
0
    tmp = fieldname(insn, 4, 4); \
7666
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7667
0
    tmp = fieldname(insn, 4, 4); \
7668
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7669
0
    tmp = fieldname(insn, 8, 4); \
7670
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7671
0
    return S; \
7672
0
  case 76: \
7673
0
    tmp = 0x0; \
7674
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7675
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7676
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7677
0
    tmp = fieldname(insn, 4, 4); \
7678
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7679
0
    tmp = fieldname(insn, 4, 4); \
7680
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7681
0
    tmp = 0x0; \
7682
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7683
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7684
0
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7685
0
    return S; \
7686
0
  case 77: \
7687
0
    tmp = fieldname(insn, 4, 4); \
7688
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7689
0
    tmp = fieldname(insn, 4, 4); \
7690
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7691
0
    tmp = 0x0; \
7692
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7693
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7694
0
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7695
0
    return S; \
7696
0
  case 78: \
7697
0
    tmp = fieldname(insn, 4, 4); \
7698
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7699
0
    tmp = fieldname(insn, 4, 4); \
7700
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7701
0
    tmp = 0x0; \
7702
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7703
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7704
0
    if (!Check(&S, decodeOffset_256_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7705
0
    return S; \
7706
0
  case 79: \
7707
0
    tmp = 0x0; \
7708
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7709
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7710
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7711
0
    tmp = fieldname(insn, 4, 4); \
7712
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7713
0
    tmp = fieldname(insn, 4, 4); \
7714
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7715
0
    tmp = 0x0; \
7716
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7717
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7718
0
    if (!Check(&S, decodeOffset_256_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7719
0
    return S; \
7720
0
  case 80: \
7721
0
    tmp = fieldname(insn, 12, 4); \
7722
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7723
0
    return S; \
7724
0
  case 81: \
7725
0
    tmp = fieldname(insn, 4, 4); \
7726
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7727
0
    tmp = 0x0; \
7728
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7729
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7730
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7731
0
    tmp = fieldname(insn, 4, 4); \
7732
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7733
0
    tmp = 0x0; \
7734
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7735
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7736
0
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7737
0
    return S; \
7738
0
  case 82: \
7739
0
    tmp = 0x0; \
7740
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7741
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7742
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7743
0
    tmp = fieldname(insn, 4, 4); \
7744
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7745
0
    tmp = fieldname(insn, 4, 4); \
7746
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7747
0
    tmp = fieldname(insn, 8, 7); \
7748
0
    if (!Check(&S, decodeOffset_128_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7749
0
    return S; \
7750
0
  case 83: \
7751
0
    tmp = 0x0; \
7752
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7753
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7754
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7755
0
    tmp = fieldname(insn, 4, 4); \
7756
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7757
0
    tmp = fieldname(insn, 4, 4); \
7758
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7759
0
    tmp = fieldname(insn, 8, 7); \
7760
0
    if (!Check(&S, decodeOffset_128_1Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7761
0
    return S; \
7762
0
  case 84: \
7763
0
    tmp = fieldname(insn, 12, 4); \
7764
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7765
0
    tmp = fieldname(insn, 20, 4); \
7766
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7767
0
    tmp = fieldname(insn, 4, 4); \
7768
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7769
0
    tmp = fieldname(insn, 4, 4); \
7770
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7771
0
    tmp = fieldname(insn, 8, 4); \
7772
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7773
0
    return S; \
7774
0
  case 85: \
7775
0
    tmp = 0x0; \
7776
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7777
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7778
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7779
0
    tmp = fieldname(insn, 12, 3); \
7780
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7781
0
    tmp = fieldname(insn, 4, 4); \
7782
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7783
0
    tmp = 0x0; \
7784
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7785
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7786
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7787
0
    tmp = fieldname(insn, 12, 3); \
7788
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7789
0
    tmp = fieldname(insn, 4, 4); \
7790
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7791
0
    tmp = fieldname(insn, 8, 4); \
7792
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7793
0
    return S; \
7794
0
  case 86: \
7795
0
    tmp = fieldname(insn, 4, 4); \
7796
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7797
0
    tmp = fieldname(insn, 12, 4); \
7798
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7799
0
    tmp = fieldname(insn, 20, 4); \
7800
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7801
0
    tmp = fieldname(insn, 4, 4); \
7802
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7803
0
    tmp = fieldname(insn, 8, 4); \
7804
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7805
0
    return S; \
7806
0
  case 87: \
7807
0
    tmp = 0x0; \
7808
0
    tmp |= fieldname(insn, 13, 1) << 0; \
7809
0
    tmp |= fieldname(insn, 15, 1) << 1; \
7810
0
    tmp |= fieldname(insn, 20, 1) << 2; \
7811
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7812
0
    tmp = fieldname(insn, 4, 4); \
7813
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7814
0
    tmp = fieldname(insn, 4, 4); \
7815
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7816
0
    tmp = fieldname(insn, 8, 3); \
7817
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7818
0
    tmp = 0x0; \
7819
0
    tmp |= fieldname(insn, 11, 2) << 0; \
7820
0
    tmp |= fieldname(insn, 14, 1) << 2; \
7821
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7822
0
    return S; \
7823
0
  case 88: \
7824
0
    tmp = 0x0; \
7825
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7826
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7827
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7828
0
    tmp = fieldname(insn, 4, 4); \
7829
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7830
0
    tmp = fieldname(insn, 4, 4); \
7831
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7832
0
    tmp = 0x0; \
7833
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7834
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7835
0
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7836
0
    return S; \
7837
0
  case 89: \
7838
0
    tmp = fieldname(insn, 8, 3); \
7839
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7840
0
    tmp = 0x0; \
7841
0
    tmp |= fieldname(insn, 11, 2) << 0; \
7842
0
    tmp |= fieldname(insn, 14, 1) << 2; \
7843
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7844
0
    return S; \
7845
0
  case 90: \
7846
0
    tmp = fieldname(insn, 4, 4); \
7847
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7848
0
    tmp = 0x0; \
7849
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7850
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7851
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7852
0
    tmp = fieldname(insn, 4, 4); \
7853
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7854
0
    tmp = 0x0; \
7855
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7856
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7857
0
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7858
0
    return S; \
7859
0
  case 91: \
7860
0
    tmp = 0x0; \
7861
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7862
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7863
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7864
0
    tmp = fieldname(insn, 8, 3); \
7865
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7866
0
    tmp = 0x0; \
7867
0
    tmp |= fieldname(insn, 11, 2) << 0; \
7868
0
    tmp |= fieldname(insn, 14, 1) << 2; \
7869
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7870
0
    tmp = fieldname(insn, 4, 4); \
7871
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7872
0
    return S; \
7873
0
  case 92: \
7874
0
    tmp = 0x0; \
7875
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7876
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7877
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7878
0
    tmp = fieldname(insn, 12, 3); \
7879
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7880
0
    tmp = 0x0; \
7881
0
    tmp |= fieldname(insn, 4, 1) << 0; \
7882
0
    tmp |= fieldname(insn, 6, 2) << 1; \
7883
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7884
0
    tmp = 0x0; \
7885
0
    tmp |= fieldname(insn, 5, 1) << 0; \
7886
0
    tmp |= fieldname(insn, 10, 2) << 1; \
7887
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7888
0
    tmp = fieldname(insn, 8, 1); \
7889
0
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7890
0
    return S; \
7891
0
  case 93: \
7892
0
    tmp = 0x0; \
7893
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7894
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7895
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7896
0
    tmp = fieldname(insn, 12, 3); \
7897
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7898
0
    tmp = fieldname(insn, 4, 4); \
7899
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7900
0
    tmp = fieldname(insn, 4, 4); \
7901
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7902
0
    return S; \
7903
0
  case 94: \
7904
0
    tmp = fieldname(insn, 4, 3); \
7905
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7906
0
    tmp = fieldname(insn, 12, 3); \
7907
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7908
0
    tmp = 0x0; \
7909
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7910
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7911
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7912
0
    return S; \
7913
0
  case 95: \
7914
0
    tmp = fieldname(insn, 12, 3); \
7915
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7916
0
    tmp = 0x0; \
7917
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7918
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7919
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7920
0
    tmp = fieldname(insn, 12, 3); \
7921
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7922
0
    tmp = 0x0; \
7923
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7924
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7925
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7926
0
    return S; \
7927
0
  case 96: \
7928
0
    tmp = 0x0; \
7929
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7930
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7931
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7932
0
    tmp = fieldname(insn, 12, 3); \
7933
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7934
0
    tmp = 0x0; \
7935
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7936
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7937
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7938
0
    tmp = fieldname(insn, 12, 3); \
7939
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7940
0
    tmp = fieldname(insn, 4, 4); \
7941
0
    if (!Check(&S, decodeSelect_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7942
0
    return S; \
7943
0
  case 97: \
7944
0
    tmp = fieldname(insn, 4, 3); \
7945
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7946
0
    tmp = fieldname(insn, 12, 3); \
7947
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7948
0
    tmp = fieldname(insn, 12, 3); \
7949
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7950
0
    tmp = 0x0; \
7951
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7952
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7953
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7954
0
    return S; \
7955
0
  case 98: \
7956
0
    tmp = fieldname(insn, 4, 4); \
7957
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7958
0
    tmp = fieldname(insn, 12, 3); \
7959
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7960
0
    tmp = 0x0; \
7961
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7962
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7963
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7964
0
    tmp = fieldname(insn, 4, 4); \
7965
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7966
0
    return S; \
7967
0
  case 99: \
7968
0
    tmp = 0x0; \
7969
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7970
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7971
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7972
0
    tmp = fieldname(insn, 4, 4); \
7973
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7974
0
    tmp = fieldname(insn, 4, 4); \
7975
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7976
0
    tmp = fieldname(insn, 8, 4); \
7977
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7978
0
    return S; \
7979
0
  case 100: \
7980
0
    tmp = fieldname(insn, 4, 4); \
7981
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7982
0
    tmp = 0x0; \
7983
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7984
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7985
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7986
0
    tmp = fieldname(insn, 4, 4); \
7987
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7988
0
    tmp = fieldname(insn, 8, 4); \
7989
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7990
0
    return S; \
7991
0
  case 101: \
7992
0
    tmp = 0x0; \
7993
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7994
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7995
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7996
0
    tmp = 0x0; \
7997
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7998
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7999
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8000
0
    tmp = fieldname(insn, 8, 4); \
8001
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8002
0
    tmp = fieldname(insn, 4, 4); \
8003
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8004
0
    return S; \
8005
0
  case 102: \
8006
0
    tmp = 0x0; \
8007
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8008
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8009
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8010
0
    tmp = 0x0; \
8011
0
    tmp |= fieldname(insn, 4, 1) << 0; \
8012
0
    tmp |= fieldname(insn, 6, 2) << 1; \
8013
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8014
0
    tmp = 0x0; \
8015
0
    tmp |= fieldname(insn, 5, 1) << 0; \
8016
0
    tmp |= fieldname(insn, 10, 2) << 1; \
8017
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8018
0
    return S; \
8019
0
  case 103: \
8020
0
    tmp = 0x0; \
8021
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8022
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8023
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8024
0
    tmp = fieldname(insn, 4, 4); \
8025
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8026
0
    tmp = fieldname(insn, 10, 2); \
8027
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8028
0
    return S; \
8029
0
  case 104: \
8030
0
    tmp = fieldname(insn, 4, 4); \
8031
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8032
0
    tmp = 0x0; \
8033
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8034
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8035
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8036
0
    tmp = fieldname(insn, 4, 4); \
8037
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8038
0
    tmp = fieldname(insn, 10, 1); \
8039
0
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8040
0
    return S; \
8041
0
  case 105: \
8042
0
    tmp = 0x0; \
8043
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8044
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8045
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8046
0
    tmp = fieldname(insn, 4, 4); \
8047
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8048
0
    return S; \
8049
0
  case 106: \
8050
0
    tmp = fieldname(insn, 4, 3); \
8051
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8052
0
    tmp = 0x0; \
8053
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8054
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8055
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8056
0
    return S; \
8057
0
  case 107: \
8058
0
    tmp = fieldname(insn, 4, 4); \
8059
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8060
0
    tmp = 0x0; \
8061
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8062
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8063
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8064
0
    tmp = fieldname(insn, 10, 2); \
8065
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8066
0
    return S; \
8067
0
  case 108: \
8068
0
    tmp = 0x0; \
8069
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8070
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8071
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8072
0
    tmp = fieldname(insn, 4, 4); \
8073
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8074
0
    tmp = fieldname(insn, 10, 1); \
8075
0
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8076
0
    return S; \
8077
0
  case 109: \
8078
0
    tmp = 0x0; \
8079
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8080
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8081
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8082
0
    tmp = fieldname(insn, 4, 4); \
8083
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8084
0
    tmp = fieldname(insn, 4, 4); \
8085
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8086
0
    return S; \
8087
0
  case 110: \
8088
0
    tmp = 0x0; \
8089
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8090
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8091
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8092
0
    tmp = 0x0; \
8093
0
    tmp |= fieldname(insn, 4, 1) << 0; \
8094
0
    tmp |= fieldname(insn, 6, 2) << 1; \
8095
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8096
0
    return S; \
8097
0
  case 111: \
8098
0
    tmp = 0x0; \
8099
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8100
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8101
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8102
0
    return S; \
8103
0
  case 112: \
8104
0
    tmp = fieldname(insn, 8, 4); \
8105
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8106
0
    tmp = fieldname(insn, 4, 4); \
8107
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8108
0
    tmp = fieldname(insn, 14, 1); \
8109
0
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8110
0
    return S; \
8111
0
  case 113: \
8112
0
    tmp = 0x0; \
8113
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8114
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8115
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8116
0
    tmp = fieldname(insn, 8, 3); \
8117
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8118
0
    tmp = 0x0; \
8119
0
    tmp |= fieldname(insn, 11, 2) << 0; \
8120
0
    tmp |= fieldname(insn, 14, 1) << 2; \
8121
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8122
0
    tmp = fieldname(insn, 4, 2); \
8123
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8124
0
    return S; \
8125
0
  case 114: \
8126
0
    tmp = 0x0; \
8127
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8128
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8129
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8130
0
    tmp = fieldname(insn, 8, 3); \
8131
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8132
0
    tmp = 0x0; \
8133
0
    tmp |= fieldname(insn, 11, 2) << 0; \
8134
0
    tmp |= fieldname(insn, 14, 1) << 2; \
8135
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8136
0
    return S; \
8137
0
  case 115: \
8138
0
    tmp = fieldname(insn, 8, 3); \
8139
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8140
0
    tmp = 0x0; \
8141
0
    tmp |= fieldname(insn, 11, 2) << 0; \
8142
0
    tmp |= fieldname(insn, 14, 1) << 2; \
8143
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8144
0
    tmp = 0x0; \
8145
0
    tmp |= fieldname(insn, 4, 1) << 0; \
8146
0
    tmp |= fieldname(insn, 15, 1) << 1; \
8147
0
    tmp |= fieldname(insn, 20, 2) << 2; \
8148
0
    if (!Check(&S, decodeSelect_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8149
0
    return S; \
8150
0
  case 116: \
8151
0
    tmp = fieldname(insn, 8, 3); \
8152
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8153
0
    tmp = 0x0; \
8154
0
    tmp |= fieldname(insn, 11, 2) << 0; \
8155
0
    tmp |= fieldname(insn, 14, 1) << 2; \
8156
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8157
0
    tmp = 0x0; \
8158
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8159
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8160
0
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8161
0
    return S; \
8162
0
  case 117: \
8163
0
    tmp = 0x0; \
8164
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8165
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8166
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8167
0
    tmp = 0x0; \
8168
0
    tmp |= fieldname(insn, 5, 1) << 0; \
8169
0
    tmp |= fieldname(insn, 10, 2) << 1; \
8170
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8171
0
    return S; \
8172
0
  case 118: \
8173
0
    tmp = 0x0; \
8174
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8175
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8176
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8177
0
    tmp = fieldname(insn, 4, 4); \
8178
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8179
0
    tmp = fieldname(insn, 20, 3); \
8180
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8181
0
    tmp = fieldname(insn, 4, 4); \
8182
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8183
0
    tmp = 0x0; \
8184
0
    tmp |= fieldname(insn, 8, 4) << 0; \
8185
0
    tmp |= fieldname(insn, 26, 2) << 4; \
8186
0
    if (!Check(&S, decodeOffset_64_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8187
0
    tmp = 0x0; \
8188
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8189
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8190
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8191
0
    tmp = 0x0; \
8192
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8193
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8194
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8195
0
    tmp = fieldname(insn, 20, 3); \
8196
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8197
0
    tmp = fieldname(insn, 16, 3); \
8198
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8199
0
    return S; \
8200
0
  case 119: \
8201
0
    tmp = 0x0; \
8202
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8203
0
    tmp |= fieldname(insn, 24, 3) << 1; \
8204
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8205
0
    tmp = 0x0; \
8206
0
    tmp |= fieldname(insn, 0, 1) << 0; \
8207
0
    tmp |= fieldname(insn, 16, 3) << 1; \
8208
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8209
0
    tmp = fieldname(insn, 12, 4); \
8210
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8211
0
    tmp = fieldname(insn, 20, 4); \
8212
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8213
0
    tmp = fieldname(insn, 4, 4); \
8214
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8215
0
    tmp = fieldname(insn, 4, 4); \
8216
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8217
0
    tmp = fieldname(insn, 8, 4); \
8218
0
    if (!Check(&S, decodeOffset_16_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8219
0
    return S; \
8220
0
  case 120: \
8221
0
    tmp = 0x0; \
8222
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8223
0
    tmp |= fieldname(insn, 24, 3) << 1; \
8224
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8225
0
    tmp = 0x0; \
8226
0
    tmp |= fieldname(insn, 0, 1) << 0; \
8227
0
    tmp |= fieldname(insn, 16, 3) << 1; \
8228
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8229
0
    tmp = fieldname(insn, 12, 4); \
8230
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8231
0
    tmp = fieldname(insn, 20, 4); \
8232
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8233
0
    tmp = fieldname(insn, 4, 4); \
8234
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8235
0
    tmp = fieldname(insn, 4, 4); \
8236
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8237
0
    tmp = fieldname(insn, 8, 4); \
8238
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8239
0
    return S; \
8240
0
  case 121: \
8241
0
    tmp = fieldname(insn, 4, 4); \
8242
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8243
0
    tmp = 0x0; \
8244
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8245
0
    tmp |= fieldname(insn, 24, 3) << 1; \
8246
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8247
0
    tmp = 0x0; \
8248
0
    tmp |= fieldname(insn, 0, 1) << 0; \
8249
0
    tmp |= fieldname(insn, 16, 3) << 1; \
8250
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8251
0
    tmp = fieldname(insn, 12, 4); \
8252
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8253
0
    tmp = fieldname(insn, 20, 4); \
8254
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8255
0
    tmp = fieldname(insn, 4, 4); \
8256
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8257
0
    tmp = fieldname(insn, 8, 4); \
8258
0
    if (!Check(&S, decodeOffset_16_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8259
0
    return S; \
8260
0
  case 122: \
8261
0
    tmp = fieldname(insn, 4, 4); \
8262
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8263
0
    tmp = 0x0; \
8264
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8265
0
    tmp |= fieldname(insn, 24, 3) << 1; \
8266
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8267
0
    tmp = 0x0; \
8268
0
    tmp |= fieldname(insn, 0, 1) << 0; \
8269
0
    tmp |= fieldname(insn, 16, 3) << 1; \
8270
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8271
0
    tmp = fieldname(insn, 12, 4); \
8272
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8273
0
    tmp = fieldname(insn, 20, 4); \
8274
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8275
0
    tmp = fieldname(insn, 4, 4); \
8276
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8277
0
    tmp = fieldname(insn, 8, 4); \
8278
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8279
0
    return S; \
8280
0
  case 123: \
8281
0
    tmp = 0x0; \
8282
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8283
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8284
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8285
0
    tmp = fieldname(insn, 4, 4); \
8286
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8287
0
    tmp = fieldname(insn, 8, 4); \
8288
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8289
0
    tmp = fieldname(insn, 20, 3); \
8290
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8291
0
    tmp = fieldname(insn, 4, 4); \
8292
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8293
0
    tmp = fieldname(insn, 8, 4); \
8294
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8295
0
    tmp = fieldname(insn, 16, 3); \
8296
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8297
0
    tmp = 0x0; \
8298
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8299
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8300
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8301
0
    tmp = 0x0; \
8302
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8303
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8304
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8305
0
    tmp = fieldname(insn, 26, 1); \
8306
0
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8307
0
    return S; \
8308
0
  case 124: \
8309
0
    tmp = fieldname(insn, 4, 4); \
8310
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8311
0
    tmp = 0x0; \
8312
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8313
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8314
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8315
0
    tmp = fieldname(insn, 20, 3); \
8316
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8317
0
    tmp = fieldname(insn, 16, 3); \
8318
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8319
0
    tmp = fieldname(insn, 4, 4); \
8320
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8321
0
    tmp = fieldname(insn, 8, 4); \
8322
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8323
0
    tmp = 0x0; \
8324
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8325
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8326
0
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8327
0
    tmp = 0x0; \
8328
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8329
0
    tmp |= fieldname(insn, 24, 1) << 1; \
8330
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8331
0
    tmp = fieldname(insn, 25, 2); \
8332
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8333
0
    return S; \
8334
0
  case 125: \
8335
0
    tmp = 0x0; \
8336
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8337
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8338
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8339
0
    tmp = fieldname(insn, 4, 4); \
8340
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8341
0
    tmp = fieldname(insn, 20, 3); \
8342
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8343
0
    tmp = fieldname(insn, 4, 4); \
8344
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8345
0
    tmp = fieldname(insn, 8, 4); \
8346
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8347
0
    tmp = 0x0; \
8348
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8349
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8350
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8351
0
    tmp = 0x0; \
8352
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8353
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8354
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8355
0
    tmp = fieldname(insn, 20, 3); \
8356
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8357
0
    tmp = fieldname(insn, 16, 3); \
8358
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8359
0
    return S; \
8360
0
  case 126: \
8361
0
    tmp = fieldname(insn, 8, 3); \
8362
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8363
0
    tmp = fieldname(insn, 4, 4); \
8364
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8365
0
    tmp = 0x0; \
8366
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8367
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8368
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8369
0
    tmp = 0x0; \
8370
0
    tmp |= fieldname(insn, 11, 1) << 0; \
8371
0
    tmp |= fieldname(insn, 19, 1) << 1; \
8372
0
    tmp |= fieldname(insn, 24, 1) << 2; \
8373
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8374
0
    tmp = fieldname(insn, 4, 4); \
8375
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8376
0
    tmp = 0x0; \
8377
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8378
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8379
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8380
0
    tmp = fieldname(insn, 20, 3); \
8381
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8382
0
    tmp = fieldname(insn, 16, 3); \
8383
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8384
0
    tmp = fieldname(insn, 25, 1); \
8385
0
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8386
0
    return S; \
8387
0
  case 127: \
8388
0
    tmp = 0x0; \
8389
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8390
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8391
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8392
0
    tmp = fieldname(insn, 4, 4); \
8393
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8394
0
    tmp = fieldname(insn, 16, 3); \
8395
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8396
0
    tmp = fieldname(insn, 4, 4); \
8397
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8398
0
    tmp = fieldname(insn, 8, 4); \
8399
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8400
0
    tmp = 0x0; \
8401
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8402
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8403
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8404
0
    tmp = fieldname(insn, 20, 3); \
8405
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8406
0
    tmp = 0x0; \
8407
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8408
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8409
0
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8410
0
    return S; \
8411
0
  case 128: \
8412
0
    tmp = fieldname(insn, 16, 3); \
8413
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8414
0
    tmp = fieldname(insn, 4, 4); \
8415
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8416
0
    tmp = 0x0; \
8417
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8418
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8419
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8420
0
    tmp = fieldname(insn, 4, 4); \
8421
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8422
0
    tmp = 0x0; \
8423
0
    tmp |= fieldname(insn, 8, 2) << 0; \
8424
0
    tmp |= fieldname(insn, 12, 2) << 3; \
8425
0
    tmp |= fieldname(insn, 19, 1) << 5; \
8426
0
    tmp |= fieldname(insn, 23, 1) << 2; \
8427
0
    tmp |= fieldname(insn, 24, 2) << 6; \
8428
0
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8429
0
    tmp = 0x0; \
8430
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8431
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8432
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8433
0
    tmp = fieldname(insn, 20, 3); \
8434
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8435
0
    return S; \
8436
0
  case 129: \
8437
0
    tmp = fieldname(insn, 12, 4); \
8438
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8439
0
    tmp = fieldname(insn, 20, 4); \
8440
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8441
0
    tmp = fieldname(insn, 4, 4); \
8442
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8443
0
    tmp = fieldname(insn, 4, 4); \
8444
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8445
0
    tmp = 0x0; \
8446
0
    tmp |= fieldname(insn, 0, 1) << 1; \
8447
0
    tmp |= fieldname(insn, 8, 1) << 0; \
8448
0
    tmp |= fieldname(insn, 16, 4) << 2; \
8449
0
    tmp |= fieldname(insn, 24, 2) << 6; \
8450
0
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8451
0
    return S; \
8452
0
  case 130: \
8453
0
    tmp = fieldname(insn, 4, 4); \
8454
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8455
0
    tmp = fieldname(insn, 12, 4); \
8456
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8457
0
    tmp = fieldname(insn, 20, 4); \
8458
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8459
0
    tmp = fieldname(insn, 4, 4); \
8460
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8461
0
    tmp = 0x0; \
8462
0
    tmp |= fieldname(insn, 0, 1) << 1; \
8463
0
    tmp |= fieldname(insn, 8, 1) << 0; \
8464
0
    tmp |= fieldname(insn, 16, 4) << 2; \
8465
0
    tmp |= fieldname(insn, 24, 2) << 6; \
8466
0
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8467
0
    return S; \
8468
0
  case 131: \
8469
0
    tmp = 0x0; \
8470
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8471
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8472
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8473
0
    tmp = fieldname(insn, 4, 4); \
8474
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8475
0
    tmp = fieldname(insn, 20, 3); \
8476
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8477
0
    tmp = fieldname(insn, 4, 4); \
8478
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8479
0
    tmp = 0x0; \
8480
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8481
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8482
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8483
0
    tmp = 0x0; \
8484
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8485
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8486
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8487
0
    tmp = fieldname(insn, 20, 3); \
8488
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8489
0
    tmp = fieldname(insn, 16, 3); \
8490
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8491
0
    return S; \
8492
0
  case 132: \
8493
0
    tmp = 0x0; \
8494
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8495
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8496
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8497
0
    tmp = fieldname(insn, 4, 4); \
8498
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8499
0
    tmp = fieldname(insn, 16, 3); \
8500
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8501
0
    tmp = fieldname(insn, 4, 4); \
8502
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8503
0
    tmp = 0x0; \
8504
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8505
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8506
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8507
0
    tmp = 0x0; \
8508
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8509
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8510
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8511
0
    tmp = fieldname(insn, 8, 2); \
8512
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8513
0
    return S; \
8514
0
  case 133: \
8515
0
    tmp = 0x0; \
8516
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8517
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8518
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8519
0
    tmp = fieldname(insn, 4, 4); \
8520
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8521
0
    tmp = fieldname(insn, 16, 3); \
8522
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8523
0
    tmp = fieldname(insn, 4, 4); \
8524
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8525
0
    tmp = 0x0; \
8526
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8527
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8528
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8529
0
    tmp = 0x0; \
8530
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8531
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8532
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8533
0
    return S; \
8534
0
  case 134: \
8535
0
    tmp = 0x0; \
8536
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8537
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8538
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8539
0
    tmp = fieldname(insn, 4, 4); \
8540
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8541
0
    tmp = fieldname(insn, 4, 4); \
8542
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8543
0
    tmp = 0x0; \
8544
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8545
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8546
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8547
0
    tmp = 0x0; \
8548
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8549
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8550
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8551
0
    tmp = 0x0; \
8552
0
    tmp |= fieldname(insn, 16, 3) << 1; \
8553
0
    tmp |= fieldname(insn, 20, 1) << 0; \
8554
0
    if (!Check(&S, decodeSelect_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8555
0
    return S; \
8556
0
  case 135: \
8557
0
    tmp = 0x0; \
8558
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8559
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8560
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8561
0
    tmp = fieldname(insn, 4, 4); \
8562
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8563
0
    tmp = fieldname(insn, 4, 4); \
8564
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8565
0
    tmp = 0x0; \
8566
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8567
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8568
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8569
0
    tmp = 0x0; \
8570
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8571
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8572
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8573
0
    tmp = fieldname(insn, 16, 3); \
8574
0
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8575
0
    return S; \
8576
0
  case 136: \
8577
0
    tmp = fieldname(insn, 16, 3); \
8578
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8579
0
    tmp = 0x0; \
8580
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8581
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8582
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8583
0
    tmp = fieldname(insn, 4, 4); \
8584
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8585
0
    tmp = 0x0; \
8586
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8587
0
    tmp |= fieldname(insn, 24, 1) << 1; \
8588
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8589
0
    tmp = 0x0; \
8590
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8591
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8592
0
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8593
0
    return S; \
8594
0
  case 137: \
8595
0
    tmp = fieldname(insn, 4, 4); \
8596
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8597
0
    tmp = fieldname(insn, 16, 3); \
8598
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8599
0
    tmp = fieldname(insn, 20, 3); \
8600
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8601
0
    tmp = fieldname(insn, 4, 4); \
8602
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8603
0
    tmp = 0x0; \
8604
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8605
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8606
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8607
0
    tmp = 0x0; \
8608
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8609
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8610
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8611
0
    tmp = fieldname(insn, 8, 2); \
8612
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8613
0
    return S; \
8614
0
  case 138: \
8615
0
    tmp = fieldname(insn, 4, 4); \
8616
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8617
0
    tmp = fieldname(insn, 16, 3); \
8618
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8619
0
    tmp = fieldname(insn, 20, 3); \
8620
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8621
0
    tmp = fieldname(insn, 4, 4); \
8622
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8623
0
    tmp = 0x0; \
8624
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8625
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8626
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8627
0
    tmp = 0x0; \
8628
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8629
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8630
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8631
0
    return S; \
8632
0
  case 139: \
8633
0
    tmp = fieldname(insn, 20, 3); \
8634
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8635
0
    tmp = 0x0; \
8636
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8637
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8638
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8639
0
    tmp = fieldname(insn, 4, 4); \
8640
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8641
0
    tmp = 0x0; \
8642
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8643
0
    tmp |= fieldname(insn, 24, 1) << 1; \
8644
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8645
0
    tmp = 0x0; \
8646
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8647
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8648
0
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8649
0
    return S; \
8650
0
  case 140: \
8651
0
    tmp = fieldname(insn, 16, 3); \
8652
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8653
0
    tmp = fieldname(insn, 4, 4); \
8654
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8655
0
    tmp = 0x0; \
8656
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8657
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8658
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8659
0
    tmp = fieldname(insn, 4, 4); \
8660
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8661
0
    tmp = fieldname(insn, 8, 4); \
8662
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8663
0
    tmp = 0x0; \
8664
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8665
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8666
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8667
0
    tmp = fieldname(insn, 20, 3); \
8668
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8669
0
    return S; \
8670
0
  case 141: \
8671
0
    tmp = fieldname(insn, 16, 3); \
8672
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8673
0
    tmp = fieldname(insn, 4, 4); \
8674
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8675
0
    tmp = 0x0; \
8676
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8677
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8678
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8679
0
    tmp = fieldname(insn, 20, 3); \
8680
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8681
0
    tmp = fieldname(insn, 4, 4); \
8682
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8683
0
    tmp = 0x0; \
8684
0
    tmp |= fieldname(insn, 12, 1) << 1; \
8685
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8686
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8687
0
    return S; \
8688
0
  case 142: \
8689
0
    tmp = 0x0; \
8690
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8691
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8692
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8693
0
    tmp = fieldname(insn, 4, 4); \
8694
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8695
0
    tmp = fieldname(insn, 4, 4); \
8696
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8697
0
    tmp = 0x0; \
8698
0
    tmp |= fieldname(insn, 8, 4) << 0; \
8699
0
    tmp |= fieldname(insn, 26, 2) << 4; \
8700
0
    if (!Check(&S, decodeOffset_64_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8701
0
    tmp = 0x0; \
8702
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8703
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8704
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8705
0
    tmp = 0x0; \
8706
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8707
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8708
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8709
0
    return S; \
8710
0
  case 143: \
8711
0
    tmp = 0x0; \
8712
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8713
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8714
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8715
0
    tmp = fieldname(insn, 4, 4); \
8716
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8717
0
    tmp = fieldname(insn, 4, 4); \
8718
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8719
0
    tmp = fieldname(insn, 8, 4); \
8720
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8721
0
    tmp = 0x0; \
8722
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8723
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8724
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8725
0
    tmp = 0x0; \
8726
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8727
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8728
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8729
0
    return S; \
8730
0
  case 144: \
8731
0
    tmp = fieldname(insn, 12, 4); \
8732
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8733
0
    tmp = fieldname(insn, 4, 4); \
8734
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8735
0
    tmp = fieldname(insn, 8, 4); \
8736
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8737
0
    return S; \
8738
0
  case 145: \
8739
0
    tmp = fieldname(insn, 8, 4); \
8740
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8741
0
    tmp = fieldname(insn, 4, 4); \
8742
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8743
0
    tmp = fieldname(insn, 12, 4); \
8744
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8745
0
    tmp = fieldname(insn, 8, 4); \
8746
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8747
0
    return S; \
8748
0
  case 146: \
8749
0
    tmp = fieldname(insn, 12, 4); \
8750
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8751
0
    tmp = fieldname(insn, 8, 4); \
8752
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8753
0
    tmp = fieldname(insn, 4, 4); \
8754
0
    MCOperand_CreateImm0(MI, tmp); \
8755
0
    return S; \
8756
0
  case 147: \
8757
0
    tmp = fieldname(insn, 8, 4); \
8758
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8759
0
    tmp = fieldname(insn, 12, 4); \
8760
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8761
0
    tmp = fieldname(insn, 8, 4); \
8762
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8763
0
    tmp = fieldname(insn, 4, 4); \
8764
0
    MCOperand_CreateImm0(MI, tmp); \
8765
0
    return S; \
8766
0
  case 148: \
8767
0
    tmp = fieldname(insn, 8, 4); \
8768
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8769
0
    tmp = fieldname(insn, 12, 4); \
8770
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8771
0
    tmp = fieldname(insn, 8, 4); \
8772
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8773
0
    tmp = fieldname(insn, 4, 4); \
8774
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8775
0
    return S; \
8776
0
  case 149: \
8777
0
    tmp = fieldname(insn, 12, 4); \
8778
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8779
0
    tmp = fieldname(insn, 4, 4); \
8780
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8781
0
    tmp = fieldname(insn, 8, 4); \
8782
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8783
0
    return S; \
8784
0
  case 150: \
8785
0
    tmp = fieldname(insn, 12, 4); \
8786
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8787
0
    tmp = fieldname(insn, 4, 2); \
8788
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8789
0
    tmp = fieldname(insn, 8, 4); \
8790
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8791
0
    tmp = fieldname(insn, 4, 2); \
8792
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8793
0
    tmp = fieldname(insn, 8, 4); \
8794
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8795
0
    return S; \
8796
0
  case 151: \
8797
0
    tmp = fieldname(insn, 4, 2); \
8798
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8799
0
    tmp = fieldname(insn, 8, 4); \
8800
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8801
0
    tmp = fieldname(insn, 12, 4); \
8802
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8803
0
    tmp = fieldname(insn, 4, 2); \
8804
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8805
0
    tmp = fieldname(insn, 8, 4); \
8806
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8807
0
    return S; \
8808
0
  case 152: \
8809
0
    tmp = fieldname(insn, 12, 4); \
8810
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8811
0
    tmp = fieldname(insn, 4, 4); \
8812
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8813
0
    tmp = fieldname(insn, 8, 4); \
8814
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8815
0
    return S; \
8816
0
  case 153: \
8817
0
    tmp = fieldname(insn, 12, 4); \
8818
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8819
0
    tmp = fieldname(insn, 8, 4); \
8820
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8821
0
    tmp = fieldname(insn, 4, 4); \
8822
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8823
0
    return S; \
8824
0
  case 154: \
8825
0
    tmp = fieldname(insn, 12, 4); \
8826
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8827
0
    tmp = fieldname(insn, 8, 4); \
8828
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8829
0
    tmp = fieldname(insn, 4, 4); \
8830
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8831
0
    return S; \
8832
0
  case 155: \
8833
0
    tmp = fieldname(insn, 12, 4); \
8834
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8835
0
    tmp = fieldname(insn, 8, 4); \
8836
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8837
0
    tmp = fieldname(insn, 4, 4); \
8838
0
    if (!Check(&S, decodeImm7_22Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8839
0
    return S; \
8840
0
  case 156: \
8841
0
    tmp = fieldname(insn, 12, 4); \
8842
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8843
0
    tmp = fieldname(insn, 8, 4); \
8844
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8845
0
    return S; \
8846
0
  case 157: \
8847
0
    tmp = fieldname(insn, 12, 4); \
8848
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8849
0
    tmp = fieldname(insn, 4, 4); \
8850
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8851
0
    return S; \
8852
0
  case 158: \
8853
0
    tmp = fieldname(insn, 12, 4); \
8854
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8855
0
    tmp = fieldname(insn, 8, 4); \
8856
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8857
0
    return S; \
8858
0
  case 159: \
8859
0
    tmp = fieldname(insn, 12, 4); \
8860
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8861
0
    tmp = fieldname(insn, 12, 4); \
8862
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8863
0
    tmp = fieldname(insn, 4, 4); \
8864
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8865
0
    tmp = fieldname(insn, 10, 2); \
8866
0
    MCOperand_CreateImm0(MI, tmp); \
8867
0
    return S; \
8868
0
  case 160: \
8869
0
    tmp = fieldname(insn, 6, 2); \
8870
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8871
0
    tmp = fieldname(insn, 4, 2); \
8872
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8873
0
    return S; \
8874
0
  case 161: \
8875
0
    tmp = fieldname(insn, 6, 2); \
8876
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8877
0
    return S; \
8878
0
  case 162: \
8879
0
    tmp = fieldname(insn, 12, 4); \
8880
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8881
0
    tmp = fieldname(insn, 12, 4); \
8882
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8883
0
    tmp = fieldname(insn, 4, 4); \
8884
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8885
0
    return S; \
8886
0
  case 163: \
8887
0
    tmp = fieldname(insn, 12, 4); \
8888
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8889
0
    tmp = fieldname(insn, 8, 4); \
8890
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8891
0
    tmp = fieldname(insn, 8, 4); \
8892
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8893
0
    tmp = fieldname(insn, 4, 3); \
8894
0
    MCOperand_CreateImm0(MI, tmp); \
8895
0
    return S; \
8896
0
  case 164: \
8897
0
    tmp = fieldname(insn, 12, 4); \
8898
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8899
0
    tmp = fieldname(insn, 12, 4); \
8900
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8901
0
    tmp = fieldname(insn, 8, 4); \
8902
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8903
0
    tmp = fieldname(insn, 5, 3); \
8904
0
    if (!Check(&S, DecodeBR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8905
0
    return S; \
8906
0
  case 165: \
8907
0
    tmp = fieldname(insn, 12, 4); \
8908
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8909
0
    tmp = fieldname(insn, 8, 4); \
8910
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8911
0
    return S; \
8912
0
  case 166: \
8913
0
    tmp = fieldname(insn, 12, 4); \
8914
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8915
0
    tmp = fieldname(insn, 8, 4); \
8916
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8917
0
    tmp = fieldname(insn, 8, 4); \
8918
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8919
0
    return S; \
8920
0
  case 167: \
8921
0
    tmp = fieldname(insn, 12, 4); \
8922
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8923
0
    tmp = 0x0; \
8924
0
    tmp |= fieldname(insn, 4, 2) << 0; \
8925
0
    tmp |= fieldname(insn, 8, 4) << 2; \
8926
0
    MCOperand_CreateImm0(MI, tmp); \
8927
0
    return S; \
8928
0
  case 168: \
8929
0
    tmp = fieldname(insn, 12, 4); \
8930
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8931
0
    tmp = fieldname(insn, 4, 4); \
8932
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8933
0
    tmp = fieldname(insn, 8, 4); \
8934
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8935
0
    return S; \
8936
0
  case 169: \
8937
0
    tmp = fieldname(insn, 12, 4); \
8938
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8939
0
    tmp = fieldname(insn, 8, 4); \
8940
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8941
0
    tmp = fieldname(insn, 8, 4); \
8942
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8943
0
    tmp = fieldname(insn, 4, 4); \
8944
0
    MCOperand_CreateImm0(MI, tmp); \
8945
0
    return S; \
8946
0
  case 170: \
8947
0
    tmp = fieldname(insn, 12, 4); \
8948
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8949
0
    tmp = fieldname(insn, 8, 4); \
8950
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8951
0
    tmp = fieldname(insn, 4, 4); \
8952
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8953
0
    return S; \
8954
0
  case 171: \
8955
0
    tmp = fieldname(insn, 13, 3); \
8956
0
    if (!Check(&S, DecodeBR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8957
0
    tmp = fieldname(insn, 8, 4); \
8958
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8959
0
    tmp = fieldname(insn, 4, 4); \
8960
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8961
0
    return S; \
8962
0
  case 172: \
8963
0
    tmp = fieldname(insn, 8, 4); \
8964
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8965
0
    tmp = fieldname(insn, 8, 4); \
8966
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8967
0
    tmp = fieldname(insn, 4, 4); \
8968
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8969
0
    tmp = fieldname(insn, 12, 4); \
8970
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8971
0
    return S; \
8972
0
  case 173: \
8973
0
    tmp = fieldname(insn, 12, 4); \
8974
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8975
0
    tmp = fieldname(insn, 12, 4); \
8976
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8977
0
    tmp = fieldname(insn, 8, 4); \
8978
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8979
0
    tmp = fieldname(insn, 4, 4); \
8980
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8981
0
    return S; \
8982
0
  case 174: \
8983
0
    tmp = fieldname(insn, 8, 4); \
8984
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8985
0
    tmp = fieldname(insn, 12, 4); \
8986
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8987
0
    tmp = fieldname(insn, 8, 4); \
8988
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8989
0
    tmp = fieldname(insn, 4, 3); \
8990
0
    MCOperand_CreateImm0(MI, tmp); \
8991
0
    return S; \
8992
0
  case 175: \
8993
0
    tmp = fieldname(insn, 12, 4); \
8994
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8995
0
    tmp = fieldname(insn, 4, 4); \
8996
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8997
0
    return S; \
8998
0
  case 176: \
8999
0
    tmp = fieldname(insn, 4, 2); \
9000
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9001
0
    tmp = fieldname(insn, 8, 4); \
9002
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9003
0
    tmp = fieldname(insn, 8, 4); \
9004
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9005
0
    return S; \
9006
0
  case 177: \
9007
0
    tmp = fieldname(insn, 4, 2); \
9008
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9009
0
    tmp = fieldname(insn, 8, 4); \
9010
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9011
0
    return S; \
9012
0
  case 178: \
9013
0
    tmp = fieldname(insn, 4, 2); \
9014
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9015
0
    tmp = fieldname(insn, 4, 2); \
9016
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9017
0
    tmp = fieldname(insn, 8, 4); \
9018
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9019
0
    return S; \
9020
0
  case 179: \
9021
0
    tmp = fieldname(insn, 8, 4); \
9022
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9023
0
    tmp = fieldname(insn, 8, 4); \
9024
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9025
0
    tmp = fieldname(insn, 4, 4); \
9026
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9027
0
    return S; \
9028
0
  case 180: \
9029
0
    tmp = fieldname(insn, 8, 4); \
9030
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9031
0
    tmp = fieldname(insn, 8, 4); \
9032
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9033
0
    tmp = fieldname(insn, 4, 4); \
9034
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9035
0
    return S; \
9036
0
  case 181: \
9037
0
    tmp = fieldname(insn, 8, 4); \
9038
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9039
0
    tmp = fieldname(insn, 8, 4); \
9040
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9041
0
    return S; \
9042
0
  case 182: \
9043
0
    tmp = fieldname(insn, 12, 4); \
9044
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9045
0
    tmp = fieldname(insn, 4, 4); \
9046
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9047
0
    tmp = 0x0; \
9048
0
    tmp |= fieldname(insn, 8, 4) << 0; \
9049
0
    tmp |= fieldname(insn, 16, 2) << 4; \
9050
0
    MCOperand_CreateImm0(MI, tmp); \
9051
0
    return S; \
9052
0
  case 183: \
9053
0
    tmp = fieldname(insn, 12, 4); \
9054
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9055
0
    tmp = fieldname(insn, 4, 4); \
9056
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9057
0
    tmp = 0x0; \
9058
0
    tmp |= fieldname(insn, 8, 4) << 0; \
9059
0
    tmp |= fieldname(insn, 16, 1) << 4; \
9060
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9061
0
    return S; \
9062
0
  case 184: \
9063
0
    tmp = fieldname(insn, 12, 4); \
9064
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9065
0
    tmp = fieldname(insn, 8, 4); \
9066
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9067
0
    tmp = fieldname(insn, 4, 4); \
9068
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9069
0
    tmp = fieldname(insn, 16, 4); \
9070
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9071
0
    return S; \
9072
0
  case 185: \
9073
0
    tmp = fieldname(insn, 12, 4); \
9074
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9075
0
    tmp = fieldname(insn, 8, 4); \
9076
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9077
0
    tmp = fieldname(insn, 8, 4); \
9078
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9079
0
    tmp = fieldname(insn, 4, 4); \
9080
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9081
0
    return S; \
9082
0
  case 186: \
9083
0
    tmp = fieldname(insn, 12, 4); \
9084
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9085
0
    tmp = fieldname(insn, 8, 4); \
9086
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9087
0
    tmp = fieldname(insn, 4, 4); \
9088
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9089
0
    return S; \
9090
0
  case 187: \
9091
0
    tmp = fieldname(insn, 12, 4); \
9092
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9093
0
    tmp = fieldname(insn, 4, 4); \
9094
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9095
0
    tmp = fieldname(insn, 4, 4); \
9096
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9097
0
    tmp = fieldname(insn, 8, 4); \
9098
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9099
0
    return S; \
9100
0
  case 188: \
9101
0
    tmp = fieldname(insn, 12, 4); \
9102
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9103
0
    tmp = fieldname(insn, 4, 4); \
9104
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9105
0
    tmp = fieldname(insn, 16, 4); \
9106
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9107
0
    tmp = fieldname(insn, 8, 4); \
9108
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9109
0
    return S; \
9110
0
  case 189: \
9111
0
    tmp = fieldname(insn, 16, 4); \
9112
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9113
0
    tmp = fieldname(insn, 20, 4); \
9114
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9115
0
    tmp = fieldname(insn, 24, 4); \
9116
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9117
0
    return S; \
9118
0
  case 190: \
9119
0
    tmp = fieldname(insn, 16, 4); \
9120
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9121
0
    tmp = fieldname(insn, 16, 4); \
9122
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9123
0
    tmp = fieldname(insn, 20, 4); \
9124
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9125
0
    tmp = fieldname(insn, 24, 4); \
9126
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9127
0
    return S; \
9128
0
  case 191: \
9129
0
    tmp = fieldname(insn, 16, 4); \
9130
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9131
0
    tmp = fieldname(insn, 16, 4); \
9132
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9133
0
    tmp = fieldname(insn, 24, 4); \
9134
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9135
0
    tmp = fieldname(insn, 20, 4); \
9136
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9137
0
    return S; \
9138
0
  case 192: \
9139
0
    tmp = fieldname(insn, 16, 4); \
9140
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9141
0
    tmp = fieldname(insn, 24, 4); \
9142
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9143
0
    tmp = fieldname(insn, 20, 4); \
9144
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9145
0
    return S; \
9146
0
  case 193: \
9147
0
    tmp = fieldname(insn, 6, 2); \
9148
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9149
0
    tmp = fieldname(insn, 8, 4); \
9150
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9151
0
    tmp = fieldname(insn, 12, 4); \
9152
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9153
0
    tmp = fieldname(insn, 6, 2); \
9154
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9155
0
    tmp = fieldname(insn, 8, 4); \
9156
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9157
0
    return S; \
9158
0
  case 194: \
9159
0
    tmp = fieldname(insn, 12, 4); \
9160
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9161
0
    tmp = fieldname(insn, 6, 2); \
9162
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9163
0
    tmp = fieldname(insn, 8, 4); \
9164
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9165
0
    tmp = fieldname(insn, 6, 2); \
9166
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9167
0
    tmp = fieldname(insn, 8, 4); \
9168
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9169
0
    return S; \
9170
0
  case 195: \
9171
0
    tmp = fieldname(insn, 8, 4); \
9172
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9173
0
    tmp = fieldname(insn, 12, 4); \
9174
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9175
0
    tmp = fieldname(insn, 8, 4); \
9176
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9177
0
    return S; \
9178
0
  case 196: \
9179
0
    tmp = fieldname(insn, 6, 2); \
9180
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9181
0
    tmp = fieldname(insn, 8, 4); \
9182
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9183
0
    tmp = fieldname(insn, 8, 4); \
9184
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9185
0
    return S; \
9186
0
  case 197: \
9187
0
    tmp = fieldname(insn, 6, 2); \
9188
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9189
0
    tmp = fieldname(insn, 6, 2); \
9190
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9191
0
    tmp = fieldname(insn, 8, 4); \
9192
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9193
0
    return S; \
9194
0
  case 198: \
9195
0
    tmp = fieldname(insn, 6, 2); \
9196
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9197
0
    tmp = fieldname(insn, 8, 4); \
9198
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9199
0
    tmp = 0x0; \
9200
0
    tmp |= fieldname(insn, 4, 2) << 0; \
9201
0
    tmp |= fieldname(insn, 28, 2) << 2; \
9202
0
    MCOperand_CreateImm0(MI, tmp); \
9203
0
    return S; \
9204
0
  case 199: \
9205
0
    tmp = fieldname(insn, 12, 4); \
9206
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9207
0
    tmp = fieldname(insn, 4, 4); \
9208
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9209
0
    return S; \
9210
0
  case 200: \
9211
0
    tmp = fieldname(insn, 20, 4); \
9212
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9213
0
    tmp = fieldname(insn, 24, 4); \
9214
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9215
0
    tmp = fieldname(insn, 16, 4); \
9216
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9217
0
    return S; \
9218
0
  case 201: \
9219
0
    tmp = fieldname(insn, 20, 4); \
9220
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9221
0
    tmp = fieldname(insn, 16, 4); \
9222
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9223
0
    return S; \
9224
0
  case 202: \
9225
0
    tmp = fieldname(insn, 16, 4); \
9226
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9227
0
    tmp = fieldname(insn, 20, 4); \
9228
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9229
0
    tmp = fieldname(insn, 16, 4); \
9230
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9231
0
    tmp = fieldname(insn, 20, 4); \
9232
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9233
0
    tmp = fieldname(insn, 24, 4); \
9234
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9235
0
    tmp = fieldname(insn, 32, 4); \
9236
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9237
0
    tmp = fieldname(insn, 36, 4); \
9238
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9239
0
    return S; \
9240
0
  case 203: \
9241
0
    tmp = fieldname(insn, 16, 4); \
9242
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9243
0
    tmp = fieldname(insn, 24, 4); \
9244
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9245
0
    tmp = fieldname(insn, 32, 4); \
9246
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9247
0
    tmp = fieldname(insn, 48, 2); \
9248
0
    MCOperand_CreateImm0(MI, tmp); \
9249
0
    return S; \
9250
0
  case 204: \
9251
0
    tmp = fieldname(insn, 16, 4); \
9252
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9253
0
    tmp = fieldname(insn, 16, 4); \
9254
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9255
0
    tmp = fieldname(insn, 24, 4); \
9256
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9257
0
    tmp = fieldname(insn, 32, 4); \
9258
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9259
0
    return S; \
9260
0
  case 205: \
9261
0
    tmp = fieldname(insn, 16, 4); \
9262
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9263
0
    tmp = fieldname(insn, 24, 4); \
9264
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9265
0
    tmp = fieldname(insn, 32, 4); \
9266
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9267
0
    return S; \
9268
0
  case 206: \
9269
0
    tmp = fieldname(insn, 28, 4); \
9270
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9271
0
    tmp = fieldname(insn, 4, 4); \
9272
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9273
0
    tmp = fieldname(insn, 12, 4); \
9274
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9275
0
    tmp = fieldname(insn, 8, 4); \
9276
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9277
0
    return S; \
9278
0
  case 207: \
9279
0
    tmp = fieldname(insn, 28, 4); \
9280
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9281
0
    tmp = fieldname(insn, 4, 4); \
9282
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9283
0
    tmp = fieldname(insn, 12, 4); \
9284
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9285
0
    tmp = fieldname(insn, 8, 4); \
9286
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9287
0
    return S; \
9288
0
  case 208: \
9289
0
    tmp = fieldname(insn, 28, 4); \
9290
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9291
0
    tmp = fieldname(insn, 4, 4); \
9292
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9293
0
    tmp = fieldname(insn, 8, 4); \
9294
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9295
0
    return S; \
9296
0
  case 209: \
9297
0
    tmp = fieldname(insn, 16, 4); \
9298
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9299
0
    tmp = fieldname(insn, 32, 4); \
9300
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9301
0
    return S; \
9302
0
  case 210: \
9303
0
    tmp = fieldname(insn, 16, 4); \
9304
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9305
0
    tmp = fieldname(insn, 20, 4); \
9306
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9307
0
    tmp = fieldname(insn, 24, 4); \
9308
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9309
0
    tmp = fieldname(insn, 32, 4); \
9310
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9311
0
    tmp = fieldname(insn, 36, 4); \
9312
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9313
0
    return S; \
9314
0
  case 211: \
9315
0
    tmp = fieldname(insn, 20, 4); \
9316
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9317
0
    tmp = fieldname(insn, 28, 4); \
9318
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9319
0
    tmp = 0x0; \
9320
0
    tmp |= fieldname(insn, 36, 4) << 0; \
9321
0
    tmp |= fieldname(insn, 56, 2) << 4; \
9322
0
    MCOperand_CreateImm0(MI, tmp); \
9323
0
    return S; \
9324
0
  case 212: \
9325
0
    tmp = fieldname(insn, 20, 4); \
9326
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9327
0
    tmp = fieldname(insn, 16, 4); \
9328
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9329
0
    tmp = fieldname(insn, 32, 4); \
9330
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9331
0
    tmp = fieldname(insn, 24, 4); \
9332
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9333
0
    return S; \
9334
0
  case 213: \
9335
0
    tmp = fieldname(insn, 20, 4); \
9336
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9337
0
    tmp = fieldname(insn, 16, 4); \
9338
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9339
0
    tmp = fieldname(insn, 20, 4); \
9340
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9341
0
    tmp = fieldname(insn, 16, 4); \
9342
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9343
0
    tmp = fieldname(insn, 32, 4); \
9344
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9345
0
    tmp = fieldname(insn, 24, 4); \
9346
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9347
0
    return S; \
9348
0
  case 214: \
9349
0
    tmp = fieldname(insn, 20, 4); \
9350
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9351
0
    tmp = fieldname(insn, 28, 4); \
9352
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9353
0
    tmp = 0x0; \
9354
0
    tmp |= fieldname(insn, 36, 4) << 0; \
9355
0
    tmp |= fieldname(insn, 56, 1) << 4; \
9356
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9357
0
    return S; \
9358
0
  case 215: \
9359
0
    tmp = fieldname(insn, 20, 4); \
9360
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9361
0
    tmp = fieldname(insn, 36, 4); \
9362
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9363
0
    tmp = fieldname(insn, 28, 4); \
9364
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9365
0
    return S; \
9366
0
  case 216: \
9367
0
    tmp = fieldname(insn, 20, 4); \
9368
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9369
0
    tmp = fieldname(insn, 20, 4); \
9370
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9371
0
    tmp = fieldname(insn, 36, 4); \
9372
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9373
0
    tmp = fieldname(insn, 28, 4); \
9374
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9375
0
    return S; \
9376
0
  case 217: \
9377
0
    tmp = fieldname(insn, 20, 4); \
9378
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9379
0
    tmp = fieldname(insn, 28, 4); \
9380
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9381
0
    tmp = fieldname(insn, 36, 4); \
9382
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9383
0
    return S; \
9384
0
  case 218: \
9385
0
    tmp = fieldname(insn, 20, 4); \
9386
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9387
0
    tmp = fieldname(insn, 36, 4); \
9388
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9389
0
    tmp = fieldname(insn, 28, 4); \
9390
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9391
0
    return S; \
9392
0
  case 219: \
9393
0
    tmp = fieldname(insn, 20, 4); \
9394
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9395
0
    tmp = fieldname(insn, 20, 4); \
9396
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9397
0
    tmp = fieldname(insn, 36, 4); \
9398
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9399
0
    tmp = fieldname(insn, 28, 4); \
9400
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9401
0
    return S; \
9402
0
  case 220: \
9403
0
    tmp = fieldname(insn, 21, 3); \
9404
0
    if (!Check(&S, DecodeBR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9405
0
    tmp = fieldname(insn, 36, 4); \
9406
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9407
0
    tmp = fieldname(insn, 28, 4); \
9408
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9409
0
    return S; \
9410
0
  case 221: \
9411
0
    tmp = fieldname(insn, 22, 2); \
9412
0
    if (!Check(&S, DecodeBR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9413
0
    tmp = fieldname(insn, 36, 4); \
9414
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9415
0
    tmp = fieldname(insn, 28, 4); \
9416
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9417
0
    return S; \
9418
0
  case 222: \
9419
0
    tmp = fieldname(insn, 20, 4); \
9420
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9421
0
    tmp = fieldname(insn, 20, 4); \
9422
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9423
0
    tmp = fieldname(insn, 36, 4); \
9424
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9425
0
    tmp = fieldname(insn, 30, 2); \
9426
0
    if (!Check(&S, DecodeBR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9427
0
    return S; \
9428
0
  case 223: \
9429
0
    tmp = fieldname(insn, 20, 4); \
9430
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9431
0
    tmp = fieldname(insn, 20, 4); \
9432
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9433
0
    tmp = fieldname(insn, 36, 4); \
9434
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9435
0
    return S; \
9436
0
  case 224: \
9437
0
    tmp = fieldname(insn, 20, 4); \
9438
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9439
0
    tmp = fieldname(insn, 36, 4); \
9440
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9441
0
    return S; \
9442
0
  case 225: \
9443
0
    tmp = fieldname(insn, 20, 4); \
9444
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9445
0
    tmp = fieldname(insn, 28, 4); \
9446
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9447
0
    return S; \
9448
0
  case 226: \
9449
0
    tmp = fieldname(insn, 20, 4); \
9450
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9451
0
    tmp = fieldname(insn, 28, 4); \
9452
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9453
0
    tmp = fieldname(insn, 36, 4); \
9454
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9455
0
    return S; \
9456
14.4k
  } \
9457
14.4k
}
XtensaDisassembler.c:decodeToMCInst_3
Line
Count
Source
7098
35.0k
    uint64_t Address, const void *Decoder, bool *DecodeComplete) \
7099
35.0k
{ \
7100
35.0k
  *DecodeComplete = true; \
7101
35.0k
  InsnType tmp; \
7102
35.0k
  switch (Idx) { \
7103
0
  default: CS_ASSERT_RET_VAL(0 && "Invalid index!", MCDisassembler_Fail); \
7104
0
  case 0: \
7105
0
    tmp = fieldname(insn, 4, 4); \
7106
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7107
0
    tmp = fieldname(insn, 8, 8); \
7108
0
    if (!Check(&S, decodeMem32nOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7109
0
    return S; \
7110
1.28k
  case 1: \
7111
1.28k
    tmp = fieldname(insn, 12, 4); \
7112
1.28k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7113
1.28k
    tmp = fieldname(insn, 8, 4); \
7114
1.28k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7115
1.28k
    tmp = fieldname(insn, 4, 4); \
7116
1.28k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7117
1.28k
    return S; \
7118
1.28k
  case 2: \
7119
0
    tmp = fieldname(insn, 12, 4); \
7120
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7121
0
    tmp = fieldname(insn, 8, 4); \
7122
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7123
0
    tmp = fieldname(insn, 4, 4); \
7124
0
    if (!Check(&S, decodeImm1n_15Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7125
0
    return S; \
7126
152
  case 3: \
7127
152
    tmp = fieldname(insn, 8, 4); \
7128
152
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7129
152
    return S; \
7130
152
  case 4: \
7131
0
    tmp = fieldname(insn, 8, 4); \
7132
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7133
0
    tmp = 0x0; \
7134
0
    tmp |= fieldname(insn, 4, 3) << 4; \
7135
0
    tmp |= fieldname(insn, 12, 4) << 0; \
7136
0
    if (!Check(&S, decodeImm32n_95Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7137
0
    return S; \
7138
181
  case 5: \
7139
181
    tmp = fieldname(insn, 4, 4); \
7140
181
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7141
181
    tmp = fieldname(insn, 8, 4); \
7142
181
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7143
181
    return S; \
7144
2.44k
  case 6: \
7145
2.44k
    return S; \
7146
181
  case 7: \
7147
69
    tmp = fieldname(insn, 8, 4); \
7148
69
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7149
69
    return S; \
7150
102
  case 8: \
7151
102
    tmp = fieldname(insn, 8, 4); \
7152
102
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7153
102
    tmp = fieldname(insn, 4, 4); \
7154
102
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7155
102
    return S; \
7156
193
  case 9: \
7157
193
    tmp = fieldname(insn, 4, 4); \
7158
193
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7159
193
    tmp = fieldname(insn, 8, 4); \
7160
193
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7161
193
    return S; \
7162
218
  case 10: \
7163
218
    tmp = fieldname(insn, 4, 4); \
7164
218
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7165
218
    tmp = fieldname(insn, 8, 4); \
7166
218
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7167
218
    return S; \
7168
218
  case 11: \
7169
188
    tmp = fieldname(insn, 12, 4); \
7170
188
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7171
188
    tmp = fieldname(insn, 8, 4); \
7172
188
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7173
188
    tmp = 0x0; \
7174
188
    tmp |= fieldname(insn, 4, 4) << 0; \
7175
188
    tmp |= fieldname(insn, 20, 1) << 4; \
7176
188
    if (!Check(&S, decodeShimm1_31Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7177
188
    return S; \
7178
188
  case 12: \
7179
93
    tmp = fieldname(insn, 12, 4); \
7180
93
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7181
93
    tmp = fieldname(insn, 4, 4); \
7182
93
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7183
93
    tmp = 0x0; \
7184
93
    tmp |= fieldname(insn, 8, 4) << 0; \
7185
93
    tmp |= fieldname(insn, 20, 1) << 4; \
7186
93
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7187
93
    return S; \
7188
93
  case 13: \
7189
10
    tmp = 0x0; \
7190
10
    tmp |= fieldname(insn, 4, 1) << 4; \
7191
10
    tmp |= fieldname(insn, 8, 4) << 0; \
7192
10
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7193
10
    return S; \
7194
24
  case 14: \
7195
24
    tmp = fieldname(insn, 4, 4); \
7196
24
    if (!Check(&S, decodeImm8n_7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7197
24
    return S; \
7198
64
  case 15: \
7199
64
    tmp = fieldname(insn, 12, 4); \
7200
64
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7201
64
    tmp = fieldname(insn, 4, 4); \
7202
64
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7203
64
    tmp = fieldname(insn, 8, 4); \
7204
64
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7205
64
    return S; \
7206
286
  case 16: \
7207
286
    tmp = fieldname(insn, 12, 4); \
7208
286
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7209
286
    tmp = fieldname(insn, 4, 4); \
7210
286
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7211
286
    return S; \
7212
1.03k
  case 17: \
7213
1.03k
    tmp = fieldname(insn, 4, 4); \
7214
1.03k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7215
1.03k
    tmp = fieldname(insn, 8, 8); \
7216
1.03k
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7217
1.03k
    tmp = fieldname(insn, 4, 4); \
7218
1.02k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7219
1.02k
    tmp = fieldname(insn, 8, 8); \
7220
1.02k
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7221
1.02k
    return S; \
7222
1.02k
  case 18: \
7223
10
    tmp = fieldname(insn, 12, 4); \
7224
10
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7225
10
    tmp = fieldname(insn, 8, 4); \
7226
10
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7227
10
    return S; \
7228
228
  case 19: \
7229
228
    tmp = fieldname(insn, 12, 4); \
7230
228
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7231
228
    tmp = fieldname(insn, 8, 4); \
7232
228
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7233
228
    tmp = fieldname(insn, 4, 4); \
7234
228
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7235
228
    return S; \
7236
1.17k
  case 20: \
7237
1.17k
    tmp = fieldname(insn, 4, 4); \
7238
1.17k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7239
1.17k
    tmp = fieldname(insn, 8, 8); \
7240
1.17k
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7241
1.17k
    return S; \
7242
1.17k
  case 21: \
7243
519
    tmp = fieldname(insn, 8, 8); \
7244
519
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7245
519
    tmp = fieldname(insn, 4, 4); \
7246
517
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7247
517
    return S; \
7248
517
  case 22: \
7249
44
    tmp = fieldname(insn, 12, 4); \
7250
44
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7251
44
    tmp = fieldname(insn, 8, 4); \
7252
44
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7253
44
    tmp = fieldname(insn, 4, 4); \
7254
44
    if (!Check(&S, decodeImm7_22Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7255
44
    return S; \
7256
92
  case 23: \
7257
92
    tmp = fieldname(insn, 12, 4); \
7258
92
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7259
92
    tmp = fieldname(insn, 12, 4); \
7260
92
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7261
92
    tmp = fieldname(insn, 8, 4); \
7262
92
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7263
92
    tmp = fieldname(insn, 4, 4); \
7264
92
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7265
92
    return S; \
7266
224
  case 24: \
7267
224
    tmp = fieldname(insn, 12, 4); \
7268
224
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7269
224
    tmp = fieldname(insn, 4, 8); \
7270
224
    if (!Check(&S, DecodeURRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7271
224
    return S; \
7272
224
  case 25: \
7273
133
    tmp = fieldname(insn, 4, 4); \
7274
133
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7275
133
    return S; \
7276
311
  case 26: \
7277
311
    tmp = fieldname(insn, 8, 8); \
7278
311
    if (!Check(&S, DecodeURRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7279
311
    tmp = fieldname(insn, 4, 4); \
7280
174
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7281
174
    return S; \
7282
476
  case 27: \
7283
476
    tmp = fieldname(insn, 12, 4); \
7284
476
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7285
476
    tmp = fieldname(insn, 4, 4); \
7286
476
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7287
476
    tmp = 0x0; \
7288
476
    tmp |= fieldname(insn, 8, 4) << 0; \
7289
476
    tmp |= fieldname(insn, 16, 1) << 4; \
7290
476
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7291
476
    tmp = fieldname(insn, 20, 4); \
7292
476
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7293
476
    return S; \
7294
476
  case 28: \
7295
292
    tmp = fieldname(insn, 4, 8); \
7296
292
    if (!Check(&S, decodeSelect_256Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7297
292
    return S; \
7298
292
  case 29: \
7299
93
    tmp = fieldname(insn, 8, 4); \
7300
93
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7301
93
    tmp = fieldname(insn, 4, 4); \
7302
93
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7303
93
    return S; \
7304
93
  case 30: \
7305
57
    tmp = fieldname(insn, 12, 4); \
7306
57
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7307
57
    tmp = fieldname(insn, 8, 4); \
7308
57
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7309
57
    tmp = fieldname(insn, 4, 4); \
7310
57
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7311
57
    return S; \
7312
139
  case 31: \
7313
139
    tmp = fieldname(insn, 4, 4); \
7314
139
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7315
139
    tmp = fieldname(insn, 8, 4); \
7316
139
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7317
139
    tmp = fieldname(insn, 12, 4) << 2; \
7318
139
    if (!Check(&S, decodeImm64n_4nOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7319
139
    return S; \
7320
141
  case 32: \
7321
141
    tmp = fieldname(insn, 12, 4); \
7322
141
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7323
141
    tmp = fieldname(insn, 8, 4); \
7324
141
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7325
141
    tmp = fieldname(insn, 8, 4); \
7326
141
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7327
141
    tmp = fieldname(insn, 4, 4); \
7328
141
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7329
141
    return S; \
7330
183
  case 33: \
7331
183
    tmp = fieldname(insn, 8, 4); \
7332
183
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7333
183
    tmp = fieldname(insn, 12, 4); \
7334
183
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7335
183
    tmp = fieldname(insn, 8, 4); \
7336
183
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7337
183
    tmp = fieldname(insn, 4, 4); \
7338
183
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7339
183
    return S; \
7340
183
  case 34: \
7341
153
    tmp = fieldname(insn, 12, 4); \
7342
153
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7343
153
    tmp = fieldname(insn, 8, 4); \
7344
153
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7345
153
    tmp = fieldname(insn, 4, 4); \
7346
153
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7347
153
    return S; \
7348
338
  case 35: \
7349
338
    tmp = fieldname(insn, 12, 4); \
7350
338
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7351
338
    tmp = fieldname(insn, 8, 4); \
7352
338
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7353
338
    tmp = fieldname(insn, 4, 4); \
7354
338
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7355
338
    return S; \
7356
787
  case 36: \
7357
787
    tmp = fieldname(insn, 12, 4); \
7358
787
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7359
787
    tmp = fieldname(insn, 12, 4); \
7360
787
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7361
787
    tmp = fieldname(insn, 8, 4); \
7362
787
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7363
787
    tmp = fieldname(insn, 4, 4); \
7364
787
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7365
787
    return S; \
7366
787
  case 37: \
7367
131
    tmp = fieldname(insn, 12, 4); \
7368
131
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7369
131
    tmp = fieldname(insn, 8, 4); \
7370
131
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7371
131
    tmp = fieldname(insn, 4, 4); \
7372
131
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7373
131
    return S; \
7374
131
  case 38: \
7375
53
    tmp = fieldname(insn, 12, 4); \
7376
53
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7377
53
    tmp = fieldname(insn, 12, 4); \
7378
53
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7379
53
    tmp = fieldname(insn, 8, 4); \
7380
53
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7381
53
    tmp = fieldname(insn, 4, 4); \
7382
53
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7383
53
    return S; \
7384
154
  case 39: \
7385
154
    tmp = fieldname(insn, 12, 4); \
7386
154
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7387
154
    tmp = fieldname(insn, 8, 4); \
7388
154
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7389
154
    tmp = fieldname(insn, 4, 4); \
7390
154
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7391
154
    return S; \
7392
154
  case 40: \
7393
14
    tmp = fieldname(insn, 12, 4); \
7394
14
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7395
14
    tmp = fieldname(insn, 12, 4); \
7396
14
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7397
14
    tmp = fieldname(insn, 8, 4); \
7398
14
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7399
14
    tmp = fieldname(insn, 4, 4); \
7400
14
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7401
14
    return S; \
7402
267
  case 41: \
7403
267
    tmp = fieldname(insn, 12, 4); \
7404
267
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7405
267
    tmp = fieldname(insn, 8, 4); \
7406
267
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7407
267
    return S; \
7408
267
  case 42: \
7409
16
    tmp = fieldname(insn, 12, 4); \
7410
16
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7411
16
    tmp = fieldname(insn, 8, 4); \
7412
16
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7413
16
    return S; \
7414
16
  case 43: \
7415
7
    tmp = fieldname(insn, 12, 4); \
7416
7
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7417
7
    tmp = fieldname(insn, 8, 4); \
7418
7
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7419
7
    return S; \
7420
431
  case 44: \
7421
431
    tmp = fieldname(insn, 12, 4); \
7422
431
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7423
431
    tmp = fieldname(insn, 8, 4); \
7424
431
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7425
431
    return S; \
7426
431
  case 45: \
7427
36
    tmp = fieldname(insn, 12, 4); \
7428
36
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7429
36
    tmp = fieldname(insn, 12, 4); \
7430
36
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7431
36
    tmp = fieldname(insn, 8, 4); \
7432
36
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7433
36
    return S; \
7434
3.08k
  case 46: \
7435
3.08k
    tmp = fieldname(insn, 4, 4); \
7436
3.08k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7437
3.08k
    tmp = fieldname(insn, 8, 16); \
7438
3.08k
    if (!Check(&S, decodeL32ROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7439
3.08k
    return S; \
7440
3.08k
  case 47: \
7441
1.40k
    tmp = fieldname(insn, 4, 4); \
7442
1.40k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7443
1.40k
    tmp = 0x0; \
7444
1.40k
    tmp |= fieldname(insn, 8, 4) << 0; \
7445
1.40k
    tmp |= fieldname(insn, 16, 8) << 4; \
7446
1.40k
    if (!Check(&S, decodeMem8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7447
1.40k
    return S; \
7448
1.40k
  case 48: \
7449
419
    tmp = fieldname(insn, 4, 4); \
7450
419
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7451
419
    tmp = 0x0; \
7452
419
    tmp |= fieldname(insn, 8, 4) << 0; \
7453
419
    tmp |= fieldname(insn, 16, 8) << 4; \
7454
419
    if (!Check(&S, decodeMem16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7455
419
    return S; \
7456
419
  case 49: \
7457
294
    tmp = fieldname(insn, 4, 4); \
7458
294
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7459
294
    tmp = 0x0; \
7460
294
    tmp |= fieldname(insn, 8, 4) << 0; \
7461
294
    tmp |= fieldname(insn, 16, 8) << 4; \
7462
294
    if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7463
294
    return S; \
7464
308
  case 50: \
7465
308
    tmp = fieldname(insn, 4, 4); \
7466
308
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7467
308
    tmp = 0x0; \
7468
308
    tmp |= fieldname(insn, 8, 4) << 8; \
7469
308
    tmp |= fieldname(insn, 16, 8) << 0; \
7470
308
    if (!Check(&S, decodeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7471
308
    return S; \
7472
308
  case 51: \
7473
132
    tmp = fieldname(insn, 4, 4); \
7474
132
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7475
132
    tmp = fieldname(insn, 8, 4); \
7476
132
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7477
132
    tmp = fieldname(insn, 16, 8); \
7478
132
    if (!Check(&S, decodeImm8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7479
132
    return S; \
7480
256
  case 52: \
7481
256
    tmp = fieldname(insn, 4, 4); \
7482
256
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7483
256
    tmp = fieldname(insn, 8, 4); \
7484
256
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7485
256
    tmp = fieldname(insn, 16, 8) << 8; \
7486
256
    if (!Check(&S, decodeImm8_sh8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7487
256
    return S; \
7488
457
  case 53: \
7489
457
    tmp = fieldname(insn, 4, 4); \
7490
457
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7491
457
    tmp = fieldname(insn, 4, 4); \
7492
457
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7493
457
    tmp = 0x0; \
7494
457
    tmp |= fieldname(insn, 8, 4) << 0; \
7495
457
    tmp |= fieldname(insn, 16, 8) << 4; \
7496
457
    if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7497
457
    return S; \
7498
457
  case 54: \
7499
384
    tmp = fieldname(insn, 4, 4); \
7500
384
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7501
384
    tmp = 0x0; \
7502
384
    tmp |= fieldname(insn, 8, 4) << 0; \
7503
384
    tmp |= fieldname(insn, 16, 8) << 4; \
7504
384
    if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7505
384
    return S; \
7506
384
  case 55: \
7507
341
    tmp = fieldname(insn, 4, 4); \
7508
341
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7509
341
    tmp = fieldname(insn, 8, 4); \
7510
341
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7511
341
    tmp = fieldname(insn, 8, 4); \
7512
341
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7513
341
    tmp = fieldname(insn, 16, 8) << 2; \
7514
341
    if (!Check(&S, decodeOffset8m32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7515
341
    return S; \
7516
609
  case 56: \
7517
609
    tmp = fieldname(insn, 8, 4); \
7518
609
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7519
609
    tmp = fieldname(insn, 4, 4); \
7520
609
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7521
609
    tmp = fieldname(insn, 8, 4); \
7522
609
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7523
609
    tmp = fieldname(insn, 16, 8) << 2; \
7524
609
    if (!Check(&S, decodeOffset8m32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7525
609
    return S; \
7526
609
  case 57: \
7527
18
    tmp = fieldname(insn, 12, 2); \
7528
18
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7529
18
    tmp = fieldname(insn, 8, 4); \
7530
18
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7531
18
    tmp = fieldname(insn, 8, 4); \
7532
18
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7533
18
    tmp = fieldname(insn, 14, 1); \
7534
18
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7535
18
    tmp = fieldname(insn, 6, 1); \
7536
18
    if (!Check(&S, DecodeMR23RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7537
18
    return S; \
7538
18
  case 58: \
7539
12
    tmp = fieldname(insn, 14, 1); \
7540
12
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7541
12
    tmp = fieldname(insn, 6, 1); \
7542
12
    if (!Check(&S, DecodeMR23RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7543
12
    return S; \
7544
12
  case 59: \
7545
12
    tmp = fieldname(insn, 8, 4); \
7546
12
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7547
12
    tmp = fieldname(insn, 6, 1); \
7548
12
    if (!Check(&S, DecodeMR23RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7549
12
    return S; \
7550
234
  case 60: \
7551
234
    tmp = fieldname(insn, 12, 2); \
7552
234
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7553
234
    tmp = fieldname(insn, 8, 4); \
7554
234
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7555
234
    tmp = fieldname(insn, 8, 4); \
7556
234
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7557
234
    tmp = fieldname(insn, 14, 1); \
7558
234
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7559
234
    tmp = fieldname(insn, 4, 4); \
7560
234
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7561
234
    return S; \
7562
234
  case 61: \
7563
36
    tmp = fieldname(insn, 12, 2); \
7564
36
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7565
36
    tmp = fieldname(insn, 8, 4); \
7566
36
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7567
36
    tmp = fieldname(insn, 8, 4); \
7568
36
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7569
36
    tmp = fieldname(insn, 14, 1); \
7570
36
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7571
36
    tmp = fieldname(insn, 4, 4); \
7572
36
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7573
36
    return S; \
7574
36
  case 62: \
7575
15
    tmp = fieldname(insn, 14, 1); \
7576
15
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7577
15
    tmp = fieldname(insn, 4, 4); \
7578
15
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7579
15
    return S; \
7580
44
  case 63: \
7581
44
    tmp = fieldname(insn, 12, 2); \
7582
44
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7583
44
    tmp = fieldname(insn, 8, 4); \
7584
44
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7585
44
    tmp = fieldname(insn, 8, 4); \
7586
44
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7587
44
    return S; \
7588
2.56k
  case 64: \
7589
2.56k
    tmp = fieldname(insn, 6, 18); \
7590
2.56k
    if (!Check(&S, decodeCallOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7591
2.56k
    return S; \
7592
2.56k
  case 65: \
7593
1.04k
    tmp = fieldname(insn, 6, 18); \
7594
1.04k
    if (!Check(&S, decodeJumpOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7595
1.04k
    return S; \
7596
1.22k
  case 66: \
7597
1.22k
    tmp = fieldname(insn, 8, 4); \
7598
1.22k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7599
1.22k
    tmp = fieldname(insn, 12, 12); \
7600
1.22k
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7601
1.22k
    return S; \
7602
1.22k
  case 67: \
7603
779
    tmp = fieldname(insn, 8, 4); \
7604
779
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7605
779
    tmp = fieldname(insn, 12, 4); \
7606
779
    if (!Check(&S, decodeB4constOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7607
779
    tmp = fieldname(insn, 16, 8); \
7608
779
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7609
779
    return S; \
7610
779
  case 68: \
7611
326
    tmp = fieldname(insn, 8, 4); \
7612
326
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7613
326
    tmp = fieldname(insn, 12, 12) << 3; \
7614
326
    if (!Check(&S, decodeEntry_Imm12OpValue(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7615
326
    return S; \
7616
326
  case 69: \
7617
35
    tmp = fieldname(insn, 8, 4); \
7618
35
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7619
35
    tmp = fieldname(insn, 16, 8); \
7620
35
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7621
35
    return S; \
7622
35
  case 70: \
7623
17
    tmp = fieldname(insn, 8, 4); \
7624
17
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7625
17
    tmp = fieldname(insn, 16, 8); \
7626
17
    if (!Check(&S, decodeLoopOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7627
17
    return S; \
7628
398
  case 71: \
7629
398
    tmp = fieldname(insn, 8, 4); \
7630
398
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7631
398
    tmp = fieldname(insn, 12, 4); \
7632
398
    if (!Check(&S, decodeB4constuOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7633
398
    tmp = fieldname(insn, 16, 8); \
7634
398
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7635
398
    return S; \
7636
1.18k
  case 72: \
7637
1.18k
    tmp = fieldname(insn, 8, 4); \
7638
1.18k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7639
1.18k
    tmp = fieldname(insn, 4, 4); \
7640
1.18k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7641
1.18k
    tmp = fieldname(insn, 16, 8); \
7642
1.18k
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7643
1.18k
    return S; \
7644
1.18k
  case 73: \
7645
558
    tmp = fieldname(insn, 8, 4); \
7646
558
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7647
558
    tmp = 0x0; \
7648
558
    tmp |= fieldname(insn, 4, 4) << 0; \
7649
558
    tmp |= fieldname(insn, 12, 1) << 4; \
7650
558
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7651
558
    tmp = fieldname(insn, 16, 8); \
7652
558
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7653
558
    return S; \
7654
558
  case 74: \
7655
169
    tmp = fieldname(insn, 4, 4); \
7656
169
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7657
169
    tmp = fieldname(insn, 4, 4); \
7658
169
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7659
169
    tmp = 0x0; \
7660
169
    tmp |= fieldname(insn, 8, 7) << 0; \
7661
169
    tmp |= fieldname(insn, 22, 1) << 7; \
7662
169
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7663
169
    return S; \
7664
169
  case 75: \
7665
118
    tmp = fieldname(insn, 4, 4); \
7666
118
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7667
118
    tmp = fieldname(insn, 4, 4); \
7668
118
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7669
118
    tmp = fieldname(insn, 8, 4); \
7670
118
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7671
118
    return S; \
7672
295
  case 76: \
7673
295
    tmp = 0x0; \
7674
295
    tmp |= fieldname(insn, 15, 1) << 0; \
7675
295
    tmp |= fieldname(insn, 20, 2) << 1; \
7676
295
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7677
295
    tmp = fieldname(insn, 4, 4); \
7678
295
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7679
295
    tmp = fieldname(insn, 4, 4); \
7680
295
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7681
295
    tmp = 0x0; \
7682
295
    tmp |= fieldname(insn, 8, 7) << 0; \
7683
295
    tmp |= fieldname(insn, 22, 1) << 7; \
7684
295
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7685
295
    return S; \
7686
295
  case 77: \
7687
207
    tmp = fieldname(insn, 4, 4); \
7688
207
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7689
207
    tmp = fieldname(insn, 4, 4); \
7690
207
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7691
207
    tmp = 0x0; \
7692
207
    tmp |= fieldname(insn, 8, 7) << 0; \
7693
207
    tmp |= fieldname(insn, 22, 1) << 7; \
7694
207
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7695
207
    return S; \
7696
207
  case 78: \
7697
191
    tmp = fieldname(insn, 4, 4); \
7698
191
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7699
191
    tmp = fieldname(insn, 4, 4); \
7700
191
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7701
191
    tmp = 0x0; \
7702
191
    tmp |= fieldname(insn, 8, 7) << 0; \
7703
191
    tmp |= fieldname(insn, 22, 1) << 7; \
7704
191
    if (!Check(&S, decodeOffset_256_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7705
191
    return S; \
7706
300
  case 79: \
7707
300
    tmp = 0x0; \
7708
300
    tmp |= fieldname(insn, 15, 1) << 0; \
7709
300
    tmp |= fieldname(insn, 20, 2) << 1; \
7710
300
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7711
300
    tmp = fieldname(insn, 4, 4); \
7712
300
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7713
300
    tmp = fieldname(insn, 4, 4); \
7714
300
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7715
300
    tmp = 0x0; \
7716
300
    tmp |= fieldname(insn, 8, 7) << 0; \
7717
300
    tmp |= fieldname(insn, 22, 1) << 7; \
7718
300
    if (!Check(&S, decodeOffset_256_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7719
300
    return S; \
7720
300
  case 80: \
7721
207
    tmp = fieldname(insn, 12, 4); \
7722
207
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7723
207
    return S; \
7724
773
  case 81: \
7725
773
    tmp = fieldname(insn, 4, 4); \
7726
773
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7727
773
    tmp = 0x0; \
7728
773
    tmp |= fieldname(insn, 15, 1) << 0; \
7729
773
    tmp |= fieldname(insn, 20, 2) << 1; \
7730
773
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7731
773
    tmp = fieldname(insn, 4, 4); \
7732
773
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7733
773
    tmp = 0x0; \
7734
773
    tmp |= fieldname(insn, 8, 7) << 0; \
7735
773
    tmp |= fieldname(insn, 22, 1) << 7; \
7736
773
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7737
773
    return S; \
7738
773
  case 82: \
7739
261
    tmp = 0x0; \
7740
261
    tmp |= fieldname(insn, 15, 1) << 0; \
7741
261
    tmp |= fieldname(insn, 20, 2) << 1; \
7742
261
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7743
261
    tmp = fieldname(insn, 4, 4); \
7744
261
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7745
261
    tmp = fieldname(insn, 4, 4); \
7746
261
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7747
261
    tmp = fieldname(insn, 8, 7); \
7748
261
    if (!Check(&S, decodeOffset_128_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7749
261
    return S; \
7750
261
  case 83: \
7751
35
    tmp = 0x0; \
7752
35
    tmp |= fieldname(insn, 15, 1) << 0; \
7753
35
    tmp |= fieldname(insn, 20, 2) << 1; \
7754
35
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7755
35
    tmp = fieldname(insn, 4, 4); \
7756
35
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7757
35
    tmp = fieldname(insn, 4, 4); \
7758
35
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7759
35
    tmp = fieldname(insn, 8, 7); \
7760
35
    if (!Check(&S, decodeOffset_128_1Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7761
35
    return S; \
7762
295
  case 84: \
7763
295
    tmp = fieldname(insn, 12, 4); \
7764
295
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7765
295
    tmp = fieldname(insn, 20, 4); \
7766
295
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7767
295
    tmp = fieldname(insn, 4, 4); \
7768
295
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7769
295
    tmp = fieldname(insn, 4, 4); \
7770
295
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7771
295
    tmp = fieldname(insn, 8, 4); \
7772
295
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7773
295
    return S; \
7774
295
  case 85: \
7775
23
    tmp = 0x0; \
7776
23
    tmp |= fieldname(insn, 15, 1) << 0; \
7777
23
    tmp |= fieldname(insn, 20, 2) << 1; \
7778
23
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7779
23
    tmp = fieldname(insn, 12, 3); \
7780
23
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7781
23
    tmp = fieldname(insn, 4, 4); \
7782
23
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7783
23
    tmp = 0x0; \
7784
23
    tmp |= fieldname(insn, 15, 1) << 0; \
7785
23
    tmp |= fieldname(insn, 20, 2) << 1; \
7786
23
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7787
23
    tmp = fieldname(insn, 12, 3); \
7788
23
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7789
23
    tmp = fieldname(insn, 4, 4); \
7790
23
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7791
23
    tmp = fieldname(insn, 8, 4); \
7792
23
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7793
23
    return S; \
7794
507
  case 86: \
7795
507
    tmp = fieldname(insn, 4, 4); \
7796
507
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7797
507
    tmp = fieldname(insn, 12, 4); \
7798
507
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7799
507
    tmp = fieldname(insn, 20, 4); \
7800
507
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7801
507
    tmp = fieldname(insn, 4, 4); \
7802
507
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7803
507
    tmp = fieldname(insn, 8, 4); \
7804
507
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7805
507
    return S; \
7806
507
  case 87: \
7807
44
    tmp = 0x0; \
7808
44
    tmp |= fieldname(insn, 13, 1) << 0; \
7809
44
    tmp |= fieldname(insn, 15, 1) << 1; \
7810
44
    tmp |= fieldname(insn, 20, 1) << 2; \
7811
44
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7812
44
    tmp = fieldname(insn, 4, 4); \
7813
44
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7814
44
    tmp = fieldname(insn, 4, 4); \
7815
44
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7816
44
    tmp = fieldname(insn, 8, 3); \
7817
44
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7818
44
    tmp = 0x0; \
7819
44
    tmp |= fieldname(insn, 11, 2) << 0; \
7820
44
    tmp |= fieldname(insn, 14, 1) << 2; \
7821
44
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7822
44
    return S; \
7823
298
  case 88: \
7824
298
    tmp = 0x0; \
7825
298
    tmp |= fieldname(insn, 15, 1) << 0; \
7826
298
    tmp |= fieldname(insn, 20, 2) << 1; \
7827
298
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7828
298
    tmp = fieldname(insn, 4, 4); \
7829
298
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7830
298
    tmp = fieldname(insn, 4, 4); \
7831
298
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7832
298
    tmp = 0x0; \
7833
298
    tmp |= fieldname(insn, 8, 7) << 0; \
7834
298
    tmp |= fieldname(insn, 22, 1) << 7; \
7835
298
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7836
298
    return S; \
7837
298
  case 89: \
7838
7
    tmp = fieldname(insn, 8, 3); \
7839
7
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7840
7
    tmp = 0x0; \
7841
7
    tmp |= fieldname(insn, 11, 2) << 0; \
7842
7
    tmp |= fieldname(insn, 14, 1) << 2; \
7843
7
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7844
7
    return S; \
7845
98
  case 90: \
7846
98
    tmp = fieldname(insn, 4, 4); \
7847
98
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7848
98
    tmp = 0x0; \
7849
98
    tmp |= fieldname(insn, 15, 1) << 0; \
7850
98
    tmp |= fieldname(insn, 20, 2) << 1; \
7851
98
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7852
98
    tmp = fieldname(insn, 4, 4); \
7853
98
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7854
98
    tmp = 0x0; \
7855
98
    tmp |= fieldname(insn, 8, 7) << 0; \
7856
98
    tmp |= fieldname(insn, 22, 1) << 7; \
7857
98
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7858
98
    return S; \
7859
98
  case 91: \
7860
17
    tmp = 0x0; \
7861
17
    tmp |= fieldname(insn, 15, 1) << 0; \
7862
17
    tmp |= fieldname(insn, 20, 2) << 1; \
7863
17
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7864
17
    tmp = fieldname(insn, 8, 3); \
7865
17
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7866
17
    tmp = 0x0; \
7867
17
    tmp |= fieldname(insn, 11, 2) << 0; \
7868
17
    tmp |= fieldname(insn, 14, 1) << 2; \
7869
17
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7870
17
    tmp = fieldname(insn, 4, 4); \
7871
17
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7872
17
    return S; \
7873
163
  case 92: \
7874
163
    tmp = 0x0; \
7875
163
    tmp |= fieldname(insn, 15, 1) << 0; \
7876
163
    tmp |= fieldname(insn, 20, 2) << 1; \
7877
163
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7878
163
    tmp = fieldname(insn, 12, 3); \
7879
163
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7880
163
    tmp = 0x0; \
7881
163
    tmp |= fieldname(insn, 4, 1) << 0; \
7882
163
    tmp |= fieldname(insn, 6, 2) << 1; \
7883
163
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7884
163
    tmp = 0x0; \
7885
163
    tmp |= fieldname(insn, 5, 1) << 0; \
7886
163
    tmp |= fieldname(insn, 10, 2) << 1; \
7887
163
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7888
163
    tmp = fieldname(insn, 8, 1); \
7889
163
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7890
163
    return S; \
7891
163
  case 93: \
7892
10
    tmp = 0x0; \
7893
10
    tmp |= fieldname(insn, 15, 1) << 0; \
7894
10
    tmp |= fieldname(insn, 20, 2) << 1; \
7895
10
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7896
10
    tmp = fieldname(insn, 12, 3); \
7897
10
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7898
10
    tmp = fieldname(insn, 4, 4); \
7899
10
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7900
10
    tmp = fieldname(insn, 4, 4); \
7901
10
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7902
10
    return S; \
7903
34
  case 94: \
7904
34
    tmp = fieldname(insn, 4, 3); \
7905
34
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7906
34
    tmp = fieldname(insn, 12, 3); \
7907
34
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7908
34
    tmp = 0x0; \
7909
34
    tmp |= fieldname(insn, 15, 1) << 0; \
7910
34
    tmp |= fieldname(insn, 20, 2) << 1; \
7911
34
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7912
34
    return S; \
7913
34
  case 95: \
7914
8
    tmp = fieldname(insn, 12, 3); \
7915
8
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7916
8
    tmp = 0x0; \
7917
8
    tmp |= fieldname(insn, 15, 1) << 0; \
7918
8
    tmp |= fieldname(insn, 20, 2) << 1; \
7919
8
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7920
8
    tmp = fieldname(insn, 12, 3); \
7921
8
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7922
8
    tmp = 0x0; \
7923
8
    tmp |= fieldname(insn, 15, 1) << 0; \
7924
8
    tmp |= fieldname(insn, 20, 2) << 1; \
7925
8
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7926
8
    return S; \
7927
706
  case 96: \
7928
706
    tmp = 0x0; \
7929
706
    tmp |= fieldname(insn, 15, 1) << 0; \
7930
706
    tmp |= fieldname(insn, 20, 2) << 1; \
7931
706
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7932
706
    tmp = fieldname(insn, 12, 3); \
7933
706
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7934
706
    tmp = 0x0; \
7935
706
    tmp |= fieldname(insn, 15, 1) << 0; \
7936
706
    tmp |= fieldname(insn, 20, 2) << 1; \
7937
706
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7938
706
    tmp = fieldname(insn, 12, 3); \
7939
706
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7940
706
    tmp = fieldname(insn, 4, 4); \
7941
706
    if (!Check(&S, decodeSelect_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7942
706
    return S; \
7943
706
  case 97: \
7944
30
    tmp = fieldname(insn, 4, 3); \
7945
30
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7946
30
    tmp = fieldname(insn, 12, 3); \
7947
30
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7948
30
    tmp = fieldname(insn, 12, 3); \
7949
30
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7950
30
    tmp = 0x0; \
7951
30
    tmp |= fieldname(insn, 15, 1) << 0; \
7952
30
    tmp |= fieldname(insn, 20, 2) << 1; \
7953
30
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7954
30
    return S; \
7955
51
  case 98: \
7956
51
    tmp = fieldname(insn, 4, 4); \
7957
51
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7958
51
    tmp = fieldname(insn, 12, 3); \
7959
51
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7960
51
    tmp = 0x0; \
7961
51
    tmp |= fieldname(insn, 15, 1) << 0; \
7962
51
    tmp |= fieldname(insn, 20, 2) << 1; \
7963
51
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7964
51
    tmp = fieldname(insn, 4, 4); \
7965
51
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7966
51
    return S; \
7967
51
  case 99: \
7968
21
    tmp = 0x0; \
7969
21
    tmp |= fieldname(insn, 15, 1) << 0; \
7970
21
    tmp |= fieldname(insn, 20, 2) << 1; \
7971
21
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7972
21
    tmp = fieldname(insn, 4, 4); \
7973
21
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7974
21
    tmp = fieldname(insn, 4, 4); \
7975
21
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7976
21
    tmp = fieldname(insn, 8, 4); \
7977
21
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7978
21
    return S; \
7979
83
  case 100: \
7980
83
    tmp = fieldname(insn, 4, 4); \
7981
83
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7982
83
    tmp = 0x0; \
7983
83
    tmp |= fieldname(insn, 15, 1) << 0; \
7984
83
    tmp |= fieldname(insn, 20, 2) << 1; \
7985
83
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7986
83
    tmp = fieldname(insn, 4, 4); \
7987
83
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7988
83
    tmp = fieldname(insn, 8, 4); \
7989
83
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7990
83
    return S; \
7991
83
  case 101: \
7992
51
    tmp = 0x0; \
7993
51
    tmp |= fieldname(insn, 15, 1) << 0; \
7994
51
    tmp |= fieldname(insn, 20, 2) << 1; \
7995
51
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7996
51
    tmp = 0x0; \
7997
51
    tmp |= fieldname(insn, 15, 1) << 0; \
7998
51
    tmp |= fieldname(insn, 20, 2) << 1; \
7999
51
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8000
51
    tmp = fieldname(insn, 8, 4); \
8001
51
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8002
51
    tmp = fieldname(insn, 4, 4); \
8003
51
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8004
51
    return S; \
8005
51
  case 102: \
8006
45
    tmp = 0x0; \
8007
45
    tmp |= fieldname(insn, 15, 1) << 0; \
8008
45
    tmp |= fieldname(insn, 20, 2) << 1; \
8009
45
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8010
45
    tmp = 0x0; \
8011
45
    tmp |= fieldname(insn, 4, 1) << 0; \
8012
45
    tmp |= fieldname(insn, 6, 2) << 1; \
8013
45
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8014
45
    tmp = 0x0; \
8015
45
    tmp |= fieldname(insn, 5, 1) << 0; \
8016
45
    tmp |= fieldname(insn, 10, 2) << 1; \
8017
45
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8018
45
    return S; \
8019
45
  case 103: \
8020
6
    tmp = 0x0; \
8021
6
    tmp |= fieldname(insn, 15, 1) << 0; \
8022
6
    tmp |= fieldname(insn, 20, 2) << 1; \
8023
6
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8024
6
    tmp = fieldname(insn, 4, 4); \
8025
6
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8026
6
    tmp = fieldname(insn, 10, 2); \
8027
6
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8028
6
    return S; \
8029
20
  case 104: \
8030
20
    tmp = fieldname(insn, 4, 4); \
8031
20
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8032
20
    tmp = 0x0; \
8033
20
    tmp |= fieldname(insn, 15, 1) << 0; \
8034
20
    tmp |= fieldname(insn, 20, 2) << 1; \
8035
20
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8036
20
    tmp = fieldname(insn, 4, 4); \
8037
20
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8038
20
    tmp = fieldname(insn, 10, 1); \
8039
20
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8040
20
    return S; \
8041
162
  case 105: \
8042
162
    tmp = 0x0; \
8043
162
    tmp |= fieldname(insn, 15, 1) << 0; \
8044
162
    tmp |= fieldname(insn, 20, 2) << 1; \
8045
162
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8046
162
    tmp = fieldname(insn, 4, 4); \
8047
162
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8048
162
    return S; \
8049
162
  case 106: \
8050
126
    tmp = fieldname(insn, 4, 3); \
8051
126
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8052
126
    tmp = 0x0; \
8053
126
    tmp |= fieldname(insn, 15, 1) << 0; \
8054
126
    tmp |= fieldname(insn, 20, 2) << 1; \
8055
126
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8056
126
    return S; \
8057
126
  case 107: \
8058
59
    tmp = fieldname(insn, 4, 4); \
8059
59
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8060
59
    tmp = 0x0; \
8061
59
    tmp |= fieldname(insn, 15, 1) << 0; \
8062
59
    tmp |= fieldname(insn, 20, 2) << 1; \
8063
59
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8064
59
    tmp = fieldname(insn, 10, 2); \
8065
59
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8066
59
    return S; \
8067
59
  case 108: \
8068
52
    tmp = 0x0; \
8069
52
    tmp |= fieldname(insn, 15, 1) << 0; \
8070
52
    tmp |= fieldname(insn, 20, 2) << 1; \
8071
52
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8072
52
    tmp = fieldname(insn, 4, 4); \
8073
52
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8074
52
    tmp = fieldname(insn, 10, 1); \
8075
52
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8076
52
    return S; \
8077
52
  case 109: \
8078
23
    tmp = 0x0; \
8079
23
    tmp |= fieldname(insn, 15, 1) << 0; \
8080
23
    tmp |= fieldname(insn, 20, 2) << 1; \
8081
23
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8082
23
    tmp = fieldname(insn, 4, 4); \
8083
23
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8084
23
    tmp = fieldname(insn, 4, 4); \
8085
23
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8086
23
    return S; \
8087
42
  case 110: \
8088
42
    tmp = 0x0; \
8089
42
    tmp |= fieldname(insn, 15, 1) << 0; \
8090
42
    tmp |= fieldname(insn, 20, 2) << 1; \
8091
42
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8092
42
    tmp = 0x0; \
8093
42
    tmp |= fieldname(insn, 4, 1) << 0; \
8094
42
    tmp |= fieldname(insn, 6, 2) << 1; \
8095
42
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8096
42
    return S; \
8097
42
  case 111: \
8098
8
    tmp = 0x0; \
8099
8
    tmp |= fieldname(insn, 15, 1) << 0; \
8100
8
    tmp |= fieldname(insn, 20, 2) << 1; \
8101
8
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8102
8
    return S; \
8103
48
  case 112: \
8104
48
    tmp = fieldname(insn, 8, 4); \
8105
48
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8106
48
    tmp = fieldname(insn, 4, 4); \
8107
48
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8108
48
    tmp = fieldname(insn, 14, 1); \
8109
48
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8110
48
    return S; \
8111
49
  case 113: \
8112
49
    tmp = 0x0; \
8113
49
    tmp |= fieldname(insn, 15, 1) << 0; \
8114
49
    tmp |= fieldname(insn, 20, 2) << 1; \
8115
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8116
49
    tmp = fieldname(insn, 8, 3); \
8117
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8118
49
    tmp = 0x0; \
8119
49
    tmp |= fieldname(insn, 11, 2) << 0; \
8120
49
    tmp |= fieldname(insn, 14, 1) << 2; \
8121
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8122
49
    tmp = fieldname(insn, 4, 2); \
8123
49
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8124
49
    return S; \
8125
207
  case 114: \
8126
207
    tmp = 0x0; \
8127
207
    tmp |= fieldname(insn, 15, 1) << 0; \
8128
207
    tmp |= fieldname(insn, 20, 2) << 1; \
8129
207
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8130
207
    tmp = fieldname(insn, 8, 3); \
8131
207
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8132
207
    tmp = 0x0; \
8133
207
    tmp |= fieldname(insn, 11, 2) << 0; \
8134
207
    tmp |= fieldname(insn, 14, 1) << 2; \
8135
207
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8136
207
    return S; \
8137
207
  case 115: \
8138
48
    tmp = fieldname(insn, 8, 3); \
8139
48
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8140
48
    tmp = 0x0; \
8141
48
    tmp |= fieldname(insn, 11, 2) << 0; \
8142
48
    tmp |= fieldname(insn, 14, 1) << 2; \
8143
48
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8144
48
    tmp = 0x0; \
8145
48
    tmp |= fieldname(insn, 4, 1) << 0; \
8146
48
    tmp |= fieldname(insn, 15, 1) << 1; \
8147
48
    tmp |= fieldname(insn, 20, 2) << 2; \
8148
48
    if (!Check(&S, decodeSelect_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8149
48
    return S; \
8150
73
  case 116: \
8151
73
    tmp = fieldname(insn, 8, 3); \
8152
73
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8153
73
    tmp = 0x0; \
8154
73
    tmp |= fieldname(insn, 11, 2) << 0; \
8155
73
    tmp |= fieldname(insn, 14, 1) << 2; \
8156
73
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8157
73
    tmp = 0x0; \
8158
73
    tmp |= fieldname(insn, 15, 1) << 0; \
8159
73
    tmp |= fieldname(insn, 20, 2) << 1; \
8160
73
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8161
73
    return S; \
8162
73
  case 117: \
8163
21
    tmp = 0x0; \
8164
21
    tmp |= fieldname(insn, 15, 1) << 0; \
8165
21
    tmp |= fieldname(insn, 20, 2) << 1; \
8166
21
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8167
21
    tmp = 0x0; \
8168
21
    tmp |= fieldname(insn, 5, 1) << 0; \
8169
21
    tmp |= fieldname(insn, 10, 2) << 1; \
8170
21
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8171
21
    return S; \
8172
21
  case 118: \
8173
0
    tmp = 0x0; \
8174
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8175
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8176
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8177
0
    tmp = fieldname(insn, 4, 4); \
8178
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8179
0
    tmp = fieldname(insn, 20, 3); \
8180
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8181
0
    tmp = fieldname(insn, 4, 4); \
8182
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8183
0
    tmp = 0x0; \
8184
0
    tmp |= fieldname(insn, 8, 4) << 0; \
8185
0
    tmp |= fieldname(insn, 26, 2) << 4; \
8186
0
    if (!Check(&S, decodeOffset_64_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8187
0
    tmp = 0x0; \
8188
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8189
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8190
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8191
0
    tmp = 0x0; \
8192
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8193
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8194
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8195
0
    tmp = fieldname(insn, 20, 3); \
8196
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8197
0
    tmp = fieldname(insn, 16, 3); \
8198
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8199
0
    return S; \
8200
0
  case 119: \
8201
0
    tmp = 0x0; \
8202
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8203
0
    tmp |= fieldname(insn, 24, 3) << 1; \
8204
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8205
0
    tmp = 0x0; \
8206
0
    tmp |= fieldname(insn, 0, 1) << 0; \
8207
0
    tmp |= fieldname(insn, 16, 3) << 1; \
8208
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8209
0
    tmp = fieldname(insn, 12, 4); \
8210
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8211
0
    tmp = fieldname(insn, 20, 4); \
8212
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8213
0
    tmp = fieldname(insn, 4, 4); \
8214
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8215
0
    tmp = fieldname(insn, 4, 4); \
8216
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8217
0
    tmp = fieldname(insn, 8, 4); \
8218
0
    if (!Check(&S, decodeOffset_16_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8219
0
    return S; \
8220
0
  case 120: \
8221
0
    tmp = 0x0; \
8222
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8223
0
    tmp |= fieldname(insn, 24, 3) << 1; \
8224
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8225
0
    tmp = 0x0; \
8226
0
    tmp |= fieldname(insn, 0, 1) << 0; \
8227
0
    tmp |= fieldname(insn, 16, 3) << 1; \
8228
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8229
0
    tmp = fieldname(insn, 12, 4); \
8230
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8231
0
    tmp = fieldname(insn, 20, 4); \
8232
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8233
0
    tmp = fieldname(insn, 4, 4); \
8234
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8235
0
    tmp = fieldname(insn, 4, 4); \
8236
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8237
0
    tmp = fieldname(insn, 8, 4); \
8238
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8239
0
    return S; \
8240
0
  case 121: \
8241
0
    tmp = fieldname(insn, 4, 4); \
8242
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8243
0
    tmp = 0x0; \
8244
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8245
0
    tmp |= fieldname(insn, 24, 3) << 1; \
8246
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8247
0
    tmp = 0x0; \
8248
0
    tmp |= fieldname(insn, 0, 1) << 0; \
8249
0
    tmp |= fieldname(insn, 16, 3) << 1; \
8250
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8251
0
    tmp = fieldname(insn, 12, 4); \
8252
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8253
0
    tmp = fieldname(insn, 20, 4); \
8254
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8255
0
    tmp = fieldname(insn, 4, 4); \
8256
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8257
0
    tmp = fieldname(insn, 8, 4); \
8258
0
    if (!Check(&S, decodeOffset_16_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8259
0
    return S; \
8260
0
  case 122: \
8261
0
    tmp = fieldname(insn, 4, 4); \
8262
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8263
0
    tmp = 0x0; \
8264
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8265
0
    tmp |= fieldname(insn, 24, 3) << 1; \
8266
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8267
0
    tmp = 0x0; \
8268
0
    tmp |= fieldname(insn, 0, 1) << 0; \
8269
0
    tmp |= fieldname(insn, 16, 3) << 1; \
8270
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8271
0
    tmp = fieldname(insn, 12, 4); \
8272
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8273
0
    tmp = fieldname(insn, 20, 4); \
8274
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8275
0
    tmp = fieldname(insn, 4, 4); \
8276
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8277
0
    tmp = fieldname(insn, 8, 4); \
8278
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8279
0
    return S; \
8280
0
  case 123: \
8281
0
    tmp = 0x0; \
8282
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8283
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8284
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8285
0
    tmp = fieldname(insn, 4, 4); \
8286
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8287
0
    tmp = fieldname(insn, 8, 4); \
8288
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8289
0
    tmp = fieldname(insn, 20, 3); \
8290
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8291
0
    tmp = fieldname(insn, 4, 4); \
8292
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8293
0
    tmp = fieldname(insn, 8, 4); \
8294
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8295
0
    tmp = fieldname(insn, 16, 3); \
8296
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8297
0
    tmp = 0x0; \
8298
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8299
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8300
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8301
0
    tmp = 0x0; \
8302
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8303
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8304
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8305
0
    tmp = fieldname(insn, 26, 1); \
8306
0
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8307
0
    return S; \
8308
0
  case 124: \
8309
0
    tmp = fieldname(insn, 4, 4); \
8310
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8311
0
    tmp = 0x0; \
8312
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8313
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8314
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8315
0
    tmp = fieldname(insn, 20, 3); \
8316
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8317
0
    tmp = fieldname(insn, 16, 3); \
8318
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8319
0
    tmp = fieldname(insn, 4, 4); \
8320
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8321
0
    tmp = fieldname(insn, 8, 4); \
8322
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8323
0
    tmp = 0x0; \
8324
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8325
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8326
0
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8327
0
    tmp = 0x0; \
8328
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8329
0
    tmp |= fieldname(insn, 24, 1) << 1; \
8330
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8331
0
    tmp = fieldname(insn, 25, 2); \
8332
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8333
0
    return S; \
8334
0
  case 125: \
8335
0
    tmp = 0x0; \
8336
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8337
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8338
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8339
0
    tmp = fieldname(insn, 4, 4); \
8340
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8341
0
    tmp = fieldname(insn, 20, 3); \
8342
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8343
0
    tmp = fieldname(insn, 4, 4); \
8344
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8345
0
    tmp = fieldname(insn, 8, 4); \
8346
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8347
0
    tmp = 0x0; \
8348
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8349
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8350
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8351
0
    tmp = 0x0; \
8352
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8353
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8354
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8355
0
    tmp = fieldname(insn, 20, 3); \
8356
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8357
0
    tmp = fieldname(insn, 16, 3); \
8358
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8359
0
    return S; \
8360
0
  case 126: \
8361
0
    tmp = fieldname(insn, 8, 3); \
8362
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8363
0
    tmp = fieldname(insn, 4, 4); \
8364
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8365
0
    tmp = 0x0; \
8366
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8367
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8368
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8369
0
    tmp = 0x0; \
8370
0
    tmp |= fieldname(insn, 11, 1) << 0; \
8371
0
    tmp |= fieldname(insn, 19, 1) << 1; \
8372
0
    tmp |= fieldname(insn, 24, 1) << 2; \
8373
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8374
0
    tmp = fieldname(insn, 4, 4); \
8375
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8376
0
    tmp = 0x0; \
8377
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8378
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8379
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8380
0
    tmp = fieldname(insn, 20, 3); \
8381
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8382
0
    tmp = fieldname(insn, 16, 3); \
8383
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8384
0
    tmp = fieldname(insn, 25, 1); \
8385
0
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8386
0
    return S; \
8387
0
  case 127: \
8388
0
    tmp = 0x0; \
8389
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8390
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8391
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8392
0
    tmp = fieldname(insn, 4, 4); \
8393
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8394
0
    tmp = fieldname(insn, 16, 3); \
8395
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8396
0
    tmp = fieldname(insn, 4, 4); \
8397
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8398
0
    tmp = fieldname(insn, 8, 4); \
8399
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8400
0
    tmp = 0x0; \
8401
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8402
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8403
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8404
0
    tmp = fieldname(insn, 20, 3); \
8405
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8406
0
    tmp = 0x0; \
8407
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8408
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8409
0
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8410
0
    return S; \
8411
0
  case 128: \
8412
0
    tmp = fieldname(insn, 16, 3); \
8413
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8414
0
    tmp = fieldname(insn, 4, 4); \
8415
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8416
0
    tmp = 0x0; \
8417
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8418
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8419
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8420
0
    tmp = fieldname(insn, 4, 4); \
8421
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8422
0
    tmp = 0x0; \
8423
0
    tmp |= fieldname(insn, 8, 2) << 0; \
8424
0
    tmp |= fieldname(insn, 12, 2) << 3; \
8425
0
    tmp |= fieldname(insn, 19, 1) << 5; \
8426
0
    tmp |= fieldname(insn, 23, 1) << 2; \
8427
0
    tmp |= fieldname(insn, 24, 2) << 6; \
8428
0
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8429
0
    tmp = 0x0; \
8430
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8431
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8432
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8433
0
    tmp = fieldname(insn, 20, 3); \
8434
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8435
0
    return S; \
8436
0
  case 129: \
8437
0
    tmp = fieldname(insn, 12, 4); \
8438
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8439
0
    tmp = fieldname(insn, 20, 4); \
8440
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8441
0
    tmp = fieldname(insn, 4, 4); \
8442
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8443
0
    tmp = fieldname(insn, 4, 4); \
8444
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8445
0
    tmp = 0x0; \
8446
0
    tmp |= fieldname(insn, 0, 1) << 1; \
8447
0
    tmp |= fieldname(insn, 8, 1) << 0; \
8448
0
    tmp |= fieldname(insn, 16, 4) << 2; \
8449
0
    tmp |= fieldname(insn, 24, 2) << 6; \
8450
0
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8451
0
    return S; \
8452
0
  case 130: \
8453
0
    tmp = fieldname(insn, 4, 4); \
8454
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8455
0
    tmp = fieldname(insn, 12, 4); \
8456
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8457
0
    tmp = fieldname(insn, 20, 4); \
8458
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8459
0
    tmp = fieldname(insn, 4, 4); \
8460
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8461
0
    tmp = 0x0; \
8462
0
    tmp |= fieldname(insn, 0, 1) << 1; \
8463
0
    tmp |= fieldname(insn, 8, 1) << 0; \
8464
0
    tmp |= fieldname(insn, 16, 4) << 2; \
8465
0
    tmp |= fieldname(insn, 24, 2) << 6; \
8466
0
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8467
0
    return S; \
8468
0
  case 131: \
8469
0
    tmp = 0x0; \
8470
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8471
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8472
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8473
0
    tmp = fieldname(insn, 4, 4); \
8474
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8475
0
    tmp = fieldname(insn, 20, 3); \
8476
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8477
0
    tmp = fieldname(insn, 4, 4); \
8478
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8479
0
    tmp = 0x0; \
8480
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8481
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8482
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8483
0
    tmp = 0x0; \
8484
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8485
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8486
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8487
0
    tmp = fieldname(insn, 20, 3); \
8488
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8489
0
    tmp = fieldname(insn, 16, 3); \
8490
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8491
0
    return S; \
8492
0
  case 132: \
8493
0
    tmp = 0x0; \
8494
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8495
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8496
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8497
0
    tmp = fieldname(insn, 4, 4); \
8498
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8499
0
    tmp = fieldname(insn, 16, 3); \
8500
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8501
0
    tmp = fieldname(insn, 4, 4); \
8502
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8503
0
    tmp = 0x0; \
8504
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8505
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8506
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8507
0
    tmp = 0x0; \
8508
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8509
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8510
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8511
0
    tmp = fieldname(insn, 8, 2); \
8512
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8513
0
    return S; \
8514
0
  case 133: \
8515
0
    tmp = 0x0; \
8516
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8517
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8518
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8519
0
    tmp = fieldname(insn, 4, 4); \
8520
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8521
0
    tmp = fieldname(insn, 16, 3); \
8522
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8523
0
    tmp = fieldname(insn, 4, 4); \
8524
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8525
0
    tmp = 0x0; \
8526
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8527
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8528
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8529
0
    tmp = 0x0; \
8530
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8531
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8532
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8533
0
    return S; \
8534
0
  case 134: \
8535
0
    tmp = 0x0; \
8536
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8537
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8538
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8539
0
    tmp = fieldname(insn, 4, 4); \
8540
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8541
0
    tmp = fieldname(insn, 4, 4); \
8542
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8543
0
    tmp = 0x0; \
8544
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8545
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8546
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8547
0
    tmp = 0x0; \
8548
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8549
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8550
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8551
0
    tmp = 0x0; \
8552
0
    tmp |= fieldname(insn, 16, 3) << 1; \
8553
0
    tmp |= fieldname(insn, 20, 1) << 0; \
8554
0
    if (!Check(&S, decodeSelect_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8555
0
    return S; \
8556
0
  case 135: \
8557
0
    tmp = 0x0; \
8558
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8559
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8560
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8561
0
    tmp = fieldname(insn, 4, 4); \
8562
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8563
0
    tmp = fieldname(insn, 4, 4); \
8564
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8565
0
    tmp = 0x0; \
8566
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8567
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8568
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8569
0
    tmp = 0x0; \
8570
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8571
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8572
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8573
0
    tmp = fieldname(insn, 16, 3); \
8574
0
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8575
0
    return S; \
8576
0
  case 136: \
8577
0
    tmp = fieldname(insn, 16, 3); \
8578
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8579
0
    tmp = 0x0; \
8580
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8581
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8582
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8583
0
    tmp = fieldname(insn, 4, 4); \
8584
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8585
0
    tmp = 0x0; \
8586
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8587
0
    tmp |= fieldname(insn, 24, 1) << 1; \
8588
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8589
0
    tmp = 0x0; \
8590
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8591
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8592
0
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8593
0
    return S; \
8594
0
  case 137: \
8595
0
    tmp = fieldname(insn, 4, 4); \
8596
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8597
0
    tmp = fieldname(insn, 16, 3); \
8598
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8599
0
    tmp = fieldname(insn, 20, 3); \
8600
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8601
0
    tmp = fieldname(insn, 4, 4); \
8602
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8603
0
    tmp = 0x0; \
8604
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8605
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8606
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8607
0
    tmp = 0x0; \
8608
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8609
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8610
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8611
0
    tmp = fieldname(insn, 8, 2); \
8612
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8613
0
    return S; \
8614
0
  case 138: \
8615
0
    tmp = fieldname(insn, 4, 4); \
8616
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8617
0
    tmp = fieldname(insn, 16, 3); \
8618
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8619
0
    tmp = fieldname(insn, 20, 3); \
8620
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8621
0
    tmp = fieldname(insn, 4, 4); \
8622
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8623
0
    tmp = 0x0; \
8624
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8625
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8626
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8627
0
    tmp = 0x0; \
8628
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8629
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8630
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8631
0
    return S; \
8632
0
  case 139: \
8633
0
    tmp = fieldname(insn, 20, 3); \
8634
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8635
0
    tmp = 0x0; \
8636
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8637
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8638
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8639
0
    tmp = fieldname(insn, 4, 4); \
8640
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8641
0
    tmp = 0x0; \
8642
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8643
0
    tmp |= fieldname(insn, 24, 1) << 1; \
8644
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8645
0
    tmp = 0x0; \
8646
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8647
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8648
0
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8649
0
    return S; \
8650
0
  case 140: \
8651
0
    tmp = fieldname(insn, 16, 3); \
8652
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8653
0
    tmp = fieldname(insn, 4, 4); \
8654
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8655
0
    tmp = 0x0; \
8656
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8657
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8658
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8659
0
    tmp = fieldname(insn, 4, 4); \
8660
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8661
0
    tmp = fieldname(insn, 8, 4); \
8662
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8663
0
    tmp = 0x0; \
8664
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8665
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8666
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8667
0
    tmp = fieldname(insn, 20, 3); \
8668
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8669
0
    return S; \
8670
0
  case 141: \
8671
0
    tmp = fieldname(insn, 16, 3); \
8672
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8673
0
    tmp = fieldname(insn, 4, 4); \
8674
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8675
0
    tmp = 0x0; \
8676
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8677
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8678
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8679
0
    tmp = fieldname(insn, 20, 3); \
8680
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8681
0
    tmp = fieldname(insn, 4, 4); \
8682
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8683
0
    tmp = 0x0; \
8684
0
    tmp |= fieldname(insn, 12, 1) << 1; \
8685
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8686
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8687
0
    return S; \
8688
0
  case 142: \
8689
0
    tmp = 0x0; \
8690
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8691
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8692
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8693
0
    tmp = fieldname(insn, 4, 4); \
8694
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8695
0
    tmp = fieldname(insn, 4, 4); \
8696
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8697
0
    tmp = 0x0; \
8698
0
    tmp |= fieldname(insn, 8, 4) << 0; \
8699
0
    tmp |= fieldname(insn, 26, 2) << 4; \
8700
0
    if (!Check(&S, decodeOffset_64_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8701
0
    tmp = 0x0; \
8702
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8703
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8704
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8705
0
    tmp = 0x0; \
8706
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8707
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8708
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8709
0
    return S; \
8710
0
  case 143: \
8711
0
    tmp = 0x0; \
8712
0
    tmp |= fieldname(insn, 19, 1) << 0; \
8713
0
    tmp |= fieldname(insn, 24, 2) << 1; \
8714
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8715
0
    tmp = fieldname(insn, 4, 4); \
8716
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8717
0
    tmp = fieldname(insn, 4, 4); \
8718
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8719
0
    tmp = fieldname(insn, 8, 4); \
8720
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8721
0
    tmp = 0x0; \
8722
0
    tmp |= fieldname(insn, 0, 1) << 2; \
8723
0
    tmp |= fieldname(insn, 14, 2) << 0; \
8724
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8725
0
    tmp = 0x0; \
8726
0
    tmp |= fieldname(insn, 12, 2) << 1; \
8727
0
    tmp |= fieldname(insn, 23, 1) << 0; \
8728
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8729
0
    return S; \
8730
0
  case 144: \
8731
0
    tmp = fieldname(insn, 12, 4); \
8732
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8733
0
    tmp = fieldname(insn, 4, 4); \
8734
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8735
0
    tmp = fieldname(insn, 8, 4); \
8736
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8737
0
    return S; \
8738
0
  case 145: \
8739
0
    tmp = fieldname(insn, 8, 4); \
8740
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8741
0
    tmp = fieldname(insn, 4, 4); \
8742
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8743
0
    tmp = fieldname(insn, 12, 4); \
8744
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8745
0
    tmp = fieldname(insn, 8, 4); \
8746
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8747
0
    return S; \
8748
0
  case 146: \
8749
0
    tmp = fieldname(insn, 12, 4); \
8750
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8751
0
    tmp = fieldname(insn, 8, 4); \
8752
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8753
0
    tmp = fieldname(insn, 4, 4); \
8754
0
    MCOperand_CreateImm0(MI, tmp); \
8755
0
    return S; \
8756
0
  case 147: \
8757
0
    tmp = fieldname(insn, 8, 4); \
8758
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8759
0
    tmp = fieldname(insn, 12, 4); \
8760
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8761
0
    tmp = fieldname(insn, 8, 4); \
8762
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8763
0
    tmp = fieldname(insn, 4, 4); \
8764
0
    MCOperand_CreateImm0(MI, tmp); \
8765
0
    return S; \
8766
0
  case 148: \
8767
0
    tmp = fieldname(insn, 8, 4); \
8768
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8769
0
    tmp = fieldname(insn, 12, 4); \
8770
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8771
0
    tmp = fieldname(insn, 8, 4); \
8772
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8773
0
    tmp = fieldname(insn, 4, 4); \
8774
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8775
0
    return S; \
8776
0
  case 149: \
8777
0
    tmp = fieldname(insn, 12, 4); \
8778
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8779
0
    tmp = fieldname(insn, 4, 4); \
8780
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8781
0
    tmp = fieldname(insn, 8, 4); \
8782
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8783
0
    return S; \
8784
0
  case 150: \
8785
0
    tmp = fieldname(insn, 12, 4); \
8786
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8787
0
    tmp = fieldname(insn, 4, 2); \
8788
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8789
0
    tmp = fieldname(insn, 8, 4); \
8790
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8791
0
    tmp = fieldname(insn, 4, 2); \
8792
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8793
0
    tmp = fieldname(insn, 8, 4); \
8794
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8795
0
    return S; \
8796
0
  case 151: \
8797
0
    tmp = fieldname(insn, 4, 2); \
8798
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8799
0
    tmp = fieldname(insn, 8, 4); \
8800
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8801
0
    tmp = fieldname(insn, 12, 4); \
8802
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8803
0
    tmp = fieldname(insn, 4, 2); \
8804
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8805
0
    tmp = fieldname(insn, 8, 4); \
8806
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8807
0
    return S; \
8808
0
  case 152: \
8809
0
    tmp = fieldname(insn, 12, 4); \
8810
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8811
0
    tmp = fieldname(insn, 4, 4); \
8812
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8813
0
    tmp = fieldname(insn, 8, 4); \
8814
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8815
0
    return S; \
8816
0
  case 153: \
8817
0
    tmp = fieldname(insn, 12, 4); \
8818
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8819
0
    tmp = fieldname(insn, 8, 4); \
8820
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8821
0
    tmp = fieldname(insn, 4, 4); \
8822
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8823
0
    return S; \
8824
0
  case 154: \
8825
0
    tmp = fieldname(insn, 12, 4); \
8826
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8827
0
    tmp = fieldname(insn, 8, 4); \
8828
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8829
0
    tmp = fieldname(insn, 4, 4); \
8830
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8831
0
    return S; \
8832
0
  case 155: \
8833
0
    tmp = fieldname(insn, 12, 4); \
8834
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8835
0
    tmp = fieldname(insn, 8, 4); \
8836
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8837
0
    tmp = fieldname(insn, 4, 4); \
8838
0
    if (!Check(&S, decodeImm7_22Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8839
0
    return S; \
8840
0
  case 156: \
8841
0
    tmp = fieldname(insn, 12, 4); \
8842
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8843
0
    tmp = fieldname(insn, 8, 4); \
8844
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8845
0
    return S; \
8846
0
  case 157: \
8847
0
    tmp = fieldname(insn, 12, 4); \
8848
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8849
0
    tmp = fieldname(insn, 4, 4); \
8850
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8851
0
    return S; \
8852
0
  case 158: \
8853
0
    tmp = fieldname(insn, 12, 4); \
8854
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8855
0
    tmp = fieldname(insn, 8, 4); \
8856
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8857
0
    return S; \
8858
0
  case 159: \
8859
0
    tmp = fieldname(insn, 12, 4); \
8860
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8861
0
    tmp = fieldname(insn, 12, 4); \
8862
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8863
0
    tmp = fieldname(insn, 4, 4); \
8864
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8865
0
    tmp = fieldname(insn, 10, 2); \
8866
0
    MCOperand_CreateImm0(MI, tmp); \
8867
0
    return S; \
8868
0
  case 160: \
8869
0
    tmp = fieldname(insn, 6, 2); \
8870
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8871
0
    tmp = fieldname(insn, 4, 2); \
8872
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8873
0
    return S; \
8874
0
  case 161: \
8875
0
    tmp = fieldname(insn, 6, 2); \
8876
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8877
0
    return S; \
8878
0
  case 162: \
8879
0
    tmp = fieldname(insn, 12, 4); \
8880
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8881
0
    tmp = fieldname(insn, 12, 4); \
8882
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8883
0
    tmp = fieldname(insn, 4, 4); \
8884
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8885
0
    return S; \
8886
0
  case 163: \
8887
0
    tmp = fieldname(insn, 12, 4); \
8888
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8889
0
    tmp = fieldname(insn, 8, 4); \
8890
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8891
0
    tmp = fieldname(insn, 8, 4); \
8892
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8893
0
    tmp = fieldname(insn, 4, 3); \
8894
0
    MCOperand_CreateImm0(MI, tmp); \
8895
0
    return S; \
8896
0
  case 164: \
8897
0
    tmp = fieldname(insn, 12, 4); \
8898
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8899
0
    tmp = fieldname(insn, 12, 4); \
8900
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8901
0
    tmp = fieldname(insn, 8, 4); \
8902
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8903
0
    tmp = fieldname(insn, 5, 3); \
8904
0
    if (!Check(&S, DecodeBR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8905
0
    return S; \
8906
0
  case 165: \
8907
0
    tmp = fieldname(insn, 12, 4); \
8908
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8909
0
    tmp = fieldname(insn, 8, 4); \
8910
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8911
0
    return S; \
8912
0
  case 166: \
8913
0
    tmp = fieldname(insn, 12, 4); \
8914
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8915
0
    tmp = fieldname(insn, 8, 4); \
8916
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8917
0
    tmp = fieldname(insn, 8, 4); \
8918
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8919
0
    return S; \
8920
0
  case 167: \
8921
0
    tmp = fieldname(insn, 12, 4); \
8922
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8923
0
    tmp = 0x0; \
8924
0
    tmp |= fieldname(insn, 4, 2) << 0; \
8925
0
    tmp |= fieldname(insn, 8, 4) << 2; \
8926
0
    MCOperand_CreateImm0(MI, tmp); \
8927
0
    return S; \
8928
0
  case 168: \
8929
0
    tmp = fieldname(insn, 12, 4); \
8930
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8931
0
    tmp = fieldname(insn, 4, 4); \
8932
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8933
0
    tmp = fieldname(insn, 8, 4); \
8934
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8935
0
    return S; \
8936
0
  case 169: \
8937
0
    tmp = fieldname(insn, 12, 4); \
8938
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8939
0
    tmp = fieldname(insn, 8, 4); \
8940
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8941
0
    tmp = fieldname(insn, 8, 4); \
8942
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8943
0
    tmp = fieldname(insn, 4, 4); \
8944
0
    MCOperand_CreateImm0(MI, tmp); \
8945
0
    return S; \
8946
0
  case 170: \
8947
0
    tmp = fieldname(insn, 12, 4); \
8948
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8949
0
    tmp = fieldname(insn, 8, 4); \
8950
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8951
0
    tmp = fieldname(insn, 4, 4); \
8952
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8953
0
    return S; \
8954
0
  case 171: \
8955
0
    tmp = fieldname(insn, 13, 3); \
8956
0
    if (!Check(&S, DecodeBR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8957
0
    tmp = fieldname(insn, 8, 4); \
8958
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8959
0
    tmp = fieldname(insn, 4, 4); \
8960
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8961
0
    return S; \
8962
0
  case 172: \
8963
0
    tmp = fieldname(insn, 8, 4); \
8964
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8965
0
    tmp = fieldname(insn, 8, 4); \
8966
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8967
0
    tmp = fieldname(insn, 4, 4); \
8968
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8969
0
    tmp = fieldname(insn, 12, 4); \
8970
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8971
0
    return S; \
8972
0
  case 173: \
8973
0
    tmp = fieldname(insn, 12, 4); \
8974
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8975
0
    tmp = fieldname(insn, 12, 4); \
8976
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8977
0
    tmp = fieldname(insn, 8, 4); \
8978
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8979
0
    tmp = fieldname(insn, 4, 4); \
8980
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8981
0
    return S; \
8982
0
  case 174: \
8983
0
    tmp = fieldname(insn, 8, 4); \
8984
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8985
0
    tmp = fieldname(insn, 12, 4); \
8986
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8987
0
    tmp = fieldname(insn, 8, 4); \
8988
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8989
0
    tmp = fieldname(insn, 4, 3); \
8990
0
    MCOperand_CreateImm0(MI, tmp); \
8991
0
    return S; \
8992
0
  case 175: \
8993
0
    tmp = fieldname(insn, 12, 4); \
8994
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8995
0
    tmp = fieldname(insn, 4, 4); \
8996
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8997
0
    return S; \
8998
0
  case 176: \
8999
0
    tmp = fieldname(insn, 4, 2); \
9000
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9001
0
    tmp = fieldname(insn, 8, 4); \
9002
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9003
0
    tmp = fieldname(insn, 8, 4); \
9004
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9005
0
    return S; \
9006
0
  case 177: \
9007
0
    tmp = fieldname(insn, 4, 2); \
9008
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9009
0
    tmp = fieldname(insn, 8, 4); \
9010
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9011
0
    return S; \
9012
0
  case 178: \
9013
0
    tmp = fieldname(insn, 4, 2); \
9014
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9015
0
    tmp = fieldname(insn, 4, 2); \
9016
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9017
0
    tmp = fieldname(insn, 8, 4); \
9018
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9019
0
    return S; \
9020
0
  case 179: \
9021
0
    tmp = fieldname(insn, 8, 4); \
9022
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9023
0
    tmp = fieldname(insn, 8, 4); \
9024
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9025
0
    tmp = fieldname(insn, 4, 4); \
9026
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9027
0
    return S; \
9028
0
  case 180: \
9029
0
    tmp = fieldname(insn, 8, 4); \
9030
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9031
0
    tmp = fieldname(insn, 8, 4); \
9032
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9033
0
    tmp = fieldname(insn, 4, 4); \
9034
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9035
0
    return S; \
9036
0
  case 181: \
9037
0
    tmp = fieldname(insn, 8, 4); \
9038
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9039
0
    tmp = fieldname(insn, 8, 4); \
9040
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9041
0
    return S; \
9042
0
  case 182: \
9043
0
    tmp = fieldname(insn, 12, 4); \
9044
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9045
0
    tmp = fieldname(insn, 4, 4); \
9046
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9047
0
    tmp = 0x0; \
9048
0
    tmp |= fieldname(insn, 8, 4) << 0; \
9049
0
    tmp |= fieldname(insn, 16, 2) << 4; \
9050
0
    MCOperand_CreateImm0(MI, tmp); \
9051
0
    return S; \
9052
0
  case 183: \
9053
0
    tmp = fieldname(insn, 12, 4); \
9054
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9055
0
    tmp = fieldname(insn, 4, 4); \
9056
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9057
0
    tmp = 0x0; \
9058
0
    tmp |= fieldname(insn, 8, 4) << 0; \
9059
0
    tmp |= fieldname(insn, 16, 1) << 4; \
9060
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9061
0
    return S; \
9062
0
  case 184: \
9063
0
    tmp = fieldname(insn, 12, 4); \
9064
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9065
0
    tmp = fieldname(insn, 8, 4); \
9066
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9067
0
    tmp = fieldname(insn, 4, 4); \
9068
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9069
0
    tmp = fieldname(insn, 16, 4); \
9070
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9071
0
    return S; \
9072
0
  case 185: \
9073
0
    tmp = fieldname(insn, 12, 4); \
9074
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9075
0
    tmp = fieldname(insn, 8, 4); \
9076
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9077
0
    tmp = fieldname(insn, 8, 4); \
9078
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9079
0
    tmp = fieldname(insn, 4, 4); \
9080
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9081
0
    return S; \
9082
0
  case 186: \
9083
0
    tmp = fieldname(insn, 12, 4); \
9084
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9085
0
    tmp = fieldname(insn, 8, 4); \
9086
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9087
0
    tmp = fieldname(insn, 4, 4); \
9088
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9089
0
    return S; \
9090
0
  case 187: \
9091
0
    tmp = fieldname(insn, 12, 4); \
9092
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9093
0
    tmp = fieldname(insn, 4, 4); \
9094
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9095
0
    tmp = fieldname(insn, 4, 4); \
9096
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9097
0
    tmp = fieldname(insn, 8, 4); \
9098
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9099
0
    return S; \
9100
0
  case 188: \
9101
0
    tmp = fieldname(insn, 12, 4); \
9102
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9103
0
    tmp = fieldname(insn, 4, 4); \
9104
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9105
0
    tmp = fieldname(insn, 16, 4); \
9106
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9107
0
    tmp = fieldname(insn, 8, 4); \
9108
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9109
0
    return S; \
9110
0
  case 189: \
9111
0
    tmp = fieldname(insn, 16, 4); \
9112
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9113
0
    tmp = fieldname(insn, 20, 4); \
9114
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9115
0
    tmp = fieldname(insn, 24, 4); \
9116
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9117
0
    return S; \
9118
0
  case 190: \
9119
0
    tmp = fieldname(insn, 16, 4); \
9120
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9121
0
    tmp = fieldname(insn, 16, 4); \
9122
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9123
0
    tmp = fieldname(insn, 20, 4); \
9124
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9125
0
    tmp = fieldname(insn, 24, 4); \
9126
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9127
0
    return S; \
9128
0
  case 191: \
9129
0
    tmp = fieldname(insn, 16, 4); \
9130
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9131
0
    tmp = fieldname(insn, 16, 4); \
9132
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9133
0
    tmp = fieldname(insn, 24, 4); \
9134
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9135
0
    tmp = fieldname(insn, 20, 4); \
9136
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9137
0
    return S; \
9138
0
  case 192: \
9139
0
    tmp = fieldname(insn, 16, 4); \
9140
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9141
0
    tmp = fieldname(insn, 24, 4); \
9142
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9143
0
    tmp = fieldname(insn, 20, 4); \
9144
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9145
0
    return S; \
9146
0
  case 193: \
9147
0
    tmp = fieldname(insn, 6, 2); \
9148
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9149
0
    tmp = fieldname(insn, 8, 4); \
9150
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9151
0
    tmp = fieldname(insn, 12, 4); \
9152
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9153
0
    tmp = fieldname(insn, 6, 2); \
9154
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9155
0
    tmp = fieldname(insn, 8, 4); \
9156
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9157
0
    return S; \
9158
0
  case 194: \
9159
0
    tmp = fieldname(insn, 12, 4); \
9160
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9161
0
    tmp = fieldname(insn, 6, 2); \
9162
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9163
0
    tmp = fieldname(insn, 8, 4); \
9164
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9165
0
    tmp = fieldname(insn, 6, 2); \
9166
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9167
0
    tmp = fieldname(insn, 8, 4); \
9168
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9169
0
    return S; \
9170
0
  case 195: \
9171
0
    tmp = fieldname(insn, 8, 4); \
9172
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9173
0
    tmp = fieldname(insn, 12, 4); \
9174
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9175
0
    tmp = fieldname(insn, 8, 4); \
9176
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9177
0
    return S; \
9178
0
  case 196: \
9179
0
    tmp = fieldname(insn, 6, 2); \
9180
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9181
0
    tmp = fieldname(insn, 8, 4); \
9182
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9183
0
    tmp = fieldname(insn, 8, 4); \
9184
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9185
0
    return S; \
9186
0
  case 197: \
9187
0
    tmp = fieldname(insn, 6, 2); \
9188
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9189
0
    tmp = fieldname(insn, 6, 2); \
9190
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9191
0
    tmp = fieldname(insn, 8, 4); \
9192
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9193
0
    return S; \
9194
0
  case 198: \
9195
0
    tmp = fieldname(insn, 6, 2); \
9196
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9197
0
    tmp = fieldname(insn, 8, 4); \
9198
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9199
0
    tmp = 0x0; \
9200
0
    tmp |= fieldname(insn, 4, 2) << 0; \
9201
0
    tmp |= fieldname(insn, 28, 2) << 2; \
9202
0
    MCOperand_CreateImm0(MI, tmp); \
9203
0
    return S; \
9204
0
  case 199: \
9205
0
    tmp = fieldname(insn, 12, 4); \
9206
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9207
0
    tmp = fieldname(insn, 4, 4); \
9208
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9209
0
    return S; \
9210
0
  case 200: \
9211
0
    tmp = fieldname(insn, 20, 4); \
9212
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9213
0
    tmp = fieldname(insn, 24, 4); \
9214
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9215
0
    tmp = fieldname(insn, 16, 4); \
9216
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9217
0
    return S; \
9218
0
  case 201: \
9219
0
    tmp = fieldname(insn, 20, 4); \
9220
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9221
0
    tmp = fieldname(insn, 16, 4); \
9222
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9223
0
    return S; \
9224
0
  case 202: \
9225
0
    tmp = fieldname(insn, 16, 4); \
9226
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9227
0
    tmp = fieldname(insn, 20, 4); \
9228
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9229
0
    tmp = fieldname(insn, 16, 4); \
9230
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9231
0
    tmp = fieldname(insn, 20, 4); \
9232
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9233
0
    tmp = fieldname(insn, 24, 4); \
9234
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9235
0
    tmp = fieldname(insn, 32, 4); \
9236
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9237
0
    tmp = fieldname(insn, 36, 4); \
9238
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9239
0
    return S; \
9240
0
  case 203: \
9241
0
    tmp = fieldname(insn, 16, 4); \
9242
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9243
0
    tmp = fieldname(insn, 24, 4); \
9244
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9245
0
    tmp = fieldname(insn, 32, 4); \
9246
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9247
0
    tmp = fieldname(insn, 48, 2); \
9248
0
    MCOperand_CreateImm0(MI, tmp); \
9249
0
    return S; \
9250
0
  case 204: \
9251
0
    tmp = fieldname(insn, 16, 4); \
9252
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9253
0
    tmp = fieldname(insn, 16, 4); \
9254
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9255
0
    tmp = fieldname(insn, 24, 4); \
9256
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9257
0
    tmp = fieldname(insn, 32, 4); \
9258
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9259
0
    return S; \
9260
0
  case 205: \
9261
0
    tmp = fieldname(insn, 16, 4); \
9262
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9263
0
    tmp = fieldname(insn, 24, 4); \
9264
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9265
0
    tmp = fieldname(insn, 32, 4); \
9266
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9267
0
    return S; \
9268
0
  case 206: \
9269
0
    tmp = fieldname(insn, 28, 4); \
9270
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9271
0
    tmp = fieldname(insn, 4, 4); \
9272
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9273
0
    tmp = fieldname(insn, 12, 4); \
9274
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9275
0
    tmp = fieldname(insn, 8, 4); \
9276
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9277
0
    return S; \
9278
0
  case 207: \
9279
0
    tmp = fieldname(insn, 28, 4); \
9280
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9281
0
    tmp = fieldname(insn, 4, 4); \
9282
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9283
0
    tmp = fieldname(insn, 12, 4); \
9284
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9285
0
    tmp = fieldname(insn, 8, 4); \
9286
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9287
0
    return S; \
9288
0
  case 208: \
9289
0
    tmp = fieldname(insn, 28, 4); \
9290
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9291
0
    tmp = fieldname(insn, 4, 4); \
9292
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9293
0
    tmp = fieldname(insn, 8, 4); \
9294
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9295
0
    return S; \
9296
0
  case 209: \
9297
0
    tmp = fieldname(insn, 16, 4); \
9298
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9299
0
    tmp = fieldname(insn, 32, 4); \
9300
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9301
0
    return S; \
9302
0
  case 210: \
9303
0
    tmp = fieldname(insn, 16, 4); \
9304
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9305
0
    tmp = fieldname(insn, 20, 4); \
9306
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9307
0
    tmp = fieldname(insn, 24, 4); \
9308
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9309
0
    tmp = fieldname(insn, 32, 4); \
9310
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9311
0
    tmp = fieldname(insn, 36, 4); \
9312
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9313
0
    return S; \
9314
0
  case 211: \
9315
0
    tmp = fieldname(insn, 20, 4); \
9316
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9317
0
    tmp = fieldname(insn, 28, 4); \
9318
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9319
0
    tmp = 0x0; \
9320
0
    tmp |= fieldname(insn, 36, 4) << 0; \
9321
0
    tmp |= fieldname(insn, 56, 2) << 4; \
9322
0
    MCOperand_CreateImm0(MI, tmp); \
9323
0
    return S; \
9324
0
  case 212: \
9325
0
    tmp = fieldname(insn, 20, 4); \
9326
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9327
0
    tmp = fieldname(insn, 16, 4); \
9328
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9329
0
    tmp = fieldname(insn, 32, 4); \
9330
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9331
0
    tmp = fieldname(insn, 24, 4); \
9332
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9333
0
    return S; \
9334
0
  case 213: \
9335
0
    tmp = fieldname(insn, 20, 4); \
9336
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9337
0
    tmp = fieldname(insn, 16, 4); \
9338
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9339
0
    tmp = fieldname(insn, 20, 4); \
9340
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9341
0
    tmp = fieldname(insn, 16, 4); \
9342
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9343
0
    tmp = fieldname(insn, 32, 4); \
9344
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9345
0
    tmp = fieldname(insn, 24, 4); \
9346
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9347
0
    return S; \
9348
0
  case 214: \
9349
0
    tmp = fieldname(insn, 20, 4); \
9350
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9351
0
    tmp = fieldname(insn, 28, 4); \
9352
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9353
0
    tmp = 0x0; \
9354
0
    tmp |= fieldname(insn, 36, 4) << 0; \
9355
0
    tmp |= fieldname(insn, 56, 1) << 4; \
9356
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9357
0
    return S; \
9358
0
  case 215: \
9359
0
    tmp = fieldname(insn, 20, 4); \
9360
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9361
0
    tmp = fieldname(insn, 36, 4); \
9362
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9363
0
    tmp = fieldname(insn, 28, 4); \
9364
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9365
0
    return S; \
9366
0
  case 216: \
9367
0
    tmp = fieldname(insn, 20, 4); \
9368
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9369
0
    tmp = fieldname(insn, 20, 4); \
9370
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9371
0
    tmp = fieldname(insn, 36, 4); \
9372
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9373
0
    tmp = fieldname(insn, 28, 4); \
9374
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9375
0
    return S; \
9376
0
  case 217: \
9377
0
    tmp = fieldname(insn, 20, 4); \
9378
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9379
0
    tmp = fieldname(insn, 28, 4); \
9380
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9381
0
    tmp = fieldname(insn, 36, 4); \
9382
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9383
0
    return S; \
9384
0
  case 218: \
9385
0
    tmp = fieldname(insn, 20, 4); \
9386
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9387
0
    tmp = fieldname(insn, 36, 4); \
9388
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9389
0
    tmp = fieldname(insn, 28, 4); \
9390
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9391
0
    return S; \
9392
0
  case 219: \
9393
0
    tmp = fieldname(insn, 20, 4); \
9394
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9395
0
    tmp = fieldname(insn, 20, 4); \
9396
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9397
0
    tmp = fieldname(insn, 36, 4); \
9398
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9399
0
    tmp = fieldname(insn, 28, 4); \
9400
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9401
0
    return S; \
9402
0
  case 220: \
9403
0
    tmp = fieldname(insn, 21, 3); \
9404
0
    if (!Check(&S, DecodeBR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9405
0
    tmp = fieldname(insn, 36, 4); \
9406
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9407
0
    tmp = fieldname(insn, 28, 4); \
9408
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9409
0
    return S; \
9410
0
  case 221: \
9411
0
    tmp = fieldname(insn, 22, 2); \
9412
0
    if (!Check(&S, DecodeBR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9413
0
    tmp = fieldname(insn, 36, 4); \
9414
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9415
0
    tmp = fieldname(insn, 28, 4); \
9416
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9417
0
    return S; \
9418
0
  case 222: \
9419
0
    tmp = fieldname(insn, 20, 4); \
9420
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9421
0
    tmp = fieldname(insn, 20, 4); \
9422
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9423
0
    tmp = fieldname(insn, 36, 4); \
9424
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9425
0
    tmp = fieldname(insn, 30, 2); \
9426
0
    if (!Check(&S, DecodeBR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9427
0
    return S; \
9428
0
  case 223: \
9429
0
    tmp = fieldname(insn, 20, 4); \
9430
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9431
0
    tmp = fieldname(insn, 20, 4); \
9432
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9433
0
    tmp = fieldname(insn, 36, 4); \
9434
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9435
0
    return S; \
9436
0
  case 224: \
9437
0
    tmp = fieldname(insn, 20, 4); \
9438
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9439
0
    tmp = fieldname(insn, 36, 4); \
9440
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9441
0
    return S; \
9442
0
  case 225: \
9443
0
    tmp = fieldname(insn, 20, 4); \
9444
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9445
0
    tmp = fieldname(insn, 28, 4); \
9446
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9447
0
    return S; \
9448
0
  case 226: \
9449
0
    tmp = fieldname(insn, 20, 4); \
9450
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9451
0
    tmp = fieldname(insn, 28, 4); \
9452
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9453
0
    tmp = fieldname(insn, 36, 4); \
9454
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9455
0
    return S; \
9456
35.0k
  } \
9457
35.0k
}
XtensaDisassembler.c:decodeToMCInst_4
Line
Count
Source
7098
6.30k
    uint64_t Address, const void *Decoder, bool *DecodeComplete) \
7099
6.30k
{ \
7100
6.30k
  *DecodeComplete = true; \
7101
6.30k
  InsnType tmp; \
7102
6.30k
  switch (Idx) { \
7103
0
  default: CS_ASSERT_RET_VAL(0 && "Invalid index!", MCDisassembler_Fail); \
7104
0
  case 0: \
7105
0
    tmp = fieldname(insn, 4, 4); \
7106
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7107
0
    tmp = fieldname(insn, 8, 8); \
7108
0
    if (!Check(&S, decodeMem32nOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7109
0
    return S; \
7110
0
  case 1: \
7111
0
    tmp = fieldname(insn, 12, 4); \
7112
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7113
0
    tmp = fieldname(insn, 8, 4); \
7114
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7115
0
    tmp = fieldname(insn, 4, 4); \
7116
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7117
0
    return S; \
7118
0
  case 2: \
7119
0
    tmp = fieldname(insn, 12, 4); \
7120
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7121
0
    tmp = fieldname(insn, 8, 4); \
7122
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7123
0
    tmp = fieldname(insn, 4, 4); \
7124
0
    if (!Check(&S, decodeImm1n_15Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7125
0
    return S; \
7126
0
  case 3: \
7127
0
    tmp = fieldname(insn, 8, 4); \
7128
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7129
0
    return S; \
7130
0
  case 4: \
7131
0
    tmp = fieldname(insn, 8, 4); \
7132
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7133
0
    tmp = 0x0; \
7134
0
    tmp |= fieldname(insn, 4, 3) << 4; \
7135
0
    tmp |= fieldname(insn, 12, 4) << 0; \
7136
0
    if (!Check(&S, decodeImm32n_95Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7137
0
    return S; \
7138
0
  case 5: \
7139
0
    tmp = fieldname(insn, 4, 4); \
7140
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7141
0
    tmp = fieldname(insn, 8, 4); \
7142
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7143
0
    return S; \
7144
0
  case 6: \
7145
0
    return S; \
7146
0
  case 7: \
7147
0
    tmp = fieldname(insn, 8, 4); \
7148
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7149
0
    return S; \
7150
0
  case 8: \
7151
0
    tmp = fieldname(insn, 8, 4); \
7152
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7153
0
    tmp = fieldname(insn, 4, 4); \
7154
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7155
0
    return S; \
7156
0
  case 9: \
7157
0
    tmp = fieldname(insn, 4, 4); \
7158
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7159
0
    tmp = fieldname(insn, 8, 4); \
7160
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7161
0
    return S; \
7162
0
  case 10: \
7163
0
    tmp = fieldname(insn, 4, 4); \
7164
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7165
0
    tmp = fieldname(insn, 8, 4); \
7166
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7167
0
    return S; \
7168
0
  case 11: \
7169
0
    tmp = fieldname(insn, 12, 4); \
7170
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7171
0
    tmp = fieldname(insn, 8, 4); \
7172
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7173
0
    tmp = 0x0; \
7174
0
    tmp |= fieldname(insn, 4, 4) << 0; \
7175
0
    tmp |= fieldname(insn, 20, 1) << 4; \
7176
0
    if (!Check(&S, decodeShimm1_31Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7177
0
    return S; \
7178
0
  case 12: \
7179
0
    tmp = fieldname(insn, 12, 4); \
7180
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7181
0
    tmp = fieldname(insn, 4, 4); \
7182
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7183
0
    tmp = 0x0; \
7184
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7185
0
    tmp |= fieldname(insn, 20, 1) << 4; \
7186
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7187
0
    return S; \
7188
0
  case 13: \
7189
0
    tmp = 0x0; \
7190
0
    tmp |= fieldname(insn, 4, 1) << 4; \
7191
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7192
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7193
0
    return S; \
7194
0
  case 14: \
7195
0
    tmp = fieldname(insn, 4, 4); \
7196
0
    if (!Check(&S, decodeImm8n_7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7197
0
    return S; \
7198
0
  case 15: \
7199
0
    tmp = fieldname(insn, 12, 4); \
7200
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7201
0
    tmp = fieldname(insn, 4, 4); \
7202
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7203
0
    tmp = fieldname(insn, 8, 4); \
7204
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7205
0
    return S; \
7206
0
  case 16: \
7207
0
    tmp = fieldname(insn, 12, 4); \
7208
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7209
0
    tmp = fieldname(insn, 4, 4); \
7210
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7211
0
    return S; \
7212
0
  case 17: \
7213
0
    tmp = fieldname(insn, 4, 4); \
7214
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7215
0
    tmp = fieldname(insn, 8, 8); \
7216
0
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7217
0
    tmp = fieldname(insn, 4, 4); \
7218
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7219
0
    tmp = fieldname(insn, 8, 8); \
7220
0
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7221
0
    return S; \
7222
0
  case 18: \
7223
0
    tmp = fieldname(insn, 12, 4); \
7224
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7225
0
    tmp = fieldname(insn, 8, 4); \
7226
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7227
0
    return S; \
7228
0
  case 19: \
7229
0
    tmp = fieldname(insn, 12, 4); \
7230
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7231
0
    tmp = fieldname(insn, 8, 4); \
7232
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7233
0
    tmp = fieldname(insn, 4, 4); \
7234
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7235
0
    return S; \
7236
0
  case 20: \
7237
0
    tmp = fieldname(insn, 4, 4); \
7238
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7239
0
    tmp = fieldname(insn, 8, 8); \
7240
0
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7241
0
    return S; \
7242
0
  case 21: \
7243
0
    tmp = fieldname(insn, 8, 8); \
7244
0
    if (!Check(&S, DecodeSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7245
0
    tmp = fieldname(insn, 4, 4); \
7246
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7247
0
    return S; \
7248
0
  case 22: \
7249
0
    tmp = fieldname(insn, 12, 4); \
7250
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7251
0
    tmp = fieldname(insn, 8, 4); \
7252
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7253
0
    tmp = fieldname(insn, 4, 4); \
7254
0
    if (!Check(&S, decodeImm7_22Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7255
0
    return S; \
7256
0
  case 23: \
7257
0
    tmp = fieldname(insn, 12, 4); \
7258
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7259
0
    tmp = fieldname(insn, 12, 4); \
7260
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7261
0
    tmp = fieldname(insn, 8, 4); \
7262
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7263
0
    tmp = fieldname(insn, 4, 4); \
7264
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7265
0
    return S; \
7266
0
  case 24: \
7267
0
    tmp = fieldname(insn, 12, 4); \
7268
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7269
0
    tmp = fieldname(insn, 4, 8); \
7270
0
    if (!Check(&S, DecodeURRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7271
0
    return S; \
7272
0
  case 25: \
7273
0
    tmp = fieldname(insn, 4, 4); \
7274
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7275
0
    return S; \
7276
0
  case 26: \
7277
0
    tmp = fieldname(insn, 8, 8); \
7278
0
    if (!Check(&S, DecodeURRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7279
0
    tmp = fieldname(insn, 4, 4); \
7280
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7281
0
    return S; \
7282
0
  case 27: \
7283
0
    tmp = fieldname(insn, 12, 4); \
7284
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7285
0
    tmp = fieldname(insn, 4, 4); \
7286
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7287
0
    tmp = 0x0; \
7288
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7289
0
    tmp |= fieldname(insn, 16, 1) << 4; \
7290
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7291
0
    tmp = fieldname(insn, 20, 4); \
7292
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7293
0
    return S; \
7294
0
  case 28: \
7295
0
    tmp = fieldname(insn, 4, 8); \
7296
0
    if (!Check(&S, decodeSelect_256Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7297
0
    return S; \
7298
0
  case 29: \
7299
0
    tmp = fieldname(insn, 8, 4); \
7300
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7301
0
    tmp = fieldname(insn, 4, 4); \
7302
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7303
0
    return S; \
7304
0
  case 30: \
7305
0
    tmp = fieldname(insn, 12, 4); \
7306
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7307
0
    tmp = fieldname(insn, 8, 4); \
7308
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7309
0
    tmp = fieldname(insn, 4, 4); \
7310
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7311
0
    return S; \
7312
0
  case 31: \
7313
0
    tmp = fieldname(insn, 4, 4); \
7314
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7315
0
    tmp = fieldname(insn, 8, 4); \
7316
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7317
0
    tmp = fieldname(insn, 12, 4) << 2; \
7318
0
    if (!Check(&S, decodeImm64n_4nOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7319
0
    return S; \
7320
0
  case 32: \
7321
0
    tmp = fieldname(insn, 12, 4); \
7322
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7323
0
    tmp = fieldname(insn, 8, 4); \
7324
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7325
0
    tmp = fieldname(insn, 8, 4); \
7326
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7327
0
    tmp = fieldname(insn, 4, 4); \
7328
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7329
0
    return S; \
7330
0
  case 33: \
7331
0
    tmp = fieldname(insn, 8, 4); \
7332
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7333
0
    tmp = fieldname(insn, 12, 4); \
7334
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7335
0
    tmp = fieldname(insn, 8, 4); \
7336
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7337
0
    tmp = fieldname(insn, 4, 4); \
7338
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7339
0
    return S; \
7340
0
  case 34: \
7341
0
    tmp = fieldname(insn, 12, 4); \
7342
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7343
0
    tmp = fieldname(insn, 8, 4); \
7344
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7345
0
    tmp = fieldname(insn, 4, 4); \
7346
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7347
0
    return S; \
7348
0
  case 35: \
7349
0
    tmp = fieldname(insn, 12, 4); \
7350
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7351
0
    tmp = fieldname(insn, 8, 4); \
7352
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7353
0
    tmp = fieldname(insn, 4, 4); \
7354
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7355
0
    return S; \
7356
0
  case 36: \
7357
0
    tmp = fieldname(insn, 12, 4); \
7358
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7359
0
    tmp = fieldname(insn, 12, 4); \
7360
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7361
0
    tmp = fieldname(insn, 8, 4); \
7362
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7363
0
    tmp = fieldname(insn, 4, 4); \
7364
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7365
0
    return S; \
7366
0
  case 37: \
7367
0
    tmp = fieldname(insn, 12, 4); \
7368
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7369
0
    tmp = fieldname(insn, 8, 4); \
7370
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7371
0
    tmp = fieldname(insn, 4, 4); \
7372
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7373
0
    return S; \
7374
0
  case 38: \
7375
0
    tmp = fieldname(insn, 12, 4); \
7376
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7377
0
    tmp = fieldname(insn, 12, 4); \
7378
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7379
0
    tmp = fieldname(insn, 8, 4); \
7380
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7381
0
    tmp = fieldname(insn, 4, 4); \
7382
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7383
0
    return S; \
7384
0
  case 39: \
7385
0
    tmp = fieldname(insn, 12, 4); \
7386
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7387
0
    tmp = fieldname(insn, 8, 4); \
7388
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7389
0
    tmp = fieldname(insn, 4, 4); \
7390
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7391
0
    return S; \
7392
0
  case 40: \
7393
0
    tmp = fieldname(insn, 12, 4); \
7394
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7395
0
    tmp = fieldname(insn, 12, 4); \
7396
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7397
0
    tmp = fieldname(insn, 8, 4); \
7398
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7399
0
    tmp = fieldname(insn, 4, 4); \
7400
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7401
0
    return S; \
7402
0
  case 41: \
7403
0
    tmp = fieldname(insn, 12, 4); \
7404
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7405
0
    tmp = fieldname(insn, 8, 4); \
7406
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7407
0
    return S; \
7408
0
  case 42: \
7409
0
    tmp = fieldname(insn, 12, 4); \
7410
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7411
0
    tmp = fieldname(insn, 8, 4); \
7412
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7413
0
    return S; \
7414
0
  case 43: \
7415
0
    tmp = fieldname(insn, 12, 4); \
7416
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7417
0
    tmp = fieldname(insn, 8, 4); \
7418
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7419
0
    return S; \
7420
0
  case 44: \
7421
0
    tmp = fieldname(insn, 12, 4); \
7422
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7423
0
    tmp = fieldname(insn, 8, 4); \
7424
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7425
0
    return S; \
7426
0
  case 45: \
7427
0
    tmp = fieldname(insn, 12, 4); \
7428
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7429
0
    tmp = fieldname(insn, 12, 4); \
7430
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7431
0
    tmp = fieldname(insn, 8, 4); \
7432
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7433
0
    return S; \
7434
0
  case 46: \
7435
0
    tmp = fieldname(insn, 4, 4); \
7436
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7437
0
    tmp = fieldname(insn, 8, 16); \
7438
0
    if (!Check(&S, decodeL32ROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7439
0
    return S; \
7440
0
  case 47: \
7441
0
    tmp = fieldname(insn, 4, 4); \
7442
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7443
0
    tmp = 0x0; \
7444
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7445
0
    tmp |= fieldname(insn, 16, 8) << 4; \
7446
0
    if (!Check(&S, decodeMem8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7447
0
    return S; \
7448
0
  case 48: \
7449
0
    tmp = fieldname(insn, 4, 4); \
7450
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7451
0
    tmp = 0x0; \
7452
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7453
0
    tmp |= fieldname(insn, 16, 8) << 4; \
7454
0
    if (!Check(&S, decodeMem16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7455
0
    return S; \
7456
0
  case 49: \
7457
0
    tmp = fieldname(insn, 4, 4); \
7458
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7459
0
    tmp = 0x0; \
7460
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7461
0
    tmp |= fieldname(insn, 16, 8) << 4; \
7462
0
    if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7463
0
    return S; \
7464
0
  case 50: \
7465
0
    tmp = fieldname(insn, 4, 4); \
7466
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7467
0
    tmp = 0x0; \
7468
0
    tmp |= fieldname(insn, 8, 4) << 8; \
7469
0
    tmp |= fieldname(insn, 16, 8) << 0; \
7470
0
    if (!Check(&S, decodeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7471
0
    return S; \
7472
0
  case 51: \
7473
0
    tmp = fieldname(insn, 4, 4); \
7474
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7475
0
    tmp = fieldname(insn, 8, 4); \
7476
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7477
0
    tmp = fieldname(insn, 16, 8); \
7478
0
    if (!Check(&S, decodeImm8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7479
0
    return S; \
7480
0
  case 52: \
7481
0
    tmp = fieldname(insn, 4, 4); \
7482
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7483
0
    tmp = fieldname(insn, 8, 4); \
7484
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7485
0
    tmp = fieldname(insn, 16, 8) << 8; \
7486
0
    if (!Check(&S, decodeImm8_sh8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7487
0
    return S; \
7488
0
  case 53: \
7489
0
    tmp = fieldname(insn, 4, 4); \
7490
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7491
0
    tmp = fieldname(insn, 4, 4); \
7492
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7493
0
    tmp = 0x0; \
7494
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7495
0
    tmp |= fieldname(insn, 16, 8) << 4; \
7496
0
    if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7497
0
    return S; \
7498
0
  case 54: \
7499
0
    tmp = fieldname(insn, 4, 4); \
7500
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7501
0
    tmp = 0x0; \
7502
0
    tmp |= fieldname(insn, 8, 4) << 0; \
7503
0
    tmp |= fieldname(insn, 16, 8) << 4; \
7504
0
    if (!Check(&S, decodeMem32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7505
0
    return S; \
7506
0
  case 55: \
7507
0
    tmp = fieldname(insn, 4, 4); \
7508
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7509
0
    tmp = fieldname(insn, 8, 4); \
7510
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7511
0
    tmp = fieldname(insn, 8, 4); \
7512
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7513
0
    tmp = fieldname(insn, 16, 8) << 2; \
7514
0
    if (!Check(&S, decodeOffset8m32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7515
0
    return S; \
7516
0
  case 56: \
7517
0
    tmp = fieldname(insn, 8, 4); \
7518
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7519
0
    tmp = fieldname(insn, 4, 4); \
7520
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7521
0
    tmp = fieldname(insn, 8, 4); \
7522
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7523
0
    tmp = fieldname(insn, 16, 8) << 2; \
7524
0
    if (!Check(&S, decodeOffset8m32Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7525
0
    return S; \
7526
0
  case 57: \
7527
0
    tmp = fieldname(insn, 12, 2); \
7528
0
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7529
0
    tmp = fieldname(insn, 8, 4); \
7530
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7531
0
    tmp = fieldname(insn, 8, 4); \
7532
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7533
0
    tmp = fieldname(insn, 14, 1); \
7534
0
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7535
0
    tmp = fieldname(insn, 6, 1); \
7536
0
    if (!Check(&S, DecodeMR23RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7537
0
    return S; \
7538
0
  case 58: \
7539
0
    tmp = fieldname(insn, 14, 1); \
7540
0
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7541
0
    tmp = fieldname(insn, 6, 1); \
7542
0
    if (!Check(&S, DecodeMR23RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7543
0
    return S; \
7544
0
  case 59: \
7545
0
    tmp = fieldname(insn, 8, 4); \
7546
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7547
0
    tmp = fieldname(insn, 6, 1); \
7548
0
    if (!Check(&S, DecodeMR23RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7549
0
    return S; \
7550
0
  case 60: \
7551
0
    tmp = fieldname(insn, 12, 2); \
7552
0
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7553
0
    tmp = fieldname(insn, 8, 4); \
7554
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7555
0
    tmp = fieldname(insn, 8, 4); \
7556
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7557
0
    tmp = fieldname(insn, 14, 1); \
7558
0
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7559
0
    tmp = fieldname(insn, 4, 4); \
7560
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7561
0
    return S; \
7562
0
  case 61: \
7563
0
    tmp = fieldname(insn, 12, 2); \
7564
0
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7565
0
    tmp = fieldname(insn, 8, 4); \
7566
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7567
0
    tmp = fieldname(insn, 8, 4); \
7568
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7569
0
    tmp = fieldname(insn, 14, 1); \
7570
0
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7571
0
    tmp = fieldname(insn, 4, 4); \
7572
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7573
0
    return S; \
7574
0
  case 62: \
7575
0
    tmp = fieldname(insn, 14, 1); \
7576
0
    if (!Check(&S, DecodeMR01RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7577
0
    tmp = fieldname(insn, 4, 4); \
7578
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7579
0
    return S; \
7580
0
  case 63: \
7581
0
    tmp = fieldname(insn, 12, 2); \
7582
0
    if (!Check(&S, DecodeMRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7583
0
    tmp = fieldname(insn, 8, 4); \
7584
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7585
0
    tmp = fieldname(insn, 8, 4); \
7586
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7587
0
    return S; \
7588
0
  case 64: \
7589
0
    tmp = fieldname(insn, 6, 18); \
7590
0
    if (!Check(&S, decodeCallOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7591
0
    return S; \
7592
0
  case 65: \
7593
0
    tmp = fieldname(insn, 6, 18); \
7594
0
    if (!Check(&S, decodeJumpOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7595
0
    return S; \
7596
0
  case 66: \
7597
0
    tmp = fieldname(insn, 8, 4); \
7598
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7599
0
    tmp = fieldname(insn, 12, 12); \
7600
0
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7601
0
    return S; \
7602
0
  case 67: \
7603
0
    tmp = fieldname(insn, 8, 4); \
7604
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7605
0
    tmp = fieldname(insn, 12, 4); \
7606
0
    if (!Check(&S, decodeB4constOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7607
0
    tmp = fieldname(insn, 16, 8); \
7608
0
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7609
0
    return S; \
7610
0
  case 68: \
7611
0
    tmp = fieldname(insn, 8, 4); \
7612
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7613
0
    tmp = fieldname(insn, 12, 12) << 3; \
7614
0
    if (!Check(&S, decodeEntry_Imm12OpValue(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7615
0
    return S; \
7616
0
  case 69: \
7617
0
    tmp = fieldname(insn, 8, 4); \
7618
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7619
0
    tmp = fieldname(insn, 16, 8); \
7620
0
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7621
0
    return S; \
7622
0
  case 70: \
7623
0
    tmp = fieldname(insn, 8, 4); \
7624
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7625
0
    tmp = fieldname(insn, 16, 8); \
7626
0
    if (!Check(&S, decodeLoopOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7627
0
    return S; \
7628
0
  case 71: \
7629
0
    tmp = fieldname(insn, 8, 4); \
7630
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7631
0
    tmp = fieldname(insn, 12, 4); \
7632
0
    if (!Check(&S, decodeB4constuOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7633
0
    tmp = fieldname(insn, 16, 8); \
7634
0
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7635
0
    return S; \
7636
0
  case 72: \
7637
0
    tmp = fieldname(insn, 8, 4); \
7638
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7639
0
    tmp = fieldname(insn, 4, 4); \
7640
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7641
0
    tmp = fieldname(insn, 16, 8); \
7642
0
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7643
0
    return S; \
7644
0
  case 73: \
7645
0
    tmp = fieldname(insn, 8, 4); \
7646
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7647
0
    tmp = 0x0; \
7648
0
    tmp |= fieldname(insn, 4, 4) << 0; \
7649
0
    tmp |= fieldname(insn, 12, 1) << 4; \
7650
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7651
0
    tmp = fieldname(insn, 16, 8); \
7652
0
    if (!Check(&S, decodeBranchOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7653
0
    return S; \
7654
0
  case 74: \
7655
0
    tmp = fieldname(insn, 4, 4); \
7656
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7657
0
    tmp = fieldname(insn, 4, 4); \
7658
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7659
0
    tmp = 0x0; \
7660
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7661
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7662
0
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7663
0
    return S; \
7664
0
  case 75: \
7665
0
    tmp = fieldname(insn, 4, 4); \
7666
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7667
0
    tmp = fieldname(insn, 4, 4); \
7668
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7669
0
    tmp = fieldname(insn, 8, 4); \
7670
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7671
0
    return S; \
7672
0
  case 76: \
7673
0
    tmp = 0x0; \
7674
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7675
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7676
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7677
0
    tmp = fieldname(insn, 4, 4); \
7678
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7679
0
    tmp = fieldname(insn, 4, 4); \
7680
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7681
0
    tmp = 0x0; \
7682
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7683
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7684
0
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7685
0
    return S; \
7686
0
  case 77: \
7687
0
    tmp = fieldname(insn, 4, 4); \
7688
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7689
0
    tmp = fieldname(insn, 4, 4); \
7690
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7691
0
    tmp = 0x0; \
7692
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7693
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7694
0
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7695
0
    return S; \
7696
0
  case 78: \
7697
0
    tmp = fieldname(insn, 4, 4); \
7698
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7699
0
    tmp = fieldname(insn, 4, 4); \
7700
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7701
0
    tmp = 0x0; \
7702
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7703
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7704
0
    if (!Check(&S, decodeOffset_256_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7705
0
    return S; \
7706
0
  case 79: \
7707
0
    tmp = 0x0; \
7708
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7709
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7710
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7711
0
    tmp = fieldname(insn, 4, 4); \
7712
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7713
0
    tmp = fieldname(insn, 4, 4); \
7714
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7715
0
    tmp = 0x0; \
7716
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7717
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7718
0
    if (!Check(&S, decodeOffset_256_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7719
0
    return S; \
7720
0
  case 80: \
7721
0
    tmp = fieldname(insn, 12, 4); \
7722
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7723
0
    return S; \
7724
0
  case 81: \
7725
0
    tmp = fieldname(insn, 4, 4); \
7726
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7727
0
    tmp = 0x0; \
7728
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7729
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7730
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7731
0
    tmp = fieldname(insn, 4, 4); \
7732
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7733
0
    tmp = 0x0; \
7734
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7735
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7736
0
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7737
0
    return S; \
7738
0
  case 82: \
7739
0
    tmp = 0x0; \
7740
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7741
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7742
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7743
0
    tmp = fieldname(insn, 4, 4); \
7744
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7745
0
    tmp = fieldname(insn, 4, 4); \
7746
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7747
0
    tmp = fieldname(insn, 8, 7); \
7748
0
    if (!Check(&S, decodeOffset_128_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7749
0
    return S; \
7750
0
  case 83: \
7751
0
    tmp = 0x0; \
7752
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7753
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7754
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7755
0
    tmp = fieldname(insn, 4, 4); \
7756
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7757
0
    tmp = fieldname(insn, 4, 4); \
7758
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7759
0
    tmp = fieldname(insn, 8, 7); \
7760
0
    if (!Check(&S, decodeOffset_128_1Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7761
0
    return S; \
7762
0
  case 84: \
7763
0
    tmp = fieldname(insn, 12, 4); \
7764
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7765
0
    tmp = fieldname(insn, 20, 4); \
7766
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7767
0
    tmp = fieldname(insn, 4, 4); \
7768
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7769
0
    tmp = fieldname(insn, 4, 4); \
7770
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7771
0
    tmp = fieldname(insn, 8, 4); \
7772
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7773
0
    return S; \
7774
0
  case 85: \
7775
0
    tmp = 0x0; \
7776
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7777
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7778
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7779
0
    tmp = fieldname(insn, 12, 3); \
7780
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7781
0
    tmp = fieldname(insn, 4, 4); \
7782
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7783
0
    tmp = 0x0; \
7784
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7785
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7786
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7787
0
    tmp = fieldname(insn, 12, 3); \
7788
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7789
0
    tmp = fieldname(insn, 4, 4); \
7790
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7791
0
    tmp = fieldname(insn, 8, 4); \
7792
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7793
0
    return S; \
7794
0
  case 86: \
7795
0
    tmp = fieldname(insn, 4, 4); \
7796
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7797
0
    tmp = fieldname(insn, 12, 4); \
7798
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7799
0
    tmp = fieldname(insn, 20, 4); \
7800
0
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7801
0
    tmp = fieldname(insn, 4, 4); \
7802
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7803
0
    tmp = fieldname(insn, 8, 4); \
7804
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7805
0
    return S; \
7806
0
  case 87: \
7807
0
    tmp = 0x0; \
7808
0
    tmp |= fieldname(insn, 13, 1) << 0; \
7809
0
    tmp |= fieldname(insn, 15, 1) << 1; \
7810
0
    tmp |= fieldname(insn, 20, 1) << 2; \
7811
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7812
0
    tmp = fieldname(insn, 4, 4); \
7813
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7814
0
    tmp = fieldname(insn, 4, 4); \
7815
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7816
0
    tmp = fieldname(insn, 8, 3); \
7817
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7818
0
    tmp = 0x0; \
7819
0
    tmp |= fieldname(insn, 11, 2) << 0; \
7820
0
    tmp |= fieldname(insn, 14, 1) << 2; \
7821
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7822
0
    return S; \
7823
0
  case 88: \
7824
0
    tmp = 0x0; \
7825
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7826
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7827
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7828
0
    tmp = fieldname(insn, 4, 4); \
7829
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7830
0
    tmp = fieldname(insn, 4, 4); \
7831
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7832
0
    tmp = 0x0; \
7833
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7834
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7835
0
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7836
0
    return S; \
7837
0
  case 89: \
7838
0
    tmp = fieldname(insn, 8, 3); \
7839
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7840
0
    tmp = 0x0; \
7841
0
    tmp |= fieldname(insn, 11, 2) << 0; \
7842
0
    tmp |= fieldname(insn, 14, 1) << 2; \
7843
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7844
0
    return S; \
7845
0
  case 90: \
7846
0
    tmp = fieldname(insn, 4, 4); \
7847
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7848
0
    tmp = 0x0; \
7849
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7850
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7851
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7852
0
    tmp = fieldname(insn, 4, 4); \
7853
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7854
0
    tmp = 0x0; \
7855
0
    tmp |= fieldname(insn, 8, 7) << 0; \
7856
0
    tmp |= fieldname(insn, 22, 1) << 7; \
7857
0
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7858
0
    return S; \
7859
0
  case 91: \
7860
0
    tmp = 0x0; \
7861
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7862
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7863
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7864
0
    tmp = fieldname(insn, 8, 3); \
7865
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7866
0
    tmp = 0x0; \
7867
0
    tmp |= fieldname(insn, 11, 2) << 0; \
7868
0
    tmp |= fieldname(insn, 14, 1) << 2; \
7869
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7870
0
    tmp = fieldname(insn, 4, 4); \
7871
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7872
0
    return S; \
7873
0
  case 92: \
7874
0
    tmp = 0x0; \
7875
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7876
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7877
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7878
0
    tmp = fieldname(insn, 12, 3); \
7879
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7880
0
    tmp = 0x0; \
7881
0
    tmp |= fieldname(insn, 4, 1) << 0; \
7882
0
    tmp |= fieldname(insn, 6, 2) << 1; \
7883
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7884
0
    tmp = 0x0; \
7885
0
    tmp |= fieldname(insn, 5, 1) << 0; \
7886
0
    tmp |= fieldname(insn, 10, 2) << 1; \
7887
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7888
0
    tmp = fieldname(insn, 8, 1); \
7889
0
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7890
0
    return S; \
7891
0
  case 93: \
7892
0
    tmp = 0x0; \
7893
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7894
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7895
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7896
0
    tmp = fieldname(insn, 12, 3); \
7897
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7898
0
    tmp = fieldname(insn, 4, 4); \
7899
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7900
0
    tmp = fieldname(insn, 4, 4); \
7901
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7902
0
    return S; \
7903
0
  case 94: \
7904
0
    tmp = fieldname(insn, 4, 3); \
7905
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7906
0
    tmp = fieldname(insn, 12, 3); \
7907
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7908
0
    tmp = 0x0; \
7909
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7910
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7911
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7912
0
    return S; \
7913
0
  case 95: \
7914
0
    tmp = fieldname(insn, 12, 3); \
7915
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7916
0
    tmp = 0x0; \
7917
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7918
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7919
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7920
0
    tmp = fieldname(insn, 12, 3); \
7921
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7922
0
    tmp = 0x0; \
7923
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7924
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7925
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7926
0
    return S; \
7927
0
  case 96: \
7928
0
    tmp = 0x0; \
7929
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7930
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7931
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7932
0
    tmp = fieldname(insn, 12, 3); \
7933
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7934
0
    tmp = 0x0; \
7935
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7936
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7937
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7938
0
    tmp = fieldname(insn, 12, 3); \
7939
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7940
0
    tmp = fieldname(insn, 4, 4); \
7941
0
    if (!Check(&S, decodeSelect_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7942
0
    return S; \
7943
0
  case 97: \
7944
0
    tmp = fieldname(insn, 4, 3); \
7945
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7946
0
    tmp = fieldname(insn, 12, 3); \
7947
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7948
0
    tmp = fieldname(insn, 12, 3); \
7949
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7950
0
    tmp = 0x0; \
7951
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7952
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7953
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7954
0
    return S; \
7955
0
  case 98: \
7956
0
    tmp = fieldname(insn, 4, 4); \
7957
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7958
0
    tmp = fieldname(insn, 12, 3); \
7959
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7960
0
    tmp = 0x0; \
7961
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7962
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7963
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7964
0
    tmp = fieldname(insn, 4, 4); \
7965
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7966
0
    return S; \
7967
0
  case 99: \
7968
0
    tmp = 0x0; \
7969
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7970
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7971
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7972
0
    tmp = fieldname(insn, 4, 4); \
7973
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7974
0
    tmp = fieldname(insn, 4, 4); \
7975
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7976
0
    tmp = fieldname(insn, 8, 4); \
7977
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7978
0
    return S; \
7979
0
  case 100: \
7980
0
    tmp = fieldname(insn, 4, 4); \
7981
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7982
0
    tmp = 0x0; \
7983
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7984
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7985
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7986
0
    tmp = fieldname(insn, 4, 4); \
7987
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7988
0
    tmp = fieldname(insn, 8, 4); \
7989
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7990
0
    return S; \
7991
0
  case 101: \
7992
0
    tmp = 0x0; \
7993
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7994
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7995
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
7996
0
    tmp = 0x0; \
7997
0
    tmp |= fieldname(insn, 15, 1) << 0; \
7998
0
    tmp |= fieldname(insn, 20, 2) << 1; \
7999
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8000
0
    tmp = fieldname(insn, 8, 4); \
8001
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8002
0
    tmp = fieldname(insn, 4, 4); \
8003
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8004
0
    return S; \
8005
0
  case 102: \
8006
0
    tmp = 0x0; \
8007
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8008
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8009
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8010
0
    tmp = 0x0; \
8011
0
    tmp |= fieldname(insn, 4, 1) << 0; \
8012
0
    tmp |= fieldname(insn, 6, 2) << 1; \
8013
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8014
0
    tmp = 0x0; \
8015
0
    tmp |= fieldname(insn, 5, 1) << 0; \
8016
0
    tmp |= fieldname(insn, 10, 2) << 1; \
8017
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8018
0
    return S; \
8019
0
  case 103: \
8020
0
    tmp = 0x0; \
8021
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8022
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8023
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8024
0
    tmp = fieldname(insn, 4, 4); \
8025
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8026
0
    tmp = fieldname(insn, 10, 2); \
8027
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8028
0
    return S; \
8029
0
  case 104: \
8030
0
    tmp = fieldname(insn, 4, 4); \
8031
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8032
0
    tmp = 0x0; \
8033
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8034
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8035
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8036
0
    tmp = fieldname(insn, 4, 4); \
8037
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8038
0
    tmp = fieldname(insn, 10, 1); \
8039
0
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8040
0
    return S; \
8041
0
  case 105: \
8042
0
    tmp = 0x0; \
8043
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8044
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8045
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8046
0
    tmp = fieldname(insn, 4, 4); \
8047
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8048
0
    return S; \
8049
0
  case 106: \
8050
0
    tmp = fieldname(insn, 4, 3); \
8051
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8052
0
    tmp = 0x0; \
8053
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8054
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8055
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8056
0
    return S; \
8057
0
  case 107: \
8058
0
    tmp = fieldname(insn, 4, 4); \
8059
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8060
0
    tmp = 0x0; \
8061
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8062
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8063
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8064
0
    tmp = fieldname(insn, 10, 2); \
8065
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8066
0
    return S; \
8067
0
  case 108: \
8068
0
    tmp = 0x0; \
8069
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8070
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8071
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8072
0
    tmp = fieldname(insn, 4, 4); \
8073
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8074
0
    tmp = fieldname(insn, 10, 1); \
8075
0
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8076
0
    return S; \
8077
0
  case 109: \
8078
0
    tmp = 0x0; \
8079
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8080
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8081
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8082
0
    tmp = fieldname(insn, 4, 4); \
8083
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8084
0
    tmp = fieldname(insn, 4, 4); \
8085
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8086
0
    return S; \
8087
0
  case 110: \
8088
0
    tmp = 0x0; \
8089
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8090
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8091
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8092
0
    tmp = 0x0; \
8093
0
    tmp |= fieldname(insn, 4, 1) << 0; \
8094
0
    tmp |= fieldname(insn, 6, 2) << 1; \
8095
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8096
0
    return S; \
8097
0
  case 111: \
8098
0
    tmp = 0x0; \
8099
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8100
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8101
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8102
0
    return S; \
8103
0
  case 112: \
8104
0
    tmp = fieldname(insn, 8, 4); \
8105
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8106
0
    tmp = fieldname(insn, 4, 4); \
8107
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8108
0
    tmp = fieldname(insn, 14, 1); \
8109
0
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8110
0
    return S; \
8111
0
  case 113: \
8112
0
    tmp = 0x0; \
8113
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8114
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8115
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8116
0
    tmp = fieldname(insn, 8, 3); \
8117
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8118
0
    tmp = 0x0; \
8119
0
    tmp |= fieldname(insn, 11, 2) << 0; \
8120
0
    tmp |= fieldname(insn, 14, 1) << 2; \
8121
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8122
0
    tmp = fieldname(insn, 4, 2); \
8123
0
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8124
0
    return S; \
8125
0
  case 114: \
8126
0
    tmp = 0x0; \
8127
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8128
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8129
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8130
0
    tmp = fieldname(insn, 8, 3); \
8131
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8132
0
    tmp = 0x0; \
8133
0
    tmp |= fieldname(insn, 11, 2) << 0; \
8134
0
    tmp |= fieldname(insn, 14, 1) << 2; \
8135
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8136
0
    return S; \
8137
0
  case 115: \
8138
0
    tmp = fieldname(insn, 8, 3); \
8139
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8140
0
    tmp = 0x0; \
8141
0
    tmp |= fieldname(insn, 11, 2) << 0; \
8142
0
    tmp |= fieldname(insn, 14, 1) << 2; \
8143
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8144
0
    tmp = 0x0; \
8145
0
    tmp |= fieldname(insn, 4, 1) << 0; \
8146
0
    tmp |= fieldname(insn, 15, 1) << 1; \
8147
0
    tmp |= fieldname(insn, 20, 2) << 2; \
8148
0
    if (!Check(&S, decodeSelect_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8149
0
    return S; \
8150
0
  case 116: \
8151
0
    tmp = fieldname(insn, 8, 3); \
8152
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8153
0
    tmp = 0x0; \
8154
0
    tmp |= fieldname(insn, 11, 2) << 0; \
8155
0
    tmp |= fieldname(insn, 14, 1) << 2; \
8156
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8157
0
    tmp = 0x0; \
8158
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8159
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8160
0
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8161
0
    return S; \
8162
0
  case 117: \
8163
0
    tmp = 0x0; \
8164
0
    tmp |= fieldname(insn, 15, 1) << 0; \
8165
0
    tmp |= fieldname(insn, 20, 2) << 1; \
8166
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8167
0
    tmp = 0x0; \
8168
0
    tmp |= fieldname(insn, 5, 1) << 0; \
8169
0
    tmp |= fieldname(insn, 10, 2) << 1; \
8170
0
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8171
0
    return S; \
8172
1.74k
  case 118: \
8173
1.74k
    tmp = 0x0; \
8174
1.74k
    tmp |= fieldname(insn, 19, 1) << 0; \
8175
1.74k
    tmp |= fieldname(insn, 24, 2) << 1; \
8176
1.74k
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8177
1.74k
    tmp = fieldname(insn, 4, 4); \
8178
1.74k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8179
1.74k
    tmp = fieldname(insn, 20, 3); \
8180
1.74k
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8181
1.74k
    tmp = fieldname(insn, 4, 4); \
8182
1.74k
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8183
1.74k
    tmp = 0x0; \
8184
1.74k
    tmp |= fieldname(insn, 8, 4) << 0; \
8185
1.74k
    tmp |= fieldname(insn, 26, 2) << 4; \
8186
1.74k
    if (!Check(&S, decodeOffset_64_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8187
1.74k
    tmp = 0x0; \
8188
1.74k
    tmp |= fieldname(insn, 0, 1) << 2; \
8189
1.74k
    tmp |= fieldname(insn, 14, 2) << 0; \
8190
1.74k
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8191
1.74k
    tmp = 0x0; \
8192
1.74k
    tmp |= fieldname(insn, 12, 2) << 1; \
8193
1.74k
    tmp |= fieldname(insn, 23, 1) << 0; \
8194
1.74k
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8195
1.74k
    tmp = fieldname(insn, 20, 3); \
8196
1.74k
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8197
1.74k
    tmp = fieldname(insn, 16, 3); \
8198
1.74k
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8199
1.74k
    return S; \
8200
1.74k
  case 119: \
8201
241
    tmp = 0x0; \
8202
241
    tmp |= fieldname(insn, 19, 1) << 0; \
8203
241
    tmp |= fieldname(insn, 24, 3) << 1; \
8204
241
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8205
241
    tmp = 0x0; \
8206
241
    tmp |= fieldname(insn, 0, 1) << 0; \
8207
241
    tmp |= fieldname(insn, 16, 3) << 1; \
8208
241
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8209
241
    tmp = fieldname(insn, 12, 4); \
8210
241
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8211
241
    tmp = fieldname(insn, 20, 4); \
8212
241
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8213
241
    tmp = fieldname(insn, 4, 4); \
8214
241
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8215
241
    tmp = fieldname(insn, 4, 4); \
8216
241
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8217
241
    tmp = fieldname(insn, 8, 4); \
8218
241
    if (!Check(&S, decodeOffset_16_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8219
241
    return S; \
8220
241
  case 120: \
8221
196
    tmp = 0x0; \
8222
196
    tmp |= fieldname(insn, 19, 1) << 0; \
8223
196
    tmp |= fieldname(insn, 24, 3) << 1; \
8224
196
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8225
196
    tmp = 0x0; \
8226
196
    tmp |= fieldname(insn, 0, 1) << 0; \
8227
196
    tmp |= fieldname(insn, 16, 3) << 1; \
8228
196
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8229
196
    tmp = fieldname(insn, 12, 4); \
8230
196
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8231
196
    tmp = fieldname(insn, 20, 4); \
8232
196
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8233
196
    tmp = fieldname(insn, 4, 4); \
8234
196
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8235
196
    tmp = fieldname(insn, 4, 4); \
8236
196
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8237
196
    tmp = fieldname(insn, 8, 4); \
8238
196
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8239
196
    return S; \
8240
196
  case 121: \
8241
165
    tmp = fieldname(insn, 4, 4); \
8242
165
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8243
165
    tmp = 0x0; \
8244
165
    tmp |= fieldname(insn, 19, 1) << 0; \
8245
165
    tmp |= fieldname(insn, 24, 3) << 1; \
8246
165
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8247
165
    tmp = 0x0; \
8248
165
    tmp |= fieldname(insn, 0, 1) << 0; \
8249
165
    tmp |= fieldname(insn, 16, 3) << 1; \
8250
165
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8251
165
    tmp = fieldname(insn, 12, 4); \
8252
165
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8253
165
    tmp = fieldname(insn, 20, 4); \
8254
165
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8255
165
    tmp = fieldname(insn, 4, 4); \
8256
165
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8257
165
    tmp = fieldname(insn, 8, 4); \
8258
165
    if (!Check(&S, decodeOffset_16_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8259
165
    return S; \
8260
385
  case 122: \
8261
385
    tmp = fieldname(insn, 4, 4); \
8262
385
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8263
385
    tmp = 0x0; \
8264
385
    tmp |= fieldname(insn, 19, 1) << 0; \
8265
385
    tmp |= fieldname(insn, 24, 3) << 1; \
8266
385
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8267
385
    tmp = 0x0; \
8268
385
    tmp |= fieldname(insn, 0, 1) << 0; \
8269
385
    tmp |= fieldname(insn, 16, 3) << 1; \
8270
385
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8271
385
    tmp = fieldname(insn, 12, 4); \
8272
385
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8273
385
    tmp = fieldname(insn, 20, 4); \
8274
385
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8275
385
    tmp = fieldname(insn, 4, 4); \
8276
385
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8277
385
    tmp = fieldname(insn, 8, 4); \
8278
385
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8279
385
    return S; \
8280
385
  case 123: \
8281
270
    tmp = 0x0; \
8282
270
    tmp |= fieldname(insn, 19, 1) << 0; \
8283
270
    tmp |= fieldname(insn, 24, 2) << 1; \
8284
270
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8285
270
    tmp = fieldname(insn, 4, 4); \
8286
270
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8287
270
    tmp = fieldname(insn, 8, 4); \
8288
270
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8289
270
    tmp = fieldname(insn, 20, 3); \
8290
270
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8291
270
    tmp = fieldname(insn, 4, 4); \
8292
270
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8293
270
    tmp = fieldname(insn, 8, 4); \
8294
270
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8295
270
    tmp = fieldname(insn, 16, 3); \
8296
270
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8297
270
    tmp = 0x0; \
8298
270
    tmp |= fieldname(insn, 0, 1) << 2; \
8299
270
    tmp |= fieldname(insn, 14, 2) << 0; \
8300
270
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8301
270
    tmp = 0x0; \
8302
270
    tmp |= fieldname(insn, 12, 2) << 1; \
8303
270
    tmp |= fieldname(insn, 23, 1) << 0; \
8304
270
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8305
270
    tmp = fieldname(insn, 26, 1); \
8306
270
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8307
270
    return S; \
8308
775
  case 124: \
8309
775
    tmp = fieldname(insn, 4, 4); \
8310
775
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8311
775
    tmp = 0x0; \
8312
775
    tmp |= fieldname(insn, 0, 1) << 2; \
8313
775
    tmp |= fieldname(insn, 14, 2) << 0; \
8314
775
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8315
775
    tmp = fieldname(insn, 20, 3); \
8316
775
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8317
775
    tmp = fieldname(insn, 16, 3); \
8318
775
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8319
775
    tmp = fieldname(insn, 4, 4); \
8320
775
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8321
775
    tmp = fieldname(insn, 8, 4); \
8322
775
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8323
775
    tmp = 0x0; \
8324
775
    tmp |= fieldname(insn, 12, 2) << 1; \
8325
775
    tmp |= fieldname(insn, 23, 1) << 0; \
8326
775
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8327
775
    tmp = 0x0; \
8328
775
    tmp |= fieldname(insn, 19, 1) << 0; \
8329
775
    tmp |= fieldname(insn, 24, 1) << 1; \
8330
775
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8331
775
    tmp = fieldname(insn, 25, 2); \
8332
775
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8333
775
    return S; \
8334
775
  case 125: \
8335
729
    tmp = 0x0; \
8336
729
    tmp |= fieldname(insn, 19, 1) << 0; \
8337
729
    tmp |= fieldname(insn, 24, 2) << 1; \
8338
729
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8339
729
    tmp = fieldname(insn, 4, 4); \
8340
729
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8341
729
    tmp = fieldname(insn, 20, 3); \
8342
729
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8343
729
    tmp = fieldname(insn, 4, 4); \
8344
729
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8345
729
    tmp = fieldname(insn, 8, 4); \
8346
729
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8347
729
    tmp = 0x0; \
8348
729
    tmp |= fieldname(insn, 0, 1) << 2; \
8349
729
    tmp |= fieldname(insn, 14, 2) << 0; \
8350
729
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8351
729
    tmp = 0x0; \
8352
729
    tmp |= fieldname(insn, 12, 2) << 1; \
8353
729
    tmp |= fieldname(insn, 23, 1) << 0; \
8354
729
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8355
729
    tmp = fieldname(insn, 20, 3); \
8356
729
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8357
729
    tmp = fieldname(insn, 16, 3); \
8358
729
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8359
729
    return S; \
8360
729
  case 126: \
8361
147
    tmp = fieldname(insn, 8, 3); \
8362
147
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8363
147
    tmp = fieldname(insn, 4, 4); \
8364
147
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8365
147
    tmp = 0x0; \
8366
147
    tmp |= fieldname(insn, 12, 2) << 1; \
8367
147
    tmp |= fieldname(insn, 23, 1) << 0; \
8368
147
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8369
147
    tmp = 0x0; \
8370
147
    tmp |= fieldname(insn, 11, 1) << 0; \
8371
147
    tmp |= fieldname(insn, 19, 1) << 1; \
8372
147
    tmp |= fieldname(insn, 24, 1) << 2; \
8373
147
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8374
147
    tmp = fieldname(insn, 4, 4); \
8375
147
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8376
147
    tmp = 0x0; \
8377
147
    tmp |= fieldname(insn, 0, 1) << 2; \
8378
147
    tmp |= fieldname(insn, 14, 2) << 0; \
8379
147
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8380
147
    tmp = fieldname(insn, 20, 3); \
8381
147
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8382
147
    tmp = fieldname(insn, 16, 3); \
8383
147
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8384
147
    tmp = fieldname(insn, 25, 1); \
8385
147
    if (!Check(&S, decodeSelect_2Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8386
147
    return S; \
8387
440
  case 127: \
8388
440
    tmp = 0x0; \
8389
440
    tmp |= fieldname(insn, 12, 2) << 1; \
8390
440
    tmp |= fieldname(insn, 23, 1) << 0; \
8391
440
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8392
440
    tmp = fieldname(insn, 4, 4); \
8393
440
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8394
440
    tmp = fieldname(insn, 16, 3); \
8395
440
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8396
440
    tmp = fieldname(insn, 4, 4); \
8397
440
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8398
440
    tmp = fieldname(insn, 8, 4); \
8399
440
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8400
440
    tmp = 0x0; \
8401
440
    tmp |= fieldname(insn, 0, 1) << 2; \
8402
440
    tmp |= fieldname(insn, 14, 2) << 0; \
8403
440
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8404
440
    tmp = fieldname(insn, 20, 3); \
8405
440
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8406
440
    tmp = 0x0; \
8407
440
    tmp |= fieldname(insn, 19, 1) << 0; \
8408
440
    tmp |= fieldname(insn, 24, 2) << 1; \
8409
440
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8410
440
    return S; \
8411
440
  case 128: \
8412
85
    tmp = fieldname(insn, 16, 3); \
8413
85
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8414
85
    tmp = fieldname(insn, 4, 4); \
8415
85
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8416
85
    tmp = 0x0; \
8417
85
    tmp |= fieldname(insn, 0, 1) << 2; \
8418
85
    tmp |= fieldname(insn, 14, 2) << 0; \
8419
85
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8420
85
    tmp = fieldname(insn, 4, 4); \
8421
85
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8422
85
    tmp = 0x0; \
8423
85
    tmp |= fieldname(insn, 8, 2) << 0; \
8424
85
    tmp |= fieldname(insn, 12, 2) << 3; \
8425
85
    tmp |= fieldname(insn, 19, 1) << 5; \
8426
85
    tmp |= fieldname(insn, 23, 1) << 2; \
8427
85
    tmp |= fieldname(insn, 24, 2) << 6; \
8428
85
    if (!Check(&S, decodeOffset_256_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8429
85
    tmp = 0x0; \
8430
85
    tmp |= fieldname(insn, 0, 1) << 2; \
8431
85
    tmp |= fieldname(insn, 14, 2) << 0; \
8432
85
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8433
85
    tmp = fieldname(insn, 20, 3); \
8434
85
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8435
85
    return S; \
8436
85
  case 129: \
8437
23
    tmp = fieldname(insn, 12, 4); \
8438
23
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8439
23
    tmp = fieldname(insn, 20, 4); \
8440
23
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8441
23
    tmp = fieldname(insn, 4, 4); \
8442
23
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8443
23
    tmp = fieldname(insn, 4, 4); \
8444
23
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8445
23
    tmp = 0x0; \
8446
23
    tmp |= fieldname(insn, 0, 1) << 1; \
8447
23
    tmp |= fieldname(insn, 8, 1) << 0; \
8448
23
    tmp |= fieldname(insn, 16, 4) << 2; \
8449
23
    tmp |= fieldname(insn, 24, 2) << 6; \
8450
23
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8451
23
    return S; \
8452
182
  case 130: \
8453
182
    tmp = fieldname(insn, 4, 4); \
8454
182
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8455
182
    tmp = fieldname(insn, 12, 4); \
8456
182
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8457
182
    tmp = fieldname(insn, 20, 4); \
8458
182
    if (!Check(&S, DecodeFPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8459
182
    tmp = fieldname(insn, 4, 4); \
8460
182
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8461
182
    tmp = 0x0; \
8462
182
    tmp |= fieldname(insn, 0, 1) << 1; \
8463
182
    tmp |= fieldname(insn, 8, 1) << 0; \
8464
182
    tmp |= fieldname(insn, 16, 4) << 2; \
8465
182
    tmp |= fieldname(insn, 24, 2) << 6; \
8466
182
    if (!Check(&S, decodeOffset_256_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8467
182
    return S; \
8468
182
  case 131: \
8469
41
    tmp = 0x0; \
8470
41
    tmp |= fieldname(insn, 19, 1) << 0; \
8471
41
    tmp |= fieldname(insn, 24, 2) << 1; \
8472
41
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8473
41
    tmp = fieldname(insn, 4, 4); \
8474
41
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8475
41
    tmp = fieldname(insn, 20, 3); \
8476
41
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8477
41
    tmp = fieldname(insn, 4, 4); \
8478
41
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8479
41
    tmp = 0x0; \
8480
41
    tmp |= fieldname(insn, 0, 1) << 2; \
8481
41
    tmp |= fieldname(insn, 14, 2) << 0; \
8482
41
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8483
41
    tmp = 0x0; \
8484
41
    tmp |= fieldname(insn, 12, 2) << 1; \
8485
41
    tmp |= fieldname(insn, 23, 1) << 0; \
8486
41
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8487
41
    tmp = fieldname(insn, 20, 3); \
8488
41
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8489
41
    tmp = fieldname(insn, 16, 3); \
8490
41
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8491
41
    return S; \
8492
41
  case 132: \
8493
9
    tmp = 0x0; \
8494
9
    tmp |= fieldname(insn, 19, 1) << 0; \
8495
9
    tmp |= fieldname(insn, 24, 2) << 1; \
8496
9
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8497
9
    tmp = fieldname(insn, 4, 4); \
8498
9
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8499
9
    tmp = fieldname(insn, 16, 3); \
8500
9
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8501
9
    tmp = fieldname(insn, 4, 4); \
8502
9
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8503
9
    tmp = 0x0; \
8504
9
    tmp |= fieldname(insn, 0, 1) << 2; \
8505
9
    tmp |= fieldname(insn, 14, 2) << 0; \
8506
9
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8507
9
    tmp = 0x0; \
8508
9
    tmp |= fieldname(insn, 12, 2) << 1; \
8509
9
    tmp |= fieldname(insn, 23, 1) << 0; \
8510
9
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8511
9
    tmp = fieldname(insn, 8, 2); \
8512
9
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8513
9
    return S; \
8514
49
  case 133: \
8515
49
    tmp = 0x0; \
8516
49
    tmp |= fieldname(insn, 19, 1) << 0; \
8517
49
    tmp |= fieldname(insn, 24, 2) << 1; \
8518
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8519
49
    tmp = fieldname(insn, 4, 4); \
8520
49
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8521
49
    tmp = fieldname(insn, 16, 3); \
8522
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8523
49
    tmp = fieldname(insn, 4, 4); \
8524
49
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8525
49
    tmp = 0x0; \
8526
49
    tmp |= fieldname(insn, 0, 1) << 2; \
8527
49
    tmp |= fieldname(insn, 14, 2) << 0; \
8528
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8529
49
    tmp = 0x0; \
8530
49
    tmp |= fieldname(insn, 12, 2) << 1; \
8531
49
    tmp |= fieldname(insn, 23, 1) << 0; \
8532
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8533
49
    return S; \
8534
49
  case 134: \
8535
18
    tmp = 0x0; \
8536
18
    tmp |= fieldname(insn, 19, 1) << 0; \
8537
18
    tmp |= fieldname(insn, 24, 2) << 1; \
8538
18
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8539
18
    tmp = fieldname(insn, 4, 4); \
8540
18
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8541
18
    tmp = fieldname(insn, 4, 4); \
8542
18
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8543
18
    tmp = 0x0; \
8544
18
    tmp |= fieldname(insn, 0, 1) << 2; \
8545
18
    tmp |= fieldname(insn, 14, 2) << 0; \
8546
18
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8547
18
    tmp = 0x0; \
8548
18
    tmp |= fieldname(insn, 12, 2) << 1; \
8549
18
    tmp |= fieldname(insn, 23, 1) << 0; \
8550
18
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8551
18
    tmp = 0x0; \
8552
18
    tmp |= fieldname(insn, 16, 3) << 1; \
8553
18
    tmp |= fieldname(insn, 20, 1) << 0; \
8554
18
    if (!Check(&S, decodeSelect_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8555
18
    return S; \
8556
60
  case 135: \
8557
60
    tmp = 0x0; \
8558
60
    tmp |= fieldname(insn, 19, 1) << 0; \
8559
60
    tmp |= fieldname(insn, 24, 2) << 1; \
8560
60
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8561
60
    tmp = fieldname(insn, 4, 4); \
8562
60
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8563
60
    tmp = fieldname(insn, 4, 4); \
8564
60
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8565
60
    tmp = 0x0; \
8566
60
    tmp |= fieldname(insn, 0, 1) << 2; \
8567
60
    tmp |= fieldname(insn, 14, 2) << 0; \
8568
60
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8569
60
    tmp = 0x0; \
8570
60
    tmp |= fieldname(insn, 12, 2) << 1; \
8571
60
    tmp |= fieldname(insn, 23, 1) << 0; \
8572
60
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8573
60
    tmp = fieldname(insn, 16, 3); \
8574
60
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8575
60
    return S; \
8576
60
  case 136: \
8577
49
    tmp = fieldname(insn, 16, 3); \
8578
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8579
49
    tmp = 0x0; \
8580
49
    tmp |= fieldname(insn, 0, 1) << 2; \
8581
49
    tmp |= fieldname(insn, 14, 2) << 0; \
8582
49
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8583
49
    tmp = fieldname(insn, 4, 4); \
8584
49
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8585
49
    tmp = 0x0; \
8586
49
    tmp |= fieldname(insn, 19, 1) << 0; \
8587
49
    tmp |= fieldname(insn, 24, 1) << 1; \
8588
49
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8589
49
    tmp = 0x0; \
8590
49
    tmp |= fieldname(insn, 12, 2) << 1; \
8591
49
    tmp |= fieldname(insn, 23, 1) << 0; \
8592
49
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8593
49
    return S; \
8594
49
  case 137: \
8595
15
    tmp = fieldname(insn, 4, 4); \
8596
15
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8597
15
    tmp = fieldname(insn, 16, 3); \
8598
15
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8599
15
    tmp = fieldname(insn, 20, 3); \
8600
15
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8601
15
    tmp = fieldname(insn, 4, 4); \
8602
15
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8603
15
    tmp = 0x0; \
8604
15
    tmp |= fieldname(insn, 0, 1) << 2; \
8605
15
    tmp |= fieldname(insn, 14, 2) << 0; \
8606
15
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8607
15
    tmp = 0x0; \
8608
15
    tmp |= fieldname(insn, 12, 2) << 1; \
8609
15
    tmp |= fieldname(insn, 23, 1) << 0; \
8610
15
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8611
15
    tmp = fieldname(insn, 8, 2); \
8612
15
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8613
15
    return S; \
8614
167
  case 138: \
8615
167
    tmp = fieldname(insn, 4, 4); \
8616
167
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8617
167
    tmp = fieldname(insn, 16, 3); \
8618
167
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8619
167
    tmp = fieldname(insn, 20, 3); \
8620
167
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8621
167
    tmp = fieldname(insn, 4, 4); \
8622
167
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8623
167
    tmp = 0x0; \
8624
167
    tmp |= fieldname(insn, 0, 1) << 2; \
8625
167
    tmp |= fieldname(insn, 14, 2) << 0; \
8626
167
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8627
167
    tmp = 0x0; \
8628
167
    tmp |= fieldname(insn, 12, 2) << 1; \
8629
167
    tmp |= fieldname(insn, 23, 1) << 0; \
8630
167
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8631
167
    return S; \
8632
167
  case 139: \
8633
50
    tmp = fieldname(insn, 20, 3); \
8634
50
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8635
50
    tmp = 0x0; \
8636
50
    tmp |= fieldname(insn, 0, 1) << 2; \
8637
50
    tmp |= fieldname(insn, 14, 2) << 0; \
8638
50
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8639
50
    tmp = fieldname(insn, 4, 4); \
8640
50
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8641
50
    tmp = 0x0; \
8642
50
    tmp |= fieldname(insn, 19, 1) << 0; \
8643
50
    tmp |= fieldname(insn, 24, 1) << 1; \
8644
50
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8645
50
    tmp = 0x0; \
8646
50
    tmp |= fieldname(insn, 12, 2) << 1; \
8647
50
    tmp |= fieldname(insn, 23, 1) << 0; \
8648
50
    if (!Check(&S, decodeSelect_8Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8649
50
    return S; \
8650
50
  case 140: \
8651
7
    tmp = fieldname(insn, 16, 3); \
8652
7
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8653
7
    tmp = fieldname(insn, 4, 4); \
8654
7
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8655
7
    tmp = 0x0; \
8656
7
    tmp |= fieldname(insn, 0, 1) << 2; \
8657
7
    tmp |= fieldname(insn, 14, 2) << 0; \
8658
7
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8659
7
    tmp = fieldname(insn, 4, 4); \
8660
7
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8661
7
    tmp = fieldname(insn, 8, 4); \
8662
7
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8663
7
    tmp = 0x0; \
8664
7
    tmp |= fieldname(insn, 0, 1) << 2; \
8665
7
    tmp |= fieldname(insn, 14, 2) << 0; \
8666
7
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8667
7
    tmp = fieldname(insn, 20, 3); \
8668
7
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8669
7
    return S; \
8670
15
  case 141: \
8671
15
    tmp = fieldname(insn, 16, 3); \
8672
15
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8673
15
    tmp = fieldname(insn, 4, 4); \
8674
15
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8675
15
    tmp = 0x0; \
8676
15
    tmp |= fieldname(insn, 0, 1) << 2; \
8677
15
    tmp |= fieldname(insn, 14, 2) << 0; \
8678
15
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8679
15
    tmp = fieldname(insn, 20, 3); \
8680
15
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8681
15
    tmp = fieldname(insn, 4, 4); \
8682
15
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8683
15
    tmp = 0x0; \
8684
15
    tmp |= fieldname(insn, 12, 1) << 1; \
8685
15
    tmp |= fieldname(insn, 23, 1) << 0; \
8686
15
    if (!Check(&S, decodeSelect_4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8687
15
    return S; \
8688
251
  case 142: \
8689
251
    tmp = 0x0; \
8690
251
    tmp |= fieldname(insn, 19, 1) << 0; \
8691
251
    tmp |= fieldname(insn, 24, 2) << 1; \
8692
251
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8693
251
    tmp = fieldname(insn, 4, 4); \
8694
251
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8695
251
    tmp = fieldname(insn, 4, 4); \
8696
251
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8697
251
    tmp = 0x0; \
8698
251
    tmp |= fieldname(insn, 8, 4) << 0; \
8699
251
    tmp |= fieldname(insn, 26, 2) << 4; \
8700
251
    if (!Check(&S, decodeOffset_64_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8701
251
    tmp = 0x0; \
8702
251
    tmp |= fieldname(insn, 0, 1) << 2; \
8703
251
    tmp |= fieldname(insn, 14, 2) << 0; \
8704
251
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8705
251
    tmp = 0x0; \
8706
251
    tmp |= fieldname(insn, 12, 2) << 1; \
8707
251
    tmp |= fieldname(insn, 23, 1) << 0; \
8708
251
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8709
251
    return S; \
8710
251
  case 143: \
8711
197
    tmp = 0x0; \
8712
197
    tmp |= fieldname(insn, 19, 1) << 0; \
8713
197
    tmp |= fieldname(insn, 24, 2) << 1; \
8714
197
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8715
197
    tmp = fieldname(insn, 4, 4); \
8716
197
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8717
197
    tmp = fieldname(insn, 4, 4); \
8718
197
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8719
197
    tmp = fieldname(insn, 8, 4); \
8720
197
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8721
197
    tmp = 0x0; \
8722
197
    tmp |= fieldname(insn, 0, 1) << 2; \
8723
197
    tmp |= fieldname(insn, 14, 2) << 0; \
8724
197
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8725
197
    tmp = 0x0; \
8726
197
    tmp |= fieldname(insn, 12, 2) << 1; \
8727
197
    tmp |= fieldname(insn, 23, 1) << 0; \
8728
197
    if (!Check(&S, DecodeQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8729
197
    return S; \
8730
197
  case 144: \
8731
0
    tmp = fieldname(insn, 12, 4); \
8732
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8733
0
    tmp = fieldname(insn, 4, 4); \
8734
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8735
0
    tmp = fieldname(insn, 8, 4); \
8736
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8737
0
    return S; \
8738
0
  case 145: \
8739
0
    tmp = fieldname(insn, 8, 4); \
8740
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8741
0
    tmp = fieldname(insn, 4, 4); \
8742
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8743
0
    tmp = fieldname(insn, 12, 4); \
8744
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8745
0
    tmp = fieldname(insn, 8, 4); \
8746
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8747
0
    return S; \
8748
0
  case 146: \
8749
0
    tmp = fieldname(insn, 12, 4); \
8750
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8751
0
    tmp = fieldname(insn, 8, 4); \
8752
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8753
0
    tmp = fieldname(insn, 4, 4); \
8754
0
    MCOperand_CreateImm0(MI, tmp); \
8755
0
    return S; \
8756
0
  case 147: \
8757
0
    tmp = fieldname(insn, 8, 4); \
8758
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8759
0
    tmp = fieldname(insn, 12, 4); \
8760
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8761
0
    tmp = fieldname(insn, 8, 4); \
8762
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8763
0
    tmp = fieldname(insn, 4, 4); \
8764
0
    MCOperand_CreateImm0(MI, tmp); \
8765
0
    return S; \
8766
0
  case 148: \
8767
0
    tmp = fieldname(insn, 8, 4); \
8768
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8769
0
    tmp = fieldname(insn, 12, 4); \
8770
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8771
0
    tmp = fieldname(insn, 8, 4); \
8772
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8773
0
    tmp = fieldname(insn, 4, 4); \
8774
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8775
0
    return S; \
8776
0
  case 149: \
8777
0
    tmp = fieldname(insn, 12, 4); \
8778
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8779
0
    tmp = fieldname(insn, 4, 4); \
8780
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8781
0
    tmp = fieldname(insn, 8, 4); \
8782
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8783
0
    return S; \
8784
0
  case 150: \
8785
0
    tmp = fieldname(insn, 12, 4); \
8786
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8787
0
    tmp = fieldname(insn, 4, 2); \
8788
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8789
0
    tmp = fieldname(insn, 8, 4); \
8790
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8791
0
    tmp = fieldname(insn, 4, 2); \
8792
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8793
0
    tmp = fieldname(insn, 8, 4); \
8794
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8795
0
    return S; \
8796
0
  case 151: \
8797
0
    tmp = fieldname(insn, 4, 2); \
8798
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8799
0
    tmp = fieldname(insn, 8, 4); \
8800
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8801
0
    tmp = fieldname(insn, 12, 4); \
8802
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8803
0
    tmp = fieldname(insn, 4, 2); \
8804
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8805
0
    tmp = fieldname(insn, 8, 4); \
8806
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8807
0
    return S; \
8808
0
  case 152: \
8809
0
    tmp = fieldname(insn, 12, 4); \
8810
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8811
0
    tmp = fieldname(insn, 4, 4); \
8812
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8813
0
    tmp = fieldname(insn, 8, 4); \
8814
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8815
0
    return S; \
8816
0
  case 153: \
8817
0
    tmp = fieldname(insn, 12, 4); \
8818
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8819
0
    tmp = fieldname(insn, 8, 4); \
8820
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8821
0
    tmp = fieldname(insn, 4, 4); \
8822
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8823
0
    return S; \
8824
0
  case 154: \
8825
0
    tmp = fieldname(insn, 12, 4); \
8826
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8827
0
    tmp = fieldname(insn, 8, 4); \
8828
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8829
0
    tmp = fieldname(insn, 4, 4); \
8830
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8831
0
    return S; \
8832
0
  case 155: \
8833
0
    tmp = fieldname(insn, 12, 4); \
8834
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8835
0
    tmp = fieldname(insn, 8, 4); \
8836
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8837
0
    tmp = fieldname(insn, 4, 4); \
8838
0
    if (!Check(&S, decodeImm7_22Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8839
0
    return S; \
8840
0
  case 156: \
8841
0
    tmp = fieldname(insn, 12, 4); \
8842
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8843
0
    tmp = fieldname(insn, 8, 4); \
8844
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8845
0
    return S; \
8846
0
  case 157: \
8847
0
    tmp = fieldname(insn, 12, 4); \
8848
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8849
0
    tmp = fieldname(insn, 4, 4); \
8850
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8851
0
    return S; \
8852
0
  case 158: \
8853
0
    tmp = fieldname(insn, 12, 4); \
8854
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8855
0
    tmp = fieldname(insn, 8, 4); \
8856
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8857
0
    return S; \
8858
0
  case 159: \
8859
0
    tmp = fieldname(insn, 12, 4); \
8860
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8861
0
    tmp = fieldname(insn, 12, 4); \
8862
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8863
0
    tmp = fieldname(insn, 4, 4); \
8864
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8865
0
    tmp = fieldname(insn, 10, 2); \
8866
0
    MCOperand_CreateImm0(MI, tmp); \
8867
0
    return S; \
8868
0
  case 160: \
8869
0
    tmp = fieldname(insn, 6, 2); \
8870
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8871
0
    tmp = fieldname(insn, 4, 2); \
8872
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8873
0
    return S; \
8874
0
  case 161: \
8875
0
    tmp = fieldname(insn, 6, 2); \
8876
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8877
0
    return S; \
8878
0
  case 162: \
8879
0
    tmp = fieldname(insn, 12, 4); \
8880
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8881
0
    tmp = fieldname(insn, 12, 4); \
8882
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8883
0
    tmp = fieldname(insn, 4, 4); \
8884
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8885
0
    return S; \
8886
0
  case 163: \
8887
0
    tmp = fieldname(insn, 12, 4); \
8888
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8889
0
    tmp = fieldname(insn, 8, 4); \
8890
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8891
0
    tmp = fieldname(insn, 8, 4); \
8892
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8893
0
    tmp = fieldname(insn, 4, 3); \
8894
0
    MCOperand_CreateImm0(MI, tmp); \
8895
0
    return S; \
8896
0
  case 164: \
8897
0
    tmp = fieldname(insn, 12, 4); \
8898
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8899
0
    tmp = fieldname(insn, 12, 4); \
8900
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8901
0
    tmp = fieldname(insn, 8, 4); \
8902
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8903
0
    tmp = fieldname(insn, 5, 3); \
8904
0
    if (!Check(&S, DecodeBR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8905
0
    return S; \
8906
0
  case 165: \
8907
0
    tmp = fieldname(insn, 12, 4); \
8908
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8909
0
    tmp = fieldname(insn, 8, 4); \
8910
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8911
0
    return S; \
8912
0
  case 166: \
8913
0
    tmp = fieldname(insn, 12, 4); \
8914
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8915
0
    tmp = fieldname(insn, 8, 4); \
8916
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8917
0
    tmp = fieldname(insn, 8, 4); \
8918
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8919
0
    return S; \
8920
0
  case 167: \
8921
0
    tmp = fieldname(insn, 12, 4); \
8922
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8923
0
    tmp = 0x0; \
8924
0
    tmp |= fieldname(insn, 4, 2) << 0; \
8925
0
    tmp |= fieldname(insn, 8, 4) << 2; \
8926
0
    MCOperand_CreateImm0(MI, tmp); \
8927
0
    return S; \
8928
0
  case 168: \
8929
0
    tmp = fieldname(insn, 12, 4); \
8930
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8931
0
    tmp = fieldname(insn, 4, 4); \
8932
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8933
0
    tmp = fieldname(insn, 8, 4); \
8934
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8935
0
    return S; \
8936
0
  case 169: \
8937
0
    tmp = fieldname(insn, 12, 4); \
8938
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8939
0
    tmp = fieldname(insn, 8, 4); \
8940
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8941
0
    tmp = fieldname(insn, 8, 4); \
8942
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8943
0
    tmp = fieldname(insn, 4, 4); \
8944
0
    MCOperand_CreateImm0(MI, tmp); \
8945
0
    return S; \
8946
0
  case 170: \
8947
0
    tmp = fieldname(insn, 12, 4); \
8948
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8949
0
    tmp = fieldname(insn, 8, 4); \
8950
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8951
0
    tmp = fieldname(insn, 4, 4); \
8952
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8953
0
    return S; \
8954
0
  case 171: \
8955
0
    tmp = fieldname(insn, 13, 3); \
8956
0
    if (!Check(&S, DecodeBR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8957
0
    tmp = fieldname(insn, 8, 4); \
8958
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8959
0
    tmp = fieldname(insn, 4, 4); \
8960
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8961
0
    return S; \
8962
0
  case 172: \
8963
0
    tmp = fieldname(insn, 8, 4); \
8964
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8965
0
    tmp = fieldname(insn, 8, 4); \
8966
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8967
0
    tmp = fieldname(insn, 4, 4); \
8968
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8969
0
    tmp = fieldname(insn, 12, 4); \
8970
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8971
0
    return S; \
8972
0
  case 173: \
8973
0
    tmp = fieldname(insn, 12, 4); \
8974
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8975
0
    tmp = fieldname(insn, 12, 4); \
8976
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8977
0
    tmp = fieldname(insn, 8, 4); \
8978
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8979
0
    tmp = fieldname(insn, 4, 4); \
8980
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8981
0
    return S; \
8982
0
  case 174: \
8983
0
    tmp = fieldname(insn, 8, 4); \
8984
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8985
0
    tmp = fieldname(insn, 12, 4); \
8986
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8987
0
    tmp = fieldname(insn, 8, 4); \
8988
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8989
0
    tmp = fieldname(insn, 4, 3); \
8990
0
    MCOperand_CreateImm0(MI, tmp); \
8991
0
    return S; \
8992
0
  case 175: \
8993
0
    tmp = fieldname(insn, 12, 4); \
8994
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8995
0
    tmp = fieldname(insn, 4, 4); \
8996
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
8997
0
    return S; \
8998
0
  case 176: \
8999
0
    tmp = fieldname(insn, 4, 2); \
9000
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9001
0
    tmp = fieldname(insn, 8, 4); \
9002
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9003
0
    tmp = fieldname(insn, 8, 4); \
9004
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9005
0
    return S; \
9006
0
  case 177: \
9007
0
    tmp = fieldname(insn, 4, 2); \
9008
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9009
0
    tmp = fieldname(insn, 8, 4); \
9010
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9011
0
    return S; \
9012
0
  case 178: \
9013
0
    tmp = fieldname(insn, 4, 2); \
9014
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9015
0
    tmp = fieldname(insn, 4, 2); \
9016
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9017
0
    tmp = fieldname(insn, 8, 4); \
9018
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9019
0
    return S; \
9020
0
  case 179: \
9021
0
    tmp = fieldname(insn, 8, 4); \
9022
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9023
0
    tmp = fieldname(insn, 8, 4); \
9024
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9025
0
    tmp = fieldname(insn, 4, 4); \
9026
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9027
0
    return S; \
9028
0
  case 180: \
9029
0
    tmp = fieldname(insn, 8, 4); \
9030
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9031
0
    tmp = fieldname(insn, 8, 4); \
9032
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9033
0
    tmp = fieldname(insn, 4, 4); \
9034
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9035
0
    return S; \
9036
0
  case 181: \
9037
0
    tmp = fieldname(insn, 8, 4); \
9038
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9039
0
    tmp = fieldname(insn, 8, 4); \
9040
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9041
0
    return S; \
9042
0
  case 182: \
9043
0
    tmp = fieldname(insn, 12, 4); \
9044
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9045
0
    tmp = fieldname(insn, 4, 4); \
9046
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9047
0
    tmp = 0x0; \
9048
0
    tmp |= fieldname(insn, 8, 4) << 0; \
9049
0
    tmp |= fieldname(insn, 16, 2) << 4; \
9050
0
    MCOperand_CreateImm0(MI, tmp); \
9051
0
    return S; \
9052
0
  case 183: \
9053
0
    tmp = fieldname(insn, 12, 4); \
9054
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9055
0
    tmp = fieldname(insn, 4, 4); \
9056
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9057
0
    tmp = 0x0; \
9058
0
    tmp |= fieldname(insn, 8, 4) << 0; \
9059
0
    tmp |= fieldname(insn, 16, 1) << 4; \
9060
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9061
0
    return S; \
9062
0
  case 184: \
9063
0
    tmp = fieldname(insn, 12, 4); \
9064
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9065
0
    tmp = fieldname(insn, 8, 4); \
9066
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9067
0
    tmp = fieldname(insn, 4, 4); \
9068
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9069
0
    tmp = fieldname(insn, 16, 4); \
9070
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9071
0
    return S; \
9072
0
  case 185: \
9073
0
    tmp = fieldname(insn, 12, 4); \
9074
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9075
0
    tmp = fieldname(insn, 8, 4); \
9076
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9077
0
    tmp = fieldname(insn, 8, 4); \
9078
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9079
0
    tmp = fieldname(insn, 4, 4); \
9080
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9081
0
    return S; \
9082
0
  case 186: \
9083
0
    tmp = fieldname(insn, 12, 4); \
9084
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9085
0
    tmp = fieldname(insn, 8, 4); \
9086
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9087
0
    tmp = fieldname(insn, 4, 4); \
9088
0
    if (!Check(&S, decodeImm1_16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9089
0
    return S; \
9090
0
  case 187: \
9091
0
    tmp = fieldname(insn, 12, 4); \
9092
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9093
0
    tmp = fieldname(insn, 4, 4); \
9094
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9095
0
    tmp = fieldname(insn, 4, 4); \
9096
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9097
0
    tmp = fieldname(insn, 8, 4); \
9098
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9099
0
    return S; \
9100
0
  case 188: \
9101
0
    tmp = fieldname(insn, 12, 4); \
9102
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9103
0
    tmp = fieldname(insn, 4, 4); \
9104
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9105
0
    tmp = fieldname(insn, 16, 4); \
9106
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9107
0
    tmp = fieldname(insn, 8, 4); \
9108
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9109
0
    return S; \
9110
0
  case 189: \
9111
0
    tmp = fieldname(insn, 16, 4); \
9112
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9113
0
    tmp = fieldname(insn, 20, 4); \
9114
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9115
0
    tmp = fieldname(insn, 24, 4); \
9116
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9117
0
    return S; \
9118
0
  case 190: \
9119
0
    tmp = fieldname(insn, 16, 4); \
9120
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9121
0
    tmp = fieldname(insn, 16, 4); \
9122
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9123
0
    tmp = fieldname(insn, 20, 4); \
9124
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9125
0
    tmp = fieldname(insn, 24, 4); \
9126
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9127
0
    return S; \
9128
0
  case 191: \
9129
0
    tmp = fieldname(insn, 16, 4); \
9130
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9131
0
    tmp = fieldname(insn, 16, 4); \
9132
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9133
0
    tmp = fieldname(insn, 24, 4); \
9134
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9135
0
    tmp = fieldname(insn, 20, 4); \
9136
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9137
0
    return S; \
9138
0
  case 192: \
9139
0
    tmp = fieldname(insn, 16, 4); \
9140
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9141
0
    tmp = fieldname(insn, 24, 4); \
9142
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9143
0
    tmp = fieldname(insn, 20, 4); \
9144
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9145
0
    return S; \
9146
0
  case 193: \
9147
0
    tmp = fieldname(insn, 6, 2); \
9148
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9149
0
    tmp = fieldname(insn, 8, 4); \
9150
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9151
0
    tmp = fieldname(insn, 12, 4); \
9152
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9153
0
    tmp = fieldname(insn, 6, 2); \
9154
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9155
0
    tmp = fieldname(insn, 8, 4); \
9156
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9157
0
    return S; \
9158
0
  case 194: \
9159
0
    tmp = fieldname(insn, 12, 4); \
9160
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9161
0
    tmp = fieldname(insn, 6, 2); \
9162
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9163
0
    tmp = fieldname(insn, 8, 4); \
9164
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9165
0
    tmp = fieldname(insn, 6, 2); \
9166
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9167
0
    tmp = fieldname(insn, 8, 4); \
9168
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9169
0
    return S; \
9170
0
  case 195: \
9171
0
    tmp = fieldname(insn, 8, 4); \
9172
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9173
0
    tmp = fieldname(insn, 12, 4); \
9174
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9175
0
    tmp = fieldname(insn, 8, 4); \
9176
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9177
0
    return S; \
9178
0
  case 196: \
9179
0
    tmp = fieldname(insn, 6, 2); \
9180
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9181
0
    tmp = fieldname(insn, 8, 4); \
9182
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9183
0
    tmp = fieldname(insn, 8, 4); \
9184
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9185
0
    return S; \
9186
0
  case 197: \
9187
0
    tmp = fieldname(insn, 6, 2); \
9188
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9189
0
    tmp = fieldname(insn, 6, 2); \
9190
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9191
0
    tmp = fieldname(insn, 8, 4); \
9192
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9193
0
    return S; \
9194
0
  case 198: \
9195
0
    tmp = fieldname(insn, 6, 2); \
9196
0
    if (!Check(&S, DecodeAE_VALIGNRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9197
0
    tmp = fieldname(insn, 8, 4); \
9198
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9199
0
    tmp = 0x0; \
9200
0
    tmp |= fieldname(insn, 4, 2) << 0; \
9201
0
    tmp |= fieldname(insn, 28, 2) << 2; \
9202
0
    MCOperand_CreateImm0(MI, tmp); \
9203
0
    return S; \
9204
0
  case 199: \
9205
0
    tmp = fieldname(insn, 12, 4); \
9206
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9207
0
    tmp = fieldname(insn, 4, 4); \
9208
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9209
0
    return S; \
9210
0
  case 200: \
9211
0
    tmp = fieldname(insn, 20, 4); \
9212
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9213
0
    tmp = fieldname(insn, 24, 4); \
9214
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9215
0
    tmp = fieldname(insn, 16, 4); \
9216
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9217
0
    return S; \
9218
0
  case 201: \
9219
0
    tmp = fieldname(insn, 20, 4); \
9220
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9221
0
    tmp = fieldname(insn, 16, 4); \
9222
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9223
0
    return S; \
9224
0
  case 202: \
9225
0
    tmp = fieldname(insn, 16, 4); \
9226
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9227
0
    tmp = fieldname(insn, 20, 4); \
9228
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9229
0
    tmp = fieldname(insn, 16, 4); \
9230
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9231
0
    tmp = fieldname(insn, 20, 4); \
9232
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9233
0
    tmp = fieldname(insn, 24, 4); \
9234
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9235
0
    tmp = fieldname(insn, 32, 4); \
9236
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9237
0
    tmp = fieldname(insn, 36, 4); \
9238
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9239
0
    return S; \
9240
0
  case 203: \
9241
0
    tmp = fieldname(insn, 16, 4); \
9242
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9243
0
    tmp = fieldname(insn, 24, 4); \
9244
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9245
0
    tmp = fieldname(insn, 32, 4); \
9246
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9247
0
    tmp = fieldname(insn, 48, 2); \
9248
0
    MCOperand_CreateImm0(MI, tmp); \
9249
0
    return S; \
9250
0
  case 204: \
9251
0
    tmp = fieldname(insn, 16, 4); \
9252
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9253
0
    tmp = fieldname(insn, 16, 4); \
9254
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9255
0
    tmp = fieldname(insn, 24, 4); \
9256
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9257
0
    tmp = fieldname(insn, 32, 4); \
9258
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9259
0
    return S; \
9260
0
  case 205: \
9261
0
    tmp = fieldname(insn, 16, 4); \
9262
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9263
0
    tmp = fieldname(insn, 24, 4); \
9264
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9265
0
    tmp = fieldname(insn, 32, 4); \
9266
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9267
0
    return S; \
9268
0
  case 206: \
9269
0
    tmp = fieldname(insn, 28, 4); \
9270
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9271
0
    tmp = fieldname(insn, 4, 4); \
9272
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9273
0
    tmp = fieldname(insn, 12, 4); \
9274
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9275
0
    tmp = fieldname(insn, 8, 4); \
9276
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9277
0
    return S; \
9278
0
  case 207: \
9279
0
    tmp = fieldname(insn, 28, 4); \
9280
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9281
0
    tmp = fieldname(insn, 4, 4); \
9282
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9283
0
    tmp = fieldname(insn, 12, 4); \
9284
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9285
0
    tmp = fieldname(insn, 8, 4); \
9286
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9287
0
    return S; \
9288
0
  case 208: \
9289
0
    tmp = fieldname(insn, 28, 4); \
9290
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9291
0
    tmp = fieldname(insn, 4, 4); \
9292
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9293
0
    tmp = fieldname(insn, 8, 4); \
9294
0
    if (!Check(&S, DecodeARRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9295
0
    return S; \
9296
0
  case 209: \
9297
0
    tmp = fieldname(insn, 16, 4); \
9298
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9299
0
    tmp = fieldname(insn, 32, 4); \
9300
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9301
0
    return S; \
9302
0
  case 210: \
9303
0
    tmp = fieldname(insn, 16, 4); \
9304
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9305
0
    tmp = fieldname(insn, 20, 4); \
9306
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9307
0
    tmp = fieldname(insn, 24, 4); \
9308
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9309
0
    tmp = fieldname(insn, 32, 4); \
9310
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9311
0
    tmp = fieldname(insn, 36, 4); \
9312
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9313
0
    return S; \
9314
0
  case 211: \
9315
0
    tmp = fieldname(insn, 20, 4); \
9316
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9317
0
    tmp = fieldname(insn, 28, 4); \
9318
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9319
0
    tmp = 0x0; \
9320
0
    tmp |= fieldname(insn, 36, 4) << 0; \
9321
0
    tmp |= fieldname(insn, 56, 2) << 4; \
9322
0
    MCOperand_CreateImm0(MI, tmp); \
9323
0
    return S; \
9324
0
  case 212: \
9325
0
    tmp = fieldname(insn, 20, 4); \
9326
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9327
0
    tmp = fieldname(insn, 16, 4); \
9328
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9329
0
    tmp = fieldname(insn, 32, 4); \
9330
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9331
0
    tmp = fieldname(insn, 24, 4); \
9332
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9333
0
    return S; \
9334
0
  case 213: \
9335
0
    tmp = fieldname(insn, 20, 4); \
9336
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9337
0
    tmp = fieldname(insn, 16, 4); \
9338
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9339
0
    tmp = fieldname(insn, 20, 4); \
9340
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9341
0
    tmp = fieldname(insn, 16, 4); \
9342
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9343
0
    tmp = fieldname(insn, 32, 4); \
9344
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9345
0
    tmp = fieldname(insn, 24, 4); \
9346
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9347
0
    return S; \
9348
0
  case 214: \
9349
0
    tmp = fieldname(insn, 20, 4); \
9350
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9351
0
    tmp = fieldname(insn, 28, 4); \
9352
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9353
0
    tmp = 0x0; \
9354
0
    tmp |= fieldname(insn, 36, 4) << 0; \
9355
0
    tmp |= fieldname(insn, 56, 1) << 4; \
9356
0
    if (!Check(&S, decodeUimm5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9357
0
    return S; \
9358
0
  case 215: \
9359
0
    tmp = fieldname(insn, 20, 4); \
9360
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9361
0
    tmp = fieldname(insn, 36, 4); \
9362
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9363
0
    tmp = fieldname(insn, 28, 4); \
9364
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9365
0
    return S; \
9366
0
  case 216: \
9367
0
    tmp = fieldname(insn, 20, 4); \
9368
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9369
0
    tmp = fieldname(insn, 20, 4); \
9370
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9371
0
    tmp = fieldname(insn, 36, 4); \
9372
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9373
0
    tmp = fieldname(insn, 28, 4); \
9374
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9375
0
    return S; \
9376
0
  case 217: \
9377
0
    tmp = fieldname(insn, 20, 4); \
9378
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9379
0
    tmp = fieldname(insn, 28, 4); \
9380
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9381
0
    tmp = fieldname(insn, 36, 4); \
9382
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9383
0
    return S; \
9384
0
  case 218: \
9385
0
    tmp = fieldname(insn, 20, 4); \
9386
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9387
0
    tmp = fieldname(insn, 36, 4); \
9388
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9389
0
    tmp = fieldname(insn, 28, 4); \
9390
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9391
0
    return S; \
9392
0
  case 219: \
9393
0
    tmp = fieldname(insn, 20, 4); \
9394
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9395
0
    tmp = fieldname(insn, 20, 4); \
9396
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9397
0
    tmp = fieldname(insn, 36, 4); \
9398
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9399
0
    tmp = fieldname(insn, 28, 4); \
9400
0
    if (!Check(&S, DecodeBRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9401
0
    return S; \
9402
0
  case 220: \
9403
0
    tmp = fieldname(insn, 21, 3); \
9404
0
    if (!Check(&S, DecodeBR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9405
0
    tmp = fieldname(insn, 36, 4); \
9406
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9407
0
    tmp = fieldname(insn, 28, 4); \
9408
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9409
0
    return S; \
9410
0
  case 221: \
9411
0
    tmp = fieldname(insn, 22, 2); \
9412
0
    if (!Check(&S, DecodeBR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9413
0
    tmp = fieldname(insn, 36, 4); \
9414
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9415
0
    tmp = fieldname(insn, 28, 4); \
9416
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9417
0
    return S; \
9418
0
  case 222: \
9419
0
    tmp = fieldname(insn, 20, 4); \
9420
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9421
0
    tmp = fieldname(insn, 20, 4); \
9422
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9423
0
    tmp = fieldname(insn, 36, 4); \
9424
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9425
0
    tmp = fieldname(insn, 30, 2); \
9426
0
    if (!Check(&S, DecodeBR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9427
0
    return S; \
9428
0
  case 223: \
9429
0
    tmp = fieldname(insn, 20, 4); \
9430
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9431
0
    tmp = fieldname(insn, 20, 4); \
9432
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9433
0
    tmp = fieldname(insn, 36, 4); \
9434
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9435
0
    return S; \
9436
0
  case 224: \
9437
0
    tmp = fieldname(insn, 20, 4); \
9438
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9439
0
    tmp = fieldname(insn, 36, 4); \
9440
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9441
0
    return S; \
9442
0
  case 225: \
9443
0
    tmp = fieldname(insn, 20, 4); \
9444
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9445
0
    tmp = fieldname(insn, 28, 4); \
9446
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9447
0
    return S; \
9448
0
  case 226: \
9449
0
    tmp = fieldname(insn, 20, 4); \
9450
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9451
0
    tmp = fieldname(insn, 28, 4); \
9452
0
    if (!Check(&S, DecodeAE_DRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9453
0
    tmp = fieldname(insn, 36, 4); \
9454
0
    if (!Check(&S, decodeUimm4Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
9455
0
    return S; \
9456
6.30k
  } \
9457
6.30k
}
Unexecuted instantiation: XtensaDisassembler.c:decodeToMCInst_6
9458
9459
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
9460
static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
9461
109k
                                      InsnType insn, uint64_t Address, const void *Decoder) { \
9462
109k
  const uint8_t *Ptr = DecodeTable; \
9463
109k
  uint64_t CurFieldValue = 0; \
9464
109k
  DecodeStatus S = MCDisassembler_Success; \
9465
1.56M
  while (true) { \
9466
1.56M
    switch (*Ptr) { \
9467
0
    default: \
9468
0
      return MCDisassembler_Fail; \
9469
204k
    case MCD_OPC_ExtractField: { \
9470
204k
      unsigned Start = *++Ptr; \
9471
204k
      unsigned Len = *++Ptr; \
9472
204k
      ++Ptr; \
9473
204k
      CurFieldValue = fieldname(insn, Start, Len); \
9474
204k
      break; \
9475
0
    } \
9476
1.18M
    case MCD_OPC_FilterValue: { \
9477
1.18M
      /* Decode the field value. */ \
9478
1.18M
      unsigned Len; \
9479
1.18M
      uint64_t Val = decodeULEB128(++Ptr, &Len); \
9480
1.18M
      Ptr += Len; \
9481
1.18M
      /* NumToSkip is a plain 24-bit integer. */ \
9482
1.18M
      unsigned NumToSkip = *Ptr++; \
9483
1.18M
      NumToSkip |= (*Ptr++) << 8; \
9484
1.18M
      NumToSkip |= (*Ptr++) << 16; \
9485
1.18M
      /* Perform the filter operation. */ \
9486
1.18M
      if (Val != CurFieldValue) \
9487
1.18M
        Ptr += NumToSkip; \
9488
1.18M
      break; \
9489
0
    } \
9490
23.3k
    case MCD_OPC_CheckField: { \
9491
23.3k
      unsigned Start = *++Ptr; \
9492
23.3k
      unsigned Len = *++Ptr; \
9493
23.3k
      uint64_t FieldValue = fieldname(insn, Start, Len); \
9494
23.3k
      /* Decode the field value. */ \
9495
23.3k
      unsigned PtrLen = 0; \
9496
23.3k
      uint64_t ExpectedValue = decodeULEB128(++Ptr, &PtrLen); \
9497
23.3k
      Ptr += PtrLen; \
9498
23.3k
      /* NumToSkip is a plain 24-bit integer. */ \
9499
23.3k
      unsigned NumToSkip = *Ptr++; \
9500
23.3k
      NumToSkip |= (*Ptr++) << 8; \
9501
23.3k
      NumToSkip |= (*Ptr++) << 16; \
9502
23.3k
      /* If the actual and expected values don't match, skip. */ \
9503
23.3k
      if (ExpectedValue != FieldValue) \
9504
23.3k
        Ptr += NumToSkip; \
9505
23.3k
      break; \
9506
0
    } \
9507
38.2k
    case MCD_OPC_CheckPredicate: { \
9508
38.2k
      unsigned Len; \
9509
38.2k
      /* Decode the Predicate Index value. */ \
9510
38.2k
      unsigned PIdx = decodeULEB128(++Ptr, &Len); \
9511
38.2k
      Ptr += Len; \
9512
38.2k
      /* NumToSkip is a plain 24-bit integer. */ \
9513
38.2k
      unsigned NumToSkip = *Ptr++; \
9514
38.2k
      NumToSkip |= (*Ptr++) << 8; \
9515
38.2k
      NumToSkip |= (*Ptr++) << 16; \
9516
38.2k
      /* Check the predicate. */ \
9517
38.2k
      bool Pred = checkDecoderPredicate(MI, PIdx); \
9518
38.2k
      if (!Pred) \
9519
38.2k
        Ptr += NumToSkip; \
9520
38.2k
      break; \
9521
0
    } \
9522
55.7k
    case MCD_OPC_Decode: { \
9523
55.7k
      unsigned Len; \
9524
55.7k
      /* Decode the Opcode value. */ \
9525
55.7k
      unsigned Opc = decodeULEB128(++Ptr, &Len); \
9526
55.7k
      Ptr += Len; \
9527
55.7k
      unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \
9528
55.7k
      Ptr += Len; \
9529
55.7k
      MCInst_clear(MI); \
9530
55.7k
      MCInst_setOpcode(MI, Opc); \
9531
55.7k
      bool DecodeComplete; \
9532
55.7k
      S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \
9533
55.7k
      return S; \
9534
0
    } \
9535
0
    case MCD_OPC_TryDecode: { \
9536
0
      unsigned Len; \
9537
0
      /* Decode the Opcode value. */ \
9538
0
      unsigned Opc = decodeULEB128(++Ptr, &Len); \
9539
0
      Ptr += Len; \
9540
0
      unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \
9541
0
      Ptr += Len; \
9542
0
      /* NumToSkip is a plain 24-bit integer. */ \
9543
0
      unsigned NumToSkip = *Ptr++; \
9544
0
      NumToSkip |= (*Ptr++) << 8; \
9545
0
      NumToSkip |= (*Ptr++) << 16; \
9546
0
      /* Perform the decode operation. */ \
9547
0
      MCInst_setOpcode(MI, Opc); \
9548
0
      bool DecodeComplete; \
9549
0
      S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \
9550
0
      if (DecodeComplete) { \
9551
0
        /* Decoding complete. */ \
9552
0
        return S; \
9553
0
      } else { \
9554
0
        /* LLVM uses a MCInst on the stack, but for our use case, */ \
9555
0
        /* it is enough for now to reset the op counter. */ \
9556
0
        MCInst_clear(MI); \
9557
0
        /* If the decoding was incomplete, skip. */ \
9558
0
        Ptr += NumToSkip; \
9559
0
        /* Reset decode status. This also drops a SoftFail status that could be */ \
9560
0
        /* set before the decode attempt. */ \
9561
0
        S = MCDisassembler_Success; \
9562
0
      } \
9563
0
      break; \
9564
0
    } \
9565
0
    case MCD_OPC_SoftFail: { \
9566
0
      /* Decode the mask values. */ \
9567
0
      unsigned Len; \
9568
0
      uint64_t PositiveMask = decodeULEB128(++Ptr, &Len); \
9569
0
      Ptr += Len; \
9570
0
      uint64_t NegativeMask = decodeULEB128(Ptr, &Len); \
9571
0
      Ptr += Len; \
9572
0
      bool Fail = (insn & PositiveMask) != 0 || (~insn & NegativeMask) != 0; \
9573
0
      if (Fail) \
9574
0
        S = MCDisassembler_SoftFail; \
9575
0
      break; \
9576
0
    } \
9577
53.8k
    case MCD_OPC_Fail: { \
9578
53.8k
      return MCDisassembler_Fail; \
9579
0
    } \
9580
1.56M
    } \
9581
1.56M
  } \
9582
109k
  /* Bogisity detected in disassembler state machine! */ \
9583
109k
}
XtensaDisassembler.c:decodeInstruction_2
Line
Count
Source
9461
55.7k
                                      InsnType insn, uint64_t Address, const void *Decoder) { \
9462
55.7k
  const uint8_t *Ptr = DecodeTable; \
9463
55.7k
  uint64_t CurFieldValue = 0; \
9464
55.7k
  DecodeStatus S = MCDisassembler_Success; \
9465
429k
  while (true) { \
9466
429k
    switch (*Ptr) { \
9467
0
    default: \
9468
0
      return MCDisassembler_Fail; \
9469
58.3k
    case MCD_OPC_ExtractField: { \
9470
58.3k
      unsigned Start = *++Ptr; \
9471
58.3k
      unsigned Len = *++Ptr; \
9472
58.3k
      ++Ptr; \
9473
58.3k
      CurFieldValue = fieldname(insn, Start, Len); \
9474
58.3k
      break; \
9475
0
    } \
9476
297k
    case MCD_OPC_FilterValue: { \
9477
297k
      /* Decode the field value. */ \
9478
297k
      unsigned Len; \
9479
297k
      uint64_t Val = decodeULEB128(++Ptr, &Len); \
9480
297k
      Ptr += Len; \
9481
297k
      /* NumToSkip is a plain 24-bit integer. */ \
9482
297k
      unsigned NumToSkip = *Ptr++; \
9483
297k
      NumToSkip |= (*Ptr++) << 8; \
9484
297k
      NumToSkip |= (*Ptr++) << 16; \
9485
297k
      /* Perform the filter operation. */ \
9486
297k
      if (Val != CurFieldValue) \
9487
297k
        Ptr += NumToSkip; \
9488
297k
      break; \
9489
0
    } \
9490
2.11k
    case MCD_OPC_CheckField: { \
9491
2.11k
      unsigned Start = *++Ptr; \
9492
2.11k
      unsigned Len = *++Ptr; \
9493
2.11k
      uint64_t FieldValue = fieldname(insn, Start, Len); \
9494
2.11k
      /* Decode the field value. */ \
9495
2.11k
      unsigned PtrLen = 0; \
9496
2.11k
      uint64_t ExpectedValue = decodeULEB128(++Ptr, &PtrLen); \
9497
2.11k
      Ptr += PtrLen; \
9498
2.11k
      /* NumToSkip is a plain 24-bit integer. */ \
9499
2.11k
      unsigned NumToSkip = *Ptr++; \
9500
2.11k
      NumToSkip |= (*Ptr++) << 8; \
9501
2.11k
      NumToSkip |= (*Ptr++) << 16; \
9502
2.11k
      /* If the actual and expected values don't match, skip. */ \
9503
2.11k
      if (ExpectedValue != FieldValue) \
9504
2.11k
        Ptr += NumToSkip; \
9505
2.11k
      break; \
9506
0
    } \
9507
15.8k
    case MCD_OPC_CheckPredicate: { \
9508
15.8k
      unsigned Len; \
9509
15.8k
      /* Decode the Predicate Index value. */ \
9510
15.8k
      unsigned PIdx = decodeULEB128(++Ptr, &Len); \
9511
15.8k
      Ptr += Len; \
9512
15.8k
      /* NumToSkip is a plain 24-bit integer. */ \
9513
15.8k
      unsigned NumToSkip = *Ptr++; \
9514
15.8k
      NumToSkip |= (*Ptr++) << 8; \
9515
15.8k
      NumToSkip |= (*Ptr++) << 16; \
9516
15.8k
      /* Check the predicate. */ \
9517
15.8k
      bool Pred = checkDecoderPredicate(MI, PIdx); \
9518
15.8k
      if (!Pred) \
9519
15.8k
        Ptr += NumToSkip; \
9520
15.8k
      break; \
9521
0
    } \
9522
14.4k
    case MCD_OPC_Decode: { \
9523
14.4k
      unsigned Len; \
9524
14.4k
      /* Decode the Opcode value. */ \
9525
14.4k
      unsigned Opc = decodeULEB128(++Ptr, &Len); \
9526
14.4k
      Ptr += Len; \
9527
14.4k
      unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \
9528
14.4k
      Ptr += Len; \
9529
14.4k
      MCInst_clear(MI); \
9530
14.4k
      MCInst_setOpcode(MI, Opc); \
9531
14.4k
      bool DecodeComplete; \
9532
14.4k
      S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \
9533
14.4k
      return S; \
9534
0
    } \
9535
0
    case MCD_OPC_TryDecode: { \
9536
0
      unsigned Len; \
9537
0
      /* Decode the Opcode value. */ \
9538
0
      unsigned Opc = decodeULEB128(++Ptr, &Len); \
9539
0
      Ptr += Len; \
9540
0
      unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \
9541
0
      Ptr += Len; \
9542
0
      /* NumToSkip is a plain 24-bit integer. */ \
9543
0
      unsigned NumToSkip = *Ptr++; \
9544
0
      NumToSkip |= (*Ptr++) << 8; \
9545
0
      NumToSkip |= (*Ptr++) << 16; \
9546
0
      /* Perform the decode operation. */ \
9547
0
      MCInst_setOpcode(MI, Opc); \
9548
0
      bool DecodeComplete; \
9549
0
      S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \
9550
0
      if (DecodeComplete) { \
9551
0
        /* Decoding complete. */ \
9552
0
        return S; \
9553
0
      } else { \
9554
0
        /* LLVM uses a MCInst on the stack, but for our use case, */ \
9555
0
        /* it is enough for now to reset the op counter. */ \
9556
0
        MCInst_clear(MI); \
9557
0
        /* If the decoding was incomplete, skip. */ \
9558
0
        Ptr += NumToSkip; \
9559
0
        /* Reset decode status. This also drops a SoftFail status that could be */ \
9560
0
        /* set before the decode attempt. */ \
9561
0
        S = MCDisassembler_Success; \
9562
0
      } \
9563
0
      break; \
9564
0
    } \
9565
0
    case MCD_OPC_SoftFail: { \
9566
0
      /* Decode the mask values. */ \
9567
0
      unsigned Len; \
9568
0
      uint64_t PositiveMask = decodeULEB128(++Ptr, &Len); \
9569
0
      Ptr += Len; \
9570
0
      uint64_t NegativeMask = decodeULEB128(Ptr, &Len); \
9571
0
      Ptr += Len; \
9572
0
      bool Fail = (insn & PositiveMask) != 0 || (~insn & NegativeMask) != 0; \
9573
0
      if (Fail) \
9574
0
        S = MCDisassembler_SoftFail; \
9575
0
      break; \
9576
0
    } \
9577
41.3k
    case MCD_OPC_Fail: { \
9578
41.3k
      return MCDisassembler_Fail; \
9579
0
    } \
9580
429k
    } \
9581
429k
  } \
9582
55.7k
  /* Bogisity detected in disassembler state machine! */ \
9583
55.7k
}
XtensaDisassembler.c:decodeInstruction_3
Line
Count
Source
9461
47.4k
                                      InsnType insn, uint64_t Address, const void *Decoder) { \
9462
47.4k
  const uint8_t *Ptr = DecodeTable; \
9463
47.4k
  uint64_t CurFieldValue = 0; \
9464
47.4k
  DecodeStatus S = MCDisassembler_Success; \
9465
1.01M
  while (true) { \
9466
1.01M
    switch (*Ptr) { \
9467
0
    default: \
9468
0
      return MCDisassembler_Fail; \
9469
132k
    case MCD_OPC_ExtractField: { \
9470
132k
      unsigned Start = *++Ptr; \
9471
132k
      unsigned Len = *++Ptr; \
9472
132k
      ++Ptr; \
9473
132k
      CurFieldValue = fieldname(insn, Start, Len); \
9474
132k
      break; \
9475
0
    } \
9476
804k
    case MCD_OPC_FilterValue: { \
9477
804k
      /* Decode the field value. */ \
9478
804k
      unsigned Len; \
9479
804k
      uint64_t Val = decodeULEB128(++Ptr, &Len); \
9480
804k
      Ptr += Len; \
9481
804k
      /* NumToSkip is a plain 24-bit integer. */ \
9482
804k
      unsigned NumToSkip = *Ptr++; \
9483
804k
      NumToSkip |= (*Ptr++) << 8; \
9484
804k
      NumToSkip |= (*Ptr++) << 16; \
9485
804k
      /* Perform the filter operation. */ \
9486
804k
      if (Val != CurFieldValue) \
9487
804k
        Ptr += NumToSkip; \
9488
804k
      break; \
9489
0
    } \
9490
14.5k
    case MCD_OPC_CheckField: { \
9491
14.5k
      unsigned Start = *++Ptr; \
9492
14.5k
      unsigned Len = *++Ptr; \
9493
14.5k
      uint64_t FieldValue = fieldname(insn, Start, Len); \
9494
14.5k
      /* Decode the field value. */ \
9495
14.5k
      unsigned PtrLen = 0; \
9496
14.5k
      uint64_t ExpectedValue = decodeULEB128(++Ptr, &PtrLen); \
9497
14.5k
      Ptr += PtrLen; \
9498
14.5k
      /* NumToSkip is a plain 24-bit integer. */ \
9499
14.5k
      unsigned NumToSkip = *Ptr++; \
9500
14.5k
      NumToSkip |= (*Ptr++) << 8; \
9501
14.5k
      NumToSkip |= (*Ptr++) << 16; \
9502
14.5k
      /* If the actual and expected values don't match, skip. */ \
9503
14.5k
      if (ExpectedValue != FieldValue) \
9504
14.5k
        Ptr += NumToSkip; \
9505
14.5k
      break; \
9506
0
    } \
9507
15.9k
    case MCD_OPC_CheckPredicate: { \
9508
15.9k
      unsigned Len; \
9509
15.9k
      /* Decode the Predicate Index value. */ \
9510
15.9k
      unsigned PIdx = decodeULEB128(++Ptr, &Len); \
9511
15.9k
      Ptr += Len; \
9512
15.9k
      /* NumToSkip is a plain 24-bit integer. */ \
9513
15.9k
      unsigned NumToSkip = *Ptr++; \
9514
15.9k
      NumToSkip |= (*Ptr++) << 8; \
9515
15.9k
      NumToSkip |= (*Ptr++) << 16; \
9516
15.9k
      /* Check the predicate. */ \
9517
15.9k
      bool Pred = checkDecoderPredicate(MI, PIdx); \
9518
15.9k
      if (!Pred) \
9519
15.9k
        Ptr += NumToSkip; \
9520
15.9k
      break; \
9521
0
    } \
9522
35.0k
    case MCD_OPC_Decode: { \
9523
35.0k
      unsigned Len; \
9524
35.0k
      /* Decode the Opcode value. */ \
9525
35.0k
      unsigned Opc = decodeULEB128(++Ptr, &Len); \
9526
35.0k
      Ptr += Len; \
9527
35.0k
      unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \
9528
35.0k
      Ptr += Len; \
9529
35.0k
      MCInst_clear(MI); \
9530
35.0k
      MCInst_setOpcode(MI, Opc); \
9531
35.0k
      bool DecodeComplete; \
9532
35.0k
      S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \
9533
35.0k
      return S; \
9534
0
    } \
9535
0
    case MCD_OPC_TryDecode: { \
9536
0
      unsigned Len; \
9537
0
      /* Decode the Opcode value. */ \
9538
0
      unsigned Opc = decodeULEB128(++Ptr, &Len); \
9539
0
      Ptr += Len; \
9540
0
      unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \
9541
0
      Ptr += Len; \
9542
0
      /* NumToSkip is a plain 24-bit integer. */ \
9543
0
      unsigned NumToSkip = *Ptr++; \
9544
0
      NumToSkip |= (*Ptr++) << 8; \
9545
0
      NumToSkip |= (*Ptr++) << 16; \
9546
0
      /* Perform the decode operation. */ \
9547
0
      MCInst_setOpcode(MI, Opc); \
9548
0
      bool DecodeComplete; \
9549
0
      S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \
9550
0
      if (DecodeComplete) { \
9551
0
        /* Decoding complete. */ \
9552
0
        return S; \
9553
0
      } else { \
9554
0
        /* LLVM uses a MCInst on the stack, but for our use case, */ \
9555
0
        /* it is enough for now to reset the op counter. */ \
9556
0
        MCInst_clear(MI); \
9557
0
        /* If the decoding was incomplete, skip. */ \
9558
0
        Ptr += NumToSkip; \
9559
0
        /* Reset decode status. This also drops a SoftFail status that could be */ \
9560
0
        /* set before the decode attempt. */ \
9561
0
        S = MCDisassembler_Success; \
9562
0
      } \
9563
0
      break; \
9564
0
    } \
9565
0
    case MCD_OPC_SoftFail: { \
9566
0
      /* Decode the mask values. */ \
9567
0
      unsigned Len; \
9568
0
      uint64_t PositiveMask = decodeULEB128(++Ptr, &Len); \
9569
0
      Ptr += Len; \
9570
0
      uint64_t NegativeMask = decodeULEB128(Ptr, &Len); \
9571
0
      Ptr += Len; \
9572
0
      bool Fail = (insn & PositiveMask) != 0 || (~insn & NegativeMask) != 0; \
9573
0
      if (Fail) \
9574
0
        S = MCDisassembler_SoftFail; \
9575
0
      break; \
9576
0
    } \
9577
12.4k
    case MCD_OPC_Fail: { \
9578
12.4k
      return MCDisassembler_Fail; \
9579
0
    } \
9580
1.01M
    } \
9581
1.01M
  } \
9582
47.4k
  /* Bogisity detected in disassembler state machine! */ \
9583
47.4k
}
XtensaDisassembler.c:decodeInstruction_4
Line
Count
Source
9461
6.35k
                                      InsnType insn, uint64_t Address, const void *Decoder) { \
9462
6.35k
  const uint8_t *Ptr = DecodeTable; \
9463
6.35k
  uint64_t CurFieldValue = 0; \
9464
6.35k
  DecodeStatus S = MCDisassembler_Success; \
9465
114k
  while (true) { \
9466
114k
    switch (*Ptr) { \
9467
0
    default: \
9468
0
      return MCDisassembler_Fail; \
9469
13.4k
    case MCD_OPC_ExtractField: { \
9470
13.4k
      unsigned Start = *++Ptr; \
9471
13.4k
      unsigned Len = *++Ptr; \
9472
13.4k
      ++Ptr; \
9473
13.4k
      CurFieldValue = fieldname(insn, Start, Len); \
9474
13.4k
      break; \
9475
0
    } \
9476
81.5k
    case MCD_OPC_FilterValue: { \
9477
81.5k
      /* Decode the field value. */ \
9478
81.5k
      unsigned Len; \
9479
81.5k
      uint64_t Val = decodeULEB128(++Ptr, &Len); \
9480
81.5k
      Ptr += Len; \
9481
81.5k
      /* NumToSkip is a plain 24-bit integer. */ \
9482
81.5k
      unsigned NumToSkip = *Ptr++; \
9483
81.5k
      NumToSkip |= (*Ptr++) << 8; \
9484
81.5k
      NumToSkip |= (*Ptr++) << 16; \
9485
81.5k
      /* Perform the filter operation. */ \
9486
81.5k
      if (Val != CurFieldValue) \
9487
81.5k
        Ptr += NumToSkip; \
9488
81.5k
      break; \
9489
0
    } \
9490
6.74k
    case MCD_OPC_CheckField: { \
9491
6.74k
      unsigned Start = *++Ptr; \
9492
6.74k
      unsigned Len = *++Ptr; \
9493
6.74k
      uint64_t FieldValue = fieldname(insn, Start, Len); \
9494
6.74k
      /* Decode the field value. */ \
9495
6.74k
      unsigned PtrLen = 0; \
9496
6.74k
      uint64_t ExpectedValue = decodeULEB128(++Ptr, &PtrLen); \
9497
6.74k
      Ptr += PtrLen; \
9498
6.74k
      /* NumToSkip is a plain 24-bit integer. */ \
9499
6.74k
      unsigned NumToSkip = *Ptr++; \
9500
6.74k
      NumToSkip |= (*Ptr++) << 8; \
9501
6.74k
      NumToSkip |= (*Ptr++) << 16; \
9502
6.74k
      /* If the actual and expected values don't match, skip. */ \
9503
6.74k
      if (ExpectedValue != FieldValue) \
9504
6.74k
        Ptr += NumToSkip; \
9505
6.74k
      break; \
9506
0
    } \
9507
6.34k
    case MCD_OPC_CheckPredicate: { \
9508
6.34k
      unsigned Len; \
9509
6.34k
      /* Decode the Predicate Index value. */ \
9510
6.34k
      unsigned PIdx = decodeULEB128(++Ptr, &Len); \
9511
6.34k
      Ptr += Len; \
9512
6.34k
      /* NumToSkip is a plain 24-bit integer. */ \
9513
6.34k
      unsigned NumToSkip = *Ptr++; \
9514
6.34k
      NumToSkip |= (*Ptr++) << 8; \
9515
6.34k
      NumToSkip |= (*Ptr++) << 16; \
9516
6.34k
      /* Check the predicate. */ \
9517
6.34k
      bool Pred = checkDecoderPredicate(MI, PIdx); \
9518
6.34k
      if (!Pred) \
9519
6.34k
        Ptr += NumToSkip; \
9520
6.34k
      break; \
9521
0
    } \
9522
6.30k
    case MCD_OPC_Decode: { \
9523
6.30k
      unsigned Len; \
9524
6.30k
      /* Decode the Opcode value. */ \
9525
6.30k
      unsigned Opc = decodeULEB128(++Ptr, &Len); \
9526
6.30k
      Ptr += Len; \
9527
6.30k
      unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \
9528
6.30k
      Ptr += Len; \
9529
6.30k
      MCInst_clear(MI); \
9530
6.30k
      MCInst_setOpcode(MI, Opc); \
9531
6.30k
      bool DecodeComplete; \
9532
6.30k
      S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \
9533
6.30k
      return S; \
9534
0
    } \
9535
0
    case MCD_OPC_TryDecode: { \
9536
0
      unsigned Len; \
9537
0
      /* Decode the Opcode value. */ \
9538
0
      unsigned Opc = decodeULEB128(++Ptr, &Len); \
9539
0
      Ptr += Len; \
9540
0
      unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \
9541
0
      Ptr += Len; \
9542
0
      /* NumToSkip is a plain 24-bit integer. */ \
9543
0
      unsigned NumToSkip = *Ptr++; \
9544
0
      NumToSkip |= (*Ptr++) << 8; \
9545
0
      NumToSkip |= (*Ptr++) << 16; \
9546
0
      /* Perform the decode operation. */ \
9547
0
      MCInst_setOpcode(MI, Opc); \
9548
0
      bool DecodeComplete; \
9549
0
      S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \
9550
0
      if (DecodeComplete) { \
9551
0
        /* Decoding complete. */ \
9552
0
        return S; \
9553
0
      } else { \
9554
0
        /* LLVM uses a MCInst on the stack, but for our use case, */ \
9555
0
        /* it is enough for now to reset the op counter. */ \
9556
0
        MCInst_clear(MI); \
9557
0
        /* If the decoding was incomplete, skip. */ \
9558
0
        Ptr += NumToSkip; \
9559
0
        /* Reset decode status. This also drops a SoftFail status that could be */ \
9560
0
        /* set before the decode attempt. */ \
9561
0
        S = MCDisassembler_Success; \
9562
0
      } \
9563
0
      break; \
9564
0
    } \
9565
0
    case MCD_OPC_SoftFail: { \
9566
0
      /* Decode the mask values. */ \
9567
0
      unsigned Len; \
9568
0
      uint64_t PositiveMask = decodeULEB128(++Ptr, &Len); \
9569
0
      Ptr += Len; \
9570
0
      uint64_t NegativeMask = decodeULEB128(Ptr, &Len); \
9571
0
      Ptr += Len; \
9572
0
      bool Fail = (insn & PositiveMask) != 0 || (~insn & NegativeMask) != 0; \
9573
0
      if (Fail) \
9574
0
        S = MCDisassembler_SoftFail; \
9575
0
      break; \
9576
0
    } \
9577
50
    case MCD_OPC_Fail: { \
9578
50
      return MCDisassembler_Fail; \
9579
0
    } \
9580
114k
    } \
9581
114k
  } \
9582
6.35k
  /* Bogisity detected in disassembler state machine! */ \
9583
6.35k
}
XtensaDisassembler.c:decodeInstruction_6
Line
Count
Source
9461
18
                                      InsnType insn, uint64_t Address, const void *Decoder) { \
9462
18
  const uint8_t *Ptr = DecodeTable; \
9463
18
  uint64_t CurFieldValue = 0; \
9464
18
  DecodeStatus S = MCDisassembler_Success; \
9465
2.70k
  while (true) { \
9466
2.70k
    switch (*Ptr) { \
9467
0
    default: \
9468
0
      return MCDisassembler_Fail; \
9469
18
    case MCD_OPC_ExtractField: { \
9470
18
      unsigned Start = *++Ptr; \
9471
18
      unsigned Len = *++Ptr; \
9472
18
      ++Ptr; \
9473
18
      CurFieldValue = fieldname(insn, Start, Len); \
9474
18
      break; \
9475
0
    } \
9476
2.64k
    case MCD_OPC_FilterValue: { \
9477
2.64k
      /* Decode the field value. */ \
9478
2.64k
      unsigned Len; \
9479
2.64k
      uint64_t Val = decodeULEB128(++Ptr, &Len); \
9480
2.64k
      Ptr += Len; \
9481
2.64k
      /* NumToSkip is a plain 24-bit integer. */ \
9482
2.64k
      unsigned NumToSkip = *Ptr++; \
9483
2.64k
      NumToSkip |= (*Ptr++) << 8; \
9484
2.64k
      NumToSkip |= (*Ptr++) << 16; \
9485
2.64k
      /* Perform the filter operation. */ \
9486
2.64k
      if (Val != CurFieldValue) \
9487
2.64k
        Ptr += NumToSkip; \
9488
2.64k
      break; \
9489
0
    } \
9490
14
    case MCD_OPC_CheckField: { \
9491
14
      unsigned Start = *++Ptr; \
9492
14
      unsigned Len = *++Ptr; \
9493
14
      uint64_t FieldValue = fieldname(insn, Start, Len); \
9494
14
      /* Decode the field value. */ \
9495
14
      unsigned PtrLen = 0; \
9496
14
      uint64_t ExpectedValue = decodeULEB128(++Ptr, &PtrLen); \
9497
14
      Ptr += PtrLen; \
9498
14
      /* NumToSkip is a plain 24-bit integer. */ \
9499
14
      unsigned NumToSkip = *Ptr++; \
9500
14
      NumToSkip |= (*Ptr++) << 8; \
9501
14
      NumToSkip |= (*Ptr++) << 16; \
9502
14
      /* If the actual and expected values don't match, skip. */ \
9503
14
      if (ExpectedValue != FieldValue) \
9504
14
        Ptr += NumToSkip; \
9505
14
      break; \
9506
0
    } \
9507
8
    case MCD_OPC_CheckPredicate: { \
9508
8
      unsigned Len; \
9509
8
      /* Decode the Predicate Index value. */ \
9510
8
      unsigned PIdx = decodeULEB128(++Ptr, &Len); \
9511
8
      Ptr += Len; \
9512
8
      /* NumToSkip is a plain 24-bit integer. */ \
9513
8
      unsigned NumToSkip = *Ptr++; \
9514
8
      NumToSkip |= (*Ptr++) << 8; \
9515
8
      NumToSkip |= (*Ptr++) << 16; \
9516
8
      /* Check the predicate. */ \
9517
8
      bool Pred = checkDecoderPredicate(MI, PIdx); \
9518
8
      if (!Pred) \
9519
8
        Ptr += NumToSkip; \
9520
8
      break; \
9521
0
    } \
9522
0
    case MCD_OPC_Decode: { \
9523
0
      unsigned Len; \
9524
0
      /* Decode the Opcode value. */ \
9525
0
      unsigned Opc = decodeULEB128(++Ptr, &Len); \
9526
0
      Ptr += Len; \
9527
0
      unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \
9528
0
      Ptr += Len; \
9529
0
      MCInst_clear(MI); \
9530
0
      MCInst_setOpcode(MI, Opc); \
9531
0
      bool DecodeComplete; \
9532
0
      S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \
9533
0
      return S; \
9534
0
    } \
9535
0
    case MCD_OPC_TryDecode: { \
9536
0
      unsigned Len; \
9537
0
      /* Decode the Opcode value. */ \
9538
0
      unsigned Opc = decodeULEB128(++Ptr, &Len); \
9539
0
      Ptr += Len; \
9540
0
      unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \
9541
0
      Ptr += Len; \
9542
0
      /* NumToSkip is a plain 24-bit integer. */ \
9543
0
      unsigned NumToSkip = *Ptr++; \
9544
0
      NumToSkip |= (*Ptr++) << 8; \
9545
0
      NumToSkip |= (*Ptr++) << 16; \
9546
0
      /* Perform the decode operation. */ \
9547
0
      MCInst_setOpcode(MI, Opc); \
9548
0
      bool DecodeComplete; \
9549
0
      S = decoder(S, DecodeIdx, insn, MI, Address, Decoder, &DecodeComplete); \
9550
0
      if (DecodeComplete) { \
9551
0
        /* Decoding complete. */ \
9552
0
        return S; \
9553
0
      } else { \
9554
0
        /* LLVM uses a MCInst on the stack, but for our use case, */ \
9555
0
        /* it is enough for now to reset the op counter. */ \
9556
0
        MCInst_clear(MI); \
9557
0
        /* If the decoding was incomplete, skip. */ \
9558
0
        Ptr += NumToSkip; \
9559
0
        /* Reset decode status. This also drops a SoftFail status that could be */ \
9560
0
        /* set before the decode attempt. */ \
9561
0
        S = MCDisassembler_Success; \
9562
0
      } \
9563
0
      break; \
9564
0
    } \
9565
0
    case MCD_OPC_SoftFail: { \
9566
0
      /* Decode the mask values. */ \
9567
0
      unsigned Len; \
9568
0
      uint64_t PositiveMask = decodeULEB128(++Ptr, &Len); \
9569
0
      Ptr += Len; \
9570
0
      uint64_t NegativeMask = decodeULEB128(Ptr, &Len); \
9571
0
      Ptr += Len; \
9572
0
      bool Fail = (insn & PositiveMask) != 0 || (~insn & NegativeMask) != 0; \
9573
0
      if (Fail) \
9574
0
        S = MCDisassembler_SoftFail; \
9575
0
      break; \
9576
0
    } \
9577
18
    case MCD_OPC_Fail: { \
9578
18
      return MCDisassembler_Fail; \
9579
0
    } \
9580
2.70k
    } \
9581
2.70k
  } \
9582
18
  /* Bogisity detected in disassembler state machine! */ \
9583
18
}
9584
9585
FieldFromInstruction(fieldFromInstruction_3, uint64_t)
9586
DecodeToMCInst(decodeToMCInst_3, fieldFromInstruction_3, uint64_t)
9587
DecodeInstruction(decodeInstruction_3, fieldFromInstruction_3, decodeToMCInst_3, uint64_t)
9588