Coverage Report

Created: 2025-07-01 07:03

/src/capstonev5/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|*Assembly Writer Source Fragment                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
15
16
/// printInstruction - This method is automatically generated by tablegen
17
/// from the instruction set description.
18
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19
30.8k
{
20
30.8k
  static const uint32_t OpInfo[] = {
21
30.8k
    0U, // PHI
22
30.8k
    0U, // INLINEASM
23
30.8k
    0U, // CFI_INSTRUCTION
24
30.8k
    0U, // EH_LABEL
25
30.8k
    0U, // GC_LABEL
26
30.8k
    0U, // KILL
27
30.8k
    0U, // EXTRACT_SUBREG
28
30.8k
    0U, // INSERT_SUBREG
29
30.8k
    0U, // IMPLICIT_DEF
30
30.8k
    0U, // SUBREG_TO_REG
31
30.8k
    0U, // COPY_TO_REGCLASS
32
30.8k
    2452U,  // DBG_VALUE
33
30.8k
    0U, // REG_SEQUENCE
34
30.8k
    0U, // COPY
35
30.8k
    2445U,  // BUNDLE
36
30.8k
    2462U,  // LIFETIME_START
37
30.8k
    2432U,  // LIFETIME_END
38
30.8k
    0U, // STACKMAP
39
30.8k
    0U, // PATCHPOINT
40
30.8k
    0U, // LOAD_STACK_GUARD
41
30.8k
    0U, // STATEPOINT
42
30.8k
    0U, // FRAME_ALLOC
43
30.8k
    4688U,  // ADDCCri
44
30.8k
    4688U,  // ADDCCrr
45
30.8k
    5925U,  // ADDCri
46
30.8k
    5925U,  // ADDCrr
47
30.8k
    4772U,  // ADDEri
48
30.8k
    4772U,  // ADDErr
49
30.8k
    4786U,  // ADDXC
50
30.8k
    4678U,  // ADDXCCC
51
30.8k
    4808U,  // ADDXri
52
30.8k
    4808U,  // ADDXrr
53
30.8k
    4808U,  // ADDri
54
30.8k
    4808U,  // ADDrr
55
30.8k
    74166U, // ADJCALLSTACKDOWN
56
30.8k
    74185U, // ADJCALLSTACKUP
57
30.8k
    5497U,  // ALIGNADDR
58
30.8k
    5127U,  // ALIGNADDRL
59
30.8k
    4695U,  // ANDCCri
60
30.8k
    4695U,  // ANDCCrr
61
30.8k
    4718U,  // ANDNCCri
62
30.8k
    4718U,  // ANDNCCrr
63
30.8k
    5182U,  // ANDNri
64
30.8k
    5182U,  // ANDNrr
65
30.8k
    5182U,  // ANDXNrr
66
30.8k
    4876U,  // ANDXri
67
30.8k
    4876U,  // ANDXrr
68
30.8k
    4876U,  // ANDri
69
30.8k
    4876U,  // ANDrr
70
30.8k
    4502U,  // ARRAY16
71
30.8k
    4255U,  // ARRAY32
72
30.8k
    4526U,  // ARRAY8
73
30.8k
    0U, // ATOMIC_LOAD_ADD_32
74
30.8k
    0U, // ATOMIC_LOAD_ADD_64
75
30.8k
    0U, // ATOMIC_LOAD_AND_32
76
30.8k
    0U, // ATOMIC_LOAD_AND_64
77
30.8k
    0U, // ATOMIC_LOAD_MAX_32
78
30.8k
    0U, // ATOMIC_LOAD_MAX_64
79
30.8k
    0U, // ATOMIC_LOAD_MIN_32
80
30.8k
    0U, // ATOMIC_LOAD_MIN_64
81
30.8k
    0U, // ATOMIC_LOAD_NAND_32
82
30.8k
    0U, // ATOMIC_LOAD_NAND_64
83
30.8k
    0U, // ATOMIC_LOAD_OR_32
84
30.8k
    0U, // ATOMIC_LOAD_OR_64
85
30.8k
    0U, // ATOMIC_LOAD_SUB_32
86
30.8k
    0U, // ATOMIC_LOAD_SUB_64
87
30.8k
    0U, // ATOMIC_LOAD_UMAX_32
88
30.8k
    0U, // ATOMIC_LOAD_UMAX_64
89
30.8k
    0U, // ATOMIC_LOAD_UMIN_32
90
30.8k
    0U, // ATOMIC_LOAD_UMIN_64
91
30.8k
    0U, // ATOMIC_LOAD_XOR_32
92
30.8k
    0U, // ATOMIC_LOAD_XOR_64
93
30.8k
    0U, // ATOMIC_SWAP_64
94
30.8k
    74271U, // BA
95
30.8k
    1194492U, // BCOND
96
30.8k
    1260028U, // BCONDA
97
30.8k
    17659U, // BINDri
98
30.8k
    17659U, // BINDrr
99
30.8k
    5065U,  // BMASK
100
30.8k
    145915U,  // BPFCC
101
30.8k
    211451U,  // BPFCCA
102
30.8k
    276987U,  // BPFCCANT
103
30.8k
    342523U,  // BPFCCNT
104
30.8k
    2106465U, // BPGEZapn
105
30.8k
    2105838U, // BPGEZapt
106
30.8k
    2106532U, // BPGEZnapn
107
30.8k
    2107288U, // BPGEZnapt
108
30.8k
    2106489U, // BPGZapn
109
30.8k
    2105856U, // BPGZapt
110
30.8k
    2106552U, // BPGZnapn
111
30.8k
    2107384U, // BPGZnapt
112
30.8k
    1456636U, // BPICC
113
30.8k
    473596U,  // BPICCA
114
30.8k
    539132U,  // BPICCANT
115
30.8k
    604668U,  // BPICCNT
116
30.8k
    2106477U, // BPLEZapn
117
30.8k
    2105847U, // BPLEZapt
118
30.8k
    2106542U, // BPLEZnapn
119
30.8k
    2107337U, // BPLEZnapt
120
30.8k
    2106500U, // BPLZapn
121
30.8k
    2105864U, // BPLZapt
122
30.8k
    2106561U, // BPLZnapn
123
30.8k
    2107428U, // BPLZnapt
124
30.8k
    2106511U, // BPNZapn
125
30.8k
    2105872U, // BPNZapt
126
30.8k
    2106570U, // BPNZnapn
127
30.8k
    2107472U, // BPNZnapt
128
30.8k
    1718780U, // BPXCC
129
30.8k
    735740U,  // BPXCCA
130
30.8k
    801276U,  // BPXCCANT
131
30.8k
    866812U,  // BPXCCNT
132
30.8k
    2106522U, // BPZapn
133
30.8k
    2105880U, // BPZapt
134
30.8k
    2106579U, // BPZnapn
135
30.8k
    2107505U, // BPZnapt
136
30.8k
    4983U,  // BSHUFFLE
137
30.8k
    74742U, // CALL
138
30.8k
    17398U, // CALLri
139
30.8k
    17398U, // CALLrr
140
30.8k
    924148U,  // CASXrr
141
30.8k
    924129U,  // CASrr
142
30.8k
    74001U, // CMASK16
143
30.8k
    73833U, // CMASK32
144
30.8k
    74150U, // CMASK8
145
30.8k
    2106607U, // CMPri
146
30.8k
    2106607U, // CMPrr
147
30.8k
    4332U,  // EDGE16
148
30.8k
    5081U,  // EDGE16L
149
30.8k
    5198U,  // EDGE16LN
150
30.8k
    5165U,  // EDGE16N
151
30.8k
    4164U,  // EDGE32
152
30.8k
    5072U,  // EDGE32L
153
30.8k
    5188U,  // EDGE32LN
154
30.8k
    5156U,  // EDGE32N
155
30.8k
    4511U,  // EDGE8
156
30.8k
    5090U,  // EDGE8L
157
30.8k
    5208U,  // EDGE8LN
158
30.8k
    5174U,  // EDGE8N
159
30.8k
    1053516U, // FABSD
160
30.8k
    1054031U, // FABSQ
161
30.8k
    1054376U, // FABSS
162
30.8k
    4813U,  // FADDD
163
30.8k
    5383U,  // FADDQ
164
30.8k
    5645U,  // FADDS
165
30.8k
    4648U,  // FALIGNADATA
166
30.8k
    4875U,  // FAND
167
30.8k
    4112U,  // FANDNOT1
168
30.8k
    5544U,  // FANDNOT1S
169
30.8k
    4271U,  // FANDNOT2
170
30.8k
    5591U,  // FANDNOT2S
171
30.8k
    5677U,  // FANDS
172
30.8k
    1194491U, // FBCOND
173
30.8k
    1260027U, // FBCONDA
174
30.8k
    4394U,  // FCHKSM16
175
30.8k
    2106173U, // FCMPD
176
30.8k
    4413U,  // FCMPEQ16
177
30.8k
    4226U,  // FCMPEQ32
178
30.8k
    4432U,  // FCMPGT16
179
30.8k
    4245U,  // FCMPGT32
180
30.8k
    4340U,  // FCMPLE16
181
30.8k
    4172U,  // FCMPLE32
182
30.8k
    4350U,  // FCMPNE16
183
30.8k
    4182U,  // FCMPNE32
184
30.8k
    2106696U, // FCMPQ
185
30.8k
    2107005U, // FCMPS
186
30.8k
    4960U,  // FDIVD
187
30.8k
    5475U,  // FDIVQ
188
30.8k
    5815U,  // FDIVS
189
30.8k
    5405U,  // FDMULQ
190
30.8k
    1053620U, // FDTOI
191
30.8k
    1053996U, // FDTOQ
192
30.8k
    1054305U, // FDTOS
193
30.8k
    1054536U, // FDTOX
194
30.8k
    1053464U, // FEXPAND
195
30.8k
    4820U,  // FHADDD
196
30.8k
    5652U,  // FHADDS
197
30.8k
    4800U,  // FHSUBD
198
30.8k
    5637U,  // FHSUBS
199
30.8k
    1053473U, // FITOD
200
30.8k
    1054003U, // FITOQ
201
30.8k
    1054312U, // FITOS
202
30.8k
    6300484U, // FLCMPD
203
30.8k
    6301316U, // FLCMPS
204
30.8k
    2606U,  // FLUSHW
205
30.8k
    4404U,  // FMEAN16
206
30.8k
    1053543U, // FMOVD
207
30.8k
    1006078U, // FMOVD_FCC
208
30.8k
    23484926U,  // FMOVD_ICC
209
30.8k
    23747070U,  // FMOVD_XCC
210
30.8k
    1054058U, // FMOVQ
211
30.8k
    1006102U, // FMOVQ_FCC
212
30.8k
    23484950U,  // FMOVQ_ICC
213
30.8k
    23747094U,  // FMOVQ_XCC
214
30.8k
    6018U,  // FMOVRGEZD
215
30.8k
    6029U,  // FMOVRGEZQ
216
30.8k
    6056U,  // FMOVRGEZS
217
30.8k
    6116U,  // FMOVRGZD
218
30.8k
    6126U,  // FMOVRGZQ
219
30.8k
    6150U,  // FMOVRGZS
220
30.8k
    6067U,  // FMOVRLEZD
221
30.8k
    6078U,  // FMOVRLEZQ
222
30.8k
    6105U,  // FMOVRLEZS
223
30.8k
    6160U,  // FMOVRLZD
224
30.8k
    6170U,  // FMOVRLZQ
225
30.8k
    6194U,  // FMOVRLZS
226
30.8k
    6204U,  // FMOVRNZD
227
30.8k
    6214U,  // FMOVRNZQ
228
30.8k
    6238U,  // FMOVRNZS
229
30.8k
    6009U,  // FMOVRZD
230
30.8k
    6248U,  // FMOVRZQ
231
30.8k
    6269U,  // FMOVRZS
232
30.8k
    1054398U, // FMOVS
233
30.8k
    1006114U, // FMOVS_FCC
234
30.8k
    23484962U,  // FMOVS_ICC
235
30.8k
    23747106U,  // FMOVS_XCC
236
30.8k
    4490U,  // FMUL8SUX16
237
30.8k
    4465U,  // FMUL8ULX16
238
30.8k
    4442U,  // FMUL8X16
239
30.8k
    5098U,  // FMUL8X16AL
240
30.8k
    5849U,  // FMUL8X16AU
241
30.8k
    4860U,  // FMULD
242
30.8k
    4477U,  // FMULD8SUX16
243
30.8k
    4452U,  // FMULD8ULX16
244
30.8k
    5413U,  // FMULQ
245
30.8k
    5714U,  // FMULS
246
30.8k
    4837U,  // FNADDD
247
30.8k
    5669U,  // FNADDS
248
30.8k
    4881U,  // FNAND
249
30.8k
    5684U,  // FNANDS
250
30.8k
    1053429U, // FNEGD
251
30.8k
    1053974U, // FNEGQ
252
30.8k
    1054283U, // FNEGS
253
30.8k
    4828U,  // FNHADDD
254
30.8k
    5660U,  // FNHADDS
255
30.8k
    4828U,  // FNMULD
256
30.8k
    5660U,  // FNMULS
257
30.8k
    5513U,  // FNOR
258
30.8k
    5778U,  // FNORS
259
30.8k
    1052698U, // FNOT1
260
30.8k
    1054131U, // FNOT1S
261
30.8k
    1052857U, // FNOT2
262
30.8k
    1054178U, // FNOT2S
263
30.8k
    5660U,  // FNSMULD
264
30.8k
    74625U, // FONE
265
30.8k
    75324U, // FONES
266
30.8k
    5508U,  // FOR
267
30.8k
    4129U,  // FORNOT1
268
30.8k
    5563U,  // FORNOT1S
269
30.8k
    4288U,  // FORNOT2
270
30.8k
    5610U,  // FORNOT2S
271
30.8k
    5772U,  // FORS
272
30.8k
    1052936U, // FPACK16
273
30.8k
    4192U,  // FPACK32
274
30.8k
    1054507U, // FPACKFIX
275
30.8k
    4323U,  // FPADD16
276
30.8k
    5620U,  // FPADD16S
277
30.8k
    4155U,  // FPADD32
278
30.8k
    5573U,  // FPADD32S
279
30.8k
    4297U,  // FPADD64
280
30.8k
    4974U,  // FPMERGE
281
30.8k
    4314U,  // FPSUB16
282
30.8k
    4580U,  // FPSUB16S
283
30.8k
    4146U,  // FPSUB32
284
30.8k
    4570U,  // FPSUB32S
285
30.8k
    1053480U, // FQTOD
286
30.8k
    1053627U, // FQTOI
287
30.8k
    1054319U, // FQTOS
288
30.8k
    1054552U, // FQTOX
289
30.8k
    4423U,  // FSLAS16
290
30.8k
    4236U,  // FSLAS32
291
30.8k
    4378U,  // FSLL16
292
30.8k
    4210U,  // FSLL32
293
30.8k
    4867U,  // FSMULD
294
30.8k
    1053523U, // FSQRTD
295
30.8k
    1054038U, // FSQRTQ
296
30.8k
    1054383U, // FSQRTS
297
30.8k
    4306U,  // FSRA16
298
30.8k
    4138U,  // FSRA32
299
30.8k
    1052681U, // FSRC1
300
30.8k
    1054112U, // FSRC1S
301
30.8k
    1052840U, // FSRC2
302
30.8k
    1054159U, // FSRC2S
303
30.8k
    4386U,  // FSRL16
304
30.8k
    4218U,  // FSRL32
305
30.8k
    1053487U, // FSTOD
306
30.8k
    1053634U, // FSTOI
307
30.8k
    1054010U, // FSTOQ
308
30.8k
    1054559U, // FSTOX
309
30.8k
    4793U,  // FSUBD
310
30.8k
    5376U,  // FSUBQ
311
30.8k
    5630U,  // FSUBS
312
30.8k
    5519U,  // FXNOR
313
30.8k
    5785U,  // FXNORS
314
30.8k
    5526U,  // FXOR
315
30.8k
    5793U,  // FXORS
316
30.8k
    1053494U, // FXTOD
317
30.8k
    1054017U, // FXTOQ
318
30.8k
    1054326U, // FXTOS
319
30.8k
    74984U, // FZERO
320
30.8k
    75353U, // FZEROS
321
30.8k
    24584U, // GETPCX
322
30.8k
    1078273U, // JMPLri
323
30.8k
    1078273U, // JMPLrr
324
30.8k
    1997243U, // LDDFri
325
30.8k
    1997243U, // LDDFrr
326
30.8k
    1997249U, // LDFri
327
30.8k
    1997249U, // LDFrr
328
30.8k
    1997275U, // LDQFri
329
30.8k
    1997275U, // LDQFrr
330
30.8k
    1997229U, // LDSBri
331
30.8k
    1997229U, // LDSBrr
332
30.8k
    1997254U, // LDSHri
333
30.8k
    1997254U, // LDSHrr
334
30.8k
    1997287U, // LDSWri
335
30.8k
    1997287U, // LDSWrr
336
30.8k
    1997236U, // LDUBri
337
30.8k
    1997236U, // LDUBrr
338
30.8k
    1997261U, // LDUHri
339
30.8k
    1997261U, // LDUHrr
340
30.8k
    1997294U, // LDXri
341
30.8k
    1997294U, // LDXrr
342
30.8k
    1997249U, // LDri
343
30.8k
    1997249U, // LDrr
344
30.8k
    33480U, // LEAX_ADDri
345
30.8k
    33480U, // LEA_ADDri
346
30.8k
    1054405U, // LZCNT
347
30.8k
    75121U, // MEMBARi
348
30.8k
    1054543U, // MOVDTOX
349
30.8k
    1006122U, // MOVFCCri
350
30.8k
    1006122U, // MOVFCCrr
351
30.8k
    23484970U,  // MOVICCri
352
30.8k
    23484970U,  // MOVICCrr
353
30.8k
    6047U,  // MOVRGEZri
354
30.8k
    6047U,  // MOVRGEZrr
355
30.8k
    6142U,  // MOVRGZri
356
30.8k
    6142U,  // MOVRGZrr
357
30.8k
    6096U,  // MOVRLEZri
358
30.8k
    6096U,  // MOVRLEZrr
359
30.8k
    6186U,  // MOVRLZri
360
30.8k
    6186U,  // MOVRLZrr
361
30.8k
    6230U,  // MOVRNZri
362
30.8k
    6230U,  // MOVRNZrr
363
30.8k
    6262U,  // MOVRRZri
364
30.8k
    6262U,  // MOVRRZrr
365
30.8k
    1054469U, // MOVSTOSW
366
30.8k
    1054479U, // MOVSTOUW
367
30.8k
    1054543U, // MOVWTOS
368
30.8k
    23747114U,  // MOVXCCri
369
30.8k
    23747114U,  // MOVXCCrr
370
30.8k
    1054543U, // MOVXTOD
371
30.8k
    5954U,  // MULXri
372
30.8k
    5954U,  // MULXrr
373
30.8k
    2578U,  // NOP
374
30.8k
    4735U,  // ORCCri
375
30.8k
    4735U,  // ORCCrr
376
30.8k
    4726U,  // ORNCCri
377
30.8k
    4726U,  // ORNCCrr
378
30.8k
    5339U,  // ORNri
379
30.8k
    5339U,  // ORNrr
380
30.8k
    5339U,  // ORXNrr
381
30.8k
    5509U,  // ORXri
382
30.8k
    5509U,  // ORXrr
383
30.8k
    5509U,  // ORri
384
30.8k
    5509U,  // ORrr
385
30.8k
    5836U,  // PDIST
386
30.8k
    5344U,  // PDISTN
387
30.8k
    1053356U, // POPCrr
388
30.8k
    73729U, // RDY
389
30.8k
    4999U,  // RESTOREri
390
30.8k
    4999U,  // RESTORErr
391
30.8k
    76132U, // RET
392
30.8k
    76141U, // RETL
393
30.8k
    18131U, // RETTri
394
30.8k
    18131U, // RETTrr
395
30.8k
    5008U,  // SAVEri
396
30.8k
    5008U,  // SAVErr
397
30.8k
    4748U,  // SDIVCCri
398
30.8k
    4748U,  // SDIVCCrr
399
30.8k
    5995U,  // SDIVXri
400
30.8k
    5995U,  // SDIVXrr
401
30.8k
    5861U,  // SDIVri
402
30.8k
    5861U,  // SDIVrr
403
30.8k
    2182U,  // SELECT_CC_DFP_FCC
404
30.8k
    2293U,  // SELECT_CC_DFP_ICC
405
30.8k
    2238U,  // SELECT_CC_FP_FCC
406
30.8k
    2349U,  // SELECT_CC_FP_ICC
407
30.8k
    2265U,  // SELECT_CC_Int_FCC
408
30.8k
    2376U,  // SELECT_CC_Int_ICC
409
30.8k
    2210U,  // SELECT_CC_QFP_FCC
410
30.8k
    2321U,  // SELECT_CC_QFP_ICC
411
30.8k
    1053595U, // SETHIXi
412
30.8k
    1053595U, // SETHIi
413
30.8k
    2569U,  // SHUTDOWN
414
30.8k
    2564U,  // SIAM
415
30.8k
    5941U,  // SLLXri
416
30.8k
    5941U,  // SLLXrr
417
30.8k
    5116U,  // SLLri
418
30.8k
    5116U,  // SLLrr
419
30.8k
    4702U,  // SMULCCri
420
30.8k
    4702U,  // SMULCCrr
421
30.8k
    5144U,  // SMULri
422
30.8k
    5144U,  // SMULrr
423
30.8k
    5913U,  // SRAXri
424
30.8k
    5913U,  // SRAXrr
425
30.8k
    4643U,  // SRAri
426
30.8k
    4643U,  // SRArr
427
30.8k
    5947U,  // SRLXri
428
30.8k
    5947U,  // SRLXrr
429
30.8k
    5139U,  // SRLri
430
30.8k
    5139U,  // SRLrr
431
30.8k
    2588U,  // STBAR
432
30.8k
    37428U, // STBri
433
30.8k
    37428U, // STBrr
434
30.8k
    37723U, // STDFri
435
30.8k
    37723U, // STDFrr
436
30.8k
    38607U, // STFri
437
30.8k
    38607U, // STFrr
438
30.8k
    37782U, // STHri
439
30.8k
    37782U, // STHrr
440
30.8k
    38238U, // STQFri
441
30.8k
    38238U, // STQFrr
442
30.8k
    38758U, // STXri
443
30.8k
    38758U, // STXrr
444
30.8k
    38607U, // STri
445
30.8k
    38607U, // STrr
446
30.8k
    4671U,  // SUBCCri
447
30.8k
    4671U,  // SUBCCrr
448
30.8k
    5919U,  // SUBCri
449
30.8k
    5919U,  // SUBCrr
450
30.8k
    4764U,  // SUBEri
451
30.8k
    4764U,  // SUBErr
452
30.8k
    4665U,  // SUBXri
453
30.8k
    4665U,  // SUBXrr
454
30.8k
    4665U,  // SUBri
455
30.8k
    4665U,  // SUBrr
456
30.8k
    1997268U, // SWAPri
457
30.8k
    1997268U, // SWAPrr
458
30.8k
    2422U,  // TA3
459
30.8k
    2427U,  // TA5
460
30.8k
    5883U,  // TADDCCTVri
461
30.8k
    5883U,  // TADDCCTVrr
462
30.8k
    4687U,  // TADDCCri
463
30.8k
    4687U,  // TADDCCrr
464
30.8k
    9873960U, // TICCri
465
30.8k
    9873960U, // TICCrr
466
30.8k
    37753544U,  // TLS_ADDXrr
467
30.8k
    37753544U,  // TLS_ADDrr
468
30.8k
    2106358U, // TLS_CALL
469
30.8k
    39746030U,  // TLS_LDXrr
470
30.8k
    39745985U,  // TLS_LDrr
471
30.8k
    5873U,  // TSUBCCTVri
472
30.8k
    5873U,  // TSUBCCTVrr
473
30.8k
    4670U,  // TSUBCCri
474
30.8k
    4670U,  // TSUBCCrr
475
30.8k
    10136104U,  // TXCCri
476
30.8k
    10136104U,  // TXCCrr
477
30.8k
    4756U,  // UDIVCCri
478
30.8k
    4756U,  // UDIVCCrr
479
30.8k
    6002U,  // UDIVXri
480
30.8k
    6002U,  // UDIVXrr
481
30.8k
    5867U,  // UDIVri
482
30.8k
    5867U,  // UDIVrr
483
30.8k
    4710U,  // UMULCCri
484
30.8k
    4710U,  // UMULCCrr
485
30.8k
    5026U,  // UMULXHI
486
30.8k
    5150U,  // UMULri
487
30.8k
    5150U,  // UMULrr
488
30.8k
    74996U, // UNIMP
489
30.8k
    6300477U, // V9FCMPD
490
30.8k
    6300397U, // V9FCMPED
491
30.8k
    6300942U, // V9FCMPEQ
492
30.8k
    6301251U, // V9FCMPES
493
30.8k
    6301000U, // V9FCMPQ
494
30.8k
    6301309U, // V9FCMPS
495
30.8k
    47614U, // V9FMOVD_FCC
496
30.8k
    47638U, // V9FMOVQ_FCC
497
30.8k
    47650U, // V9FMOVS_FCC
498
30.8k
    47658U, // V9MOVFCCri
499
30.8k
    47658U, // V9MOVFCCrr
500
30.8k
    14689692U,  // WRYri
501
30.8k
    14689692U,  // WRYrr
502
30.8k
    5953U,  // XMULX
503
30.8k
    5035U,  // XMULXHI
504
30.8k
    4733U,  // XNORCCri
505
30.8k
    4733U,  // XNORCCrr
506
30.8k
    5520U,  // XNORXrr
507
30.8k
    5520U,  // XNORri
508
30.8k
    5520U,  // XNORrr
509
30.8k
    4741U,  // XORCCri
510
30.8k
    4741U,  // XORCCrr
511
30.8k
    5527U,  // XORXri
512
30.8k
    5527U,  // XORXrr
513
30.8k
    5527U,  // XORri
514
30.8k
    5527U,  // XORrr
515
30.8k
    0U
516
30.8k
  };
517
518
30.8k
#ifndef CAPSTONE_DIET
519
30.8k
  static const char AsmStrs[] = {
520
30.8k
  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521
30.8k
  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522
30.8k
  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523
30.8k
  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524
30.8k
  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525
30.8k
  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526
30.8k
  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527
30.8k
  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528
30.8k
  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529
30.8k
  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530
30.8k
  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531
30.8k
  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532
30.8k
  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533
30.8k
  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534
30.8k
  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535
30.8k
  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536
30.8k
  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537
30.8k
  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538
30.8k
  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539
30.8k
  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540
30.8k
  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541
30.8k
  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542
30.8k
  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543
30.8k
  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544
30.8k
  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545
30.8k
  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546
30.8k
  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547
30.8k
  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548
30.8k
  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549
30.8k
  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550
30.8k
  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551
30.8k
  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552
30.8k
  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553
30.8k
  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554
30.8k
  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555
30.8k
  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556
30.8k
  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557
30.8k
  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558
30.8k
  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559
30.8k
  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560
30.8k
  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561
30.8k
  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562
30.8k
  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563
30.8k
  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564
30.8k
  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565
30.8k
  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566
30.8k
  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567
30.8k
  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568
30.8k
  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569
30.8k
  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570
30.8k
  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571
30.8k
  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572
30.8k
  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573
30.8k
  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574
30.8k
  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575
30.8k
  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576
30.8k
  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577
30.8k
  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578
30.8k
  /* 542 */ 'b', 'a', 32, 0,
579
30.8k
  /* 546 */ 's', 'r', 'a', 32, 0,
580
30.8k
  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581
30.8k
  /* 563 */ 's', 't', 'b', 32, 0,
582
30.8k
  /* 568 */ 's', 'u', 'b', 32, 0,
583
30.8k
  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584
30.8k
  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585
30.8k
  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586
30.8k
  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587
30.8k
  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588
30.8k
  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589
30.8k
  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590
30.8k
  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591
30.8k
  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592
30.8k
  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593
30.8k
  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594
30.8k
  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595
30.8k
  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596
30.8k
  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597
30.8k
  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598
30.8k
  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599
30.8k
  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600
30.8k
  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601
30.8k
  /* 711 */ 'a', 'd', 'd', 32, 0,
602
30.8k
  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603
30.8k
  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604
30.8k
  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605
30.8k
  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606
30.8k
  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607
30.8k
  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608
30.8k
  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609
30.8k
  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610
30.8k
  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611
30.8k
  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612
30.8k
  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613
30.8k
  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614
30.8k
  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615
30.8k
  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616
30.8k
  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617
30.8k
  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618
30.8k
  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619
30.8k
  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620
30.8k
  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621
30.8k
  /* 858 */ 's', 't', 'd', 32, 0,
622
30.8k
  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623
30.8k
  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624
30.8k
  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625
30.8k
  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626
30.8k
  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627
30.8k
  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628
30.8k
  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629
30.8k
  /* 917 */ 's', 't', 'h', 32, 0,
630
30.8k
  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631
30.8k
  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632
30.8k
  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633
30.8k
  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634
30.8k
  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635
30.8k
  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636
30.8k
  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637
30.8k
  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638
30.8k
  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639
30.8k
  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640
30.8k
  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641
30.8k
  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642
30.8k
  /* 1019 */ 's', 'l', 'l', 32, 0,
643
30.8k
  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644
30.8k
  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645
30.8k
  /* 1042 */ 's', 'r', 'l', 32, 0,
646
30.8k
  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647
30.8k
  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648
30.8k
  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649
30.8k
  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650
30.8k
  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651
30.8k
  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652
30.8k
  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653
30.8k
  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654
30.8k
  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655
30.8k
  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656
30.8k
  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657
30.8k
  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658
30.8k
  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659
30.8k
  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660
30.8k
  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661
30.8k
  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662
30.8k
  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663
30.8k
  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664
30.8k
  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665
30.8k
  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666
30.8k
  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667
30.8k
  /* 1242 */ 'o', 'r', 'n', 32, 0,
668
30.8k
  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669
30.8k
  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670
30.8k
  /* 1262 */ 'c', 'm', 'p', 32, 0,
671
30.8k
  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672
30.8k
  /* 1274 */ 'j', 'm', 'p', 32, 0,
673
30.8k
  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674
30.8k
  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675
30.8k
  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676
30.8k
  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677
30.8k
  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678
30.8k
  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679
30.8k
  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680
30.8k
  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681
30.8k
  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682
30.8k
  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683
30.8k
  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684
30.8k
  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685
30.8k
  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686
30.8k
  /* 1373 */ 's', 't', 'q', 32, 0,
687
30.8k
  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688
30.8k
  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689
30.8k
  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690
30.8k
  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691
30.8k
  /* 1411 */ 'f', 'o', 'r', 32, 0,
692
30.8k
  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693
30.8k
  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694
30.8k
  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695
30.8k
  /* 1435 */ 'w', 'r', 32, 0,
696
30.8k
  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697
30.8k
  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698
30.8k
  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699
30.8k
  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700
30.8k
  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701
30.8k
  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702
30.8k
  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703
30.8k
  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704
30.8k
  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705
30.8k
  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706
30.8k
  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707
30.8k
  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708
30.8k
  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709
30.8k
  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710
30.8k
  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711
30.8k
  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712
30.8k
  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713
30.8k
  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714
30.8k
  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715
30.8k
  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716
30.8k
  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717
30.8k
  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718
30.8k
  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719
30.8k
  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720
30.8k
  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721
30.8k
  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722
30.8k
  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723
30.8k
  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724
30.8k
  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725
30.8k
  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726
30.8k
  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727
30.8k
  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728
30.8k
  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729
30.8k
  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730
30.8k
  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731
30.8k
  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732
30.8k
  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733
30.8k
  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734
30.8k
  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735
30.8k
  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736
30.8k
  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737
30.8k
  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738
30.8k
  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739
30.8k
  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740
30.8k
  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741
30.8k
  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742
30.8k
  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743
30.8k
  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744
30.8k
  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745
30.8k
  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746
30.8k
  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747
30.8k
  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748
30.8k
  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749
30.8k
  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750
30.8k
  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751
30.8k
  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752
30.8k
  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753
30.8k
  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754
30.8k
  /* 1893 */ 's', 't', 'x', 32, 0,
755
30.8k
  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756
30.8k
  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757
30.8k
  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758
30.8k
  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759
30.8k
  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760
30.8k
  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761
30.8k
  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762
30.8k
  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763
30.8k
  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764
30.8k
  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765
30.8k
  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766
30.8k
  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767
30.8k
  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768
30.8k
  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769
30.8k
  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770
30.8k
  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771
30.8k
  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772
30.8k
  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773
30.8k
  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774
30.8k
  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775
30.8k
  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776
30.8k
  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777
30.8k
  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778
30.8k
  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779
30.8k
  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780
30.8k
  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781
30.8k
  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782
30.8k
  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783
30.8k
  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784
30.8k
  /* 2160 */ 'b', 'r', 'z', 32, 0,
785
30.8k
  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786
30.8k
  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787
30.8k
  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788
30.8k
  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789
30.8k
  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790
30.8k
  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791
30.8k
  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792
30.8k
  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793
30.8k
  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794
30.8k
  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795
30.8k
  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796
30.8k
  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797
30.8k
  /* 2421 */ 't', 'a', 32, '3', 0,
798
30.8k
  /* 2426 */ 't', 'a', 32, '5', 0,
799
30.8k
  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800
30.8k
  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801
30.8k
  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802
30.8k
  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803
30.8k
  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804
30.8k
  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805
30.8k
  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806
30.8k
  /* 2496 */ 'l', 'd', 32, '[', 0,
807
30.8k
  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808
30.8k
  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809
30.8k
  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810
30.8k
  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811
30.8k
  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812
30.8k
  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813
30.8k
  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814
30.8k
  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815
30.8k
  /* 2554 */ 'f', 'b', 0,
816
30.8k
  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817
30.8k
  /* 2563 */ 's', 'i', 'a', 'm', 0,
818
30.8k
  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819
30.8k
  /* 2577 */ 'n', 'o', 'p', 0,
820
30.8k
  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821
30.8k
  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822
30.8k
  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823
30.8k
  /* 2599 */ 't', 0,
824
30.8k
  /* 2601 */ 'm', 'o', 'v', 0,
825
30.8k
  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826
30.8k
  };
827
30.8k
#endif
828
829
  // Emit the opcode for the instruction.
830
30.8k
  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831
30.8k
#ifndef CAPSTONE_DIET
832
  // assert(Bits != 0 && "Cannot print this instruction.");
833
30.8k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834
30.8k
#endif
835
836
837
  // Fragment 0 encoded into 4 bits for 12 unique commands.
838
  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839
30.8k
  switch ((Bits >> 12) & 15) {
840
0
  default:   // unreachable.
841
69
  case 0:
842
    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843
69
    return;
844
0
    break;
845
5.96k
  case 1:
846
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847
5.96k
    printOperand(MI, 1, O); 
848
5.96k
    break;
849
17.2k
  case 2:
850
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851
17.2k
    printOperand(MI, 0, O); 
852
17.2k
    break;
853
2.53k
  case 3:
854
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855
2.53k
    printCCOperand(MI, 1, O); 
856
2.53k
    break;
857
585
  case 4:
858
    // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859
585
    printMemOperand(MI, 0, O, NULL); 
860
585
    return;
861
0
    break;
862
1.56k
  case 5:
863
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864
1.56k
    printCCOperand(MI, 3, O); 
865
1.56k
    break;
866
0
  case 6:
867
    // GETPCX
868
0
    printGetPCX(MI, 0, O); 
869
0
    return;
870
0
    break;
871
904
  case 7:
872
    // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873
904
    printMemOperand(MI, 1, O, NULL); 
874
904
    break;
875
0
  case 8:
876
    // LEAX_ADDri, LEA_ADDri
877
0
    printMemOperand(MI, 1, O, "arith"); 
878
0
    SStream_concat0(O, ", "); 
879
0
    printOperand(MI, 0, O); 
880
0
    return;
881
0
    break;
882
790
  case 9:
883
    // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884
790
    printOperand(MI, 2, O); 
885
790
    SStream_concat0(O, ", ["); 
886
790
    printMemOperand(MI, 0, O, NULL); 
887
790
    SStream_concat0(O, "]"); 
888
790
    return;
889
0
    break;
890
475
  case 10:
891
    // TICCri, TICCrr, TXCCri, TXCCrr
892
475
    printCCOperand(MI, 2, O); 
893
475
    break;
894
699
  case 11:
895
    // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896
699
    printCCOperand(MI, 4, O); 
897
699
    SStream_concat0(O, " "); 
898
699
    printOperand(MI, 1, O); 
899
699
    SStream_concat0(O, ", "); 
900
699
    printOperand(MI, 2, O); 
901
699
    SStream_concat0(O, ", "); 
902
699
    printOperand(MI, 0, O); 
903
699
    return;
904
0
    break;
905
30.8k
  }
906
907
908
  // Fragment 1 encoded into 4 bits for 16 unique commands.
909
  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910
28.7k
  switch ((Bits >> 16) & 15) {
911
0
  default:   // unreachable.
912
8.74k
  case 0:
913
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914
8.74k
    SStream_concat0(O, ", "); 
915
8.74k
    break;
916
14.4k
  case 1:
917
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918
14.4k
    return;
919
0
    break;
920
857
  case 2:
921
    // BCOND, BPFCC, FBCOND
922
857
    SStream_concat0(O, " "); 
923
857
    break;
924
731
  case 3:
925
    // BCONDA, BPFCCA, FBCONDA
926
731
    SStream_concat0(O, ",a ");
927
731
  Sparc_add_hint(MI, SPARC_HINT_A);
928
731
    break;
929
0
  case 4:
930
    // BPFCCANT
931
0
    SStream_concat0(O, ",a,pn ");
932
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933
0
    printOperand(MI, 2, O); 
934
0
    SStream_concat0(O, ", "); 
935
0
    printOperand(MI, 0, O); 
936
0
    return;
937
0
    break;
938
0
  case 5:
939
    // BPFCCNT
940
0
    SStream_concat0(O, ",pn ");
941
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
942
0
    printOperand(MI, 2, O); 
943
0
    SStream_concat0(O, ", "); 
944
0
    printOperand(MI, 0, O); 
945
0
    return;
946
0
    break;
947
1.25k
  case 6:
948
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949
1.25k
    SStream_concat0(O, " %icc, ");
950
1.25k
  Sparc_add_reg(MI, SPARC_REG_ICC);
951
1.25k
    break;
952
171
  case 7:
953
    // BPICCA
954
171
    SStream_concat0(O, ",a %icc, ");
955
171
  Sparc_add_hint(MI, SPARC_HINT_A);
956
171
  Sparc_add_reg(MI, SPARC_REG_ICC);
957
171
    printOperand(MI, 0, O); 
958
171
    return;
959
0
    break;
960
0
  case 8:
961
    // BPICCANT
962
0
    SStream_concat0(O, ",a,pn %icc, ");
963
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
965
0
    printOperand(MI, 0, O); 
966
0
    return;
967
0
    break;
968
0
  case 9:
969
    // BPICCNT
970
0
    SStream_concat0(O, ",pn %icc, ");
971
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
972
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
973
0
    printOperand(MI, 0, O); 
974
0
    return;
975
0
    break;
976
561
  case 10:
977
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978
561
    SStream_concat0(O, " %xcc, ");
979
561
  Sparc_add_reg(MI, SPARC_REG_XCC);
980
561
    break;
981
437
  case 11:
982
    // BPXCCA
983
437
    SStream_concat0(O, ",a %xcc, ");
984
437
  Sparc_add_hint(MI, SPARC_HINT_A);
985
437
  Sparc_add_reg(MI, SPARC_REG_XCC);
986
437
    printOperand(MI, 0, O); 
987
437
    return;
988
0
    break;
989
0
  case 12:
990
    // BPXCCANT
991
0
    SStream_concat0(O, ",a,pn %xcc, ");
992
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
994
0
    printOperand(MI, 0, O); 
995
0
    return;
996
0
    break;
997
0
  case 13:
998
    // BPXCCNT
999
0
    SStream_concat0(O, ",pn %xcc, ");
1000
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
1001
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
1002
0
    printOperand(MI, 0, O); 
1003
0
    return;
1004
0
    break;
1005
934
  case 14:
1006
    // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007
934
    SStream_concat0(O, "], "); 
1008
934
    break;
1009
556
  case 15:
1010
    // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011
556
    SStream_concat0(O, " %fcc0, ");
1012
556
  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013
556
    printOperand(MI, 1, O); 
1014
556
    SStream_concat0(O, ", "); 
1015
556
    printOperand(MI, 0, O); 
1016
556
    return;
1017
0
    break;
1018
28.7k
  }
1019
1020
1021
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022
  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023
13.0k
  switch ((Bits >> 20) & 3) {
1024
0
  default:   // unreachable.
1025
3.67k
  case 0:
1026
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027
3.67k
    printOperand(MI, 2, O); 
1028
3.67k
    SStream_concat0(O, ", "); 
1029
3.67k
    printOperand(MI, 0, O); 
1030
3.67k
    break;
1031
5.59k
  case 1:
1032
    // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033
5.59k
    printOperand(MI, 0, O); 
1034
5.59k
    break;
1035
3.80k
  case 2:
1036
    // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037
3.80k
    printOperand(MI, 1, O); 
1038
3.80k
    break;
1039
13.0k
  }
1040
1041
1042
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043
  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044
13.0k
  switch ((Bits >> 22) & 3) {
1045
0
  default:   // unreachable.
1046
10.7k
  case 0:
1047
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048
10.7k
    return;
1049
0
    break;
1050
1.70k
  case 1:
1051
    // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052
1.70k
    SStream_concat0(O, ", "); 
1053
1.70k
    break;
1054
475
  case 2:
1055
    // TICCri, TICCrr, TXCCri, TXCCrr
1056
475
    SStream_concat0(O, " + ");  // qq
1057
475
    printOperand(MI, 1, O); 
1058
475
    return;
1059
0
    break;
1060
197
  case 3:
1061
    // WRYri, WRYrr
1062
197
    SStream_concat0(O, ", %y");
1063
197
  Sparc_add_reg(MI, SPARC_REG_Y);
1064
197
    return;
1065
0
    break;
1066
13.0k
  }
1067
1068
1069
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070
  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071
1.70k
  switch ((Bits >> 24) & 3) {
1072
0
  default:   // unreachable.
1073
700
  case 0:
1074
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075
700
    printOperand(MI, 2, O); 
1076
700
    return;
1077
0
    break;
1078
1.00k
  case 1:
1079
    // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080
1.00k
    printOperand(MI, 0, O); 
1081
1.00k
    return;
1082
0
    break;
1083
0
  case 2:
1084
    // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085
0
    printOperand(MI, 3, O); 
1086
0
    return;
1087
0
    break;
1088
1.70k
  }
1089
1.70k
}
1090
1091
1092
/// getRegisterName - This method is automatically generated by tblgen
1093
/// from the register set description.  This returns the assembler name
1094
/// for the specified register.
1095
static const char *getRegisterName(unsigned RegNo)
1096
39.6k
{
1097
  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098
1099
39.6k
#ifndef CAPSTONE_DIET
1100
39.6k
  static const char AsmStrs[] = {
1101
39.6k
  /* 0 */ 'f', '1', '0', 0,
1102
39.6k
  /* 4 */ 'f', '2', '0', 0,
1103
39.6k
  /* 8 */ 'f', '3', '0', 0,
1104
39.6k
  /* 12 */ 'f', '4', '0', 0,
1105
39.6k
  /* 16 */ 'f', '5', '0', 0,
1106
39.6k
  /* 20 */ 'f', '6', '0', 0,
1107
39.6k
  /* 24 */ 'f', 'c', 'c', '0', 0,
1108
39.6k
  /* 29 */ 'f', '0', 0,
1109
39.6k
  /* 32 */ 'g', '0', 0,
1110
39.6k
  /* 35 */ 'i', '0', 0,
1111
39.6k
  /* 38 */ 'l', '0', 0,
1112
39.6k
  /* 41 */ 'o', '0', 0,
1113
39.6k
  /* 44 */ 'f', '1', '1', 0,
1114
39.6k
  /* 48 */ 'f', '2', '1', 0,
1115
39.6k
  /* 52 */ 'f', '3', '1', 0,
1116
39.6k
  /* 56 */ 'f', 'c', 'c', '1', 0,
1117
39.6k
  /* 61 */ 'f', '1', 0,
1118
39.6k
  /* 64 */ 'g', '1', 0,
1119
39.6k
  /* 67 */ 'i', '1', 0,
1120
39.6k
  /* 70 */ 'l', '1', 0,
1121
39.6k
  /* 73 */ 'o', '1', 0,
1122
39.6k
  /* 76 */ 'f', '1', '2', 0,
1123
39.6k
  /* 80 */ 'f', '2', '2', 0,
1124
39.6k
  /* 84 */ 'f', '3', '2', 0,
1125
39.6k
  /* 88 */ 'f', '4', '2', 0,
1126
39.6k
  /* 92 */ 'f', '5', '2', 0,
1127
39.6k
  /* 96 */ 'f', '6', '2', 0,
1128
39.6k
  /* 100 */ 'f', 'c', 'c', '2', 0,
1129
39.6k
  /* 105 */ 'f', '2', 0,
1130
39.6k
  /* 108 */ 'g', '2', 0,
1131
39.6k
  /* 111 */ 'i', '2', 0,
1132
39.6k
  /* 114 */ 'l', '2', 0,
1133
39.6k
  /* 117 */ 'o', '2', 0,
1134
39.6k
  /* 120 */ 'f', '1', '3', 0,
1135
39.6k
  /* 124 */ 'f', '2', '3', 0,
1136
39.6k
  /* 128 */ 'f', 'c', 'c', '3', 0,
1137
39.6k
  /* 133 */ 'f', '3', 0,
1138
39.6k
  /* 136 */ 'g', '3', 0,
1139
39.6k
  /* 139 */ 'i', '3', 0,
1140
39.6k
  /* 142 */ 'l', '3', 0,
1141
39.6k
  /* 145 */ 'o', '3', 0,
1142
39.6k
  /* 148 */ 'f', '1', '4', 0,
1143
39.6k
  /* 152 */ 'f', '2', '4', 0,
1144
39.6k
  /* 156 */ 'f', '3', '4', 0,
1145
39.6k
  /* 160 */ 'f', '4', '4', 0,
1146
39.6k
  /* 164 */ 'f', '5', '4', 0,
1147
39.6k
  /* 168 */ 'f', '4', 0,
1148
39.6k
  /* 171 */ 'g', '4', 0,
1149
39.6k
  /* 174 */ 'i', '4', 0,
1150
39.6k
  /* 177 */ 'l', '4', 0,
1151
39.6k
  /* 180 */ 'o', '4', 0,
1152
39.6k
  /* 183 */ 'f', '1', '5', 0,
1153
39.6k
  /* 187 */ 'f', '2', '5', 0,
1154
39.6k
  /* 191 */ 'f', '5', 0,
1155
39.6k
  /* 194 */ 'g', '5', 0,
1156
39.6k
  /* 197 */ 'i', '5', 0,
1157
39.6k
  /* 200 */ 'l', '5', 0,
1158
39.6k
  /* 203 */ 'o', '5', 0,
1159
39.6k
  /* 206 */ 'f', '1', '6', 0,
1160
39.6k
  /* 210 */ 'f', '2', '6', 0,
1161
39.6k
  /* 214 */ 'f', '3', '6', 0,
1162
39.6k
  /* 218 */ 'f', '4', '6', 0,
1163
39.6k
  /* 222 */ 'f', '5', '6', 0,
1164
39.6k
  /* 226 */ 'f', '6', 0,
1165
39.6k
  /* 229 */ 'g', '6', 0,
1166
39.6k
  /* 232 */ 'l', '6', 0,
1167
39.6k
  /* 235 */ 'f', '1', '7', 0,
1168
39.6k
  /* 239 */ 'f', '2', '7', 0,
1169
39.6k
  /* 243 */ 'f', '7', 0,
1170
39.6k
  /* 246 */ 'g', '7', 0,
1171
39.6k
  /* 249 */ 'i', '7', 0,
1172
39.6k
  /* 252 */ 'l', '7', 0,
1173
39.6k
  /* 255 */ 'o', '7', 0,
1174
39.6k
  /* 258 */ 'f', '1', '8', 0,
1175
39.6k
  /* 262 */ 'f', '2', '8', 0,
1176
39.6k
  /* 266 */ 'f', '3', '8', 0,
1177
39.6k
  /* 270 */ 'f', '4', '8', 0,
1178
39.6k
  /* 274 */ 'f', '5', '8', 0,
1179
39.6k
  /* 278 */ 'f', '8', 0,
1180
39.6k
  /* 281 */ 'f', '1', '9', 0,
1181
39.6k
  /* 285 */ 'f', '2', '9', 0,
1182
39.6k
  /* 289 */ 'f', '9', 0,
1183
39.6k
  /* 292 */ 'i', 'c', 'c', 0,
1184
39.6k
  /* 296 */ 'f', 'p', 0,
1185
39.6k
  /* 299 */ 's', 'p', 0,
1186
39.6k
  /* 302 */ 'y', 0,
1187
39.6k
  };
1188
1189
39.6k
  static const uint16_t RegAsmOffset[] = {
1190
39.6k
    292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 
1191
39.6k
    152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 
1192
39.6k
    92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 
1193
39.6k
    278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 
1194
39.6k
    80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 
1195
39.6k
    32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 
1196
39.6k
    296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 
1197
39.6k
    180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 
1198
39.6k
    12, 160, 270, 92, 222, 20, 
1199
39.6k
  };
1200
1201
  //int i;
1202
  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203
  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204
  //printf("*************************\n");
1205
39.6k
  return AsmStrs+RegAsmOffset[RegNo-1];
1206
#else
1207
  return NULL;
1208
#endif
1209
39.6k
}
1210
1211
#ifdef PRINT_ALIAS_INSTR
1212
#undef PRINT_ALIAS_INSTR
1213
1214
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1215
  unsigned PrintMethodIdx, SStream *OS)
1216
0
{
1217
0
}
1218
1219
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1220
51.5k
{
1221
220k
  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1222
51.5k
  const char *AsmString;
1223
51.5k
  char *tmp, *AsmMnem, *AsmOps, *c;
1224
51.5k
  int OpIdx, PrintMethodIdx;
1225
51.5k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1226
51.5k
  switch (MCInst_getOpcode(MI)) {
1227
28.8k
  default: return NULL;
1228
1.79k
  case SP_BCOND:
1229
1.79k
    if (MCInst_getNumOperands(MI) == 2 &&
1230
1.79k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1231
1.79k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1232
      // (BCOND brtarget:$imm, 8)
1233
0
      AsmString = "ba $\x01";
1234
0
      break;
1235
0
    }
1236
1.79k
    if (MCInst_getNumOperands(MI) == 2 &&
1237
1.79k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1238
1.79k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1239
      // (BCOND brtarget:$imm, 0)
1240
418
      AsmString = "bn $\x01";
1241
418
      break;
1242
418
    }
1243
1.37k
    if (MCInst_getNumOperands(MI) == 2 &&
1244
1.37k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1245
1.37k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1246
      // (BCOND brtarget:$imm, 9)
1247
62
      AsmString = "bne $\x01";
1248
62
      break;
1249
62
    }
1250
1.31k
    if (MCInst_getNumOperands(MI) == 2 &&
1251
1.31k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1252
1.31k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1253
      // (BCOND brtarget:$imm, 1)
1254
29
      AsmString = "be $\x01";
1255
29
      break;
1256
29
    }
1257
1.28k
    if (MCInst_getNumOperands(MI) == 2 &&
1258
1.28k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1259
1.28k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1260
      // (BCOND brtarget:$imm, 10)
1261
33
      AsmString = "bg $\x01";
1262
33
      break;
1263
33
    }
1264
1.24k
    if (MCInst_getNumOperands(MI) == 2 &&
1265
1.24k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1266
1.24k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1267
      // (BCOND brtarget:$imm, 2)
1268
43
      AsmString = "ble $\x01";
1269
43
      break;
1270
43
    }
1271
1.20k
    if (MCInst_getNumOperands(MI) == 2 &&
1272
1.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1273
1.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1274
      // (BCOND brtarget:$imm, 11)
1275
88
      AsmString = "bge $\x01";
1276
88
      break;
1277
88
    }
1278
1.11k
    if (MCInst_getNumOperands(MI) == 2 &&
1279
1.11k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1280
1.11k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1281
      // (BCOND brtarget:$imm, 3)
1282
180
      AsmString = "bl $\x01";
1283
180
      break;
1284
180
    }
1285
938
    if (MCInst_getNumOperands(MI) == 2 &&
1286
938
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1287
938
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1288
      // (BCOND brtarget:$imm, 12)
1289
36
      AsmString = "bgu $\x01";
1290
36
      break;
1291
36
    }
1292
902
    if (MCInst_getNumOperands(MI) == 2 &&
1293
902
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1294
902
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1295
      // (BCOND brtarget:$imm, 4)
1296
98
      AsmString = "bleu $\x01";
1297
98
      break;
1298
98
    }
1299
804
    if (MCInst_getNumOperands(MI) == 2 &&
1300
804
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1301
804
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1302
      // (BCOND brtarget:$imm, 13)
1303
20
      AsmString = "bcc $\x01";
1304
20
      break;
1305
20
    }
1306
784
    if (MCInst_getNumOperands(MI) == 2 &&
1307
784
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1308
784
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1309
      // (BCOND brtarget:$imm, 5)
1310
176
      AsmString = "bcs $\x01";
1311
176
      break;
1312
176
    }
1313
608
    if (MCInst_getNumOperands(MI) == 2 &&
1314
608
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1315
608
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1316
      // (BCOND brtarget:$imm, 14)
1317
118
      AsmString = "bpos $\x01";
1318
118
      break;
1319
118
    }
1320
490
    if (MCInst_getNumOperands(MI) == 2 &&
1321
490
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1322
490
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1323
      // (BCOND brtarget:$imm, 6)
1324
169
      AsmString = "bneg $\x01";
1325
169
      break;
1326
169
    }
1327
321
    if (MCInst_getNumOperands(MI) == 2 &&
1328
321
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1329
321
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1330
      // (BCOND brtarget:$imm, 15)
1331
83
      AsmString = "bvc $\x01";
1332
83
      break;
1333
83
    }
1334
238
    if (MCInst_getNumOperands(MI) == 2 &&
1335
238
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1336
238
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1337
      // (BCOND brtarget:$imm, 7)
1338
238
      AsmString = "bvs $\x01";
1339
238
      break;
1340
238
    }
1341
0
    return NULL;
1342
1.80k
  case SP_BCONDA:
1343
1.80k
    if (MCInst_getNumOperands(MI) == 2 &&
1344
1.80k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1345
1.80k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1346
      // (BCONDA brtarget:$imm, 8)
1347
76
      AsmString = "ba,a $\x01";
1348
76
      break;
1349
76
    }
1350
1.73k
    if (MCInst_getNumOperands(MI) == 2 &&
1351
1.73k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1352
1.73k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1353
      // (BCONDA brtarget:$imm, 0)
1354
115
      AsmString = "bn,a $\x01";
1355
115
      break;
1356
115
    }
1357
1.61k
    if (MCInst_getNumOperands(MI) == 2 &&
1358
1.61k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1359
1.61k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1360
      // (BCONDA brtarget:$imm, 9)
1361
57
      AsmString = "bne,a $\x01";
1362
57
      break;
1363
57
    }
1364
1.55k
    if (MCInst_getNumOperands(MI) == 2 &&
1365
1.55k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1366
1.55k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1367
      // (BCONDA brtarget:$imm, 1)
1368
19
      AsmString = "be,a $\x01";
1369
19
      break;
1370
19
    }
1371
1.53k
    if (MCInst_getNumOperands(MI) == 2 &&
1372
1.53k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1373
1.53k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1374
      // (BCONDA brtarget:$imm, 10)
1375
53
      AsmString = "bg,a $\x01";
1376
53
      break;
1377
53
    }
1378
1.48k
    if (MCInst_getNumOperands(MI) == 2 &&
1379
1.48k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1380
1.48k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1381
      // (BCONDA brtarget:$imm, 2)
1382
170
      AsmString = "ble,a $\x01";
1383
170
      break;
1384
170
    }
1385
1.31k
    if (MCInst_getNumOperands(MI) == 2 &&
1386
1.31k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1387
1.31k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1388
      // (BCONDA brtarget:$imm, 11)
1389
35
      AsmString = "bge,a $\x01";
1390
35
      break;
1391
35
    }
1392
1.28k
    if (MCInst_getNumOperands(MI) == 2 &&
1393
1.28k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1394
1.28k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1395
      // (BCONDA brtarget:$imm, 3)
1396
19
      AsmString = "bl,a $\x01";
1397
19
      break;
1398
19
    }
1399
1.26k
    if (MCInst_getNumOperands(MI) == 2 &&
1400
1.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1401
1.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1402
      // (BCONDA brtarget:$imm, 12)
1403
135
      AsmString = "bgu,a $\x01";
1404
135
      break;
1405
135
    }
1406
1.12k
    if (MCInst_getNumOperands(MI) == 2 &&
1407
1.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1408
1.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1409
      // (BCONDA brtarget:$imm, 4)
1410
144
      AsmString = "bleu,a $\x01";
1411
144
      break;
1412
144
    }
1413
983
    if (MCInst_getNumOperands(MI) == 2 &&
1414
983
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1415
983
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1416
      // (BCONDA brtarget:$imm, 13)
1417
59
      AsmString = "bcc,a $\x01";
1418
59
      break;
1419
59
    }
1420
924
    if (MCInst_getNumOperands(MI) == 2 &&
1421
924
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1422
924
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1423
      // (BCONDA brtarget:$imm, 5)
1424
64
      AsmString = "bcs,a $\x01";
1425
64
      break;
1426
64
    }
1427
860
    if (MCInst_getNumOperands(MI) == 2 &&
1428
860
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1429
860
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1430
      // (BCONDA brtarget:$imm, 14)
1431
591
      AsmString = "bpos,a $\x01";
1432
591
      break;
1433
591
    }
1434
269
    if (MCInst_getNumOperands(MI) == 2 &&
1435
269
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1436
269
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1437
      // (BCONDA brtarget:$imm, 6)
1438
124
      AsmString = "bneg,a $\x01";
1439
124
      break;
1440
124
    }
1441
145
    if (MCInst_getNumOperands(MI) == 2 &&
1442
145
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1443
145
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1444
      // (BCONDA brtarget:$imm, 15)
1445
71
      AsmString = "bvc,a $\x01";
1446
71
      break;
1447
71
    }
1448
74
    if (MCInst_getNumOperands(MI) == 2 &&
1449
74
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1450
74
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1451
      // (BCONDA brtarget:$imm, 7)
1452
74
      AsmString = "bvs,a $\x01";
1453
74
      break;
1454
74
    }
1455
0
    return NULL;
1456
2.05k
  case SP_BPFCCANT:
1457
2.05k
    if (MCInst_getNumOperands(MI) == 3 &&
1458
2.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1459
2.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1460
2.05k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1461
2.05k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1462
      // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1463
45
      AsmString = "fba,a,pn $\x03, $\x01";
1464
45
      break;
1465
45
    }
1466
2.00k
    if (MCInst_getNumOperands(MI) == 3 &&
1467
2.00k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1468
2.00k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1469
2.00k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1470
2.00k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1471
      // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1472
104
      AsmString = "fbn,a,pn $\x03, $\x01";
1473
104
      break;
1474
104
    }
1475
1.90k
    if (MCInst_getNumOperands(MI) == 3 &&
1476
1.90k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1477
1.90k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1478
1.90k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1479
1.90k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1480
      // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1481
296
      AsmString = "fbu,a,pn $\x03, $\x01";
1482
296
      break;
1483
296
    }
1484
1.60k
    if (MCInst_getNumOperands(MI) == 3 &&
1485
1.60k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1486
1.60k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1487
1.60k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1488
1.60k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1489
      // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1490
142
      AsmString = "fbg,a,pn $\x03, $\x01";
1491
142
      break;
1492
142
    }
1493
1.46k
    if (MCInst_getNumOperands(MI) == 3 &&
1494
1.46k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1495
1.46k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1496
1.46k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1497
1.46k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1498
      // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1499
144
      AsmString = "fbug,a,pn $\x03, $\x01";
1500
144
      break;
1501
144
    }
1502
1.32k
    if (MCInst_getNumOperands(MI) == 3 &&
1503
1.32k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1504
1.32k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1505
1.32k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1506
1.32k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1507
      // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1508
203
      AsmString = "fbl,a,pn $\x03, $\x01";
1509
203
      break;
1510
203
    }
1511
1.11k
    if (MCInst_getNumOperands(MI) == 3 &&
1512
1.11k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1513
1.11k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1514
1.11k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1515
1.11k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1516
      // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1517
209
      AsmString = "fbul,a,pn $\x03, $\x01";
1518
209
      break;
1519
209
    }
1520
908
    if (MCInst_getNumOperands(MI) == 3 &&
1521
908
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1522
908
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1523
908
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1524
908
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1525
      // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1526
152
      AsmString = "fblg,a,pn $\x03, $\x01";
1527
152
      break;
1528
152
    }
1529
756
    if (MCInst_getNumOperands(MI) == 3 &&
1530
756
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1531
756
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1532
756
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1533
756
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1534
      // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1535
61
      AsmString = "fbne,a,pn $\x03, $\x01";
1536
61
      break;
1537
61
    }
1538
695
    if (MCInst_getNumOperands(MI) == 3 &&
1539
695
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1540
695
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1541
695
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1542
695
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1543
      // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1544
206
      AsmString = "fbe,a,pn $\x03, $\x01";
1545
206
      break;
1546
206
    }
1547
489
    if (MCInst_getNumOperands(MI) == 3 &&
1548
489
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1549
489
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1550
489
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1551
489
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1552
      // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1553
36
      AsmString = "fbue,a,pn $\x03, $\x01";
1554
36
      break;
1555
36
    }
1556
453
    if (MCInst_getNumOperands(MI) == 3 &&
1557
453
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1558
453
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1559
453
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1560
453
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1561
      // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1562
42
      AsmString = "fbge,a,pn $\x03, $\x01";
1563
42
      break;
1564
42
    }
1565
411
    if (MCInst_getNumOperands(MI) == 3 &&
1566
411
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1567
411
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1568
411
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1569
411
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1570
      // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1571
75
      AsmString = "fbuge,a,pn $\x03, $\x01";
1572
75
      break;
1573
75
    }
1574
336
    if (MCInst_getNumOperands(MI) == 3 &&
1575
336
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1576
336
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1577
336
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1578
336
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1579
      // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1580
59
      AsmString = "fble,a,pn $\x03, $\x01";
1581
59
      break;
1582
59
    }
1583
277
    if (MCInst_getNumOperands(MI) == 3 &&
1584
277
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1585
277
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1586
277
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1587
277
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1588
      // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1589
161
      AsmString = "fbule,a,pn $\x03, $\x01";
1590
161
      break;
1591
161
    }
1592
116
    if (MCInst_getNumOperands(MI) == 3 &&
1593
116
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1594
116
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1595
116
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1596
116
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1597
      // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1598
116
      AsmString = "fbo,a,pn $\x03, $\x01";
1599
116
      break;
1600
116
    }
1601
0
    return NULL;
1602
1.99k
  case SP_BPFCCNT:
1603
1.99k
    if (MCInst_getNumOperands(MI) == 3 &&
1604
1.99k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1605
1.99k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1606
1.99k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1607
1.99k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1608
      // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1609
169
      AsmString = "fba,pn $\x03, $\x01";
1610
169
      break;
1611
169
    }
1612
1.82k
    if (MCInst_getNumOperands(MI) == 3 &&
1613
1.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1614
1.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1615
1.82k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1616
1.82k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1617
      // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1618
203
      AsmString = "fbn,pn $\x03, $\x01";
1619
203
      break;
1620
203
    }
1621
1.62k
    if (MCInst_getNumOperands(MI) == 3 &&
1622
1.62k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
1.62k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1624
1.62k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1625
1.62k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1626
      // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1627
256
      AsmString = "fbu,pn $\x03, $\x01";
1628
256
      break;
1629
256
    }
1630
1.36k
    if (MCInst_getNumOperands(MI) == 3 &&
1631
1.36k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1632
1.36k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1633
1.36k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1634
1.36k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1635
      // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1636
91
      AsmString = "fbg,pn $\x03, $\x01";
1637
91
      break;
1638
91
    }
1639
1.27k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
1.27k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1641
1.27k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1642
1.27k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1643
1.27k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1644
      // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1645
84
      AsmString = "fbug,pn $\x03, $\x01";
1646
84
      break;
1647
84
    }
1648
1.19k
    if (MCInst_getNumOperands(MI) == 3 &&
1649
1.19k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1650
1.19k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1651
1.19k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1652
1.19k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1653
      // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1654
56
      AsmString = "fbl,pn $\x03, $\x01";
1655
56
      break;
1656
56
    }
1657
1.13k
    if (MCInst_getNumOperands(MI) == 3 &&
1658
1.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1659
1.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1660
1.13k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1661
1.13k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1662
      // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1663
156
      AsmString = "fbul,pn $\x03, $\x01";
1664
156
      break;
1665
156
    }
1666
981
    if (MCInst_getNumOperands(MI) == 3 &&
1667
981
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1668
981
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1669
981
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1670
981
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1671
      // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1672
191
      AsmString = "fblg,pn $\x03, $\x01";
1673
191
      break;
1674
191
    }
1675
790
    if (MCInst_getNumOperands(MI) == 3 &&
1676
790
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1677
790
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1678
790
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1679
790
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1680
      // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1681
128
      AsmString = "fbne,pn $\x03, $\x01";
1682
128
      break;
1683
128
    }
1684
662
    if (MCInst_getNumOperands(MI) == 3 &&
1685
662
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1686
662
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1687
662
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1688
662
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1689
      // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1690
154
      AsmString = "fbe,pn $\x03, $\x01";
1691
154
      break;
1692
154
    }
1693
508
    if (MCInst_getNumOperands(MI) == 3 &&
1694
508
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1695
508
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1696
508
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1697
508
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1698
      // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1699
85
      AsmString = "fbue,pn $\x03, $\x01";
1700
85
      break;
1701
85
    }
1702
423
    if (MCInst_getNumOperands(MI) == 3 &&
1703
423
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1704
423
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1705
423
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1706
423
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1707
      // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1708
35
      AsmString = "fbge,pn $\x03, $\x01";
1709
35
      break;
1710
35
    }
1711
388
    if (MCInst_getNumOperands(MI) == 3 &&
1712
388
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1713
388
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1714
388
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1715
388
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1716
      // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1717
199
      AsmString = "fbuge,pn $\x03, $\x01";
1718
199
      break;
1719
199
    }
1720
189
    if (MCInst_getNumOperands(MI) == 3 &&
1721
189
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1722
189
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1723
189
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1724
189
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1725
      // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1726
55
      AsmString = "fble,pn $\x03, $\x01";
1727
55
      break;
1728
55
    }
1729
134
    if (MCInst_getNumOperands(MI) == 3 &&
1730
134
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1731
134
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1732
134
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1733
134
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1734
      // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1735
36
      AsmString = "fbule,pn $\x03, $\x01";
1736
36
      break;
1737
36
    }
1738
98
    if (MCInst_getNumOperands(MI) == 3 &&
1739
98
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1740
98
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1741
98
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1742
98
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1743
      // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1744
98
      AsmString = "fbo,pn $\x03, $\x01";
1745
98
      break;
1746
98
    }
1747
0
    return NULL;
1748
1.69k
  case SP_BPICCANT:
1749
1.69k
    if (MCInst_getNumOperands(MI) == 2 &&
1750
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1751
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1752
      // (BPICCANT brtarget:$imm, 8)
1753
35
      AsmString = "ba,a,pn %icc, $\x01";
1754
35
      break;
1755
35
    }
1756
1.65k
    if (MCInst_getNumOperands(MI) == 2 &&
1757
1.65k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
1.65k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1759
      // (BPICCANT brtarget:$imm, 0)
1760
213
      AsmString = "bn,a,pn %icc, $\x01";
1761
213
      break;
1762
213
    }
1763
1.44k
    if (MCInst_getNumOperands(MI) == 2 &&
1764
1.44k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1765
1.44k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1766
      // (BPICCANT brtarget:$imm, 9)
1767
69
      AsmString = "bne,a,pn %icc, $\x01";
1768
69
      break;
1769
69
    }
1770
1.37k
    if (MCInst_getNumOperands(MI) == 2 &&
1771
1.37k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1772
1.37k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1773
      // (BPICCANT brtarget:$imm, 1)
1774
141
      AsmString = "be,a,pn %icc, $\x01";
1775
141
      break;
1776
141
    }
1777
1.23k
    if (MCInst_getNumOperands(MI) == 2 &&
1778
1.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1779
1.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1780
      // (BPICCANT brtarget:$imm, 10)
1781
88
      AsmString = "bg,a,pn %icc, $\x01";
1782
88
      break;
1783
88
    }
1784
1.14k
    if (MCInst_getNumOperands(MI) == 2 &&
1785
1.14k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1786
1.14k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1787
      // (BPICCANT brtarget:$imm, 2)
1788
18
      AsmString = "ble,a,pn %icc, $\x01";
1789
18
      break;
1790
18
    }
1791
1.12k
    if (MCInst_getNumOperands(MI) == 2 &&
1792
1.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1793
1.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1794
      // (BPICCANT brtarget:$imm, 11)
1795
96
      AsmString = "bge,a,pn %icc, $\x01";
1796
96
      break;
1797
96
    }
1798
1.03k
    if (MCInst_getNumOperands(MI) == 2 &&
1799
1.03k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1800
1.03k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1801
      // (BPICCANT brtarget:$imm, 3)
1802
59
      AsmString = "bl,a,pn %icc, $\x01";
1803
59
      break;
1804
59
    }
1805
971
    if (MCInst_getNumOperands(MI) == 2 &&
1806
971
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1807
971
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1808
      // (BPICCANT brtarget:$imm, 12)
1809
62
      AsmString = "bgu,a,pn %icc, $\x01";
1810
62
      break;
1811
62
    }
1812
909
    if (MCInst_getNumOperands(MI) == 2 &&
1813
909
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1814
909
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1815
      // (BPICCANT brtarget:$imm, 4)
1816
166
      AsmString = "bleu,a,pn %icc, $\x01";
1817
166
      break;
1818
166
    }
1819
743
    if (MCInst_getNumOperands(MI) == 2 &&
1820
743
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1821
743
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1822
      // (BPICCANT brtarget:$imm, 13)
1823
265
      AsmString = "bcc,a,pn %icc, $\x01";
1824
265
      break;
1825
265
    }
1826
478
    if (MCInst_getNumOperands(MI) == 2 &&
1827
478
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1828
478
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1829
      // (BPICCANT brtarget:$imm, 5)
1830
90
      AsmString = "bcs,a,pn %icc, $\x01";
1831
90
      break;
1832
90
    }
1833
388
    if (MCInst_getNumOperands(MI) == 2 &&
1834
388
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1835
388
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1836
      // (BPICCANT brtarget:$imm, 14)
1837
173
      AsmString = "bpos,a,pn %icc, $\x01";
1838
173
      break;
1839
173
    }
1840
215
    if (MCInst_getNumOperands(MI) == 2 &&
1841
215
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1842
215
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1843
      // (BPICCANT brtarget:$imm, 6)
1844
59
      AsmString = "bneg,a,pn %icc, $\x01";
1845
59
      break;
1846
59
    }
1847
156
    if (MCInst_getNumOperands(MI) == 2 &&
1848
156
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1849
156
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1850
      // (BPICCANT brtarget:$imm, 15)
1851
53
      AsmString = "bvc,a,pn %icc, $\x01";
1852
53
      break;
1853
53
    }
1854
103
    if (MCInst_getNumOperands(MI) == 2 &&
1855
103
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1856
103
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1857
      // (BPICCANT brtarget:$imm, 7)
1858
103
      AsmString = "bvs,a,pn %icc, $\x01";
1859
103
      break;
1860
103
    }
1861
0
    return NULL;
1862
2.67k
  case SP_BPICCNT:
1863
2.67k
    if (MCInst_getNumOperands(MI) == 2 &&
1864
2.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1865
2.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1866
      // (BPICCNT brtarget:$imm, 8)
1867
82
      AsmString = "ba,pn %icc, $\x01";
1868
82
      break;
1869
82
    }
1870
2.59k
    if (MCInst_getNumOperands(MI) == 2 &&
1871
2.59k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1872
2.59k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1873
      // (BPICCNT brtarget:$imm, 0)
1874
357
      AsmString = "bn,pn %icc, $\x01";
1875
357
      break;
1876
357
    }
1877
2.23k
    if (MCInst_getNumOperands(MI) == 2 &&
1878
2.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1879
2.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1880
      // (BPICCNT brtarget:$imm, 9)
1881
174
      AsmString = "bne,pn %icc, $\x01";
1882
174
      break;
1883
174
    }
1884
2.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1885
2.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1886
2.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1887
      // (BPICCNT brtarget:$imm, 1)
1888
758
      AsmString = "be,pn %icc, $\x01";
1889
758
      break;
1890
758
    }
1891
1.30k
    if (MCInst_getNumOperands(MI) == 2 &&
1892
1.30k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1893
1.30k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1894
      // (BPICCNT brtarget:$imm, 10)
1895
40
      AsmString = "bg,pn %icc, $\x01";
1896
40
      break;
1897
40
    }
1898
1.26k
    if (MCInst_getNumOperands(MI) == 2 &&
1899
1.26k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1900
1.26k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1901
      // (BPICCNT brtarget:$imm, 2)
1902
64
      AsmString = "ble,pn %icc, $\x01";
1903
64
      break;
1904
64
    }
1905
1.20k
    if (MCInst_getNumOperands(MI) == 2 &&
1906
1.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1907
1.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1908
      // (BPICCNT brtarget:$imm, 11)
1909
39
      AsmString = "bge,pn %icc, $\x01";
1910
39
      break;
1911
39
    }
1912
1.16k
    if (MCInst_getNumOperands(MI) == 2 &&
1913
1.16k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1914
1.16k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1915
      // (BPICCNT brtarget:$imm, 3)
1916
47
      AsmString = "bl,pn %icc, $\x01";
1917
47
      break;
1918
47
    }
1919
1.11k
    if (MCInst_getNumOperands(MI) == 2 &&
1920
1.11k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1921
1.11k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1922
      // (BPICCNT brtarget:$imm, 12)
1923
58
      AsmString = "bgu,pn %icc, $\x01";
1924
58
      break;
1925
58
    }
1926
1.05k
    if (MCInst_getNumOperands(MI) == 2 &&
1927
1.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1928
1.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1929
      // (BPICCNT brtarget:$imm, 4)
1930
187
      AsmString = "bleu,pn %icc, $\x01";
1931
187
      break;
1932
187
    }
1933
869
    if (MCInst_getNumOperands(MI) == 2 &&
1934
869
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1935
869
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1936
      // (BPICCNT brtarget:$imm, 13)
1937
24
      AsmString = "bcc,pn %icc, $\x01";
1938
24
      break;
1939
24
    }
1940
845
    if (MCInst_getNumOperands(MI) == 2 &&
1941
845
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1942
845
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1943
      // (BPICCNT brtarget:$imm, 5)
1944
178
      AsmString = "bcs,pn %icc, $\x01";
1945
178
      break;
1946
178
    }
1947
667
    if (MCInst_getNumOperands(MI) == 2 &&
1948
667
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1949
667
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1950
      // (BPICCNT brtarget:$imm, 14)
1951
19
      AsmString = "bpos,pn %icc, $\x01";
1952
19
      break;
1953
19
    }
1954
648
    if (MCInst_getNumOperands(MI) == 2 &&
1955
648
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1956
648
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1957
      // (BPICCNT brtarget:$imm, 6)
1958
159
      AsmString = "bneg,pn %icc, $\x01";
1959
159
      break;
1960
159
    }
1961
489
    if (MCInst_getNumOperands(MI) == 2 &&
1962
489
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1963
489
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1964
      // (BPICCNT brtarget:$imm, 15)
1965
174
      AsmString = "bvc,pn %icc, $\x01";
1966
174
      break;
1967
174
    }
1968
315
    if (MCInst_getNumOperands(MI) == 2 &&
1969
315
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1970
315
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1971
      // (BPICCNT brtarget:$imm, 7)
1972
315
      AsmString = "bvs,pn %icc, $\x01";
1973
315
      break;
1974
315
    }
1975
0
    return NULL;
1976
933
  case SP_BPXCCANT:
1977
933
    if (MCInst_getNumOperands(MI) == 2 &&
1978
933
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1979
933
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1980
      // (BPXCCANT brtarget:$imm, 8)
1981
23
      AsmString = "ba,a,pn %xcc, $\x01";
1982
23
      break;
1983
23
    }
1984
910
    if (MCInst_getNumOperands(MI) == 2 &&
1985
910
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1986
910
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1987
      // (BPXCCANT brtarget:$imm, 0)
1988
62
      AsmString = "bn,a,pn %xcc, $\x01";
1989
62
      break;
1990
62
    }
1991
848
    if (MCInst_getNumOperands(MI) == 2 &&
1992
848
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1993
848
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1994
      // (BPXCCANT brtarget:$imm, 9)
1995
44
      AsmString = "bne,a,pn %xcc, $\x01";
1996
44
      break;
1997
44
    }
1998
804
    if (MCInst_getNumOperands(MI) == 2 &&
1999
804
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2000
804
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2001
      // (BPXCCANT brtarget:$imm, 1)
2002
36
      AsmString = "be,a,pn %xcc, $\x01";
2003
36
      break;
2004
36
    }
2005
768
    if (MCInst_getNumOperands(MI) == 2 &&
2006
768
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2007
768
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2008
      // (BPXCCANT brtarget:$imm, 10)
2009
62
      AsmString = "bg,a,pn %xcc, $\x01";
2010
62
      break;
2011
62
    }
2012
706
    if (MCInst_getNumOperands(MI) == 2 &&
2013
706
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2014
706
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2015
      // (BPXCCANT brtarget:$imm, 2)
2016
53
      AsmString = "ble,a,pn %xcc, $\x01";
2017
53
      break;
2018
53
    }
2019
653
    if (MCInst_getNumOperands(MI) == 2 &&
2020
653
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2021
653
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2022
      // (BPXCCANT brtarget:$imm, 11)
2023
46
      AsmString = "bge,a,pn %xcc, $\x01";
2024
46
      break;
2025
46
    }
2026
607
    if (MCInst_getNumOperands(MI) == 2 &&
2027
607
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2028
607
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2029
      // (BPXCCANT brtarget:$imm, 3)
2030
68
      AsmString = "bl,a,pn %xcc, $\x01";
2031
68
      break;
2032
68
    }
2033
539
    if (MCInst_getNumOperands(MI) == 2 &&
2034
539
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2035
539
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2036
      // (BPXCCANT brtarget:$imm, 12)
2037
56
      AsmString = "bgu,a,pn %xcc, $\x01";
2038
56
      break;
2039
56
    }
2040
483
    if (MCInst_getNumOperands(MI) == 2 &&
2041
483
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2042
483
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2043
      // (BPXCCANT brtarget:$imm, 4)
2044
163
      AsmString = "bleu,a,pn %xcc, $\x01";
2045
163
      break;
2046
163
    }
2047
320
    if (MCInst_getNumOperands(MI) == 2 &&
2048
320
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2049
320
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2050
      // (BPXCCANT brtarget:$imm, 13)
2051
32
      AsmString = "bcc,a,pn %xcc, $\x01";
2052
32
      break;
2053
32
    }
2054
288
    if (MCInst_getNumOperands(MI) == 2 &&
2055
288
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2056
288
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2057
      // (BPXCCANT brtarget:$imm, 5)
2058
22
      AsmString = "bcs,a,pn %xcc, $\x01";
2059
22
      break;
2060
22
    }
2061
266
    if (MCInst_getNumOperands(MI) == 2 &&
2062
266
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2063
266
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2064
      // (BPXCCANT brtarget:$imm, 14)
2065
62
      AsmString = "bpos,a,pn %xcc, $\x01";
2066
62
      break;
2067
62
    }
2068
204
    if (MCInst_getNumOperands(MI) == 2 &&
2069
204
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2070
204
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2071
      // (BPXCCANT brtarget:$imm, 6)
2072
49
      AsmString = "bneg,a,pn %xcc, $\x01";
2073
49
      break;
2074
49
    }
2075
155
    if (MCInst_getNumOperands(MI) == 2 &&
2076
155
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2077
155
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2078
      // (BPXCCANT brtarget:$imm, 15)
2079
91
      AsmString = "bvc,a,pn %xcc, $\x01";
2080
91
      break;
2081
91
    }
2082
64
    if (MCInst_getNumOperands(MI) == 2 &&
2083
64
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2084
64
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2085
      // (BPXCCANT brtarget:$imm, 7)
2086
64
      AsmString = "bvs,a,pn %xcc, $\x01";
2087
64
      break;
2088
64
    }
2089
0
    return NULL;
2090
1.24k
  case SP_BPXCCNT:
2091
1.24k
    if (MCInst_getNumOperands(MI) == 2 &&
2092
1.24k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2093
1.24k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2094
      // (BPXCCNT brtarget:$imm, 8)
2095
51
      AsmString = "ba,pn %xcc, $\x01";
2096
51
      break;
2097
51
    }
2098
1.19k
    if (MCInst_getNumOperands(MI) == 2 &&
2099
1.19k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2100
1.19k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2101
      // (BPXCCNT brtarget:$imm, 0)
2102
229
      AsmString = "bn,pn %xcc, $\x01";
2103
229
      break;
2104
229
    }
2105
964
    if (MCInst_getNumOperands(MI) == 2 &&
2106
964
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2107
964
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2108
      // (BPXCCNT brtarget:$imm, 9)
2109
20
      AsmString = "bne,pn %xcc, $\x01";
2110
20
      break;
2111
20
    }
2112
944
    if (MCInst_getNumOperands(MI) == 2 &&
2113
944
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2114
944
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2115
      // (BPXCCNT brtarget:$imm, 1)
2116
78
      AsmString = "be,pn %xcc, $\x01";
2117
78
      break;
2118
78
    }
2119
866
    if (MCInst_getNumOperands(MI) == 2 &&
2120
866
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2121
866
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2122
      // (BPXCCNT brtarget:$imm, 10)
2123
191
      AsmString = "bg,pn %xcc, $\x01";
2124
191
      break;
2125
191
    }
2126
675
    if (MCInst_getNumOperands(MI) == 2 &&
2127
675
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2128
675
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2129
      // (BPXCCNT brtarget:$imm, 2)
2130
44
      AsmString = "ble,pn %xcc, $\x01";
2131
44
      break;
2132
44
    }
2133
631
    if (MCInst_getNumOperands(MI) == 2 &&
2134
631
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2135
631
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2136
      // (BPXCCNT brtarget:$imm, 11)
2137
23
      AsmString = "bge,pn %xcc, $\x01";
2138
23
      break;
2139
23
    }
2140
608
    if (MCInst_getNumOperands(MI) == 2 &&
2141
608
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2142
608
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2143
      // (BPXCCNT brtarget:$imm, 3)
2144
64
      AsmString = "bl,pn %xcc, $\x01";
2145
64
      break;
2146
64
    }
2147
544
    if (MCInst_getNumOperands(MI) == 2 &&
2148
544
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2149
544
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2150
      // (BPXCCNT brtarget:$imm, 12)
2151
59
      AsmString = "bgu,pn %xcc, $\x01";
2152
59
      break;
2153
59
    }
2154
485
    if (MCInst_getNumOperands(MI) == 2 &&
2155
485
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2156
485
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2157
      // (BPXCCNT brtarget:$imm, 4)
2158
69
      AsmString = "bleu,pn %xcc, $\x01";
2159
69
      break;
2160
69
    }
2161
416
    if (MCInst_getNumOperands(MI) == 2 &&
2162
416
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2163
416
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2164
      // (BPXCCNT brtarget:$imm, 13)
2165
201
      AsmString = "bcc,pn %xcc, $\x01";
2166
201
      break;
2167
201
    }
2168
215
    if (MCInst_getNumOperands(MI) == 2 &&
2169
215
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2170
215
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2171
      // (BPXCCNT brtarget:$imm, 5)
2172
63
      AsmString = "bcs,pn %xcc, $\x01";
2173
63
      break;
2174
63
    }
2175
152
    if (MCInst_getNumOperands(MI) == 2 &&
2176
152
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2177
152
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2178
      // (BPXCCNT brtarget:$imm, 14)
2179
35
      AsmString = "bpos,pn %xcc, $\x01";
2180
35
      break;
2181
35
    }
2182
117
    if (MCInst_getNumOperands(MI) == 2 &&
2183
117
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2184
117
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2185
      // (BPXCCNT brtarget:$imm, 6)
2186
35
      AsmString = "bneg,pn %xcc, $\x01";
2187
35
      break;
2188
35
    }
2189
82
    if (MCInst_getNumOperands(MI) == 2 &&
2190
82
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2191
82
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2192
      // (BPXCCNT brtarget:$imm, 15)
2193
34
      AsmString = "bvc,pn %xcc, $\x01";
2194
34
      break;
2195
34
    }
2196
48
    if (MCInst_getNumOperands(MI) == 2 &&
2197
48
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2198
48
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2199
      // (BPXCCNT brtarget:$imm, 7)
2200
48
      AsmString = "bvs,pn %xcc, $\x01";
2201
48
      break;
2202
48
    }
2203
0
    return NULL;
2204
88
  case SP_FMOVD_ICC:
2205
88
    if (MCInst_getNumOperands(MI) == 3 &&
2206
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2207
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2208
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2209
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2210
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2211
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2212
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2213
0
      AsmString = "fmovda %icc, $\x02, $\x01";
2214
0
      break;
2215
0
    }
2216
88
    if (MCInst_getNumOperands(MI) == 3 &&
2217
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2218
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2219
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2220
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2221
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2222
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2223
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2224
0
      AsmString = "fmovdn %icc, $\x02, $\x01";
2225
0
      break;
2226
0
    }
2227
88
    if (MCInst_getNumOperands(MI) == 3 &&
2228
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2229
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2230
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2231
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2232
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2233
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2234
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2235
0
      AsmString = "fmovdne %icc, $\x02, $\x01";
2236
0
      break;
2237
0
    }
2238
88
    if (MCInst_getNumOperands(MI) == 3 &&
2239
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2240
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2241
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2242
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2243
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2244
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2245
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2246
0
      AsmString = "fmovde %icc, $\x02, $\x01";
2247
0
      break;
2248
0
    }
2249
88
    if (MCInst_getNumOperands(MI) == 3 &&
2250
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2251
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2252
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2253
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2254
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2255
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2256
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2257
0
      AsmString = "fmovdg %icc, $\x02, $\x01";
2258
0
      break;
2259
0
    }
2260
88
    if (MCInst_getNumOperands(MI) == 3 &&
2261
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2262
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2263
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2264
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2265
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2266
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2267
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2268
0
      AsmString = "fmovdle %icc, $\x02, $\x01";
2269
0
      break;
2270
0
    }
2271
88
    if (MCInst_getNumOperands(MI) == 3 &&
2272
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2273
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2274
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2275
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2276
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2277
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2278
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2279
0
      AsmString = "fmovdge %icc, $\x02, $\x01";
2280
0
      break;
2281
0
    }
2282
88
    if (MCInst_getNumOperands(MI) == 3 &&
2283
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2285
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2287
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2288
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2289
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2290
0
      AsmString = "fmovdl %icc, $\x02, $\x01";
2291
0
      break;
2292
0
    }
2293
88
    if (MCInst_getNumOperands(MI) == 3 &&
2294
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2295
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2296
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2297
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2298
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2299
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2300
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2301
0
      AsmString = "fmovdgu %icc, $\x02, $\x01";
2302
0
      break;
2303
0
    }
2304
88
    if (MCInst_getNumOperands(MI) == 3 &&
2305
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2306
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2307
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2308
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2309
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2310
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2311
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2312
0
      AsmString = "fmovdleu %icc, $\x02, $\x01";
2313
0
      break;
2314
0
    }
2315
88
    if (MCInst_getNumOperands(MI) == 3 &&
2316
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2317
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2318
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2319
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2320
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2321
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2322
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2323
0
      AsmString = "fmovdcc %icc, $\x02, $\x01";
2324
0
      break;
2325
0
    }
2326
88
    if (MCInst_getNumOperands(MI) == 3 &&
2327
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2328
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2329
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2330
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2331
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2332
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2333
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2334
0
      AsmString = "fmovdcs %icc, $\x02, $\x01";
2335
0
      break;
2336
0
    }
2337
88
    if (MCInst_getNumOperands(MI) == 3 &&
2338
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2339
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2340
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2341
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2342
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2343
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2344
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2345
0
      AsmString = "fmovdpos %icc, $\x02, $\x01";
2346
0
      break;
2347
0
    }
2348
88
    if (MCInst_getNumOperands(MI) == 3 &&
2349
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2350
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2351
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2352
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2353
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2354
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2355
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2356
0
      AsmString = "fmovdneg %icc, $\x02, $\x01";
2357
0
      break;
2358
0
    }
2359
88
    if (MCInst_getNumOperands(MI) == 3 &&
2360
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2361
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2362
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2363
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2364
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2365
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2366
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2367
0
      AsmString = "fmovdvc %icc, $\x02, $\x01";
2368
0
      break;
2369
0
    }
2370
88
    if (MCInst_getNumOperands(MI) == 3 &&
2371
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2372
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2373
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2374
88
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2375
88
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2376
88
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2377
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2378
0
      AsmString = "fmovdvs %icc, $\x02, $\x01";
2379
0
      break;
2380
0
    }
2381
88
    return NULL;
2382
36
  case SP_FMOVD_XCC:
2383
36
    if (MCInst_getNumOperands(MI) == 3 &&
2384
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2385
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2386
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2387
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2388
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2389
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2390
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2391
0
      AsmString = "fmovda %xcc, $\x02, $\x01";
2392
0
      break;
2393
0
    }
2394
36
    if (MCInst_getNumOperands(MI) == 3 &&
2395
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2396
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2397
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2398
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2399
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2400
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2401
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2402
0
      AsmString = "fmovdn %xcc, $\x02, $\x01";
2403
0
      break;
2404
0
    }
2405
36
    if (MCInst_getNumOperands(MI) == 3 &&
2406
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2407
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2408
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2409
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2410
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2411
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2412
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2413
0
      AsmString = "fmovdne %xcc, $\x02, $\x01";
2414
0
      break;
2415
0
    }
2416
36
    if (MCInst_getNumOperands(MI) == 3 &&
2417
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2418
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2419
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2420
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2421
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2422
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2423
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2424
0
      AsmString = "fmovde %xcc, $\x02, $\x01";
2425
0
      break;
2426
0
    }
2427
36
    if (MCInst_getNumOperands(MI) == 3 &&
2428
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2429
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2430
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2431
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2432
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2433
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2434
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2435
0
      AsmString = "fmovdg %xcc, $\x02, $\x01";
2436
0
      break;
2437
0
    }
2438
36
    if (MCInst_getNumOperands(MI) == 3 &&
2439
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2440
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2441
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2442
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2443
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2444
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2445
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2446
0
      AsmString = "fmovdle %xcc, $\x02, $\x01";
2447
0
      break;
2448
0
    }
2449
36
    if (MCInst_getNumOperands(MI) == 3 &&
2450
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2451
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2452
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2453
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2454
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2455
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2456
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2457
0
      AsmString = "fmovdge %xcc, $\x02, $\x01";
2458
0
      break;
2459
0
    }
2460
36
    if (MCInst_getNumOperands(MI) == 3 &&
2461
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2462
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2463
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2464
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2465
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2466
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2467
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2468
0
      AsmString = "fmovdl %xcc, $\x02, $\x01";
2469
0
      break;
2470
0
    }
2471
36
    if (MCInst_getNumOperands(MI) == 3 &&
2472
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2473
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2474
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2475
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2476
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2477
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2478
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2479
0
      AsmString = "fmovdgu %xcc, $\x02, $\x01";
2480
0
      break;
2481
0
    }
2482
36
    if (MCInst_getNumOperands(MI) == 3 &&
2483
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2484
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2485
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2486
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2487
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2488
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2489
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2490
0
      AsmString = "fmovdleu %xcc, $\x02, $\x01";
2491
0
      break;
2492
0
    }
2493
36
    if (MCInst_getNumOperands(MI) == 3 &&
2494
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2495
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2496
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2497
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2498
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2499
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2500
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2501
0
      AsmString = "fmovdcc %xcc, $\x02, $\x01";
2502
0
      break;
2503
0
    }
2504
36
    if (MCInst_getNumOperands(MI) == 3 &&
2505
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2506
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2507
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2508
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2509
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2510
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2511
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2512
0
      AsmString = "fmovdcs %xcc, $\x02, $\x01";
2513
0
      break;
2514
0
    }
2515
36
    if (MCInst_getNumOperands(MI) == 3 &&
2516
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2518
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2519
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2520
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2521
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2522
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2523
0
      AsmString = "fmovdpos %xcc, $\x02, $\x01";
2524
0
      break;
2525
0
    }
2526
36
    if (MCInst_getNumOperands(MI) == 3 &&
2527
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2528
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2529
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2530
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2531
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2532
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2533
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2534
0
      AsmString = "fmovdneg %xcc, $\x02, $\x01";
2535
0
      break;
2536
0
    }
2537
36
    if (MCInst_getNumOperands(MI) == 3 &&
2538
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2539
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2540
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2541
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2542
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2543
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2544
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2545
0
      AsmString = "fmovdvc %xcc, $\x02, $\x01";
2546
0
      break;
2547
0
    }
2548
36
    if (MCInst_getNumOperands(MI) == 3 &&
2549
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2550
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2551
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2552
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2553
36
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2554
36
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2555
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2556
0
      AsmString = "fmovdvs %xcc, $\x02, $\x01";
2557
0
      break;
2558
0
    }
2559
36
    return NULL;
2560
235
  case SP_FMOVQ_ICC:
2561
235
    if (MCInst_getNumOperands(MI) == 3 &&
2562
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2563
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2564
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2565
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2566
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2567
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2568
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2569
0
      AsmString = "fmovqa %icc, $\x02, $\x01";
2570
0
      break;
2571
0
    }
2572
235
    if (MCInst_getNumOperands(MI) == 3 &&
2573
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2574
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2575
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2576
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2577
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2578
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2579
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2580
0
      AsmString = "fmovqn %icc, $\x02, $\x01";
2581
0
      break;
2582
0
    }
2583
235
    if (MCInst_getNumOperands(MI) == 3 &&
2584
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2585
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2586
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2587
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2588
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2589
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2590
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2591
0
      AsmString = "fmovqne %icc, $\x02, $\x01";
2592
0
      break;
2593
0
    }
2594
235
    if (MCInst_getNumOperands(MI) == 3 &&
2595
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2596
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2597
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2598
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2599
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2600
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2601
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2602
0
      AsmString = "fmovqe %icc, $\x02, $\x01";
2603
0
      break;
2604
0
    }
2605
235
    if (MCInst_getNumOperands(MI) == 3 &&
2606
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2607
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2608
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2609
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2610
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2611
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2612
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2613
0
      AsmString = "fmovqg %icc, $\x02, $\x01";
2614
0
      break;
2615
0
    }
2616
235
    if (MCInst_getNumOperands(MI) == 3 &&
2617
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2618
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2619
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2620
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2621
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2622
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2623
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2624
0
      AsmString = "fmovqle %icc, $\x02, $\x01";
2625
0
      break;
2626
0
    }
2627
235
    if (MCInst_getNumOperands(MI) == 3 &&
2628
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2629
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2630
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2631
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2632
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2633
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2634
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2635
0
      AsmString = "fmovqge %icc, $\x02, $\x01";
2636
0
      break;
2637
0
    }
2638
235
    if (MCInst_getNumOperands(MI) == 3 &&
2639
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2640
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2641
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2642
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2643
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2644
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2645
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2646
0
      AsmString = "fmovql %icc, $\x02, $\x01";
2647
0
      break;
2648
0
    }
2649
235
    if (MCInst_getNumOperands(MI) == 3 &&
2650
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2651
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2652
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2653
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2654
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2655
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2656
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2657
0
      AsmString = "fmovqgu %icc, $\x02, $\x01";
2658
0
      break;
2659
0
    }
2660
235
    if (MCInst_getNumOperands(MI) == 3 &&
2661
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2662
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2663
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2664
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2665
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2666
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2667
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2668
0
      AsmString = "fmovqleu %icc, $\x02, $\x01";
2669
0
      break;
2670
0
    }
2671
235
    if (MCInst_getNumOperands(MI) == 3 &&
2672
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2673
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2674
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2675
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2676
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2677
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2678
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2679
0
      AsmString = "fmovqcc %icc, $\x02, $\x01";
2680
0
      break;
2681
0
    }
2682
235
    if (MCInst_getNumOperands(MI) == 3 &&
2683
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2684
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2685
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2686
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2687
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2688
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2689
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2690
0
      AsmString = "fmovqcs %icc, $\x02, $\x01";
2691
0
      break;
2692
0
    }
2693
235
    if (MCInst_getNumOperands(MI) == 3 &&
2694
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2695
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2696
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2697
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2698
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2699
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2700
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2701
0
      AsmString = "fmovqpos %icc, $\x02, $\x01";
2702
0
      break;
2703
0
    }
2704
235
    if (MCInst_getNumOperands(MI) == 3 &&
2705
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2706
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2707
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2708
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2709
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2710
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2711
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2712
0
      AsmString = "fmovqneg %icc, $\x02, $\x01";
2713
0
      break;
2714
0
    }
2715
235
    if (MCInst_getNumOperands(MI) == 3 &&
2716
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2717
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2718
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2719
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2720
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2721
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2722
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2723
0
      AsmString = "fmovqvc %icc, $\x02, $\x01";
2724
0
      break;
2725
0
    }
2726
235
    if (MCInst_getNumOperands(MI) == 3 &&
2727
235
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2728
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2729
235
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2730
235
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2731
235
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2732
235
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2733
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2734
0
      AsmString = "fmovqvs %icc, $\x02, $\x01";
2735
0
      break;
2736
0
    }
2737
235
    return NULL;
2738
17
  case SP_FMOVQ_XCC:
2739
17
    if (MCInst_getNumOperands(MI) == 3 &&
2740
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2741
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2742
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2743
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2744
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2745
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2746
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2747
0
      AsmString = "fmovqa %xcc, $\x02, $\x01";
2748
0
      break;
2749
0
    }
2750
17
    if (MCInst_getNumOperands(MI) == 3 &&
2751
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2752
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2753
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2754
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2755
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2756
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2757
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2758
0
      AsmString = "fmovqn %xcc, $\x02, $\x01";
2759
0
      break;
2760
0
    }
2761
17
    if (MCInst_getNumOperands(MI) == 3 &&
2762
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2763
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2764
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2765
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2766
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2767
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2768
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2769
0
      AsmString = "fmovqne %xcc, $\x02, $\x01";
2770
0
      break;
2771
0
    }
2772
17
    if (MCInst_getNumOperands(MI) == 3 &&
2773
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2774
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2775
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2776
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2777
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2778
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2779
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2780
0
      AsmString = "fmovqe %xcc, $\x02, $\x01";
2781
0
      break;
2782
0
    }
2783
17
    if (MCInst_getNumOperands(MI) == 3 &&
2784
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2785
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2786
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2787
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2788
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2789
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2790
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2791
0
      AsmString = "fmovqg %xcc, $\x02, $\x01";
2792
0
      break;
2793
0
    }
2794
17
    if (MCInst_getNumOperands(MI) == 3 &&
2795
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2796
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2797
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2798
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2799
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2800
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2801
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2802
0
      AsmString = "fmovqle %xcc, $\x02, $\x01";
2803
0
      break;
2804
0
    }
2805
17
    if (MCInst_getNumOperands(MI) == 3 &&
2806
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2807
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2808
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2809
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2810
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2811
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2812
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2813
0
      AsmString = "fmovqge %xcc, $\x02, $\x01";
2814
0
      break;
2815
0
    }
2816
17
    if (MCInst_getNumOperands(MI) == 3 &&
2817
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2818
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2819
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2820
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2821
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2822
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2823
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2824
0
      AsmString = "fmovql %xcc, $\x02, $\x01";
2825
0
      break;
2826
0
    }
2827
17
    if (MCInst_getNumOperands(MI) == 3 &&
2828
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2829
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2830
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2831
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2832
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2834
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2835
0
      AsmString = "fmovqgu %xcc, $\x02, $\x01";
2836
0
      break;
2837
0
    }
2838
17
    if (MCInst_getNumOperands(MI) == 3 &&
2839
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2840
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2841
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2842
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2843
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2844
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2845
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2846
0
      AsmString = "fmovqleu %xcc, $\x02, $\x01";
2847
0
      break;
2848
0
    }
2849
17
    if (MCInst_getNumOperands(MI) == 3 &&
2850
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2851
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2852
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2853
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2854
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2855
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2856
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2857
0
      AsmString = "fmovqcc %xcc, $\x02, $\x01";
2858
0
      break;
2859
0
    }
2860
17
    if (MCInst_getNumOperands(MI) == 3 &&
2861
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2862
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2863
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2864
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2865
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2866
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2867
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2868
0
      AsmString = "fmovqcs %xcc, $\x02, $\x01";
2869
0
      break;
2870
0
    }
2871
17
    if (MCInst_getNumOperands(MI) == 3 &&
2872
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2873
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2874
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2875
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2876
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2877
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2878
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2879
0
      AsmString = "fmovqpos %xcc, $\x02, $\x01";
2880
0
      break;
2881
0
    }
2882
17
    if (MCInst_getNumOperands(MI) == 3 &&
2883
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2884
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2885
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2886
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2887
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2888
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2889
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2890
0
      AsmString = "fmovqneg %xcc, $\x02, $\x01";
2891
0
      break;
2892
0
    }
2893
17
    if (MCInst_getNumOperands(MI) == 3 &&
2894
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2895
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2896
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2897
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2898
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2899
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2900
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2901
0
      AsmString = "fmovqvc %xcc, $\x02, $\x01";
2902
0
      break;
2903
0
    }
2904
17
    if (MCInst_getNumOperands(MI) == 3 &&
2905
17
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2906
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2907
17
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2908
17
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2909
17
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2910
17
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2911
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2912
0
      AsmString = "fmovqvs %xcc, $\x02, $\x01";
2913
0
      break;
2914
0
    }
2915
17
    return NULL;
2916
42
  case SP_FMOVS_ICC:
2917
42
    if (MCInst_getNumOperands(MI) == 3 &&
2918
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2919
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2920
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2921
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2922
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2923
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2924
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2925
0
      AsmString = "fmovsa %icc, $\x02, $\x01";
2926
0
      break;
2927
0
    }
2928
42
    if (MCInst_getNumOperands(MI) == 3 &&
2929
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2930
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2931
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2932
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2933
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2934
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2935
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2936
0
      AsmString = "fmovsn %icc, $\x02, $\x01";
2937
0
      break;
2938
0
    }
2939
42
    if (MCInst_getNumOperands(MI) == 3 &&
2940
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2941
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2942
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2943
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2944
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2945
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2946
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2947
0
      AsmString = "fmovsne %icc, $\x02, $\x01";
2948
0
      break;
2949
0
    }
2950
42
    if (MCInst_getNumOperands(MI) == 3 &&
2951
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2952
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2953
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2954
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2955
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2956
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2957
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2958
0
      AsmString = "fmovse %icc, $\x02, $\x01";
2959
0
      break;
2960
0
    }
2961
42
    if (MCInst_getNumOperands(MI) == 3 &&
2962
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2963
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2964
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2965
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2966
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2967
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2968
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2969
0
      AsmString = "fmovsg %icc, $\x02, $\x01";
2970
0
      break;
2971
0
    }
2972
42
    if (MCInst_getNumOperands(MI) == 3 &&
2973
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2974
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2975
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2976
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2977
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2978
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2979
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2980
0
      AsmString = "fmovsle %icc, $\x02, $\x01";
2981
0
      break;
2982
0
    }
2983
42
    if (MCInst_getNumOperands(MI) == 3 &&
2984
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2985
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2986
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2987
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2988
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2989
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2990
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2991
0
      AsmString = "fmovsge %icc, $\x02, $\x01";
2992
0
      break;
2993
0
    }
2994
42
    if (MCInst_getNumOperands(MI) == 3 &&
2995
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2996
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2997
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2998
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2999
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3000
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3001
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3002
0
      AsmString = "fmovsl %icc, $\x02, $\x01";
3003
0
      break;
3004
0
    }
3005
42
    if (MCInst_getNumOperands(MI) == 3 &&
3006
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3007
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3008
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3009
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3010
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3011
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3012
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3013
0
      AsmString = "fmovsgu %icc, $\x02, $\x01";
3014
0
      break;
3015
0
    }
3016
42
    if (MCInst_getNumOperands(MI) == 3 &&
3017
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3018
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3019
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3020
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3021
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3022
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3023
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3024
0
      AsmString = "fmovsleu %icc, $\x02, $\x01";
3025
0
      break;
3026
0
    }
3027
42
    if (MCInst_getNumOperands(MI) == 3 &&
3028
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3029
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3030
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3031
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3032
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3033
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3034
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3035
0
      AsmString = "fmovscc %icc, $\x02, $\x01";
3036
0
      break;
3037
0
    }
3038
42
    if (MCInst_getNumOperands(MI) == 3 &&
3039
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3040
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3041
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3042
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3043
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3044
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3045
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3046
0
      AsmString = "fmovscs %icc, $\x02, $\x01";
3047
0
      break;
3048
0
    }
3049
42
    if (MCInst_getNumOperands(MI) == 3 &&
3050
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3051
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3052
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3053
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3054
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3055
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3056
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3057
0
      AsmString = "fmovspos %icc, $\x02, $\x01";
3058
0
      break;
3059
0
    }
3060
42
    if (MCInst_getNumOperands(MI) == 3 &&
3061
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3062
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3063
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3064
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3065
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3066
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3067
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3068
0
      AsmString = "fmovsneg %icc, $\x02, $\x01";
3069
0
      break;
3070
0
    }
3071
42
    if (MCInst_getNumOperands(MI) == 3 &&
3072
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3073
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3074
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3075
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3076
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3077
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3078
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3079
0
      AsmString = "fmovsvc %icc, $\x02, $\x01";
3080
0
      break;
3081
0
    }
3082
42
    if (MCInst_getNumOperands(MI) == 3 &&
3083
42
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3084
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3085
42
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3086
42
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3087
42
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3088
42
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3089
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3090
0
      AsmString = "fmovsvs %icc, $\x02, $\x01";
3091
0
      break;
3092
0
    }
3093
42
    return NULL;
3094
23
  case SP_FMOVS_XCC:
3095
23
    if (MCInst_getNumOperands(MI) == 3 &&
3096
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3097
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3098
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3099
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3100
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3101
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3102
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3103
0
      AsmString = "fmovsa %xcc, $\x02, $\x01";
3104
0
      break;
3105
0
    }
3106
23
    if (MCInst_getNumOperands(MI) == 3 &&
3107
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3108
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3109
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3110
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3111
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3112
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3113
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3114
0
      AsmString = "fmovsn %xcc, $\x02, $\x01";
3115
0
      break;
3116
0
    }
3117
23
    if (MCInst_getNumOperands(MI) == 3 &&
3118
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3119
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3120
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3121
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3122
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3123
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3124
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3125
0
      AsmString = "fmovsne %xcc, $\x02, $\x01";
3126
0
      break;
3127
0
    }
3128
23
    if (MCInst_getNumOperands(MI) == 3 &&
3129
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3130
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3131
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3132
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3133
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3134
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3135
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3136
0
      AsmString = "fmovse %xcc, $\x02, $\x01";
3137
0
      break;
3138
0
    }
3139
23
    if (MCInst_getNumOperands(MI) == 3 &&
3140
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3141
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3142
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3143
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3144
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3145
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3146
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3147
0
      AsmString = "fmovsg %xcc, $\x02, $\x01";
3148
0
      break;
3149
0
    }
3150
23
    if (MCInst_getNumOperands(MI) == 3 &&
3151
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3152
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3153
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3154
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3155
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3156
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3157
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3158
0
      AsmString = "fmovsle %xcc, $\x02, $\x01";
3159
0
      break;
3160
0
    }
3161
23
    if (MCInst_getNumOperands(MI) == 3 &&
3162
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3163
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3164
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3165
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3166
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3167
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3168
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3169
0
      AsmString = "fmovsge %xcc, $\x02, $\x01";
3170
0
      break;
3171
0
    }
3172
23
    if (MCInst_getNumOperands(MI) == 3 &&
3173
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3174
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3175
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3176
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3177
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3178
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3179
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3180
0
      AsmString = "fmovsl %xcc, $\x02, $\x01";
3181
0
      break;
3182
0
    }
3183
23
    if (MCInst_getNumOperands(MI) == 3 &&
3184
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3185
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3186
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3187
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3188
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3190
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3191
0
      AsmString = "fmovsgu %xcc, $\x02, $\x01";
3192
0
      break;
3193
0
    }
3194
23
    if (MCInst_getNumOperands(MI) == 3 &&
3195
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3196
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3197
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3198
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3199
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3200
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3201
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3202
0
      AsmString = "fmovsleu %xcc, $\x02, $\x01";
3203
0
      break;
3204
0
    }
3205
23
    if (MCInst_getNumOperands(MI) == 3 &&
3206
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3207
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3208
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3209
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3210
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3211
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3212
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3213
0
      AsmString = "fmovscc %xcc, $\x02, $\x01";
3214
0
      break;
3215
0
    }
3216
23
    if (MCInst_getNumOperands(MI) == 3 &&
3217
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3218
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3219
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3220
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3221
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3222
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3223
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3224
0
      AsmString = "fmovscs %xcc, $\x02, $\x01";
3225
0
      break;
3226
0
    }
3227
23
    if (MCInst_getNumOperands(MI) == 3 &&
3228
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3229
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3230
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3231
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3232
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3233
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3234
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3235
0
      AsmString = "fmovspos %xcc, $\x02, $\x01";
3236
0
      break;
3237
0
    }
3238
23
    if (MCInst_getNumOperands(MI) == 3 &&
3239
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3240
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3241
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3242
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3243
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3244
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3245
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3246
0
      AsmString = "fmovsneg %xcc, $\x02, $\x01";
3247
0
      break;
3248
0
    }
3249
23
    if (MCInst_getNumOperands(MI) == 3 &&
3250
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3251
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3252
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3253
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3254
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3255
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3256
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3257
0
      AsmString = "fmovsvc %xcc, $\x02, $\x01";
3258
0
      break;
3259
0
    }
3260
23
    if (MCInst_getNumOperands(MI) == 3 &&
3261
23
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3262
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3263
23
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3264
23
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3265
23
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3266
23
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3267
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3268
0
      AsmString = "fmovsvs %xcc, $\x02, $\x01";
3269
0
      break;
3270
0
    }
3271
23
    return NULL;
3272
143
  case SP_MOVICCri:
3273
143
    if (MCInst_getNumOperands(MI) == 3 &&
3274
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3275
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3276
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3277
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3278
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3279
0
      AsmString = "mova %icc, $\x02, $\x01";
3280
0
      break;
3281
0
    }
3282
143
    if (MCInst_getNumOperands(MI) == 3 &&
3283
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3284
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3285
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3286
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3287
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3288
0
      AsmString = "movn %icc, $\x02, $\x01";
3289
0
      break;
3290
0
    }
3291
143
    if (MCInst_getNumOperands(MI) == 3 &&
3292
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3293
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3294
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3295
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3296
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3297
0
      AsmString = "movne %icc, $\x02, $\x01";
3298
0
      break;
3299
0
    }
3300
143
    if (MCInst_getNumOperands(MI) == 3 &&
3301
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3302
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3303
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3304
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3305
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3306
0
      AsmString = "move %icc, $\x02, $\x01";
3307
0
      break;
3308
0
    }
3309
143
    if (MCInst_getNumOperands(MI) == 3 &&
3310
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3311
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3312
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3313
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3314
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3315
0
      AsmString = "movg %icc, $\x02, $\x01";
3316
0
      break;
3317
0
    }
3318
143
    if (MCInst_getNumOperands(MI) == 3 &&
3319
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3320
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3321
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3322
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3323
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3324
0
      AsmString = "movle %icc, $\x02, $\x01";
3325
0
      break;
3326
0
    }
3327
143
    if (MCInst_getNumOperands(MI) == 3 &&
3328
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3329
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3330
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3331
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3332
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3333
0
      AsmString = "movge %icc, $\x02, $\x01";
3334
0
      break;
3335
0
    }
3336
143
    if (MCInst_getNumOperands(MI) == 3 &&
3337
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3338
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3339
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3340
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3341
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3342
0
      AsmString = "movl %icc, $\x02, $\x01";
3343
0
      break;
3344
0
    }
3345
143
    if (MCInst_getNumOperands(MI) == 3 &&
3346
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3347
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3348
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3349
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3350
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3351
0
      AsmString = "movgu %icc, $\x02, $\x01";
3352
0
      break;
3353
0
    }
3354
143
    if (MCInst_getNumOperands(MI) == 3 &&
3355
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3356
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3357
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3358
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3359
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3360
0
      AsmString = "movleu %icc, $\x02, $\x01";
3361
0
      break;
3362
0
    }
3363
143
    if (MCInst_getNumOperands(MI) == 3 &&
3364
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3365
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3366
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3367
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3368
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3369
0
      AsmString = "movcc %icc, $\x02, $\x01";
3370
0
      break;
3371
0
    }
3372
143
    if (MCInst_getNumOperands(MI) == 3 &&
3373
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3374
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3375
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3376
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3377
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3378
0
      AsmString = "movcs %icc, $\x02, $\x01";
3379
0
      break;
3380
0
    }
3381
143
    if (MCInst_getNumOperands(MI) == 3 &&
3382
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3383
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3384
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3385
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3386
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3387
0
      AsmString = "movpos %icc, $\x02, $\x01";
3388
0
      break;
3389
0
    }
3390
143
    if (MCInst_getNumOperands(MI) == 3 &&
3391
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3392
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3393
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3394
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3395
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3396
0
      AsmString = "movneg %icc, $\x02, $\x01";
3397
0
      break;
3398
0
    }
3399
143
    if (MCInst_getNumOperands(MI) == 3 &&
3400
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3401
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3402
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3403
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3404
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3405
0
      AsmString = "movvc %icc, $\x02, $\x01";
3406
0
      break;
3407
0
    }
3408
143
    if (MCInst_getNumOperands(MI) == 3 &&
3409
143
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3410
143
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3411
143
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3412
143
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3413
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3414
0
      AsmString = "movvs %icc, $\x02, $\x01";
3415
0
      break;
3416
0
    }
3417
143
    return NULL;
3418
159
  case SP_MOVICCrr:
3419
159
    if (MCInst_getNumOperands(MI) == 3 &&
3420
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3421
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3422
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3423
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3424
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3425
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3426
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3427
0
      AsmString = "mova %icc, $\x02, $\x01";
3428
0
      break;
3429
0
    }
3430
159
    if (MCInst_getNumOperands(MI) == 3 &&
3431
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3432
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3433
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3434
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3435
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3436
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3437
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3438
0
      AsmString = "movn %icc, $\x02, $\x01";
3439
0
      break;
3440
0
    }
3441
159
    if (MCInst_getNumOperands(MI) == 3 &&
3442
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3443
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3444
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3445
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3446
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3447
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3448
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3449
0
      AsmString = "movne %icc, $\x02, $\x01";
3450
0
      break;
3451
0
    }
3452
159
    if (MCInst_getNumOperands(MI) == 3 &&
3453
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3454
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3455
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3456
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3457
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3458
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3459
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3460
0
      AsmString = "move %icc, $\x02, $\x01";
3461
0
      break;
3462
0
    }
3463
159
    if (MCInst_getNumOperands(MI) == 3 &&
3464
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3465
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3466
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3467
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3468
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3469
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3470
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3471
0
      AsmString = "movg %icc, $\x02, $\x01";
3472
0
      break;
3473
0
    }
3474
159
    if (MCInst_getNumOperands(MI) == 3 &&
3475
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3476
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3477
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3478
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3479
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3480
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3481
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3482
0
      AsmString = "movle %icc, $\x02, $\x01";
3483
0
      break;
3484
0
    }
3485
159
    if (MCInst_getNumOperands(MI) == 3 &&
3486
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3487
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3488
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3489
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3490
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3491
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3492
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3493
0
      AsmString = "movge %icc, $\x02, $\x01";
3494
0
      break;
3495
0
    }
3496
159
    if (MCInst_getNumOperands(MI) == 3 &&
3497
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3498
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3499
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3500
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3501
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3502
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3503
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3504
0
      AsmString = "movl %icc, $\x02, $\x01";
3505
0
      break;
3506
0
    }
3507
159
    if (MCInst_getNumOperands(MI) == 3 &&
3508
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3509
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3510
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3511
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3512
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3513
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3514
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3515
0
      AsmString = "movgu %icc, $\x02, $\x01";
3516
0
      break;
3517
0
    }
3518
159
    if (MCInst_getNumOperands(MI) == 3 &&
3519
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3520
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3521
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3522
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3523
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3524
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3525
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3526
0
      AsmString = "movleu %icc, $\x02, $\x01";
3527
0
      break;
3528
0
    }
3529
159
    if (MCInst_getNumOperands(MI) == 3 &&
3530
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3531
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3532
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3533
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3534
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3535
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3536
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3537
0
      AsmString = "movcc %icc, $\x02, $\x01";
3538
0
      break;
3539
0
    }
3540
159
    if (MCInst_getNumOperands(MI) == 3 &&
3541
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3542
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3543
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3544
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3545
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3546
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3547
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3548
0
      AsmString = "movcs %icc, $\x02, $\x01";
3549
0
      break;
3550
0
    }
3551
159
    if (MCInst_getNumOperands(MI) == 3 &&
3552
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3553
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3554
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3555
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3556
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3557
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3558
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3559
0
      AsmString = "movpos %icc, $\x02, $\x01";
3560
0
      break;
3561
0
    }
3562
159
    if (MCInst_getNumOperands(MI) == 3 &&
3563
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3564
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3565
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3566
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3567
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3568
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3569
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3570
0
      AsmString = "movneg %icc, $\x02, $\x01";
3571
0
      break;
3572
0
    }
3573
159
    if (MCInst_getNumOperands(MI) == 3 &&
3574
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3575
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3576
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3577
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3578
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3579
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3580
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3581
0
      AsmString = "movvc %icc, $\x02, $\x01";
3582
0
      break;
3583
0
    }
3584
159
    if (MCInst_getNumOperands(MI) == 3 &&
3585
159
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3586
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3587
159
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3588
159
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3589
159
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3590
159
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3591
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3592
0
      AsmString = "movvs %icc, $\x02, $\x01";
3593
0
      break;
3594
0
    }
3595
159
    return NULL;
3596
63
  case SP_MOVXCCri:
3597
63
    if (MCInst_getNumOperands(MI) == 3 &&
3598
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3599
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3600
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3601
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3602
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3603
0
      AsmString = "mova %xcc, $\x02, $\x01";
3604
0
      break;
3605
0
    }
3606
63
    if (MCInst_getNumOperands(MI) == 3 &&
3607
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3608
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3609
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3610
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3611
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3612
0
      AsmString = "movn %xcc, $\x02, $\x01";
3613
0
      break;
3614
0
    }
3615
63
    if (MCInst_getNumOperands(MI) == 3 &&
3616
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3617
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3618
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3619
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3620
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3621
0
      AsmString = "movne %xcc, $\x02, $\x01";
3622
0
      break;
3623
0
    }
3624
63
    if (MCInst_getNumOperands(MI) == 3 &&
3625
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3626
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3627
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3628
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3629
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3630
0
      AsmString = "move %xcc, $\x02, $\x01";
3631
0
      break;
3632
0
    }
3633
63
    if (MCInst_getNumOperands(MI) == 3 &&
3634
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3635
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3636
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3637
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3638
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3639
0
      AsmString = "movg %xcc, $\x02, $\x01";
3640
0
      break;
3641
0
    }
3642
63
    if (MCInst_getNumOperands(MI) == 3 &&
3643
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3644
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3645
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3646
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3647
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3648
0
      AsmString = "movle %xcc, $\x02, $\x01";
3649
0
      break;
3650
0
    }
3651
63
    if (MCInst_getNumOperands(MI) == 3 &&
3652
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3653
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3654
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3655
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3656
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3657
0
      AsmString = "movge %xcc, $\x02, $\x01";
3658
0
      break;
3659
0
    }
3660
63
    if (MCInst_getNumOperands(MI) == 3 &&
3661
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3662
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3663
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3664
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3665
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3666
0
      AsmString = "movl %xcc, $\x02, $\x01";
3667
0
      break;
3668
0
    }
3669
63
    if (MCInst_getNumOperands(MI) == 3 &&
3670
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3671
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3672
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3673
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3674
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3675
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3676
0
      break;
3677
0
    }
3678
63
    if (MCInst_getNumOperands(MI) == 3 &&
3679
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3680
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3681
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3682
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3683
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3684
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3685
0
      break;
3686
0
    }
3687
63
    if (MCInst_getNumOperands(MI) == 3 &&
3688
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3689
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3690
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3691
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3692
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3693
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3694
0
      break;
3695
0
    }
3696
63
    if (MCInst_getNumOperands(MI) == 3 &&
3697
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3698
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3699
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3700
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3701
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3702
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3703
0
      break;
3704
0
    }
3705
63
    if (MCInst_getNumOperands(MI) == 3 &&
3706
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3707
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3708
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3709
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3710
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3711
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3712
0
      break;
3713
0
    }
3714
63
    if (MCInst_getNumOperands(MI) == 3 &&
3715
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3716
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3717
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3718
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3719
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3720
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3721
0
      break;
3722
0
    }
3723
63
    if (MCInst_getNumOperands(MI) == 3 &&
3724
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3725
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3726
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3727
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3728
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3729
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3730
0
      break;
3731
0
    }
3732
63
    if (MCInst_getNumOperands(MI) == 3 &&
3733
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3734
63
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3735
63
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3736
63
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3737
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3738
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3739
0
      break;
3740
0
    }
3741
63
    return NULL;
3742
199
  case SP_MOVXCCrr:
3743
199
    if (MCInst_getNumOperands(MI) == 3 &&
3744
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3745
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3746
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3747
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3748
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3749
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3750
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3751
0
      AsmString = "mova %xcc, $\x02, $\x01";
3752
0
      break;
3753
0
    }
3754
199
    if (MCInst_getNumOperands(MI) == 3 &&
3755
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3756
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3757
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3758
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3759
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3760
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3761
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3762
0
      AsmString = "movn %xcc, $\x02, $\x01";
3763
0
      break;
3764
0
    }
3765
199
    if (MCInst_getNumOperands(MI) == 3 &&
3766
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3767
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3768
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3769
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3770
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3771
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3772
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3773
0
      AsmString = "movne %xcc, $\x02, $\x01";
3774
0
      break;
3775
0
    }
3776
199
    if (MCInst_getNumOperands(MI) == 3 &&
3777
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3778
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3779
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3780
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3781
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3782
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3783
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3784
0
      AsmString = "move %xcc, $\x02, $\x01";
3785
0
      break;
3786
0
    }
3787
199
    if (MCInst_getNumOperands(MI) == 3 &&
3788
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3789
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3790
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3791
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3792
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3793
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3794
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3795
0
      AsmString = "movg %xcc, $\x02, $\x01";
3796
0
      break;
3797
0
    }
3798
199
    if (MCInst_getNumOperands(MI) == 3 &&
3799
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3800
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3801
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3802
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3803
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3804
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3805
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3806
0
      AsmString = "movle %xcc, $\x02, $\x01";
3807
0
      break;
3808
0
    }
3809
199
    if (MCInst_getNumOperands(MI) == 3 &&
3810
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3811
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3812
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3813
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3814
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3815
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3816
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3817
0
      AsmString = "movge %xcc, $\x02, $\x01";
3818
0
      break;
3819
0
    }
3820
199
    if (MCInst_getNumOperands(MI) == 3 &&
3821
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3822
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3823
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3824
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3825
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3826
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3827
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3828
0
      AsmString = "movl %xcc, $\x02, $\x01";
3829
0
      break;
3830
0
    }
3831
199
    if (MCInst_getNumOperands(MI) == 3 &&
3832
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3833
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3834
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3835
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3836
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3837
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3838
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3839
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3840
0
      break;
3841
0
    }
3842
199
    if (MCInst_getNumOperands(MI) == 3 &&
3843
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3844
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3845
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3846
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3847
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3848
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3849
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3850
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3851
0
      break;
3852
0
    }
3853
199
    if (MCInst_getNumOperands(MI) == 3 &&
3854
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3855
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3856
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3857
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3858
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3859
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3860
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3861
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3862
0
      break;
3863
0
    }
3864
199
    if (MCInst_getNumOperands(MI) == 3 &&
3865
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3866
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3867
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3868
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3869
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3870
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3871
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3872
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3873
0
      break;
3874
0
    }
3875
199
    if (MCInst_getNumOperands(MI) == 3 &&
3876
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3877
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3878
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3879
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3880
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3881
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3882
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3883
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3884
0
      break;
3885
0
    }
3886
199
    if (MCInst_getNumOperands(MI) == 3 &&
3887
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3888
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3889
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3890
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3891
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3892
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3893
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3894
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3895
0
      break;
3896
0
    }
3897
199
    if (MCInst_getNumOperands(MI) == 3 &&
3898
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3899
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3900
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3901
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3902
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3903
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3904
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3905
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3906
0
      break;
3907
0
    }
3908
199
    if (MCInst_getNumOperands(MI) == 3 &&
3909
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3910
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3911
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3912
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3913
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3914
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3915
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3916
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3917
0
      break;
3918
0
    }
3919
199
    return NULL;
3920
80
  case SP_ORri:
3921
80
    if (MCInst_getNumOperands(MI) == 3 &&
3922
80
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3923
80
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3924
80
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3925
      // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3926
10
      AsmString = "mov $\x03, $\x01";
3927
10
      break;
3928
10
    }
3929
70
    return NULL;
3930
95
  case SP_ORrr:
3931
95
    if (MCInst_getNumOperands(MI) == 3 &&
3932
95
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3933
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3934
95
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3935
95
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3936
95
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3937
      // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3938
47
      AsmString = "mov $\x03, $\x01";
3939
47
      break;
3940
47
    }
3941
48
    return NULL;
3942
271
  case SP_RESTORErr:
3943
271
    if (MCInst_getNumOperands(MI) == 3 &&
3944
271
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3945
271
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3946
271
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3947
      // (RESTORErr G0, G0, G0)
3948
45
      AsmString = "restore";
3949
45
      break;
3950
45
    }
3951
226
    return NULL;
3952
0
  case SP_RET:
3953
0
    if (MCInst_getNumOperands(MI) == 1 &&
3954
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3955
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3956
      // (RET 8)
3957
0
      AsmString = "ret";
3958
0
      break;
3959
0
    }
3960
0
    return NULL;
3961
0
  case SP_RETL:
3962
0
    if (MCInst_getNumOperands(MI) == 1 &&
3963
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3964
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3965
      // (RETL 8)
3966
0
      AsmString = "retl";
3967
0
      break;
3968
0
    }
3969
0
    return NULL;
3970
2.51k
  case SP_TXCCri:
3971
2.51k
    if (MCInst_getNumOperands(MI) == 3 &&
3972
2.51k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3973
2.51k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3974
2.51k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3975
2.51k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3976
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3977
247
      AsmString = "ta %xcc, $\x01 + $\x02";
3978
247
      break;
3979
247
    }
3980
2.27k
    if (MCInst_getNumOperands(MI) == 3 &&
3981
2.27k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3982
2.27k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3983
2.27k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3984
      // (TXCCri G0, i32imm:$imm, 8)
3985
0
      AsmString = "ta %xcc, $\x02";
3986
0
      break;
3987
0
    }
3988
2.27k
    if (MCInst_getNumOperands(MI) == 3 &&
3989
2.27k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3990
2.27k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3991
2.27k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3992
2.27k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3993
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3994
184
      AsmString = "tn %xcc, $\x01 + $\x02";
3995
184
      break;
3996
184
    }
3997
2.08k
    if (MCInst_getNumOperands(MI) == 3 &&
3998
2.08k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3999
2.08k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4000
2.08k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4001
      // (TXCCri G0, i32imm:$imm, 0)
4002
0
      AsmString = "tn %xcc, $\x02";
4003
0
      break;
4004
0
    }
4005
2.08k
    if (MCInst_getNumOperands(MI) == 3 &&
4006
2.08k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4007
2.08k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4008
2.08k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4009
2.08k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4010
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4011
271
      AsmString = "tne %xcc, $\x01 + $\x02";
4012
271
      break;
4013
271
    }
4014
1.81k
    if (MCInst_getNumOperands(MI) == 3 &&
4015
1.81k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4016
1.81k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4017
1.81k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4018
      // (TXCCri G0, i32imm:$imm, 9)
4019
0
      AsmString = "tne %xcc, $\x02";
4020
0
      break;
4021
0
    }
4022
1.81k
    if (MCInst_getNumOperands(MI) == 3 &&
4023
1.81k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4024
1.81k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4025
1.81k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4026
1.81k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4027
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4028
40
      AsmString = "te %xcc, $\x01 + $\x02";
4029
40
      break;
4030
40
    }
4031
1.77k
    if (MCInst_getNumOperands(MI) == 3 &&
4032
1.77k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4033
1.77k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4034
1.77k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4035
      // (TXCCri G0, i32imm:$imm, 1)
4036
0
      AsmString = "te %xcc, $\x02";
4037
0
      break;
4038
0
    }
4039
1.77k
    if (MCInst_getNumOperands(MI) == 3 &&
4040
1.77k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4041
1.77k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4042
1.77k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4043
1.77k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4044
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4045
359
      AsmString = "tg %xcc, $\x01 + $\x02";
4046
359
      break;
4047
359
    }
4048
1.41k
    if (MCInst_getNumOperands(MI) == 3 &&
4049
1.41k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4050
1.41k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4051
1.41k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4052
      // (TXCCri G0, i32imm:$imm, 10)
4053
0
      AsmString = "tg %xcc, $\x02";
4054
0
      break;
4055
0
    }
4056
1.41k
    if (MCInst_getNumOperands(MI) == 3 &&
4057
1.41k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4058
1.41k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4059
1.41k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4060
1.41k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4061
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4062
751
      AsmString = "tle %xcc, $\x01 + $\x02";
4063
751
      break;
4064
751
    }
4065
667
    if (MCInst_getNumOperands(MI) == 3 &&
4066
667
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4067
667
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4068
667
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4069
      // (TXCCri G0, i32imm:$imm, 2)
4070
0
      AsmString = "tle %xcc, $\x02";
4071
0
      break;
4072
0
    }
4073
667
    if (MCInst_getNumOperands(MI) == 3 &&
4074
667
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4075
667
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4076
667
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4077
667
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4078
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4079
83
      AsmString = "tge %xcc, $\x01 + $\x02";
4080
83
      break;
4081
83
    }
4082
584
    if (MCInst_getNumOperands(MI) == 3 &&
4083
584
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4084
584
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4085
584
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4086
      // (TXCCri G0, i32imm:$imm, 11)
4087
0
      AsmString = "tge %xcc, $\x02";
4088
0
      break;
4089
0
    }
4090
584
    if (MCInst_getNumOperands(MI) == 3 &&
4091
584
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4092
584
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4093
584
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4094
584
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4095
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4096
56
      AsmString = "tl %xcc, $\x01 + $\x02";
4097
56
      break;
4098
56
    }
4099
528
    if (MCInst_getNumOperands(MI) == 3 &&
4100
528
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4101
528
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4102
528
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4103
      // (TXCCri G0, i32imm:$imm, 3)
4104
0
      AsmString = "tl %xcc, $\x02";
4105
0
      break;
4106
0
    }
4107
528
    if (MCInst_getNumOperands(MI) == 3 &&
4108
528
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4109
528
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4110
528
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4111
528
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4112
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4113
65
      AsmString = "tgu %xcc, $\x01 + $\x02";
4114
65
      break;
4115
65
    }
4116
463
    if (MCInst_getNumOperands(MI) == 3 &&
4117
463
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4118
463
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4119
463
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4120
      // (TXCCri G0, i32imm:$imm, 12)
4121
0
      AsmString = "tgu %xcc, $\x02";
4122
0
      break;
4123
0
    }
4124
463
    if (MCInst_getNumOperands(MI) == 3 &&
4125
463
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4126
463
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4127
463
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4128
463
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4129
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4130
19
      AsmString = "tleu %xcc, $\x01 + $\x02";
4131
19
      break;
4132
19
    }
4133
444
    if (MCInst_getNumOperands(MI) == 3 &&
4134
444
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4135
444
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4136
444
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4137
      // (TXCCri G0, i32imm:$imm, 4)
4138
0
      AsmString = "tleu %xcc, $\x02";
4139
0
      break;
4140
0
    }
4141
444
    if (MCInst_getNumOperands(MI) == 3 &&
4142
444
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4143
444
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4144
444
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4145
444
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4146
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4147
190
      AsmString = "tcc %xcc, $\x01 + $\x02";
4148
190
      break;
4149
190
    }
4150
254
    if (MCInst_getNumOperands(MI) == 3 &&
4151
254
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4152
254
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4153
254
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4154
      // (TXCCri G0, i32imm:$imm, 13)
4155
0
      AsmString = "tcc %xcc, $\x02";
4156
0
      break;
4157
0
    }
4158
254
    if (MCInst_getNumOperands(MI) == 3 &&
4159
254
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4160
254
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4161
254
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4162
254
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4163
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4164
24
      AsmString = "tcs %xcc, $\x01 + $\x02";
4165
24
      break;
4166
24
    }
4167
230
    if (MCInst_getNumOperands(MI) == 3 &&
4168
230
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4169
230
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4170
230
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4171
      // (TXCCri G0, i32imm:$imm, 5)
4172
0
      AsmString = "tcs %xcc, $\x02";
4173
0
      break;
4174
0
    }
4175
230
    if (MCInst_getNumOperands(MI) == 3 &&
4176
230
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4177
230
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4178
230
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4179
230
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4180
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4181
6
      AsmString = "tpos %xcc, $\x01 + $\x02";
4182
6
      break;
4183
6
    }
4184
224
    if (MCInst_getNumOperands(MI) == 3 &&
4185
224
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4186
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4187
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4188
      // (TXCCri G0, i32imm:$imm, 14)
4189
0
      AsmString = "tpos %xcc, $\x02";
4190
0
      break;
4191
0
    }
4192
224
    if (MCInst_getNumOperands(MI) == 3 &&
4193
224
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4194
224
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4195
224
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4196
224
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4197
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4198
87
      AsmString = "tneg %xcc, $\x01 + $\x02";
4199
87
      break;
4200
87
    }
4201
137
    if (MCInst_getNumOperands(MI) == 3 &&
4202
137
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4203
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4204
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4205
      // (TXCCri G0, i32imm:$imm, 6)
4206
0
      AsmString = "tneg %xcc, $\x02";
4207
0
      break;
4208
0
    }
4209
137
    if (MCInst_getNumOperands(MI) == 3 &&
4210
137
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4211
137
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4212
137
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4213
137
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4214
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4215
56
      AsmString = "tvc %xcc, $\x01 + $\x02";
4216
56
      break;
4217
56
    }
4218
81
    if (MCInst_getNumOperands(MI) == 3 &&
4219
81
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4220
81
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4221
81
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4222
      // (TXCCri G0, i32imm:$imm, 15)
4223
0
      AsmString = "tvc %xcc, $\x02";
4224
0
      break;
4225
0
    }
4226
81
    if (MCInst_getNumOperands(MI) == 3 &&
4227
81
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4228
81
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4229
81
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4230
81
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4231
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4232
81
      AsmString = "tvs %xcc, $\x01 + $\x02";
4233
81
      break;
4234
81
    }
4235
0
    if (MCInst_getNumOperands(MI) == 3 &&
4236
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4237
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4238
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4239
      // (TXCCri G0, i32imm:$imm, 7)
4240
0
      AsmString = "tvs %xcc, $\x02";
4241
0
      break;
4242
0
    }
4243
0
    return NULL;
4244
2.07k
  case SP_TXCCrr:
4245
2.07k
    if (MCInst_getNumOperands(MI) == 3 &&
4246
2.07k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4247
2.07k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4248
2.07k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4249
2.07k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4250
2.07k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4251
2.07k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4252
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4253
72
      AsmString = "ta %xcc, $\x01 + $\x02";
4254
72
      break;
4255
72
    }
4256
2.00k
    if (MCInst_getNumOperands(MI) == 3 &&
4257
2.00k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4258
2.00k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4259
2.00k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4260
2.00k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4261
2.00k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4262
      // (TXCCrr G0, IntRegs:$rs2, 8)
4263
0
      AsmString = "ta %xcc, $\x02";
4264
0
      break;
4265
0
    }
4266
2.00k
    if (MCInst_getNumOperands(MI) == 3 &&
4267
2.00k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4268
2.00k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4269
2.00k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4270
2.00k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4271
2.00k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4272
2.00k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4273
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4274
24
      AsmString = "tn %xcc, $\x01 + $\x02";
4275
24
      break;
4276
24
    }
4277
1.98k
    if (MCInst_getNumOperands(MI) == 3 &&
4278
1.98k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4279
1.98k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4280
1.98k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4281
1.98k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4282
1.98k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4283
      // (TXCCrr G0, IntRegs:$rs2, 0)
4284
0
      AsmString = "tn %xcc, $\x02";
4285
0
      break;
4286
0
    }
4287
1.98k
    if (MCInst_getNumOperands(MI) == 3 &&
4288
1.98k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4289
1.98k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4290
1.98k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4291
1.98k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4292
1.98k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4293
1.98k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4294
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4295
242
      AsmString = "tne %xcc, $\x01 + $\x02";
4296
242
      break;
4297
242
    }
4298
1.73k
    if (MCInst_getNumOperands(MI) == 3 &&
4299
1.73k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4300
1.73k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4301
1.73k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4302
1.73k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4303
1.73k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4304
      // (TXCCrr G0, IntRegs:$rs2, 9)
4305
0
      AsmString = "tne %xcc, $\x02";
4306
0
      break;
4307
0
    }
4308
1.73k
    if (MCInst_getNumOperands(MI) == 3 &&
4309
1.73k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4310
1.73k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4311
1.73k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4312
1.73k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4313
1.73k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4314
1.73k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4315
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4316
31
      AsmString = "te %xcc, $\x01 + $\x02";
4317
31
      break;
4318
31
    }
4319
1.70k
    if (MCInst_getNumOperands(MI) == 3 &&
4320
1.70k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4321
1.70k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4322
1.70k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4323
1.70k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4324
1.70k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4325
      // (TXCCrr G0, IntRegs:$rs2, 1)
4326
0
      AsmString = "te %xcc, $\x02";
4327
0
      break;
4328
0
    }
4329
1.70k
    if (MCInst_getNumOperands(MI) == 3 &&
4330
1.70k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4331
1.70k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4332
1.70k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4333
1.70k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4334
1.70k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4335
1.70k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4336
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4337
22
      AsmString = "tg %xcc, $\x01 + $\x02";
4338
22
      break;
4339
22
    }
4340
1.68k
    if (MCInst_getNumOperands(MI) == 3 &&
4341
1.68k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4342
1.68k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4343
1.68k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4344
1.68k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4345
1.68k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4346
      // (TXCCrr G0, IntRegs:$rs2, 10)
4347
0
      AsmString = "tg %xcc, $\x02";
4348
0
      break;
4349
0
    }
4350
1.68k
    if (MCInst_getNumOperands(MI) == 3 &&
4351
1.68k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4352
1.68k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4353
1.68k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4354
1.68k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4355
1.68k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4356
1.68k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4357
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4358
30
      AsmString = "tle %xcc, $\x01 + $\x02";
4359
30
      break;
4360
30
    }
4361
1.65k
    if (MCInst_getNumOperands(MI) == 3 &&
4362
1.65k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4363
1.65k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4364
1.65k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4365
1.65k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4366
1.65k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4367
      // (TXCCrr G0, IntRegs:$rs2, 2)
4368
0
      AsmString = "tle %xcc, $\x02";
4369
0
      break;
4370
0
    }
4371
1.65k
    if (MCInst_getNumOperands(MI) == 3 &&
4372
1.65k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4373
1.65k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4374
1.65k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4375
1.65k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4376
1.65k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4377
1.65k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4378
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4379
70
      AsmString = "tge %xcc, $\x01 + $\x02";
4380
70
      break;
4381
70
    }
4382
1.58k
    if (MCInst_getNumOperands(MI) == 3 &&
4383
1.58k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4384
1.58k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4385
1.58k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4386
1.58k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4387
1.58k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4388
      // (TXCCrr G0, IntRegs:$rs2, 11)
4389
0
      AsmString = "tge %xcc, $\x02";
4390
0
      break;
4391
0
    }
4392
1.58k
    if (MCInst_getNumOperands(MI) == 3 &&
4393
1.58k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4394
1.58k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4395
1.58k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4396
1.58k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4397
1.58k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4398
1.58k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4399
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4400
363
      AsmString = "tl %xcc, $\x01 + $\x02";
4401
363
      break;
4402
363
    }
4403
1.22k
    if (MCInst_getNumOperands(MI) == 3 &&
4404
1.22k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4405
1.22k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4406
1.22k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4407
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4408
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4409
      // (TXCCrr G0, IntRegs:$rs2, 3)
4410
0
      AsmString = "tl %xcc, $\x02";
4411
0
      break;
4412
0
    }
4413
1.22k
    if (MCInst_getNumOperands(MI) == 3 &&
4414
1.22k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4415
1.22k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4416
1.22k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4417
1.22k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4418
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4419
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4420
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4421
53
      AsmString = "tgu %xcc, $\x01 + $\x02";
4422
53
      break;
4423
53
    }
4424
1.16k
    if (MCInst_getNumOperands(MI) == 3 &&
4425
1.16k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4426
1.16k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4427
1.16k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4428
1.16k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4429
1.16k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4430
      // (TXCCrr G0, IntRegs:$rs2, 12)
4431
0
      AsmString = "tgu %xcc, $\x02";
4432
0
      break;
4433
0
    }
4434
1.16k
    if (MCInst_getNumOperands(MI) == 3 &&
4435
1.16k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4436
1.16k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4437
1.16k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4438
1.16k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4439
1.16k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4440
1.16k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4441
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4442
18
      AsmString = "tleu %xcc, $\x01 + $\x02";
4443
18
      break;
4444
18
    }
4445
1.15k
    if (MCInst_getNumOperands(MI) == 3 &&
4446
1.15k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4447
1.15k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4448
1.15k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4449
1.15k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4450
1.15k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4451
      // (TXCCrr G0, IntRegs:$rs2, 4)
4452
0
      AsmString = "tleu %xcc, $\x02";
4453
0
      break;
4454
0
    }
4455
1.15k
    if (MCInst_getNumOperands(MI) == 3 &&
4456
1.15k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4457
1.15k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4458
1.15k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4459
1.15k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4460
1.15k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4461
1.15k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4462
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4463
160
      AsmString = "tcc %xcc, $\x01 + $\x02";
4464
160
      break;
4465
160
    }
4466
991
    if (MCInst_getNumOperands(MI) == 3 &&
4467
991
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4468
991
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4469
991
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4470
991
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4471
991
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4472
      // (TXCCrr G0, IntRegs:$rs2, 13)
4473
0
      AsmString = "tcc %xcc, $\x02";
4474
0
      break;
4475
0
    }
4476
991
    if (MCInst_getNumOperands(MI) == 3 &&
4477
991
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4478
991
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4479
991
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4480
991
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4481
991
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4482
991
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4483
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4484
28
      AsmString = "tcs %xcc, $\x01 + $\x02";
4485
28
      break;
4486
28
    }
4487
963
    if (MCInst_getNumOperands(MI) == 3 &&
4488
963
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4489
963
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4490
963
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4491
963
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4492
963
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4493
      // (TXCCrr G0, IntRegs:$rs2, 5)
4494
0
      AsmString = "tcs %xcc, $\x02";
4495
0
      break;
4496
0
    }
4497
963
    if (MCInst_getNumOperands(MI) == 3 &&
4498
963
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4499
963
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4500
963
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4501
963
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4502
963
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4503
963
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4504
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4505
229
      AsmString = "tpos %xcc, $\x01 + $\x02";
4506
229
      break;
4507
229
    }
4508
734
    if (MCInst_getNumOperands(MI) == 3 &&
4509
734
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4510
734
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4511
734
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4512
734
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4513
734
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4514
      // (TXCCrr G0, IntRegs:$rs2, 14)
4515
0
      AsmString = "tpos %xcc, $\x02";
4516
0
      break;
4517
0
    }
4518
734
    if (MCInst_getNumOperands(MI) == 3 &&
4519
734
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4520
734
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4521
734
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4522
734
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4523
734
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4524
734
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4525
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4526
51
      AsmString = "tneg %xcc, $\x01 + $\x02";
4527
51
      break;
4528
51
    }
4529
683
    if (MCInst_getNumOperands(MI) == 3 &&
4530
683
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4531
683
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4532
683
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4533
683
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4534
683
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4535
      // (TXCCrr G0, IntRegs:$rs2, 6)
4536
0
      AsmString = "tneg %xcc, $\x02";
4537
0
      break;
4538
0
    }
4539
683
    if (MCInst_getNumOperands(MI) == 3 &&
4540
683
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4541
683
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4542
683
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4543
683
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4544
683
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4545
683
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4546
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4547
182
      AsmString = "tvc %xcc, $\x01 + $\x02";
4548
182
      break;
4549
182
    }
4550
501
    if (MCInst_getNumOperands(MI) == 3 &&
4551
501
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4552
501
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4553
501
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4554
501
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4555
501
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4556
      // (TXCCrr G0, IntRegs:$rs2, 15)
4557
0
      AsmString = "tvc %xcc, $\x02";
4558
0
      break;
4559
0
    }
4560
501
    if (MCInst_getNumOperands(MI) == 3 &&
4561
501
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4562
501
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4563
501
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4564
501
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4565
501
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4566
501
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4567
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4568
501
      AsmString = "tvs %xcc, $\x01 + $\x02";
4569
501
      break;
4570
501
    }
4571
0
    if (MCInst_getNumOperands(MI) == 3 &&
4572
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4573
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4574
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4575
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4576
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4577
      // (TXCCrr G0, IntRegs:$rs2, 7)
4578
0
      AsmString = "tvs %xcc, $\x02";
4579
0
      break;
4580
0
    }
4581
0
    return NULL;
4582
75
  case SP_V9FCMPD:
4583
75
    if (MCInst_getNumOperands(MI) == 3 &&
4584
75
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4585
75
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4586
75
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4587
75
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4588
75
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4589
      // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4590
24
      AsmString = "fcmpd $\x02, $\x03";
4591
24
      break;
4592
24
    }
4593
51
    return NULL;
4594
385
  case SP_V9FCMPED:
4595
385
    if (MCInst_getNumOperands(MI) == 3 &&
4596
385
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4597
385
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4598
385
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4599
385
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4600
385
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4601
      // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4602
363
      AsmString = "fcmped $\x02, $\x03";
4603
363
      break;
4604
363
    }
4605
22
    return NULL;
4606
375
  case SP_V9FCMPEQ:
4607
375
    if (MCInst_getNumOperands(MI) == 3 &&
4608
375
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4609
375
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4610
375
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4611
375
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4612
375
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4613
      // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4614
26
      AsmString = "fcmpeq $\x02, $\x03";
4615
26
      break;
4616
26
    }
4617
349
    return NULL;
4618
535
  case SP_V9FCMPES:
4619
535
    if (MCInst_getNumOperands(MI) == 3 &&
4620
535
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4621
535
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4622
535
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4623
535
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4624
535
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4625
      // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4626
500
      AsmString = "fcmpes $\x02, $\x03";
4627
500
      break;
4628
500
    }
4629
35
    return NULL;
4630
88
  case SP_V9FCMPQ:
4631
88
    if (MCInst_getNumOperands(MI) == 3 &&
4632
88
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4633
88
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4634
88
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4635
88
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4636
88
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4637
      // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4638
46
      AsmString = "fcmpq $\x02, $\x03";
4639
46
      break;
4640
46
    }
4641
42
    return NULL;
4642
270
  case SP_V9FCMPS:
4643
270
    if (MCInst_getNumOperands(MI) == 3 &&
4644
270
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4645
270
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4646
270
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4647
270
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4648
270
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4649
      // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4650
69
      AsmString = "fcmps $\x02, $\x03";
4651
69
      break;
4652
69
    }
4653
201
    return NULL;
4654
63
  case SP_V9FMOVD_FCC:
4655
63
    if (MCInst_getNumOperands(MI) == 4 &&
4656
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4657
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4658
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4659
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4660
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4661
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4662
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4663
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4664
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4665
0
      AsmString = "fmovda $\x02, $\x03, $\x01";
4666
0
      break;
4667
0
    }
4668
63
    if (MCInst_getNumOperands(MI) == 4 &&
4669
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4670
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4671
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4672
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4673
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4674
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4675
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4676
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4677
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4678
0
      AsmString = "fmovdn $\x02, $\x03, $\x01";
4679
0
      break;
4680
0
    }
4681
63
    if (MCInst_getNumOperands(MI) == 4 &&
4682
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4683
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4684
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4685
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4686
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4687
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4688
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4689
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4690
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4691
0
      AsmString = "fmovdu $\x02, $\x03, $\x01";
4692
0
      break;
4693
0
    }
4694
63
    if (MCInst_getNumOperands(MI) == 4 &&
4695
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4696
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4697
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4698
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4699
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4700
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4701
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4702
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4703
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4704
0
      AsmString = "fmovdg $\x02, $\x03, $\x01";
4705
0
      break;
4706
0
    }
4707
63
    if (MCInst_getNumOperands(MI) == 4 &&
4708
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4709
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4710
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4711
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4712
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4713
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4714
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4715
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4716
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4717
0
      AsmString = "fmovdug $\x02, $\x03, $\x01";
4718
0
      break;
4719
0
    }
4720
63
    if (MCInst_getNumOperands(MI) == 4 &&
4721
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4722
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4723
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4724
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4725
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4726
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4727
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4728
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4729
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4730
0
      AsmString = "fmovdl $\x02, $\x03, $\x01";
4731
0
      break;
4732
0
    }
4733
63
    if (MCInst_getNumOperands(MI) == 4 &&
4734
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4735
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4736
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4737
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4738
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4739
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4740
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4741
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4742
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4743
0
      AsmString = "fmovdul $\x02, $\x03, $\x01";
4744
0
      break;
4745
0
    }
4746
63
    if (MCInst_getNumOperands(MI) == 4 &&
4747
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4748
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4749
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4750
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4751
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4752
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4753
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4754
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4755
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4756
0
      AsmString = "fmovdlg $\x02, $\x03, $\x01";
4757
0
      break;
4758
0
    }
4759
63
    if (MCInst_getNumOperands(MI) == 4 &&
4760
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4761
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4762
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4763
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4764
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4765
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4766
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4767
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4768
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4769
0
      AsmString = "fmovdne $\x02, $\x03, $\x01";
4770
0
      break;
4771
0
    }
4772
63
    if (MCInst_getNumOperands(MI) == 4 &&
4773
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4774
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4775
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4776
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4777
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4778
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4779
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4780
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4781
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4782
0
      AsmString = "fmovde $\x02, $\x03, $\x01";
4783
0
      break;
4784
0
    }
4785
63
    if (MCInst_getNumOperands(MI) == 4 &&
4786
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4787
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4788
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4789
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4790
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4791
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4792
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4793
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4794
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4795
0
      AsmString = "fmovdue $\x02, $\x03, $\x01";
4796
0
      break;
4797
0
    }
4798
63
    if (MCInst_getNumOperands(MI) == 4 &&
4799
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4800
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4801
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4802
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4803
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4804
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4805
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4806
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4807
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4808
0
      AsmString = "fmovdge $\x02, $\x03, $\x01";
4809
0
      break;
4810
0
    }
4811
63
    if (MCInst_getNumOperands(MI) == 4 &&
4812
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4813
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4814
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4815
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4816
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4817
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4818
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4819
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4820
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4821
0
      AsmString = "fmovduge $\x02, $\x03, $\x01";
4822
0
      break;
4823
0
    }
4824
63
    if (MCInst_getNumOperands(MI) == 4 &&
4825
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4826
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4827
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4828
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4829
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4830
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4831
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4832
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4833
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4834
0
      AsmString = "fmovdle $\x02, $\x03, $\x01";
4835
0
      break;
4836
0
    }
4837
63
    if (MCInst_getNumOperands(MI) == 4 &&
4838
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4839
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4840
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4841
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4842
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4843
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4844
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4845
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4846
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4847
0
      AsmString = "fmovdule $\x02, $\x03, $\x01";
4848
0
      break;
4849
0
    }
4850
63
    if (MCInst_getNumOperands(MI) == 4 &&
4851
63
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4852
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4853
63
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4854
63
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4855
63
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4856
63
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4857
63
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4858
63
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4859
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4860
0
      AsmString = "fmovdo $\x02, $\x03, $\x01";
4861
0
      break;
4862
0
    }
4863
63
    return NULL;
4864
38
  case SP_V9FMOVQ_FCC:
4865
38
    if (MCInst_getNumOperands(MI) == 4 &&
4866
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4867
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4868
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4869
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4870
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4871
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4872
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4873
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4874
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4875
0
      AsmString = "fmovqa $\x02, $\x03, $\x01";
4876
0
      break;
4877
0
    }
4878
38
    if (MCInst_getNumOperands(MI) == 4 &&
4879
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4880
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4881
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4882
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4883
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4884
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4885
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4886
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4887
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4888
0
      AsmString = "fmovqn $\x02, $\x03, $\x01";
4889
0
      break;
4890
0
    }
4891
38
    if (MCInst_getNumOperands(MI) == 4 &&
4892
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4893
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4894
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4895
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4896
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4897
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4898
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4899
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4900
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4901
0
      AsmString = "fmovqu $\x02, $\x03, $\x01";
4902
0
      break;
4903
0
    }
4904
38
    if (MCInst_getNumOperands(MI) == 4 &&
4905
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4906
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4907
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4908
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4909
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4910
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4911
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4912
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4913
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4914
0
      AsmString = "fmovqg $\x02, $\x03, $\x01";
4915
0
      break;
4916
0
    }
4917
38
    if (MCInst_getNumOperands(MI) == 4 &&
4918
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4919
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4920
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4921
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4922
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4923
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4924
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4925
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4926
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4927
0
      AsmString = "fmovqug $\x02, $\x03, $\x01";
4928
0
      break;
4929
0
    }
4930
38
    if (MCInst_getNumOperands(MI) == 4 &&
4931
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4932
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4933
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4934
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4935
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4936
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4937
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4938
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4939
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4940
0
      AsmString = "fmovql $\x02, $\x03, $\x01";
4941
0
      break;
4942
0
    }
4943
38
    if (MCInst_getNumOperands(MI) == 4 &&
4944
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4945
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4946
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4947
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4948
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4949
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4950
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4951
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4952
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4953
0
      AsmString = "fmovqul $\x02, $\x03, $\x01";
4954
0
      break;
4955
0
    }
4956
38
    if (MCInst_getNumOperands(MI) == 4 &&
4957
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4958
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4959
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4960
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4961
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4962
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4963
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4964
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4965
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4966
0
      AsmString = "fmovqlg $\x02, $\x03, $\x01";
4967
0
      break;
4968
0
    }
4969
38
    if (MCInst_getNumOperands(MI) == 4 &&
4970
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4971
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4972
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4973
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4974
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4975
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4976
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4977
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4978
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4979
0
      AsmString = "fmovqne $\x02, $\x03, $\x01";
4980
0
      break;
4981
0
    }
4982
38
    if (MCInst_getNumOperands(MI) == 4 &&
4983
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4984
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4985
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4986
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4987
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4988
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4989
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4990
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4991
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4992
0
      AsmString = "fmovqe $\x02, $\x03, $\x01";
4993
0
      break;
4994
0
    }
4995
38
    if (MCInst_getNumOperands(MI) == 4 &&
4996
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4997
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4998
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4999
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5000
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5001
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5002
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5003
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5004
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5005
0
      AsmString = "fmovque $\x02, $\x03, $\x01";
5006
0
      break;
5007
0
    }
5008
38
    if (MCInst_getNumOperands(MI) == 4 &&
5009
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5010
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5011
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5012
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5013
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5014
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5015
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5016
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5017
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5018
0
      AsmString = "fmovqge $\x02, $\x03, $\x01";
5019
0
      break;
5020
0
    }
5021
38
    if (MCInst_getNumOperands(MI) == 4 &&
5022
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5023
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5024
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5025
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5026
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5027
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5028
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5029
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5030
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5031
0
      AsmString = "fmovquge $\x02, $\x03, $\x01";
5032
0
      break;
5033
0
    }
5034
38
    if (MCInst_getNumOperands(MI) == 4 &&
5035
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5036
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5037
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5038
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5039
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5040
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5041
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5042
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5043
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5044
0
      AsmString = "fmovqle $\x02, $\x03, $\x01";
5045
0
      break;
5046
0
    }
5047
38
    if (MCInst_getNumOperands(MI) == 4 &&
5048
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5049
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5050
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5051
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5052
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5053
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5054
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5055
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5056
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5057
0
      AsmString = "fmovqule $\x02, $\x03, $\x01";
5058
0
      break;
5059
0
    }
5060
38
    if (MCInst_getNumOperands(MI) == 4 &&
5061
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5062
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5063
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5064
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5065
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5066
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5067
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5068
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5069
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5070
0
      AsmString = "fmovqo $\x02, $\x03, $\x01";
5071
0
      break;
5072
0
    }
5073
38
    return NULL;
5074
84
  case SP_V9FMOVS_FCC:
5075
84
    if (MCInst_getNumOperands(MI) == 4 &&
5076
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5077
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5078
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5079
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5080
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5081
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5082
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5083
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5084
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5085
0
      AsmString = "fmovsa $\x02, $\x03, $\x01";
5086
0
      break;
5087
0
    }
5088
84
    if (MCInst_getNumOperands(MI) == 4 &&
5089
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5090
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5091
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5092
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5093
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5094
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5095
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5096
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5097
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5098
0
      AsmString = "fmovsn $\x02, $\x03, $\x01";
5099
0
      break;
5100
0
    }
5101
84
    if (MCInst_getNumOperands(MI) == 4 &&
5102
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5103
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5104
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5105
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5106
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5107
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5108
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5109
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5110
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5111
0
      AsmString = "fmovsu $\x02, $\x03, $\x01";
5112
0
      break;
5113
0
    }
5114
84
    if (MCInst_getNumOperands(MI) == 4 &&
5115
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5116
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5117
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5118
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5119
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5120
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5121
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5122
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5123
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5124
0
      AsmString = "fmovsg $\x02, $\x03, $\x01";
5125
0
      break;
5126
0
    }
5127
84
    if (MCInst_getNumOperands(MI) == 4 &&
5128
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5129
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5130
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5131
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5132
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5133
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5134
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5135
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5136
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5137
0
      AsmString = "fmovsug $\x02, $\x03, $\x01";
5138
0
      break;
5139
0
    }
5140
84
    if (MCInst_getNumOperands(MI) == 4 &&
5141
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5142
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5143
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5144
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5145
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5146
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5147
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5148
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5149
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5150
0
      AsmString = "fmovsl $\x02, $\x03, $\x01";
5151
0
      break;
5152
0
    }
5153
84
    if (MCInst_getNumOperands(MI) == 4 &&
5154
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5155
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5156
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5157
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5158
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5159
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5160
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5161
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5162
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5163
0
      AsmString = "fmovsul $\x02, $\x03, $\x01";
5164
0
      break;
5165
0
    }
5166
84
    if (MCInst_getNumOperands(MI) == 4 &&
5167
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5168
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5169
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5170
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5171
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5172
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5173
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5174
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5175
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5176
0
      AsmString = "fmovslg $\x02, $\x03, $\x01";
5177
0
      break;
5178
0
    }
5179
84
    if (MCInst_getNumOperands(MI) == 4 &&
5180
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5181
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5182
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5183
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5184
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5185
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5186
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5187
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5188
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5189
0
      AsmString = "fmovsne $\x02, $\x03, $\x01";
5190
0
      break;
5191
0
    }
5192
84
    if (MCInst_getNumOperands(MI) == 4 &&
5193
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5194
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5195
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5196
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5197
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5198
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5199
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5200
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5201
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5202
0
      AsmString = "fmovse $\x02, $\x03, $\x01";
5203
0
      break;
5204
0
    }
5205
84
    if (MCInst_getNumOperands(MI) == 4 &&
5206
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5207
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5208
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5209
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5210
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5211
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5212
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5213
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5214
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5215
0
      AsmString = "fmovsue $\x02, $\x03, $\x01";
5216
0
      break;
5217
0
    }
5218
84
    if (MCInst_getNumOperands(MI) == 4 &&
5219
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5220
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5221
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5222
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5223
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5224
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5225
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5226
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5227
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5228
0
      AsmString = "fmovsge $\x02, $\x03, $\x01";
5229
0
      break;
5230
0
    }
5231
84
    if (MCInst_getNumOperands(MI) == 4 &&
5232
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5233
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5234
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5235
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5236
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5237
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5238
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5239
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5240
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5241
0
      AsmString = "fmovsuge $\x02, $\x03, $\x01";
5242
0
      break;
5243
0
    }
5244
84
    if (MCInst_getNumOperands(MI) == 4 &&
5245
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5246
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5247
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5248
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5249
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5250
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5251
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5252
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5253
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5254
0
      AsmString = "fmovsle $\x02, $\x03, $\x01";
5255
0
      break;
5256
0
    }
5257
84
    if (MCInst_getNumOperands(MI) == 4 &&
5258
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5259
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5260
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5261
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5262
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5263
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5264
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5265
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5266
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5267
0
      AsmString = "fmovsule $\x02, $\x03, $\x01";
5268
0
      break;
5269
0
    }
5270
84
    if (MCInst_getNumOperands(MI) == 4 &&
5271
84
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5272
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5273
84
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5274
84
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5275
84
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5276
84
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5277
84
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5278
84
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5279
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5280
0
      AsmString = "fmovso $\x02, $\x03, $\x01";
5281
0
      break;
5282
0
    }
5283
84
    return NULL;
5284
211
  case SP_V9MOVFCCri:
5285
211
    if (MCInst_getNumOperands(MI) == 4 &&
5286
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5287
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5288
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5289
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5290
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5291
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5292
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5293
0
      AsmString = "mova $\x02, $\x03, $\x01";
5294
0
      break;
5295
0
    }
5296
211
    if (MCInst_getNumOperands(MI) == 4 &&
5297
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5298
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5299
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5300
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5301
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5302
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5303
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5304
0
      AsmString = "movn $\x02, $\x03, $\x01";
5305
0
      break;
5306
0
    }
5307
211
    if (MCInst_getNumOperands(MI) == 4 &&
5308
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5309
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5310
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5311
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5312
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5313
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5314
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5315
0
      AsmString = "movu $\x02, $\x03, $\x01";
5316
0
      break;
5317
0
    }
5318
211
    if (MCInst_getNumOperands(MI) == 4 &&
5319
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5320
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5321
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5322
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5323
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5324
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5325
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5326
0
      AsmString = "movg $\x02, $\x03, $\x01";
5327
0
      break;
5328
0
    }
5329
211
    if (MCInst_getNumOperands(MI) == 4 &&
5330
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5331
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5332
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5333
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5334
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5335
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5336
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5337
0
      AsmString = "movug $\x02, $\x03, $\x01";
5338
0
      break;
5339
0
    }
5340
211
    if (MCInst_getNumOperands(MI) == 4 &&
5341
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5342
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5343
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5344
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5345
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5346
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5347
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5348
0
      AsmString = "movl $\x02, $\x03, $\x01";
5349
0
      break;
5350
0
    }
5351
211
    if (MCInst_getNumOperands(MI) == 4 &&
5352
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5353
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5354
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5355
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5356
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5357
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5358
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5359
0
      AsmString = "movul $\x02, $\x03, $\x01";
5360
0
      break;
5361
0
    }
5362
211
    if (MCInst_getNumOperands(MI) == 4 &&
5363
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5364
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5365
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5366
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5367
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5368
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5369
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5370
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5371
0
      break;
5372
0
    }
5373
211
    if (MCInst_getNumOperands(MI) == 4 &&
5374
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5375
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5376
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5377
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5378
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5379
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5380
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5381
0
      AsmString = "movne $\x02, $\x03, $\x01";
5382
0
      break;
5383
0
    }
5384
211
    if (MCInst_getNumOperands(MI) == 4 &&
5385
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5386
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5387
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5388
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5389
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5390
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5391
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5392
0
      AsmString = "move $\x02, $\x03, $\x01";
5393
0
      break;
5394
0
    }
5395
211
    if (MCInst_getNumOperands(MI) == 4 &&
5396
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5397
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5398
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5399
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5400
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5401
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5402
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5403
0
      AsmString = "movue $\x02, $\x03, $\x01";
5404
0
      break;
5405
0
    }
5406
211
    if (MCInst_getNumOperands(MI) == 4 &&
5407
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5408
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5409
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5410
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5411
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5412
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5413
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5414
0
      AsmString = "movge $\x02, $\x03, $\x01";
5415
0
      break;
5416
0
    }
5417
211
    if (MCInst_getNumOperands(MI) == 4 &&
5418
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5419
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5420
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5421
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5422
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5423
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5424
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5425
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5426
0
      break;
5427
0
    }
5428
211
    if (MCInst_getNumOperands(MI) == 4 &&
5429
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5430
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5431
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5432
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5433
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5434
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5435
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5436
0
      AsmString = "movle $\x02, $\x03, $\x01";
5437
0
      break;
5438
0
    }
5439
211
    if (MCInst_getNumOperands(MI) == 4 &&
5440
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5441
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5442
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5443
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5444
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5445
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5446
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5447
0
      AsmString = "movule $\x02, $\x03, $\x01";
5448
0
      break;
5449
0
    }
5450
211
    if (MCInst_getNumOperands(MI) == 4 &&
5451
211
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5452
211
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5453
211
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5454
211
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5455
211
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5456
211
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5457
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5458
0
      AsmString = "movo $\x02, $\x03, $\x01";
5459
0
      break;
5460
0
    }
5461
211
    return NULL;
5462
303
  case SP_V9MOVFCCrr:
5463
303
    if (MCInst_getNumOperands(MI) == 4 &&
5464
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5465
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5466
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5467
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5468
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5469
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5470
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5471
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5472
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5473
0
      AsmString = "mova $\x02, $\x03, $\x01";
5474
0
      break;
5475
0
    }
5476
303
    if (MCInst_getNumOperands(MI) == 4 &&
5477
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5478
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5479
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5480
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5481
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5482
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5483
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5484
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5485
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5486
0
      AsmString = "movn $\x02, $\x03, $\x01";
5487
0
      break;
5488
0
    }
5489
303
    if (MCInst_getNumOperands(MI) == 4 &&
5490
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5491
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5492
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5493
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5494
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5495
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5496
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5497
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5498
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5499
0
      AsmString = "movu $\x02, $\x03, $\x01";
5500
0
      break;
5501
0
    }
5502
303
    if (MCInst_getNumOperands(MI) == 4 &&
5503
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5504
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5505
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5506
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5507
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5508
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5509
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5510
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5511
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5512
0
      AsmString = "movg $\x02, $\x03, $\x01";
5513
0
      break;
5514
0
    }
5515
303
    if (MCInst_getNumOperands(MI) == 4 &&
5516
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5517
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5518
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5519
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5520
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5521
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5522
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5523
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5524
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5525
0
      AsmString = "movug $\x02, $\x03, $\x01";
5526
0
      break;
5527
0
    }
5528
303
    if (MCInst_getNumOperands(MI) == 4 &&
5529
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5530
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5531
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5532
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5533
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5534
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5535
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5536
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5537
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5538
0
      AsmString = "movl $\x02, $\x03, $\x01";
5539
0
      break;
5540
0
    }
5541
303
    if (MCInst_getNumOperands(MI) == 4 &&
5542
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5543
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5544
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5545
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5546
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5547
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5548
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5549
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5550
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5551
0
      AsmString = "movul $\x02, $\x03, $\x01";
5552
0
      break;
5553
0
    }
5554
303
    if (MCInst_getNumOperands(MI) == 4 &&
5555
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5556
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5557
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5558
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5559
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5560
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5561
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5562
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5563
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5564
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5565
0
      break;
5566
0
    }
5567
303
    if (MCInst_getNumOperands(MI) == 4 &&
5568
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5569
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5570
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5571
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5572
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5573
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5574
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5575
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5576
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5577
0
      AsmString = "movne $\x02, $\x03, $\x01";
5578
0
      break;
5579
0
    }
5580
303
    if (MCInst_getNumOperands(MI) == 4 &&
5581
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5582
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5583
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5584
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5585
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5586
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5587
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5588
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5589
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5590
0
      AsmString = "move $\x02, $\x03, $\x01";
5591
0
      break;
5592
0
    }
5593
303
    if (MCInst_getNumOperands(MI) == 4 &&
5594
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5595
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5596
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5597
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5598
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5599
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5600
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5601
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5602
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5603
0
      AsmString = "movue $\x02, $\x03, $\x01";
5604
0
      break;
5605
0
    }
5606
303
    if (MCInst_getNumOperands(MI) == 4 &&
5607
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5608
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5609
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5610
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5611
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5612
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5613
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5614
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5615
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5616
0
      AsmString = "movge $\x02, $\x03, $\x01";
5617
0
      break;
5618
0
    }
5619
303
    if (MCInst_getNumOperands(MI) == 4 &&
5620
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5621
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5622
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5623
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5624
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5625
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5626
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5627
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5628
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5629
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5630
0
      break;
5631
0
    }
5632
303
    if (MCInst_getNumOperands(MI) == 4 &&
5633
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5634
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5635
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5636
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5637
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5638
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5639
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5640
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5641
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5642
0
      AsmString = "movle $\x02, $\x03, $\x01";
5643
0
      break;
5644
0
    }
5645
303
    if (MCInst_getNumOperands(MI) == 4 &&
5646
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5647
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5648
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5649
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5650
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5651
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5652
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5653
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5654
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5655
0
      AsmString = "movule $\x02, $\x03, $\x01";
5656
0
      break;
5657
0
    }
5658
303
    if (MCInst_getNumOperands(MI) == 4 &&
5659
303
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5660
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5661
303
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5662
303
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5663
303
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5664
303
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5665
303
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5666
303
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5667
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5668
0
      AsmString = "movo $\x02, $\x03, $\x01";
5669
0
      break;
5670
0
    }
5671
303
    return NULL;
5672
51.5k
  }
5673
5674
19.9k
  tmp = cs_strdup(AsmString);
5675
19.9k
  AsmMnem = tmp;
5676
127k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5677
127k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
5678
19.8k
      *AsmOps = '\0';
5679
19.8k
      AsmOps++;
5680
19.8k
      break;
5681
19.8k
    }
5682
127k
  }
5683
19.9k
  SStream_concat0(OS, AsmMnem);
5684
19.9k
  if (*AsmOps) {
5685
19.8k
    SStream_concat0(OS, "\t");
5686
19.8k
    if (strstr(AsmOps, "icc"))
5687
4.36k
      Sparc_addReg(MI, SPARC_REG_ICC);
5688
19.8k
    if (strstr(AsmOps, "xcc"))
5689
6.77k
      Sparc_addReg(MI, SPARC_REG_XCC);
5690
140k
    for (c = AsmOps; *c; c++) {
5691
120k
      if (*c == '$') {
5692
29.5k
        c += 1;
5693
29.5k
        if (*c == (char)0xff) {
5694
0
          c += 1;
5695
0
          OpIdx = *c - 1;
5696
0
          c += 1;
5697
0
          PrintMethodIdx = *c - 1;
5698
0
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5699
0
        } else
5700
29.5k
          printOperand(MI, *c - 1, OS);
5701
90.8k
      } else {
5702
90.8k
        SStream_concat(OS, "%c", *c);
5703
90.8k
      }
5704
120k
    }
5705
19.8k
  }
5706
19.9k
  return tmp;
5707
51.5k
}
5708
5709
#endif // PRINT_ALIAS_INSTR