/src/capstonenext/arch/RISCV/RISCVInstPrinter.c
Line | Count | Source (jump to first uncovered line) |
1 | | //===-- RISCVInstPrinter.cpp - Convert RISCV MCInst to asm syntax ---------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This class prints an RISCV MCInst to a .s file. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #ifdef CAPSTONE_HAS_RISCV |
15 | | |
16 | | #include <stdio.h> // DEBUG |
17 | | #include <stdlib.h> |
18 | | #include <string.h> |
19 | | #include <capstone/platform.h> |
20 | | |
21 | | #include "RISCVInstPrinter.h" |
22 | | #include "RISCVBaseInfo.h" |
23 | | #include "../../MCInst.h" |
24 | | #include "../../SStream.h" |
25 | | #include "../../MCRegisterInfo.h" |
26 | | #include "../../utils.h" |
27 | | #include "../../Mapping.h" |
28 | | #include "RISCVMapping.h" |
29 | | |
30 | | //#include "RISCVDisassembler.h" |
31 | | |
32 | | #define GET_REGINFO_ENUM |
33 | | #define GET_REGINFO_MC_DESC |
34 | | #include "RISCVGenRegisterInfo.inc" |
35 | | #define GET_INSTRINFO_ENUM |
36 | | #include "RISCVGenInstrInfo.inc" |
37 | | |
38 | | // Autogenerated by tblgen. |
39 | | static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI); |
40 | | static bool printAliasInstr(MCInst *MI, SStream *OS, void *info); |
41 | | static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); |
42 | | static void printFenceArg(MCInst *MI, unsigned OpNo, SStream *O); |
43 | | static void printCSRSystemRegister(MCInst*, unsigned, SStream *); |
44 | | static void printFRMArg(MCInst *MI, unsigned OpNo, SStream *O); |
45 | | static void printCustomAliasOperand( MCInst *, unsigned, unsigned, SStream *); |
46 | | /// getRegisterName - This method is automatically generated by tblgen |
47 | | /// from the register set description. This returns the assembler name |
48 | | /// for the specified register. |
49 | | static const char *getRegisterName(unsigned RegNo, unsigned AltIdx); |
50 | | |
51 | | // Include the auto-generated portion of the assembly writer. |
52 | | #define PRINT_ALIAS_INSTR |
53 | | #include "RISCVGenAsmWriter.inc" |
54 | | |
55 | | |
56 | | static void fixDetailOfEffectiveAddr(MCInst *MI) |
57 | 10.7k | { |
58 | | // Operands for load and store instructions in RISCV vary widely |
59 | 10.7k | unsigned id = MI->flat_insn->id; |
60 | 10.7k | unsigned reg = 0; |
61 | 10.7k | int64_t imm = 0; |
62 | 10.7k | uint8_t access = 0; |
63 | | |
64 | 10.7k | switch (id) { |
65 | 0 | case RISCV_INS_C_FLD: |
66 | 0 | case RISCV_INS_C_LW: |
67 | 0 | case RISCV_INS_C_FLW: |
68 | 0 | case RISCV_INS_C_LD: |
69 | 0 | case RISCV_INS_C_FSD: |
70 | 0 | case RISCV_INS_C_SW: |
71 | 0 | case RISCV_INS_C_FSW: |
72 | 0 | case RISCV_INS_C_SD: |
73 | 0 | case RISCV_INS_C_FLDSP: |
74 | 0 | case RISCV_INS_C_LWSP: |
75 | 0 | case RISCV_INS_C_FLWSP: |
76 | 0 | case RISCV_INS_C_LDSP: |
77 | 0 | case RISCV_INS_C_FSDSP: |
78 | 0 | case RISCV_INS_C_SWSP: |
79 | 0 | case RISCV_INS_C_FSWSP: |
80 | 0 | case RISCV_INS_C_SDSP: |
81 | 100 | case RISCV_INS_FLW: |
82 | 358 | case RISCV_INS_FSW: |
83 | 426 | case RISCV_INS_FLD: |
84 | 448 | case RISCV_INS_FSD: |
85 | 684 | case RISCV_INS_LB: |
86 | 832 | case RISCV_INS_LBU: |
87 | 893 | case RISCV_INS_LD: |
88 | 1.74k | case RISCV_INS_LH: |
89 | 1.85k | case RISCV_INS_LHU: |
90 | 1.96k | case RISCV_INS_LW: |
91 | 2.04k | case RISCV_INS_LWU: |
92 | 2.15k | case RISCV_INS_SB: |
93 | 2.61k | case RISCV_INS_SD: |
94 | 2.75k | case RISCV_INS_SH: |
95 | 3.17k | case RISCV_INS_SW: { |
96 | 3.17k | CS_ASSERT(3 == MI->flat_insn->detail->riscv.op_count); |
97 | 3.17k | CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -3)->type); |
98 | 3.17k | CS_ASSERT(RISCV_OP_IMM == RISCV_get_detail_op(MI, -2)->type); |
99 | 3.17k | CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -1)->type); |
100 | | |
101 | 3.17k | imm = RISCV_get_detail_op(MI, -2)->imm; |
102 | 3.17k | reg = RISCV_get_detail_op(MI, -1)->reg; |
103 | 3.17k | access = RISCV_get_detail_op(MI, -1)->access; |
104 | | |
105 | 3.17k | RISCV_get_detail_op(MI, -2)->type = RISCV_OP_MEM; |
106 | 3.17k | RISCV_get_detail_op(MI, -2)->mem.base = reg; |
107 | 3.17k | RISCV_get_detail_op(MI, -2)->mem.disp = imm; |
108 | 3.17k | RISCV_get_detail_op(MI, -2)->access = access; |
109 | | |
110 | 3.17k | RISCV_dec_op_count(MI); |
111 | | |
112 | 3.17k | break; |
113 | 2.75k | } |
114 | 35 | case RISCV_INS_LR_W: |
115 | 45 | case RISCV_INS_LR_W_AQ: |
116 | 87 | case RISCV_INS_LR_W_AQ_RL: |
117 | 97 | case RISCV_INS_LR_W_RL: |
118 | 192 | case RISCV_INS_LR_D: |
119 | 202 | case RISCV_INS_LR_D_AQ: |
120 | 437 | case RISCV_INS_LR_D_AQ_RL: |
121 | 456 | case RISCV_INS_LR_D_RL: { |
122 | 456 | CS_ASSERT(2 == MI->flat_insn->detail->riscv.op_count); |
123 | 456 | CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -1)->type); |
124 | 456 | CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -2)->type); |
125 | | |
126 | 456 | reg = RISCV_get_detail_op(MI, -1)->reg; |
127 | | |
128 | 456 | RISCV_get_detail_op(MI, -1)->type = RISCV_OP_MEM; |
129 | 456 | RISCV_get_detail_op(MI, -1)->mem.base = reg; |
130 | 456 | RISCV_get_detail_op(MI, -1)->mem.disp = 0; |
131 | | |
132 | 456 | break; |
133 | 437 | } |
134 | 209 | case RISCV_INS_SC_W: |
135 | 227 | case RISCV_INS_SC_W_AQ: |
136 | 238 | case RISCV_INS_SC_W_AQ_RL: |
137 | 248 | case RISCV_INS_SC_W_RL: |
138 | 317 | case RISCV_INS_SC_D: |
139 | 341 | case RISCV_INS_SC_D_AQ: |
140 | 406 | case RISCV_INS_SC_D_AQ_RL: |
141 | 472 | case RISCV_INS_SC_D_RL: |
142 | 497 | case RISCV_INS_AMOADD_D: |
143 | 515 | case RISCV_INS_AMOADD_D_AQ: |
144 | 1.12k | case RISCV_INS_AMOADD_D_AQ_RL: |
145 | 1.29k | case RISCV_INS_AMOADD_D_RL: |
146 | 1.34k | case RISCV_INS_AMOADD_W: |
147 | 1.36k | case RISCV_INS_AMOADD_W_AQ: |
148 | 1.42k | case RISCV_INS_AMOADD_W_AQ_RL: |
149 | 1.86k | case RISCV_INS_AMOADD_W_RL: |
150 | 2.05k | case RISCV_INS_AMOAND_D: |
151 | 2.08k | case RISCV_INS_AMOAND_D_AQ: |
152 | 2.12k | case RISCV_INS_AMOAND_D_AQ_RL: |
153 | 2.14k | case RISCV_INS_AMOAND_D_RL: |
154 | 2.15k | case RISCV_INS_AMOAND_W: |
155 | 2.18k | case RISCV_INS_AMOAND_W_AQ: |
156 | 2.22k | case RISCV_INS_AMOAND_W_AQ_RL: |
157 | 2.24k | case RISCV_INS_AMOAND_W_RL: |
158 | 2.27k | case RISCV_INS_AMOMAXU_D: |
159 | 2.30k | case RISCV_INS_AMOMAXU_D_AQ: |
160 | 2.34k | case RISCV_INS_AMOMAXU_D_AQ_RL: |
161 | 2.35k | case RISCV_INS_AMOMAXU_D_RL: |
162 | 2.36k | case RISCV_INS_AMOMAXU_W: |
163 | 2.37k | case RISCV_INS_AMOMAXU_W_AQ: |
164 | 2.44k | case RISCV_INS_AMOMAXU_W_AQ_RL: |
165 | 2.45k | case RISCV_INS_AMOMAXU_W_RL: |
166 | 2.46k | case RISCV_INS_AMOMAX_D: |
167 | 2.53k | case RISCV_INS_AMOMAX_D_AQ: |
168 | 3.00k | case RISCV_INS_AMOMAX_D_AQ_RL: |
169 | 3.02k | case RISCV_INS_AMOMAX_D_RL: |
170 | 3.05k | case RISCV_INS_AMOMAX_W: |
171 | 3.12k | case RISCV_INS_AMOMAX_W_AQ: |
172 | 3.15k | case RISCV_INS_AMOMAX_W_AQ_RL: |
173 | 3.36k | case RISCV_INS_AMOMAX_W_RL: |
174 | 3.61k | case RISCV_INS_AMOMINU_D: |
175 | 3.64k | case RISCV_INS_AMOMINU_D_AQ: |
176 | 3.76k | case RISCV_INS_AMOMINU_D_AQ_RL: |
177 | 4.19k | case RISCV_INS_AMOMINU_D_RL: |
178 | 4.59k | case RISCV_INS_AMOMINU_W: |
179 | 4.62k | case RISCV_INS_AMOMINU_W_AQ: |
180 | 4.76k | case RISCV_INS_AMOMINU_W_AQ_RL: |
181 | 4.79k | case RISCV_INS_AMOMINU_W_RL: |
182 | 4.94k | case RISCV_INS_AMOMIN_D: |
183 | 4.97k | case RISCV_INS_AMOMIN_D_AQ: |
184 | 4.98k | case RISCV_INS_AMOMIN_D_AQ_RL: |
185 | 5.00k | case RISCV_INS_AMOMIN_D_RL: |
186 | 5.04k | case RISCV_INS_AMOMIN_W: |
187 | 5.11k | case RISCV_INS_AMOMIN_W_AQ: |
188 | 5.14k | case RISCV_INS_AMOMIN_W_AQ_RL: |
189 | 5.18k | case RISCV_INS_AMOMIN_W_RL: |
190 | 5.38k | case RISCV_INS_AMOOR_D: |
191 | 5.58k | case RISCV_INS_AMOOR_D_AQ: |
192 | 5.98k | case RISCV_INS_AMOOR_D_AQ_RL: |
193 | 6.01k | case RISCV_INS_AMOOR_D_RL: |
194 | 6.02k | case RISCV_INS_AMOOR_W: |
195 | 6.10k | case RISCV_INS_AMOOR_W_AQ: |
196 | 6.34k | case RISCV_INS_AMOOR_W_AQ_RL: |
197 | 6.35k | case RISCV_INS_AMOOR_W_RL: |
198 | 6.36k | case RISCV_INS_AMOSWAP_D: |
199 | 6.39k | case RISCV_INS_AMOSWAP_D_AQ: |
200 | 6.51k | case RISCV_INS_AMOSWAP_D_AQ_RL: |
201 | 6.58k | case RISCV_INS_AMOSWAP_D_RL: |
202 | 6.59k | case RISCV_INS_AMOSWAP_W: |
203 | 6.60k | case RISCV_INS_AMOSWAP_W_AQ: |
204 | 6.64k | case RISCV_INS_AMOSWAP_W_AQ_RL: |
205 | 6.69k | case RISCV_INS_AMOSWAP_W_RL: |
206 | 6.74k | case RISCV_INS_AMOXOR_D: |
207 | 6.76k | case RISCV_INS_AMOXOR_D_AQ: |
208 | 6.79k | case RISCV_INS_AMOXOR_D_AQ_RL: |
209 | 6.81k | case RISCV_INS_AMOXOR_D_RL: |
210 | 6.84k | case RISCV_INS_AMOXOR_W: |
211 | 7.04k | case RISCV_INS_AMOXOR_W_AQ: |
212 | 7.06k | case RISCV_INS_AMOXOR_W_AQ_RL: |
213 | 7.13k | case RISCV_INS_AMOXOR_W_RL: { |
214 | 7.13k | CS_ASSERT(3 == MI->flat_insn->detail->riscv.op_count); |
215 | 7.13k | CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -3)->type); |
216 | 7.13k | CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -2)->type); |
217 | 7.13k | CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -1)->type); |
218 | | |
219 | 7.13k | reg = RISCV_get_detail_op(MI, -1)->reg; |
220 | | |
221 | 7.13k | RISCV_get_detail_op(MI, -1)->type = RISCV_OP_MEM; |
222 | 7.13k | RISCV_get_detail_op(MI, -1)->mem.base = reg; |
223 | 7.13k | RISCV_get_detail_op(MI, -1)->mem.disp = 0; |
224 | | |
225 | 7.13k | break; |
226 | 7.06k | } |
227 | 0 | default: { |
228 | 0 | CS_ASSERT(0 && "id is not a RISC-V memory instruction"); |
229 | 0 | break; |
230 | 7.06k | } |
231 | 10.7k | } |
232 | 10.7k | return; |
233 | 10.7k | } |
234 | | |
235 | | |
236 | | //void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O, |
237 | | // StringRef Annot, const MCSubtargetInfo &STI) |
238 | | void RISCV_printInst(MCInst *MI, SStream *O, void *info) |
239 | 72.1k | { |
240 | 72.1k | MCRegisterInfo *MRI = (MCRegisterInfo *) info; |
241 | | //bool Res = false; |
242 | | //MCInst *NewMI = MI; |
243 | | // TODO: RISCV compressd instructions. |
244 | | //MCInst UncompressedMI; |
245 | | //if (!NoAliases) |
246 | | //Res = uncompressInst(UncompressedMI, *MI, MRI, STI); |
247 | | //if (Res) |
248 | | //NewMI = const_cast<MCInst *>(&UncompressedMI); |
249 | 72.1k | if (/*NoAliases ||*/ !printAliasInstr(MI, O, info)) |
250 | 57.7k | printInstruction(MI, O, MRI); |
251 | | //printAnnotation(O, Annot); |
252 | | // fix load/store type insttuction |
253 | 72.1k | if (MI->csh->detail_opt && |
254 | 72.1k | MI->flat_insn->detail->riscv.need_effective_addr) |
255 | 10.7k | fixDetailOfEffectiveAddr(MI); |
256 | | |
257 | 72.1k | return; |
258 | 72.1k | } |
259 | | |
260 | | static void printRegName(SStream *OS, unsigned RegNo) |
261 | 134k | { |
262 | 134k | SStream_concat0(OS, getRegisterName(RegNo, RISCV_ABIRegAltName)); |
263 | 134k | } |
264 | | |
265 | | /** |
266 | | void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, |
267 | | raw_ostream &O, const char *Modifier) |
268 | | */ |
269 | | static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) |
270 | 156k | { |
271 | 156k | unsigned reg; |
272 | 156k | int64_t Imm = 0; |
273 | | |
274 | 156k | RISCV_add_cs_detail(MI, OpNo); |
275 | | |
276 | 156k | MCOperand *MO = MCInst_getOperand(MI, OpNo); |
277 | | |
278 | 156k | if (MCOperand_isReg(MO)) { |
279 | 134k | reg = MCOperand_getReg(MO); |
280 | 134k | printRegName(O, reg); |
281 | 134k | } else { |
282 | 21.8k | CS_ASSERT(MCOperand_isImm(MO) && "Unknown operand kind in printOperand"); |
283 | 21.8k | Imm = MCOperand_getImm(MO); |
284 | 21.8k | if (Imm >= 0) { |
285 | 19.9k | if (Imm > HEX_THRESHOLD) |
286 | 11.8k | SStream_concat(O, "0x%" PRIx64, Imm); |
287 | 8.17k | else |
288 | 8.17k | SStream_concat(O, "%" PRIu64, Imm); |
289 | 19.9k | } else { |
290 | 1.87k | if (Imm < -HEX_THRESHOLD) |
291 | 1.83k | SStream_concat(O, "-0x%" PRIx64, -Imm); |
292 | 47 | else |
293 | 47 | SStream_concat(O, "-%" PRIu64, -Imm); |
294 | 1.87k | } |
295 | 21.8k | } |
296 | | |
297 | | //CS_ASSERT(MO.isExpr() && "Unknown operand kind in printOperand"); |
298 | | |
299 | 156k | return; |
300 | 156k | } |
301 | | |
302 | | static const char *getCSRSystemRegisterName(unsigned CsrNo) |
303 | 35.2k | { |
304 | 35.2k | switch (CsrNo) { |
305 | | /* |
306 | | * From RISC-V Privileged Architecture Version 1.10. |
307 | | * In the same order as Table 2.5. |
308 | | */ |
309 | 505 | case 0x0000: return "ustatus"; |
310 | 38 | case 0x0004: return "uie"; |
311 | 151 | case 0x0005: return "utvec"; |
312 | | |
313 | 35 | case 0x0040: return "uscratch"; |
314 | 71 | case 0x0041: return "uepc"; |
315 | 128 | case 0x0042: return "ucause"; |
316 | 91 | case 0x0043: return "utval"; |
317 | 71 | case 0x0044: return "uip"; |
318 | | |
319 | 231 | case 0x0001: return "fflags"; |
320 | 251 | case 0x0002: return "frm"; |
321 | 34 | case 0x0003: return "fcsr"; |
322 | | |
323 | 2.03k | case 0x0c00: return "cycle"; |
324 | 1.51k | case 0x0c01: return "time"; |
325 | 49 | case 0x0c02: return "instret"; |
326 | 63 | case 0x0c03: return "hpmcounter3"; |
327 | 33 | case 0x0c04: return "hpmcounter4"; |
328 | 1.20k | case 0x0c05: return "hpmcounter5"; |
329 | 177 | case 0x0c06: return "hpmcounter6"; |
330 | 184 | case 0x0c07: return "hpmcounter7"; |
331 | 369 | case 0x0c08: return "hpmcounter8"; |
332 | 552 | case 0x0c09: return "hpmcounter9"; |
333 | 34 | case 0x0c0a: return "hpmcounter10"; |
334 | 39 | case 0x0c0b: return "hpmcounter11"; |
335 | 40 | case 0x0c0c: return "hpmcounter12"; |
336 | 334 | case 0x0c0d: return "hpmcounter13"; |
337 | 166 | case 0x0c0e: return "hpmcounter14"; |
338 | 45 | case 0x0c0f: return "hpmcounter15"; |
339 | 115 | case 0x0c10: return "hpmcounter16"; |
340 | 250 | case 0x0c11: return "hpmcounter17"; |
341 | 74 | case 0x0c12: return "hpmcounter18"; |
342 | 70 | case 0x0c13: return "hpmcounter19"; |
343 | 140 | case 0x0c14: return "hpmcounter20"; |
344 | 51 | case 0x0c15: return "hpmcounter21"; |
345 | 14 | case 0x0c16: return "hpmcounter22"; |
346 | 67 | case 0x0c17: return "hpmcounter23"; |
347 | 881 | case 0x0c18: return "hpmcounter24"; |
348 | 119 | case 0x0c19: return "hpmcounter25"; |
349 | 36 | case 0x0c1a: return "hpmcounter26"; |
350 | 232 | case 0x0c1b: return "hpmcounter27"; |
351 | 24 | case 0x0c1c: return "hpmcounter28"; |
352 | 10 | case 0x0c1d: return "hpmcounter29"; |
353 | 490 | case 0x0c1e: return "hpmcounter30"; |
354 | 11 | case 0x0c1f: return "hpmcounter31"; |
355 | 16 | case 0x0c80: return "cycleh"; |
356 | 128 | case 0x0c81: return "timeh"; |
357 | 452 | case 0x0c82: return "instreth"; |
358 | 77 | case 0x0c83: return "hpmcounter3h"; |
359 | 41 | case 0x0c84: return "hpmcounter4h"; |
360 | 61 | case 0x0c85: return "hpmcounter5h"; |
361 | 84 | case 0x0c86: return "hpmcounter6h"; |
362 | 81 | case 0x0c87: return "hpmcounter7h"; |
363 | 102 | case 0x0c88: return "hpmcounter8h"; |
364 | 34 | case 0x0c89: return "hpmcounter9h"; |
365 | 339 | case 0x0c8a: return "hpmcounter10h"; |
366 | 39 | case 0x0c8b: return "hpmcounter11h"; |
367 | 22 | case 0x0c8c: return "hpmcounter12h"; |
368 | 113 | case 0x0c8d: return "hpmcounter13h"; |
369 | 64 | case 0x0c8e: return "hpmcounter14h"; |
370 | 19 | case 0x0c8f: return "hpmcounter15h"; |
371 | 408 | case 0x0c90: return "hpmcounter16h"; |
372 | 263 | case 0x0c91: return "hpmcounter17h"; |
373 | 118 | case 0x0c92: return "hpmcounter18h"; |
374 | 174 | case 0x0c93: return "hpmcounter19h"; |
375 | 129 | case 0x0c94: return "hpmcounter20h"; |
376 | 139 | case 0x0c95: return "hpmcounter21h"; |
377 | 193 | case 0x0c96: return "hpmcounter22h"; |
378 | 11 | case 0x0c97: return "hpmcounter23h"; |
379 | 43 | case 0x0c98: return "hpmcounter24h"; |
380 | 20 | case 0x0c99: return "hpmcounter25h"; |
381 | 276 | case 0x0c9a: return "hpmcounter26h"; |
382 | 11 | case 0x0c9b: return "hpmcounter27h"; |
383 | 15 | case 0x0c9c: return "hpmcounter28h"; |
384 | 198 | case 0x0c9d: return "hpmcounter29h"; |
385 | 44 | case 0x0c9e: return "hpmcounter30h"; |
386 | 152 | case 0x0c9f: return "hpmcounter31h"; |
387 | | |
388 | 10 | case 0x0100: return "sstatus"; |
389 | 20 | case 0x0102: return "sedeleg"; |
390 | 73 | case 0x0103: return "sideleg"; |
391 | 200 | case 0x0104: return "sie"; |
392 | 27 | case 0x0105: return "stvec"; |
393 | 18 | case 0x0106: return "scounteren"; |
394 | | |
395 | 19 | case 0x0140: return "sscratch"; |
396 | 86 | case 0x0141: return "sepc"; |
397 | 68 | case 0x0142: return "scause"; |
398 | 34 | case 0x0143: return "stval"; |
399 | 18 | case 0x0144: return "sip"; |
400 | | |
401 | 21 | case 0x0180: return "satp"; |
402 | | |
403 | 34 | case 0x0f11: return "mvendorid"; |
404 | 17 | case 0x0f12: return "marchid"; |
405 | 36 | case 0x0f13: return "mimpid"; |
406 | 36 | case 0x0f14: return "mhartid"; |
407 | | |
408 | 36 | case 0x0300: return "mstatus"; |
409 | 15 | case 0x0301: return "misa"; |
410 | 12 | case 0x0302: return "medeleg"; |
411 | 21 | case 0x0303: return "mideleg"; |
412 | 70 | case 0x0304: return "mie"; |
413 | 289 | case 0x0305: return "mtvec"; |
414 | 19 | case 0x0306: return "mcounteren"; |
415 | | |
416 | 148 | case 0x0340: return "mscratch"; |
417 | 992 | case 0x0341: return "mepc"; |
418 | 71 | case 0x0342: return "mcause"; |
419 | 178 | case 0x0343: return "mtval"; |
420 | 70 | case 0x0344: return "mip"; |
421 | | |
422 | 12 | case 0x03a0: return "pmpcfg0"; |
423 | 10 | case 0x03a1: return "pmpcfg1"; |
424 | 186 | case 0x03a2: return "pmpcfg2"; |
425 | 17 | case 0x03a3: return "pmpcfg3"; |
426 | 75 | case 0x03b0: return "pmpaddr0"; |
427 | 16 | case 0x03b1: return "pmpaddr1"; |
428 | 296 | case 0x03b2: return "pmpaddr2"; |
429 | 48 | case 0x03b3: return "pmpaddr3"; |
430 | 37 | case 0x03b4: return "pmpaddr4"; |
431 | 38 | case 0x03b5: return "pmpaddr5"; |
432 | 39 | case 0x03b6: return "pmpaddr6"; |
433 | 139 | case 0x03b7: return "pmpaddr7"; |
434 | 47 | case 0x03b8: return "pmpaddr8"; |
435 | 19 | case 0x03b9: return "pmpaddr9"; |
436 | 41 | case 0x03ba: return "pmpaddr10"; |
437 | 10 | case 0x03bb: return "pmpaddr11"; |
438 | 10 | case 0x03bc: return "pmpaddr12"; |
439 | 42 | case 0x03bd: return "pmpaddr13"; |
440 | 517 | case 0x03be: return "pmpaddr14"; |
441 | 10 | case 0x03bf: return "pmpaddr15"; |
442 | | |
443 | 465 | case 0x0b00: return "mcycle"; |
444 | 60 | case 0x0b02: return "minstret"; |
445 | 106 | case 0x0b03: return "mhpmcounter3"; |
446 | 145 | case 0x0b04: return "mhpmcounter4"; |
447 | 68 | case 0x0b05: return "mhpmcounter5"; |
448 | 11 | case 0x0b06: return "mhpmcounter6"; |
449 | 20 | case 0x0b07: return "mhpmcounter7"; |
450 | 440 | case 0x0b08: return "mhpmcounter8"; |
451 | 36 | case 0x0b09: return "mhpmcounter9"; |
452 | 292 | case 0x0b0a: return "mhpmcounter10"; |
453 | 36 | case 0x0b0b: return "mhpmcounter11"; |
454 | 528 | case 0x0b0c: return "mhpmcounter12"; |
455 | 433 | case 0x0b0d: return "mhpmcounter13"; |
456 | 111 | case 0x0b0e: return "mhpmcounter14"; |
457 | 383 | case 0x0b0f: return "mhpmcounter15"; |
458 | 27 | case 0x0b10: return "mhpmcounter16"; |
459 | 109 | case 0x0b11: return "mhpmcounter17"; |
460 | 75 | case 0x0b12: return "mhpmcounter18"; |
461 | 92 | case 0x0b13: return "mhpmcounter19"; |
462 | 18 | case 0x0b14: return "mhpmcounter20"; |
463 | 133 | case 0x0b15: return "mhpmcounter21"; |
464 | 11 | case 0x0b16: return "mhpmcounter22"; |
465 | 34 | case 0x0b17: return "mhpmcounter23"; |
466 | 10 | case 0x0b18: return "mhpmcounter24"; |
467 | 178 | case 0x0b19: return "mhpmcounter25"; |
468 | 76 | case 0x0b1a: return "mhpmcounter26"; |
469 | 460 | case 0x0b1b: return "mhpmcounter27"; |
470 | 18 | case 0x0b1c: return "mhpmcounter28"; |
471 | 10 | case 0x0b1d: return "mhpmcounter29"; |
472 | 59 | case 0x0b1e: return "mhpmcounter30"; |
473 | 124 | case 0x0b1f: return "mhpmcounter31"; |
474 | 108 | case 0x0b80: return "mcycleh"; |
475 | 21 | case 0x0b82: return "minstreth"; |
476 | 18 | case 0x0b83: return "mhpmcounter3h"; |
477 | 34 | case 0x0b84: return "mhpmcounter4h"; |
478 | 18 | case 0x0b85: return "mhpmcounter5h"; |
479 | 12 | case 0x0b86: return "mhpmcounter6h"; |
480 | 69 | case 0x0b87: return "mhpmcounter7h"; |
481 | 11 | case 0x0b88: return "mhpmcounter8h"; |
482 | 74 | case 0x0b89: return "mhpmcounter9h"; |
483 | 69 | case 0x0b8a: return "mhpmcounter10h"; |
484 | 448 | case 0x0b8b: return "mhpmcounter11h"; |
485 | 10 | case 0x0b8c: return "mhpmcounter12h"; |
486 | 20 | case 0x0b8d: return "mhpmcounter13h"; |
487 | 39 | case 0x0b8e: return "mhpmcounter14h"; |
488 | 21 | case 0x0b8f: return "mhpmcounter15h"; |
489 | 147 | case 0x0b90: return "mhpmcounter16h"; |
490 | 44 | case 0x0b91: return "mhpmcounter17h"; |
491 | 25 | case 0x0b92: return "mhpmcounter18h"; |
492 | 127 | case 0x0b93: return "mhpmcounter19h"; |
493 | 35 | case 0x0b94: return "mhpmcounter20h"; |
494 | 58 | case 0x0b95: return "mhpmcounter21h"; |
495 | 227 | case 0x0b96: return "mhpmcounter22h"; |
496 | 67 | case 0x0b97: return "mhpmcounter23h"; |
497 | 161 | case 0x0b98: return "mhpmcounter24h"; |
498 | 246 | case 0x0b99: return "mhpmcounter25h"; |
499 | 56 | case 0x0b9a: return "mhpmcounter26h"; |
500 | 220 | case 0x0b9b: return "mhpmcounter27h"; |
501 | 15 | case 0x0b9c: return "mhpmcounter28h"; |
502 | 144 | case 0x0b9d: return "mhpmcounter29h"; |
503 | 38 | case 0x0b9e: return "mhpmcounter30h"; |
504 | 15 | case 0x0b9f: return "mhpmcounter31h"; |
505 | | |
506 | 11 | case 0x0323: return "mhpmevent3"; |
507 | 66 | case 0x0324: return "mhpmevent4"; |
508 | 311 | case 0x0325: return "mhpmevent5"; |
509 | 18 | case 0x0326: return "mhpmevent6"; |
510 | 42 | case 0x0327: return "mhpmevent7"; |
511 | 83 | case 0x0328: return "mhpmevent8"; |
512 | 49 | case 0x0329: return "mhpmevent9"; |
513 | 12 | case 0x032a: return "mhpmevent10"; |
514 | 205 | case 0x032b: return "mhpmevent11"; |
515 | 10 | case 0x032c: return "mhpmevent12"; |
516 | 107 | case 0x032d: return "mhpmevent13"; |
517 | 133 | case 0x032e: return "mhpmevent14"; |
518 | 114 | case 0x032f: return "mhpmevent15"; |
519 | 115 | case 0x0330: return "mhpmevent16"; |
520 | 197 | case 0x0331: return "mhpmevent17"; |
521 | 92 | case 0x0332: return "mhpmevent18"; |
522 | 34 | case 0x0333: return "mhpmevent19"; |
523 | 102 | case 0x0334: return "mhpmevent20"; |
524 | 126 | case 0x0335: return "mhpmevent21"; |
525 | 11 | case 0x0336: return "mhpmevent22"; |
526 | 70 | case 0x0337: return "mhpmevent23"; |
527 | 54 | case 0x0338: return "mhpmevent24"; |
528 | 11 | case 0x0339: return "mhpmevent25"; |
529 | 197 | case 0x033a: return "mhpmevent26"; |
530 | 243 | case 0x033b: return "mhpmevent27"; |
531 | 21 | case 0x033c: return "mhpmevent28"; |
532 | 176 | case 0x033d: return "mhpmevent29"; |
533 | 142 | case 0x033e: return "mhpmevent30"; |
534 | 88 | case 0x033f: return "mhpmevent31"; |
535 | | |
536 | 10 | case 0x07a0: return "tselect"; |
537 | 29 | case 0x07a1: return "tdata1"; |
538 | 10 | case 0x07a2: return "tdata2"; |
539 | 10 | case 0x07a3: return "tdata3"; |
540 | | |
541 | 39 | case 0x07b0: return "dcsr"; |
542 | 36 | case 0x07b1: return "dpc"; |
543 | 67 | case 0x07b2: return "dscratch"; |
544 | 35.2k | } |
545 | 5.86k | return NULL; |
546 | 35.2k | } |
547 | | |
548 | | static void printCSRSystemRegister(MCInst *MI, unsigned OpNo, |
549 | | //const MCSubtargetInfo &STI, |
550 | | SStream *O) |
551 | 35.2k | { |
552 | 35.2k | unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)); |
553 | 35.2k | const char *Name = getCSRSystemRegisterName(Imm); |
554 | | |
555 | 35.2k | if (Name) { |
556 | 29.3k | SStream_concat0(O, Name); |
557 | 29.3k | } else { |
558 | 5.86k | SStream_concat(O, "%u", Imm); |
559 | 5.86k | } |
560 | 35.2k | } |
561 | | |
562 | | static void printFenceArg(MCInst *MI, unsigned OpNo, SStream *O) |
563 | 2.10k | { |
564 | 2.10k | unsigned FenceArg = MCOperand_getImm(MCInst_getOperand(MI, OpNo)); |
565 | | //CS_ASSERT (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg"); |
566 | | |
567 | 2.10k | if ((FenceArg & RISCVFenceField_I) != 0) |
568 | 1.07k | SStream_concat0(O, "i"); |
569 | 2.10k | if ((FenceArg & RISCVFenceField_O) != 0) |
570 | 572 | SStream_concat0(O, "o"); |
571 | 2.10k | if ((FenceArg & RISCVFenceField_R) != 0) |
572 | 1.07k | SStream_concat0(O, "r"); |
573 | 2.10k | if ((FenceArg & RISCVFenceField_W) != 0) |
574 | 994 | SStream_concat0(O, "w"); |
575 | 2.10k | if (FenceArg == 0) |
576 | 519 | SStream_concat0(O, "unknown"); |
577 | 2.10k | } |
578 | | |
579 | | static void printFRMArg(MCInst *MI, unsigned OpNo, SStream *O) |
580 | 8.14k | { |
581 | 8.14k | enum RoundingMode FRMArg = |
582 | 8.14k | (enum RoundingMode)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); |
583 | | #if 0 |
584 | | auto FRMArg = |
585 | | static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm()); |
586 | | O << RISCVFPRndMode::roundingModeToString(FRMArg); |
587 | | #endif |
588 | 8.14k | SStream_concat0(O, roundingModeToString(FRMArg)); |
589 | 8.14k | } |
590 | | |
591 | | #endif // CAPSTONE_HAS_RISCV |