Coverage Report

Created: 2025-07-18 06:43

/src/capstonev5/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|*Assembly Writer Source Fragment                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
15
16
/// printInstruction - This method is automatically generated by tablegen
17
/// from the instruction set description.
18
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19
42.6k
{
20
42.6k
  static const uint32_t OpInfo[] = {
21
42.6k
    0U, // PHI
22
42.6k
    0U, // INLINEASM
23
42.6k
    0U, // CFI_INSTRUCTION
24
42.6k
    0U, // EH_LABEL
25
42.6k
    0U, // GC_LABEL
26
42.6k
    0U, // KILL
27
42.6k
    0U, // EXTRACT_SUBREG
28
42.6k
    0U, // INSERT_SUBREG
29
42.6k
    0U, // IMPLICIT_DEF
30
42.6k
    0U, // SUBREG_TO_REG
31
42.6k
    0U, // COPY_TO_REGCLASS
32
42.6k
    2452U,  // DBG_VALUE
33
42.6k
    0U, // REG_SEQUENCE
34
42.6k
    0U, // COPY
35
42.6k
    2445U,  // BUNDLE
36
42.6k
    2462U,  // LIFETIME_START
37
42.6k
    2432U,  // LIFETIME_END
38
42.6k
    0U, // STACKMAP
39
42.6k
    0U, // PATCHPOINT
40
42.6k
    0U, // LOAD_STACK_GUARD
41
42.6k
    0U, // STATEPOINT
42
42.6k
    0U, // FRAME_ALLOC
43
42.6k
    4688U,  // ADDCCri
44
42.6k
    4688U,  // ADDCCrr
45
42.6k
    5925U,  // ADDCri
46
42.6k
    5925U,  // ADDCrr
47
42.6k
    4772U,  // ADDEri
48
42.6k
    4772U,  // ADDErr
49
42.6k
    4786U,  // ADDXC
50
42.6k
    4678U,  // ADDXCCC
51
42.6k
    4808U,  // ADDXri
52
42.6k
    4808U,  // ADDXrr
53
42.6k
    4808U,  // ADDri
54
42.6k
    4808U,  // ADDrr
55
42.6k
    74166U, // ADJCALLSTACKDOWN
56
42.6k
    74185U, // ADJCALLSTACKUP
57
42.6k
    5497U,  // ALIGNADDR
58
42.6k
    5127U,  // ALIGNADDRL
59
42.6k
    4695U,  // ANDCCri
60
42.6k
    4695U,  // ANDCCrr
61
42.6k
    4718U,  // ANDNCCri
62
42.6k
    4718U,  // ANDNCCrr
63
42.6k
    5182U,  // ANDNri
64
42.6k
    5182U,  // ANDNrr
65
42.6k
    5182U,  // ANDXNrr
66
42.6k
    4876U,  // ANDXri
67
42.6k
    4876U,  // ANDXrr
68
42.6k
    4876U,  // ANDri
69
42.6k
    4876U,  // ANDrr
70
42.6k
    4502U,  // ARRAY16
71
42.6k
    4255U,  // ARRAY32
72
42.6k
    4526U,  // ARRAY8
73
42.6k
    0U, // ATOMIC_LOAD_ADD_32
74
42.6k
    0U, // ATOMIC_LOAD_ADD_64
75
42.6k
    0U, // ATOMIC_LOAD_AND_32
76
42.6k
    0U, // ATOMIC_LOAD_AND_64
77
42.6k
    0U, // ATOMIC_LOAD_MAX_32
78
42.6k
    0U, // ATOMIC_LOAD_MAX_64
79
42.6k
    0U, // ATOMIC_LOAD_MIN_32
80
42.6k
    0U, // ATOMIC_LOAD_MIN_64
81
42.6k
    0U, // ATOMIC_LOAD_NAND_32
82
42.6k
    0U, // ATOMIC_LOAD_NAND_64
83
42.6k
    0U, // ATOMIC_LOAD_OR_32
84
42.6k
    0U, // ATOMIC_LOAD_OR_64
85
42.6k
    0U, // ATOMIC_LOAD_SUB_32
86
42.6k
    0U, // ATOMIC_LOAD_SUB_64
87
42.6k
    0U, // ATOMIC_LOAD_UMAX_32
88
42.6k
    0U, // ATOMIC_LOAD_UMAX_64
89
42.6k
    0U, // ATOMIC_LOAD_UMIN_32
90
42.6k
    0U, // ATOMIC_LOAD_UMIN_64
91
42.6k
    0U, // ATOMIC_LOAD_XOR_32
92
42.6k
    0U, // ATOMIC_LOAD_XOR_64
93
42.6k
    0U, // ATOMIC_SWAP_64
94
42.6k
    74271U, // BA
95
42.6k
    1194492U, // BCOND
96
42.6k
    1260028U, // BCONDA
97
42.6k
    17659U, // BINDri
98
42.6k
    17659U, // BINDrr
99
42.6k
    5065U,  // BMASK
100
42.6k
    145915U,  // BPFCC
101
42.6k
    211451U,  // BPFCCA
102
42.6k
    276987U,  // BPFCCANT
103
42.6k
    342523U,  // BPFCCNT
104
42.6k
    2106465U, // BPGEZapn
105
42.6k
    2105838U, // BPGEZapt
106
42.6k
    2106532U, // BPGEZnapn
107
42.6k
    2107288U, // BPGEZnapt
108
42.6k
    2106489U, // BPGZapn
109
42.6k
    2105856U, // BPGZapt
110
42.6k
    2106552U, // BPGZnapn
111
42.6k
    2107384U, // BPGZnapt
112
42.6k
    1456636U, // BPICC
113
42.6k
    473596U,  // BPICCA
114
42.6k
    539132U,  // BPICCANT
115
42.6k
    604668U,  // BPICCNT
116
42.6k
    2106477U, // BPLEZapn
117
42.6k
    2105847U, // BPLEZapt
118
42.6k
    2106542U, // BPLEZnapn
119
42.6k
    2107337U, // BPLEZnapt
120
42.6k
    2106500U, // BPLZapn
121
42.6k
    2105864U, // BPLZapt
122
42.6k
    2106561U, // BPLZnapn
123
42.6k
    2107428U, // BPLZnapt
124
42.6k
    2106511U, // BPNZapn
125
42.6k
    2105872U, // BPNZapt
126
42.6k
    2106570U, // BPNZnapn
127
42.6k
    2107472U, // BPNZnapt
128
42.6k
    1718780U, // BPXCC
129
42.6k
    735740U,  // BPXCCA
130
42.6k
    801276U,  // BPXCCANT
131
42.6k
    866812U,  // BPXCCNT
132
42.6k
    2106522U, // BPZapn
133
42.6k
    2105880U, // BPZapt
134
42.6k
    2106579U, // BPZnapn
135
42.6k
    2107505U, // BPZnapt
136
42.6k
    4983U,  // BSHUFFLE
137
42.6k
    74742U, // CALL
138
42.6k
    17398U, // CALLri
139
42.6k
    17398U, // CALLrr
140
42.6k
    924148U,  // CASXrr
141
42.6k
    924129U,  // CASrr
142
42.6k
    74001U, // CMASK16
143
42.6k
    73833U, // CMASK32
144
42.6k
    74150U, // CMASK8
145
42.6k
    2106607U, // CMPri
146
42.6k
    2106607U, // CMPrr
147
42.6k
    4332U,  // EDGE16
148
42.6k
    5081U,  // EDGE16L
149
42.6k
    5198U,  // EDGE16LN
150
42.6k
    5165U,  // EDGE16N
151
42.6k
    4164U,  // EDGE32
152
42.6k
    5072U,  // EDGE32L
153
42.6k
    5188U,  // EDGE32LN
154
42.6k
    5156U,  // EDGE32N
155
42.6k
    4511U,  // EDGE8
156
42.6k
    5090U,  // EDGE8L
157
42.6k
    5208U,  // EDGE8LN
158
42.6k
    5174U,  // EDGE8N
159
42.6k
    1053516U, // FABSD
160
42.6k
    1054031U, // FABSQ
161
42.6k
    1054376U, // FABSS
162
42.6k
    4813U,  // FADDD
163
42.6k
    5383U,  // FADDQ
164
42.6k
    5645U,  // FADDS
165
42.6k
    4648U,  // FALIGNADATA
166
42.6k
    4875U,  // FAND
167
42.6k
    4112U,  // FANDNOT1
168
42.6k
    5544U,  // FANDNOT1S
169
42.6k
    4271U,  // FANDNOT2
170
42.6k
    5591U,  // FANDNOT2S
171
42.6k
    5677U,  // FANDS
172
42.6k
    1194491U, // FBCOND
173
42.6k
    1260027U, // FBCONDA
174
42.6k
    4394U,  // FCHKSM16
175
42.6k
    2106173U, // FCMPD
176
42.6k
    4413U,  // FCMPEQ16
177
42.6k
    4226U,  // FCMPEQ32
178
42.6k
    4432U,  // FCMPGT16
179
42.6k
    4245U,  // FCMPGT32
180
42.6k
    4340U,  // FCMPLE16
181
42.6k
    4172U,  // FCMPLE32
182
42.6k
    4350U,  // FCMPNE16
183
42.6k
    4182U,  // FCMPNE32
184
42.6k
    2106696U, // FCMPQ
185
42.6k
    2107005U, // FCMPS
186
42.6k
    4960U,  // FDIVD
187
42.6k
    5475U,  // FDIVQ
188
42.6k
    5815U,  // FDIVS
189
42.6k
    5405U,  // FDMULQ
190
42.6k
    1053620U, // FDTOI
191
42.6k
    1053996U, // FDTOQ
192
42.6k
    1054305U, // FDTOS
193
42.6k
    1054536U, // FDTOX
194
42.6k
    1053464U, // FEXPAND
195
42.6k
    4820U,  // FHADDD
196
42.6k
    5652U,  // FHADDS
197
42.6k
    4800U,  // FHSUBD
198
42.6k
    5637U,  // FHSUBS
199
42.6k
    1053473U, // FITOD
200
42.6k
    1054003U, // FITOQ
201
42.6k
    1054312U, // FITOS
202
42.6k
    6300484U, // FLCMPD
203
42.6k
    6301316U, // FLCMPS
204
42.6k
    2606U,  // FLUSHW
205
42.6k
    4404U,  // FMEAN16
206
42.6k
    1053543U, // FMOVD
207
42.6k
    1006078U, // FMOVD_FCC
208
42.6k
    23484926U,  // FMOVD_ICC
209
42.6k
    23747070U,  // FMOVD_XCC
210
42.6k
    1054058U, // FMOVQ
211
42.6k
    1006102U, // FMOVQ_FCC
212
42.6k
    23484950U,  // FMOVQ_ICC
213
42.6k
    23747094U,  // FMOVQ_XCC
214
42.6k
    6018U,  // FMOVRGEZD
215
42.6k
    6029U,  // FMOVRGEZQ
216
42.6k
    6056U,  // FMOVRGEZS
217
42.6k
    6116U,  // FMOVRGZD
218
42.6k
    6126U,  // FMOVRGZQ
219
42.6k
    6150U,  // FMOVRGZS
220
42.6k
    6067U,  // FMOVRLEZD
221
42.6k
    6078U,  // FMOVRLEZQ
222
42.6k
    6105U,  // FMOVRLEZS
223
42.6k
    6160U,  // FMOVRLZD
224
42.6k
    6170U,  // FMOVRLZQ
225
42.6k
    6194U,  // FMOVRLZS
226
42.6k
    6204U,  // FMOVRNZD
227
42.6k
    6214U,  // FMOVRNZQ
228
42.6k
    6238U,  // FMOVRNZS
229
42.6k
    6009U,  // FMOVRZD
230
42.6k
    6248U,  // FMOVRZQ
231
42.6k
    6269U,  // FMOVRZS
232
42.6k
    1054398U, // FMOVS
233
42.6k
    1006114U, // FMOVS_FCC
234
42.6k
    23484962U,  // FMOVS_ICC
235
42.6k
    23747106U,  // FMOVS_XCC
236
42.6k
    4490U,  // FMUL8SUX16
237
42.6k
    4465U,  // FMUL8ULX16
238
42.6k
    4442U,  // FMUL8X16
239
42.6k
    5098U,  // FMUL8X16AL
240
42.6k
    5849U,  // FMUL8X16AU
241
42.6k
    4860U,  // FMULD
242
42.6k
    4477U,  // FMULD8SUX16
243
42.6k
    4452U,  // FMULD8ULX16
244
42.6k
    5413U,  // FMULQ
245
42.6k
    5714U,  // FMULS
246
42.6k
    4837U,  // FNADDD
247
42.6k
    5669U,  // FNADDS
248
42.6k
    4881U,  // FNAND
249
42.6k
    5684U,  // FNANDS
250
42.6k
    1053429U, // FNEGD
251
42.6k
    1053974U, // FNEGQ
252
42.6k
    1054283U, // FNEGS
253
42.6k
    4828U,  // FNHADDD
254
42.6k
    5660U,  // FNHADDS
255
42.6k
    4828U,  // FNMULD
256
42.6k
    5660U,  // FNMULS
257
42.6k
    5513U,  // FNOR
258
42.6k
    5778U,  // FNORS
259
42.6k
    1052698U, // FNOT1
260
42.6k
    1054131U, // FNOT1S
261
42.6k
    1052857U, // FNOT2
262
42.6k
    1054178U, // FNOT2S
263
42.6k
    5660U,  // FNSMULD
264
42.6k
    74625U, // FONE
265
42.6k
    75324U, // FONES
266
42.6k
    5508U,  // FOR
267
42.6k
    4129U,  // FORNOT1
268
42.6k
    5563U,  // FORNOT1S
269
42.6k
    4288U,  // FORNOT2
270
42.6k
    5610U,  // FORNOT2S
271
42.6k
    5772U,  // FORS
272
42.6k
    1052936U, // FPACK16
273
42.6k
    4192U,  // FPACK32
274
42.6k
    1054507U, // FPACKFIX
275
42.6k
    4323U,  // FPADD16
276
42.6k
    5620U,  // FPADD16S
277
42.6k
    4155U,  // FPADD32
278
42.6k
    5573U,  // FPADD32S
279
42.6k
    4297U,  // FPADD64
280
42.6k
    4974U,  // FPMERGE
281
42.6k
    4314U,  // FPSUB16
282
42.6k
    4580U,  // FPSUB16S
283
42.6k
    4146U,  // FPSUB32
284
42.6k
    4570U,  // FPSUB32S
285
42.6k
    1053480U, // FQTOD
286
42.6k
    1053627U, // FQTOI
287
42.6k
    1054319U, // FQTOS
288
42.6k
    1054552U, // FQTOX
289
42.6k
    4423U,  // FSLAS16
290
42.6k
    4236U,  // FSLAS32
291
42.6k
    4378U,  // FSLL16
292
42.6k
    4210U,  // FSLL32
293
42.6k
    4867U,  // FSMULD
294
42.6k
    1053523U, // FSQRTD
295
42.6k
    1054038U, // FSQRTQ
296
42.6k
    1054383U, // FSQRTS
297
42.6k
    4306U,  // FSRA16
298
42.6k
    4138U,  // FSRA32
299
42.6k
    1052681U, // FSRC1
300
42.6k
    1054112U, // FSRC1S
301
42.6k
    1052840U, // FSRC2
302
42.6k
    1054159U, // FSRC2S
303
42.6k
    4386U,  // FSRL16
304
42.6k
    4218U,  // FSRL32
305
42.6k
    1053487U, // FSTOD
306
42.6k
    1053634U, // FSTOI
307
42.6k
    1054010U, // FSTOQ
308
42.6k
    1054559U, // FSTOX
309
42.6k
    4793U,  // FSUBD
310
42.6k
    5376U,  // FSUBQ
311
42.6k
    5630U,  // FSUBS
312
42.6k
    5519U,  // FXNOR
313
42.6k
    5785U,  // FXNORS
314
42.6k
    5526U,  // FXOR
315
42.6k
    5793U,  // FXORS
316
42.6k
    1053494U, // FXTOD
317
42.6k
    1054017U, // FXTOQ
318
42.6k
    1054326U, // FXTOS
319
42.6k
    74984U, // FZERO
320
42.6k
    75353U, // FZEROS
321
42.6k
    24584U, // GETPCX
322
42.6k
    1078273U, // JMPLri
323
42.6k
    1078273U, // JMPLrr
324
42.6k
    1997243U, // LDDFri
325
42.6k
    1997243U, // LDDFrr
326
42.6k
    1997249U, // LDFri
327
42.6k
    1997249U, // LDFrr
328
42.6k
    1997275U, // LDQFri
329
42.6k
    1997275U, // LDQFrr
330
42.6k
    1997229U, // LDSBri
331
42.6k
    1997229U, // LDSBrr
332
42.6k
    1997254U, // LDSHri
333
42.6k
    1997254U, // LDSHrr
334
42.6k
    1997287U, // LDSWri
335
42.6k
    1997287U, // LDSWrr
336
42.6k
    1997236U, // LDUBri
337
42.6k
    1997236U, // LDUBrr
338
42.6k
    1997261U, // LDUHri
339
42.6k
    1997261U, // LDUHrr
340
42.6k
    1997294U, // LDXri
341
42.6k
    1997294U, // LDXrr
342
42.6k
    1997249U, // LDri
343
42.6k
    1997249U, // LDrr
344
42.6k
    33480U, // LEAX_ADDri
345
42.6k
    33480U, // LEA_ADDri
346
42.6k
    1054405U, // LZCNT
347
42.6k
    75121U, // MEMBARi
348
42.6k
    1054543U, // MOVDTOX
349
42.6k
    1006122U, // MOVFCCri
350
42.6k
    1006122U, // MOVFCCrr
351
42.6k
    23484970U,  // MOVICCri
352
42.6k
    23484970U,  // MOVICCrr
353
42.6k
    6047U,  // MOVRGEZri
354
42.6k
    6047U,  // MOVRGEZrr
355
42.6k
    6142U,  // MOVRGZri
356
42.6k
    6142U,  // MOVRGZrr
357
42.6k
    6096U,  // MOVRLEZri
358
42.6k
    6096U,  // MOVRLEZrr
359
42.6k
    6186U,  // MOVRLZri
360
42.6k
    6186U,  // MOVRLZrr
361
42.6k
    6230U,  // MOVRNZri
362
42.6k
    6230U,  // MOVRNZrr
363
42.6k
    6262U,  // MOVRRZri
364
42.6k
    6262U,  // MOVRRZrr
365
42.6k
    1054469U, // MOVSTOSW
366
42.6k
    1054479U, // MOVSTOUW
367
42.6k
    1054543U, // MOVWTOS
368
42.6k
    23747114U,  // MOVXCCri
369
42.6k
    23747114U,  // MOVXCCrr
370
42.6k
    1054543U, // MOVXTOD
371
42.6k
    5954U,  // MULXri
372
42.6k
    5954U,  // MULXrr
373
42.6k
    2578U,  // NOP
374
42.6k
    4735U,  // ORCCri
375
42.6k
    4735U,  // ORCCrr
376
42.6k
    4726U,  // ORNCCri
377
42.6k
    4726U,  // ORNCCrr
378
42.6k
    5339U,  // ORNri
379
42.6k
    5339U,  // ORNrr
380
42.6k
    5339U,  // ORXNrr
381
42.6k
    5509U,  // ORXri
382
42.6k
    5509U,  // ORXrr
383
42.6k
    5509U,  // ORri
384
42.6k
    5509U,  // ORrr
385
42.6k
    5836U,  // PDIST
386
42.6k
    5344U,  // PDISTN
387
42.6k
    1053356U, // POPCrr
388
42.6k
    73729U, // RDY
389
42.6k
    4999U,  // RESTOREri
390
42.6k
    4999U,  // RESTORErr
391
42.6k
    76132U, // RET
392
42.6k
    76141U, // RETL
393
42.6k
    18131U, // RETTri
394
42.6k
    18131U, // RETTrr
395
42.6k
    5008U,  // SAVEri
396
42.6k
    5008U,  // SAVErr
397
42.6k
    4748U,  // SDIVCCri
398
42.6k
    4748U,  // SDIVCCrr
399
42.6k
    5995U,  // SDIVXri
400
42.6k
    5995U,  // SDIVXrr
401
42.6k
    5861U,  // SDIVri
402
42.6k
    5861U,  // SDIVrr
403
42.6k
    2182U,  // SELECT_CC_DFP_FCC
404
42.6k
    2293U,  // SELECT_CC_DFP_ICC
405
42.6k
    2238U,  // SELECT_CC_FP_FCC
406
42.6k
    2349U,  // SELECT_CC_FP_ICC
407
42.6k
    2265U,  // SELECT_CC_Int_FCC
408
42.6k
    2376U,  // SELECT_CC_Int_ICC
409
42.6k
    2210U,  // SELECT_CC_QFP_FCC
410
42.6k
    2321U,  // SELECT_CC_QFP_ICC
411
42.6k
    1053595U, // SETHIXi
412
42.6k
    1053595U, // SETHIi
413
42.6k
    2569U,  // SHUTDOWN
414
42.6k
    2564U,  // SIAM
415
42.6k
    5941U,  // SLLXri
416
42.6k
    5941U,  // SLLXrr
417
42.6k
    5116U,  // SLLri
418
42.6k
    5116U,  // SLLrr
419
42.6k
    4702U,  // SMULCCri
420
42.6k
    4702U,  // SMULCCrr
421
42.6k
    5144U,  // SMULri
422
42.6k
    5144U,  // SMULrr
423
42.6k
    5913U,  // SRAXri
424
42.6k
    5913U,  // SRAXrr
425
42.6k
    4643U,  // SRAri
426
42.6k
    4643U,  // SRArr
427
42.6k
    5947U,  // SRLXri
428
42.6k
    5947U,  // SRLXrr
429
42.6k
    5139U,  // SRLri
430
42.6k
    5139U,  // SRLrr
431
42.6k
    2588U,  // STBAR
432
42.6k
    37428U, // STBri
433
42.6k
    37428U, // STBrr
434
42.6k
    37723U, // STDFri
435
42.6k
    37723U, // STDFrr
436
42.6k
    38607U, // STFri
437
42.6k
    38607U, // STFrr
438
42.6k
    37782U, // STHri
439
42.6k
    37782U, // STHrr
440
42.6k
    38238U, // STQFri
441
42.6k
    38238U, // STQFrr
442
42.6k
    38758U, // STXri
443
42.6k
    38758U, // STXrr
444
42.6k
    38607U, // STri
445
42.6k
    38607U, // STrr
446
42.6k
    4671U,  // SUBCCri
447
42.6k
    4671U,  // SUBCCrr
448
42.6k
    5919U,  // SUBCri
449
42.6k
    5919U,  // SUBCrr
450
42.6k
    4764U,  // SUBEri
451
42.6k
    4764U,  // SUBErr
452
42.6k
    4665U,  // SUBXri
453
42.6k
    4665U,  // SUBXrr
454
42.6k
    4665U,  // SUBri
455
42.6k
    4665U,  // SUBrr
456
42.6k
    1997268U, // SWAPri
457
42.6k
    1997268U, // SWAPrr
458
42.6k
    2422U,  // TA3
459
42.6k
    2427U,  // TA5
460
42.6k
    5883U,  // TADDCCTVri
461
42.6k
    5883U,  // TADDCCTVrr
462
42.6k
    4687U,  // TADDCCri
463
42.6k
    4687U,  // TADDCCrr
464
42.6k
    9873960U, // TICCri
465
42.6k
    9873960U, // TICCrr
466
42.6k
    37753544U,  // TLS_ADDXrr
467
42.6k
    37753544U,  // TLS_ADDrr
468
42.6k
    2106358U, // TLS_CALL
469
42.6k
    39746030U,  // TLS_LDXrr
470
42.6k
    39745985U,  // TLS_LDrr
471
42.6k
    5873U,  // TSUBCCTVri
472
42.6k
    5873U,  // TSUBCCTVrr
473
42.6k
    4670U,  // TSUBCCri
474
42.6k
    4670U,  // TSUBCCrr
475
42.6k
    10136104U,  // TXCCri
476
42.6k
    10136104U,  // TXCCrr
477
42.6k
    4756U,  // UDIVCCri
478
42.6k
    4756U,  // UDIVCCrr
479
42.6k
    6002U,  // UDIVXri
480
42.6k
    6002U,  // UDIVXrr
481
42.6k
    5867U,  // UDIVri
482
42.6k
    5867U,  // UDIVrr
483
42.6k
    4710U,  // UMULCCri
484
42.6k
    4710U,  // UMULCCrr
485
42.6k
    5026U,  // UMULXHI
486
42.6k
    5150U,  // UMULri
487
42.6k
    5150U,  // UMULrr
488
42.6k
    74996U, // UNIMP
489
42.6k
    6300477U, // V9FCMPD
490
42.6k
    6300397U, // V9FCMPED
491
42.6k
    6300942U, // V9FCMPEQ
492
42.6k
    6301251U, // V9FCMPES
493
42.6k
    6301000U, // V9FCMPQ
494
42.6k
    6301309U, // V9FCMPS
495
42.6k
    47614U, // V9FMOVD_FCC
496
42.6k
    47638U, // V9FMOVQ_FCC
497
42.6k
    47650U, // V9FMOVS_FCC
498
42.6k
    47658U, // V9MOVFCCri
499
42.6k
    47658U, // V9MOVFCCrr
500
42.6k
    14689692U,  // WRYri
501
42.6k
    14689692U,  // WRYrr
502
42.6k
    5953U,  // XMULX
503
42.6k
    5035U,  // XMULXHI
504
42.6k
    4733U,  // XNORCCri
505
42.6k
    4733U,  // XNORCCrr
506
42.6k
    5520U,  // XNORXrr
507
42.6k
    5520U,  // XNORri
508
42.6k
    5520U,  // XNORrr
509
42.6k
    4741U,  // XORCCri
510
42.6k
    4741U,  // XORCCrr
511
42.6k
    5527U,  // XORXri
512
42.6k
    5527U,  // XORXrr
513
42.6k
    5527U,  // XORri
514
42.6k
    5527U,  // XORrr
515
42.6k
    0U
516
42.6k
  };
517
518
42.6k
#ifndef CAPSTONE_DIET
519
42.6k
  static const char AsmStrs[] = {
520
42.6k
  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521
42.6k
  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522
42.6k
  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523
42.6k
  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524
42.6k
  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525
42.6k
  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526
42.6k
  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527
42.6k
  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528
42.6k
  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529
42.6k
  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530
42.6k
  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531
42.6k
  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532
42.6k
  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533
42.6k
  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534
42.6k
  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535
42.6k
  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536
42.6k
  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537
42.6k
  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538
42.6k
  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539
42.6k
  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540
42.6k
  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541
42.6k
  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542
42.6k
  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543
42.6k
  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544
42.6k
  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545
42.6k
  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546
42.6k
  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547
42.6k
  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548
42.6k
  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549
42.6k
  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550
42.6k
  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551
42.6k
  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552
42.6k
  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553
42.6k
  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554
42.6k
  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555
42.6k
  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556
42.6k
  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557
42.6k
  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558
42.6k
  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559
42.6k
  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560
42.6k
  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561
42.6k
  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562
42.6k
  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563
42.6k
  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564
42.6k
  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565
42.6k
  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566
42.6k
  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567
42.6k
  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568
42.6k
  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569
42.6k
  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570
42.6k
  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571
42.6k
  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572
42.6k
  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573
42.6k
  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574
42.6k
  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575
42.6k
  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576
42.6k
  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577
42.6k
  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578
42.6k
  /* 542 */ 'b', 'a', 32, 0,
579
42.6k
  /* 546 */ 's', 'r', 'a', 32, 0,
580
42.6k
  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581
42.6k
  /* 563 */ 's', 't', 'b', 32, 0,
582
42.6k
  /* 568 */ 's', 'u', 'b', 32, 0,
583
42.6k
  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584
42.6k
  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585
42.6k
  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586
42.6k
  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587
42.6k
  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588
42.6k
  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589
42.6k
  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590
42.6k
  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591
42.6k
  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592
42.6k
  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593
42.6k
  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594
42.6k
  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595
42.6k
  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596
42.6k
  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597
42.6k
  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598
42.6k
  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599
42.6k
  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600
42.6k
  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601
42.6k
  /* 711 */ 'a', 'd', 'd', 32, 0,
602
42.6k
  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603
42.6k
  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604
42.6k
  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605
42.6k
  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606
42.6k
  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607
42.6k
  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608
42.6k
  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609
42.6k
  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610
42.6k
  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611
42.6k
  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612
42.6k
  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613
42.6k
  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614
42.6k
  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615
42.6k
  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616
42.6k
  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617
42.6k
  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618
42.6k
  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619
42.6k
  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620
42.6k
  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621
42.6k
  /* 858 */ 's', 't', 'd', 32, 0,
622
42.6k
  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623
42.6k
  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624
42.6k
  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625
42.6k
  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626
42.6k
  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627
42.6k
  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628
42.6k
  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629
42.6k
  /* 917 */ 's', 't', 'h', 32, 0,
630
42.6k
  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631
42.6k
  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632
42.6k
  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633
42.6k
  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634
42.6k
  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635
42.6k
  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636
42.6k
  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637
42.6k
  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638
42.6k
  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639
42.6k
  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640
42.6k
  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641
42.6k
  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642
42.6k
  /* 1019 */ 's', 'l', 'l', 32, 0,
643
42.6k
  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644
42.6k
  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645
42.6k
  /* 1042 */ 's', 'r', 'l', 32, 0,
646
42.6k
  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647
42.6k
  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648
42.6k
  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649
42.6k
  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650
42.6k
  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651
42.6k
  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652
42.6k
  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653
42.6k
  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654
42.6k
  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655
42.6k
  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656
42.6k
  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657
42.6k
  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658
42.6k
  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659
42.6k
  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660
42.6k
  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661
42.6k
  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662
42.6k
  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663
42.6k
  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664
42.6k
  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665
42.6k
  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666
42.6k
  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667
42.6k
  /* 1242 */ 'o', 'r', 'n', 32, 0,
668
42.6k
  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669
42.6k
  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670
42.6k
  /* 1262 */ 'c', 'm', 'p', 32, 0,
671
42.6k
  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672
42.6k
  /* 1274 */ 'j', 'm', 'p', 32, 0,
673
42.6k
  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674
42.6k
  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675
42.6k
  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676
42.6k
  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677
42.6k
  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678
42.6k
  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679
42.6k
  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680
42.6k
  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681
42.6k
  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682
42.6k
  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683
42.6k
  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684
42.6k
  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685
42.6k
  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686
42.6k
  /* 1373 */ 's', 't', 'q', 32, 0,
687
42.6k
  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688
42.6k
  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689
42.6k
  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690
42.6k
  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691
42.6k
  /* 1411 */ 'f', 'o', 'r', 32, 0,
692
42.6k
  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693
42.6k
  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694
42.6k
  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695
42.6k
  /* 1435 */ 'w', 'r', 32, 0,
696
42.6k
  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697
42.6k
  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698
42.6k
  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699
42.6k
  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700
42.6k
  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701
42.6k
  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702
42.6k
  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703
42.6k
  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704
42.6k
  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705
42.6k
  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706
42.6k
  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707
42.6k
  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708
42.6k
  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709
42.6k
  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710
42.6k
  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711
42.6k
  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712
42.6k
  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713
42.6k
  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714
42.6k
  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715
42.6k
  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716
42.6k
  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717
42.6k
  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718
42.6k
  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719
42.6k
  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720
42.6k
  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721
42.6k
  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722
42.6k
  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723
42.6k
  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724
42.6k
  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725
42.6k
  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726
42.6k
  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727
42.6k
  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728
42.6k
  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729
42.6k
  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730
42.6k
  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731
42.6k
  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732
42.6k
  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733
42.6k
  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734
42.6k
  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735
42.6k
  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736
42.6k
  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737
42.6k
  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738
42.6k
  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739
42.6k
  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740
42.6k
  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741
42.6k
  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742
42.6k
  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743
42.6k
  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744
42.6k
  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745
42.6k
  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746
42.6k
  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747
42.6k
  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748
42.6k
  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749
42.6k
  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750
42.6k
  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751
42.6k
  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752
42.6k
  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753
42.6k
  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754
42.6k
  /* 1893 */ 's', 't', 'x', 32, 0,
755
42.6k
  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756
42.6k
  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757
42.6k
  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758
42.6k
  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759
42.6k
  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760
42.6k
  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761
42.6k
  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762
42.6k
  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763
42.6k
  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764
42.6k
  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765
42.6k
  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766
42.6k
  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767
42.6k
  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768
42.6k
  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769
42.6k
  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770
42.6k
  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771
42.6k
  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772
42.6k
  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773
42.6k
  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774
42.6k
  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775
42.6k
  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776
42.6k
  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777
42.6k
  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778
42.6k
  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779
42.6k
  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780
42.6k
  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781
42.6k
  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782
42.6k
  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783
42.6k
  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784
42.6k
  /* 2160 */ 'b', 'r', 'z', 32, 0,
785
42.6k
  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786
42.6k
  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787
42.6k
  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788
42.6k
  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789
42.6k
  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790
42.6k
  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791
42.6k
  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792
42.6k
  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793
42.6k
  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794
42.6k
  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795
42.6k
  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796
42.6k
  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797
42.6k
  /* 2421 */ 't', 'a', 32, '3', 0,
798
42.6k
  /* 2426 */ 't', 'a', 32, '5', 0,
799
42.6k
  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800
42.6k
  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801
42.6k
  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802
42.6k
  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803
42.6k
  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804
42.6k
  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805
42.6k
  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806
42.6k
  /* 2496 */ 'l', 'd', 32, '[', 0,
807
42.6k
  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808
42.6k
  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809
42.6k
  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810
42.6k
  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811
42.6k
  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812
42.6k
  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813
42.6k
  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814
42.6k
  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815
42.6k
  /* 2554 */ 'f', 'b', 0,
816
42.6k
  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817
42.6k
  /* 2563 */ 's', 'i', 'a', 'm', 0,
818
42.6k
  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819
42.6k
  /* 2577 */ 'n', 'o', 'p', 0,
820
42.6k
  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821
42.6k
  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822
42.6k
  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823
42.6k
  /* 2599 */ 't', 0,
824
42.6k
  /* 2601 */ 'm', 'o', 'v', 0,
825
42.6k
  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826
42.6k
  };
827
42.6k
#endif
828
829
  // Emit the opcode for the instruction.
830
42.6k
  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831
42.6k
#ifndef CAPSTONE_DIET
832
  // assert(Bits != 0 && "Cannot print this instruction.");
833
42.6k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834
42.6k
#endif
835
836
837
  // Fragment 0 encoded into 4 bits for 12 unique commands.
838
  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839
42.6k
  switch ((Bits >> 12) & 15) {
840
0
  default:   // unreachable.
841
99
  case 0:
842
    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843
99
    return;
844
0
    break;
845
6.78k
  case 1:
846
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847
6.78k
    printOperand(MI, 1, O); 
848
6.78k
    break;
849
25.0k
  case 2:
850
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851
25.0k
    printOperand(MI, 0, O); 
852
25.0k
    break;
853
3.44k
  case 3:
854
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855
3.44k
    printCCOperand(MI, 1, O); 
856
3.44k
    break;
857
910
  case 4:
858
    // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859
910
    printMemOperand(MI, 0, O, NULL); 
860
910
    return;
861
0
    break;
862
2.17k
  case 5:
863
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864
2.17k
    printCCOperand(MI, 3, O); 
865
2.17k
    break;
866
0
  case 6:
867
    // GETPCX
868
0
    printGetPCX(MI, 0, O); 
869
0
    return;
870
0
    break;
871
1.84k
  case 7:
872
    // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873
1.84k
    printMemOperand(MI, 1, O, NULL); 
874
1.84k
    break;
875
0
  case 8:
876
    // LEAX_ADDri, LEA_ADDri
877
0
    printMemOperand(MI, 1, O, "arith"); 
878
0
    SStream_concat0(O, ", "); 
879
0
    printOperand(MI, 0, O); 
880
0
    return;
881
0
    break;
882
765
  case 9:
883
    // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884
765
    printOperand(MI, 2, O); 
885
765
    SStream_concat0(O, ", ["); 
886
765
    printMemOperand(MI, 0, O, NULL); 
887
765
    SStream_concat0(O, "]"); 
888
765
    return;
889
0
    break;
890
623
  case 10:
891
    // TICCri, TICCrr, TXCCri, TXCCrr
892
623
    printCCOperand(MI, 2, O); 
893
623
    break;
894
1.01k
  case 11:
895
    // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896
1.01k
    printCCOperand(MI, 4, O); 
897
1.01k
    SStream_concat0(O, " "); 
898
1.01k
    printOperand(MI, 1, O); 
899
1.01k
    SStream_concat0(O, ", "); 
900
1.01k
    printOperand(MI, 2, O); 
901
1.01k
    SStream_concat0(O, ", "); 
902
1.01k
    printOperand(MI, 0, O); 
903
1.01k
    return;
904
0
    break;
905
42.6k
  }
906
907
908
  // Fragment 1 encoded into 4 bits for 16 unique commands.
909
  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910
39.8k
  switch ((Bits >> 16) & 15) {
911
0
  default:   // unreachable.
912
11.1k
  case 0:
913
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914
11.1k
    SStream_concat0(O, ", "); 
915
11.1k
    break;
916
20.6k
  case 1:
917
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918
20.6k
    return;
919
0
    break;
920
1.29k
  case 2:
921
    // BCOND, BPFCC, FBCOND
922
1.29k
    SStream_concat0(O, " "); 
923
1.29k
    break;
924
1.17k
  case 3:
925
    // BCONDA, BPFCCA, FBCONDA
926
1.17k
    SStream_concat0(O, ",a ");
927
1.17k
  Sparc_add_hint(MI, SPARC_HINT_A);
928
1.17k
    break;
929
0
  case 4:
930
    // BPFCCANT
931
0
    SStream_concat0(O, ",a,pn ");
932
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933
0
    printOperand(MI, 2, O); 
934
0
    SStream_concat0(O, ", "); 
935
0
    printOperand(MI, 0, O); 
936
0
    return;
937
0
    break;
938
0
  case 5:
939
    // BPFCCNT
940
0
    SStream_concat0(O, ",pn ");
941
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
942
0
    printOperand(MI, 2, O); 
943
0
    SStream_concat0(O, ", "); 
944
0
    printOperand(MI, 0, O); 
945
0
    return;
946
0
    break;
947
2.13k
  case 6:
948
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949
2.13k
    SStream_concat0(O, " %icc, ");
950
2.13k
  Sparc_add_reg(MI, SPARC_REG_ICC);
951
2.13k
    break;
952
365
  case 7:
953
    // BPICCA
954
365
    SStream_concat0(O, ",a %icc, ");
955
365
  Sparc_add_hint(MI, SPARC_HINT_A);
956
365
  Sparc_add_reg(MI, SPARC_REG_ICC);
957
365
    printOperand(MI, 0, O); 
958
365
    return;
959
0
    break;
960
0
  case 8:
961
    // BPICCANT
962
0
    SStream_concat0(O, ",a,pn %icc, ");
963
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
965
0
    printOperand(MI, 0, O); 
966
0
    return;
967
0
    break;
968
0
  case 9:
969
    // BPICCNT
970
0
    SStream_concat0(O, ",pn %icc, ");
971
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
972
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
973
0
    printOperand(MI, 0, O); 
974
0
    return;
975
0
    break;
976
481
  case 10:
977
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978
481
    SStream_concat0(O, " %xcc, ");
979
481
  Sparc_add_reg(MI, SPARC_REG_XCC);
980
481
    break;
981
80
  case 11:
982
    // BPXCCA
983
80
    SStream_concat0(O, ",a %xcc, ");
984
80
  Sparc_add_hint(MI, SPARC_HINT_A);
985
80
  Sparc_add_reg(MI, SPARC_REG_XCC);
986
80
    printOperand(MI, 0, O); 
987
80
    return;
988
0
    break;
989
0
  case 12:
990
    // BPXCCANT
991
0
    SStream_concat0(O, ",a,pn %xcc, ");
992
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
994
0
    printOperand(MI, 0, O); 
995
0
    return;
996
0
    break;
997
0
  case 13:
998
    // BPXCCNT
999
0
    SStream_concat0(O, ",pn %xcc, ");
1000
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
1001
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
1002
0
    printOperand(MI, 0, O); 
1003
0
    return;
1004
0
    break;
1005
1.85k
  case 14:
1006
    // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007
1.85k
    SStream_concat0(O, "], "); 
1008
1.85k
    break;
1009
714
  case 15:
1010
    // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011
714
    SStream_concat0(O, " %fcc0, ");
1012
714
  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013
714
    printOperand(MI, 1, O); 
1014
714
    SStream_concat0(O, ", "); 
1015
714
    printOperand(MI, 0, O); 
1016
714
    return;
1017
0
    break;
1018
39.8k
  }
1019
1020
1021
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022
  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023
18.1k
  switch ((Bits >> 20) & 3) {
1024
0
  default:   // unreachable.
1025
5.51k
  case 0:
1026
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027
5.51k
    printOperand(MI, 2, O); 
1028
5.51k
    SStream_concat0(O, ", "); 
1029
5.51k
    printOperand(MI, 0, O); 
1030
5.51k
    break;
1031
6.73k
  case 1:
1032
    // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033
6.73k
    printOperand(MI, 0, O); 
1034
6.73k
    break;
1035
5.84k
  case 2:
1036
    // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037
5.84k
    printOperand(MI, 1, O); 
1038
5.84k
    break;
1039
18.1k
  }
1040
1041
1042
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043
  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044
18.1k
  switch ((Bits >> 22) & 3) {
1045
0
  default:   // unreachable.
1046
14.7k
  case 0:
1047
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048
14.7k
    return;
1049
0
    break;
1050
2.46k
  case 1:
1051
    // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052
2.46k
    SStream_concat0(O, ", "); 
1053
2.46k
    break;
1054
623
  case 2:
1055
    // TICCri, TICCrr, TXCCri, TXCCrr
1056
623
    SStream_concat0(O, " + ");  // qq
1057
623
    printOperand(MI, 1, O); 
1058
623
    return;
1059
0
    break;
1060
234
  case 3:
1061
    // WRYri, WRYrr
1062
234
    SStream_concat0(O, ", %y");
1063
234
  Sparc_add_reg(MI, SPARC_REG_Y);
1064
234
    return;
1065
0
    break;
1066
18.1k
  }
1067
1068
1069
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070
  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071
2.46k
  switch ((Bits >> 24) & 3) {
1072
0
  default:   // unreachable.
1073
1.00k
  case 0:
1074
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075
1.00k
    printOperand(MI, 2, O); 
1076
1.00k
    return;
1077
0
    break;
1078
1.46k
  case 1:
1079
    // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080
1.46k
    printOperand(MI, 0, O); 
1081
1.46k
    return;
1082
0
    break;
1083
0
  case 2:
1084
    // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085
0
    printOperand(MI, 3, O); 
1086
0
    return;
1087
0
    break;
1088
2.46k
  }
1089
2.46k
}
1090
1091
1092
/// getRegisterName - This method is automatically generated by tblgen
1093
/// from the register set description.  This returns the assembler name
1094
/// for the specified register.
1095
static const char *getRegisterName(unsigned RegNo)
1096
57.8k
{
1097
  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098
1099
57.8k
#ifndef CAPSTONE_DIET
1100
57.8k
  static const char AsmStrs[] = {
1101
57.8k
  /* 0 */ 'f', '1', '0', 0,
1102
57.8k
  /* 4 */ 'f', '2', '0', 0,
1103
57.8k
  /* 8 */ 'f', '3', '0', 0,
1104
57.8k
  /* 12 */ 'f', '4', '0', 0,
1105
57.8k
  /* 16 */ 'f', '5', '0', 0,
1106
57.8k
  /* 20 */ 'f', '6', '0', 0,
1107
57.8k
  /* 24 */ 'f', 'c', 'c', '0', 0,
1108
57.8k
  /* 29 */ 'f', '0', 0,
1109
57.8k
  /* 32 */ 'g', '0', 0,
1110
57.8k
  /* 35 */ 'i', '0', 0,
1111
57.8k
  /* 38 */ 'l', '0', 0,
1112
57.8k
  /* 41 */ 'o', '0', 0,
1113
57.8k
  /* 44 */ 'f', '1', '1', 0,
1114
57.8k
  /* 48 */ 'f', '2', '1', 0,
1115
57.8k
  /* 52 */ 'f', '3', '1', 0,
1116
57.8k
  /* 56 */ 'f', 'c', 'c', '1', 0,
1117
57.8k
  /* 61 */ 'f', '1', 0,
1118
57.8k
  /* 64 */ 'g', '1', 0,
1119
57.8k
  /* 67 */ 'i', '1', 0,
1120
57.8k
  /* 70 */ 'l', '1', 0,
1121
57.8k
  /* 73 */ 'o', '1', 0,
1122
57.8k
  /* 76 */ 'f', '1', '2', 0,
1123
57.8k
  /* 80 */ 'f', '2', '2', 0,
1124
57.8k
  /* 84 */ 'f', '3', '2', 0,
1125
57.8k
  /* 88 */ 'f', '4', '2', 0,
1126
57.8k
  /* 92 */ 'f', '5', '2', 0,
1127
57.8k
  /* 96 */ 'f', '6', '2', 0,
1128
57.8k
  /* 100 */ 'f', 'c', 'c', '2', 0,
1129
57.8k
  /* 105 */ 'f', '2', 0,
1130
57.8k
  /* 108 */ 'g', '2', 0,
1131
57.8k
  /* 111 */ 'i', '2', 0,
1132
57.8k
  /* 114 */ 'l', '2', 0,
1133
57.8k
  /* 117 */ 'o', '2', 0,
1134
57.8k
  /* 120 */ 'f', '1', '3', 0,
1135
57.8k
  /* 124 */ 'f', '2', '3', 0,
1136
57.8k
  /* 128 */ 'f', 'c', 'c', '3', 0,
1137
57.8k
  /* 133 */ 'f', '3', 0,
1138
57.8k
  /* 136 */ 'g', '3', 0,
1139
57.8k
  /* 139 */ 'i', '3', 0,
1140
57.8k
  /* 142 */ 'l', '3', 0,
1141
57.8k
  /* 145 */ 'o', '3', 0,
1142
57.8k
  /* 148 */ 'f', '1', '4', 0,
1143
57.8k
  /* 152 */ 'f', '2', '4', 0,
1144
57.8k
  /* 156 */ 'f', '3', '4', 0,
1145
57.8k
  /* 160 */ 'f', '4', '4', 0,
1146
57.8k
  /* 164 */ 'f', '5', '4', 0,
1147
57.8k
  /* 168 */ 'f', '4', 0,
1148
57.8k
  /* 171 */ 'g', '4', 0,
1149
57.8k
  /* 174 */ 'i', '4', 0,
1150
57.8k
  /* 177 */ 'l', '4', 0,
1151
57.8k
  /* 180 */ 'o', '4', 0,
1152
57.8k
  /* 183 */ 'f', '1', '5', 0,
1153
57.8k
  /* 187 */ 'f', '2', '5', 0,
1154
57.8k
  /* 191 */ 'f', '5', 0,
1155
57.8k
  /* 194 */ 'g', '5', 0,
1156
57.8k
  /* 197 */ 'i', '5', 0,
1157
57.8k
  /* 200 */ 'l', '5', 0,
1158
57.8k
  /* 203 */ 'o', '5', 0,
1159
57.8k
  /* 206 */ 'f', '1', '6', 0,
1160
57.8k
  /* 210 */ 'f', '2', '6', 0,
1161
57.8k
  /* 214 */ 'f', '3', '6', 0,
1162
57.8k
  /* 218 */ 'f', '4', '6', 0,
1163
57.8k
  /* 222 */ 'f', '5', '6', 0,
1164
57.8k
  /* 226 */ 'f', '6', 0,
1165
57.8k
  /* 229 */ 'g', '6', 0,
1166
57.8k
  /* 232 */ 'l', '6', 0,
1167
57.8k
  /* 235 */ 'f', '1', '7', 0,
1168
57.8k
  /* 239 */ 'f', '2', '7', 0,
1169
57.8k
  /* 243 */ 'f', '7', 0,
1170
57.8k
  /* 246 */ 'g', '7', 0,
1171
57.8k
  /* 249 */ 'i', '7', 0,
1172
57.8k
  /* 252 */ 'l', '7', 0,
1173
57.8k
  /* 255 */ 'o', '7', 0,
1174
57.8k
  /* 258 */ 'f', '1', '8', 0,
1175
57.8k
  /* 262 */ 'f', '2', '8', 0,
1176
57.8k
  /* 266 */ 'f', '3', '8', 0,
1177
57.8k
  /* 270 */ 'f', '4', '8', 0,
1178
57.8k
  /* 274 */ 'f', '5', '8', 0,
1179
57.8k
  /* 278 */ 'f', '8', 0,
1180
57.8k
  /* 281 */ 'f', '1', '9', 0,
1181
57.8k
  /* 285 */ 'f', '2', '9', 0,
1182
57.8k
  /* 289 */ 'f', '9', 0,
1183
57.8k
  /* 292 */ 'i', 'c', 'c', 0,
1184
57.8k
  /* 296 */ 'f', 'p', 0,
1185
57.8k
  /* 299 */ 's', 'p', 0,
1186
57.8k
  /* 302 */ 'y', 0,
1187
57.8k
  };
1188
1189
57.8k
  static const uint16_t RegAsmOffset[] = {
1190
57.8k
    292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 
1191
57.8k
    152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 
1192
57.8k
    92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 
1193
57.8k
    278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 
1194
57.8k
    80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 
1195
57.8k
    32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 
1196
57.8k
    296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 
1197
57.8k
    180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 
1198
57.8k
    12, 160, 270, 92, 222, 20, 
1199
57.8k
  };
1200
1201
  //int i;
1202
  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203
  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204
  //printf("*************************\n");
1205
57.8k
  return AsmStrs+RegAsmOffset[RegNo-1];
1206
#else
1207
  return NULL;
1208
#endif
1209
57.8k
}
1210
1211
#ifdef PRINT_ALIAS_INSTR
1212
#undef PRINT_ALIAS_INSTR
1213
1214
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1215
  unsigned PrintMethodIdx, SStream *OS)
1216
0
{
1217
0
}
1218
1219
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1220
74.4k
{
1221
346k
  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1222
74.4k
  const char *AsmString;
1223
74.4k
  char *tmp, *AsmMnem, *AsmOps, *c;
1224
74.4k
  int OpIdx, PrintMethodIdx;
1225
74.4k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1226
74.4k
  switch (MCInst_getOpcode(MI)) {
1227
39.8k
  default: return NULL;
1228
2.56k
  case SP_BCOND:
1229
2.56k
    if (MCInst_getNumOperands(MI) == 2 &&
1230
2.56k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1231
2.56k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1232
      // (BCOND brtarget:$imm, 8)
1233
0
      AsmString = "ba $\x01";
1234
0
      break;
1235
0
    }
1236
2.56k
    if (MCInst_getNumOperands(MI) == 2 &&
1237
2.56k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1238
2.56k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1239
      // (BCOND brtarget:$imm, 0)
1240
576
      AsmString = "bn $\x01";
1241
576
      break;
1242
576
    }
1243
1.98k
    if (MCInst_getNumOperands(MI) == 2 &&
1244
1.98k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1245
1.98k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1246
      // (BCOND brtarget:$imm, 9)
1247
88
      AsmString = "bne $\x01";
1248
88
      break;
1249
88
    }
1250
1.90k
    if (MCInst_getNumOperands(MI) == 2 &&
1251
1.90k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1252
1.90k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1253
      // (BCOND brtarget:$imm, 1)
1254
79
      AsmString = "be $\x01";
1255
79
      break;
1256
79
    }
1257
1.82k
    if (MCInst_getNumOperands(MI) == 2 &&
1258
1.82k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1259
1.82k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1260
      // (BCOND brtarget:$imm, 10)
1261
45
      AsmString = "bg $\x01";
1262
45
      break;
1263
45
    }
1264
1.77k
    if (MCInst_getNumOperands(MI) == 2 &&
1265
1.77k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1266
1.77k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1267
      // (BCOND brtarget:$imm, 2)
1268
222
      AsmString = "ble $\x01";
1269
222
      break;
1270
222
    }
1271
1.55k
    if (MCInst_getNumOperands(MI) == 2 &&
1272
1.55k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1273
1.55k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1274
      // (BCOND brtarget:$imm, 11)
1275
199
      AsmString = "bge $\x01";
1276
199
      break;
1277
199
    }
1278
1.35k
    if (MCInst_getNumOperands(MI) == 2 &&
1279
1.35k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1280
1.35k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1281
      // (BCOND brtarget:$imm, 3)
1282
281
      AsmString = "bl $\x01";
1283
281
      break;
1284
281
    }
1285
1.07k
    if (MCInst_getNumOperands(MI) == 2 &&
1286
1.07k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1287
1.07k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1288
      // (BCOND brtarget:$imm, 12)
1289
75
      AsmString = "bgu $\x01";
1290
75
      break;
1291
75
    }
1292
1.00k
    if (MCInst_getNumOperands(MI) == 2 &&
1293
1.00k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1294
1.00k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1295
      // (BCOND brtarget:$imm, 4)
1296
116
      AsmString = "bleu $\x01";
1297
116
      break;
1298
116
    }
1299
884
    if (MCInst_getNumOperands(MI) == 2 &&
1300
884
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1301
884
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1302
      // (BCOND brtarget:$imm, 13)
1303
79
      AsmString = "bcc $\x01";
1304
79
      break;
1305
79
    }
1306
805
    if (MCInst_getNumOperands(MI) == 2 &&
1307
805
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1308
805
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1309
      // (BCOND brtarget:$imm, 5)
1310
97
      AsmString = "bcs $\x01";
1311
97
      break;
1312
97
    }
1313
708
    if (MCInst_getNumOperands(MI) == 2 &&
1314
708
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1315
708
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1316
      // (BCOND brtarget:$imm, 14)
1317
197
      AsmString = "bpos $\x01";
1318
197
      break;
1319
197
    }
1320
511
    if (MCInst_getNumOperands(MI) == 2 &&
1321
511
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1322
511
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1323
      // (BCOND brtarget:$imm, 6)
1324
282
      AsmString = "bneg $\x01";
1325
282
      break;
1326
282
    }
1327
229
    if (MCInst_getNumOperands(MI) == 2 &&
1328
229
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1329
229
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1330
      // (BCOND brtarget:$imm, 15)
1331
22
      AsmString = "bvc $\x01";
1332
22
      break;
1333
22
    }
1334
207
    if (MCInst_getNumOperands(MI) == 2 &&
1335
207
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1336
207
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1337
      // (BCOND brtarget:$imm, 7)
1338
207
      AsmString = "bvs $\x01";
1339
207
      break;
1340
207
    }
1341
0
    return NULL;
1342
2.03k
  case SP_BCONDA:
1343
2.03k
    if (MCInst_getNumOperands(MI) == 2 &&
1344
2.03k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1345
2.03k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1346
      // (BCONDA brtarget:$imm, 8)
1347
500
      AsmString = "ba,a $\x01";
1348
500
      break;
1349
500
    }
1350
1.53k
    if (MCInst_getNumOperands(MI) == 2 &&
1351
1.53k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1352
1.53k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1353
      // (BCONDA brtarget:$imm, 0)
1354
86
      AsmString = "bn,a $\x01";
1355
86
      break;
1356
86
    }
1357
1.44k
    if (MCInst_getNumOperands(MI) == 2 &&
1358
1.44k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1359
1.44k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1360
      // (BCONDA brtarget:$imm, 9)
1361
65
      AsmString = "bne,a $\x01";
1362
65
      break;
1363
65
    }
1364
1.38k
    if (MCInst_getNumOperands(MI) == 2 &&
1365
1.38k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1366
1.38k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1367
      // (BCONDA brtarget:$imm, 1)
1368
74
      AsmString = "be,a $\x01";
1369
74
      break;
1370
74
    }
1371
1.31k
    if (MCInst_getNumOperands(MI) == 2 &&
1372
1.31k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1373
1.31k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1374
      // (BCONDA brtarget:$imm, 10)
1375
83
      AsmString = "bg,a $\x01";
1376
83
      break;
1377
83
    }
1378
1.22k
    if (MCInst_getNumOperands(MI) == 2 &&
1379
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1380
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1381
      // (BCONDA brtarget:$imm, 2)
1382
237
      AsmString = "ble,a $\x01";
1383
237
      break;
1384
237
    }
1385
990
    if (MCInst_getNumOperands(MI) == 2 &&
1386
990
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1387
990
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1388
      // (BCONDA brtarget:$imm, 11)
1389
203
      AsmString = "bge,a $\x01";
1390
203
      break;
1391
203
    }
1392
787
    if (MCInst_getNumOperands(MI) == 2 &&
1393
787
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1394
787
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1395
      // (BCONDA brtarget:$imm, 3)
1396
41
      AsmString = "bl,a $\x01";
1397
41
      break;
1398
41
    }
1399
746
    if (MCInst_getNumOperands(MI) == 2 &&
1400
746
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1401
746
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1402
      // (BCONDA brtarget:$imm, 12)
1403
127
      AsmString = "bgu,a $\x01";
1404
127
      break;
1405
127
    }
1406
619
    if (MCInst_getNumOperands(MI) == 2 &&
1407
619
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1408
619
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1409
      // (BCONDA brtarget:$imm, 4)
1410
79
      AsmString = "bleu,a $\x01";
1411
79
      break;
1412
79
    }
1413
540
    if (MCInst_getNumOperands(MI) == 2 &&
1414
540
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1415
540
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1416
      // (BCONDA brtarget:$imm, 13)
1417
62
      AsmString = "bcc,a $\x01";
1418
62
      break;
1419
62
    }
1420
478
    if (MCInst_getNumOperands(MI) == 2 &&
1421
478
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1422
478
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1423
      // (BCONDA brtarget:$imm, 5)
1424
118
      AsmString = "bcs,a $\x01";
1425
118
      break;
1426
118
    }
1427
360
    if (MCInst_getNumOperands(MI) == 2 &&
1428
360
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1429
360
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1430
      // (BCONDA brtarget:$imm, 14)
1431
205
      AsmString = "bpos,a $\x01";
1432
205
      break;
1433
205
    }
1434
155
    if (MCInst_getNumOperands(MI) == 2 &&
1435
155
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1436
155
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1437
      // (BCONDA brtarget:$imm, 6)
1438
39
      AsmString = "bneg,a $\x01";
1439
39
      break;
1440
39
    }
1441
116
    if (MCInst_getNumOperands(MI) == 2 &&
1442
116
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1443
116
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1444
      // (BCONDA brtarget:$imm, 15)
1445
21
      AsmString = "bvc,a $\x01";
1446
21
      break;
1447
21
    }
1448
95
    if (MCInst_getNumOperands(MI) == 2 &&
1449
95
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1450
95
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1451
      // (BCONDA brtarget:$imm, 7)
1452
95
      AsmString = "bvs,a $\x01";
1453
95
      break;
1454
95
    }
1455
0
    return NULL;
1456
3.42k
  case SP_BPFCCANT:
1457
3.42k
    if (MCInst_getNumOperands(MI) == 3 &&
1458
3.42k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1459
3.42k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1460
3.42k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1461
3.42k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1462
      // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1463
128
      AsmString = "fba,a,pn $\x03, $\x01";
1464
128
      break;
1465
128
    }
1466
3.29k
    if (MCInst_getNumOperands(MI) == 3 &&
1467
3.29k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1468
3.29k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1469
3.29k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1470
3.29k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1471
      // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1472
393
      AsmString = "fbn,a,pn $\x03, $\x01";
1473
393
      break;
1474
393
    }
1475
2.90k
    if (MCInst_getNumOperands(MI) == 3 &&
1476
2.90k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1477
2.90k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1478
2.90k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1479
2.90k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1480
      // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1481
314
      AsmString = "fbu,a,pn $\x03, $\x01";
1482
314
      break;
1483
314
    }
1484
2.58k
    if (MCInst_getNumOperands(MI) == 3 &&
1485
2.58k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1486
2.58k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1487
2.58k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1488
2.58k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1489
      // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1490
125
      AsmString = "fbg,a,pn $\x03, $\x01";
1491
125
      break;
1492
125
    }
1493
2.46k
    if (MCInst_getNumOperands(MI) == 3 &&
1494
2.46k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1495
2.46k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1496
2.46k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1497
2.46k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1498
      // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1499
334
      AsmString = "fbug,a,pn $\x03, $\x01";
1500
334
      break;
1501
334
    }
1502
2.12k
    if (MCInst_getNumOperands(MI) == 3 &&
1503
2.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1504
2.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1505
2.12k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1506
2.12k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1507
      // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1508
221
      AsmString = "fbl,a,pn $\x03, $\x01";
1509
221
      break;
1510
221
    }
1511
1.90k
    if (MCInst_getNumOperands(MI) == 3 &&
1512
1.90k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1513
1.90k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1514
1.90k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1515
1.90k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1516
      // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1517
230
      AsmString = "fbul,a,pn $\x03, $\x01";
1518
230
      break;
1519
230
    }
1520
1.67k
    if (MCInst_getNumOperands(MI) == 3 &&
1521
1.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1522
1.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1523
1.67k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1524
1.67k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1525
      // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1526
282
      AsmString = "fblg,a,pn $\x03, $\x01";
1527
282
      break;
1528
282
    }
1529
1.39k
    if (MCInst_getNumOperands(MI) == 3 &&
1530
1.39k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1531
1.39k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1532
1.39k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1533
1.39k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1534
      // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1535
221
      AsmString = "fbne,a,pn $\x03, $\x01";
1536
221
      break;
1537
221
    }
1538
1.17k
    if (MCInst_getNumOperands(MI) == 3 &&
1539
1.17k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1540
1.17k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1541
1.17k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1542
1.17k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1543
      // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1544
340
      AsmString = "fbe,a,pn $\x03, $\x01";
1545
340
      break;
1546
340
    }
1547
833
    if (MCInst_getNumOperands(MI) == 3 &&
1548
833
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1549
833
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1550
833
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1551
833
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1552
      // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1553
38
      AsmString = "fbue,a,pn $\x03, $\x01";
1554
38
      break;
1555
38
    }
1556
795
    if (MCInst_getNumOperands(MI) == 3 &&
1557
795
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1558
795
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1559
795
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1560
795
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1561
      // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1562
79
      AsmString = "fbge,a,pn $\x03, $\x01";
1563
79
      break;
1564
79
    }
1565
716
    if (MCInst_getNumOperands(MI) == 3 &&
1566
716
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1567
716
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1568
716
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1569
716
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1570
      // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1571
88
      AsmString = "fbuge,a,pn $\x03, $\x01";
1572
88
      break;
1573
88
    }
1574
628
    if (MCInst_getNumOperands(MI) == 3 &&
1575
628
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1576
628
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1577
628
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1578
628
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1579
      // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1580
177
      AsmString = "fble,a,pn $\x03, $\x01";
1581
177
      break;
1582
177
    }
1583
451
    if (MCInst_getNumOperands(MI) == 3 &&
1584
451
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1585
451
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1586
451
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1587
451
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1588
      // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1589
164
      AsmString = "fbule,a,pn $\x03, $\x01";
1590
164
      break;
1591
164
    }
1592
287
    if (MCInst_getNumOperands(MI) == 3 &&
1593
287
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1594
287
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1595
287
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1596
287
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1597
      // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1598
287
      AsmString = "fbo,a,pn $\x03, $\x01";
1599
287
      break;
1600
287
    }
1601
0
    return NULL;
1602
2.78k
  case SP_BPFCCNT:
1603
2.78k
    if (MCInst_getNumOperands(MI) == 3 &&
1604
2.78k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1605
2.78k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1606
2.78k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1607
2.78k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1608
      // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1609
127
      AsmString = "fba,pn $\x03, $\x01";
1610
127
      break;
1611
127
    }
1612
2.65k
    if (MCInst_getNumOperands(MI) == 3 &&
1613
2.65k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1614
2.65k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1615
2.65k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1616
2.65k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1617
      // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1618
67
      AsmString = "fbn,pn $\x03, $\x01";
1619
67
      break;
1620
67
    }
1621
2.59k
    if (MCInst_getNumOperands(MI) == 3 &&
1622
2.59k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
2.59k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1624
2.59k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1625
2.59k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1626
      // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1627
244
      AsmString = "fbu,pn $\x03, $\x01";
1628
244
      break;
1629
244
    }
1630
2.34k
    if (MCInst_getNumOperands(MI) == 3 &&
1631
2.34k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1632
2.34k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1633
2.34k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1634
2.34k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1635
      // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1636
257
      AsmString = "fbg,pn $\x03, $\x01";
1637
257
      break;
1638
257
    }
1639
2.08k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
2.08k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1641
2.08k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1642
2.08k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1643
2.08k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1644
      // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1645
97
      AsmString = "fbug,pn $\x03, $\x01";
1646
97
      break;
1647
97
    }
1648
1.99k
    if (MCInst_getNumOperands(MI) == 3 &&
1649
1.99k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1650
1.99k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1651
1.99k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1652
1.99k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1653
      // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1654
340
      AsmString = "fbl,pn $\x03, $\x01";
1655
340
      break;
1656
340
    }
1657
1.65k
    if (MCInst_getNumOperands(MI) == 3 &&
1658
1.65k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1659
1.65k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1660
1.65k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1661
1.65k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1662
      // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1663
211
      AsmString = "fbul,pn $\x03, $\x01";
1664
211
      break;
1665
211
    }
1666
1.44k
    if (MCInst_getNumOperands(MI) == 3 &&
1667
1.44k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1668
1.44k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1669
1.44k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1670
1.44k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1671
      // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1672
208
      AsmString = "fblg,pn $\x03, $\x01";
1673
208
      break;
1674
208
    }
1675
1.23k
    if (MCInst_getNumOperands(MI) == 3 &&
1676
1.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1677
1.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1678
1.23k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1679
1.23k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1680
      // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1681
147
      AsmString = "fbne,pn $\x03, $\x01";
1682
147
      break;
1683
147
    }
1684
1.08k
    if (MCInst_getNumOperands(MI) == 3 &&
1685
1.08k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1686
1.08k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1687
1.08k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1688
1.08k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1689
      // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1690
244
      AsmString = "fbe,pn $\x03, $\x01";
1691
244
      break;
1692
244
    }
1693
842
    if (MCInst_getNumOperands(MI) == 3 &&
1694
842
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1695
842
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1696
842
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1697
842
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1698
      // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1699
212
      AsmString = "fbue,pn $\x03, $\x01";
1700
212
      break;
1701
212
    }
1702
630
    if (MCInst_getNumOperands(MI) == 3 &&
1703
630
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1704
630
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1705
630
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1706
630
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1707
      // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1708
38
      AsmString = "fbge,pn $\x03, $\x01";
1709
38
      break;
1710
38
    }
1711
592
    if (MCInst_getNumOperands(MI) == 3 &&
1712
592
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1713
592
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1714
592
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1715
592
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1716
      // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1717
201
      AsmString = "fbuge,pn $\x03, $\x01";
1718
201
      break;
1719
201
    }
1720
391
    if (MCInst_getNumOperands(MI) == 3 &&
1721
391
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1722
391
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1723
391
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1724
391
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1725
      // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1726
67
      AsmString = "fble,pn $\x03, $\x01";
1727
67
      break;
1728
67
    }
1729
324
    if (MCInst_getNumOperands(MI) == 3 &&
1730
324
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1731
324
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1732
324
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1733
324
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1734
      // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1735
124
      AsmString = "fbule,pn $\x03, $\x01";
1736
124
      break;
1737
124
    }
1738
200
    if (MCInst_getNumOperands(MI) == 3 &&
1739
200
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1740
200
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1741
200
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1742
200
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1743
      // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1744
200
      AsmString = "fbo,pn $\x03, $\x01";
1745
200
      break;
1746
200
    }
1747
0
    return NULL;
1748
2.23k
  case SP_BPICCANT:
1749
2.23k
    if (MCInst_getNumOperands(MI) == 2 &&
1750
2.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1751
2.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1752
      // (BPICCANT brtarget:$imm, 8)
1753
209
      AsmString = "ba,a,pn %icc, $\x01";
1754
209
      break;
1755
209
    }
1756
2.02k
    if (MCInst_getNumOperands(MI) == 2 &&
1757
2.02k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
2.02k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1759
      // (BPICCANT brtarget:$imm, 0)
1760
94
      AsmString = "bn,a,pn %icc, $\x01";
1761
94
      break;
1762
94
    }
1763
1.92k
    if (MCInst_getNumOperands(MI) == 2 &&
1764
1.92k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1765
1.92k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1766
      // (BPICCANT brtarget:$imm, 9)
1767
138
      AsmString = "bne,a,pn %icc, $\x01";
1768
138
      break;
1769
138
    }
1770
1.79k
    if (MCInst_getNumOperands(MI) == 2 &&
1771
1.79k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1772
1.79k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1773
      // (BPICCANT brtarget:$imm, 1)
1774
40
      AsmString = "be,a,pn %icc, $\x01";
1775
40
      break;
1776
40
    }
1777
1.75k
    if (MCInst_getNumOperands(MI) == 2 &&
1778
1.75k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1779
1.75k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1780
      // (BPICCANT brtarget:$imm, 10)
1781
93
      AsmString = "bg,a,pn %icc, $\x01";
1782
93
      break;
1783
93
    }
1784
1.65k
    if (MCInst_getNumOperands(MI) == 2 &&
1785
1.65k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1786
1.65k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1787
      // (BPICCANT brtarget:$imm, 2)
1788
73
      AsmString = "ble,a,pn %icc, $\x01";
1789
73
      break;
1790
73
    }
1791
1.58k
    if (MCInst_getNumOperands(MI) == 2 &&
1792
1.58k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1793
1.58k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1794
      // (BPICCANT brtarget:$imm, 11)
1795
75
      AsmString = "bge,a,pn %icc, $\x01";
1796
75
      break;
1797
75
    }
1798
1.50k
    if (MCInst_getNumOperands(MI) == 2 &&
1799
1.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1800
1.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1801
      // (BPICCANT brtarget:$imm, 3)
1802
80
      AsmString = "bl,a,pn %icc, $\x01";
1803
80
      break;
1804
80
    }
1805
1.42k
    if (MCInst_getNumOperands(MI) == 2 &&
1806
1.42k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1807
1.42k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1808
      // (BPICCANT brtarget:$imm, 12)
1809
225
      AsmString = "bgu,a,pn %icc, $\x01";
1810
225
      break;
1811
225
    }
1812
1.20k
    if (MCInst_getNumOperands(MI) == 2 &&
1813
1.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1814
1.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1815
      // (BPICCANT brtarget:$imm, 4)
1816
329
      AsmString = "bleu,a,pn %icc, $\x01";
1817
329
      break;
1818
329
    }
1819
875
    if (MCInst_getNumOperands(MI) == 2 &&
1820
875
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1821
875
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1822
      // (BPICCANT brtarget:$imm, 13)
1823
210
      AsmString = "bcc,a,pn %icc, $\x01";
1824
210
      break;
1825
210
    }
1826
665
    if (MCInst_getNumOperands(MI) == 2 &&
1827
665
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1828
665
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1829
      // (BPICCANT brtarget:$imm, 5)
1830
118
      AsmString = "bcs,a,pn %icc, $\x01";
1831
118
      break;
1832
118
    }
1833
547
    if (MCInst_getNumOperands(MI) == 2 &&
1834
547
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1835
547
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1836
      // (BPICCANT brtarget:$imm, 14)
1837
222
      AsmString = "bpos,a,pn %icc, $\x01";
1838
222
      break;
1839
222
    }
1840
325
    if (MCInst_getNumOperands(MI) == 2 &&
1841
325
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1842
325
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1843
      // (BPICCANT brtarget:$imm, 6)
1844
81
      AsmString = "bneg,a,pn %icc, $\x01";
1845
81
      break;
1846
81
    }
1847
244
    if (MCInst_getNumOperands(MI) == 2 &&
1848
244
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1849
244
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1850
      // (BPICCANT brtarget:$imm, 15)
1851
104
      AsmString = "bvc,a,pn %icc, $\x01";
1852
104
      break;
1853
104
    }
1854
140
    if (MCInst_getNumOperands(MI) == 2 &&
1855
140
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1856
140
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1857
      // (BPICCANT brtarget:$imm, 7)
1858
140
      AsmString = "bvs,a,pn %icc, $\x01";
1859
140
      break;
1860
140
    }
1861
0
    return NULL;
1862
4.33k
  case SP_BPICCNT:
1863
4.33k
    if (MCInst_getNumOperands(MI) == 2 &&
1864
4.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1865
4.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1866
      // (BPICCNT brtarget:$imm, 8)
1867
296
      AsmString = "ba,pn %icc, $\x01";
1868
296
      break;
1869
296
    }
1870
4.03k
    if (MCInst_getNumOperands(MI) == 2 &&
1871
4.03k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1872
4.03k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1873
      // (BPICCNT brtarget:$imm, 0)
1874
303
      AsmString = "bn,pn %icc, $\x01";
1875
303
      break;
1876
303
    }
1877
3.73k
    if (MCInst_getNumOperands(MI) == 2 &&
1878
3.73k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1879
3.73k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1880
      // (BPICCNT brtarget:$imm, 9)
1881
74
      AsmString = "bne,pn %icc, $\x01";
1882
74
      break;
1883
74
    }
1884
3.66k
    if (MCInst_getNumOperands(MI) == 2 &&
1885
3.66k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1886
3.66k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1887
      // (BPICCNT brtarget:$imm, 1)
1888
1.56k
      AsmString = "be,pn %icc, $\x01";
1889
1.56k
      break;
1890
1.56k
    }
1891
2.09k
    if (MCInst_getNumOperands(MI) == 2 &&
1892
2.09k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1893
2.09k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1894
      // (BPICCNT brtarget:$imm, 10)
1895
41
      AsmString = "bg,pn %icc, $\x01";
1896
41
      break;
1897
41
    }
1898
2.05k
    if (MCInst_getNumOperands(MI) == 2 &&
1899
2.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1900
2.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1901
      // (BPICCNT brtarget:$imm, 2)
1902
95
      AsmString = "ble,pn %icc, $\x01";
1903
95
      break;
1904
95
    }
1905
1.96k
    if (MCInst_getNumOperands(MI) == 2 &&
1906
1.96k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1907
1.96k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1908
      // (BPICCNT brtarget:$imm, 11)
1909
97
      AsmString = "bge,pn %icc, $\x01";
1910
97
      break;
1911
97
    }
1912
1.86k
    if (MCInst_getNumOperands(MI) == 2 &&
1913
1.86k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1914
1.86k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1915
      // (BPICCNT brtarget:$imm, 3)
1916
73
      AsmString = "bl,pn %icc, $\x01";
1917
73
      break;
1918
73
    }
1919
1.79k
    if (MCInst_getNumOperands(MI) == 2 &&
1920
1.79k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1921
1.79k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1922
      // (BPICCNT brtarget:$imm, 12)
1923
70
      AsmString = "bgu,pn %icc, $\x01";
1924
70
      break;
1925
70
    }
1926
1.72k
    if (MCInst_getNumOperands(MI) == 2 &&
1927
1.72k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1928
1.72k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1929
      // (BPICCNT brtarget:$imm, 4)
1930
203
      AsmString = "bleu,pn %icc, $\x01";
1931
203
      break;
1932
203
    }
1933
1.51k
    if (MCInst_getNumOperands(MI) == 2 &&
1934
1.51k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1935
1.51k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1936
      // (BPICCNT brtarget:$imm, 13)
1937
84
      AsmString = "bcc,pn %icc, $\x01";
1938
84
      break;
1939
84
    }
1940
1.43k
    if (MCInst_getNumOperands(MI) == 2 &&
1941
1.43k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1942
1.43k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1943
      // (BPICCNT brtarget:$imm, 5)
1944
228
      AsmString = "bcs,pn %icc, $\x01";
1945
228
      break;
1946
228
    }
1947
1.20k
    if (MCInst_getNumOperands(MI) == 2 &&
1948
1.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1949
1.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1950
      // (BPICCNT brtarget:$imm, 14)
1951
68
      AsmString = "bpos,pn %icc, $\x01";
1952
68
      break;
1953
68
    }
1954
1.13k
    if (MCInst_getNumOperands(MI) == 2 &&
1955
1.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1956
1.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1957
      // (BPICCNT brtarget:$imm, 6)
1958
254
      AsmString = "bneg,pn %icc, $\x01";
1959
254
      break;
1960
254
    }
1961
885
    if (MCInst_getNumOperands(MI) == 2 &&
1962
885
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1963
885
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1964
      // (BPICCNT brtarget:$imm, 15)
1965
74
      AsmString = "bvc,pn %icc, $\x01";
1966
74
      break;
1967
74
    }
1968
811
    if (MCInst_getNumOperands(MI) == 2 &&
1969
811
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1970
811
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1971
      // (BPICCNT brtarget:$imm, 7)
1972
811
      AsmString = "bvs,pn %icc, $\x01";
1973
811
      break;
1974
811
    }
1975
0
    return NULL;
1976
2.27k
  case SP_BPXCCANT:
1977
2.27k
    if (MCInst_getNumOperands(MI) == 2 &&
1978
2.27k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1979
2.27k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1980
      // (BPXCCANT brtarget:$imm, 8)
1981
35
      AsmString = "ba,a,pn %xcc, $\x01";
1982
35
      break;
1983
35
    }
1984
2.23k
    if (MCInst_getNumOperands(MI) == 2 &&
1985
2.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1986
2.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1987
      // (BPXCCANT brtarget:$imm, 0)
1988
91
      AsmString = "bn,a,pn %xcc, $\x01";
1989
91
      break;
1990
91
    }
1991
2.14k
    if (MCInst_getNumOperands(MI) == 2 &&
1992
2.14k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1993
2.14k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1994
      // (BPXCCANT brtarget:$imm, 9)
1995
75
      AsmString = "bne,a,pn %xcc, $\x01";
1996
75
      break;
1997
75
    }
1998
2.07k
    if (MCInst_getNumOperands(MI) == 2 &&
1999
2.07k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2000
2.07k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2001
      // (BPXCCANT brtarget:$imm, 1)
2002
44
      AsmString = "be,a,pn %xcc, $\x01";
2003
44
      break;
2004
44
    }
2005
2.02k
    if (MCInst_getNumOperands(MI) == 2 &&
2006
2.02k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2007
2.02k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2008
      // (BPXCCANT brtarget:$imm, 10)
2009
74
      AsmString = "bg,a,pn %xcc, $\x01";
2010
74
      break;
2011
74
    }
2012
1.95k
    if (MCInst_getNumOperands(MI) == 2 &&
2013
1.95k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2014
1.95k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2015
      // (BPXCCANT brtarget:$imm, 2)
2016
73
      AsmString = "ble,a,pn %xcc, $\x01";
2017
73
      break;
2018
73
    }
2019
1.88k
    if (MCInst_getNumOperands(MI) == 2 &&
2020
1.88k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2021
1.88k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2022
      // (BPXCCANT brtarget:$imm, 11)
2023
47
      AsmString = "bge,a,pn %xcc, $\x01";
2024
47
      break;
2025
47
    }
2026
1.83k
    if (MCInst_getNumOperands(MI) == 2 &&
2027
1.83k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2028
1.83k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2029
      // (BPXCCANT brtarget:$imm, 3)
2030
70
      AsmString = "bl,a,pn %xcc, $\x01";
2031
70
      break;
2032
70
    }
2033
1.76k
    if (MCInst_getNumOperands(MI) == 2 &&
2034
1.76k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2035
1.76k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2036
      // (BPXCCANT brtarget:$imm, 12)
2037
231
      AsmString = "bgu,a,pn %xcc, $\x01";
2038
231
      break;
2039
231
    }
2040
1.53k
    if (MCInst_getNumOperands(MI) == 2 &&
2041
1.53k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2042
1.53k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2043
      // (BPXCCANT brtarget:$imm, 4)
2044
466
      AsmString = "bleu,a,pn %xcc, $\x01";
2045
466
      break;
2046
466
    }
2047
1.06k
    if (MCInst_getNumOperands(MI) == 2 &&
2048
1.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2049
1.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2050
      // (BPXCCANT brtarget:$imm, 13)
2051
42
      AsmString = "bcc,a,pn %xcc, $\x01";
2052
42
      break;
2053
42
    }
2054
1.02k
    if (MCInst_getNumOperands(MI) == 2 &&
2055
1.02k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2056
1.02k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2057
      // (BPXCCANT brtarget:$imm, 5)
2058
258
      AsmString = "bcs,a,pn %xcc, $\x01";
2059
258
      break;
2060
258
    }
2061
766
    if (MCInst_getNumOperands(MI) == 2 &&
2062
766
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2063
766
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2064
      // (BPXCCANT brtarget:$imm, 14)
2065
104
      AsmString = "bpos,a,pn %xcc, $\x01";
2066
104
      break;
2067
104
    }
2068
662
    if (MCInst_getNumOperands(MI) == 2 &&
2069
662
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2070
662
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2071
      // (BPXCCANT brtarget:$imm, 6)
2072
116
      AsmString = "bneg,a,pn %xcc, $\x01";
2073
116
      break;
2074
116
    }
2075
546
    if (MCInst_getNumOperands(MI) == 2 &&
2076
546
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2077
546
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2078
      // (BPXCCANT brtarget:$imm, 15)
2079
154
      AsmString = "bvc,a,pn %xcc, $\x01";
2080
154
      break;
2081
154
    }
2082
392
    if (MCInst_getNumOperands(MI) == 2 &&
2083
392
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2084
392
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2085
      // (BPXCCANT brtarget:$imm, 7)
2086
392
      AsmString = "bvs,a,pn %xcc, $\x01";
2087
392
      break;
2088
392
    }
2089
0
    return NULL;
2090
1.86k
  case SP_BPXCCNT:
2091
1.86k
    if (MCInst_getNumOperands(MI) == 2 &&
2092
1.86k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2093
1.86k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2094
      // (BPXCCNT brtarget:$imm, 8)
2095
75
      AsmString = "ba,pn %xcc, $\x01";
2096
75
      break;
2097
75
    }
2098
1.78k
    if (MCInst_getNumOperands(MI) == 2 &&
2099
1.78k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2100
1.78k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2101
      // (BPXCCNT brtarget:$imm, 0)
2102
212
      AsmString = "bn,pn %xcc, $\x01";
2103
212
      break;
2104
212
    }
2105
1.57k
    if (MCInst_getNumOperands(MI) == 2 &&
2106
1.57k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2107
1.57k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2108
      // (BPXCCNT brtarget:$imm, 9)
2109
87
      AsmString = "bne,pn %xcc, $\x01";
2110
87
      break;
2111
87
    }
2112
1.49k
    if (MCInst_getNumOperands(MI) == 2 &&
2113
1.49k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2114
1.49k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2115
      // (BPXCCNT brtarget:$imm, 1)
2116
241
      AsmString = "be,pn %xcc, $\x01";
2117
241
      break;
2118
241
    }
2119
1.24k
    if (MCInst_getNumOperands(MI) == 2 &&
2120
1.24k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2121
1.24k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2122
      // (BPXCCNT brtarget:$imm, 10)
2123
27
      AsmString = "bg,pn %xcc, $\x01";
2124
27
      break;
2125
27
    }
2126
1.22k
    if (MCInst_getNumOperands(MI) == 2 &&
2127
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2128
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2129
      // (BPXCCNT brtarget:$imm, 2)
2130
121
      AsmString = "ble,pn %xcc, $\x01";
2131
121
      break;
2132
121
    }
2133
1.10k
    if (MCInst_getNumOperands(MI) == 2 &&
2134
1.10k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2135
1.10k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2136
      // (BPXCCNT brtarget:$imm, 11)
2137
15
      AsmString = "bge,pn %xcc, $\x01";
2138
15
      break;
2139
15
    }
2140
1.08k
    if (MCInst_getNumOperands(MI) == 2 &&
2141
1.08k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2142
1.08k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2143
      // (BPXCCNT brtarget:$imm, 3)
2144
44
      AsmString = "bl,pn %xcc, $\x01";
2145
44
      break;
2146
44
    }
2147
1.04k
    if (MCInst_getNumOperands(MI) == 2 &&
2148
1.04k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2149
1.04k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2150
      // (BPXCCNT brtarget:$imm, 12)
2151
139
      AsmString = "bgu,pn %xcc, $\x01";
2152
139
      break;
2153
139
    }
2154
903
    if (MCInst_getNumOperands(MI) == 2 &&
2155
903
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2156
903
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2157
      // (BPXCCNT brtarget:$imm, 4)
2158
135
      AsmString = "bleu,pn %xcc, $\x01";
2159
135
      break;
2160
135
    }
2161
768
    if (MCInst_getNumOperands(MI) == 2 &&
2162
768
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2163
768
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2164
      // (BPXCCNT brtarget:$imm, 13)
2165
478
      AsmString = "bcc,pn %xcc, $\x01";
2166
478
      break;
2167
478
    }
2168
290
    if (MCInst_getNumOperands(MI) == 2 &&
2169
290
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2170
290
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2171
      // (BPXCCNT brtarget:$imm, 5)
2172
97
      AsmString = "bcs,pn %xcc, $\x01";
2173
97
      break;
2174
97
    }
2175
193
    if (MCInst_getNumOperands(MI) == 2 &&
2176
193
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2177
193
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2178
      // (BPXCCNT brtarget:$imm, 14)
2179
37
      AsmString = "bpos,pn %xcc, $\x01";
2180
37
      break;
2181
37
    }
2182
156
    if (MCInst_getNumOperands(MI) == 2 &&
2183
156
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2184
156
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2185
      // (BPXCCNT brtarget:$imm, 6)
2186
47
      AsmString = "bneg,pn %xcc, $\x01";
2187
47
      break;
2188
47
    }
2189
109
    if (MCInst_getNumOperands(MI) == 2 &&
2190
109
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2191
109
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2192
      // (BPXCCNT brtarget:$imm, 15)
2193
39
      AsmString = "bvc,pn %xcc, $\x01";
2194
39
      break;
2195
39
    }
2196
70
    if (MCInst_getNumOperands(MI) == 2 &&
2197
70
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2198
70
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2199
      // (BPXCCNT brtarget:$imm, 7)
2200
70
      AsmString = "bvs,pn %xcc, $\x01";
2201
70
      break;
2202
70
    }
2203
0
    return NULL;
2204
108
  case SP_FMOVD_ICC:
2205
108
    if (MCInst_getNumOperands(MI) == 3 &&
2206
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2207
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2208
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2209
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2210
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2211
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2212
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2213
0
      AsmString = "fmovda %icc, $\x02, $\x01";
2214
0
      break;
2215
0
    }
2216
108
    if (MCInst_getNumOperands(MI) == 3 &&
2217
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2218
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2219
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2220
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2221
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2222
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2223
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2224
0
      AsmString = "fmovdn %icc, $\x02, $\x01";
2225
0
      break;
2226
0
    }
2227
108
    if (MCInst_getNumOperands(MI) == 3 &&
2228
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2229
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2230
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2231
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2232
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2233
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2234
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2235
0
      AsmString = "fmovdne %icc, $\x02, $\x01";
2236
0
      break;
2237
0
    }
2238
108
    if (MCInst_getNumOperands(MI) == 3 &&
2239
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2240
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2241
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2242
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2243
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2244
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2245
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2246
0
      AsmString = "fmovde %icc, $\x02, $\x01";
2247
0
      break;
2248
0
    }
2249
108
    if (MCInst_getNumOperands(MI) == 3 &&
2250
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2251
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2252
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2253
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2254
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2255
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2256
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2257
0
      AsmString = "fmovdg %icc, $\x02, $\x01";
2258
0
      break;
2259
0
    }
2260
108
    if (MCInst_getNumOperands(MI) == 3 &&
2261
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2262
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2263
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2264
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2265
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2266
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2267
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2268
0
      AsmString = "fmovdle %icc, $\x02, $\x01";
2269
0
      break;
2270
0
    }
2271
108
    if (MCInst_getNumOperands(MI) == 3 &&
2272
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2273
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2274
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2275
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2276
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2277
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2278
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2279
0
      AsmString = "fmovdge %icc, $\x02, $\x01";
2280
0
      break;
2281
0
    }
2282
108
    if (MCInst_getNumOperands(MI) == 3 &&
2283
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2285
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2287
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2288
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2289
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2290
0
      AsmString = "fmovdl %icc, $\x02, $\x01";
2291
0
      break;
2292
0
    }
2293
108
    if (MCInst_getNumOperands(MI) == 3 &&
2294
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2295
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2296
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2297
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2298
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2299
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2300
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2301
0
      AsmString = "fmovdgu %icc, $\x02, $\x01";
2302
0
      break;
2303
0
    }
2304
108
    if (MCInst_getNumOperands(MI) == 3 &&
2305
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2306
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2307
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2308
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2309
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2310
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2311
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2312
0
      AsmString = "fmovdleu %icc, $\x02, $\x01";
2313
0
      break;
2314
0
    }
2315
108
    if (MCInst_getNumOperands(MI) == 3 &&
2316
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2317
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2318
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2319
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2320
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2321
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2322
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2323
0
      AsmString = "fmovdcc %icc, $\x02, $\x01";
2324
0
      break;
2325
0
    }
2326
108
    if (MCInst_getNumOperands(MI) == 3 &&
2327
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2328
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2329
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2330
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2331
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2332
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2333
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2334
0
      AsmString = "fmovdcs %icc, $\x02, $\x01";
2335
0
      break;
2336
0
    }
2337
108
    if (MCInst_getNumOperands(MI) == 3 &&
2338
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2339
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2340
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2341
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2342
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2343
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2344
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2345
0
      AsmString = "fmovdpos %icc, $\x02, $\x01";
2346
0
      break;
2347
0
    }
2348
108
    if (MCInst_getNumOperands(MI) == 3 &&
2349
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2350
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2351
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2352
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2353
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2354
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2355
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2356
0
      AsmString = "fmovdneg %icc, $\x02, $\x01";
2357
0
      break;
2358
0
    }
2359
108
    if (MCInst_getNumOperands(MI) == 3 &&
2360
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2361
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2362
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2363
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2364
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2365
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2366
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2367
0
      AsmString = "fmovdvc %icc, $\x02, $\x01";
2368
0
      break;
2369
0
    }
2370
108
    if (MCInst_getNumOperands(MI) == 3 &&
2371
108
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2372
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2373
108
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2374
108
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2375
108
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2376
108
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2377
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2378
0
      AsmString = "fmovdvs %icc, $\x02, $\x01";
2379
0
      break;
2380
0
    }
2381
108
    return NULL;
2382
19
  case SP_FMOVD_XCC:
2383
19
    if (MCInst_getNumOperands(MI) == 3 &&
2384
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2385
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2386
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2387
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2388
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2389
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2390
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2391
0
      AsmString = "fmovda %xcc, $\x02, $\x01";
2392
0
      break;
2393
0
    }
2394
19
    if (MCInst_getNumOperands(MI) == 3 &&
2395
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2396
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2397
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2398
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2399
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2400
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2401
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2402
0
      AsmString = "fmovdn %xcc, $\x02, $\x01";
2403
0
      break;
2404
0
    }
2405
19
    if (MCInst_getNumOperands(MI) == 3 &&
2406
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2407
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2408
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2409
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2410
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2411
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2412
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2413
0
      AsmString = "fmovdne %xcc, $\x02, $\x01";
2414
0
      break;
2415
0
    }
2416
19
    if (MCInst_getNumOperands(MI) == 3 &&
2417
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2418
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2419
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2420
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2421
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2422
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2423
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2424
0
      AsmString = "fmovde %xcc, $\x02, $\x01";
2425
0
      break;
2426
0
    }
2427
19
    if (MCInst_getNumOperands(MI) == 3 &&
2428
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2429
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2430
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2431
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2432
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2433
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2434
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2435
0
      AsmString = "fmovdg %xcc, $\x02, $\x01";
2436
0
      break;
2437
0
    }
2438
19
    if (MCInst_getNumOperands(MI) == 3 &&
2439
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2440
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2441
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2442
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2443
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2444
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2445
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2446
0
      AsmString = "fmovdle %xcc, $\x02, $\x01";
2447
0
      break;
2448
0
    }
2449
19
    if (MCInst_getNumOperands(MI) == 3 &&
2450
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2451
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2452
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2453
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2454
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2455
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2456
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2457
0
      AsmString = "fmovdge %xcc, $\x02, $\x01";
2458
0
      break;
2459
0
    }
2460
19
    if (MCInst_getNumOperands(MI) == 3 &&
2461
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2462
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2463
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2464
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2465
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2466
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2467
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2468
0
      AsmString = "fmovdl %xcc, $\x02, $\x01";
2469
0
      break;
2470
0
    }
2471
19
    if (MCInst_getNumOperands(MI) == 3 &&
2472
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2473
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2474
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2475
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2476
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2477
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2478
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2479
0
      AsmString = "fmovdgu %xcc, $\x02, $\x01";
2480
0
      break;
2481
0
    }
2482
19
    if (MCInst_getNumOperands(MI) == 3 &&
2483
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2484
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2485
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2486
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2487
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2488
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2489
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2490
0
      AsmString = "fmovdleu %xcc, $\x02, $\x01";
2491
0
      break;
2492
0
    }
2493
19
    if (MCInst_getNumOperands(MI) == 3 &&
2494
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2495
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2496
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2497
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2498
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2499
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2500
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2501
0
      AsmString = "fmovdcc %xcc, $\x02, $\x01";
2502
0
      break;
2503
0
    }
2504
19
    if (MCInst_getNumOperands(MI) == 3 &&
2505
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2506
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2507
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2508
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2509
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2510
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2511
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2512
0
      AsmString = "fmovdcs %xcc, $\x02, $\x01";
2513
0
      break;
2514
0
    }
2515
19
    if (MCInst_getNumOperands(MI) == 3 &&
2516
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2518
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2519
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2520
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2521
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2522
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2523
0
      AsmString = "fmovdpos %xcc, $\x02, $\x01";
2524
0
      break;
2525
0
    }
2526
19
    if (MCInst_getNumOperands(MI) == 3 &&
2527
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2528
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2529
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2530
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2531
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2532
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2533
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2534
0
      AsmString = "fmovdneg %xcc, $\x02, $\x01";
2535
0
      break;
2536
0
    }
2537
19
    if (MCInst_getNumOperands(MI) == 3 &&
2538
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2539
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2540
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2541
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2542
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2543
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2544
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2545
0
      AsmString = "fmovdvc %xcc, $\x02, $\x01";
2546
0
      break;
2547
0
    }
2548
19
    if (MCInst_getNumOperands(MI) == 3 &&
2549
19
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2550
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2551
19
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2552
19
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2553
19
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2554
19
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2555
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2556
0
      AsmString = "fmovdvs %xcc, $\x02, $\x01";
2557
0
      break;
2558
0
    }
2559
19
    return NULL;
2560
402
  case SP_FMOVQ_ICC:
2561
402
    if (MCInst_getNumOperands(MI) == 3 &&
2562
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2563
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2564
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2565
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2566
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2567
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2568
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2569
0
      AsmString = "fmovqa %icc, $\x02, $\x01";
2570
0
      break;
2571
0
    }
2572
402
    if (MCInst_getNumOperands(MI) == 3 &&
2573
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2574
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2575
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2576
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2577
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2578
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2579
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2580
0
      AsmString = "fmovqn %icc, $\x02, $\x01";
2581
0
      break;
2582
0
    }
2583
402
    if (MCInst_getNumOperands(MI) == 3 &&
2584
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2585
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2586
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2587
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2588
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2589
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2590
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2591
0
      AsmString = "fmovqne %icc, $\x02, $\x01";
2592
0
      break;
2593
0
    }
2594
402
    if (MCInst_getNumOperands(MI) == 3 &&
2595
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2596
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2597
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2598
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2599
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2600
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2601
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2602
0
      AsmString = "fmovqe %icc, $\x02, $\x01";
2603
0
      break;
2604
0
    }
2605
402
    if (MCInst_getNumOperands(MI) == 3 &&
2606
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2607
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2608
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2609
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2610
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2611
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2612
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2613
0
      AsmString = "fmovqg %icc, $\x02, $\x01";
2614
0
      break;
2615
0
    }
2616
402
    if (MCInst_getNumOperands(MI) == 3 &&
2617
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2618
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2619
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2620
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2621
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2622
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2623
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2624
0
      AsmString = "fmovqle %icc, $\x02, $\x01";
2625
0
      break;
2626
0
    }
2627
402
    if (MCInst_getNumOperands(MI) == 3 &&
2628
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2629
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2630
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2631
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2632
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2633
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2634
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2635
0
      AsmString = "fmovqge %icc, $\x02, $\x01";
2636
0
      break;
2637
0
    }
2638
402
    if (MCInst_getNumOperands(MI) == 3 &&
2639
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2640
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2641
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2642
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2643
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2644
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2645
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2646
0
      AsmString = "fmovql %icc, $\x02, $\x01";
2647
0
      break;
2648
0
    }
2649
402
    if (MCInst_getNumOperands(MI) == 3 &&
2650
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2651
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2652
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2653
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2654
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2655
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2656
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2657
0
      AsmString = "fmovqgu %icc, $\x02, $\x01";
2658
0
      break;
2659
0
    }
2660
402
    if (MCInst_getNumOperands(MI) == 3 &&
2661
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2662
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2663
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2664
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2665
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2666
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2667
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2668
0
      AsmString = "fmovqleu %icc, $\x02, $\x01";
2669
0
      break;
2670
0
    }
2671
402
    if (MCInst_getNumOperands(MI) == 3 &&
2672
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2673
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2674
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2675
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2676
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2677
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2678
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2679
0
      AsmString = "fmovqcc %icc, $\x02, $\x01";
2680
0
      break;
2681
0
    }
2682
402
    if (MCInst_getNumOperands(MI) == 3 &&
2683
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2684
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2685
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2686
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2687
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2688
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2689
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2690
0
      AsmString = "fmovqcs %icc, $\x02, $\x01";
2691
0
      break;
2692
0
    }
2693
402
    if (MCInst_getNumOperands(MI) == 3 &&
2694
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2695
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2696
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2697
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2698
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2699
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2700
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2701
0
      AsmString = "fmovqpos %icc, $\x02, $\x01";
2702
0
      break;
2703
0
    }
2704
402
    if (MCInst_getNumOperands(MI) == 3 &&
2705
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2706
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2707
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2708
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2709
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2710
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2711
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2712
0
      AsmString = "fmovqneg %icc, $\x02, $\x01";
2713
0
      break;
2714
0
    }
2715
402
    if (MCInst_getNumOperands(MI) == 3 &&
2716
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2717
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2718
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2719
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2720
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2721
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2722
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2723
0
      AsmString = "fmovqvc %icc, $\x02, $\x01";
2724
0
      break;
2725
0
    }
2726
402
    if (MCInst_getNumOperands(MI) == 3 &&
2727
402
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2728
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2729
402
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2730
402
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2731
402
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2732
402
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2733
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2734
0
      AsmString = "fmovqvs %icc, $\x02, $\x01";
2735
0
      break;
2736
0
    }
2737
402
    return NULL;
2738
39
  case SP_FMOVQ_XCC:
2739
39
    if (MCInst_getNumOperands(MI) == 3 &&
2740
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2741
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2742
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2743
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2744
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2745
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2746
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2747
0
      AsmString = "fmovqa %xcc, $\x02, $\x01";
2748
0
      break;
2749
0
    }
2750
39
    if (MCInst_getNumOperands(MI) == 3 &&
2751
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2752
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2753
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2754
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2755
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2756
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2757
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2758
0
      AsmString = "fmovqn %xcc, $\x02, $\x01";
2759
0
      break;
2760
0
    }
2761
39
    if (MCInst_getNumOperands(MI) == 3 &&
2762
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2763
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2764
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2765
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2766
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2767
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2768
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2769
0
      AsmString = "fmovqne %xcc, $\x02, $\x01";
2770
0
      break;
2771
0
    }
2772
39
    if (MCInst_getNumOperands(MI) == 3 &&
2773
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2774
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2775
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2776
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2777
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2778
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2779
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2780
0
      AsmString = "fmovqe %xcc, $\x02, $\x01";
2781
0
      break;
2782
0
    }
2783
39
    if (MCInst_getNumOperands(MI) == 3 &&
2784
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2785
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2786
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2787
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2788
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2789
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2790
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2791
0
      AsmString = "fmovqg %xcc, $\x02, $\x01";
2792
0
      break;
2793
0
    }
2794
39
    if (MCInst_getNumOperands(MI) == 3 &&
2795
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2796
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2797
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2798
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2799
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2800
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2801
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2802
0
      AsmString = "fmovqle %xcc, $\x02, $\x01";
2803
0
      break;
2804
0
    }
2805
39
    if (MCInst_getNumOperands(MI) == 3 &&
2806
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2807
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2808
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2809
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2810
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2811
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2812
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2813
0
      AsmString = "fmovqge %xcc, $\x02, $\x01";
2814
0
      break;
2815
0
    }
2816
39
    if (MCInst_getNumOperands(MI) == 3 &&
2817
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2818
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2819
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2820
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2821
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2822
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2823
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2824
0
      AsmString = "fmovql %xcc, $\x02, $\x01";
2825
0
      break;
2826
0
    }
2827
39
    if (MCInst_getNumOperands(MI) == 3 &&
2828
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2829
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2830
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2831
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2832
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2834
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2835
0
      AsmString = "fmovqgu %xcc, $\x02, $\x01";
2836
0
      break;
2837
0
    }
2838
39
    if (MCInst_getNumOperands(MI) == 3 &&
2839
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2840
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2841
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2842
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2843
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2844
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2845
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2846
0
      AsmString = "fmovqleu %xcc, $\x02, $\x01";
2847
0
      break;
2848
0
    }
2849
39
    if (MCInst_getNumOperands(MI) == 3 &&
2850
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2851
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2852
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2853
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2854
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2855
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2856
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2857
0
      AsmString = "fmovqcc %xcc, $\x02, $\x01";
2858
0
      break;
2859
0
    }
2860
39
    if (MCInst_getNumOperands(MI) == 3 &&
2861
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2862
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2863
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2864
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2865
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2866
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2867
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2868
0
      AsmString = "fmovqcs %xcc, $\x02, $\x01";
2869
0
      break;
2870
0
    }
2871
39
    if (MCInst_getNumOperands(MI) == 3 &&
2872
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2873
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2874
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2875
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2876
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2877
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2878
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2879
0
      AsmString = "fmovqpos %xcc, $\x02, $\x01";
2880
0
      break;
2881
0
    }
2882
39
    if (MCInst_getNumOperands(MI) == 3 &&
2883
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2884
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2885
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2886
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2887
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2888
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2889
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2890
0
      AsmString = "fmovqneg %xcc, $\x02, $\x01";
2891
0
      break;
2892
0
    }
2893
39
    if (MCInst_getNumOperands(MI) == 3 &&
2894
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2895
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2896
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2897
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2898
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2899
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2900
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2901
0
      AsmString = "fmovqvc %xcc, $\x02, $\x01";
2902
0
      break;
2903
0
    }
2904
39
    if (MCInst_getNumOperands(MI) == 3 &&
2905
39
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2906
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2907
39
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2908
39
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2909
39
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2910
39
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2911
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2912
0
      AsmString = "fmovqvs %xcc, $\x02, $\x01";
2913
0
      break;
2914
0
    }
2915
39
    return NULL;
2916
48
  case SP_FMOVS_ICC:
2917
48
    if (MCInst_getNumOperands(MI) == 3 &&
2918
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2919
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2920
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2921
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2922
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2923
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2924
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2925
0
      AsmString = "fmovsa %icc, $\x02, $\x01";
2926
0
      break;
2927
0
    }
2928
48
    if (MCInst_getNumOperands(MI) == 3 &&
2929
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2930
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2931
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2932
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2933
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2934
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2935
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2936
0
      AsmString = "fmovsn %icc, $\x02, $\x01";
2937
0
      break;
2938
0
    }
2939
48
    if (MCInst_getNumOperands(MI) == 3 &&
2940
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2941
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2942
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2943
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2944
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2945
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2946
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2947
0
      AsmString = "fmovsne %icc, $\x02, $\x01";
2948
0
      break;
2949
0
    }
2950
48
    if (MCInst_getNumOperands(MI) == 3 &&
2951
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2952
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2953
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2954
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2955
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2956
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2957
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2958
0
      AsmString = "fmovse %icc, $\x02, $\x01";
2959
0
      break;
2960
0
    }
2961
48
    if (MCInst_getNumOperands(MI) == 3 &&
2962
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2963
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2964
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2965
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2966
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2967
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2968
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2969
0
      AsmString = "fmovsg %icc, $\x02, $\x01";
2970
0
      break;
2971
0
    }
2972
48
    if (MCInst_getNumOperands(MI) == 3 &&
2973
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2974
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2975
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2976
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2977
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2978
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2979
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2980
0
      AsmString = "fmovsle %icc, $\x02, $\x01";
2981
0
      break;
2982
0
    }
2983
48
    if (MCInst_getNumOperands(MI) == 3 &&
2984
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2985
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2986
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2987
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2988
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2989
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2990
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2991
0
      AsmString = "fmovsge %icc, $\x02, $\x01";
2992
0
      break;
2993
0
    }
2994
48
    if (MCInst_getNumOperands(MI) == 3 &&
2995
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2996
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2997
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2998
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2999
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3000
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3001
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3002
0
      AsmString = "fmovsl %icc, $\x02, $\x01";
3003
0
      break;
3004
0
    }
3005
48
    if (MCInst_getNumOperands(MI) == 3 &&
3006
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3007
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3008
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3009
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3010
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3011
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3012
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3013
0
      AsmString = "fmovsgu %icc, $\x02, $\x01";
3014
0
      break;
3015
0
    }
3016
48
    if (MCInst_getNumOperands(MI) == 3 &&
3017
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3018
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3019
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3020
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3021
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3022
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3023
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3024
0
      AsmString = "fmovsleu %icc, $\x02, $\x01";
3025
0
      break;
3026
0
    }
3027
48
    if (MCInst_getNumOperands(MI) == 3 &&
3028
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3029
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3030
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3031
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3032
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3033
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3034
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3035
0
      AsmString = "fmovscc %icc, $\x02, $\x01";
3036
0
      break;
3037
0
    }
3038
48
    if (MCInst_getNumOperands(MI) == 3 &&
3039
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3040
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3041
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3042
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3043
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3044
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3045
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3046
0
      AsmString = "fmovscs %icc, $\x02, $\x01";
3047
0
      break;
3048
0
    }
3049
48
    if (MCInst_getNumOperands(MI) == 3 &&
3050
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3051
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3052
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3053
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3054
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3055
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3056
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3057
0
      AsmString = "fmovspos %icc, $\x02, $\x01";
3058
0
      break;
3059
0
    }
3060
48
    if (MCInst_getNumOperands(MI) == 3 &&
3061
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3062
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3063
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3064
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3065
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3066
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3067
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3068
0
      AsmString = "fmovsneg %icc, $\x02, $\x01";
3069
0
      break;
3070
0
    }
3071
48
    if (MCInst_getNumOperands(MI) == 3 &&
3072
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3073
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3074
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3075
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3076
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3077
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3078
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3079
0
      AsmString = "fmovsvc %icc, $\x02, $\x01";
3080
0
      break;
3081
0
    }
3082
48
    if (MCInst_getNumOperands(MI) == 3 &&
3083
48
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3084
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3085
48
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3086
48
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3087
48
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3088
48
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3089
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3090
0
      AsmString = "fmovsvs %icc, $\x02, $\x01";
3091
0
      break;
3092
0
    }
3093
48
    return NULL;
3094
35
  case SP_FMOVS_XCC:
3095
35
    if (MCInst_getNumOperands(MI) == 3 &&
3096
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3097
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3098
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3099
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3100
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3101
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3102
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3103
0
      AsmString = "fmovsa %xcc, $\x02, $\x01";
3104
0
      break;
3105
0
    }
3106
35
    if (MCInst_getNumOperands(MI) == 3 &&
3107
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3108
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3109
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3110
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3111
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3112
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3113
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3114
0
      AsmString = "fmovsn %xcc, $\x02, $\x01";
3115
0
      break;
3116
0
    }
3117
35
    if (MCInst_getNumOperands(MI) == 3 &&
3118
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3119
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3120
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3121
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3122
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3123
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3124
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3125
0
      AsmString = "fmovsne %xcc, $\x02, $\x01";
3126
0
      break;
3127
0
    }
3128
35
    if (MCInst_getNumOperands(MI) == 3 &&
3129
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3130
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3131
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3132
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3133
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3134
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3135
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3136
0
      AsmString = "fmovse %xcc, $\x02, $\x01";
3137
0
      break;
3138
0
    }
3139
35
    if (MCInst_getNumOperands(MI) == 3 &&
3140
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3141
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3142
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3143
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3144
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3145
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3146
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3147
0
      AsmString = "fmovsg %xcc, $\x02, $\x01";
3148
0
      break;
3149
0
    }
3150
35
    if (MCInst_getNumOperands(MI) == 3 &&
3151
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3152
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3153
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3154
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3155
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3156
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3157
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3158
0
      AsmString = "fmovsle %xcc, $\x02, $\x01";
3159
0
      break;
3160
0
    }
3161
35
    if (MCInst_getNumOperands(MI) == 3 &&
3162
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3163
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3164
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3165
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3166
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3167
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3168
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3169
0
      AsmString = "fmovsge %xcc, $\x02, $\x01";
3170
0
      break;
3171
0
    }
3172
35
    if (MCInst_getNumOperands(MI) == 3 &&
3173
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3174
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3175
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3176
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3177
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3178
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3179
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3180
0
      AsmString = "fmovsl %xcc, $\x02, $\x01";
3181
0
      break;
3182
0
    }
3183
35
    if (MCInst_getNumOperands(MI) == 3 &&
3184
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3185
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3186
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3187
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3188
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3190
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3191
0
      AsmString = "fmovsgu %xcc, $\x02, $\x01";
3192
0
      break;
3193
0
    }
3194
35
    if (MCInst_getNumOperands(MI) == 3 &&
3195
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3196
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3197
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3198
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3199
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3200
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3201
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3202
0
      AsmString = "fmovsleu %xcc, $\x02, $\x01";
3203
0
      break;
3204
0
    }
3205
35
    if (MCInst_getNumOperands(MI) == 3 &&
3206
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3207
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3208
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3209
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3210
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3211
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3212
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3213
0
      AsmString = "fmovscc %xcc, $\x02, $\x01";
3214
0
      break;
3215
0
    }
3216
35
    if (MCInst_getNumOperands(MI) == 3 &&
3217
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3218
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3219
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3220
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3221
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3222
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3223
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3224
0
      AsmString = "fmovscs %xcc, $\x02, $\x01";
3225
0
      break;
3226
0
    }
3227
35
    if (MCInst_getNumOperands(MI) == 3 &&
3228
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3229
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3230
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3231
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3232
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3233
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3234
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3235
0
      AsmString = "fmovspos %xcc, $\x02, $\x01";
3236
0
      break;
3237
0
    }
3238
35
    if (MCInst_getNumOperands(MI) == 3 &&
3239
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3240
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3241
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3242
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3243
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3244
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3245
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3246
0
      AsmString = "fmovsneg %xcc, $\x02, $\x01";
3247
0
      break;
3248
0
    }
3249
35
    if (MCInst_getNumOperands(MI) == 3 &&
3250
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3251
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3252
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3253
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3254
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3255
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3256
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3257
0
      AsmString = "fmovsvc %xcc, $\x02, $\x01";
3258
0
      break;
3259
0
    }
3260
35
    if (MCInst_getNumOperands(MI) == 3 &&
3261
35
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3262
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3263
35
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3264
35
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3265
35
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3266
35
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3267
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3268
0
      AsmString = "fmovsvs %xcc, $\x02, $\x01";
3269
0
      break;
3270
0
    }
3271
35
    return NULL;
3272
249
  case SP_MOVICCri:
3273
249
    if (MCInst_getNumOperands(MI) == 3 &&
3274
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3275
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3276
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3277
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3278
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3279
0
      AsmString = "mova %icc, $\x02, $\x01";
3280
0
      break;
3281
0
    }
3282
249
    if (MCInst_getNumOperands(MI) == 3 &&
3283
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3284
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3285
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3286
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3287
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3288
0
      AsmString = "movn %icc, $\x02, $\x01";
3289
0
      break;
3290
0
    }
3291
249
    if (MCInst_getNumOperands(MI) == 3 &&
3292
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3293
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3294
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3295
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3296
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3297
0
      AsmString = "movne %icc, $\x02, $\x01";
3298
0
      break;
3299
0
    }
3300
249
    if (MCInst_getNumOperands(MI) == 3 &&
3301
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3302
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3303
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3304
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3305
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3306
0
      AsmString = "move %icc, $\x02, $\x01";
3307
0
      break;
3308
0
    }
3309
249
    if (MCInst_getNumOperands(MI) == 3 &&
3310
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3311
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3312
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3313
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3314
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3315
0
      AsmString = "movg %icc, $\x02, $\x01";
3316
0
      break;
3317
0
    }
3318
249
    if (MCInst_getNumOperands(MI) == 3 &&
3319
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3320
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3321
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3322
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3323
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3324
0
      AsmString = "movle %icc, $\x02, $\x01";
3325
0
      break;
3326
0
    }
3327
249
    if (MCInst_getNumOperands(MI) == 3 &&
3328
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3329
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3330
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3331
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3332
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3333
0
      AsmString = "movge %icc, $\x02, $\x01";
3334
0
      break;
3335
0
    }
3336
249
    if (MCInst_getNumOperands(MI) == 3 &&
3337
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3338
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3339
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3340
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3341
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3342
0
      AsmString = "movl %icc, $\x02, $\x01";
3343
0
      break;
3344
0
    }
3345
249
    if (MCInst_getNumOperands(MI) == 3 &&
3346
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3347
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3348
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3349
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3350
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3351
0
      AsmString = "movgu %icc, $\x02, $\x01";
3352
0
      break;
3353
0
    }
3354
249
    if (MCInst_getNumOperands(MI) == 3 &&
3355
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3356
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3357
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3358
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3359
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3360
0
      AsmString = "movleu %icc, $\x02, $\x01";
3361
0
      break;
3362
0
    }
3363
249
    if (MCInst_getNumOperands(MI) == 3 &&
3364
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3365
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3366
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3367
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3368
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3369
0
      AsmString = "movcc %icc, $\x02, $\x01";
3370
0
      break;
3371
0
    }
3372
249
    if (MCInst_getNumOperands(MI) == 3 &&
3373
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3374
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3375
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3376
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3377
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3378
0
      AsmString = "movcs %icc, $\x02, $\x01";
3379
0
      break;
3380
0
    }
3381
249
    if (MCInst_getNumOperands(MI) == 3 &&
3382
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3383
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3384
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3385
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3386
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3387
0
      AsmString = "movpos %icc, $\x02, $\x01";
3388
0
      break;
3389
0
    }
3390
249
    if (MCInst_getNumOperands(MI) == 3 &&
3391
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3392
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3393
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3394
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3395
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3396
0
      AsmString = "movneg %icc, $\x02, $\x01";
3397
0
      break;
3398
0
    }
3399
249
    if (MCInst_getNumOperands(MI) == 3 &&
3400
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3401
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3402
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3403
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3404
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3405
0
      AsmString = "movvc %icc, $\x02, $\x01";
3406
0
      break;
3407
0
    }
3408
249
    if (MCInst_getNumOperands(MI) == 3 &&
3409
249
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3410
249
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3411
249
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3412
249
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3413
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3414
0
      AsmString = "movvs %icc, $\x02, $\x01";
3415
0
      break;
3416
0
    }
3417
249
    return NULL;
3418
407
  case SP_MOVICCrr:
3419
407
    if (MCInst_getNumOperands(MI) == 3 &&
3420
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3421
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3422
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3423
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3424
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3425
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3426
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3427
0
      AsmString = "mova %icc, $\x02, $\x01";
3428
0
      break;
3429
0
    }
3430
407
    if (MCInst_getNumOperands(MI) == 3 &&
3431
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3432
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3433
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3434
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3435
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3436
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3437
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3438
0
      AsmString = "movn %icc, $\x02, $\x01";
3439
0
      break;
3440
0
    }
3441
407
    if (MCInst_getNumOperands(MI) == 3 &&
3442
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3443
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3444
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3445
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3446
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3447
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3448
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3449
0
      AsmString = "movne %icc, $\x02, $\x01";
3450
0
      break;
3451
0
    }
3452
407
    if (MCInst_getNumOperands(MI) == 3 &&
3453
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3454
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3455
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3456
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3457
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3458
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3459
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3460
0
      AsmString = "move %icc, $\x02, $\x01";
3461
0
      break;
3462
0
    }
3463
407
    if (MCInst_getNumOperands(MI) == 3 &&
3464
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3465
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3466
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3467
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3468
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3469
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3470
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3471
0
      AsmString = "movg %icc, $\x02, $\x01";
3472
0
      break;
3473
0
    }
3474
407
    if (MCInst_getNumOperands(MI) == 3 &&
3475
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3476
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3477
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3478
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3479
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3480
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3481
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3482
0
      AsmString = "movle %icc, $\x02, $\x01";
3483
0
      break;
3484
0
    }
3485
407
    if (MCInst_getNumOperands(MI) == 3 &&
3486
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3487
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3488
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3489
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3490
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3491
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3492
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3493
0
      AsmString = "movge %icc, $\x02, $\x01";
3494
0
      break;
3495
0
    }
3496
407
    if (MCInst_getNumOperands(MI) == 3 &&
3497
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3498
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3499
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3500
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3501
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3502
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3503
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3504
0
      AsmString = "movl %icc, $\x02, $\x01";
3505
0
      break;
3506
0
    }
3507
407
    if (MCInst_getNumOperands(MI) == 3 &&
3508
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3509
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3510
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3511
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3512
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3513
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3514
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3515
0
      AsmString = "movgu %icc, $\x02, $\x01";
3516
0
      break;
3517
0
    }
3518
407
    if (MCInst_getNumOperands(MI) == 3 &&
3519
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3520
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3521
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3522
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3523
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3524
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3525
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3526
0
      AsmString = "movleu %icc, $\x02, $\x01";
3527
0
      break;
3528
0
    }
3529
407
    if (MCInst_getNumOperands(MI) == 3 &&
3530
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3531
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3532
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3533
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3534
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3535
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3536
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3537
0
      AsmString = "movcc %icc, $\x02, $\x01";
3538
0
      break;
3539
0
    }
3540
407
    if (MCInst_getNumOperands(MI) == 3 &&
3541
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3542
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3543
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3544
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3545
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3546
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3547
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3548
0
      AsmString = "movcs %icc, $\x02, $\x01";
3549
0
      break;
3550
0
    }
3551
407
    if (MCInst_getNumOperands(MI) == 3 &&
3552
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3553
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3554
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3555
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3556
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3557
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3558
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3559
0
      AsmString = "movpos %icc, $\x02, $\x01";
3560
0
      break;
3561
0
    }
3562
407
    if (MCInst_getNumOperands(MI) == 3 &&
3563
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3564
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3565
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3566
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3567
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3568
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3569
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3570
0
      AsmString = "movneg %icc, $\x02, $\x01";
3571
0
      break;
3572
0
    }
3573
407
    if (MCInst_getNumOperands(MI) == 3 &&
3574
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3575
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3576
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3577
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3578
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3579
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3580
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3581
0
      AsmString = "movvc %icc, $\x02, $\x01";
3582
0
      break;
3583
0
    }
3584
407
    if (MCInst_getNumOperands(MI) == 3 &&
3585
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3586
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3587
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3588
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3589
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3590
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3591
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3592
0
      AsmString = "movvs %icc, $\x02, $\x01";
3593
0
      break;
3594
0
    }
3595
407
    return NULL;
3596
83
  case SP_MOVXCCri:
3597
83
    if (MCInst_getNumOperands(MI) == 3 &&
3598
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3599
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3600
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3601
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3602
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3603
0
      AsmString = "mova %xcc, $\x02, $\x01";
3604
0
      break;
3605
0
    }
3606
83
    if (MCInst_getNumOperands(MI) == 3 &&
3607
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3608
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3609
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3610
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3611
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3612
0
      AsmString = "movn %xcc, $\x02, $\x01";
3613
0
      break;
3614
0
    }
3615
83
    if (MCInst_getNumOperands(MI) == 3 &&
3616
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3617
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3618
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3619
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3620
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3621
0
      AsmString = "movne %xcc, $\x02, $\x01";
3622
0
      break;
3623
0
    }
3624
83
    if (MCInst_getNumOperands(MI) == 3 &&
3625
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3626
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3627
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3628
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3629
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3630
0
      AsmString = "move %xcc, $\x02, $\x01";
3631
0
      break;
3632
0
    }
3633
83
    if (MCInst_getNumOperands(MI) == 3 &&
3634
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3635
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3636
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3637
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3638
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3639
0
      AsmString = "movg %xcc, $\x02, $\x01";
3640
0
      break;
3641
0
    }
3642
83
    if (MCInst_getNumOperands(MI) == 3 &&
3643
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3644
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3645
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3646
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3647
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3648
0
      AsmString = "movle %xcc, $\x02, $\x01";
3649
0
      break;
3650
0
    }
3651
83
    if (MCInst_getNumOperands(MI) == 3 &&
3652
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3653
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3654
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3655
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3656
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3657
0
      AsmString = "movge %xcc, $\x02, $\x01";
3658
0
      break;
3659
0
    }
3660
83
    if (MCInst_getNumOperands(MI) == 3 &&
3661
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3662
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3663
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3664
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3665
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3666
0
      AsmString = "movl %xcc, $\x02, $\x01";
3667
0
      break;
3668
0
    }
3669
83
    if (MCInst_getNumOperands(MI) == 3 &&
3670
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3671
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3672
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3673
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3674
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3675
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3676
0
      break;
3677
0
    }
3678
83
    if (MCInst_getNumOperands(MI) == 3 &&
3679
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3680
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3681
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3682
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3683
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3684
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3685
0
      break;
3686
0
    }
3687
83
    if (MCInst_getNumOperands(MI) == 3 &&
3688
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3689
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3690
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3691
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3692
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3693
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3694
0
      break;
3695
0
    }
3696
83
    if (MCInst_getNumOperands(MI) == 3 &&
3697
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3698
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3699
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3700
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3701
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3702
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3703
0
      break;
3704
0
    }
3705
83
    if (MCInst_getNumOperands(MI) == 3 &&
3706
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3707
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3708
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3709
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3710
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3711
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3712
0
      break;
3713
0
    }
3714
83
    if (MCInst_getNumOperands(MI) == 3 &&
3715
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3716
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3717
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3718
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3719
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3720
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3721
0
      break;
3722
0
    }
3723
83
    if (MCInst_getNumOperands(MI) == 3 &&
3724
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3725
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3726
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3727
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3728
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3729
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3730
0
      break;
3731
0
    }
3732
83
    if (MCInst_getNumOperands(MI) == 3 &&
3733
83
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3734
83
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3735
83
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3736
83
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3737
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3738
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3739
0
      break;
3740
0
    }
3741
83
    return NULL;
3742
71
  case SP_MOVXCCrr:
3743
71
    if (MCInst_getNumOperands(MI) == 3 &&
3744
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3745
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3746
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3747
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3748
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3749
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3750
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3751
0
      AsmString = "mova %xcc, $\x02, $\x01";
3752
0
      break;
3753
0
    }
3754
71
    if (MCInst_getNumOperands(MI) == 3 &&
3755
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3756
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3757
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3758
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3759
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3760
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3761
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3762
0
      AsmString = "movn %xcc, $\x02, $\x01";
3763
0
      break;
3764
0
    }
3765
71
    if (MCInst_getNumOperands(MI) == 3 &&
3766
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3767
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3768
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3769
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3770
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3771
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3772
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3773
0
      AsmString = "movne %xcc, $\x02, $\x01";
3774
0
      break;
3775
0
    }
3776
71
    if (MCInst_getNumOperands(MI) == 3 &&
3777
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3778
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3779
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3780
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3781
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3782
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3783
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3784
0
      AsmString = "move %xcc, $\x02, $\x01";
3785
0
      break;
3786
0
    }
3787
71
    if (MCInst_getNumOperands(MI) == 3 &&
3788
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3789
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3790
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3791
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3792
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3793
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3794
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3795
0
      AsmString = "movg %xcc, $\x02, $\x01";
3796
0
      break;
3797
0
    }
3798
71
    if (MCInst_getNumOperands(MI) == 3 &&
3799
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3800
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3801
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3802
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3803
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3804
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3805
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3806
0
      AsmString = "movle %xcc, $\x02, $\x01";
3807
0
      break;
3808
0
    }
3809
71
    if (MCInst_getNumOperands(MI) == 3 &&
3810
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3811
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3812
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3813
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3814
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3815
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3816
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3817
0
      AsmString = "movge %xcc, $\x02, $\x01";
3818
0
      break;
3819
0
    }
3820
71
    if (MCInst_getNumOperands(MI) == 3 &&
3821
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3822
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3823
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3824
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3825
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3826
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3827
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3828
0
      AsmString = "movl %xcc, $\x02, $\x01";
3829
0
      break;
3830
0
    }
3831
71
    if (MCInst_getNumOperands(MI) == 3 &&
3832
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3833
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3834
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3835
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3836
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3837
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3838
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3839
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3840
0
      break;
3841
0
    }
3842
71
    if (MCInst_getNumOperands(MI) == 3 &&
3843
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3844
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3845
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3846
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3847
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3848
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3849
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3850
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3851
0
      break;
3852
0
    }
3853
71
    if (MCInst_getNumOperands(MI) == 3 &&
3854
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3855
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3856
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3857
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3858
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3859
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3860
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3861
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3862
0
      break;
3863
0
    }
3864
71
    if (MCInst_getNumOperands(MI) == 3 &&
3865
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3866
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3867
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3868
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3869
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3870
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3871
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3872
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3873
0
      break;
3874
0
    }
3875
71
    if (MCInst_getNumOperands(MI) == 3 &&
3876
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3877
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3878
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3879
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3880
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3881
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3882
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3883
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3884
0
      break;
3885
0
    }
3886
71
    if (MCInst_getNumOperands(MI) == 3 &&
3887
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3888
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3889
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3890
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3891
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3892
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3893
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3894
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3895
0
      break;
3896
0
    }
3897
71
    if (MCInst_getNumOperands(MI) == 3 &&
3898
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3899
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3900
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3901
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3902
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3903
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3904
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3905
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3906
0
      break;
3907
0
    }
3908
71
    if (MCInst_getNumOperands(MI) == 3 &&
3909
71
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3910
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3911
71
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3912
71
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3913
71
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3914
71
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3915
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3916
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3917
0
      break;
3918
0
    }
3919
71
    return NULL;
3920
88
  case SP_ORri:
3921
88
    if (MCInst_getNumOperands(MI) == 3 &&
3922
88
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3923
88
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3924
88
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3925
      // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3926
19
      AsmString = "mov $\x03, $\x01";
3927
19
      break;
3928
19
    }
3929
69
    return NULL;
3930
61
  case SP_ORrr:
3931
61
    if (MCInst_getNumOperands(MI) == 3 &&
3932
61
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3933
61
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3934
61
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3935
61
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3936
61
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3937
      // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3938
18
      AsmString = "mov $\x03, $\x01";
3939
18
      break;
3940
18
    }
3941
43
    return NULL;
3942
426
  case SP_RESTORErr:
3943
426
    if (MCInst_getNumOperands(MI) == 3 &&
3944
426
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3945
426
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3946
426
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3947
      // (RESTORErr G0, G0, G0)
3948
99
      AsmString = "restore";
3949
99
      break;
3950
99
    }
3951
327
    return NULL;
3952
0
  case SP_RET:
3953
0
    if (MCInst_getNumOperands(MI) == 1 &&
3954
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3955
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3956
      // (RET 8)
3957
0
      AsmString = "ret";
3958
0
      break;
3959
0
    }
3960
0
    return NULL;
3961
0
  case SP_RETL:
3962
0
    if (MCInst_getNumOperands(MI) == 1 &&
3963
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3964
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3965
      // (RETL 8)
3966
0
      AsmString = "retl";
3967
0
      break;
3968
0
    }
3969
0
    return NULL;
3970
3.98k
  case SP_TXCCri:
3971
3.98k
    if (MCInst_getNumOperands(MI) == 3 &&
3972
3.98k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3973
3.98k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3974
3.98k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3975
3.98k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3976
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3977
173
      AsmString = "ta %xcc, $\x01 + $\x02";
3978
173
      break;
3979
173
    }
3980
3.80k
    if (MCInst_getNumOperands(MI) == 3 &&
3981
3.80k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3982
3.80k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3983
3.80k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3984
      // (TXCCri G0, i32imm:$imm, 8)
3985
0
      AsmString = "ta %xcc, $\x02";
3986
0
      break;
3987
0
    }
3988
3.80k
    if (MCInst_getNumOperands(MI) == 3 &&
3989
3.80k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3990
3.80k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3991
3.80k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3992
3.80k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3993
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3994
123
      AsmString = "tn %xcc, $\x01 + $\x02";
3995
123
      break;
3996
123
    }
3997
3.68k
    if (MCInst_getNumOperands(MI) == 3 &&
3998
3.68k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3999
3.68k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4000
3.68k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4001
      // (TXCCri G0, i32imm:$imm, 0)
4002
0
      AsmString = "tn %xcc, $\x02";
4003
0
      break;
4004
0
    }
4005
3.68k
    if (MCInst_getNumOperands(MI) == 3 &&
4006
3.68k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4007
3.68k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4008
3.68k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4009
3.68k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4010
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4011
180
      AsmString = "tne %xcc, $\x01 + $\x02";
4012
180
      break;
4013
180
    }
4014
3.50k
    if (MCInst_getNumOperands(MI) == 3 &&
4015
3.50k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4016
3.50k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4017
3.50k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4018
      // (TXCCri G0, i32imm:$imm, 9)
4019
0
      AsmString = "tne %xcc, $\x02";
4020
0
      break;
4021
0
    }
4022
3.50k
    if (MCInst_getNumOperands(MI) == 3 &&
4023
3.50k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4024
3.50k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4025
3.50k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4026
3.50k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4027
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4028
70
      AsmString = "te %xcc, $\x01 + $\x02";
4029
70
      break;
4030
70
    }
4031
3.43k
    if (MCInst_getNumOperands(MI) == 3 &&
4032
3.43k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4033
3.43k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4034
3.43k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4035
      // (TXCCri G0, i32imm:$imm, 1)
4036
0
      AsmString = "te %xcc, $\x02";
4037
0
      break;
4038
0
    }
4039
3.43k
    if (MCInst_getNumOperands(MI) == 3 &&
4040
3.43k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4041
3.43k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4042
3.43k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4043
3.43k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4044
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4045
534
      AsmString = "tg %xcc, $\x01 + $\x02";
4046
534
      break;
4047
534
    }
4048
2.90k
    if (MCInst_getNumOperands(MI) == 3 &&
4049
2.90k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4050
2.90k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4051
2.90k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4052
      // (TXCCri G0, i32imm:$imm, 10)
4053
0
      AsmString = "tg %xcc, $\x02";
4054
0
      break;
4055
0
    }
4056
2.90k
    if (MCInst_getNumOperands(MI) == 3 &&
4057
2.90k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4058
2.90k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4059
2.90k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4060
2.90k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4061
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4062
1.08k
      AsmString = "tle %xcc, $\x01 + $\x02";
4063
1.08k
      break;
4064
1.08k
    }
4065
1.81k
    if (MCInst_getNumOperands(MI) == 3 &&
4066
1.81k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4067
1.81k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4068
1.81k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4069
      // (TXCCri G0, i32imm:$imm, 2)
4070
0
      AsmString = "tle %xcc, $\x02";
4071
0
      break;
4072
0
    }
4073
1.81k
    if (MCInst_getNumOperands(MI) == 3 &&
4074
1.81k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4075
1.81k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4076
1.81k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4077
1.81k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4078
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4079
102
      AsmString = "tge %xcc, $\x01 + $\x02";
4080
102
      break;
4081
102
    }
4082
1.71k
    if (MCInst_getNumOperands(MI) == 3 &&
4083
1.71k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4084
1.71k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4085
1.71k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4086
      // (TXCCri G0, i32imm:$imm, 11)
4087
0
      AsmString = "tge %xcc, $\x02";
4088
0
      break;
4089
0
    }
4090
1.71k
    if (MCInst_getNumOperands(MI) == 3 &&
4091
1.71k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4092
1.71k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4093
1.71k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4094
1.71k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4095
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4096
14
      AsmString = "tl %xcc, $\x01 + $\x02";
4097
14
      break;
4098
14
    }
4099
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
4100
1.69k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4101
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4102
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4103
      // (TXCCri G0, i32imm:$imm, 3)
4104
0
      AsmString = "tl %xcc, $\x02";
4105
0
      break;
4106
0
    }
4107
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
4108
1.69k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4109
1.69k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4110
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4111
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4112
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4113
35
      AsmString = "tgu %xcc, $\x01 + $\x02";
4114
35
      break;
4115
35
    }
4116
1.66k
    if (MCInst_getNumOperands(MI) == 3 &&
4117
1.66k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4118
1.66k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4119
1.66k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4120
      // (TXCCri G0, i32imm:$imm, 12)
4121
0
      AsmString = "tgu %xcc, $\x02";
4122
0
      break;
4123
0
    }
4124
1.66k
    if (MCInst_getNumOperands(MI) == 3 &&
4125
1.66k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4126
1.66k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4127
1.66k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4128
1.66k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4129
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4130
29
      AsmString = "tleu %xcc, $\x01 + $\x02";
4131
29
      break;
4132
29
    }
4133
1.63k
    if (MCInst_getNumOperands(MI) == 3 &&
4134
1.63k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4135
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4136
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4137
      // (TXCCri G0, i32imm:$imm, 4)
4138
0
      AsmString = "tleu %xcc, $\x02";
4139
0
      break;
4140
0
    }
4141
1.63k
    if (MCInst_getNumOperands(MI) == 3 &&
4142
1.63k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4143
1.63k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4144
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4145
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4146
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4147
123
      AsmString = "tcc %xcc, $\x01 + $\x02";
4148
123
      break;
4149
123
    }
4150
1.51k
    if (MCInst_getNumOperands(MI) == 3 &&
4151
1.51k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4152
1.51k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4153
1.51k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4154
      // (TXCCri G0, i32imm:$imm, 13)
4155
0
      AsmString = "tcc %xcc, $\x02";
4156
0
      break;
4157
0
    }
4158
1.51k
    if (MCInst_getNumOperands(MI) == 3 &&
4159
1.51k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4160
1.51k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4161
1.51k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4162
1.51k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4163
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4164
38
      AsmString = "tcs %xcc, $\x01 + $\x02";
4165
38
      break;
4166
38
    }
4167
1.47k
    if (MCInst_getNumOperands(MI) == 3 &&
4168
1.47k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4169
1.47k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4170
1.47k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4171
      // (TXCCri G0, i32imm:$imm, 5)
4172
0
      AsmString = "tcs %xcc, $\x02";
4173
0
      break;
4174
0
    }
4175
1.47k
    if (MCInst_getNumOperands(MI) == 3 &&
4176
1.47k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4177
1.47k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4178
1.47k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4179
1.47k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4180
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4181
12
      AsmString = "tpos %xcc, $\x01 + $\x02";
4182
12
      break;
4183
12
    }
4184
1.46k
    if (MCInst_getNumOperands(MI) == 3 &&
4185
1.46k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4186
1.46k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4187
1.46k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4188
      // (TXCCri G0, i32imm:$imm, 14)
4189
0
      AsmString = "tpos %xcc, $\x02";
4190
0
      break;
4191
0
    }
4192
1.46k
    if (MCInst_getNumOperands(MI) == 3 &&
4193
1.46k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4194
1.46k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4195
1.46k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4196
1.46k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4197
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4198
171
      AsmString = "tneg %xcc, $\x01 + $\x02";
4199
171
      break;
4200
171
    }
4201
1.28k
    if (MCInst_getNumOperands(MI) == 3 &&
4202
1.28k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4203
1.28k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4204
1.28k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4205
      // (TXCCri G0, i32imm:$imm, 6)
4206
0
      AsmString = "tneg %xcc, $\x02";
4207
0
      break;
4208
0
    }
4209
1.28k
    if (MCInst_getNumOperands(MI) == 3 &&
4210
1.28k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4211
1.28k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4212
1.28k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4213
1.28k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4214
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4215
155
      AsmString = "tvc %xcc, $\x01 + $\x02";
4216
155
      break;
4217
155
    }
4218
1.13k
    if (MCInst_getNumOperands(MI) == 3 &&
4219
1.13k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4220
1.13k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4221
1.13k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4222
      // (TXCCri G0, i32imm:$imm, 15)
4223
0
      AsmString = "tvc %xcc, $\x02";
4224
0
      break;
4225
0
    }
4226
1.13k
    if (MCInst_getNumOperands(MI) == 3 &&
4227
1.13k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4228
1.13k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4229
1.13k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4230
1.13k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4231
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4232
1.13k
      AsmString = "tvs %xcc, $\x01 + $\x02";
4233
1.13k
      break;
4234
1.13k
    }
4235
0
    if (MCInst_getNumOperands(MI) == 3 &&
4236
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4237
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4238
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4239
      // (TXCCri G0, i32imm:$imm, 7)
4240
0
      AsmString = "tvs %xcc, $\x02";
4241
0
      break;
4242
0
    }
4243
0
    return NULL;
4244
3.14k
  case SP_TXCCrr:
4245
3.14k
    if (MCInst_getNumOperands(MI) == 3 &&
4246
3.14k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4247
3.14k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4248
3.14k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4249
3.14k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4250
3.14k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4251
3.14k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4252
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4253
115
      AsmString = "ta %xcc, $\x01 + $\x02";
4254
115
      break;
4255
115
    }
4256
3.02k
    if (MCInst_getNumOperands(MI) == 3 &&
4257
3.02k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4258
3.02k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4259
3.02k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4260
3.02k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4261
3.02k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4262
      // (TXCCrr G0, IntRegs:$rs2, 8)
4263
0
      AsmString = "ta %xcc, $\x02";
4264
0
      break;
4265
0
    }
4266
3.02k
    if (MCInst_getNumOperands(MI) == 3 &&
4267
3.02k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4268
3.02k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4269
3.02k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4270
3.02k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4271
3.02k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4272
3.02k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4273
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4274
29
      AsmString = "tn %xcc, $\x01 + $\x02";
4275
29
      break;
4276
29
    }
4277
2.99k
    if (MCInst_getNumOperands(MI) == 3 &&
4278
2.99k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4279
2.99k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4280
2.99k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4281
2.99k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4282
2.99k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4283
      // (TXCCrr G0, IntRegs:$rs2, 0)
4284
0
      AsmString = "tn %xcc, $\x02";
4285
0
      break;
4286
0
    }
4287
2.99k
    if (MCInst_getNumOperands(MI) == 3 &&
4288
2.99k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4289
2.99k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4290
2.99k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4291
2.99k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4292
2.99k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4293
2.99k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4294
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4295
370
      AsmString = "tne %xcc, $\x01 + $\x02";
4296
370
      break;
4297
370
    }
4298
2.62k
    if (MCInst_getNumOperands(MI) == 3 &&
4299
2.62k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4300
2.62k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4301
2.62k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4302
2.62k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4303
2.62k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4304
      // (TXCCrr G0, IntRegs:$rs2, 9)
4305
0
      AsmString = "tne %xcc, $\x02";
4306
0
      break;
4307
0
    }
4308
2.62k
    if (MCInst_getNumOperands(MI) == 3 &&
4309
2.62k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4310
2.62k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4311
2.62k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4312
2.62k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4313
2.62k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4314
2.62k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4315
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4316
78
      AsmString = "te %xcc, $\x01 + $\x02";
4317
78
      break;
4318
78
    }
4319
2.55k
    if (MCInst_getNumOperands(MI) == 3 &&
4320
2.55k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4321
2.55k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4322
2.55k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4323
2.55k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4324
2.55k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4325
      // (TXCCrr G0, IntRegs:$rs2, 1)
4326
0
      AsmString = "te %xcc, $\x02";
4327
0
      break;
4328
0
    }
4329
2.55k
    if (MCInst_getNumOperands(MI) == 3 &&
4330
2.55k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4331
2.55k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4332
2.55k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4333
2.55k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4334
2.55k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4335
2.55k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4336
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4337
216
      AsmString = "tg %xcc, $\x01 + $\x02";
4338
216
      break;
4339
216
    }
4340
2.33k
    if (MCInst_getNumOperands(MI) == 3 &&
4341
2.33k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4342
2.33k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4343
2.33k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4344
2.33k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4345
2.33k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4346
      // (TXCCrr G0, IntRegs:$rs2, 10)
4347
0
      AsmString = "tg %xcc, $\x02";
4348
0
      break;
4349
0
    }
4350
2.33k
    if (MCInst_getNumOperands(MI) == 3 &&
4351
2.33k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4352
2.33k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4353
2.33k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4354
2.33k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4355
2.33k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4356
2.33k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4357
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4358
69
      AsmString = "tle %xcc, $\x01 + $\x02";
4359
69
      break;
4360
69
    }
4361
2.26k
    if (MCInst_getNumOperands(MI) == 3 &&
4362
2.26k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4363
2.26k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4364
2.26k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4365
2.26k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4366
2.26k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4367
      // (TXCCrr G0, IntRegs:$rs2, 2)
4368
0
      AsmString = "tle %xcc, $\x02";
4369
0
      break;
4370
0
    }
4371
2.26k
    if (MCInst_getNumOperands(MI) == 3 &&
4372
2.26k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4373
2.26k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4374
2.26k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4375
2.26k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4376
2.26k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4377
2.26k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4378
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4379
47
      AsmString = "tge %xcc, $\x01 + $\x02";
4380
47
      break;
4381
47
    }
4382
2.21k
    if (MCInst_getNumOperands(MI) == 3 &&
4383
2.21k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4384
2.21k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4385
2.21k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4386
2.21k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4387
2.21k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4388
      // (TXCCrr G0, IntRegs:$rs2, 11)
4389
0
      AsmString = "tge %xcc, $\x02";
4390
0
      break;
4391
0
    }
4392
2.21k
    if (MCInst_getNumOperands(MI) == 3 &&
4393
2.21k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4394
2.21k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4395
2.21k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4396
2.21k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4397
2.21k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4398
2.21k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4399
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4400
618
      AsmString = "tl %xcc, $\x01 + $\x02";
4401
618
      break;
4402
618
    }
4403
1.60k
    if (MCInst_getNumOperands(MI) == 3 &&
4404
1.60k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4405
1.60k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4406
1.60k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4407
1.60k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4408
1.60k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4409
      // (TXCCrr G0, IntRegs:$rs2, 3)
4410
0
      AsmString = "tl %xcc, $\x02";
4411
0
      break;
4412
0
    }
4413
1.60k
    if (MCInst_getNumOperands(MI) == 3 &&
4414
1.60k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4415
1.60k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4416
1.60k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4417
1.60k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4418
1.60k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4419
1.60k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4420
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4421
12
      AsmString = "tgu %xcc, $\x01 + $\x02";
4422
12
      break;
4423
12
    }
4424
1.58k
    if (MCInst_getNumOperands(MI) == 3 &&
4425
1.58k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4426
1.58k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4427
1.58k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4428
1.58k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4429
1.58k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4430
      // (TXCCrr G0, IntRegs:$rs2, 12)
4431
0
      AsmString = "tgu %xcc, $\x02";
4432
0
      break;
4433
0
    }
4434
1.58k
    if (MCInst_getNumOperands(MI) == 3 &&
4435
1.58k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4436
1.58k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4437
1.58k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4438
1.58k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4439
1.58k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4440
1.58k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4441
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4442
19
      AsmString = "tleu %xcc, $\x01 + $\x02";
4443
19
      break;
4444
19
    }
4445
1.56k
    if (MCInst_getNumOperands(MI) == 3 &&
4446
1.56k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4447
1.56k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4448
1.56k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4449
1.56k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4450
1.56k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4451
      // (TXCCrr G0, IntRegs:$rs2, 4)
4452
0
      AsmString = "tleu %xcc, $\x02";
4453
0
      break;
4454
0
    }
4455
1.56k
    if (MCInst_getNumOperands(MI) == 3 &&
4456
1.56k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4457
1.56k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4458
1.56k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4459
1.56k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4460
1.56k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4461
1.56k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4462
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4463
378
      AsmString = "tcc %xcc, $\x01 + $\x02";
4464
378
      break;
4465
378
    }
4466
1.19k
    if (MCInst_getNumOperands(MI) == 3 &&
4467
1.19k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4468
1.19k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4469
1.19k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4470
1.19k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4471
1.19k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4472
      // (TXCCrr G0, IntRegs:$rs2, 13)
4473
0
      AsmString = "tcc %xcc, $\x02";
4474
0
      break;
4475
0
    }
4476
1.19k
    if (MCInst_getNumOperands(MI) == 3 &&
4477
1.19k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4478
1.19k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4479
1.19k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4480
1.19k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4481
1.19k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4482
1.19k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4483
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4484
67
      AsmString = "tcs %xcc, $\x01 + $\x02";
4485
67
      break;
4486
67
    }
4487
1.12k
    if (MCInst_getNumOperands(MI) == 3 &&
4488
1.12k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4489
1.12k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4490
1.12k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4491
1.12k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4492
1.12k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4493
      // (TXCCrr G0, IntRegs:$rs2, 5)
4494
0
      AsmString = "tcs %xcc, $\x02";
4495
0
      break;
4496
0
    }
4497
1.12k
    if (MCInst_getNumOperands(MI) == 3 &&
4498
1.12k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4499
1.12k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4500
1.12k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4501
1.12k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4502
1.12k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4503
1.12k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4504
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4505
162
      AsmString = "tpos %xcc, $\x01 + $\x02";
4506
162
      break;
4507
162
    }
4508
962
    if (MCInst_getNumOperands(MI) == 3 &&
4509
962
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4510
962
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4511
962
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4512
962
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4513
962
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4514
      // (TXCCrr G0, IntRegs:$rs2, 14)
4515
0
      AsmString = "tpos %xcc, $\x02";
4516
0
      break;
4517
0
    }
4518
962
    if (MCInst_getNumOperands(MI) == 3 &&
4519
962
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4520
962
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4521
962
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4522
962
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4523
962
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4524
962
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4525
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4526
14
      AsmString = "tneg %xcc, $\x01 + $\x02";
4527
14
      break;
4528
14
    }
4529
948
    if (MCInst_getNumOperands(MI) == 3 &&
4530
948
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4531
948
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4532
948
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4533
948
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4534
948
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4535
      // (TXCCrr G0, IntRegs:$rs2, 6)
4536
0
      AsmString = "tneg %xcc, $\x02";
4537
0
      break;
4538
0
    }
4539
948
    if (MCInst_getNumOperands(MI) == 3 &&
4540
948
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4541
948
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4542
948
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4543
948
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4544
948
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4545
948
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4546
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4547
109
      AsmString = "tvc %xcc, $\x01 + $\x02";
4548
109
      break;
4549
109
    }
4550
839
    if (MCInst_getNumOperands(MI) == 3 &&
4551
839
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4552
839
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4553
839
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4554
839
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4555
839
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4556
      // (TXCCrr G0, IntRegs:$rs2, 15)
4557
0
      AsmString = "tvc %xcc, $\x02";
4558
0
      break;
4559
0
    }
4560
839
    if (MCInst_getNumOperands(MI) == 3 &&
4561
839
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4562
839
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4563
839
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4564
839
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4565
839
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4566
839
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4567
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4568
839
      AsmString = "tvs %xcc, $\x01 + $\x02";
4569
839
      break;
4570
839
    }
4571
0
    if (MCInst_getNumOperands(MI) == 3 &&
4572
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4573
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4574
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4575
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4576
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4577
      // (TXCCrr G0, IntRegs:$rs2, 7)
4578
0
      AsmString = "tvs %xcc, $\x02";
4579
0
      break;
4580
0
    }
4581
0
    return NULL;
4582
57
  case SP_V9FCMPD:
4583
57
    if (MCInst_getNumOperands(MI) == 3 &&
4584
57
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4585
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4586
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4587
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4588
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4589
      // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4590
19
      AsmString = "fcmpd $\x02, $\x03";
4591
19
      break;
4592
19
    }
4593
38
    return NULL;
4594
717
  case SP_V9FCMPED:
4595
717
    if (MCInst_getNumOperands(MI) == 3 &&
4596
717
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4597
717
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4598
717
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4599
717
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4600
717
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4601
      // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4602
707
      AsmString = "fcmped $\x02, $\x03";
4603
707
      break;
4604
707
    }
4605
10
    return NULL;
4606
504
  case SP_V9FCMPEQ:
4607
504
    if (MCInst_getNumOperands(MI) == 3 &&
4608
504
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4609
504
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4610
504
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4611
504
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4612
504
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4613
      // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4614
49
      AsmString = "fcmpeq $\x02, $\x03";
4615
49
      break;
4616
49
    }
4617
455
    return NULL;
4618
1.07k
  case SP_V9FCMPES:
4619
1.07k
    if (MCInst_getNumOperands(MI) == 3 &&
4620
1.07k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4621
1.07k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4622
1.07k
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4623
1.07k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4624
1.07k
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4625
      // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4626
999
      AsmString = "fcmpes $\x02, $\x03";
4627
999
      break;
4628
999
    }
4629
73
    return NULL;
4630
91
  case SP_V9FCMPQ:
4631
91
    if (MCInst_getNumOperands(MI) == 3 &&
4632
91
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4633
91
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4634
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4635
91
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4636
91
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4637
      // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4638
66
      AsmString = "fcmpq $\x02, $\x03";
4639
66
      break;
4640
66
    }
4641
25
    return NULL;
4642
419
  case SP_V9FCMPS:
4643
419
    if (MCInst_getNumOperands(MI) == 3 &&
4644
419
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4645
419
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4646
419
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4647
419
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4648
419
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4649
      // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4650
19
      AsmString = "fcmps $\x02, $\x03";
4651
19
      break;
4652
19
    }
4653
400
    return NULL;
4654
36
  case SP_V9FMOVD_FCC:
4655
36
    if (MCInst_getNumOperands(MI) == 4 &&
4656
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4657
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4658
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4659
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4660
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4661
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4662
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4663
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4664
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4665
0
      AsmString = "fmovda $\x02, $\x03, $\x01";
4666
0
      break;
4667
0
    }
4668
36
    if (MCInst_getNumOperands(MI) == 4 &&
4669
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4670
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4671
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4672
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4673
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4674
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4675
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4676
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4677
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4678
0
      AsmString = "fmovdn $\x02, $\x03, $\x01";
4679
0
      break;
4680
0
    }
4681
36
    if (MCInst_getNumOperands(MI) == 4 &&
4682
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4683
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4684
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4685
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4686
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4687
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4688
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4689
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4690
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4691
0
      AsmString = "fmovdu $\x02, $\x03, $\x01";
4692
0
      break;
4693
0
    }
4694
36
    if (MCInst_getNumOperands(MI) == 4 &&
4695
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4696
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4697
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4698
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4699
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4700
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4701
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4702
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4703
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4704
0
      AsmString = "fmovdg $\x02, $\x03, $\x01";
4705
0
      break;
4706
0
    }
4707
36
    if (MCInst_getNumOperands(MI) == 4 &&
4708
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4709
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4710
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4711
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4712
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4713
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4714
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4715
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4716
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4717
0
      AsmString = "fmovdug $\x02, $\x03, $\x01";
4718
0
      break;
4719
0
    }
4720
36
    if (MCInst_getNumOperands(MI) == 4 &&
4721
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4722
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4723
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4724
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4725
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4726
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4727
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4728
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4729
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4730
0
      AsmString = "fmovdl $\x02, $\x03, $\x01";
4731
0
      break;
4732
0
    }
4733
36
    if (MCInst_getNumOperands(MI) == 4 &&
4734
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4735
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4736
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4737
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4738
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4739
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4740
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4741
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4742
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4743
0
      AsmString = "fmovdul $\x02, $\x03, $\x01";
4744
0
      break;
4745
0
    }
4746
36
    if (MCInst_getNumOperands(MI) == 4 &&
4747
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4748
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4749
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4750
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4751
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4752
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4753
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4754
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4755
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4756
0
      AsmString = "fmovdlg $\x02, $\x03, $\x01";
4757
0
      break;
4758
0
    }
4759
36
    if (MCInst_getNumOperands(MI) == 4 &&
4760
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4761
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4762
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4763
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4764
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4765
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4766
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4767
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4768
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4769
0
      AsmString = "fmovdne $\x02, $\x03, $\x01";
4770
0
      break;
4771
0
    }
4772
36
    if (MCInst_getNumOperands(MI) == 4 &&
4773
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4774
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4775
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4776
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4777
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4778
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4779
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4780
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4781
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4782
0
      AsmString = "fmovde $\x02, $\x03, $\x01";
4783
0
      break;
4784
0
    }
4785
36
    if (MCInst_getNumOperands(MI) == 4 &&
4786
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4787
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4788
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4789
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4790
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4791
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4792
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4793
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4794
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4795
0
      AsmString = "fmovdue $\x02, $\x03, $\x01";
4796
0
      break;
4797
0
    }
4798
36
    if (MCInst_getNumOperands(MI) == 4 &&
4799
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4800
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4801
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4802
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4803
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4804
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4805
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4806
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4807
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4808
0
      AsmString = "fmovdge $\x02, $\x03, $\x01";
4809
0
      break;
4810
0
    }
4811
36
    if (MCInst_getNumOperands(MI) == 4 &&
4812
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4813
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4814
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4815
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4816
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4817
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4818
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4819
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4820
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4821
0
      AsmString = "fmovduge $\x02, $\x03, $\x01";
4822
0
      break;
4823
0
    }
4824
36
    if (MCInst_getNumOperands(MI) == 4 &&
4825
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4826
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4827
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4828
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4829
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4830
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4831
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4832
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4833
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4834
0
      AsmString = "fmovdle $\x02, $\x03, $\x01";
4835
0
      break;
4836
0
    }
4837
36
    if (MCInst_getNumOperands(MI) == 4 &&
4838
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4839
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4840
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4841
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4842
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4843
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4844
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4845
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4846
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4847
0
      AsmString = "fmovdule $\x02, $\x03, $\x01";
4848
0
      break;
4849
0
    }
4850
36
    if (MCInst_getNumOperands(MI) == 4 &&
4851
36
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4852
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4853
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4854
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4855
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4856
36
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4857
36
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4858
36
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4859
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4860
0
      AsmString = "fmovdo $\x02, $\x03, $\x01";
4861
0
      break;
4862
0
    }
4863
36
    return NULL;
4864
183
  case SP_V9FMOVQ_FCC:
4865
183
    if (MCInst_getNumOperands(MI) == 4 &&
4866
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4867
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4868
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4869
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4870
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4871
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4872
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4873
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4874
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4875
0
      AsmString = "fmovqa $\x02, $\x03, $\x01";
4876
0
      break;
4877
0
    }
4878
183
    if (MCInst_getNumOperands(MI) == 4 &&
4879
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4880
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4881
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4882
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4883
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4884
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4885
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4886
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4887
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4888
0
      AsmString = "fmovqn $\x02, $\x03, $\x01";
4889
0
      break;
4890
0
    }
4891
183
    if (MCInst_getNumOperands(MI) == 4 &&
4892
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4893
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4894
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4895
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4896
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4897
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4898
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4899
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4900
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4901
0
      AsmString = "fmovqu $\x02, $\x03, $\x01";
4902
0
      break;
4903
0
    }
4904
183
    if (MCInst_getNumOperands(MI) == 4 &&
4905
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4906
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4907
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4908
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4909
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4910
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4911
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4912
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4913
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4914
0
      AsmString = "fmovqg $\x02, $\x03, $\x01";
4915
0
      break;
4916
0
    }
4917
183
    if (MCInst_getNumOperands(MI) == 4 &&
4918
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4919
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4920
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4921
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4922
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4923
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4924
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4925
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4926
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4927
0
      AsmString = "fmovqug $\x02, $\x03, $\x01";
4928
0
      break;
4929
0
    }
4930
183
    if (MCInst_getNumOperands(MI) == 4 &&
4931
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4932
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4933
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4934
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4935
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4936
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4937
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4938
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4939
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4940
0
      AsmString = "fmovql $\x02, $\x03, $\x01";
4941
0
      break;
4942
0
    }
4943
183
    if (MCInst_getNumOperands(MI) == 4 &&
4944
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4945
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4946
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4947
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4948
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4949
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4950
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4951
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4952
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4953
0
      AsmString = "fmovqul $\x02, $\x03, $\x01";
4954
0
      break;
4955
0
    }
4956
183
    if (MCInst_getNumOperands(MI) == 4 &&
4957
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4958
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4959
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4960
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4961
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4962
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4963
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4964
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4965
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4966
0
      AsmString = "fmovqlg $\x02, $\x03, $\x01";
4967
0
      break;
4968
0
    }
4969
183
    if (MCInst_getNumOperands(MI) == 4 &&
4970
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4971
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4972
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4973
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4974
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4975
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4976
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4977
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4978
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4979
0
      AsmString = "fmovqne $\x02, $\x03, $\x01";
4980
0
      break;
4981
0
    }
4982
183
    if (MCInst_getNumOperands(MI) == 4 &&
4983
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4984
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4985
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4986
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4987
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4988
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4989
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4990
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4991
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4992
0
      AsmString = "fmovqe $\x02, $\x03, $\x01";
4993
0
      break;
4994
0
    }
4995
183
    if (MCInst_getNumOperands(MI) == 4 &&
4996
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4997
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4998
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4999
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5000
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5001
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5002
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5003
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5004
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5005
0
      AsmString = "fmovque $\x02, $\x03, $\x01";
5006
0
      break;
5007
0
    }
5008
183
    if (MCInst_getNumOperands(MI) == 4 &&
5009
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5010
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5011
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5012
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5013
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5014
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5015
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5016
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5017
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5018
0
      AsmString = "fmovqge $\x02, $\x03, $\x01";
5019
0
      break;
5020
0
    }
5021
183
    if (MCInst_getNumOperands(MI) == 4 &&
5022
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5023
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5024
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5025
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5026
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5027
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5028
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5029
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5030
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5031
0
      AsmString = "fmovquge $\x02, $\x03, $\x01";
5032
0
      break;
5033
0
    }
5034
183
    if (MCInst_getNumOperands(MI) == 4 &&
5035
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5036
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5037
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5038
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5039
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5040
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5041
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5042
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5043
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5044
0
      AsmString = "fmovqle $\x02, $\x03, $\x01";
5045
0
      break;
5046
0
    }
5047
183
    if (MCInst_getNumOperands(MI) == 4 &&
5048
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5049
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5050
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5051
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5052
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5053
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5054
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5055
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5056
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5057
0
      AsmString = "fmovqule $\x02, $\x03, $\x01";
5058
0
      break;
5059
0
    }
5060
183
    if (MCInst_getNumOperands(MI) == 4 &&
5061
183
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5062
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5063
183
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5064
183
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5065
183
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5066
183
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5067
183
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5068
183
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5069
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5070
0
      AsmString = "fmovqo $\x02, $\x03, $\x01";
5071
0
      break;
5072
0
    }
5073
183
    return NULL;
5074
286
  case SP_V9FMOVS_FCC:
5075
286
    if (MCInst_getNumOperands(MI) == 4 &&
5076
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5077
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5078
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5079
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5080
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5081
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5082
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5083
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5084
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5085
0
      AsmString = "fmovsa $\x02, $\x03, $\x01";
5086
0
      break;
5087
0
    }
5088
286
    if (MCInst_getNumOperands(MI) == 4 &&
5089
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5090
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5091
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5092
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5093
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5094
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5095
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5096
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5097
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5098
0
      AsmString = "fmovsn $\x02, $\x03, $\x01";
5099
0
      break;
5100
0
    }
5101
286
    if (MCInst_getNumOperands(MI) == 4 &&
5102
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5103
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5104
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5105
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5106
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5107
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5108
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5109
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5110
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5111
0
      AsmString = "fmovsu $\x02, $\x03, $\x01";
5112
0
      break;
5113
0
    }
5114
286
    if (MCInst_getNumOperands(MI) == 4 &&
5115
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5116
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5117
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5118
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5119
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5120
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5121
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5122
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5123
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5124
0
      AsmString = "fmovsg $\x02, $\x03, $\x01";
5125
0
      break;
5126
0
    }
5127
286
    if (MCInst_getNumOperands(MI) == 4 &&
5128
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5129
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5130
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5131
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5132
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5133
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5134
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5135
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5136
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5137
0
      AsmString = "fmovsug $\x02, $\x03, $\x01";
5138
0
      break;
5139
0
    }
5140
286
    if (MCInst_getNumOperands(MI) == 4 &&
5141
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5142
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5143
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5144
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5145
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5146
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5147
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5148
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5149
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5150
0
      AsmString = "fmovsl $\x02, $\x03, $\x01";
5151
0
      break;
5152
0
    }
5153
286
    if (MCInst_getNumOperands(MI) == 4 &&
5154
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5155
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5156
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5157
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5158
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5159
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5160
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5161
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5162
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5163
0
      AsmString = "fmovsul $\x02, $\x03, $\x01";
5164
0
      break;
5165
0
    }
5166
286
    if (MCInst_getNumOperands(MI) == 4 &&
5167
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5168
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5169
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5170
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5171
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5172
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5173
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5174
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5175
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5176
0
      AsmString = "fmovslg $\x02, $\x03, $\x01";
5177
0
      break;
5178
0
    }
5179
286
    if (MCInst_getNumOperands(MI) == 4 &&
5180
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5181
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5182
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5183
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5184
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5185
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5186
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5187
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5188
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5189
0
      AsmString = "fmovsne $\x02, $\x03, $\x01";
5190
0
      break;
5191
0
    }
5192
286
    if (MCInst_getNumOperands(MI) == 4 &&
5193
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5194
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5195
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5196
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5197
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5198
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5199
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5200
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5201
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5202
0
      AsmString = "fmovse $\x02, $\x03, $\x01";
5203
0
      break;
5204
0
    }
5205
286
    if (MCInst_getNumOperands(MI) == 4 &&
5206
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5207
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5208
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5209
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5210
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5211
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5212
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5213
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5214
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5215
0
      AsmString = "fmovsue $\x02, $\x03, $\x01";
5216
0
      break;
5217
0
    }
5218
286
    if (MCInst_getNumOperands(MI) == 4 &&
5219
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5220
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5221
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5222
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5223
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5224
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5225
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5226
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5227
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5228
0
      AsmString = "fmovsge $\x02, $\x03, $\x01";
5229
0
      break;
5230
0
    }
5231
286
    if (MCInst_getNumOperands(MI) == 4 &&
5232
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5233
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5234
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5235
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5236
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5237
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5238
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5239
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5240
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5241
0
      AsmString = "fmovsuge $\x02, $\x03, $\x01";
5242
0
      break;
5243
0
    }
5244
286
    if (MCInst_getNumOperands(MI) == 4 &&
5245
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5246
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5247
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5248
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5249
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5250
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5251
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5252
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5253
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5254
0
      AsmString = "fmovsle $\x02, $\x03, $\x01";
5255
0
      break;
5256
0
    }
5257
286
    if (MCInst_getNumOperands(MI) == 4 &&
5258
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5259
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5260
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5261
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5262
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5263
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5264
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5265
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5266
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5267
0
      AsmString = "fmovsule $\x02, $\x03, $\x01";
5268
0
      break;
5269
0
    }
5270
286
    if (MCInst_getNumOperands(MI) == 4 &&
5271
286
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5272
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5273
286
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5274
286
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5275
286
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5276
286
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5277
286
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5278
286
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5279
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5280
0
      AsmString = "fmovso $\x02, $\x03, $\x01";
5281
0
      break;
5282
0
    }
5283
286
    return NULL;
5284
92
  case SP_V9MOVFCCri:
5285
92
    if (MCInst_getNumOperands(MI) == 4 &&
5286
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5287
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5288
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5289
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5290
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5291
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5292
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5293
0
      AsmString = "mova $\x02, $\x03, $\x01";
5294
0
      break;
5295
0
    }
5296
92
    if (MCInst_getNumOperands(MI) == 4 &&
5297
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5298
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5299
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5300
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5301
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5302
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5303
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5304
0
      AsmString = "movn $\x02, $\x03, $\x01";
5305
0
      break;
5306
0
    }
5307
92
    if (MCInst_getNumOperands(MI) == 4 &&
5308
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5309
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5310
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5311
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5312
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5313
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5314
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5315
0
      AsmString = "movu $\x02, $\x03, $\x01";
5316
0
      break;
5317
0
    }
5318
92
    if (MCInst_getNumOperands(MI) == 4 &&
5319
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5320
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5321
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5322
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5323
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5324
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5325
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5326
0
      AsmString = "movg $\x02, $\x03, $\x01";
5327
0
      break;
5328
0
    }
5329
92
    if (MCInst_getNumOperands(MI) == 4 &&
5330
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5331
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5332
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5333
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5334
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5335
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5336
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5337
0
      AsmString = "movug $\x02, $\x03, $\x01";
5338
0
      break;
5339
0
    }
5340
92
    if (MCInst_getNumOperands(MI) == 4 &&
5341
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5342
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5343
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5344
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5345
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5346
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5347
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5348
0
      AsmString = "movl $\x02, $\x03, $\x01";
5349
0
      break;
5350
0
    }
5351
92
    if (MCInst_getNumOperands(MI) == 4 &&
5352
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5353
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5354
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5355
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5356
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5357
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5358
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5359
0
      AsmString = "movul $\x02, $\x03, $\x01";
5360
0
      break;
5361
0
    }
5362
92
    if (MCInst_getNumOperands(MI) == 4 &&
5363
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5364
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5365
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5366
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5367
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5368
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5369
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5370
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5371
0
      break;
5372
0
    }
5373
92
    if (MCInst_getNumOperands(MI) == 4 &&
5374
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5375
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5376
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5377
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5378
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5379
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5380
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5381
0
      AsmString = "movne $\x02, $\x03, $\x01";
5382
0
      break;
5383
0
    }
5384
92
    if (MCInst_getNumOperands(MI) == 4 &&
5385
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5386
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5387
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5388
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5389
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5390
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5391
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5392
0
      AsmString = "move $\x02, $\x03, $\x01";
5393
0
      break;
5394
0
    }
5395
92
    if (MCInst_getNumOperands(MI) == 4 &&
5396
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5397
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5398
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5399
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5400
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5401
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5402
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5403
0
      AsmString = "movue $\x02, $\x03, $\x01";
5404
0
      break;
5405
0
    }
5406
92
    if (MCInst_getNumOperands(MI) == 4 &&
5407
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5408
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5409
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5410
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5411
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5412
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5413
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5414
0
      AsmString = "movge $\x02, $\x03, $\x01";
5415
0
      break;
5416
0
    }
5417
92
    if (MCInst_getNumOperands(MI) == 4 &&
5418
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5419
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5420
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5421
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5422
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5423
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5424
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5425
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5426
0
      break;
5427
0
    }
5428
92
    if (MCInst_getNumOperands(MI) == 4 &&
5429
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5430
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5431
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5432
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5433
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5434
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5435
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5436
0
      AsmString = "movle $\x02, $\x03, $\x01";
5437
0
      break;
5438
0
    }
5439
92
    if (MCInst_getNumOperands(MI) == 4 &&
5440
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5441
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5442
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5443
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5444
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5445
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5446
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5447
0
      AsmString = "movule $\x02, $\x03, $\x01";
5448
0
      break;
5449
0
    }
5450
92
    if (MCInst_getNumOperands(MI) == 4 &&
5451
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5452
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5453
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5454
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5455
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5456
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5457
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5458
0
      AsmString = "movo $\x02, $\x03, $\x01";
5459
0
      break;
5460
0
    }
5461
92
    return NULL;
5462
422
  case SP_V9MOVFCCrr:
5463
422
    if (MCInst_getNumOperands(MI) == 4 &&
5464
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5465
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5466
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5467
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5468
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5469
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5470
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5471
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5472
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5473
0
      AsmString = "mova $\x02, $\x03, $\x01";
5474
0
      break;
5475
0
    }
5476
422
    if (MCInst_getNumOperands(MI) == 4 &&
5477
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5478
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5479
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5480
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5481
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5482
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5483
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5484
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5485
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5486
0
      AsmString = "movn $\x02, $\x03, $\x01";
5487
0
      break;
5488
0
    }
5489
422
    if (MCInst_getNumOperands(MI) == 4 &&
5490
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5491
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5492
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5493
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5494
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5495
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5496
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5497
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5498
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5499
0
      AsmString = "movu $\x02, $\x03, $\x01";
5500
0
      break;
5501
0
    }
5502
422
    if (MCInst_getNumOperands(MI) == 4 &&
5503
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5504
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5505
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5506
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5507
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5508
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5509
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5510
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5511
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5512
0
      AsmString = "movg $\x02, $\x03, $\x01";
5513
0
      break;
5514
0
    }
5515
422
    if (MCInst_getNumOperands(MI) == 4 &&
5516
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5517
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5518
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5519
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5520
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5521
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5522
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5523
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5524
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5525
0
      AsmString = "movug $\x02, $\x03, $\x01";
5526
0
      break;
5527
0
    }
5528
422
    if (MCInst_getNumOperands(MI) == 4 &&
5529
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5530
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5531
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5532
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5533
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5534
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5535
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5536
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5537
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5538
0
      AsmString = "movl $\x02, $\x03, $\x01";
5539
0
      break;
5540
0
    }
5541
422
    if (MCInst_getNumOperands(MI) == 4 &&
5542
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5543
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5544
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5545
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5546
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5547
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5548
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5549
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5550
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5551
0
      AsmString = "movul $\x02, $\x03, $\x01";
5552
0
      break;
5553
0
    }
5554
422
    if (MCInst_getNumOperands(MI) == 4 &&
5555
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5556
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5557
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5558
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5559
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5560
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5561
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5562
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5563
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5564
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5565
0
      break;
5566
0
    }
5567
422
    if (MCInst_getNumOperands(MI) == 4 &&
5568
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5569
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5570
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5571
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5572
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5573
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5574
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5575
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5576
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5577
0
      AsmString = "movne $\x02, $\x03, $\x01";
5578
0
      break;
5579
0
    }
5580
422
    if (MCInst_getNumOperands(MI) == 4 &&
5581
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5582
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5583
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5584
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5585
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5586
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5587
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5588
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5589
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5590
0
      AsmString = "move $\x02, $\x03, $\x01";
5591
0
      break;
5592
0
    }
5593
422
    if (MCInst_getNumOperands(MI) == 4 &&
5594
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5595
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5596
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5597
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5598
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5599
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5600
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5601
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5602
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5603
0
      AsmString = "movue $\x02, $\x03, $\x01";
5604
0
      break;
5605
0
    }
5606
422
    if (MCInst_getNumOperands(MI) == 4 &&
5607
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5608
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5609
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5610
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5611
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5612
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5613
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5614
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5615
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5616
0
      AsmString = "movge $\x02, $\x03, $\x01";
5617
0
      break;
5618
0
    }
5619
422
    if (MCInst_getNumOperands(MI) == 4 &&
5620
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5621
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5622
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5623
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5624
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5625
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5626
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5627
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5628
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5629
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5630
0
      break;
5631
0
    }
5632
422
    if (MCInst_getNumOperands(MI) == 4 &&
5633
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5634
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5635
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5636
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5637
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5638
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5639
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5640
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5641
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5642
0
      AsmString = "movle $\x02, $\x03, $\x01";
5643
0
      break;
5644
0
    }
5645
422
    if (MCInst_getNumOperands(MI) == 4 &&
5646
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5647
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5648
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5649
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5650
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5651
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5652
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5653
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5654
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5655
0
      AsmString = "movule $\x02, $\x03, $\x01";
5656
0
      break;
5657
0
    }
5658
422
    if (MCInst_getNumOperands(MI) == 4 &&
5659
422
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5660
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5661
422
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5662
422
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5663
422
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5664
422
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5665
422
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5666
422
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5667
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5668
0
      AsmString = "movo $\x02, $\x03, $\x01";
5669
0
      break;
5670
0
    }
5671
422
    return NULL;
5672
74.4k
  }
5673
5674
30.6k
  tmp = cs_strdup(AsmString);
5675
30.6k
  AsmMnem = tmp;
5676
198k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5677
198k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
5678
30.5k
      *AsmOps = '\0';
5679
30.5k
      AsmOps++;
5680
30.5k
      break;
5681
30.5k
    }
5682
198k
  }
5683
30.6k
  SStream_concat0(OS, AsmMnem);
5684
30.6k
  if (*AsmOps) {
5685
30.5k
    SStream_concat0(OS, "\t");
5686
30.5k
    if (strstr(AsmOps, "icc"))
5687
6.56k
      Sparc_addReg(MI, SPARC_REG_ICC);
5688
30.5k
    if (strstr(AsmOps, "xcc"))
5689
11.2k
      Sparc_addReg(MI, SPARC_REG_XCC);
5690
220k
    for (c = AsmOps; *c; c++) {
5691
190k
      if (*c == '$') {
5692
45.7k
        c += 1;
5693
45.7k
        if (*c == (char)0xff) {
5694
0
          c += 1;
5695
0
          OpIdx = *c - 1;
5696
0
          c += 1;
5697
0
          PrintMethodIdx = *c - 1;
5698
0
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5699
0
        } else
5700
45.7k
          printOperand(MI, *c - 1, OS);
5701
144k
      } else {
5702
144k
        SStream_concat(OS, "%c", *c);
5703
144k
      }
5704
190k
    }
5705
30.5k
  }
5706
30.6k
  return tmp;
5707
74.4k
}
5708
5709
#endif // PRINT_ALIAS_INSTR