/src/capstonenext/arch/Sparc/SparcGenAsmWriter.inc

Source (jump to first uncovered line)
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/*    Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */

/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */

/* Do not edit. */

/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */

#include <capstone/platform.h>
#include "../../cs_priv.h"

/// getMnemonic - This method is automatically generated by tablegen
/// from the instruction set description.
static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
#ifndef CAPSTONE_DIET
  static const char AsmStrs[] = {
  /* 0 */ "fcmpd %fcc0, \0"
  /* 14 */ "fcmpq %fcc0, \0"
  /* 28 */ "fcmps %fcc0, \0"
  /* 42 */ "rd %wim, \0"
  /* 52 */ "rdpr %fq, \0"
  /* 63 */ "rd %tbr, \0"
  /* 73 */ "rd %psr, \0"
  /* 83 */ "fsrc1 \0"
  /* 90 */ "fandnot1 \0"
  /* 100 */ "fnot1 \0"
  /* 107 */ "fornot1 \0"
  /* 116 */ "fsra32 \0"
  /* 124 */ "fpsub32 \0"
  /* 133 */ "fpadd32 \0"
  /* 142 */ "edge32 \0"
  /* 150 */ "fcmple32 \0"
  /* 160 */ "fcmpne32 \0"
  /* 170 */ "fpack32 \0"
  /* 179 */ "cmask32 \0"
  /* 188 */ "fsll32 \0"
  /* 196 */ "fsrl32 \0"
  /* 204 */ "fcmpeq32 \0"
  /* 214 */ "fslas32 \0"
  /* 223 */ "fcmpgt32 \0"
  /* 233 */ "array32 \0"
  /* 242 */ "fsrc2 \0"
  /* 249 */ "fandnot2 \0"
  /* 259 */ "fnot2 \0"
  /* 266 */ "fornot2 \0"
  /* 275 */ "fpadd64 \0"
  /* 284 */ "fsra16 \0"
  /* 292 */ "fpsub16 \0"
  /* 301 */ "fpadd16 \0"
  /* 310 */ "edge16 \0"
  /* 318 */ "fcmple16 \0"
  /* 328 */ "fcmpne16 \0"
  /* 338 */ "fpack16 \0"
  /* 347 */ "cmask16 \0"
  /* 356 */ "fsll16 \0"
  /* 364 */ "fsrl16 \0"
  /* 372 */ "fchksm16 \0"
  /* 382 */ "fmean16 \0"
  /* 391 */ "fcmpeq16 \0"
  /* 401 */ "fslas16 \0"
  /* 410 */ "fcmpgt16 \0"
  /* 420 */ "fmul8x16 \0"
  /* 430 */ "fmuld8ulx16 \0"
  /* 443 */ "fmul8ulx16 \0"
  /* 455 */ "fmuld8sux16 \0"
  /* 468 */ "fmul8sux16 \0"
  /* 480 */ "array16 \0"
  /* 489 */ "edge8 \0"
  /* 496 */ "cmask8 \0"
  /* 504 */ "array8 \0"
  /* 512 */ "!ADJCALLSTACKDOWN \0"
  /* 531 */ "!ADJCALLSTACKUP \0"
  /* 548 */ "stba \0"
  /* 554 */ "stda \0"
  /* 560 */ "stha \0"
  /* 566 */ "stqa \0"
  /* 572 */ "sra \0"
  /* 577 */ "faligndata \0"
  /* 589 */ "sta \0"
  /* 594 */ "stxa \0"
  /* 600 */ "stb \0"
  /* 605 */ "sub \0"
  /* 610 */ "smac \0"
  /* 616 */ "umac \0"
  /* 622 */ "tsubcc \0"
  /* 630 */ "addxccc \0"
  /* 639 */ "taddcc \0"
  /* 647 */ "andcc \0"
  /* 654 */ "smulcc \0"
  /* 662 */ "umulcc \0"
  /* 670 */ "andncc \0"
  /* 678 */ "orncc \0"
  /* 685 */ "xnorcc \0"
  /* 693 */ "xorcc \0"
  /* 700 */ "mulscc \0"
  /* 708 */ "sdivcc \0"
  /* 716 */ "udivcc \0"
  /* 724 */ "subxcc \0"
  /* 732 */ "addxcc \0"
  /* 740 */ "popc \0"
  /* 746 */ "addxc \0"
  /* 753 */ "fsubd \0"
  /* 760 */ "fhsubd \0"
  /* 768 */ "add \0"
  /* 773 */ "faddd \0"
  /* 780 */ "fhaddd \0"
  /* 788 */ "fnhaddd \0"
  /* 797 */ "fnaddd \0"
  /* 805 */ "fcmped \0"
  /* 813 */ "fnegd \0"
  /* 820 */ "fmuld \0"
  /* 827 */ "fnmuld \0"
  /* 835 */ "fsmuld \0"
  /* 843 */ "fnsmuld \0"
  /* 852 */ "fand \0"
  /* 858 */ "fnand \0"
  /* 865 */ "fexpand \0"
  /* 874 */ "fitod \0"
  /* 881 */ "fqtod \0"
  /* 888 */ "fstod \0"
  /* 895 */ "fxtod \0"
  /* 902 */ "movxtod \0"
  /* 911 */ "fcmpd \0"
  /* 918 */ "flcmpd \0"
  /* 926 */ "rd \0"
  /* 930 */ "fabsd \0"
  /* 937 */ "fsqrtd \0"
  /* 945 */ "std \0"
  /* 950 */ "fdivd \0"
  /* 957 */ "fmovd \0"
  /* 964 */ "fpmerge \0"
  /* 973 */ "bshuffle \0"
  /* 983 */ "fone \0"
  /* 989 */ "restore \0"
  /* 998 */ "save \0"
  /* 1004 */ "flush \0"
  /* 1011 */ "sth \0"
  /* 1016 */ "sethi \0"
  /* 1023 */ "umulxhi \0"
  /* 1032 */ "xmulxhi \0"
  /* 1041 */ "fdtoi \0"
  /* 1048 */ "fqtoi \0"
  /* 1055 */ "fstoi \0"
  /* 1062 */ "bmask \0"
  /* 1069 */ "edge32l \0"
  /* 1078 */ "edge16l \0"
  /* 1087 */ "edge8l \0"
  /* 1095 */ "fmul8x16al \0"
  /* 1107 */ "call \0"
  /* 1113 */ "sll \0"
  /* 1118 */ "jmpl \0"
  /* 1124 */ "alignaddrl \0"
  /* 1136 */ "srl \0"
  /* 1141 */ "smul \0"
  /* 1147 */ "umul \0"
  /* 1153 */ "edge32n \0"
  /* 1162 */ "edge16n \0"
  /* 1171 */ "edge8n \0"
  /* 1179 */ "andn \0"
  /* 1185 */ "edge32ln \0"
  /* 1195 */ "edge16ln \0"
  /* 1205 */ "edge8ln \0"
  /* 1214 */ "orn \0"
  /* 1219 */ "pdistn \0"
  /* 1227 */ "fzero \0"
  /* 1234 */ "unimp \0"
  /* 1241 */ "jmp \0"
  /* 1246 */ "fsubq \0"
  /* 1253 */ "faddq \0"
  /* 1260 */ "fcmpeq \0"
  /* 1268 */ "fnegq \0"
  /* 1275 */ "fdmulq \0"
  /* 1283 */ "fmulq \0"
  /* 1290 */ "fdtoq \0"
  /* 1297 */ "fitoq \0"
  /* 1304 */ "fstoq \0"
  /* 1311 */ "fxtoq \0"
  /* 1318 */ "fcmpq \0"
  /* 1325 */ "fabsq \0"
  /* 1332 */ "fsqrtq \0"
  /* 1340 */ "stq \0"
  /* 1345 */ "fdivq \0"
  /* 1352 */ "fmovq \0"
  /* 1359 */ "membar \0"
  /* 1367 */ "alignaddr \0"
  /* 1378 */ "sir \0"
  /* 1383 */ "for \0"
  /* 1388 */ "fnor \0"
  /* 1394 */ "fxnor \0"
  /* 1401 */ "fxor \0"
  /* 1407 */ "rdpr \0"
  /* 1413 */ "wrpr \0"
  /* 1419 */ "pwr \0"
  /* 1424 */ "fsrc1s \0"
  /* 1432 */ "fandnot1s \0"
  /* 1443 */ "fnot1s \0"
  /* 1451 */ "fornot1s \0"
  /* 1461 */ "fpsub32s \0"
  /* 1471 */ "fpadd32s \0"
  /* 1481 */ "fsrc2s \0"
  /* 1489 */ "fandnot2s \0"
  /* 1500 */ "fnot2s \0"
  /* 1508 */ "fornot2s \0"
  /* 1518 */ "fpsub16s \0"
  /* 1528 */ "fpadd16s \0"
  /* 1538 */ "fsubs \0"
  /* 1545 */ "fhsubs \0"
  /* 1553 */ "fadds \0"
  /* 1560 */ "fhadds \0"
  /* 1568 */ "fnhadds \0"
  /* 1577 */ "fnadds \0"
  /* 1585 */ "fands \0"
  /* 1592 */ "fnands \0"
  /* 1600 */ "fones \0"
  /* 1607 */ "fcmpes \0"
  /* 1615 */ "fnegs \0"
  /* 1622 */ "fmuls \0"
  /* 1629 */ "fnmuls \0"
  /* 1637 */ "fzeros \0"
  /* 1645 */ "fdtos \0"
  /* 1652 */ "fitos \0"
  /* 1659 */ "fqtos \0"
  /* 1666 */ "movwtos \0"
  /* 1675 */ "fxtos \0"
  /* 1682 */ "fcmps \0"
  /* 1689 */ "flcmps \0"
  /* 1697 */ "fors \0"
  /* 1703 */ "fnors \0"
  /* 1710 */ "fxnors \0"
  /* 1718 */ "fxors \0"
  /* 1725 */ "fabss \0"
  /* 1732 */ "fsqrts \0"
  /* 1740 */ "fdivs \0"
  /* 1747 */ "fmovs \0"
  /* 1754 */ "set \0"
  /* 1759 */ "lzcnt \0"
  /* 1766 */ "pdist \0"
  /* 1773 */ "rett \0"
  /* 1779 */ "fmul8x16au \0"
  /* 1791 */ "sdiv \0"
  /* 1797 */ "udiv \0"
  /* 1803 */ "tsubcctv \0"
  /* 1813 */ "taddcctv \0"
  /* 1823 */ "movstosw \0"
  /* 1833 */ "movstouw \0"
  /* 1843 */ "srax \0"
  /* 1849 */ "subx \0"
  /* 1855 */ "addx \0"
  /* 1861 */ "fpackfix \0"
  /* 1871 */ "sllx \0"
  /* 1877 */ "srlx \0"
  /* 1883 */ "xmulx \0"
  /* 1890 */ "fdtox \0"
  /* 1897 */ "movdtox \0"
  /* 1906 */ "fqtox \0"
  /* 1913 */ "fstox \0"
  /* 1920 */ "setx \0"
  /* 1926 */ "stx \0"
  /* 1931 */ "sdivx \0"
  /* 1938 */ "udivx \0"
  /* 1945 */ "; SELECT_CC_DFP_FCC PSEUDO!\0"
  /* 1973 */ "; SELECT_CC_QFP_FCC PSEUDO!\0"
  /* 2001 */ "; SELECT_CC_FP_FCC PSEUDO!\0"
  /* 2028 */ "; SELECT_CC_Int_FCC PSEUDO!\0"
  /* 2056 */ "; SELECT_CC_DFP_ICC PSEUDO!\0"
  /* 2084 */ "; SELECT_CC_QFP_ICC PSEUDO!\0"
  /* 2112 */ "; SELECT_CC_FP_ICC PSEUDO!\0"
  /* 2139 */ "; SELECT_CC_Int_ICC PSEUDO!\0"
  /* 2167 */ "; SELECT_CC_DFP_XCC PSEUDO!\0"
  /* 2195 */ "; SELECT_CC_QFP_XCC PSEUDO!\0"
  /* 2223 */ "; SELECT_CC_FP_XCC PSEUDO!\0"
  /* 2250 */ "; SELECT_CC_Int_XCC PSEUDO!\0"
  /* 2278 */ "jmp %i7+\0"
  /* 2287 */ "jmp %o7+\0"
  /* 2296 */ "# XRay Function Patchable RET.\0"
  /* 2327 */ "# XRay Typed Event Log.\0"
  /* 2351 */ "# XRay Custom Event Log.\0"
  /* 2376 */ "# XRay Function Enter.\0"
  /* 2399 */ "# XRay Tail Call Exit.\0"
  /* 2422 */ "# XRay Function Exit.\0"
  /* 2444 */ "flush %g0\0"
  /* 2454 */ "ta 1\0"
  /* 2459 */ "ta 3\0"
  /* 2464 */ "ta 5\0"
  /* 2469 */ "LIFETIME_END\0"
  /* 2482 */ "PSEUDO_PROBE\0"
  /* 2495 */ "BUNDLE\0"
  /* 2502 */ "DBG_VALUE\0"
  /* 2512 */ "DBG_INSTR_REF\0"
  /* 2526 */ "DBG_PHI\0"
  /* 2534 */ "DBG_LABEL\0"
  /* 2544 */ "LIFETIME_START\0"
  /* 2559 */ "DBG_VALUE_LIST\0"
  /* 2574 */ "std %cq, [\0"
  /* 2585 */ "std %fq, [\0"
  /* 2596 */ "st %csr, [\0"
  /* 2607 */ "st %fsr, [\0"
  /* 2618 */ "stx %fsr, [\0"
  /* 2630 */ "ldsba [\0"
  /* 2638 */ "lduba [\0"
  /* 2646 */ "ldstuba [\0"
  /* 2656 */ "ldda [\0"
  /* 2663 */ "lda [\0"
  /* 2669 */ "ldsha [\0"
  /* 2677 */ "lduha [\0"
  /* 2685 */ "swapa [\0"
  /* 2693 */ "ldqa [\0"
  /* 2700 */ "casa [\0"
  /* 2707 */ "ldswa [\0"
  /* 2715 */ "ldxa [\0"
  /* 2722 */ "casxa [\0"
  /* 2730 */ "ldsb [\0"
  /* 2737 */ "ldub [\0"
  /* 2744 */ "ldstub [\0"
  /* 2753 */ "ldd [\0"
  /* 2759 */ "ld [\0"
  /* 2764 */ "prefetch [\0"
  /* 2775 */ "ldsh [\0"
  /* 2782 */ "lduh [\0"
  /* 2789 */ "swap [\0"
  /* 2796 */ "ldq [\0"
  /* 2802 */ "ldsw [\0"
  /* 2809 */ "ldx [\0"
  /* 2815 */ "cb\0"
  /* 2818 */ "fb\0"
  /* 2821 */ "restored\0"
  /* 2830 */ "saved\0"
  /* 2836 */ "fmovrd\0"
  /* 2843 */ "fmovd\0"
  /* 2849 */ "done\0"
  /* 2854 */ "# FEntry call\0"
  /* 2868 */ "siam\0"
  /* 2873 */ "shutdown\0"
  /* 2882 */ "nop\0"
  /* 2886 */ "fmovrq\0"
  /* 2893 */ "fmovq\0"
  /* 2899 */ "stbar\0"
  /* 2905 */ "br\0"
  /* 2908 */ "movr\0"
  /* 2913 */ "fmovrs\0"
  /* 2920 */ "fmovs\0"
  /* 2926 */ "t\0"
  /* 2928 */ "mov\0"
  /* 2932 */ "flushw\0"
  /* 2939 */ "retry\0"
};
#endif // CAPSTONE_DIET

  static const uint32_t OpInfo0[] = {
    0U, // PHI
    0U, // INLINEASM
    0U, // INLINEASM_BR
    0U, // CFI_INSTRUCTION
    0U, // EH_LABEL
    0U, // GC_LABEL
    0U, // ANNOTATION_LABEL
    0U, // KILL
    0U, // EXTRACT_SUBREG
    0U, // INSERT_SUBREG
    0U, // IMPLICIT_DEF
    0U, // SUBREG_TO_REG
    0U, // COPY_TO_REGCLASS
    2503U,  // DBG_VALUE
    2560U,  // DBG_VALUE_LIST
    2513U,  // DBG_INSTR_REF
    2527U,  // DBG_PHI
    2535U,  // DBG_LABEL
    0U, // REG_SEQUENCE
    0U, // COPY
    2496U,  // BUNDLE
    2545U,  // LIFETIME_START
    2470U,  // LIFETIME_END
    2483U,  // PSEUDO_PROBE
    0U, // ARITH_FENCE
    0U, // STACKMAP
    2855U,  // FENTRY_CALL
    0U, // PATCHPOINT
    0U, // LOAD_STACK_GUARD
    0U, // PREALLOCATED_SETUP
    0U, // PREALLOCATED_ARG
    0U, // STATEPOINT
    0U, // LOCAL_ESCAPE
    0U, // FAULTING_OP
    0U, // PATCHABLE_OP
    2377U,  // PATCHABLE_FUNCTION_ENTER
    2297U,  // PATCHABLE_RET
    2423U,  // PATCHABLE_FUNCTION_EXIT
    2400U,  // PATCHABLE_TAIL_CALL
    2352U,  // PATCHABLE_EVENT_CALL
    2328U,  // PATCHABLE_TYPED_EVENT_CALL
    0U, // ICALL_BRANCH_FUNNEL
    0U, // MEMBARRIER
    0U, // JUMP_TABLE_DEBUG_INFO
    0U, // G_ASSERT_SEXT
    0U, // G_ASSERT_ZEXT
    0U, // G_ASSERT_ALIGN
    0U, // G_ADD
    0U, // G_SUB
    0U, // G_MUL
    0U, // G_SDIV
    0U, // G_UDIV
    0U, // G_SREM
    0U, // G_UREM
    0U, // G_SDIVREM
    0U, // G_UDIVREM
    0U, // G_AND
    0U, // G_OR
    0U, // G_XOR
    0U, // G_IMPLICIT_DEF
    0U, // G_PHI
    0U, // G_FRAME_INDEX
    0U, // G_GLOBAL_VALUE
    0U, // G_CONSTANT_POOL
    0U, // G_EXTRACT
    0U, // G_UNMERGE_VALUES
    0U, // G_INSERT
    0U, // G_MERGE_VALUES
    0U, // G_BUILD_VECTOR
    0U, // G_BUILD_VECTOR_TRUNC
    0U, // G_CONCAT_VECTORS
    0U, // G_PTRTOINT
    0U, // G_INTTOPTR
    0U, // G_BITCAST
    0U, // G_FREEZE
    0U, // G_CONSTANT_FOLD_BARRIER
    0U, // G_INTRINSIC_FPTRUNC_ROUND
    0U, // G_INTRINSIC_TRUNC
    0U, // G_INTRINSIC_ROUND
    0U, // G_INTRINSIC_LRINT
    0U, // G_INTRINSIC_ROUNDEVEN
    0U, // G_READCYCLECOUNTER
    0U, // G_LOAD
    0U, // G_SEXTLOAD
    0U, // G_ZEXTLOAD
    0U, // G_INDEXED_LOAD
    0U, // G_INDEXED_SEXTLOAD
    0U, // G_INDEXED_ZEXTLOAD
    0U, // G_STORE
    0U, // G_INDEXED_STORE
    0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
    0U, // G_ATOMIC_CMPXCHG
    0U, // G_ATOMICRMW_XCHG
    0U, // G_ATOMICRMW_ADD
    0U, // G_ATOMICRMW_SUB
    0U, // G_ATOMICRMW_AND
    0U, // G_ATOMICRMW_NAND
    0U, // G_ATOMICRMW_OR
    0U, // G_ATOMICRMW_XOR
    0U, // G_ATOMICRMW_MAX
    0U, // G_ATOMICRMW_MIN
    0U, // G_ATOMICRMW_UMAX
    0U, // G_ATOMICRMW_UMIN
    0U, // G_ATOMICRMW_FADD
    0U, // G_ATOMICRMW_FSUB
    0U, // G_ATOMICRMW_FMAX
    0U, // G_ATOMICRMW_FMIN
    0U, // G_ATOMICRMW_UINC_WRAP
    0U, // G_ATOMICRMW_UDEC_WRAP
    0U, // G_FENCE
    0U, // G_PREFETCH
    0U, // G_BRCOND
    0U, // G_BRINDIRECT
    0U, // G_INVOKE_REGION_START
    0U, // G_INTRINSIC
    0U, // G_INTRINSIC_W_SIDE_EFFECTS
    0U, // G_INTRINSIC_CONVERGENT
    0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    0U, // G_ANYEXT
    0U, // G_TRUNC
    0U, // G_CONSTANT
    0U, // G_FCONSTANT
    0U, // G_VASTART
    0U, // G_VAARG
    0U, // G_SEXT
    0U, // G_SEXT_INREG
    0U, // G_ZEXT
    0U, // G_SHL
    0U, // G_LSHR
    0U, // G_ASHR
    0U, // G_FSHL
    0U, // G_FSHR
    0U, // G_ROTR
    0U, // G_ROTL
    0U, // G_ICMP
    0U, // G_FCMP
    0U, // G_SELECT
    0U, // G_UADDO
    0U, // G_UADDE
    0U, // G_USUBO
    0U, // G_USUBE
    0U, // G_SADDO
    0U, // G_SADDE
    0U, // G_SSUBO
    0U, // G_SSUBE
    0U, // G_UMULO
    0U, // G_SMULO
    0U, // G_UMULH
    0U, // G_SMULH
    0U, // G_UADDSAT
    0U, // G_SADDSAT
    0U, // G_USUBSAT
    0U, // G_SSUBSAT
    0U, // G_USHLSAT
    0U, // G_SSHLSAT
    0U, // G_SMULFIX
    0U, // G_UMULFIX
    0U, // G_SMULFIXSAT
    0U, // G_UMULFIXSAT
    0U, // G_SDIVFIX
    0U, // G_UDIVFIX
    0U, // G_SDIVFIXSAT
    0U, // G_UDIVFIXSAT
    0U, // G_FADD
    0U, // G_FSUB
    0U, // G_FMUL
    0U, // G_FMA
    0U, // G_FMAD
    0U, // G_FDIV
    0U, // G_FREM
    0U, // G_FPOW
    0U, // G_FPOWI
    0U, // G_FEXP
    0U, // G_FEXP2
    0U, // G_FEXP10
    0U, // G_FLOG
    0U, // G_FLOG2
    0U, // G_FLOG10
    0U, // G_FLDEXP
    0U, // G_FFREXP
    0U, // G_FNEG
    0U, // G_FPEXT
    0U, // G_FPTRUNC
    0U, // G_FPTOSI
    0U, // G_FPTOUI
    0U, // G_SITOFP
    0U, // G_UITOFP
    0U, // G_FABS
    0U, // G_FCOPYSIGN
    0U, // G_IS_FPCLASS
    0U, // G_FCANONICALIZE
    0U, // G_FMINNUM
    0U, // G_FMAXNUM
    0U, // G_FMINNUM_IEEE
    0U, // G_FMAXNUM_IEEE
    0U, // G_FMINIMUM
    0U, // G_FMAXIMUM
    0U, // G_GET_FPENV
    0U, // G_SET_FPENV
    0U, // G_RESET_FPENV
    0U, // G_GET_FPMODE
    0U, // G_SET_FPMODE
    0U, // G_RESET_FPMODE
    0U, // G_PTR_ADD
    0U, // G_PTRMASK
    0U, // G_SMIN
    0U, // G_SMAX
    0U, // G_UMIN
    0U, // G_UMAX
    0U, // G_ABS
    0U, // G_LROUND
    0U, // G_LLROUND
    0U, // G_BR
    0U, // G_BRJT
    0U, // G_INSERT_VECTOR_ELT
    0U, // G_EXTRACT_VECTOR_ELT
    0U, // G_SHUFFLE_VECTOR
    0U, // G_CTTZ
    0U, // G_CTTZ_ZERO_UNDEF
    0U, // G_CTLZ
    0U, // G_CTLZ_ZERO_UNDEF
    0U, // G_CTPOP
    0U, // G_BSWAP
    0U, // G_BITREVERSE
    0U, // G_FCEIL
    0U, // G_FCOS
    0U, // G_FSIN
    0U, // G_FSQRT
    0U, // G_FFLOOR
    0U, // G_FRINT
    0U, // G_FNEARBYINT
    0U, // G_ADDRSPACE_CAST
    0U, // G_BLOCK_ADDR
    0U, // G_JUMP_TABLE
    0U, // G_DYN_STACKALLOC
    0U, // G_STACKSAVE
    0U, // G_STACKRESTORE
    0U, // G_STRICT_FADD
    0U, // G_STRICT_FSUB
    0U, // G_STRICT_FMUL
    0U, // G_STRICT_FDIV
    0U, // G_STRICT_FREM
    0U, // G_STRICT_FMA
    0U, // G_STRICT_FSQRT
    0U, // G_STRICT_FLDEXP
    0U, // G_READ_REGISTER
    0U, // G_WRITE_REGISTER
    0U, // G_MEMCPY
    0U, // G_MEMCPY_INLINE
    0U, // G_MEMMOVE
    0U, // G_MEMSET
    0U, // G_BZERO
    0U, // G_VECREDUCE_SEQ_FADD
    0U, // G_VECREDUCE_SEQ_FMUL
    0U, // G_VECREDUCE_FADD
    0U, // G_VECREDUCE_FMUL
    0U, // G_VECREDUCE_FMAX
    0U, // G_VECREDUCE_FMIN
    0U, // G_VECREDUCE_FMAXIMUM
    0U, // G_VECREDUCE_FMINIMUM
    0U, // G_VECREDUCE_ADD
    0U, // G_VECREDUCE_MUL
    0U, // G_VECREDUCE_AND
    0U, // G_VECREDUCE_OR
    0U, // G_VECREDUCE_XOR
    0U, // G_VECREDUCE_SMAX
    0U, // G_VECREDUCE_SMIN
    0U, // G_VECREDUCE_UMAX
    0U, // G_VECREDUCE_UMIN
    0U, // G_SBFX
    0U, // G_UBFX
    4609U,  // ADJCALLSTACKDOWN
    70164U, // ADJCALLSTACKUP
    8206U,  // GETPCX
    1946U,  // SELECT_CC_DFP_FCC
    2057U,  // SELECT_CC_DFP_ICC
    2168U,  // SELECT_CC_DFP_XCC
    2002U,  // SELECT_CC_FP_FCC
    2113U,  // SELECT_CC_FP_ICC
    2224U,  // SELECT_CC_FP_XCC
    2029U,  // SELECT_CC_Int_FCC
    2140U,  // SELECT_CC_Int_ICC
    2251U,  // SELECT_CC_Int_XCC
    1974U,  // SELECT_CC_QFP_FCC
    2085U,  // SELECT_CC_QFP_ICC
    2196U,  // SELECT_CC_QFP_XCC
    2111195U, // SET
    20985729U,  // SETX
    20984449U,  // ADDCCri
    20984449U,  // ADDCCrr
    20985664U,  // ADDCri
    20985664U,  // ADDCrr
    20984541U,  // ADDEri
    20984541U,  // ADDErr
    20984555U,  // ADDXC
    20984439U,  // ADDXCCC
    20984577U,  // ADDri
    20984577U,  // ADDrr
    20985176U,  // ALIGNADDR
    20984933U,  // ALIGNADDRL
    20984456U,  // ANDCCri
    20984456U,  // ANDCCrr
    20984479U,  // ANDNCCri
    20984479U,  // ANDNCCrr
    20984988U,  // ANDNri
    20984988U,  // ANDNrr
    20984662U,  // ANDri
    20984662U,  // ANDrr
    20984289U,  // ARRAY16
    20984042U,  // ARRAY32
    20984313U,  // ARRAY8
    2247425U, // BCOND
    2312961U, // BCONDA
    87258U, // BINDri
    87258U, // BINDrr
    20984871U,  // BMASK
    21121795U,  // BPFCC
    21187331U,  // BPFCCA
    281347U,  // BPFCCANT
    346883U,  // BPFCCNT
    2509569U, // BPICC
    477953U,  // BPICCA
    543489U,  // BPICCANT
    609025U,  // BPICCNT
    21121882U,  // BPR
    21187418U,  // BPRA
    281434U,  // BPRANT
    346970U,  // BPRNT
    2771713U, // BPXCC
    740097U,  // BPXCCA
    805633U,  // BPXCCANT
    871169U,  // BPXCCNT
    20984782U,  // BSHUFFLE
    70740U, // CALL
    87124U, // CALLri
    87124U, // CALLrr
    21904013U,  // CASAri
    7289485U, // CASArr
    21904035U,  // CASXAri
    7289507U, // CASXArr
    2247424U, // CBCOND
    2312960U, // CBCONDA
    69980U, // CMASK16
    69812U, // CMASK32
    70129U, // CMASK8
    2850U,  // DONE
    20984119U,  // EDGE16
    20984887U,  // EDGE16L
    20985004U,  // EDGE16LN
    20984971U,  // EDGE16N
    20983951U,  // EDGE32
    20984878U,  // EDGE32L
    20984994U,  // EDGE32LN
    20984962U,  // EDGE32N
    20984298U,  // EDGE8
    20984896U,  // EDGE8L
    20985014U,  // EDGE8LN
    20984980U,  // EDGE8N
    2110371U, // FABSD
    2110766U, // FABSQ
    2111166U, // FABSS
    20984582U,  // FADDD
    20985062U,  // FADDQ
    20985362U,  // FADDS
    20984386U,  // FALIGNADATA
    20984661U,  // FAND
    20983899U,  // FANDNOT1
    20985241U,  // FANDNOT1S
    20984058U,  // FANDNOT2
    20985298U,  // FANDNOT2S
    20985394U,  // FANDS
    2247427U, // FBCOND
    2312963U, // FBCONDA
    1067779U, // FBCONDA_V9
    3230467U, // FBCOND_V9
    20984181U,  // FCHKSM16
    5008U,  // FCMPD
    4097U,  // FCMPD_V9
    20984200U,  // FCMPEQ16
    20984013U,  // FCMPEQ32
    20984219U,  // FCMPGT16
    20984032U,  // FCMPGT32
    20984127U,  // FCMPLE16
    20983959U,  // FCMPLE32
    20984137U,  // FCMPNE16
    20983969U,  // FCMPNE32
    5415U,  // FCMPQ
    4111U,  // FCMPQ_V9
    5779U,  // FCMPS
    4125U,  // FCMPS_V9
    20984759U,  // FDIVD
    20985154U,  // FDIVQ
    20985549U,  // FDIVS
    20985084U,  // FDMULQ
    2110482U, // FDTOI
    2110731U, // FDTOQ
    2111086U, // FDTOS
    2111331U, // FDTOX
    2110306U, // FEXPAND
    20984589U,  // FHADDD
    20985369U,  // FHADDS
    20984569U,  // FHSUBD
    20985354U,  // FHSUBS
    2110315U, // FITOD
    2110738U, // FITOQ
    2111093U, // FITOS
    150999959U, // FLCMPD
    151000730U, // FLCMPS
    2445U,  // FLUSH
    2933U,  // FLUSHW
    87021U, // FLUSHri
    87021U, // FLUSHrr
    20984191U,  // FMEAN16
    2110398U, // FMOVD
    17918748U,  // FMOVD_FCC
    17197852U,  // FMOVD_ICC
    17459996U,  // FMOVD_XCC
    2110793U, // FMOVQ
    17918798U,  // FMOVQ_FCC
    17197902U,  // FMOVQ_ICC
    17460046U,  // FMOVQ_XCC
    31509U, // FMOVRD
    31559U, // FMOVRQ
    31586U, // FMOVRS
    2111188U, // FMOVS
    17918825U,  // FMOVS_FCC
    17197929U,  // FMOVS_ICC
    17460073U,  // FMOVS_XCC
    20984277U,  // FMUL8SUX16
    20984252U,  // FMUL8ULX16
    20984229U,  // FMUL8X16
    20984904U,  // FMUL8X16AL
    20985588U,  // FMUL8X16AU
    20984629U,  // FMULD
    20984264U,  // FMULD8SUX16
    20984239U,  // FMULD8ULX16
    20985092U,  // FMULQ
    20985431U,  // FMULS
    20984606U,  // FNADDD
    20985386U,  // FNADDS
    20984667U,  // FNAND
    20985401U,  // FNANDS
    2110254U, // FNEGD
    2110709U, // FNEGQ
    2111056U, // FNEGS
    20984597U,  // FNHADDD
    20985377U,  // FNHADDS
    20984636U,  // FNMULD
    20985438U,  // FNMULS
    20985197U,  // FNOR
    20985512U,  // FNORS
    2109541U, // FNOT1
    2110884U, // FNOT1S
    2109700U, // FNOT2
    2110941U, // FNOT2S
    20984652U,  // FNSMULD
    70616U, // FONE
    71233U, // FONES
    20985192U,  // FOR
    20983916U,  // FORNOT1
    20985260U,  // FORNOT1S
    20984075U,  // FORNOT2
    20985317U,  // FORNOT2S
    20985506U,  // FORS
    2109779U, // FPACK16
    20983979U,  // FPACK32
    2111302U, // FPACKFIX
    20984110U,  // FPADD16
    20985337U,  // FPADD16S
    20983942U,  // FPADD32
    20985280U,  // FPADD32S
    20984084U,  // FPADD64
    20984773U,  // FPMERGE
    20984101U,  // FPSUB16
    20985327U,  // FPSUB16S
    20983933U,  // FPSUB32
    20985270U,  // FPSUB32S
    2110322U, // FQTOD
    2110489U, // FQTOI
    2111100U, // FQTOS
    2111347U, // FQTOX
    20984210U,  // FSLAS16
    20984023U,  // FSLAS32
    20984165U,  // FSLL16
    20983997U,  // FSLL32
    20984644U,  // FSMULD
    2110378U, // FSQRTD
    2110773U, // FSQRTQ
    2111173U, // FSQRTS
    20984093U,  // FSRA16
    20983925U,  // FSRA32
    2109524U, // FSRC1
    2110865U, // FSRC1S
    2109683U, // FSRC2
    2110922U, // FSRC2S
    20984173U,  // FSRL16
    20984005U,  // FSRL32
    2110329U, // FSTOD
    2110496U, // FSTOI
    2110745U, // FSTOQ
    2111354U, // FSTOX
    20984562U,  // FSUBD
    20985055U,  // FSUBQ
    20985347U,  // FSUBS
    20985203U,  // FXNOR
    20985519U,  // FXNORS
    20985210U,  // FXOR
    20985527U,  // FXORS
    2110336U, // FXTOD
    2110752U, // FXTOQ
    2111116U, // FXTOS
    70860U, // FZERO
    71270U, // FZEROS
    288525050U, // GDOP_LDXrr
    288525000U, // GDOP_LDrr
    2131039U, // JMPLri
    2131039U, // JMPLrr
    3050088U, // LDAri
    26184296U,  // LDArr
    1268424U, // LDCSRri
    1268424U, // LDCSRrr
    3312328U, // LDCri
    3312328U, // LDCrr
    3050081U, // LDDAri
    26184289U,  // LDDArr
    3312322U, // LDDCri
    3312322U, // LDDCrr
    3050081U, // LDDFAri
    26184289U,  // LDDFArr
    3312322U, // LDDFri
    3312322U, // LDDFrr
    3312322U, // LDDri
    3312322U, // LDDrr
    3050088U, // LDFAri
    26184296U,  // LDFArr
    1333960U, // LDFSRri
    1333960U, // LDFSRrr
    3312328U, // LDFri
    3312328U, // LDFrr
    3050118U, // LDQFAri
    26184326U,  // LDQFArr
    3312365U, // LDQFri
    3312365U, // LDQFrr
    3050055U, // LDSBAri
    26184263U,  // LDSBArr
    3312299U, // LDSBri
    3312299U, // LDSBrr
    3050094U, // LDSHAri
    26184302U,  // LDSHArr
    3312344U, // LDSHri
    3312344U, // LDSHrr
    3050071U, // LDSTUBAri
    26184279U,  // LDSTUBArr
    3312313U, // LDSTUBri
    3312313U, // LDSTUBrr
    3050132U, // LDSWAri
    26184340U,  // LDSWArr
    3312371U, // LDSWri
    3312371U, // LDSWrr
    3050063U, // LDUBAri
    26184271U,  // LDUBArr
    3312306U, // LDUBri
    3312306U, // LDUBrr
    3050102U, // LDUHAri
    26184310U,  // LDUHArr
    3312351U, // LDUHri
    3312351U, // LDUHrr
    3050140U, // LDXAri
    26184348U,  // LDXArr
    1334010U, // LDXFSRri
    1334010U, // LDXFSRrr
    3312378U, // LDXri
    3312378U, // LDXrr
    3312328U, // LDri
    3312328U, // LDrr
    2111200U, // LZCNT
    38224U, // MEMBARi
    2111338U, // MOVDTOX
    17918833U,  // MOVFCCri
    17918833U,  // MOVFCCrr
    17197937U,  // MOVICCri
    17197937U,  // MOVICCrr
    31581U, // MOVRri
    31581U, // MOVRrr
    2111264U, // MOVSTOSW
    2111274U, // MOVSTOUW
    2111107U, // MOVWTOS
    17460081U,  // MOVXCCri
    17460081U,  // MOVXCCrr
    2110343U, // MOVXTOD
    20984509U,  // MULSCCri
    20984509U,  // MULSCCrr
    20985693U,  // MULXri
    20985693U,  // MULXrr
    2883U,  // NOP
    20984496U,  // ORCCri
    20984496U,  // ORCCrr
    20984487U,  // ORNCCri
    20984487U,  // ORNCCrr
    20985023U,  // ORNri
    20985023U,  // ORNrr
    20985193U,  // ORri
    20985193U,  // ORrr
    20985575U,  // PDIST
    20985028U,  // PDISTN
    2110181U, // POPCrr
    5397197U, // PREFETCHi
    5397197U, // PREFETCHr
    33559948U,  // PWRPSRri
    33559948U,  // PWRPSRrr
    2110367U, // RDASR
    69685U, // RDFQ
    2110848U, // RDPR
    69706U, // RDPSR
    69696U, // RDTBR
    69675U, // RDWIM
    2822U,  // RESTORED
    20984798U,  // RESTOREri
    20984798U,  // RESTORErr
    71911U, // RET
    71920U, // RETL
    2940U,  // RETRY
    87790U, // RETTri
    87790U, // RETTrr
    2831U,  // SAVED
    20984807U,  // SAVEri
    20984807U,  // SAVErr
    20984517U,  // SDIVCCri
    20984517U,  // SDIVCCrr
    20985740U,  // SDIVXri
    20985740U,  // SDIVXrr
    20985600U,  // SDIVri
    20985600U,  // SDIVrr
    2110457U, // SETHIi
    2874U,  // SHUTDOWN
    2869U,  // SIAM
    71011U, // SIR
    20985680U,  // SLLXri
    20985680U,  // SLLXrr
    20984922U,  // SLLri
    20984922U,  // SLLrr
    20984419U,  // SMACri
    20984419U,  // SMACrr
    20984463U,  // SMULCCri
    20984463U,  // SMULCCrr
    20984950U,  // SMULri
    20984950U,  // SMULrr
    20985652U,  // SRAXri
    20985652U,  // SRAXrr
    20984381U,  // SRAri
    20984381U,  // SRArr
    20985686U,  // SRLXri
    20985686U,  // SRLXrr
    20984945U,  // SRLri
    20984945U,  // SRLrr
    1417806U, // STAri
    9413198U, // STArr
    2900U,  // STBAR
    1417765U, // STBAri
    9413157U, // STBArr
    1483353U, // STBri
    1483353U, // STBrr
    1464869U, // STCSRri
    1464869U, // STCSRrr
    1484522U, // STCri
    1484522U, // STCrr
    1417771U, // STDAri
    9413163U, // STDArr
    1464847U, // STDCQri
    1464847U, // STDCQrr
    1483698U, // STDCri
    1483698U, // STDCrr
    1417771U, // STDFAri
    9413163U, // STDFArr
    1464858U, // STDFQri
    1464858U, // STDFQrr
    1483698U, // STDFri
    1483698U, // STDFrr
    1483698U, // STDri
    1483698U, // STDrr
    1417806U, // STFAri
    9413198U, // STFArr
    1464880U, // STFSRri
    1464880U, // STFSRrr
    1484522U, // STFri
    1484522U, // STFrr
    1417777U, // STHAri
    9413169U, // STHArr
    1483764U, // STHri
    1483764U, // STHrr
    1417783U, // STQFAri
    9413175U, // STQFArr
    1484093U, // STQFri
    1484093U, // STQFrr
    1417811U, // STXAri
    9413203U, // STXArr
    1464891U, // STXFSRri
    1464891U, // STXFSRrr
    1484679U, // STXri
    1484679U, // STXrr
    1484522U, // STri
    1484522U, // STrr
    20984432U,  // SUBCCri
    20984432U,  // SUBCCrr
    20985658U,  // SUBCri
    20985658U,  // SUBCrr
    20984533U,  // SUBEri
    20984533U,  // SUBErr
    20984414U,  // SUBri
    20984414U,  // SUBrr
    3050110U, // SWAPAri
    26184318U,  // SWAPArr
    3312358U, // SWAPri
    3312358U, // SWAPrr
    2455U,  // TA1
    2460U,  // TA3
    2465U,  // TA5
    20985622U,  // TADDCCTVri
    20985622U,  // TADDCCTVrr
    20984448U,  // TADDCCri
    20984448U,  // TADDCCrr
    70740U, // TAIL_CALL
    87258U, // TAIL_CALLri
    52869999U,  // TICCri
    52869999U,  // TICCrr
    557855489U, // TLS_ADDrr
    5204U,  // TLS_CALL
    288525050U, // TLS_LDXrr
    288525000U, // TLS_LDrr
    52607855U,  // TRAPri
    52607855U,  // TRAPrr
    20985612U,  // TSUBCCTVri
    20985612U,  // TSUBCCTVrr
    20984431U,  // TSUBCCri
    20984431U,  // TSUBCCrr
    53132143U,  // TXCCri
    53132143U,  // TXCCrr
    20984525U,  // UDIVCCri
    20984525U,  // UDIVCCrr
    20985747U,  // UDIVXri
    20985747U,  // UDIVXrr
    20985606U,  // UDIVri
    20985606U,  // UDIVrr
    20984425U,  // UMACri
    20984425U,  // UMACrr
    20984471U,  // UMULCCri
    20984471U,  // UMULCCrr
    20984832U,  // UMULXHI
    20984956U,  // UMULri
    20984956U,  // UMULrr
    70867U, // UNIMP
    150999952U, // V9FCMPD
    150999846U, // V9FCMPED
    151000301U, // V9FCMPEQ
    151000648U, // V9FCMPES
    151000359U, // V9FCMPQ
    151000723U, // V9FCMPS
    31516U, // V9FMOVD_FCC
    31566U, // V9FMOVQ_FCC
    31593U, // V9FMOVS_FCC
    31601U, // V9MOVFCCri
    31601U, // V9MOVFCCrr
    20985229U,  // WRASRri
    20985229U,  // WRASRrr
    20985222U,  // WRPRri
    20985222U,  // WRPRrr
    33559949U,  // WRPSRri
    33559949U,  // WRPSRrr
    67114381U,  // WRTBRri
    67114381U,  // WRTBRrr
    83891597U,  // WRWIMri
    83891597U,  // WRWIMrr
    20985692U,  // XMULX
    20984841U,  // XMULXHI
    20984494U,  // XNORCCri
    20984494U,  // XNORCCrr
    20985204U,  // XNORri
    20985204U,  // XNORrr
    20984502U,  // XORCCri
    20984502U,  // XORCCrr
    20985211U,  // XORri
    20985211U,  // XORrr
  };

  // Emit the opcode for the instruction.
  uint32_t Bits = 0;
  Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0;
  MnemonicBitsInfo MBI = {
#ifndef CAPSTONE_DIET
    AsmStrs+(Bits & 4095)-1,
#else
    NULL,
#endif // CAPSTONE_DIET
    Bits
  };
  return MBI;
}

/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
  SStream_concat0(O, "");
  MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O);

  SStream_concat0(O, MnemonicInfo.first);

  uint32_t Bits = MnemonicInfo.second;
  CS_ASSERT_RET(Bits != 0 && "Cannot print this instruction.");

  // Fragment 0 encoded into 4 bits for 12 unique commands.
  switch ((Bits >> 12) & 15) {
  default: CS_ASSERT_RET(0 && "Invalid command number.");
  case 0:
    // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
    return;
    break;
  case 1:
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, CALL, CMASK16, CMASK32, CMASK8, FCMP...
    printOperand(MI, 0, O);
    break;
  case 2:
    // GETPCX
    printGetPCX(MI, 0, O);
    return;
    break;
  case 3:
    // SET, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, AD...
    printOperand(MI, 1, O);
    break;
  case 4:
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
    printCCOperand(MI, 1, O);
    break;
  case 5:
    // BINDri, BINDrr, CALLri, CALLrr, FLUSHri, FLUSHrr, LDCSRri, LDCSRrr, LD...
    printMemOperand(MI, 0, O);
    break;
  case 6:
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
    printCCOperand(MI, 3, O);
    break;
  case 7:
    // FMOVRD, FMOVRQ, FMOVRS, MOVRri, MOVRrr, V9FMOVD_FCC, V9FMOVQ_FCC, V9FM...
    printCCOperand(MI, 4, O);
    SStream_concat1(O, ' ');
    printOperand(MI, 1, O);
    SStream_concat0(O, ", ");
    printOperand(MI, 2, O);
    SStream_concat0(O, ", ");
    printOperand(MI, 0, O);
    return;
    break;
  case 8:
    // GDOP_LDXrr, GDOP_LDrr, JMPLri, JMPLrr, LDAri, LDArr, LDCri, LDCrr, LDD...
    printMemOperand(MI, 1, O);
    break;
  case 9:
    // MEMBARi
    printMembarTag(MI, 0, O);
    return;
    break;
  case 10:
    // STAri, STArr, STBAri, STBArr, STBri, STBrr, STCri, STCrr, STDAri, STDA...
    printOperand(MI, 2, O);
    SStream_concat0(O, ", [");
    printMemOperand(MI, 0, O);
    break;
  case 11:
    // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
    printCCOperand(MI, 2, O);
    break;
  }


  // Fragment 1 encoded into 5 bits for 23 unique commands.
  switch ((Bits >> 16) & 31) {
  default: CS_ASSERT_RET(0 && "Invalid command number.");
  case 0:
    // ADJCALLSTACKDOWN, SET, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri,...
    SStream_concat0(O, ", ");
    break;
  case 1:
    // ADJCALLSTACKUP, BINDri, BINDrr, CALL, CALLri, CALLrr, CMASK16, CMASK32...
    return;
    break;
  case 2:
    // BCOND, BPFCC, BPR, CBCOND, FBCOND, TRAPri, TRAPrr
    SStream_concat1(O, ' ');
    break;
  case 3:
    // BCONDA, BPFCCA, BPRA, CBCONDA, FBCONDA
    SStream_concat0(O, ",a ");
    break;
  case 4:
    // BPFCCANT, BPRANT
    SStream_concat0(O, ",a,pn ");
    printOperand(MI, 2, O);
    SStream_concat0(O, ", ");
    printOperand(MI, 0, O);
    return;
    break;
  case 5:
    // BPFCCNT, BPRNT
    SStream_concat0(O, ",pn ");
    printOperand(MI, 2, O);
    SStream_concat0(O, ", ");
    printOperand(MI, 0, O);
    return;
    break;
  case 6:
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
    SStream_concat0(O, " %icc, ");
    break;
  case 7:
    // BPICCA
    SStream_concat0(O, ",a %icc, ");
    printOperand(MI, 0, O);
    return;
    break;
  case 8:
    // BPICCANT
    SStream_concat0(O, ",a,pn %icc, ");
    printOperand(MI, 0, O);
    return;
    break;
  case 9:
    // BPICCNT
    SStream_concat0(O, ",pn %icc, ");
    printOperand(MI, 0, O);
    return;
    break;
  case 10:
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
    SStream_concat0(O, " %xcc, ");
    break;
  case 11:
    // BPXCCA
    SStream_concat0(O, ",a %xcc, ");
    printOperand(MI, 0, O);
    return;
    break;
  case 12:
    // BPXCCANT
    SStream_concat0(O, ",a,pn %xcc, ");
    printOperand(MI, 0, O);
    return;
    break;
  case 13:
    // BPXCCNT
    SStream_concat0(O, ",pn %xcc, ");
    printOperand(MI, 0, O);
    return;
    break;
  case 14:
    // CASAri, CASXAri, LDAri, LDDAri, LDDFAri, LDFAri, LDQFAri, LDSBAri, LDS...
    SStream_concat0(O, "] %asi, ");
    break;
  case 15:
    // CASArr, CASXArr, LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDS...
    SStream_concat0(O, "] ");
    break;
  case 16:
    // FBCONDA_V9
    SStream_concat0(O, ",a %fcc0, ");
    printOperand(MI, 0, O);
    return;
    break;
  case 17:
    // FBCOND_V9, FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
    SStream_concat0(O, " %fcc0, ");
    break;
  case 18:
    // GDOP_LDXrr, GDOP_LDrr, LDCri, LDCrr, LDDCri, LDDCrr, LDDFri, LDDFrr, L...
    SStream_concat0(O, "], ");
    break;
  case 19:
    // LDCSRri, LDCSRrr
    SStream_concat0(O, "], %csr");
    return;
    break;
  case 20:
    // LDFSRri, LDFSRrr, LDXFSRri, LDXFSRrr
    SStream_concat0(O, "], %fsr");
    return;
    break;
  case 21:
    // STAri, STBAri, STDAri, STDFAri, STFAri, STHAri, STQFAri, STXAri
    SStream_concat0(O, "] %asi");
    return;
    break;
  case 22:
    // STBri, STBrr, STCSRri, STCSRrr, STCri, STCrr, STDCQri, STDCQrr, STDCri...
    SStream_concat1(O, ']');
    return;
    break;
  }


  // Fragment 2 encoded into 3 bits for 5 unique commands.
  switch ((Bits >> 21) & 7) {
  default: CS_ASSERT_RET(0 && "Invalid command number.");
  case 0:
    // ADJCALLSTACKDOWN, FCMPD, FCMPD_V9, FCMPQ, FCMPQ_V9, FCMPS, FCMPS_V9, F...
    printOperand(MI, 1, O);
    break;
  case 1:
    // SET, BCOND, BCONDA, BPICC, BPXCC, CBCOND, CBCONDA, FABSD, FABSQ, FABSS...
    printOperand(MI, 0, O);
    break;
  case 2:
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
    printOperand(MI, 2, O);
    break;
  case 3:
    // CASArr, CASXArr
    printASITag(MI, 4, O);
    SStream_concat0(O, ", ");
    printOperand(MI, 2, O);
    SStream_concat0(O, ", ");
    printOperand(MI, 0, O);
    return;
    break;
  case 4:
    // LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDSHArr, LDSTUBArr, ...
    printASITag(MI, 3, O);
    break;
  }


  // Fragment 3 encoded into 3 bits for 6 unique commands.
  switch ((Bits >> 24) & 7) {
  default: CS_ASSERT_RET(0 && "Invalid command number.");
  case 0:
    // ADJCALLSTACKDOWN, SET, BCOND, BCONDA, BPICC, BPXCC, CBCOND, CBCONDA, F...
    return;
    break;
  case 1:
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
    SStream_concat0(O, ", ");
    break;
  case 2:
    // PWRPSRri, PWRPSRrr, WRPSRri, WRPSRrr
    SStream_concat0(O, ", %psr");
    return;
    break;
  case 3:
    // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
    SStream_concat0(O, " + ");
    printOperand(MI, 1, O);
    return;
    break;
  case 4:
    // WRTBRri, WRTBRrr
    SStream_concat0(O, ", %tbr");
    return;
    break;
  case 5:
    // WRWIMri, WRWIMrr
    SStream_concat0(O, ", %wim");
    return;
    break;
  }


  // Fragment 4 encoded into 2 bits for 3 unique commands.
  switch ((Bits >> 27) & 3) {
  default: CS_ASSERT_RET(0 && "Invalid command number.");
  case 0:
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
    printOperand(MI, 0, O);
    break;
  case 1:
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
    printOperand(MI, 2, O);
    return;
    break;
  case 2:
    // GDOP_LDXrr, GDOP_LDrr, TLS_LDXrr, TLS_LDrr
    printOperand(MI, 3, O);
    return;
    break;
  }


  // Fragment 5 encoded into 1 bits for 2 unique commands.
  if ((Bits >> 29) & 1) {
    // TLS_ADDrr
    SStream_concat0(O, ", ");
    printOperand(MI, 3, O);
    return;
  } else {
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
    return;
  }

}


/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description.  This returns the assembler name
/// for the specified register.
static const char *
getRegisterName(unsigned RegNo, unsigned AltIdx) {
#ifndef CAPSTONE_DIET
  CS_ASSERT_RET_VAL(RegNo && RegNo < 238 && "Invalid register number!", NULL);

  static const char AsmStrsNoRegAltName[] = {
  /* 0 */ "c10\0"
  /* 4 */ "f10\0"
  /* 8 */ "asr10\0"
  /* 14 */ "c20\0"
  /* 18 */ "f20\0"
  /* 22 */ "asr20\0"
  /* 28 */ "c30\0"
  /* 32 */ "f30\0"
  /* 36 */ "asr30\0"
  /* 42 */ "f40\0"
  /* 46 */ "f50\0"
  /* 50 */ "f60\0"
  /* 54 */ "fcc0\0"
  /* 59 */ "f0\0"
  /* 62 */ "g0\0"
  /* 65 */ "i0\0"
  /* 68 */ "l0\0"
  /* 71 */ "o0\0"
  /* 74 */ "c11\0"
  /* 78 */ "f11\0"
  /* 82 */ "asr11\0"
  /* 88 */ "c21\0"
  /* 92 */ "f21\0"
  /* 96 */ "asr21\0"
  /* 102 */ "c31\0"
  /* 106 */ "f31\0"
  /* 110 */ "asr31\0"
  /* 116 */ "fcc1\0"
  /* 121 */ "f1\0"
  /* 124 */ "g1\0"
  /* 127 */ "i1\0"
  /* 130 */ "l1\0"
  /* 133 */ "o1\0"
  /* 136 */ "asr1\0"
  /* 141 */ "c12\0"
  /* 145 */ "f12\0"
  /* 149 */ "asr12\0"
  /* 155 */ "c22\0"
  /* 159 */ "f22\0"
  /* 163 */ "asr22\0"
  /* 169 */ "f32\0"
  /* 173 */ "f42\0"
  /* 177 */ "f52\0"
  /* 181 */ "f62\0"
  /* 185 */ "fcc2\0"
  /* 190 */ "f2\0"
  /* 193 */ "g2\0"
  /* 196 */ "i2\0"
  /* 199 */ "l2\0"
  /* 202 */ "o2\0"
  /* 205 */ "asr2\0"
  /* 210 */ "c13\0"
  /* 214 */ "f13\0"
  /* 218 */ "asr13\0"
  /* 224 */ "c23\0"
  /* 228 */ "f23\0"
  /* 232 */ "asr23\0"
  /* 238 */ "fcc3\0"
  /* 243 */ "f3\0"
  /* 246 */ "g3\0"
  /* 249 */ "i3\0"
  /* 252 */ "l3\0"
  /* 255 */ "o3\0"
  /* 258 */ "asr3\0"
  /* 263 */ "c14\0"
  /* 267 */ "f14\0"
  /* 271 */ "asr14\0"
  /* 277 */ "c24\0"
  /* 281 */ "f24\0"
  /* 285 */ "asr24\0"
  /* 291 */ "f34\0"
  /* 295 */ "f44\0"
  /* 299 */ "f54\0"
  /* 303 */ "c4\0"
  /* 306 */ "f4\0"
  /* 309 */ "g4\0"
  /* 312 */ "i4\0"
  /* 315 */ "l4\0"
  /* 318 */ "o4\0"
  /* 321 */ "asr4\0"
  /* 326 */ "c15\0"
  /* 330 */ "f15\0"
  /* 334 */ "asr15\0"
  /* 340 */ "c25\0"
  /* 344 */ "f25\0"
  /* 348 */ "asr25\0"
  /* 354 */ "c5\0"
  /* 357 */ "f5\0"
  /* 360 */ "g5\0"
  /* 363 */ "i5\0"
  /* 366 */ "l5\0"
  /* 369 */ "o5\0"
  /* 372 */ "asr5\0"
  /* 377 */ "c16\0"
  /* 381 */ "f16\0"
  /* 385 */ "asr16\0"
  /* 391 */ "c26\0"
  /* 395 */ "f26\0"
  /* 399 */ "asr26\0"
  /* 405 */ "f36\0"
  /* 409 */ "f46\0"
  /* 413 */ "f56\0"
  /* 417 */ "c6\0"
  /* 420 */ "f6\0"
  /* 423 */ "g6\0"
  /* 426 */ "i6\0"
  /* 429 */ "l6\0"
  /* 432 */ "o6\0"
  /* 435 */ "asr6\0"
  /* 440 */ "c17\0"
  /* 444 */ "f17\0"
  /* 448 */ "asr17\0"
  /* 454 */ "c27\0"
  /* 458 */ "f27\0"
  /* 462 */ "asr27\0"
  /* 468 */ "c7\0"
  /* 471 */ "f7\0"
  /* 474 */ "g7\0"
  /* 477 */ "i7\0"
  /* 480 */ "l7\0"
  /* 483 */ "o7\0"
  /* 486 */ "asr7\0"
  /* 491 */ "c18\0"
  /* 495 */ "f18\0"
  /* 499 */ "asr18\0"
  /* 505 */ "c28\0"
  /* 509 */ "f28\0"
  /* 513 */ "asr28\0"
  /* 519 */ "f38\0"
  /* 523 */ "f48\0"
  /* 527 */ "f58\0"
  /* 531 */ "c8\0"
  /* 534 */ "f8\0"
  /* 537 */ "asr8\0"
  /* 542 */ "c19\0"
  /* 546 */ "f19\0"
  /* 550 */ "asr19\0"
  /* 556 */ "c29\0"
  /* 560 */ "f29\0"
  /* 564 */ "asr29\0"
  /* 570 */ "c9\0"
  /* 573 */ "f9\0"
  /* 576 */ "asr9\0"
  /* 581 */ "tba\0"
  /* 585 */ "icc\0"
  /* 589 */ "tnpc\0"
  /* 594 */ "tpc\0"
  /* 598 */ "canrestore\0"
  /* 609 */ "pstate\0"
  /* 616 */ "tstate\0"
  /* 623 */ "wstate\0"
  /* 630 */ "cansave\0"
  /* 638 */ "tick\0"
  /* 643 */ "gl\0"
  /* 646 */ "pil\0"
  /* 650 */ "tl\0"
  /* 653 */ "wim\0"
  /* 657 */ "cleanwin\0"
  /* 666 */ "otherwin\0"
  /* 675 */ "fp\0"
  /* 678 */ "sp\0"
  /* 681 */ "cwp\0"
  /* 685 */ "cq\0"
  /* 688 */ "fq\0"
  /* 691 */ "tbr\0"
  /* 695 */ "ver\0"
  /* 699 */ "csr\0"
  /* 703 */ "fsr\0"
  /* 707 */ "psr\0"
  /* 711 */ "tt\0"
  /* 714 */ "y\0"
};
  static const uint16_t RegAsmOffsetNoRegAltName[] = {
    598, 630, 657, 685, 699, 681, 688, 703, 643, 585, 666, 646, 707, 609, 
    581, 691, 638, 650, 589, 594, 616, 711, 695, 653, 623, 714, 136, 205, 
    258, 321, 372, 435, 486, 537, 576, 8, 82, 149, 218, 271, 334, 385, 
    448, 499, 550, 22, 96, 163, 232, 285, 348, 399, 462, 513, 564, 36, 
    110, 56, 118, 187, 240, 303, 354, 417, 468, 531, 570, 0, 74, 141, 
    210, 263, 326, 377, 440, 491, 542, 14, 88, 155, 224, 277, 340, 391, 
    454, 505, 556, 28, 102, 59, 190, 306, 420, 534, 4, 145, 267, 381, 
    495, 18, 159, 281, 395, 509, 32, 169, 291, 405, 519, 42, 173, 295, 
    409, 523, 46, 177, 299, 413, 527, 50, 181, 59, 121, 190, 243, 306, 
    357, 420, 471, 534, 573, 4, 78, 145, 214, 267, 330, 381, 444, 495, 
    546, 18, 92, 159, 228, 281, 344, 395, 458, 509, 560, 32, 106, 54, 
    116, 185, 238, 62, 124, 193, 246, 309, 360, 423, 474, 65, 127, 196, 
    249, 312, 363, 675, 477, 68, 130, 199, 252, 315, 366, 429, 480, 71, 
    133, 202, 255, 318, 369, 678, 483, 59, 306, 534, 145, 381, 18, 281, 
    509, 169, 405, 42, 295, 523, 177, 413, 50, 56, 187, 303, 417, 531, 
    0, 141, 263, 377, 491, 14, 155, 277, 391, 505, 28, 62, 193, 309, 
    423, 65, 196, 312, 426, 68, 199, 315, 429, 71, 202, 318, 432, 
  };

  static const char AsmStrsRegNamesStateReg[] = {
  /* 0 */ "pc\0"
  /* 3 */ "asi\0"
  /* 7 */ "tick\0"
  /* 12 */ "ccr\0"
  /* 16 */ "fprs\0"
};
  static const uint8_t RegAsmOffsetRegNamesStateReg[] = {
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 12, 
    3, 7, 0, 16, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
  };

  switch(AltIdx) {
  default: CS_ASSERT_RET_VAL(0 && "Invalid register alt name index!", NULL);
  case Sparc_NoRegAltName:
    CS_ASSERT_RET_VAL(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
           "Invalid alt name index for register!", NULL);
    return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
  case Sparc_RegNamesStateReg:
    if (!*(AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1]))
      return getRegisterName(RegNo, Sparc_NoRegAltName);
    return AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1];
  }
#else
  return NULL;
#endif // CAPSTONE_DIET
}
#ifdef PRINT_ALIAS_INSTR
#undef PRINT_ALIAS_INSTR

static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) {
#ifndef CAPSTONE_DIET
  static const PatternsForOpcode OpToPatterns[] = {
    {Sparc_BCOND, 0, 16 },
    {Sparc_BCONDA, 16, 16 },
    {Sparc_BPFCCANT, 32, 16 },
    {Sparc_BPFCCNT, 48, 16 },
    {Sparc_BPICCANT, 64, 16 },
    {Sparc_BPICCNT, 80, 16 },
    {Sparc_BPRANT, 96, 6 },
    {Sparc_BPRNT, 102, 6 },
    {Sparc_BPXCCANT, 108, 16 },
    {Sparc_BPXCCNT, 124, 16 },
    {Sparc_CASArr, 140, 2 },
    {Sparc_CASXArr, 142, 2 },
    {Sparc_FMOVD_ICC, 144, 16 },
    {Sparc_FMOVD_XCC, 160, 16 },
    {Sparc_FMOVQ_ICC, 176, 16 },
    {Sparc_FMOVQ_XCC, 192, 16 },
    {Sparc_FMOVRD, 208, 6 },
    {Sparc_FMOVRQ, 214, 6 },
    {Sparc_FMOVRS, 220, 6 },
    {Sparc_FMOVS_ICC, 226, 16 },
    {Sparc_FMOVS_XCC, 242, 16 },
    {Sparc_MOVICCri, 258, 16 },
    {Sparc_MOVICCrr, 274, 16 },
    {Sparc_MOVRri, 290, 6 },
    {Sparc_MOVRrr, 296, 6 },
    {Sparc_MOVXCCri, 302, 16 },
    {Sparc_MOVXCCrr, 318, 16 },
    {Sparc_ORCCrr, 334, 1 },
    {Sparc_ORri, 335, 1 },
    {Sparc_ORrr, 336, 1 },
    {Sparc_RESTORErr, 337, 1 },
    {Sparc_RET, 338, 1 },
    {Sparc_RETL, 339, 1 },
    {Sparc_SAVErr, 340, 1 },
    {Sparc_SUBCCri, 341, 1 },
    {Sparc_SUBCCrr, 342, 1 },
    {Sparc_TICCri, 343, 32 },
    {Sparc_TICCrr, 375, 32 },
    {Sparc_TRAPri, 407, 32 },
    {Sparc_TRAPrr, 439, 32 },
    {Sparc_TXCCri, 471, 32 },
    {Sparc_TXCCrr, 503, 32 },
    {Sparc_V9FCMPD, 535, 1 },
    {Sparc_V9FCMPED, 536, 1 },
    {Sparc_V9FCMPEQ, 537, 1 },
    {Sparc_V9FCMPES, 538, 1 },
    {Sparc_V9FCMPQ, 539, 1 },
    {Sparc_V9FCMPS, 540, 1 },
    {Sparc_V9FMOVD_FCC, 541, 16 },
    {Sparc_V9FMOVQ_FCC, 557, 16 },
    {Sparc_V9FMOVS_FCC, 573, 16 },
    {Sparc_V9MOVFCCri, 589, 16 },
    {Sparc_V9MOVFCCrr, 605, 16 },
  {0},  };

  static const AliasPattern Patterns[] = {
    // Sparc_BCOND - 0
    {0, 0, 2, 2 },
    {6, 2, 2, 2 },
    {12, 4, 2, 2 },
    {19, 6, 2, 2 },
    {25, 8, 2, 2 },
    {31, 10, 2, 2 },
    {38, 12, 2, 2 },
    {45, 14, 2, 2 },
    {51, 16, 2, 2 },
    {58, 18, 2, 2 },
    {66, 20, 2, 2 },
    {73, 22, 2, 2 },
    {80, 24, 2, 2 },
    {88, 26, 2, 2 },
    {96, 28, 2, 2 },
    {103, 30, 2, 2 },
    // Sparc_BCONDA - 16
    {110, 32, 2, 2 },
    {118, 34, 2, 2 },
    {126, 36, 2, 2 },
    {135, 38, 2, 2 },
    {143, 40, 2, 2 },
    {151, 42, 2, 2 },
    {160, 44, 2, 2 },
    {169, 46, 2, 2 },
    {177, 48, 2, 2 },
    {186, 50, 2, 2 },
    {196, 52, 2, 2 },
    {205, 54, 2, 2 },
    {214, 56, 2, 2 },
    {224, 58, 2, 2 },
    {234, 60, 2, 2 },
    {243, 62, 2, 2 },
    // Sparc_BPFCCANT - 32
    {252, 64, 3, 4 },
    {268, 68, 3, 4 },
    {284, 72, 3, 4 },
    {300, 76, 3, 4 },
    {316, 80, 3, 4 },
    {333, 84, 3, 4 },
    {349, 88, 3, 4 },
    {366, 92, 3, 4 },
    {383, 96, 3, 4 },
    {400, 100, 3, 4 },
    {416, 104, 3, 4 },
    {433, 108, 3, 4 },
    {450, 112, 3, 4 },
    {468, 116, 3, 4 },
    {485, 120, 3, 4 },
    {503, 124, 3, 4 },
    // Sparc_BPFCCNT - 48
    {519, 128, 3, 4 },
    {533, 132, 3, 4 },
    {547, 136, 3, 4 },
    {561, 140, 3, 4 },
    {575, 144, 3, 4 },
    {590, 148, 3, 4 },
    {604, 152, 3, 4 },
    {619, 156, 3, 4 },
    {634, 160, 3, 4 },
    {649, 164, 3, 4 },
    {663, 168, 3, 4 },
    {678, 172, 3, 4 },
    {693, 176, 3, 4 },
    {709, 180, 3, 4 },
    {724, 184, 3, 4 },
    {740, 188, 3, 4 },
    // Sparc_BPICCANT - 64
    {754, 192, 2, 3 },
    {771, 195, 2, 3 },
    {788, 198, 2, 3 },
    {806, 201, 2, 3 },
    {823, 204, 2, 3 },
    {840, 207, 2, 3 },
    {858, 210, 2, 3 },
    {876, 213, 2, 3 },
    {893, 216, 2, 3 },
    {911, 219, 2, 3 },
    {930, 222, 2, 3 },
    {948, 225, 2, 3 },
    {966, 228, 2, 3 },
    {985, 231, 2, 3 },
    {1004, 234, 2, 3 },
    {1022, 237, 2, 3 },
    // Sparc_BPICCNT - 80
    {1040, 240, 2, 3 },
    {1055, 243, 2, 3 },
    {1070, 246, 2, 3 },
    {1086, 249, 2, 3 },
    {1101, 252, 2, 3 },
    {1116, 255, 2, 3 },
    {1132, 258, 2, 3 },
    {1148, 261, 2, 3 },
    {1163, 264, 2, 3 },
    {1179, 267, 2, 3 },
    {1196, 270, 2, 3 },
    {1212, 273, 2, 3 },
    {1228, 276, 2, 3 },
    {1245, 279, 2, 3 },
    {1262, 282, 2, 3 },
    {1278, 285, 2, 3 },
    // Sparc_BPRANT - 96
    {1294, 288, 3, 4 },
    {1310, 292, 3, 4 },
    {1328, 296, 3, 4 },
    {1345, 300, 3, 4 },
    {1362, 304, 3, 4 },
    {1379, 308, 3, 4 },
    // Sparc_BPRNT - 102
    {1397, 312, 3, 4 },
    {1411, 316, 3, 4 },
    {1427, 320, 3, 4 },
    {1442, 324, 3, 4 },
    {1457, 328, 3, 4 },
    {1472, 332, 3, 4 },
    // Sparc_BPXCCANT - 108
    {1488, 336, 2, 3 },
    {1505, 339, 2, 3 },
    {1522, 342, 2, 3 },
    {1540, 345, 2, 3 },
    {1557, 348, 2, 3 },
    {1574, 351, 2, 3 },
    {1592, 354, 2, 3 },
    {1610, 357, 2, 3 },
    {1627, 360, 2, 3 },
    {1645, 363, 2, 3 },
    {1664, 366, 2, 3 },
    {1682, 369, 2, 3 },
    {1700, 372, 2, 3 },
    {1719, 375, 2, 3 },
    {1738, 378, 2, 3 },
    {1756, 381, 2, 3 },
    // Sparc_BPXCCNT - 124
    {1774, 384, 2, 3 },
    {1789, 387, 2, 3 },
    {1804, 390, 2, 3 },
    {1820, 393, 2, 3 },
    {1835, 396, 2, 3 },
    {1850, 399, 2, 3 },
    {1866, 402, 2, 3 },
    {1882, 405, 2, 3 },
    {1897, 408, 2, 3 },
    {1913, 411, 2, 3 },
    {1930, 414, 2, 3 },
    {1946, 417, 2, 3 },
    {1962, 420, 2, 3 },
    {1979, 423, 2, 3 },
    {1996, 426, 2, 3 },
    {2012, 429, 2, 3 },
    // Sparc_CASArr - 140
    {2028, 432, 5, 6 },
    {2045, 438, 5, 6 },
    // Sparc_CASXArr - 142
    {2063, 444, 5, 6 },
    {2081, 450, 5, 6 },
    // Sparc_FMOVD_ICC - 144
    {2100, 456, 4, 5 },
    {2120, 461, 4, 5 },
    {2140, 466, 4, 5 },
    {2161, 471, 4, 5 },
    {2181, 476, 4, 5 },
    {2201, 481, 4, 5 },
    {2222, 486, 4, 5 },
    {2243, 491, 4, 5 },
    {2263, 496, 4, 5 },
    {2284, 501, 4, 5 },
    {2306, 506, 4, 5 },
    {2327, 511, 4, 5 },
    {2348, 516, 4, 5 },
    {2370, 521, 4, 5 },
    {2392, 526, 4, 5 },
    {2413, 531, 4, 5 },
    // Sparc_FMOVD_XCC - 160
    {2434, 536, 4, 5 },
    {2454, 541, 4, 5 },
    {2474, 546, 4, 5 },
    {2495, 551, 4, 5 },
    {2515, 556, 4, 5 },
    {2535, 561, 4, 5 },
    {2556, 566, 4, 5 },
    {2577, 571, 4, 5 },
    {2597, 576, 4, 5 },
    {2618, 581, 4, 5 },
    {2640, 586, 4, 5 },
    {2661, 591, 4, 5 },
    {2682, 596, 4, 5 },
    {2704, 601, 4, 5 },
    {2726, 606, 4, 5 },
    {2747, 611, 4, 5 },
    // Sparc_FMOVQ_ICC - 176
    {2768, 616, 4, 5 },
    {2788, 621, 4, 5 },
    {2808, 626, 4, 5 },
    {2829, 631, 4, 5 },
    {2849, 636, 4, 5 },
    {2869, 641, 4, 5 },
    {2890, 646, 4, 5 },
    {2911, 651, 4, 5 },
    {2931, 656, 4, 5 },
    {2952, 661, 4, 5 },
    {2974, 666, 4, 5 },
    {2995, 671, 4, 5 },
    {3016, 676, 4, 5 },
    {3038, 681, 4, 5 },
    {3060, 686, 4, 5 },
    {3081, 691, 4, 5 },
    // Sparc_FMOVQ_XCC - 192
    {3102, 696, 4, 5 },
    {3122, 701, 4, 5 },
    {3142, 706, 4, 5 },
    {3163, 711, 4, 5 },
    {3183, 716, 4, 5 },
    {3203, 721, 4, 5 },
    {3224, 726, 4, 5 },
    {3245, 731, 4, 5 },
    {3265, 736, 4, 5 },
    {3286, 741, 4, 5 },
    {3308, 746, 4, 5 },
    {3329, 751, 4, 5 },
    {3350, 756, 4, 5 },
    {3372, 761, 4, 5 },
    {3394, 766, 4, 5 },
    {3415, 771, 4, 5 },
    // Sparc_FMOVRD - 208
    {3436, 776, 5, 6 },
    {3455, 782, 5, 6 },
    {3476, 788, 5, 6 },
    {3496, 794, 5, 6 },
    {3516, 800, 5, 6 },
    {3536, 806, 5, 6 },
    // Sparc_FMOVRQ - 214
    {3557, 812, 5, 6 },
    {3576, 818, 5, 6 },
    {3597, 824, 5, 6 },
    {3617, 830, 5, 6 },
    {3637, 836, 5, 6 },
    {3657, 842, 5, 6 },
    // Sparc_FMOVRS - 220
    {3678, 848, 5, 6 },
    {3697, 854, 5, 6 },
    {3718, 860, 5, 6 },
    {3738, 866, 5, 6 },
    {3758, 872, 5, 6 },
    {3778, 878, 5, 6 },
    // Sparc_FMOVS_ICC - 226
    {3799, 884, 4, 5 },
    {3819, 889, 4, 5 },
    {3839, 894, 4, 5 },
    {3860, 899, 4, 5 },
    {3880, 904, 4, 5 },
    {3900, 909, 4, 5 },
    {3921, 914, 4, 5 },
    {3942, 919, 4, 5 },
    {3962, 924, 4, 5 },
    {3983, 929, 4, 5 },
    {4005, 934, 4, 5 },
    {4026, 939, 4, 5 },
    {4047, 944, 4, 5 },
    {4069, 949, 4, 5 },
    {4091, 954, 4, 5 },
    {4112, 959, 4, 5 },
    // Sparc_FMOVS_XCC - 242
    {4133, 964, 4, 5 },
    {4153, 969, 4, 5 },
    {4173, 974, 4, 5 },
    {4194, 979, 4, 5 },
    {4214, 984, 4, 5 },
    {4234, 989, 4, 5 },
    {4255, 994, 4, 5 },
    {4276, 999, 4, 5 },
    {4296, 1004, 4, 5 },
    {4317, 1009, 4, 5 },
    {4339, 1014, 4, 5 },
    {4360, 1019, 4, 5 },
    {4381, 1024, 4, 5 },
    {4403, 1029, 4, 5 },
    {4425, 1034, 4, 5 },
    {4446, 1039, 4, 5 },
    // Sparc_MOVICCri - 258
    {4467, 1044, 4, 5 },
    {4485, 1049, 4, 5 },
    {4503, 1054, 4, 5 },
    {4522, 1059, 4, 5 },
    {4540, 1064, 4, 5 },
    {4558, 1069, 4, 5 },
    {4577, 1074, 4, 5 },
    {4596, 1079, 4, 5 },
    {4614, 1084, 4, 5 },
    {4633, 1089, 4, 5 },
    {4653, 1094, 4, 5 },
    {4672, 1099, 4, 5 },
    {4691, 1104, 4, 5 },
    {4711, 1109, 4, 5 },
    {4731, 1114, 4, 5 },
    {4750, 1119, 4, 5 },
    // Sparc_MOVICCrr - 274
    {4467, 1124, 4, 5 },
    {4485, 1129, 4, 5 },
    {4503, 1134, 4, 5 },
    {4522, 1139, 4, 5 },
    {4540, 1144, 4, 5 },
    {4558, 1149, 4, 5 },
    {4577, 1154, 4, 5 },
    {4596, 1159, 4, 5 },
    {4614, 1164, 4, 5 },
    {4633, 1169, 4, 5 },
    {4653, 1174, 4, 5 },
    {4672, 1179, 4, 5 },
    {4691, 1184, 4, 5 },
    {4711, 1189, 4, 5 },
    {4731, 1194, 4, 5 },
    {4750, 1199, 4, 5 },
    // Sparc_MOVRri - 290
    {4769, 1204, 5, 6 },
    {4786, 1210, 5, 6 },
    {4805, 1216, 5, 6 },
    {4823, 1222, 5, 6 },
    {4841, 1228, 5, 6 },
    {4859, 1234, 5, 6 },
    // Sparc_MOVRrr - 296
    {4769, 1240, 5, 6 },
    {4786, 1246, 5, 6 },
    {4805, 1252, 5, 6 },
    {4823, 1258, 5, 6 },
    {4841, 1264, 5, 6 },
    {4859, 1270, 5, 6 },
    // Sparc_MOVXCCri - 302
    {4878, 1276, 4, 5 },
    {4896, 1281, 4, 5 },
    {4914, 1286, 4, 5 },
    {4933, 1291, 4, 5 },
    {4951, 1296, 4, 5 },
    {4969, 1301, 4, 5 },
    {4988, 1306, 4, 5 },
    {5007, 1311, 4, 5 },
    {5025, 1316, 4, 5 },
    {5044, 1321, 4, 5 },
    {5064, 1326, 4, 5 },
    {5083, 1331, 4, 5 },
    {5102, 1336, 4, 5 },
    {5122, 1341, 4, 5 },
    {5142, 1346, 4, 5 },
    {5161, 1351, 4, 5 },
    // Sparc_MOVXCCrr - 318
    {4878, 1356, 4, 5 },
    {4896, 1361, 4, 5 },
    {4914, 1366, 4, 5 },
    {4933, 1371, 4, 5 },
    {4951, 1376, 4, 5 },
    {4969, 1381, 4, 5 },
    {4988, 1386, 4, 5 },
    {5007, 1391, 4, 5 },
    {5025, 1396, 4, 5 },
    {5044, 1401, 4, 5 },
    {5064, 1406, 4, 5 },
    {5083, 1411, 4, 5 },
    {5102, 1416, 4, 5 },
    {5122, 1421, 4, 5 },
    {5142, 1426, 4, 5 },
    {5161, 1431, 4, 5 },
    // Sparc_ORCCrr - 334
    {5180, 1436, 3, 3 },
    // Sparc_ORri - 335
    {5187, 1439, 3, 2 },
    // Sparc_ORrr - 336
    {5187, 1441, 3, 3 },
    // Sparc_RESTORErr - 337
    {5198, 1444, 3, 3 },
    // Sparc_RET - 338
    {5206, 1447, 1, 1 },
    // Sparc_RETL - 339
    {5210, 1448, 1, 1 },
    // Sparc_SAVErr - 340
    {5215, 1449, 3, 3 },
    // Sparc_SUBCCri - 341
    {5220, 1452, 3, 2 },
    // Sparc_SUBCCrr - 342
    {5220, 1454, 3, 3 },
    // Sparc_TICCri - 343
    {5231, 1457, 3, 4 },
    {5243, 1461, 3, 4 },
    {5260, 1465, 3, 4 },
    {5272, 1469, 3, 4 },
    {5289, 1473, 3, 4 },
    {5302, 1477, 3, 4 },
    {5320, 1481, 3, 4 },
    {5332, 1485, 3, 4 },
    {5349, 1489, 3, 4 },
    {5361, 1493, 3, 4 },
    {5378, 1497, 3, 4 },
    {5391, 1501, 3, 4 },
    {5409, 1505, 3, 4 },
    {5422, 1509, 3, 4 },
    {5440, 1513, 3, 4 },
    {5452, 1517, 3, 4 },
    {5469, 1521, 3, 4 },
    {5482, 1525, 3, 4 },
    {5500, 1529, 3, 4 },
    {5514, 1533, 3, 4 },
    {5533, 1537, 3, 4 },
    {5546, 1541, 3, 4 },
    {5564, 1545, 3, 4 },
    {5577, 1549, 3, 4 },
    {5595, 1553, 3, 4 },
    {5609, 1557, 3, 4 },
    {5628, 1561, 3, 4 },
    {5642, 1565, 3, 4 },
    {5661, 1569, 3, 4 },
    {5674, 1573, 3, 4 },
    {5692, 1577, 3, 4 },
    {5705, 1581, 3, 4 },
    // Sparc_TICCrr - 375
    {5231, 1585, 3, 4 },
    {5243, 1589, 3, 4 },
    {5260, 1593, 3, 4 },
    {5272, 1597, 3, 4 },
    {5289, 1601, 3, 4 },
    {5302, 1605, 3, 4 },
    {5320, 1609, 3, 4 },
    {5332, 1613, 3, 4 },
    {5349, 1617, 3, 4 },
    {5361, 1621, 3, 4 },
    {5378, 1625, 3, 4 },
    {5391, 1629, 3, 4 },
    {5409, 1633, 3, 4 },
    {5422, 1637, 3, 4 },
    {5440, 1641, 3, 4 },
    {5452, 1645, 3, 4 },
    {5469, 1649, 3, 4 },
    {5482, 1653, 3, 4 },
    {5500, 1657, 3, 4 },
    {5514, 1661, 3, 4 },
    {5533, 1665, 3, 4 },
    {5546, 1669, 3, 4 },
    {5564, 1673, 3, 4 },
    {5577, 1677, 3, 4 },
    {5595, 1681, 3, 4 },
    {5609, 1685, 3, 4 },
    {5628, 1689, 3, 4 },
    {5642, 1693, 3, 4 },
    {5661, 1697, 3, 4 },
    {5674, 1701, 3, 4 },
    {5692, 1705, 3, 4 },
    {5705, 1709, 3, 4 },
    // Sparc_TRAPri - 407
    {5723, 1713, 3, 3 },
    {5729, 1716, 3, 3 },
    {5740, 1719, 3, 3 },
    {5746, 1722, 3, 3 },
    {5757, 1725, 3, 3 },
    {5764, 1728, 3, 3 },
    {5776, 1731, 3, 3 },
    {5782, 1734, 3, 3 },
    {5793, 1737, 3, 3 },
    {5799, 1740, 3, 3 },
    {5810, 1743, 3, 3 },
    {5817, 1746, 3, 3 },
    {5829, 1749, 3, 3 },
    {5836, 1752, 3, 3 },
    {5848, 1755, 3, 3 },
    {5854, 1758, 3, 3 },
    {5865, 1761, 3, 3 },
    {5872, 1764, 3, 3 },
    {5884, 1767, 3, 3 },
    {5892, 1770, 3, 3 },
    {5905, 1773, 3, 3 },
    {5912, 1776, 3, 3 },
    {5924, 1779, 3, 3 },
    {5931, 1782, 3, 3 },
    {5943, 1785, 3, 3 },
    {5951, 1788, 3, 3 },
    {5964, 1791, 3, 3 },
    {5972, 1794, 3, 3 },
    {5985, 1797, 3, 3 },
    {5992, 1800, 3, 3 },
    {6004, 1803, 3, 3 },
    {6011, 1806, 3, 3 },
    // Sparc_TRAPrr - 439
    {5723, 1809, 3, 3 },
    {5729, 1812, 3, 3 },
    {5740, 1815, 3, 3 },
    {5746, 1818, 3, 3 },
    {5757, 1821, 3, 3 },
    {5764, 1824, 3, 3 },
    {5776, 1827, 3, 3 },
    {5782, 1830, 3, 3 },
    {5793, 1833, 3, 3 },
    {5799, 1836, 3, 3 },
    {5810, 1839, 3, 3 },
    {5817, 1842, 3, 3 },
    {5829, 1845, 3, 3 },
    {5836, 1848, 3, 3 },
    {5848, 1851, 3, 3 },
    {5854, 1854, 3, 3 },
    {5865, 1857, 3, 3 },
    {5872, 1860, 3, 3 },
    {5884, 1863, 3, 3 },
    {5892, 1866, 3, 3 },
    {5905, 1869, 3, 3 },
    {5912, 1872, 3, 3 },
    {5924, 1875, 3, 3 },
    {5931, 1878, 3, 3 },
    {5943, 1881, 3, 3 },
    {5951, 1884, 3, 3 },
    {5964, 1887, 3, 3 },
    {5972, 1890, 3, 3 },
    {5985, 1893, 3, 3 },
    {5992, 1896, 3, 3 },
    {6004, 1899, 3, 3 },
    {6011, 1902, 3, 3 },
    // Sparc_TXCCri - 471
    {6023, 1905, 3, 4 },
    {6035, 1909, 3, 4 },
    {6052, 1913, 3, 4 },
    {6064, 1917, 3, 4 },
    {6081, 1921, 3, 4 },
    {6094, 1925, 3, 4 },
    {6112, 1929, 3, 4 },
    {6124, 1933, 3, 4 },
    {6141, 1937, 3, 4 },
    {6153, 1941, 3, 4 },
    {6170, 1945, 3, 4 },
    {6183, 1949, 3, 4 },
    {6201, 1953, 3, 4 },
    {6214, 1957, 3, 4 },
    {6232, 1961, 3, 4 },
    {6244, 1965, 3, 4 },
    {6261, 1969, 3, 4 },
    {6274, 1973, 3, 4 },
    {6292, 1977, 3, 4 },
    {6306, 1981, 3, 4 },
    {6325, 1985, 3, 4 },
    {6338, 1989, 3, 4 },
    {6356, 1993, 3, 4 },
    {6369, 1997, 3, 4 },
    {6387, 2001, 3, 4 },
    {6401, 2005, 3, 4 },
    {6420, 2009, 3, 4 },
    {6434, 2013, 3, 4 },
    {6453, 2017, 3, 4 },
    {6466, 2021, 3, 4 },
    {6484, 2025, 3, 4 },
    {6497, 2029, 3, 4 },
    // Sparc_TXCCrr - 503
    {6023, 2033, 3, 4 },
    {6035, 2037, 3, 4 },
    {6052, 2041, 3, 4 },
    {6064, 2045, 3, 4 },
    {6081, 2049, 3, 4 },
    {6094, 2053, 3, 4 },
    {6112, 2057, 3, 4 },
    {6124, 2061, 3, 4 },
    {6141, 2065, 3, 4 },
    {6153, 2069, 3, 4 },
    {6170, 2073, 3, 4 },
    {6183, 2077, 3, 4 },
    {6201, 2081, 3, 4 },
    {6214, 2085, 3, 4 },
    {6232, 2089, 3, 4 },
    {6244, 2093, 3, 4 },
    {6261, 2097, 3, 4 },
    {6274, 2101, 3, 4 },
    {6292, 2105, 3, 4 },
    {6306, 2109, 3, 4 },
    {6325, 2113, 3, 4 },
    {6338, 2117, 3, 4 },
    {6356, 2121, 3, 4 },
    {6369, 2125, 3, 4 },
    {6387, 2129, 3, 4 },
    {6401, 2133, 3, 4 },
    {6420, 2137, 3, 4 },
    {6434, 2141, 3, 4 },
    {6453, 2145, 3, 4 },
    {6466, 2149, 3, 4 },
    {6484, 2153, 3, 4 },
    {6497, 2157, 3, 4 },
    // Sparc_V9FCMPD - 535
    {6515, 2161, 3, 3 },
    // Sparc_V9FCMPED - 536
    {6528, 2164, 3, 3 },
    // Sparc_V9FCMPEQ - 537
    {6542, 2167, 3, 3 },
    // Sparc_V9FCMPES - 538
    {6556, 2170, 3, 3 },
    // Sparc_V9FCMPQ - 539
    {6570, 2173, 3, 3 },
    // Sparc_V9FCMPS - 540
    {6583, 2176, 3, 3 },
    // Sparc_V9FMOVD_FCC - 541
    {6596, 2179, 5, 6 },
    {6614, 2185, 5, 6 },
    {6632, 2191, 5, 6 },
    {6650, 2197, 5, 6 },
    {6668, 2203, 5, 6 },
    {6687, 2209, 5, 6 },
    {6705, 2215, 5, 6 },
    {6724, 2221, 5, 6 },
    {6743, 2227, 5, 6 },
    {6762, 2233, 5, 6 },
    {6780, 2239, 5, 6 },
    {6799, 2245, 5, 6 },
    {6818, 2251, 5, 6 },
    {6838, 2257, 5, 6 },
    {6857, 2263, 5, 6 },
    {6877, 2269, 5, 6 },
    // Sparc_V9FMOVQ_FCC - 557
    {6895, 2275, 5, 6 },
    {6913, 2281, 5, 6 },
    {6931, 2287, 5, 6 },
    {6949, 2293, 5, 6 },
    {6967, 2299, 5, 6 },
    {6986, 2305, 5, 6 },
    {7004, 2311, 5, 6 },
    {7023, 2317, 5, 6 },
    {7042, 2323, 5, 6 },
    {7061, 2329, 5, 6 },
    {7079, 2335, 5, 6 },
    {7098, 2341, 5, 6 },
    {7117, 2347, 5, 6 },
    {7137, 2353, 5, 6 },
    {7156, 2359, 5, 6 },
    {7176, 2365, 5, 6 },
    // Sparc_V9FMOVS_FCC - 573
    {7194, 2371, 5, 6 },
    {7212, 2377, 5, 6 },
    {7230, 2383, 5, 6 },
    {7248, 2389, 5, 6 },
    {7266, 2395, 5, 6 },
    {7285, 2401, 5, 6 },
    {7303, 2407, 5, 6 },
    {7322, 2413, 5, 6 },
    {7341, 2419, 5, 6 },
    {7360, 2425, 5, 6 },
    {7378, 2431, 5, 6 },
    {7397, 2437, 5, 6 },
    {7416, 2443, 5, 6 },
    {7436, 2449, 5, 6 },
    {7455, 2455, 5, 6 },
    {7475, 2461, 5, 6 },
    // Sparc_V9MOVFCCri - 589
    {7493, 2467, 5, 6 },
    {7509, 2473, 5, 6 },
    {7525, 2479, 5, 6 },
    {7541, 2485, 5, 6 },
    {7557, 2491, 5, 6 },
    {7574, 2497, 5, 6 },
    {7590, 2503, 5, 6 },
    {7607, 2509, 5, 6 },
    {7624, 2515, 5, 6 },
    {7641, 2521, 5, 6 },
    {7657, 2527, 5, 6 },
    {7674, 2533, 5, 6 },
    {7691, 2539, 5, 6 },
    {7709, 2545, 5, 6 },
    {7726, 2551, 5, 6 },
    {7744, 2557, 5, 6 },
    // Sparc_V9MOVFCCrr - 605
    {7493, 2563, 5, 6 },
    {7509, 2569, 5, 6 },
    {7525, 2575, 5, 6 },
    {7541, 2581, 5, 6 },
    {7557, 2587, 5, 6 },
    {7574, 2593, 5, 6 },
    {7590, 2599, 5, 6 },
    {7607, 2605, 5, 6 },
    {7624, 2611, 5, 6 },
    {7641, 2617, 5, 6 },
    {7657, 2623, 5, 6 },
    {7674, 2629, 5, 6 },
    {7691, 2635, 5, 6 },
    {7709, 2641, 5, 6 },
    {7726, 2647, 5, 6 },
    {7744, 2653, 5, 6 },
  {0},  };

  static const AliasPatternCond Conds[] = {
    // (BCOND brtarget:$imm, 8) - 0
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    // (BCOND brtarget:$imm, 0) - 2
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    // (BCOND brtarget:$imm, 9) - 4
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    // (BCOND brtarget:$imm, 1) - 6
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    // (BCOND brtarget:$imm, 10) - 8
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    // (BCOND brtarget:$imm, 2) - 10
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    // (BCOND brtarget:$imm, 11) - 12
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    // (BCOND brtarget:$imm, 3) - 14
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    // (BCOND brtarget:$imm, 12) - 16
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    // (BCOND brtarget:$imm, 4) - 18
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    // (BCOND brtarget:$imm, 13) - 20
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    // (BCOND brtarget:$imm, 5) - 22
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    // (BCOND brtarget:$imm, 14) - 24
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    // (BCOND brtarget:$imm, 6) - 26
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    // (BCOND brtarget:$imm, 15) - 28
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    // (BCOND brtarget:$imm, 7) - 30
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    // (BCONDA brtarget:$imm, 8) - 32
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    // (BCONDA brtarget:$imm, 0) - 34
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    // (BCONDA brtarget:$imm, 9) - 36
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    // (BCONDA brtarget:$imm, 1) - 38
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    // (BCONDA brtarget:$imm, 10) - 40
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    // (BCONDA brtarget:$imm, 2) - 42
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    // (BCONDA brtarget:$imm, 11) - 44
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    // (BCONDA brtarget:$imm, 3) - 46
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    // (BCONDA brtarget:$imm, 12) - 48
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    // (BCONDA brtarget:$imm, 4) - 50
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    // (BCONDA brtarget:$imm, 13) - 52
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    // (BCONDA brtarget:$imm, 5) - 54
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    // (BCONDA brtarget:$imm, 14) - 56
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    // (BCONDA brtarget:$imm, 6) - 58
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    // (BCONDA brtarget:$imm, 15) - 60
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    // (BCONDA brtarget:$imm, 7) - 62
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) - 64
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) - 68
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) - 72
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) - 76
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) - 80
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) - 84
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) - 88
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) - 92
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) - 96
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) - 100
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) - 104
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) - 108
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) - 112
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) - 116
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) - 120
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) - 124
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) - 128
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) - 132
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) - 136
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) - 140
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) - 144
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) - 148
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) - 152
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) - 156
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) - 160
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) - 164
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) - 168
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) - 172
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) - 176
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) - 180
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) - 184
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) - 188
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 8) - 192
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 0) - 195
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 9) - 198
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 1) - 201
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 10) - 204
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 2) - 207
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 11) - 210
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 3) - 213
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 12) - 216
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 4) - 219
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 13) - 222
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 5) - 225
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 14) - 228
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 6) - 231
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 15) - 234
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCANT brtarget:$imm, 7) - 237
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 8) - 240
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 0) - 243
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 9) - 246
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 1) - 249
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 10) - 252
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 2) - 255
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 11) - 258
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 3) - 261
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 12) - 264
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 4) - 267
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 13) - 270
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 5) - 273
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 14) - 276
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 6) - 279
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 15) - 282
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPICCNT brtarget:$imm, 7) - 285
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPRANT bprtarget16:$imm, 1, I64Regs:$rs1) - 288
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPRANT bprtarget16:$imm, 2, I64Regs:$rs1) - 292
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPRANT bprtarget16:$imm, 3, I64Regs:$rs1) - 296
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPRANT bprtarget16:$imm, 5, I64Regs:$rs1) - 300
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPRANT bprtarget16:$imm, 6, I64Regs:$rs1) - 304
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPRANT bprtarget16:$imm, 7, I64Regs:$rs1) - 308
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPRNT bprtarget16:$imm, 1, I64Regs:$rs1) - 312
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPRNT bprtarget16:$imm, 2, I64Regs:$rs1) - 316
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPRNT bprtarget16:$imm, 3, I64Regs:$rs1) - 320
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPRNT bprtarget16:$imm, 5, I64Regs:$rs1) - 324
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPRNT bprtarget16:$imm, 6, I64Regs:$rs1) - 328
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPRNT bprtarget16:$imm, 7, I64Regs:$rs1) - 332
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 8) - 336
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 0) - 339
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 9) - 342
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 1) - 345
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 10) - 348
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 2) - 351
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 11) - 354
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 3) - 357
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 12) - 360
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 4) - 363
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 13) - 366
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 5) - 369
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 14) - 372
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 6) - 375
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 15) - 378
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCANT brtarget:$imm, 7) - 381
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 8) - 384
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 0) - 387
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 9) - 390
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 1) - 393
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 10) - 396
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 2) - 399
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 11) - 402
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 3) - 405
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 12) - 408
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 4) - 411
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 13) - 414
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 5) - 417
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 14) - 420
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 6) - 423
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 15) - 426
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (BPXCCNT brtarget:$imm, 7) - 429
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 128) - 432
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)128},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 136) - 438
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)136},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 128) - 444
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)128},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 136) - 450
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)136},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 456
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 461
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 466
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 471
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 476
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 481
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 486
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 491
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 496
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 501
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 506
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 511
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 516
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 521
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 526
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 531
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8) - 536
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0) - 541
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9) - 546
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1) - 551
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10) - 556
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2) - 561
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11) - 566
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3) - 571
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12) - 576
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4) - 581
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13) - 586
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5) - 591
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14) - 596
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6) - 601
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15) - 606
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7) - 611
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 616
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 621
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 626
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 631
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 636
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 641
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 646
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 651
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 656
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 661
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 666
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 671
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 676
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 681
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 686
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 691
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8) - 696
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0) - 701
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9) - 706
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1) - 711
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10) - 716
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2) - 721
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11) - 726
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3) - 731
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12) - 736
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4) - 741
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13) - 746
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5) - 751
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14) - 756
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6) - 761
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15) - 766
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7) - 771
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 1) - 776
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 2) - 782
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 3) - 788
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 5) - 794
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 6) - 800
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 7) - 806
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 1) - 812
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 2) - 818
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 3) - 824
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 5) - 830
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 6) - 836
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 7) - 842
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 1) - 848
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 2) - 854
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 3) - 860
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 5) - 866
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 6) - 872
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 7) - 878
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 884
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 889
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 894
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 899
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 904
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 909
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 914
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 919
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 924
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 929
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 934
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 939
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 944
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 949
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 954
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 959
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8) - 964
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0) - 969
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9) - 974
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1) - 979
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10) - 984
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2) - 989
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11) - 994
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3) - 999
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12) - 1004
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4) - 1009
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13) - 1014
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5) - 1019
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14) - 1024
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6) - 1029
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15) - 1034
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7) - 1039
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 1044
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 1049
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 1054
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 1059
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 1064
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 1069
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 1074
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 1079
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 1084
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 1089
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 1094
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 1099
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 1104
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 1109
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1114
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1119
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1124
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1129
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1134
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1139
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1144
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1149
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1154
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1159
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1164
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1169
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1174
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1179
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1184
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1189
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1194
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1199
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 1) - 1204
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 2) - 1210
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 3) - 1216
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 5) - 1222
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 6) - 1228
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 7) - 1234
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 1) - 1240
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 2) - 1246
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 3) - 1252
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 5) - 1258
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 6) - 1264
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 7) - 1270
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8) - 1276
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0) - 1281
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9) - 1286
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1) - 1291
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10) - 1296
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2) - 1301
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11) - 1306
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3) - 1311
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12) - 1316
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4) - 1321
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13) - 1326
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5) - 1331
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14) - 1336
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6) - 1341
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15) - 1346
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7) - 1351
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1356
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1361
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1366
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1371
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1376
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1381
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1386
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1391
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1396
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1401
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1406
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1411
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1416
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1421
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1426
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1431
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (ORCCrr G0, IntRegs:$rs2, G0) - 1436
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Reg, Sparc_G0},
    // (ORri IntRegs:$rd, G0, simm13Op:$simm13) - 1439
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Reg, Sparc_G0},
    // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) - 1441
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    // (RESTORErr G0, G0, G0) - 1444
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Reg, Sparc_G0},
    // (RET 8) - 1447
    {AliasPatternCond_K_Imm, (uint32_t)8},
    // (RETL 8) - 1448
    {AliasPatternCond_K_Imm, (uint32_t)8},
    // (SAVErr G0, G0, G0) - 1449
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Reg, Sparc_G0},
    // (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm) - 1452
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    // (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2) - 1454
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    // (TICCri G0, i32imm:$imm, 8) - 1457
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1461
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri G0, i32imm:$imm, 0) - 1465
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1469
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri G0, i32imm:$imm, 9) - 1473
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1477
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri G0, i32imm:$imm, 1) - 1481
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1485
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri G0, i32imm:$imm, 10) - 1489
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1493
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri G0, i32imm:$imm, 2) - 1497
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1501
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri G0, i32imm:$imm, 11) - 1505
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1509
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri G0, i32imm:$imm, 3) - 1513
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1517
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri G0, i32imm:$imm, 12) - 1521
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1525
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri G0, i32imm:$imm, 4) - 1529
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1533
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri G0, i32imm:$imm, 13) - 1537
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1541
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri G0, i32imm:$imm, 5) - 1545
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1549
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri G0, i32imm:$imm, 14) - 1553
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1557
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri G0, i32imm:$imm, 6) - 1561
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1565
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri G0, i32imm:$imm, 15) - 1569
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 1573
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri G0, i32imm:$imm, 7) - 1577
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 1581
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 8) - 1585
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1589
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 0) - 1593
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1597
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 9) - 1601
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1605
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 1) - 1609
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1613
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 10) - 1617
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1621
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 2) - 1625
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1629
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 11) - 1633
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1637
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 3) - 1641
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1645
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 12) - 1649
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1653
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 4) - 1657
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1661
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 13) - 1665
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1669
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 5) - 1673
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1677
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 14) - 1681
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1685
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 6) - 1689
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1693
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 15) - 1697
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1701
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 7) - 1705
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1709
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TRAPri G0, i32imm:$imm, 8) - 1713
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 8) - 1716
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    // (TRAPri G0, i32imm:$imm, 0) - 1719
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 0) - 1722
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    // (TRAPri G0, i32imm:$imm, 9) - 1725
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 9) - 1728
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    // (TRAPri G0, i32imm:$imm, 1) - 1731
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 1) - 1734
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    // (TRAPri G0, i32imm:$imm, 10) - 1737
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 10) - 1740
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    // (TRAPri G0, i32imm:$imm, 2) - 1743
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 2) - 1746
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    // (TRAPri G0, i32imm:$imm, 11) - 1749
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 11) - 1752
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    // (TRAPri G0, i32imm:$imm, 3) - 1755
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 3) - 1758
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    // (TRAPri G0, i32imm:$imm, 12) - 1761
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 12) - 1764
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    // (TRAPri G0, i32imm:$imm, 4) - 1767
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 4) - 1770
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    // (TRAPri G0, i32imm:$imm, 13) - 1773
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 13) - 1776
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    // (TRAPri G0, i32imm:$imm, 5) - 1779
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 5) - 1782
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    // (TRAPri G0, i32imm:$imm, 14) - 1785
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 14) - 1788
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    // (TRAPri G0, i32imm:$imm, 6) - 1791
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 6) - 1794
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    // (TRAPri G0, i32imm:$imm, 15) - 1797
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 15) - 1800
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    // (TRAPri G0, i32imm:$imm, 7) - 1803
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 7) - 1806
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    // (TRAPrr G0, IntRegs:$rs1, 8) - 1809
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1812
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    // (TRAPrr G0, IntRegs:$rs1, 0) - 1815
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1818
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    // (TRAPrr G0, IntRegs:$rs1, 9) - 1821
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1824
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    // (TRAPrr G0, IntRegs:$rs1, 1) - 1827
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1830
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    // (TRAPrr G0, IntRegs:$rs1, 10) - 1833
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1836
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    // (TRAPrr G0, IntRegs:$rs1, 2) - 1839
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1842
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    // (TRAPrr G0, IntRegs:$rs1, 11) - 1845
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1848
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    // (TRAPrr G0, IntRegs:$rs1, 3) - 1851
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1854
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    // (TRAPrr G0, IntRegs:$rs1, 12) - 1857
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1860
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    // (TRAPrr G0, IntRegs:$rs1, 4) - 1863
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1866
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    // (TRAPrr G0, IntRegs:$rs1, 13) - 1869
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1872
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    // (TRAPrr G0, IntRegs:$rs1, 5) - 1875
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1878
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    // (TRAPrr G0, IntRegs:$rs1, 14) - 1881
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1884
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    // (TRAPrr G0, IntRegs:$rs1, 6) - 1887
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1890
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    // (TRAPrr G0, IntRegs:$rs1, 15) - 1893
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1896
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    // (TRAPrr G0, IntRegs:$rs1, 7) - 1899
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1902
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    // (TXCCri G0, i32imm:$imm, 8) - 1905
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 1909
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri G0, i32imm:$imm, 0) - 1913
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 1917
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri G0, i32imm:$imm, 9) - 1921
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 1925
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri G0, i32imm:$imm, 1) - 1929
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 1933
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri G0, i32imm:$imm, 10) - 1937
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 1941
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri G0, i32imm:$imm, 2) - 1945
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 1949
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri G0, i32imm:$imm, 11) - 1953
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 1957
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri G0, i32imm:$imm, 3) - 1961
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 1965
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri G0, i32imm:$imm, 12) - 1969
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 1973
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri G0, i32imm:$imm, 4) - 1977
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 1981
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri G0, i32imm:$imm, 13) - 1985
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 1989
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri G0, i32imm:$imm, 5) - 1993
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 1997
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri G0, i32imm:$imm, 14) - 2001
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 2005
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri G0, i32imm:$imm, 6) - 2009
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 2013
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri G0, i32imm:$imm, 15) - 2017
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 2021
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri G0, i32imm:$imm, 7) - 2025
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 2029
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 8) - 2033
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2037
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 0) - 2041
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2045
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 9) - 2049
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2053
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 1) - 2057
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2061
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 10) - 2065
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2069
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 2) - 2073
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2077
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 11) - 2081
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2085
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 3) - 2089
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2093
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 12) - 2097
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2101
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 4) - 2105
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2109
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 13) - 2113
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2117
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 5) - 2121
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2125
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 14) - 2129
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2133
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 6) - 2137
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2141
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 15) - 2145
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2149
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 7) - 2153
    {AliasPatternCond_K_Reg, Sparc_G0},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2157
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 2161
    {AliasPatternCond_K_Reg, Sparc_FCC0},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 2164
    {AliasPatternCond_K_Reg, Sparc_FCC0},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 2167
    {AliasPatternCond_K_Reg, Sparc_FCC0},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) - 2170
    {AliasPatternCond_K_Reg, Sparc_FCC0},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 2173
    {AliasPatternCond_K_Reg, Sparc_FCC0},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) - 2176
    {AliasPatternCond_K_Reg, Sparc_FCC0},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) - 2179
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) - 2185
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) - 2191
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) - 2197
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) - 2203
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) - 2209
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) - 2215
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) - 2221
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) - 2227
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) - 2233
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) - 2239
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) - 2245
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) - 2251
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) - 2257
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) - 2263
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) - 2269
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) - 2275
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) - 2281
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) - 2287
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) - 2293
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) - 2299
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) - 2305
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) - 2311
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) - 2317
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) - 2323
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) - 2329
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) - 2335
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) - 2341
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) - 2347
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) - 2353
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) - 2359
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) - 2365
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) - 2371
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) - 2377
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) - 2383
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) - 2389
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) - 2395
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) - 2401
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) - 2407
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) - 2413
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) - 2419
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) - 2425
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) - 2431
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) - 2437
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) - 2443
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) - 2449
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) - 2455
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) - 2461
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) - 2467
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) - 2473
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) - 2479
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) - 2485
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) - 2491
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) - 2497
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) - 2503
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) - 2509
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) - 2515
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) - 2521
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) - 2527
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) - 2533
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) - 2539
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) - 2545
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) - 2551
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) - 2557
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) - 2563
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)8},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) - 2569
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)0},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) - 2575
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)7},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) - 2581
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)6},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) - 2587
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)5},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) - 2593
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)4},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) - 2599
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)3},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) - 2605
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)2},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) - 2611
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)1},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) - 2617
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)9},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) - 2623
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)10},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) - 2629
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)11},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) - 2635
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)12},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) - 2641
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)13},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) - 2647
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)14},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) - 2653
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID},
    {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID},
    {AliasPatternCond_K_Ignore, 0},
    {AliasPatternCond_K_Imm, (uint32_t)15},
    {AliasPatternCond_K_Feature, Sparc_FeatureV9},
  {0},  };

  static const char AsmStrings[] =
    /* 0 */ "ba $\x01\0"
    /* 6 */ "bn $\x01\0"
    /* 12 */ "bne $\x01\0"
    /* 19 */ "be $\x01\0"
    /* 25 */ "bg $\x01\0"
    /* 31 */ "ble $\x01\0"
    /* 38 */ "bge $\x01\0"
    /* 45 */ "bl $\x01\0"
    /* 51 */ "bgu $\x01\0"
    /* 58 */ "bleu $\x01\0"
    /* 66 */ "bcc $\x01\0"
    /* 73 */ "bcs $\x01\0"
    /* 80 */ "bpos $\x01\0"
    /* 88 */ "bneg $\x01\0"
    /* 96 */ "bvc $\x01\0"
    /* 103 */ "bvs $\x01\0"
    /* 110 */ "ba,a $\x01\0"
    /* 118 */ "bn,a $\x01\0"
    /* 126 */ "bne,a $\x01\0"
    /* 135 */ "be,a $\x01\0"
    /* 143 */ "bg,a $\x01\0"
    /* 151 */ "ble,a $\x01\0"
    /* 160 */ "bge,a $\x01\0"
    /* 169 */ "bl,a $\x01\0"
    /* 177 */ "bgu,a $\x01\0"
    /* 186 */ "bleu,a $\x01\0"
    /* 196 */ "bcc,a $\x01\0"
    /* 205 */ "bcs,a $\x01\0"
    /* 214 */ "bpos,a $\x01\0"
    /* 224 */ "bneg,a $\x01\0"
    /* 234 */ "bvc,a $\x01\0"
    /* 243 */ "bvs,a $\x01\0"
    /* 252 */ "fba,a,pn $\x03, $\x01\0"
    /* 268 */ "fbn,a,pn $\x03, $\x01\0"
    /* 284 */ "fbu,a,pn $\x03, $\x01\0"
    /* 300 */ "fbg,a,pn $\x03, $\x01\0"
    /* 316 */ "fbug,a,pn $\x03, $\x01\0"
    /* 333 */ "fbl,a,pn $\x03, $\x01\0"
    /* 349 */ "fbul,a,pn $\x03, $\x01\0"
    /* 366 */ "fblg,a,pn $\x03, $\x01\0"
    /* 383 */ "fbne,a,pn $\x03, $\x01\0"
    /* 400 */ "fbe,a,pn $\x03, $\x01\0"
    /* 416 */ "fbue,a,pn $\x03, $\x01\0"
    /* 433 */ "fbge,a,pn $\x03, $\x01\0"
    /* 450 */ "fbuge,a,pn $\x03, $\x01\0"
    /* 468 */ "fble,a,pn $\x03, $\x01\0"
    /* 485 */ "fbule,a,pn $\x03, $\x01\0"
    /* 503 */ "fbo,a,pn $\x03, $\x01\0"
    /* 519 */ "fba,pn $\x03, $\x01\0"
    /* 533 */ "fbn,pn $\x03, $\x01\0"
    /* 547 */ "fbu,pn $\x03, $\x01\0"
    /* 561 */ "fbg,pn $\x03, $\x01\0"
    /* 575 */ "fbug,pn $\x03, $\x01\0"
    /* 590 */ "fbl,pn $\x03, $\x01\0"
    /* 604 */ "fbul,pn $\x03, $\x01\0"
    /* 619 */ "fblg,pn $\x03, $\x01\0"
    /* 634 */ "fbne,pn $\x03, $\x01\0"
    /* 649 */ "fbe,pn $\x03, $\x01\0"
    /* 663 */ "fbue,pn $\x03, $\x01\0"
    /* 678 */ "fbge,pn $\x03, $\x01\0"
    /* 693 */ "fbuge,pn $\x03, $\x01\0"
    /* 709 */ "fble,pn $\x03, $\x01\0"
    /* 724 */ "fbule,pn $\x03, $\x01\0"
    /* 740 */ "fbo,pn $\x03, $\x01\0"
    /* 754 */ "ba,a,pn %icc, $\x01\0"
    /* 771 */ "bn,a,pn %icc, $\x01\0"
    /* 788 */ "bne,a,pn %icc, $\x01\0"
    /* 806 */ "be,a,pn %icc, $\x01\0"
    /* 823 */ "bg,a,pn %icc, $\x01\0"
    /* 840 */ "ble,a,pn %icc, $\x01\0"
    /* 858 */ "bge,a,pn %icc, $\x01\0"
    /* 876 */ "bl,a,pn %icc, $\x01\0"
    /* 893 */ "bgu,a,pn %icc, $\x01\0"
    /* 911 */ "bleu,a,pn %icc, $\x01\0"
    /* 930 */ "bcc,a,pn %icc, $\x01\0"
    /* 948 */ "bcs,a,pn %icc, $\x01\0"
    /* 966 */ "bpos,a,pn %icc, $\x01\0"
    /* 985 */ "bneg,a,pn %icc, $\x01\0"
    /* 1004 */ "bvc,a,pn %icc, $\x01\0"
    /* 1022 */ "bvs,a,pn %icc, $\x01\0"
    /* 1040 */ "ba,pn %icc, $\x01\0"
    /* 1055 */ "bn,pn %icc, $\x01\0"
    /* 1070 */ "bne,pn %icc, $\x01\0"
    /* 1086 */ "be,pn %icc, $\x01\0"
    /* 1101 */ "bg,pn %icc, $\x01\0"
    /* 1116 */ "ble,pn %icc, $\x01\0"
    /* 1132 */ "bge,pn %icc, $\x01\0"
    /* 1148 */ "bl,pn %icc, $\x01\0"
    /* 1163 */ "bgu,pn %icc, $\x01\0"
    /* 1179 */ "bleu,pn %icc, $\x01\0"
    /* 1196 */ "bcc,pn %icc, $\x01\0"
    /* 1212 */ "bcs,pn %icc, $\x01\0"
    /* 1228 */ "bpos,pn %icc, $\x01\0"
    /* 1245 */ "bneg,pn %icc, $\x01\0"
    /* 1262 */ "bvc,pn %icc, $\x01\0"
    /* 1278 */ "bvs,pn %icc, $\x01\0"
    /* 1294 */ "brz,a,pn $\x03, $\x01\0"
    /* 1310 */ "brlez,a,pn $\x03, $\x01\0"
    /* 1328 */ "brlz,a,pn $\x03, $\x01\0"
    /* 1345 */ "brnz,a,pn $\x03, $\x01\0"
    /* 1362 */ "brgz,a,pn $\x03, $\x01\0"
    /* 1379 */ "brgez,a,pn $\x03, $\x01\0"
    /* 1397 */ "brz,pn $\x03, $\x01\0"
    /* 1411 */ "brlez,pn $\x03, $\x01\0"
    /* 1427 */ "brlz,pn $\x03, $\x01\0"
    /* 1442 */ "brnz,pn $\x03, $\x01\0"
    /* 1457 */ "brgz,pn $\x03, $\x01\0"
    /* 1472 */ "brgez,pn $\x03, $\x01\0"
    /* 1488 */ "ba,a,pn %xcc, $\x01\0"
    /* 1505 */ "bn,a,pn %xcc, $\x01\0"
    /* 1522 */ "bne,a,pn %xcc, $\x01\0"
    /* 1540 */ "be,a,pn %xcc, $\x01\0"
    /* 1557 */ "bg,a,pn %xcc, $\x01\0"
    /* 1574 */ "ble,a,pn %xcc, $\x01\0"
    /* 1592 */ "bge,a,pn %xcc, $\x01\0"
    /* 1610 */ "bl,a,pn %xcc, $\x01\0"
    /* 1627 */ "bgu,a,pn %xcc, $\x01\0"
    /* 1645 */ "bleu,a,pn %xcc, $\x01\0"
    /* 1664 */ "bcc,a,pn %xcc, $\x01\0"
    /* 1682 */ "bcs,a,pn %xcc, $\x01\0"
    /* 1700 */ "bpos,a,pn %xcc, $\x01\0"
    /* 1719 */ "bneg,a,pn %xcc, $\x01\0"
    /* 1738 */ "bvc,a,pn %xcc, $\x01\0"
    /* 1756 */ "bvs,a,pn %xcc, $\x01\0"
    /* 1774 */ "ba,pn %xcc, $\x01\0"
    /* 1789 */ "bn,pn %xcc, $\x01\0"
    /* 1804 */ "bne,pn %xcc, $\x01\0"
    /* 1820 */ "be,pn %xcc, $\x01\0"
    /* 1835 */ "bg,pn %xcc, $\x01\0"
    /* 1850 */ "ble,pn %xcc, $\x01\0"
    /* 1866 */ "bge,pn %xcc, $\x01\0"
    /* 1882 */ "bl,pn %xcc, $\x01\0"
    /* 1897 */ "bgu,pn %xcc, $\x01\0"
    /* 1913 */ "bleu,pn %xcc, $\x01\0"
    /* 1930 */ "bcc,pn %xcc, $\x01\0"
    /* 1946 */ "bcs,pn %xcc, $\x01\0"
    /* 1962 */ "bpos,pn %xcc, $\x01\0"
    /* 1979 */ "bneg,pn %xcc, $\x01\0"
    /* 1996 */ "bvc,pn %xcc, $\x01\0"
    /* 2012 */ "bvs,pn %xcc, $\x01\0"
    /* 2028 */ "cas [$\x02], $\x03, $\x01\0"
    /* 2045 */ "casl [$\x02], $\x03, $\x01\0"
    /* 2063 */ "casx [$\x02], $\x03, $\x01\0"
    /* 2081 */ "casxl [$\x02], $\x03, $\x01\0"
    /* 2100 */ "fmovda %icc, $\x02, $\x01\0"
    /* 2120 */ "fmovdn %icc, $\x02, $\x01\0"
    /* 2140 */ "fmovdne %icc, $\x02, $\x01\0"
    /* 2161 */ "fmovde %icc, $\x02, $\x01\0"
    /* 2181 */ "fmovdg %icc, $\x02, $\x01\0"
    /* 2201 */ "fmovdle %icc, $\x02, $\x01\0"
    /* 2222 */ "fmovdge %icc, $\x02, $\x01\0"
    /* 2243 */ "fmovdl %icc, $\x02, $\x01\0"
    /* 2263 */ "fmovdgu %icc, $\x02, $\x01\0"
    /* 2284 */ "fmovdleu %icc, $\x02, $\x01\0"
    /* 2306 */ "fmovdcc %icc, $\x02, $\x01\0"
    /* 2327 */ "fmovdcs %icc, $\x02, $\x01\0"
    /* 2348 */ "fmovdpos %icc, $\x02, $\x01\0"
    /* 2370 */ "fmovdneg %icc, $\x02, $\x01\0"
    /* 2392 */ "fmovdvc %icc, $\x02, $\x01\0"
    /* 2413 */ "fmovdvs %icc, $\x02, $\x01\0"
    /* 2434 */ "fmovda %xcc, $\x02, $\x01\0"
    /* 2454 */ "fmovdn %xcc, $\x02, $\x01\0"
    /* 2474 */ "fmovdne %xcc, $\x02, $\x01\0"
    /* 2495 */ "fmovde %xcc, $\x02, $\x01\0"
    /* 2515 */ "fmovdg %xcc, $\x02, $\x01\0"
    /* 2535 */ "fmovdle %xcc, $\x02, $\x01\0"
    /* 2556 */ "fmovdge %xcc, $\x02, $\x01\0"
    /* 2577 */ "fmovdl %xcc, $\x02, $\x01\0"
    /* 2597 */ "fmovdgu %xcc, $\x02, $\x01\0"
    /* 2618 */ "fmovdleu %xcc, $\x02, $\x01\0"
    /* 2640 */ "fmovdcc %xcc, $\x02, $\x01\0"
    /* 2661 */ "fmovdcs %xcc, $\x02, $\x01\0"
    /* 2682 */ "fmovdpos %xcc, $\x02, $\x01\0"
    /* 2704 */ "fmovdneg %xcc, $\x02, $\x01\0"
    /* 2726 */ "fmovdvc %xcc, $\x02, $\x01\0"
    /* 2747 */ "fmovdvs %xcc, $\x02, $\x01\0"
    /* 2768 */ "fmovqa %icc, $\x02, $\x01\0"
    /* 2788 */ "fmovqn %icc, $\x02, $\x01\0"
    /* 2808 */ "fmovqne %icc, $\x02, $\x01\0"
    /* 2829 */ "fmovqe %icc, $\x02, $\x01\0"
    /* 2849 */ "fmovqg %icc, $\x02, $\x01\0"
    /* 2869 */ "fmovqle %icc, $\x02, $\x01\0"
    /* 2890 */ "fmovqge %icc, $\x02, $\x01\0"
    /* 2911 */ "fmovql %icc, $\x02, $\x01\0"
    /* 2931 */ "fmovqgu %icc, $\x02, $\x01\0"
    /* 2952 */ "fmovqleu %icc, $\x02, $\x01\0"
    /* 2974 */ "fmovqcc %icc, $\x02, $\x01\0"
    /* 2995 */ "fmovqcs %icc, $\x02, $\x01\0"
    /* 3016 */ "fmovqpos %icc, $\x02, $\x01\0"
    /* 3038 */ "fmovqneg %icc, $\x02, $\x01\0"
    /* 3060 */ "fmovqvc %icc, $\x02, $\x01\0"
    /* 3081 */ "fmovqvs %icc, $\x02, $\x01\0"
    /* 3102 */ "fmovqa %xcc, $\x02, $\x01\0"
    /* 3122 */ "fmovqn %xcc, $\x02, $\x01\0"
    /* 3142 */ "fmovqne %xcc, $\x02, $\x01\0"
    /* 3163 */ "fmovqe %xcc, $\x02, $\x01\0"
    /* 3183 */ "fmovqg %xcc, $\x02, $\x01\0"
    /* 3203 */ "fmovqle %xcc, $\x02, $\x01\0"
    /* 3224 */ "fmovqge %xcc, $\x02, $\x01\0"
    /* 3245 */ "fmovql %xcc, $\x02, $\x01\0"
    /* 3265 */ "fmovqgu %xcc, $\x02, $\x01\0"
    /* 3286 */ "fmovqleu %xcc, $\x02, $\x01\0"
    /* 3308 */ "fmovqcc %xcc, $\x02, $\x01\0"
    /* 3329 */ "fmovqcs %xcc, $\x02, $\x01\0"
    /* 3350 */ "fmovqpos %xcc, $\x02, $\x01\0"
    /* 3372 */ "fmovqneg %xcc, $\x02, $\x01\0"
    /* 3394 */ "fmovqvc %xcc, $\x02, $\x01\0"
    /* 3415 */ "fmovqvs %xcc, $\x02, $\x01\0"
    /* 3436 */ "fmovrdz $\x02, $\x03, $\x01\0"
    /* 3455 */ "fmovrdlez $\x02, $\x03, $\x01\0"
    /* 3476 */ "fmovrdlz $\x02, $\x03, $\x01\0"
    /* 3496 */ "fmovrdnz $\x02, $\x03, $\x01\0"
    /* 3516 */ "fmovrdgz $\x02, $\x03, $\x01\0"
    /* 3536 */ "fmovrdgez $\x02, $\x03, $\x01\0"
    /* 3557 */ "fmovrqz $\x02, $\x03, $\x01\0"
    /* 3576 */ "fmovrqlez $\x02, $\x03, $\x01\0"
    /* 3597 */ "fmovrqlz $\x02, $\x03, $\x01\0"
    /* 3617 */ "fmovrqnz $\x02, $\x03, $\x01\0"
    /* 3637 */ "fmovrqgz $\x02, $\x03, $\x01\0"
    /* 3657 */ "fmovrqgez $\x02, $\x03, $\x01\0"
    /* 3678 */ "fmovrsz $\x02, $\x03, $\x01\0"
    /* 3697 */ "fmovrslez $\x02, $\x03, $\x01\0"
    /* 3718 */ "fmovrslz $\x02, $\x03, $\x01\0"
    /* 3738 */ "fmovrsnz $\x02, $\x03, $\x01\0"
    /* 3758 */ "fmovrsgz $\x02, $\x03, $\x01\0"
    /* 3778 */ "fmovrsgez $\x02, $\x03, $\x01\0"
    /* 3799 */ "fmovsa %icc, $\x02, $\x01\0"
    /* 3819 */ "fmovsn %icc, $\x02, $\x01\0"
    /* 3839 */ "fmovsne %icc, $\x02, $\x01\0"
    /* 3860 */ "fmovse %icc, $\x02, $\x01\0"
    /* 3880 */ "fmovsg %icc, $\x02, $\x01\0"
    /* 3900 */ "fmovsle %icc, $\x02, $\x01\0"
    /* 3921 */ "fmovsge %icc, $\x02, $\x01\0"
    /* 3942 */ "fmovsl %icc, $\x02, $\x01\0"
    /* 3962 */ "fmovsgu %icc, $\x02, $\x01\0"
    /* 3983 */ "fmovsleu %icc, $\x02, $\x01\0"
    /* 4005 */ "fmovscc %icc, $\x02, $\x01\0"
    /* 4026 */ "fmovscs %icc, $\x02, $\x01\0"
    /* 4047 */ "fmovspos %icc, $\x02, $\x01\0"
    /* 4069 */ "fmovsneg %icc, $\x02, $\x01\0"
    /* 4091 */ "fmovsvc %icc, $\x02, $\x01\0"
    /* 4112 */ "fmovsvs %icc, $\x02, $\x01\0"
    /* 4133 */ "fmovsa %xcc, $\x02, $\x01\0"
    /* 4153 */ "fmovsn %xcc, $\x02, $\x01\0"
    /* 4173 */ "fmovsne %xcc, $\x02, $\x01\0"
    /* 4194 */ "fmovse %xcc, $\x02, $\x01\0"
    /* 4214 */ "fmovsg %xcc, $\x02, $\x01\0"
    /* 4234 */ "fmovsle %xcc, $\x02, $\x01\0"
    /* 4255 */ "fmovsge %xcc, $\x02, $\x01\0"
    /* 4276 */ "fmovsl %xcc, $\x02, $\x01\0"
    /* 4296 */ "fmovsgu %xcc, $\x02, $\x01\0"
    /* 4317 */ "fmovsleu %xcc, $\x02, $\x01\0"
    /* 4339 */ "fmovscc %xcc, $\x02, $\x01\0"
    /* 4360 */ "fmovscs %xcc, $\x02, $\x01\0"
    /* 4381 */ "fmovspos %xcc, $\x02, $\x01\0"
    /* 4403 */ "fmovsneg %xcc, $\x02, $\x01\0"
    /* 4425 */ "fmovsvc %xcc, $\x02, $\x01\0"
    /* 4446 */ "fmovsvs %xcc, $\x02, $\x01\0"
    /* 4467 */ "mova %icc, $\x02, $\x01\0"
    /* 4485 */ "movn %icc, $\x02, $\x01\0"
    /* 4503 */ "movne %icc, $\x02, $\x01\0"
    /* 4522 */ "move %icc, $\x02, $\x01\0"
    /* 4540 */ "movg %icc, $\x02, $\x01\0"
    /* 4558 */ "movle %icc, $\x02, $\x01\0"
    /* 4577 */ "movge %icc, $\x02, $\x01\0"
    /* 4596 */ "movl %icc, $\x02, $\x01\0"
    /* 4614 */ "movgu %icc, $\x02, $\x01\0"
    /* 4633 */ "movleu %icc, $\x02, $\x01\0"
    /* 4653 */ "movcc %icc, $\x02, $\x01\0"
    /* 4672 */ "movcs %icc, $\x02, $\x01\0"
    /* 4691 */ "movpos %icc, $\x02, $\x01\0"
    /* 4711 */ "movneg %icc, $\x02, $\x01\0"
    /* 4731 */ "movvc %icc, $\x02, $\x01\0"
    /* 4750 */ "movvs %icc, $\x02, $\x01\0"
    /* 4769 */ "movrz $\x02, $\x03, $\x01\0"
    /* 4786 */ "movrlez $\x02, $\x03, $\x01\0"
    /* 4805 */ "movrlz $\x02, $\x03, $\x01\0"
    /* 4823 */ "movrnz $\x02, $\x03, $\x01\0"
    /* 4841 */ "movrgz $\x02, $\x03, $\x01\0"
    /* 4859 */ "movrgez $\x02, $\x03, $\x01\0"
    /* 4878 */ "mova %xcc, $\x02, $\x01\0"
    /* 4896 */ "movn %xcc, $\x02, $\x01\0"
    /* 4914 */ "movne %xcc, $\x02, $\x01\0"
    /* 4933 */ "move %xcc, $\x02, $\x01\0"
    /* 4951 */ "movg %xcc, $\x02, $\x01\0"
    /* 4969 */ "movle %xcc, $\x02, $\x01\0"
    /* 4988 */ "movge %xcc, $\x02, $\x01\0"
    /* 5007 */ "movl %xcc, $\x02, $\x01\0"
    /* 5025 */ "movgu %xcc, $\x02, $\x01\0"
    /* 5044 */ "movleu %xcc, $\x02, $\x01\0"
    /* 5064 */ "movcc %xcc, $\x02, $\x01\0"
    /* 5083 */ "movcs %xcc, $\x02, $\x01\0"
    /* 5102 */ "movpos %xcc, $\x02, $\x01\0"
    /* 5122 */ "movneg %xcc, $\x02, $\x01\0"
    /* 5142 */ "movvc %xcc, $\x02, $\x01\0"
    /* 5161 */ "movvs %xcc, $\x02, $\x01\0"
    /* 5180 */ "tst $\x02\0"
    /* 5187 */ "mov $\x03, $\x01\0"
    /* 5198 */ "restore\0"
    /* 5206 */ "ret\0"
    /* 5210 */ "retl\0"
    /* 5215 */ "save\0"
    /* 5220 */ "cmp $\x02, $\x03\0"
    /* 5231 */ "ta %icc, $\x02\0"
    /* 5243 */ "ta %icc, $\x01 + $\x02\0"
    /* 5260 */ "tn %icc, $\x02\0"
    /* 5272 */ "tn %icc, $\x01 + $\x02\0"
    /* 5289 */ "tne %icc, $\x02\0"
    /* 5302 */ "tne %icc, $\x01 + $\x02\0"
    /* 5320 */ "te %icc, $\x02\0"
    /* 5332 */ "te %icc, $\x01 + $\x02\0"
    /* 5349 */ "tg %icc, $\x02\0"
    /* 5361 */ "tg %icc, $\x01 + $\x02\0"
    /* 5378 */ "tle %icc, $\x02\0"
    /* 5391 */ "tle %icc, $\x01 + $\x02\0"
    /* 5409 */ "tge %icc, $\x02\0"
    /* 5422 */ "tge %icc, $\x01 + $\x02\0"
    /* 5440 */ "tl %icc, $\x02\0"
    /* 5452 */ "tl %icc, $\x01 + $\x02\0"
    /* 5469 */ "tgu %icc, $\x02\0"
    /* 5482 */ "tgu %icc, $\x01 + $\x02\0"
    /* 5500 */ "tleu %icc, $\x02\0"
    /* 5514 */ "tleu %icc, $\x01 + $\x02\0"
    /* 5533 */ "tcc %icc, $\x02\0"
    /* 5546 */ "tcc %icc, $\x01 + $\x02\0"
    /* 5564 */ "tcs %icc, $\x02\0"
    /* 5577 */ "tcs %icc, $\x01 + $\x02\0"
    /* 5595 */ "tpos %icc, $\x02\0"
    /* 5609 */ "tpos %icc, $\x01 + $\x02\0"
    /* 5628 */ "tneg %icc, $\x02\0"
    /* 5642 */ "tneg %icc, $\x01 + $\x02\0"
    /* 5661 */ "tvc %icc, $\x02\0"
    /* 5674 */ "tvc %icc, $\x01 + $\x02\0"
    /* 5692 */ "tvs %icc, $\x02\0"
    /* 5705 */ "tvs %icc, $\x01 + $\x02\0"
    /* 5723 */ "ta $\x02\0"
    /* 5729 */ "ta $\x01 + $\x02\0"
    /* 5740 */ "tn $\x02\0"
    /* 5746 */ "tn $\x01 + $\x02\0"
    /* 5757 */ "tne $\x02\0"
    /* 5764 */ "tne $\x01 + $\x02\0"
    /* 5776 */ "te $\x02\0"
    /* 5782 */ "te $\x01 + $\x02\0"
    /* 5793 */ "tg $\x02\0"
    /* 5799 */ "tg $\x01 + $\x02\0"
    /* 5810 */ "tle $\x02\0"
    /* 5817 */ "tle $\x01 + $\x02\0"
    /* 5829 */ "tge $\x02\0"
    /* 5836 */ "tge $\x01 + $\x02\0"
    /* 5848 */ "tl $\x02\0"
    /* 5854 */ "tl $\x01 + $\x02\0"
    /* 5865 */ "tgu $\x02\0"
    /* 5872 */ "tgu $\x01 + $\x02\0"
    /* 5884 */ "tleu $\x02\0"
    /* 5892 */ "tleu $\x01 + $\x02\0"
    /* 5905 */ "tcc $\x02\0"
    /* 5912 */ "tcc $\x01 + $\x02\0"
    /* 5924 */ "tcs $\x02\0"
    /* 5931 */ "tcs $\x01 + $\x02\0"
    /* 5943 */ "tpos $\x02\0"
    /* 5951 */ "tpos $\x01 + $\x02\0"
    /* 5964 */ "tneg $\x02\0"
    /* 5972 */ "tneg $\x01 + $\x02\0"
    /* 5985 */ "tvc $\x02\0"
    /* 5992 */ "tvc $\x01 + $\x02\0"
    /* 6004 */ "tvs $\x02\0"
    /* 6011 */ "tvs $\x01 + $\x02\0"
    /* 6023 */ "ta %xcc, $\x02\0"
    /* 6035 */ "ta %xcc, $\x01 + $\x02\0"
    /* 6052 */ "tn %xcc, $\x02\0"
    /* 6064 */ "tn %xcc, $\x01 + $\x02\0"
    /* 6081 */ "tne %xcc, $\x02\0"
    /* 6094 */ "tne %xcc, $\x01 + $\x02\0"
    /* 6112 */ "te %xcc, $\x02\0"
    /* 6124 */ "te %xcc, $\x01 + $\x02\0"
    /* 6141 */ "tg %xcc, $\x02\0"
    /* 6153 */ "tg %xcc, $\x01 + $\x02\0"
    /* 6170 */ "tle %xcc, $\x02\0"
    /* 6183 */ "tle %xcc, $\x01 + $\x02\0"
    /* 6201 */ "tge %xcc, $\x02\0"
    /* 6214 */ "tge %xcc, $\x01 + $\x02\0"
    /* 6232 */ "tl %xcc, $\x02\0"
    /* 6244 */ "tl %xcc, $\x01 + $\x02\0"
    /* 6261 */ "tgu %xcc, $\x02\0"
    /* 6274 */ "tgu %xcc, $\x01 + $\x02\0"
    /* 6292 */ "tleu %xcc, $\x02\0"
    /* 6306 */ "tleu %xcc, $\x01 + $\x02\0"
    /* 6325 */ "tcc %xcc, $\x02\0"
    /* 6338 */ "tcc %xcc, $\x01 + $\x02\0"
    /* 6356 */ "tcs %xcc, $\x02\0"
    /* 6369 */ "tcs %xcc, $\x01 + $\x02\0"
    /* 6387 */ "tpos %xcc, $\x02\0"
    /* 6401 */ "tpos %xcc, $\x01 + $\x02\0"
    /* 6420 */ "tneg %xcc, $\x02\0"
    /* 6434 */ "tneg %xcc, $\x01 + $\x02\0"
    /* 6453 */ "tvc %xcc, $\x02\0"
    /* 6466 */ "tvc %xcc, $\x01 + $\x02\0"
    /* 6484 */ "tvs %xcc, $\x02\0"
    /* 6497 */ "tvs %xcc, $\x01 + $\x02\0"
    /* 6515 */ "fcmpd $\x02, $\x03\0"
    /* 6528 */ "fcmped $\x02, $\x03\0"
    /* 6542 */ "fcmpeq $\x02, $\x03\0"
    /* 6556 */ "fcmpes $\x02, $\x03\0"
    /* 6570 */ "fcmpq $\x02, $\x03\0"
    /* 6583 */ "fcmps $\x02, $\x03\0"
    /* 6596 */ "fmovda $\x02, $\x03, $\x01\0"
    /* 6614 */ "fmovdn $\x02, $\x03, $\x01\0"
    /* 6632 */ "fmovdu $\x02, $\x03, $\x01\0"
    /* 6650 */ "fmovdg $\x02, $\x03, $\x01\0"
    /* 6668 */ "fmovdug $\x02, $\x03, $\x01\0"
    /* 6687 */ "fmovdl $\x02, $\x03, $\x01\0"
    /* 6705 */ "fmovdul $\x02, $\x03, $\x01\0"
    /* 6724 */ "fmovdlg $\x02, $\x03, $\x01\0"
    /* 6743 */ "fmovdne $\x02, $\x03, $\x01\0"
    /* 6762 */ "fmovde $\x02, $\x03, $\x01\0"
    /* 6780 */ "fmovdue $\x02, $\x03, $\x01\0"
    /* 6799 */ "fmovdge $\x02, $\x03, $\x01\0"
    /* 6818 */ "fmovduge $\x02, $\x03, $\x01\0"
    /* 6838 */ "fmovdle $\x02, $\x03, $\x01\0"
    /* 6857 */ "fmovdule $\x02, $\x03, $\x01\0"
    /* 6877 */ "fmovdo $\x02, $\x03, $\x01\0"
    /* 6895 */ "fmovqa $\x02, $\x03, $\x01\0"
    /* 6913 */ "fmovqn $\x02, $\x03, $\x01\0"
    /* 6931 */ "fmovqu $\x02, $\x03, $\x01\0"
    /* 6949 */ "fmovqg $\x02, $\x03, $\x01\0"
    /* 6967 */ "fmovqug $\x02, $\x03, $\x01\0"
    /* 6986 */ "fmovql $\x02, $\x03, $\x01\0"
    /* 7004 */ "fmovqul $\x02, $\x03, $\x01\0"
    /* 7023 */ "fmovqlg $\x02, $\x03, $\x01\0"
    /* 7042 */ "fmovqne $\x02, $\x03, $\x01\0"
    /* 7061 */ "fmovqe $\x02, $\x03, $\x01\0"
    /* 7079 */ "fmovque $\x02, $\x03, $\x01\0"
    /* 7098 */ "fmovqge $\x02, $\x03, $\x01\0"
    /* 7117 */ "fmovquge $\x02, $\x03, $\x01\0"
    /* 7137 */ "fmovqle $\x02, $\x03, $\x01\0"
    /* 7156 */ "fmovqule $\x02, $\x03, $\x01\0"
    /* 7176 */ "fmovqo $\x02, $\x03, $\x01\0"
    /* 7194 */ "fmovsa $\x02, $\x03, $\x01\0"
    /* 7212 */ "fmovsn $\x02, $\x03, $\x01\0"
    /* 7230 */ "fmovsu $\x02, $\x03, $\x01\0"
    /* 7248 */ "fmovsg $\x02, $\x03, $\x01\0"
    /* 7266 */ "fmovsug $\x02, $\x03, $\x01\0"
    /* 7285 */ "fmovsl $\x02, $\x03, $\x01\0"
    /* 7303 */ "fmovsul $\x02, $\x03, $\x01\0"
    /* 7322 */ "fmovslg $\x02, $\x03, $\x01\0"
    /* 7341 */ "fmovsne $\x02, $\x03, $\x01\0"
    /* 7360 */ "fmovse $\x02, $\x03, $\x01\0"
    /* 7378 */ "fmovsue $\x02, $\x03, $\x01\0"
    /* 7397 */ "fmovsge $\x02, $\x03, $\x01\0"
    /* 7416 */ "fmovsuge $\x02, $\x03, $\x01\0"
    /* 7436 */ "fmovsle $\x02, $\x03, $\x01\0"
    /* 7455 */ "fmovsule $\x02, $\x03, $\x01\0"
    /* 7475 */ "fmovso $\x02, $\x03, $\x01\0"
    /* 7493 */ "mova $\x02, $\x03, $\x01\0"
    /* 7509 */ "movn $\x02, $\x03, $\x01\0"
    /* 7525 */ "movu $\x02, $\x03, $\x01\0"
    /* 7541 */ "movg $\x02, $\x03, $\x01\0"
    /* 7557 */ "movug $\x02, $\x03, $\x01\0"
    /* 7574 */ "movl $\x02, $\x03, $\x01\0"
    /* 7590 */ "movul $\x02, $\x03, $\x01\0"
    /* 7607 */ "movlg $\x02, $\x03, $\x01\0"
    /* 7624 */ "movne $\x02, $\x03, $\x01\0"
    /* 7641 */ "move $\x02, $\x03, $\x01\0"
    /* 7657 */ "movue $\x02, $\x03, $\x01\0"
    /* 7674 */ "movge $\x02, $\x03, $\x01\0"
    /* 7691 */ "movuge $\x02, $\x03, $\x01\0"
    /* 7709 */ "movle $\x02, $\x03, $\x01\0"
    /* 7726 */ "movule $\x02, $\x03, $\x01\0"
    /* 7744 */ "movo $\x02, $\x03, $\x01\0"
  ;

#ifndef NDEBUG
  //static struct SortCheck {
  //  SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
  //    assert(std::is_sorted(
  //               OpToPatterns.begin(), OpToPatterns.end(),
  //               [](const PatternsForOpcode &L, const //PatternsForOpcode &R) {
  //                 return L.Opcode < R.Opcode;
  //               }) &&
  //           "tablegen failed to sort opcode patterns");
  //  }
  //} sortCheckVar(OpToPatterns);
#endif

  AliasMatchingData M = {
    OpToPatterns,
    Patterns,
    Conds,
    AsmStrings,
    NULL,
  };
  const char *AsmString = matchAliasPatterns(MI, &M);
  if (!AsmString) return false;

  unsigned I = 0;
  while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
         AsmString[I] != '$' && AsmString[I] != '\0')
    ++I;
  SStream_concat1(OS, '\t');
  char *substr = malloc(I+1);
  memcpy(substr, AsmString, I);
  substr[I] = '\0';
  SStream_concat0(OS, substr);
  free(substr);
  if (AsmString[I] != '\0') {
    if (AsmString[I] == ' ' || AsmString[I] == '\t') {
      SStream_concat1(OS, '\t');
      ++I;
    }
    do {
      if (AsmString[I] == '$') {
        ++I;
        if (AsmString[I] == (char)0xff) {
          ++I;
          int OpIdx = AsmString[I++] - 1;
          int PrintMethodIdx = AsmString[I++] - 1;
          printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS);
        } else
          printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS);
      } else {
        SStream_concat1(OS, AsmString[I++]);
      }
    } while (AsmString[I] != '\0');
  }

  return true;
#else
  return false;
#endif // CAPSTONE_DIET
}

static void printCustomAliasOperand(
         MCInst *MI, uint64_t Address, unsigned OpIdx,
         unsigned PrintMethodIdx,
         SStream *OS) {
#ifndef CAPSTONE_DIET
  CS_ASSERT_RET(0 && "Unknown PrintMethod kind");
#endif // CAPSTONE_DIET
}

#endif // PRINT_ALIAS_INSTR

Coverage Report

Created: 2025-08-29 06:29