/src/capstonenext/arch/TMS320C64x/TMS320C64xInstPrinter.c

Source (jump to first uncovered line)
/* Capstone Disassembly Engine */
/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */

#ifdef CAPSTONE_HAS_TMS320C64X

#include <ctype.h>
#include <string.h>

#include "TMS320C64xInstPrinter.h"
#include "../../MCInst.h"
#include "../../utils.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "../../MathExtras.h"
#include "TMS320C64xMapping.h"

#include "capstone/tms320c64x.h"

static const char *getRegisterName(unsigned RegNo);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O);
static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O);

void TMS320C64x_post_printer(csh ud, cs_insn *insn, SStream *insn_asm,
           MCInst *mci)
{
  SStream ss;
  const char *op_str_ptr, *p2;
  char tmp[8] = { 0 };
  unsigned int unit = 0;
  int i;
  cs_tms320c64x *tms320c64x;

  if (mci->csh->detail_opt) {
    tms320c64x = &mci->flat_insn->detail->tms320c64x;

    for (i = 0; i < insn->detail->groups_count; i++) {
      switch (insn->detail->groups[i]) {
      case TMS320C64X_GRP_FUNIT_D:
        unit = TMS320C64X_FUNIT_D;
        break;
      case TMS320C64X_GRP_FUNIT_L:
        unit = TMS320C64X_FUNIT_L;
        break;
      case TMS320C64X_GRP_FUNIT_M:
        unit = TMS320C64X_FUNIT_M;
        break;
      case TMS320C64X_GRP_FUNIT_S:
        unit = TMS320C64X_FUNIT_S;
        break;
      case TMS320C64X_GRP_FUNIT_NO:
        unit = TMS320C64X_FUNIT_NO;
        break;
      }
      if (unit != 0)
        break;
    }
    tms320c64x->funit.unit = unit;

    SStream_Init(&ss);
    if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
      SStream_concat(
        &ss, "[%c%s]|",
        (tms320c64x->condition.zero == 1) ? '!' : '|',
        cs_reg_name(ud, tms320c64x->condition.reg));

    // Sorry for all the fixes below. I don't have time to add more helper SStream functions.
    // Before that they messed around with the private buffer of the stream.
    // So it is better now. But still not efficient.
    op_str_ptr = strchr(SStream_rbuf(insn_asm), '\t');

    if ((op_str_ptr != NULL) &&
        (((p2 = strchr(op_str_ptr, '[')) != NULL) ||
         ((p2 = strchr(op_str_ptr, '(')) != NULL))) {
      while ((p2 > op_str_ptr) &&
             ((*p2 != 'a') && (*p2 != 'b')))
        p2--;
      if (p2 == op_str_ptr) {
        SStream_Flush(insn_asm, NULL);
        SStream_concat0(insn_asm, "Invalid!");
        return;
      }
      if (*p2 == 'a')
        strncpy(tmp, "1T", sizeof(tmp));
      else
        strncpy(tmp, "2T", sizeof(tmp));
    } else {
      tmp[0] = '\0';
    }
    SStream mnem_post = { 0 };
    SStream_Init(&mnem_post);
    switch (tms320c64x->funit.unit) {
    case TMS320C64X_FUNIT_D:
      SStream_concat(&mnem_post, ".D%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_L:
      SStream_concat(&mnem_post, ".L%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_M:
      SStream_concat(&mnem_post, ".M%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_S:
      SStream_concat(&mnem_post, ".S%s%u", tmp,
               tms320c64x->funit.side);
      break;
    }
    if (tms320c64x->funit.crosspath > 0)
      SStream_concat0(&mnem_post, "X");

    if (op_str_ptr != NULL) {
      // There is an op_str
      SStream_concat1(&mnem_post, '\t');
      SStream_replc_str(insn_asm, '\t',
            SStream_rbuf(&mnem_post));
    }

    if (tms320c64x->parallel != 0)
      SStream_concat0(insn_asm, "\t||");
    SStream_concat0(&ss, SStream_rbuf(insn_asm));
    SStream_Flush(insn_asm, NULL);
    SStream_concat0(insn_asm, SStream_rbuf(&ss));
  }
}

#define PRINT_ALIAS_INSTR
#include "TMS320C64xGenAsmWriter.inc"

#define GET_INSTRINFO_ENUM
#include "TMS320C64xGenInstrInfo.inc"

static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg;

  if (MCOperand_isReg(Op)) {
    reg = MCOperand_getReg(Op);
    if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) &&
        (OpNo == 1)) {
      switch (reg) {
      case TMS320C64X_REG_EFR:
        SStream_concat0(O, "EFR");
        break;
      case TMS320C64X_REG_IFR:
        SStream_concat0(O, "IFR");
        break;
      default:
        SStream_concat0(O, getRegisterName(reg));
        break;
      }
    } else {
      SStream_concat0(O, getRegisterName(reg));
    }

    if (MI->csh->detail_opt) {
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .type = TMS320C64X_OP_REG;
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .reg = reg;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  } else if (MCOperand_isImm(Op)) {
    int64_t Imm = MCOperand_getImm(Op);

    if (Imm >= 0) {
      if (Imm > HEX_THRESHOLD)
        SStream_concat(O, "0x%" PRIx64, Imm);
      else
        SStream_concat(O, "%" PRIu64, Imm);
    } else {
      if (Imm < -HEX_THRESHOLD)
        SStream_concat(O, "-0x%" PRIx64, -Imm);
      else
        SStream_concat(O, "-%" PRIu64, -Imm);
    }

    if (MI->csh->detail_opt) {
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .type = TMS320C64X_OP_IMM;
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .imm = Imm;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  }
}

static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  unsigned scaled, base, offset, mode, unit;
  cs_tms320c64x *tms320c64x;
  char st, nd;

  scaled = (Val >> 19) & 1;
  base = (Val >> 12) & 0x7f;
  offset = (Val >> 5) & 0x7f;
  mode = (Val >> 1) & 0xf;
  unit = Val & 1;

  if (scaled) {
    st = '[';
    nd = ']';
  } else {
    st = '(';
    nd = ')';
  }

  switch (mode) {
  case 0:
    SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 1:
    SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 4:
    SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 5:
    SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 8:
    SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 9:
    SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 10:
    SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 11:
    SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 12:
    SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 13:
    SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 14:
    SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 15:
    SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  }

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = base;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
    tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
    switch (mode) {
    case 0:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 1:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 4:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 5:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 8:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 9:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 10:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 11:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 12:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 13:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 14:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 15:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    }
    tms320c64x->op_count++;
  }
}

static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  uint16_t offset;
  unsigned basereg;
  cs_tms320c64x *tms320c64x;

  basereg = Val & 0x7f;
  offset = (Val >> 7) & 0x7fff;
  SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.disptype =
      TMS320C64X_MEM_DISP_CONSTANT;
    tms320c64x->operands[tms320c64x->op_count].mem.direction =
      TMS320C64X_MEM_DIR_FW;
    tms320c64x->operands[tms320c64x->op_count].mem.modify =
      TMS320C64X_MEM_MOD_NO;
    tms320c64x->op_count++;
  }
}

static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg = MCOperand_getReg(Op);
  cs_tms320c64x *tms320c64x;

  SStream_concat(O, "%s:%s", getRegisterName(reg + 1),
           getRegisterName(reg));

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_REGPAIR;
    tms320c64x->operands[tms320c64x->op_count].reg = reg;
    tms320c64x->op_count++;
  }
}

static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
{
  unsigned opcode = MCInst_getOpcode(MI);
  MCOperand *op;

  switch (opcode) {
  /* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
  case TMS320C64x_ADD_d2_rir:
  /* ADD.L -i, x, y -> SUB.L x, i, y */
  case TMS320C64x_ADD_l1_irr:
  case TMS320C64x_ADD_l1_ipp:
  /* ADD.S -i, x, y -> SUB.S x, i, y */
  case TMS320C64x_ADD_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
      op = MCInst_getOperand(MI, 2);
      MCOperand_setImm(op, -MCOperand_getImm(op));

      SStream_concat0(O, "SUB\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 2, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* ADD.D 0, x, y -> MV.D x, y */
  case TMS320C64x_ADD_d1_rir:
  /* OR.D x, 0, y -> MV.D x, y */
  case TMS320C64x_OR_d2_rir:
  /* ADD.L 0, x, y -> MV.L x, y */
  case TMS320C64x_ADD_l1_irr:
  case TMS320C64x_ADD_l1_ipp:
  /* OR.L 0, x, y -> MV.L x, y */
  case TMS320C64x_OR_l1_irr:
  /* ADD.S 0, x, y -> MV.S x, y */
  case TMS320C64x_ADD_s1_irr:
  /* OR.S 0, x, y -> MV.S x, y */
  case TMS320C64x_OR_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
      MI->size--;

      SStream_concat0(O, "MV\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* XOR.D -1, x, y -> NOT.D x, y */
  case TMS320C64x_XOR_d2_rir:
  /* XOR.L -1, x, y -> NOT.L x, y */
  case TMS320C64x_XOR_l1_irr:
  /* XOR.S -1, x, y -> NOT.S x, y */
  case TMS320C64x_XOR_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
      MI->size--;

      SStream_concat0(O, "NOT\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* MVK.D 0, x -> ZERO.D x */
  case TMS320C64x_MVK_d1_rr:
  /* MVK.L 0, x -> ZERO.L x */
  case TMS320C64x_MVK_l2_ir:
    if ((MCInst_getNumOperands(MI) == 2) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
      MI->size--;

      SStream_concat0(O, "ZERO\t");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* SUB.L x, x, y -> ZERO.L y */
  case TMS320C64x_SUB_l1_rrp_x1:
  /* SUB.S x, x, y -> ZERO.S y */
  case TMS320C64x_SUB_s1_rrr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
         MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
      MI->size -= 2;

      SStream_concat0(O, "ZERO\t");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* SUB.L 0, x, y -> NEG.L x, y */
  case TMS320C64x_SUB_l1_irr:
  case TMS320C64x_SUB_l1_ipp:
  /* SUB.S 0, x, y -> NEG.S x, y */
  case TMS320C64x_SUB_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
      MI->size--;

      SStream_concat0(O, "NEG\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* PACKLH2.L x, x, y -> SWAP2.L x, y */
  case TMS320C64x_PACKLH2_l1_rrr_x2:
  /* PACKLH2.S x, x, y -> SWAP2.S x, y */
  case TMS320C64x_PACKLH2_s1_rrr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
         MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
      MI->size--;

      SStream_concat0(O, "SWAP2\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* NOP 16 -> IDLE */
  /* NOP 1 -> NOP */
  case TMS320C64x_NOP_n:
    if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
      MI->size--;

      SStream_concat0(O, "IDLE");

      return true;
    }
    if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
      MI->size--;

      SStream_concat0(O, "NOP");

      return true;
    }
    break;
  }

  return false;
}

void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info)
{
  if (!printAliasInstruction(MI, O, Info))
    printInstruction(MI, O, Info);
}

#endif

Coverage Report

Created: 2025-08-29 06:29

Line	Count	Source (jump to first uncovered line)
1		/* Capstone Disassembly Engine */
2		/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
3
4		#ifdef CAPSTONE_HAS_TMS320C64X
5
6		#include <ctype.h>
7		#include <string.h>
8
9		#include "TMS320C64xInstPrinter.h"
10		#include "../../MCInst.h"
11		#include "../../utils.h"
12		#include "../../SStream.h"
13		#include "../../MCRegisterInfo.h"
14		#include "../../MathExtras.h"
15		#include "TMS320C64xMapping.h"
16
17		#include "capstone/tms320c64x.h"
18
19		static const char *getRegisterName(unsigned RegNo);
20		static void printOperand(MCInst MI, unsigned OpNo, SStream O);
21		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O);
22		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O);
23		static void printRegPair(MCInst MI, unsigned OpNo, SStream O);
24
25		void TMS320C64x_post_printer(csh ud, cs_insn insn, SStream insn_asm,
26		MCInst *mci)
27	23.8k	{
28	23.8k	SStream ss;
29	23.8k	const char op_str_ptr, p2;
30	23.8k	char tmp[8] = { 0 };
31	23.8k	unsigned int unit = 0;
32	23.8k	int i;
33	23.8k	cs_tms320c64x *tms320c64x;
34
35	23.8k	if (mci->csh->detail_opt) {
36	23.8k	tms320c64x = &mci->flat_insn->detail->tms320c64x;
37
38	23.8k	for (i = 0; i < insn->detail->groups_count; i++) {
39	23.8k	switch (insn->detail->groups[i]) {
40	6.24k	case TMS320C64X_GRP_FUNIT_D:
41	6.24k	unit = TMS320C64X_FUNIT_D;
42	6.24k	break;
43	4.54k	case TMS320C64X_GRP_FUNIT_L:
44	4.54k	unit = TMS320C64X_FUNIT_L;
45	4.54k	break;
46	1.59k	case TMS320C64X_GRP_FUNIT_M:
47	1.59k	unit = TMS320C64X_FUNIT_M;
48	1.59k	break;
49	10.7k	case TMS320C64X_GRP_FUNIT_S:
50	10.7k	unit = TMS320C64X_FUNIT_S;
51	10.7k	break;
52	675	case TMS320C64X_GRP_FUNIT_NO:
53	675	unit = TMS320C64X_FUNIT_NO;
54	675	break;
55	23.8k	}
56	23.8k	if (unit != 0)
57	23.8k	break;
58	23.8k	}
59	23.8k	tms320c64x->funit.unit = unit;
60
61	23.8k	SStream_Init(&ss);
62	23.8k	if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
63	13.8k	SStream_concat(
64	13.8k	&ss, "[%c%s]\|",
65	13.8k	(tms320c64x->condition.zero == 1) ? '!' : '\|',
66	13.8k	cs_reg_name(ud, tms320c64x->condition.reg));
67
68		// Sorry for all the fixes below. I don't have time to add more helper SStream functions.
69		// Before that they messed around with the private buffer of the stream.
70		// So it is better now. But still not efficient.
71	23.8k	op_str_ptr = strchr(SStream_rbuf(insn_asm), '\t');
72
73	23.8k	if ((op_str_ptr != NULL) &&
74	23.8k	(((p2 = strchr(op_str_ptr, '[')) != NULL) \|\|
75	23.1k	((p2 = strchr(op_str_ptr, '(')) != NULL))) {
76	20.3k	while ((p2 > op_str_ptr) &&
77	20.3k	((p2 != 'a') && (p2 != 'b')))
78	15.3k	p2--;
79	4.97k	if (p2 == op_str_ptr) {
80	0	SStream_Flush(insn_asm, NULL);
81	0	SStream_concat0(insn_asm, "Invalid!");
82	0	return;
83	0	}
84	4.97k	if (*p2 == 'a')
85	2.44k	strncpy(tmp, "1T", sizeof(tmp));
86	2.53k	else
87	2.53k	strncpy(tmp, "2T", sizeof(tmp));
88	18.8k	} else {
89	18.8k	tmp[0] = '\0';
90	18.8k	}
91	23.8k	SStream mnem_post = { 0 };
92	23.8k	SStream_Init(&mnem_post);
93	23.8k	switch (tms320c64x->funit.unit) {
94	6.24k	case TMS320C64X_FUNIT_D:
95	6.24k	SStream_concat(&mnem_post, ".D%s%u", tmp,
96	6.24k	tms320c64x->funit.side);
97	6.24k	break;
98	4.54k	case TMS320C64X_FUNIT_L:
99	4.54k	SStream_concat(&mnem_post, ".L%s%u", tmp,
100	4.54k	tms320c64x->funit.side);
101	4.54k	break;
102	1.59k	case TMS320C64X_FUNIT_M:
103	1.59k	SStream_concat(&mnem_post, ".M%s%u", tmp,
104	1.59k	tms320c64x->funit.side);
105	1.59k	break;
106	10.7k	case TMS320C64X_FUNIT_S:
107	10.7k	SStream_concat(&mnem_post, ".S%s%u", tmp,
108	10.7k	tms320c64x->funit.side);
109	10.7k	break;
110	23.8k	}
111	23.8k	if (tms320c64x->funit.crosspath > 0)
112	6.27k	SStream_concat0(&mnem_post, "X");
113
114	23.8k	if (op_str_ptr != NULL) {
115		// There is an op_str
116	23.1k	SStream_concat1(&mnem_post, '\t');
117	23.1k	SStream_replc_str(insn_asm, '\t',
118	23.1k	SStream_rbuf(&mnem_post));
119	23.1k	}
120
121	23.8k	if (tms320c64x->parallel != 0)
122	10.1k	SStream_concat0(insn_asm, "\t\|\|");
123	23.8k	SStream_concat0(&ss, SStream_rbuf(insn_asm));
124	23.8k	SStream_Flush(insn_asm, NULL);
125	23.8k	SStream_concat0(insn_asm, SStream_rbuf(&ss));
126	23.8k	}
127	23.8k	}
128
129		#define PRINT_ALIAS_INSTR
130		#include "TMS320C64xGenAsmWriter.inc"
131
132		#define GET_INSTRINFO_ENUM
133		#include "TMS320C64xGenInstrInfo.inc"
134
135		static void printOperand(MCInst MI, unsigned OpNo, SStream O)
136	46.0k	{
137	46.0k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
138	46.0k	unsigned reg;
139
140	46.0k	if (MCOperand_isReg(Op)) {
141	32.7k	reg = MCOperand_getReg(Op);
142	32.7k	if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) &&
143	32.7k	(OpNo == 1)) {
144	1.03k	switch (reg) {
145	636	case TMS320C64X_REG_EFR:
146	636	SStream_concat0(O, "EFR");
147	636	break;
148	285	case TMS320C64X_REG_IFR:
149	285	SStream_concat0(O, "IFR");
150	285	break;
151	111	default:
152	111	SStream_concat0(O, getRegisterName(reg));
153	111	break;
154	1.03k	}
155	31.7k	} else {
156	31.7k	SStream_concat0(O, getRegisterName(reg));
157	31.7k	}
158
159	32.7k	if (MI->csh->detail_opt) {
160	32.7k	MI->flat_insn->detail->tms320c64x
161	32.7k	.operands[MI->flat_insn->detail->tms320c64x
162	32.7k	.op_count]
163	32.7k	.type = TMS320C64X_OP_REG;
164	32.7k	MI->flat_insn->detail->tms320c64x
165	32.7k	.operands[MI->flat_insn->detail->tms320c64x
166	32.7k	.op_count]
167	32.7k	.reg = reg;
168	32.7k	MI->flat_insn->detail->tms320c64x.op_count++;
169	32.7k	}
170	32.7k	} else if (MCOperand_isImm(Op)) {
171	13.3k	int64_t Imm = MCOperand_getImm(Op);
172
173	13.3k	if (Imm >= 0) {
174	10.6k	if (Imm > HEX_THRESHOLD)
175	6.51k	SStream_concat(O, "0x%" PRIx64, Imm);
176	4.13k	else
177	4.13k	SStream_concat(O, "%" PRIu64, Imm);
178	10.6k	} else {
179	2.66k	if (Imm < -HEX_THRESHOLD)
180	2.15k	SStream_concat(O, "-0x%" PRIx64, -Imm);
181	514	else
182	514	SStream_concat(O, "-%" PRIu64, -Imm);
183	2.66k	}
184
185	13.3k	if (MI->csh->detail_opt) {
186	13.3k	MI->flat_insn->detail->tms320c64x
187	13.3k	.operands[MI->flat_insn->detail->tms320c64x
188	13.3k	.op_count]
189	13.3k	.type = TMS320C64X_OP_IMM;
190	13.3k	MI->flat_insn->detail->tms320c64x
191	13.3k	.operands[MI->flat_insn->detail->tms320c64x
192	13.3k	.op_count]
193	13.3k	.imm = Imm;
194	13.3k	MI->flat_insn->detail->tms320c64x.op_count++;
195	13.3k	}
196	13.3k	}
197	46.0k	}
198
199		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O)
200	2.44k	{
201	2.44k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
202	2.44k	int64_t Val = MCOperand_getImm(Op);
203	2.44k	unsigned scaled, base, offset, mode, unit;
204	2.44k	cs_tms320c64x *tms320c64x;
205	2.44k	char st, nd;
206
207	2.44k	scaled = (Val >> 19) & 1;
208	2.44k	base = (Val >> 12) & 0x7f;
209	2.44k	offset = (Val >> 5) & 0x7f;
210	2.44k	mode = (Val >> 1) & 0xf;
211	2.44k	unit = Val & 1;
212
213	2.44k	if (scaled) {
214	2.33k	st = '[';
215	2.33k	nd = ']';
216	2.33k	} else {
217	105	st = '(';
218	105	nd = ')';
219	105	}
220
221	2.44k	switch (mode) {
222	652	case 0:
223	652	SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st,
224	652	offset, nd);
225	652	break;
226	237	case 1:
227	237	SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st,
228	237	offset, nd);
229	237	break;
230	105	case 4:
231	105	SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st,
232	105	getRegisterName(offset), nd);
233	105	break;
234	80	case 5:
235	80	SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st,
236	80	getRegisterName(offset), nd);
237	80	break;
238	237	case 8:
239	237	SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st,
240	237	offset, nd);
241	237	break;
242	198	case 9:
243	198	SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st,
244	198	offset, nd);
245	198	break;
246	252	case 10:
247	252	SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st,
248	252	offset, nd);
249	252	break;
250	263	case 11:
251	263	SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st,
252	263	offset, nd);
253	263	break;
254	54	case 12:
255	54	SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st,
256	54	getRegisterName(offset), nd);
257	54	break;
258	132	case 13:
259	132	SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st,
260	132	getRegisterName(offset), nd);
261	132	break;
262	31	case 14:
263	31	SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st,
264	31	getRegisterName(offset), nd);
265	31	break;
266	201	case 15:
267	201	SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st,
268	201	getRegisterName(offset), nd);
269	201	break;
270	2.44k	}
271
272	2.44k	if (MI->csh->detail_opt) {
273	2.44k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
274
275	2.44k	tms320c64x->operands[tms320c64x->op_count].type =
276	2.44k	TMS320C64X_OP_MEM;
277	2.44k	tms320c64x->operands[tms320c64x->op_count].mem.base = base;
278	2.44k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
279	2.44k	tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
280	2.44k	tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
281	2.44k	switch (mode) {
282	652	case 0:
283	652	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
284	652	TMS320C64X_MEM_DISP_CONSTANT;
285	652	tms320c64x->operands[tms320c64x->op_count]
286	652	.mem.direction = TMS320C64X_MEM_DIR_BW;
287	652	tms320c64x->operands[tms320c64x->op_count].mem.modify =
288	652	TMS320C64X_MEM_MOD_NO;
289	652	break;
290	237	case 1:
291	237	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
292	237	TMS320C64X_MEM_DISP_CONSTANT;
293	237	tms320c64x->operands[tms320c64x->op_count]
294	237	.mem.direction = TMS320C64X_MEM_DIR_FW;
295	237	tms320c64x->operands[tms320c64x->op_count].mem.modify =
296	237	TMS320C64X_MEM_MOD_NO;
297	237	break;
298	105	case 4:
299	105	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
300	105	TMS320C64X_MEM_DISP_REGISTER;
301	105	tms320c64x->operands[tms320c64x->op_count]
302	105	.mem.direction = TMS320C64X_MEM_DIR_BW;
303	105	tms320c64x->operands[tms320c64x->op_count].mem.modify =
304	105	TMS320C64X_MEM_MOD_NO;
305	105	break;
306	80	case 5:
307	80	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
308	80	TMS320C64X_MEM_DISP_REGISTER;
309	80	tms320c64x->operands[tms320c64x->op_count]
310	80	.mem.direction = TMS320C64X_MEM_DIR_FW;
311	80	tms320c64x->operands[tms320c64x->op_count].mem.modify =
312	80	TMS320C64X_MEM_MOD_NO;
313	80	break;
314	237	case 8:
315	237	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
316	237	TMS320C64X_MEM_DISP_CONSTANT;
317	237	tms320c64x->operands[tms320c64x->op_count]
318	237	.mem.direction = TMS320C64X_MEM_DIR_BW;
319	237	tms320c64x->operands[tms320c64x->op_count].mem.modify =
320	237	TMS320C64X_MEM_MOD_PRE;
321	237	break;
322	198	case 9:
323	198	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
324	198	TMS320C64X_MEM_DISP_CONSTANT;
325	198	tms320c64x->operands[tms320c64x->op_count]
326	198	.mem.direction = TMS320C64X_MEM_DIR_FW;
327	198	tms320c64x->operands[tms320c64x->op_count].mem.modify =
328	198	TMS320C64X_MEM_MOD_PRE;
329	198	break;
330	252	case 10:
331	252	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
332	252	TMS320C64X_MEM_DISP_CONSTANT;
333	252	tms320c64x->operands[tms320c64x->op_count]
334	252	.mem.direction = TMS320C64X_MEM_DIR_BW;
335	252	tms320c64x->operands[tms320c64x->op_count].mem.modify =
336	252	TMS320C64X_MEM_MOD_POST;
337	252	break;
338	263	case 11:
339	263	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
340	263	TMS320C64X_MEM_DISP_CONSTANT;
341	263	tms320c64x->operands[tms320c64x->op_count]
342	263	.mem.direction = TMS320C64X_MEM_DIR_FW;
343	263	tms320c64x->operands[tms320c64x->op_count].mem.modify =
344	263	TMS320C64X_MEM_MOD_POST;
345	263	break;
346	54	case 12:
347	54	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
348	54	TMS320C64X_MEM_DISP_REGISTER;
349	54	tms320c64x->operands[tms320c64x->op_count]
350	54	.mem.direction = TMS320C64X_MEM_DIR_BW;
351	54	tms320c64x->operands[tms320c64x->op_count].mem.modify =
352	54	TMS320C64X_MEM_MOD_PRE;
353	54	break;
354	132	case 13:
355	132	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
356	132	TMS320C64X_MEM_DISP_REGISTER;
357	132	tms320c64x->operands[tms320c64x->op_count]
358	132	.mem.direction = TMS320C64X_MEM_DIR_FW;
359	132	tms320c64x->operands[tms320c64x->op_count].mem.modify =
360	132	TMS320C64X_MEM_MOD_PRE;
361	132	break;
362	31	case 14:
363	31	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
364	31	TMS320C64X_MEM_DISP_REGISTER;
365	31	tms320c64x->operands[tms320c64x->op_count]
366	31	.mem.direction = TMS320C64X_MEM_DIR_BW;
367	31	tms320c64x->operands[tms320c64x->op_count].mem.modify =
368	31	TMS320C64X_MEM_MOD_POST;
369	31	break;
370	201	case 15:
371	201	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
372	201	TMS320C64X_MEM_DISP_REGISTER;
373	201	tms320c64x->operands[tms320c64x->op_count]
374	201	.mem.direction = TMS320C64X_MEM_DIR_FW;
375	201	tms320c64x->operands[tms320c64x->op_count].mem.modify =
376	201	TMS320C64X_MEM_MOD_POST;
377	201	break;
378	2.44k	}
379	2.44k	tms320c64x->op_count++;
380	2.44k	}
381	2.44k	}
382
383		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O)
384	2.53k	{
385	2.53k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
386	2.53k	int64_t Val = MCOperand_getImm(Op);
387	2.53k	uint16_t offset;
388	2.53k	unsigned basereg;
389	2.53k	cs_tms320c64x *tms320c64x;
390
391	2.53k	basereg = Val & 0x7f;
392	2.53k	offset = (Val >> 7) & 0x7fff;
393	2.53k	SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);
394
395	2.53k	if (MI->csh->detail_opt) {
396	2.53k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
397
398	2.53k	tms320c64x->operands[tms320c64x->op_count].type =
399	2.53k	TMS320C64X_OP_MEM;
400	2.53k	tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
401	2.53k	tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
402	2.53k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
403	2.53k	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
404	2.53k	TMS320C64X_MEM_DISP_CONSTANT;
405	2.53k	tms320c64x->operands[tms320c64x->op_count].mem.direction =
406	2.53k	TMS320C64X_MEM_DIR_FW;
407	2.53k	tms320c64x->operands[tms320c64x->op_count].mem.modify =
408	2.53k	TMS320C64X_MEM_MOD_NO;
409	2.53k	tms320c64x->op_count++;
410	2.53k	}
411	2.53k	}
412
413		static void printRegPair(MCInst MI, unsigned OpNo, SStream O)
414	6.60k	{
415	6.60k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
416	6.60k	unsigned reg = MCOperand_getReg(Op);
417	6.60k	cs_tms320c64x *tms320c64x;
418
419	6.60k	SStream_concat(O, "%s:%s", getRegisterName(reg + 1),
420	6.60k	getRegisterName(reg));
421
422	6.60k	if (MI->csh->detail_opt) {
423	6.60k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
424
425	6.60k	tms320c64x->operands[tms320c64x->op_count].type =
426	6.60k	TMS320C64X_OP_REGPAIR;
427	6.60k	tms320c64x->operands[tms320c64x->op_count].reg = reg;
428	6.60k	tms320c64x->op_count++;
429	6.60k	}
430	6.60k	}
431
432		static bool printAliasInstruction(MCInst MI, SStream O, MCRegisterInfo *MRI)
433	23.8k	{
434	23.8k	unsigned opcode = MCInst_getOpcode(MI);
435	23.8k	MCOperand *op;
436
437	23.8k	switch (opcode) {
438		/* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
439	175	case TMS320C64x_ADD_d2_rir:
440		/* ADD.L -i, x, y -> SUB.L x, i, y */
441	393	case TMS320C64x_ADD_l1_irr:
442	551	case TMS320C64x_ADD_l1_ipp:
443		/* ADD.S -i, x, y -> SUB.S x, i, y */
444	623	case TMS320C64x_ADD_s1_irr:
445	623	if ((MCInst_getNumOperands(MI) == 3) &&
446	623	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
447	623	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
448	623	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
449	623	(MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
450	60	MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
451	60	op = MCInst_getOperand(MI, 2);
452	60	MCOperand_setImm(op, -MCOperand_getImm(op));
453
454	60	SStream_concat0(O, "SUB\t");
455	60	printOperand(MI, 1, O);
456	60	SStream_concat0(O, ", ");
457	60	printOperand(MI, 2, O);
458	60	SStream_concat0(O, ", ");
459	60	printOperand(MI, 0, O);
460
461	60	return true;
462	60	}
463	563	break;
464	23.8k	}
465	23.7k	switch (opcode) {
466		/* ADD.D 0, x, y -> MV.D x, y */
467	15	case TMS320C64x_ADD_d1_rir:
468		/* OR.D x, 0, y -> MV.D x, y */
469	266	case TMS320C64x_OR_d2_rir:
470		/* ADD.L 0, x, y -> MV.L x, y */
471	466	case TMS320C64x_ADD_l1_irr:
472	615	case TMS320C64x_ADD_l1_ipp:
473		/* OR.L 0, x, y -> MV.L x, y */
474	628	case TMS320C64x_OR_l1_irr:
475		/* ADD.S 0, x, y -> MV.S x, y */
476	675	case TMS320C64x_ADD_s1_irr:
477		/* OR.S 0, x, y -> MV.S x, y */
478	1.04k	case TMS320C64x_OR_s1_irr:
479	1.04k	if ((MCInst_getNumOperands(MI) == 3) &&
480	1.04k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
481	1.04k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
482	1.04k	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
483	1.04k	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
484	206	MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
485	206	MI->size--;
486
487	206	SStream_concat0(O, "MV\t");
488	206	printOperand(MI, 1, O);
489	206	SStream_concat0(O, ", ");
490	206	printOperand(MI, 0, O);
491
492	206	return true;
493	206	}
494	837	break;
495	23.7k	}
496	23.5k	switch (opcode) {
497		/* XOR.D -1, x, y -> NOT.D x, y */
498	284	case TMS320C64x_XOR_d2_rir:
499		/* XOR.L -1, x, y -> NOT.L x, y */
500	324	case TMS320C64x_XOR_l1_irr:
501		/* XOR.S -1, x, y -> NOT.S x, y */
502	534	case TMS320C64x_XOR_s1_irr:
503	534	if ((MCInst_getNumOperands(MI) == 3) &&
504	534	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
505	534	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
506	534	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
507	534	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
508	39	MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
509	39	MI->size--;
510
511	39	SStream_concat0(O, "NOT\t");
512	39	printOperand(MI, 1, O);
513	39	SStream_concat0(O, ", ");
514	39	printOperand(MI, 0, O);
515
516	39	return true;
517	39	}
518	495	break;
519	23.5k	}
520	23.5k	switch (opcode) {
521		/* MVK.D 0, x -> ZERO.D x */
522	126	case TMS320C64x_MVK_d1_rr:
523		/* MVK.L 0, x -> ZERO.L x */
524	523	case TMS320C64x_MVK_l2_ir:
525	523	if ((MCInst_getNumOperands(MI) == 2) &&
526	523	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
527	523	MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
528	523	(MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
529	145	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
530	145	MI->size--;
531
532	145	SStream_concat0(O, "ZERO\t");
533	145	printOperand(MI, 0, O);
534
535	145	return true;
536	145	}
537	378	break;
538	23.5k	}
539	23.3k	switch (opcode) {
540		/* SUB.L x, x, y -> ZERO.L y */
541	37	case TMS320C64x_SUB_l1_rrp_x1:
542		/* SUB.S x, x, y -> ZERO.S y */
543	89	case TMS320C64x_SUB_s1_rrr:
544	89	if ((MCInst_getNumOperands(MI) == 3) &&
545	89	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
546	89	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
547	89	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
548	89	(MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
549	89	MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
550	7	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
551	7	MI->size -= 2;
552
553	7	SStream_concat0(O, "ZERO\t");
554	7	printOperand(MI, 0, O);
555
556	7	return true;
557	7	}
558	82	break;
559	23.3k	}
560	23.3k	switch (opcode) {
561		/* SUB.L 0, x, y -> NEG.L x, y */
562	86	case TMS320C64x_SUB_l1_irr:
563	165	case TMS320C64x_SUB_l1_ipp:
564		/* SUB.S 0, x, y -> NEG.S x, y */
565	224	case TMS320C64x_SUB_s1_irr:
566	224	if ((MCInst_getNumOperands(MI) == 3) &&
567	224	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
568	224	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
569	224	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
570	224	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
571	86	MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
572	86	MI->size--;
573
574	86	SStream_concat0(O, "NEG\t");
575	86	printOperand(MI, 1, O);
576	86	SStream_concat0(O, ", ");
577	86	printOperand(MI, 0, O);
578
579	86	return true;
580	86	}
581	138	break;
582	23.3k	}
583	23.2k	switch (opcode) {
584		/* PACKLH2.L x, x, y -> SWAP2.L x, y */
585	92	case TMS320C64x_PACKLH2_l1_rrr_x2:
586		/* PACKLH2.S x, x, y -> SWAP2.S x, y */
587	286	case TMS320C64x_PACKLH2_s1_rrr:
588	286	if ((MCInst_getNumOperands(MI) == 3) &&
589	286	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
590	286	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
591	286	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
592	286	(MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
593	286	MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
594	89	MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
595	89	MI->size--;
596
597	89	SStream_concat0(O, "SWAP2\t");
598	89	printOperand(MI, 1, O);
599	89	SStream_concat0(O, ", ");
600	89	printOperand(MI, 0, O);
601
602	89	return true;
603	89	}
604	197	break;
605	23.2k	}
606	23.1k	switch (opcode) {
607		/* NOP 16 -> IDLE */
608		/* NOP 1 -> NOP */
609	675	case TMS320C64x_NOP_n:
610	675	if ((MCInst_getNumOperands(MI) == 1) &&
611	675	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
612	675	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
613	110	MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
614	110	MI->size--;
615
616	110	SStream_concat0(O, "IDLE");
617
618	110	return true;
619	110	}
620	565	if ((MCInst_getNumOperands(MI) == 1) &&
621	565	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
622	565	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
623	542	MI->size--;
624
625	542	SStream_concat0(O, "NOP");
626
627	542	return true;
628	542	}
629	23	break;
630	23.1k	}
631
632	22.5k	return false;
633	23.1k	}
634
635		void TMS320C64x_printInst(MCInst MI, SStream O, void *Info)
636	23.8k	{
637	23.8k	if (!printAliasInstruction(MI, O, Info))
638	22.5k	printInstruction(MI, O, Info);
639	23.8k	}
640
641		#endif