Coverage Report

Created: 2025-08-29 06:29

/src/capstonev5/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|*Assembly Writer Source Fragment                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
15
16
/// printInstruction - This method is automatically generated by tablegen
17
/// from the instruction set description.
18
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19
35.9k
{
20
35.9k
  static const uint32_t OpInfo[] = {
21
35.9k
    0U, // PHI
22
35.9k
    0U, // INLINEASM
23
35.9k
    0U, // CFI_INSTRUCTION
24
35.9k
    0U, // EH_LABEL
25
35.9k
    0U, // GC_LABEL
26
35.9k
    0U, // KILL
27
35.9k
    0U, // EXTRACT_SUBREG
28
35.9k
    0U, // INSERT_SUBREG
29
35.9k
    0U, // IMPLICIT_DEF
30
35.9k
    0U, // SUBREG_TO_REG
31
35.9k
    0U, // COPY_TO_REGCLASS
32
35.9k
    2452U,  // DBG_VALUE
33
35.9k
    0U, // REG_SEQUENCE
34
35.9k
    0U, // COPY
35
35.9k
    2445U,  // BUNDLE
36
35.9k
    2462U,  // LIFETIME_START
37
35.9k
    2432U,  // LIFETIME_END
38
35.9k
    0U, // STACKMAP
39
35.9k
    0U, // PATCHPOINT
40
35.9k
    0U, // LOAD_STACK_GUARD
41
35.9k
    0U, // STATEPOINT
42
35.9k
    0U, // FRAME_ALLOC
43
35.9k
    4688U,  // ADDCCri
44
35.9k
    4688U,  // ADDCCrr
45
35.9k
    5925U,  // ADDCri
46
35.9k
    5925U,  // ADDCrr
47
35.9k
    4772U,  // ADDEri
48
35.9k
    4772U,  // ADDErr
49
35.9k
    4786U,  // ADDXC
50
35.9k
    4678U,  // ADDXCCC
51
35.9k
    4808U,  // ADDXri
52
35.9k
    4808U,  // ADDXrr
53
35.9k
    4808U,  // ADDri
54
35.9k
    4808U,  // ADDrr
55
35.9k
    74166U, // ADJCALLSTACKDOWN
56
35.9k
    74185U, // ADJCALLSTACKUP
57
35.9k
    5497U,  // ALIGNADDR
58
35.9k
    5127U,  // ALIGNADDRL
59
35.9k
    4695U,  // ANDCCri
60
35.9k
    4695U,  // ANDCCrr
61
35.9k
    4718U,  // ANDNCCri
62
35.9k
    4718U,  // ANDNCCrr
63
35.9k
    5182U,  // ANDNri
64
35.9k
    5182U,  // ANDNrr
65
35.9k
    5182U,  // ANDXNrr
66
35.9k
    4876U,  // ANDXri
67
35.9k
    4876U,  // ANDXrr
68
35.9k
    4876U,  // ANDri
69
35.9k
    4876U,  // ANDrr
70
35.9k
    4502U,  // ARRAY16
71
35.9k
    4255U,  // ARRAY32
72
35.9k
    4526U,  // ARRAY8
73
35.9k
    0U, // ATOMIC_LOAD_ADD_32
74
35.9k
    0U, // ATOMIC_LOAD_ADD_64
75
35.9k
    0U, // ATOMIC_LOAD_AND_32
76
35.9k
    0U, // ATOMIC_LOAD_AND_64
77
35.9k
    0U, // ATOMIC_LOAD_MAX_32
78
35.9k
    0U, // ATOMIC_LOAD_MAX_64
79
35.9k
    0U, // ATOMIC_LOAD_MIN_32
80
35.9k
    0U, // ATOMIC_LOAD_MIN_64
81
35.9k
    0U, // ATOMIC_LOAD_NAND_32
82
35.9k
    0U, // ATOMIC_LOAD_NAND_64
83
35.9k
    0U, // ATOMIC_LOAD_OR_32
84
35.9k
    0U, // ATOMIC_LOAD_OR_64
85
35.9k
    0U, // ATOMIC_LOAD_SUB_32
86
35.9k
    0U, // ATOMIC_LOAD_SUB_64
87
35.9k
    0U, // ATOMIC_LOAD_UMAX_32
88
35.9k
    0U, // ATOMIC_LOAD_UMAX_64
89
35.9k
    0U, // ATOMIC_LOAD_UMIN_32
90
35.9k
    0U, // ATOMIC_LOAD_UMIN_64
91
35.9k
    0U, // ATOMIC_LOAD_XOR_32
92
35.9k
    0U, // ATOMIC_LOAD_XOR_64
93
35.9k
    0U, // ATOMIC_SWAP_64
94
35.9k
    74271U, // BA
95
35.9k
    1194492U, // BCOND
96
35.9k
    1260028U, // BCONDA
97
35.9k
    17659U, // BINDri
98
35.9k
    17659U, // BINDrr
99
35.9k
    5065U,  // BMASK
100
35.9k
    145915U,  // BPFCC
101
35.9k
    211451U,  // BPFCCA
102
35.9k
    276987U,  // BPFCCANT
103
35.9k
    342523U,  // BPFCCNT
104
35.9k
    2106465U, // BPGEZapn
105
35.9k
    2105838U, // BPGEZapt
106
35.9k
    2106532U, // BPGEZnapn
107
35.9k
    2107288U, // BPGEZnapt
108
35.9k
    2106489U, // BPGZapn
109
35.9k
    2105856U, // BPGZapt
110
35.9k
    2106552U, // BPGZnapn
111
35.9k
    2107384U, // BPGZnapt
112
35.9k
    1456636U, // BPICC
113
35.9k
    473596U,  // BPICCA
114
35.9k
    539132U,  // BPICCANT
115
35.9k
    604668U,  // BPICCNT
116
35.9k
    2106477U, // BPLEZapn
117
35.9k
    2105847U, // BPLEZapt
118
35.9k
    2106542U, // BPLEZnapn
119
35.9k
    2107337U, // BPLEZnapt
120
35.9k
    2106500U, // BPLZapn
121
35.9k
    2105864U, // BPLZapt
122
35.9k
    2106561U, // BPLZnapn
123
35.9k
    2107428U, // BPLZnapt
124
35.9k
    2106511U, // BPNZapn
125
35.9k
    2105872U, // BPNZapt
126
35.9k
    2106570U, // BPNZnapn
127
35.9k
    2107472U, // BPNZnapt
128
35.9k
    1718780U, // BPXCC
129
35.9k
    735740U,  // BPXCCA
130
35.9k
    801276U,  // BPXCCANT
131
35.9k
    866812U,  // BPXCCNT
132
35.9k
    2106522U, // BPZapn
133
35.9k
    2105880U, // BPZapt
134
35.9k
    2106579U, // BPZnapn
135
35.9k
    2107505U, // BPZnapt
136
35.9k
    4983U,  // BSHUFFLE
137
35.9k
    74742U, // CALL
138
35.9k
    17398U, // CALLri
139
35.9k
    17398U, // CALLrr
140
35.9k
    924148U,  // CASXrr
141
35.9k
    924129U,  // CASrr
142
35.9k
    74001U, // CMASK16
143
35.9k
    73833U, // CMASK32
144
35.9k
    74150U, // CMASK8
145
35.9k
    2106607U, // CMPri
146
35.9k
    2106607U, // CMPrr
147
35.9k
    4332U,  // EDGE16
148
35.9k
    5081U,  // EDGE16L
149
35.9k
    5198U,  // EDGE16LN
150
35.9k
    5165U,  // EDGE16N
151
35.9k
    4164U,  // EDGE32
152
35.9k
    5072U,  // EDGE32L
153
35.9k
    5188U,  // EDGE32LN
154
35.9k
    5156U,  // EDGE32N
155
35.9k
    4511U,  // EDGE8
156
35.9k
    5090U,  // EDGE8L
157
35.9k
    5208U,  // EDGE8LN
158
35.9k
    5174U,  // EDGE8N
159
35.9k
    1053516U, // FABSD
160
35.9k
    1054031U, // FABSQ
161
35.9k
    1054376U, // FABSS
162
35.9k
    4813U,  // FADDD
163
35.9k
    5383U,  // FADDQ
164
35.9k
    5645U,  // FADDS
165
35.9k
    4648U,  // FALIGNADATA
166
35.9k
    4875U,  // FAND
167
35.9k
    4112U,  // FANDNOT1
168
35.9k
    5544U,  // FANDNOT1S
169
35.9k
    4271U,  // FANDNOT2
170
35.9k
    5591U,  // FANDNOT2S
171
35.9k
    5677U,  // FANDS
172
35.9k
    1194491U, // FBCOND
173
35.9k
    1260027U, // FBCONDA
174
35.9k
    4394U,  // FCHKSM16
175
35.9k
    2106173U, // FCMPD
176
35.9k
    4413U,  // FCMPEQ16
177
35.9k
    4226U,  // FCMPEQ32
178
35.9k
    4432U,  // FCMPGT16
179
35.9k
    4245U,  // FCMPGT32
180
35.9k
    4340U,  // FCMPLE16
181
35.9k
    4172U,  // FCMPLE32
182
35.9k
    4350U,  // FCMPNE16
183
35.9k
    4182U,  // FCMPNE32
184
35.9k
    2106696U, // FCMPQ
185
35.9k
    2107005U, // FCMPS
186
35.9k
    4960U,  // FDIVD
187
35.9k
    5475U,  // FDIVQ
188
35.9k
    5815U,  // FDIVS
189
35.9k
    5405U,  // FDMULQ
190
35.9k
    1053620U, // FDTOI
191
35.9k
    1053996U, // FDTOQ
192
35.9k
    1054305U, // FDTOS
193
35.9k
    1054536U, // FDTOX
194
35.9k
    1053464U, // FEXPAND
195
35.9k
    4820U,  // FHADDD
196
35.9k
    5652U,  // FHADDS
197
35.9k
    4800U,  // FHSUBD
198
35.9k
    5637U,  // FHSUBS
199
35.9k
    1053473U, // FITOD
200
35.9k
    1054003U, // FITOQ
201
35.9k
    1054312U, // FITOS
202
35.9k
    6300484U, // FLCMPD
203
35.9k
    6301316U, // FLCMPS
204
35.9k
    2606U,  // FLUSHW
205
35.9k
    4404U,  // FMEAN16
206
35.9k
    1053543U, // FMOVD
207
35.9k
    1006078U, // FMOVD_FCC
208
35.9k
    23484926U,  // FMOVD_ICC
209
35.9k
    23747070U,  // FMOVD_XCC
210
35.9k
    1054058U, // FMOVQ
211
35.9k
    1006102U, // FMOVQ_FCC
212
35.9k
    23484950U,  // FMOVQ_ICC
213
35.9k
    23747094U,  // FMOVQ_XCC
214
35.9k
    6018U,  // FMOVRGEZD
215
35.9k
    6029U,  // FMOVRGEZQ
216
35.9k
    6056U,  // FMOVRGEZS
217
35.9k
    6116U,  // FMOVRGZD
218
35.9k
    6126U,  // FMOVRGZQ
219
35.9k
    6150U,  // FMOVRGZS
220
35.9k
    6067U,  // FMOVRLEZD
221
35.9k
    6078U,  // FMOVRLEZQ
222
35.9k
    6105U,  // FMOVRLEZS
223
35.9k
    6160U,  // FMOVRLZD
224
35.9k
    6170U,  // FMOVRLZQ
225
35.9k
    6194U,  // FMOVRLZS
226
35.9k
    6204U,  // FMOVRNZD
227
35.9k
    6214U,  // FMOVRNZQ
228
35.9k
    6238U,  // FMOVRNZS
229
35.9k
    6009U,  // FMOVRZD
230
35.9k
    6248U,  // FMOVRZQ
231
35.9k
    6269U,  // FMOVRZS
232
35.9k
    1054398U, // FMOVS
233
35.9k
    1006114U, // FMOVS_FCC
234
35.9k
    23484962U,  // FMOVS_ICC
235
35.9k
    23747106U,  // FMOVS_XCC
236
35.9k
    4490U,  // FMUL8SUX16
237
35.9k
    4465U,  // FMUL8ULX16
238
35.9k
    4442U,  // FMUL8X16
239
35.9k
    5098U,  // FMUL8X16AL
240
35.9k
    5849U,  // FMUL8X16AU
241
35.9k
    4860U,  // FMULD
242
35.9k
    4477U,  // FMULD8SUX16
243
35.9k
    4452U,  // FMULD8ULX16
244
35.9k
    5413U,  // FMULQ
245
35.9k
    5714U,  // FMULS
246
35.9k
    4837U,  // FNADDD
247
35.9k
    5669U,  // FNADDS
248
35.9k
    4881U,  // FNAND
249
35.9k
    5684U,  // FNANDS
250
35.9k
    1053429U, // FNEGD
251
35.9k
    1053974U, // FNEGQ
252
35.9k
    1054283U, // FNEGS
253
35.9k
    4828U,  // FNHADDD
254
35.9k
    5660U,  // FNHADDS
255
35.9k
    4828U,  // FNMULD
256
35.9k
    5660U,  // FNMULS
257
35.9k
    5513U,  // FNOR
258
35.9k
    5778U,  // FNORS
259
35.9k
    1052698U, // FNOT1
260
35.9k
    1054131U, // FNOT1S
261
35.9k
    1052857U, // FNOT2
262
35.9k
    1054178U, // FNOT2S
263
35.9k
    5660U,  // FNSMULD
264
35.9k
    74625U, // FONE
265
35.9k
    75324U, // FONES
266
35.9k
    5508U,  // FOR
267
35.9k
    4129U,  // FORNOT1
268
35.9k
    5563U,  // FORNOT1S
269
35.9k
    4288U,  // FORNOT2
270
35.9k
    5610U,  // FORNOT2S
271
35.9k
    5772U,  // FORS
272
35.9k
    1052936U, // FPACK16
273
35.9k
    4192U,  // FPACK32
274
35.9k
    1054507U, // FPACKFIX
275
35.9k
    4323U,  // FPADD16
276
35.9k
    5620U,  // FPADD16S
277
35.9k
    4155U,  // FPADD32
278
35.9k
    5573U,  // FPADD32S
279
35.9k
    4297U,  // FPADD64
280
35.9k
    4974U,  // FPMERGE
281
35.9k
    4314U,  // FPSUB16
282
35.9k
    4580U,  // FPSUB16S
283
35.9k
    4146U,  // FPSUB32
284
35.9k
    4570U,  // FPSUB32S
285
35.9k
    1053480U, // FQTOD
286
35.9k
    1053627U, // FQTOI
287
35.9k
    1054319U, // FQTOS
288
35.9k
    1054552U, // FQTOX
289
35.9k
    4423U,  // FSLAS16
290
35.9k
    4236U,  // FSLAS32
291
35.9k
    4378U,  // FSLL16
292
35.9k
    4210U,  // FSLL32
293
35.9k
    4867U,  // FSMULD
294
35.9k
    1053523U, // FSQRTD
295
35.9k
    1054038U, // FSQRTQ
296
35.9k
    1054383U, // FSQRTS
297
35.9k
    4306U,  // FSRA16
298
35.9k
    4138U,  // FSRA32
299
35.9k
    1052681U, // FSRC1
300
35.9k
    1054112U, // FSRC1S
301
35.9k
    1052840U, // FSRC2
302
35.9k
    1054159U, // FSRC2S
303
35.9k
    4386U,  // FSRL16
304
35.9k
    4218U,  // FSRL32
305
35.9k
    1053487U, // FSTOD
306
35.9k
    1053634U, // FSTOI
307
35.9k
    1054010U, // FSTOQ
308
35.9k
    1054559U, // FSTOX
309
35.9k
    4793U,  // FSUBD
310
35.9k
    5376U,  // FSUBQ
311
35.9k
    5630U,  // FSUBS
312
35.9k
    5519U,  // FXNOR
313
35.9k
    5785U,  // FXNORS
314
35.9k
    5526U,  // FXOR
315
35.9k
    5793U,  // FXORS
316
35.9k
    1053494U, // FXTOD
317
35.9k
    1054017U, // FXTOQ
318
35.9k
    1054326U, // FXTOS
319
35.9k
    74984U, // FZERO
320
35.9k
    75353U, // FZEROS
321
35.9k
    24584U, // GETPCX
322
35.9k
    1078273U, // JMPLri
323
35.9k
    1078273U, // JMPLrr
324
35.9k
    1997243U, // LDDFri
325
35.9k
    1997243U, // LDDFrr
326
35.9k
    1997249U, // LDFri
327
35.9k
    1997249U, // LDFrr
328
35.9k
    1997275U, // LDQFri
329
35.9k
    1997275U, // LDQFrr
330
35.9k
    1997229U, // LDSBri
331
35.9k
    1997229U, // LDSBrr
332
35.9k
    1997254U, // LDSHri
333
35.9k
    1997254U, // LDSHrr
334
35.9k
    1997287U, // LDSWri
335
35.9k
    1997287U, // LDSWrr
336
35.9k
    1997236U, // LDUBri
337
35.9k
    1997236U, // LDUBrr
338
35.9k
    1997261U, // LDUHri
339
35.9k
    1997261U, // LDUHrr
340
35.9k
    1997294U, // LDXri
341
35.9k
    1997294U, // LDXrr
342
35.9k
    1997249U, // LDri
343
35.9k
    1997249U, // LDrr
344
35.9k
    33480U, // LEAX_ADDri
345
35.9k
    33480U, // LEA_ADDri
346
35.9k
    1054405U, // LZCNT
347
35.9k
    75121U, // MEMBARi
348
35.9k
    1054543U, // MOVDTOX
349
35.9k
    1006122U, // MOVFCCri
350
35.9k
    1006122U, // MOVFCCrr
351
35.9k
    23484970U,  // MOVICCri
352
35.9k
    23484970U,  // MOVICCrr
353
35.9k
    6047U,  // MOVRGEZri
354
35.9k
    6047U,  // MOVRGEZrr
355
35.9k
    6142U,  // MOVRGZri
356
35.9k
    6142U,  // MOVRGZrr
357
35.9k
    6096U,  // MOVRLEZri
358
35.9k
    6096U,  // MOVRLEZrr
359
35.9k
    6186U,  // MOVRLZri
360
35.9k
    6186U,  // MOVRLZrr
361
35.9k
    6230U,  // MOVRNZri
362
35.9k
    6230U,  // MOVRNZrr
363
35.9k
    6262U,  // MOVRRZri
364
35.9k
    6262U,  // MOVRRZrr
365
35.9k
    1054469U, // MOVSTOSW
366
35.9k
    1054479U, // MOVSTOUW
367
35.9k
    1054543U, // MOVWTOS
368
35.9k
    23747114U,  // MOVXCCri
369
35.9k
    23747114U,  // MOVXCCrr
370
35.9k
    1054543U, // MOVXTOD
371
35.9k
    5954U,  // MULXri
372
35.9k
    5954U,  // MULXrr
373
35.9k
    2578U,  // NOP
374
35.9k
    4735U,  // ORCCri
375
35.9k
    4735U,  // ORCCrr
376
35.9k
    4726U,  // ORNCCri
377
35.9k
    4726U,  // ORNCCrr
378
35.9k
    5339U,  // ORNri
379
35.9k
    5339U,  // ORNrr
380
35.9k
    5339U,  // ORXNrr
381
35.9k
    5509U,  // ORXri
382
35.9k
    5509U,  // ORXrr
383
35.9k
    5509U,  // ORri
384
35.9k
    5509U,  // ORrr
385
35.9k
    5836U,  // PDIST
386
35.9k
    5344U,  // PDISTN
387
35.9k
    1053356U, // POPCrr
388
35.9k
    73729U, // RDY
389
35.9k
    4999U,  // RESTOREri
390
35.9k
    4999U,  // RESTORErr
391
35.9k
    76132U, // RET
392
35.9k
    76141U, // RETL
393
35.9k
    18131U, // RETTri
394
35.9k
    18131U, // RETTrr
395
35.9k
    5008U,  // SAVEri
396
35.9k
    5008U,  // SAVErr
397
35.9k
    4748U,  // SDIVCCri
398
35.9k
    4748U,  // SDIVCCrr
399
35.9k
    5995U,  // SDIVXri
400
35.9k
    5995U,  // SDIVXrr
401
35.9k
    5861U,  // SDIVri
402
35.9k
    5861U,  // SDIVrr
403
35.9k
    2182U,  // SELECT_CC_DFP_FCC
404
35.9k
    2293U,  // SELECT_CC_DFP_ICC
405
35.9k
    2238U,  // SELECT_CC_FP_FCC
406
35.9k
    2349U,  // SELECT_CC_FP_ICC
407
35.9k
    2265U,  // SELECT_CC_Int_FCC
408
35.9k
    2376U,  // SELECT_CC_Int_ICC
409
35.9k
    2210U,  // SELECT_CC_QFP_FCC
410
35.9k
    2321U,  // SELECT_CC_QFP_ICC
411
35.9k
    1053595U, // SETHIXi
412
35.9k
    1053595U, // SETHIi
413
35.9k
    2569U,  // SHUTDOWN
414
35.9k
    2564U,  // SIAM
415
35.9k
    5941U,  // SLLXri
416
35.9k
    5941U,  // SLLXrr
417
35.9k
    5116U,  // SLLri
418
35.9k
    5116U,  // SLLrr
419
35.9k
    4702U,  // SMULCCri
420
35.9k
    4702U,  // SMULCCrr
421
35.9k
    5144U,  // SMULri
422
35.9k
    5144U,  // SMULrr
423
35.9k
    5913U,  // SRAXri
424
35.9k
    5913U,  // SRAXrr
425
35.9k
    4643U,  // SRAri
426
35.9k
    4643U,  // SRArr
427
35.9k
    5947U,  // SRLXri
428
35.9k
    5947U,  // SRLXrr
429
35.9k
    5139U,  // SRLri
430
35.9k
    5139U,  // SRLrr
431
35.9k
    2588U,  // STBAR
432
35.9k
    37428U, // STBri
433
35.9k
    37428U, // STBrr
434
35.9k
    37723U, // STDFri
435
35.9k
    37723U, // STDFrr
436
35.9k
    38607U, // STFri
437
35.9k
    38607U, // STFrr
438
35.9k
    37782U, // STHri
439
35.9k
    37782U, // STHrr
440
35.9k
    38238U, // STQFri
441
35.9k
    38238U, // STQFrr
442
35.9k
    38758U, // STXri
443
35.9k
    38758U, // STXrr
444
35.9k
    38607U, // STri
445
35.9k
    38607U, // STrr
446
35.9k
    4671U,  // SUBCCri
447
35.9k
    4671U,  // SUBCCrr
448
35.9k
    5919U,  // SUBCri
449
35.9k
    5919U,  // SUBCrr
450
35.9k
    4764U,  // SUBEri
451
35.9k
    4764U,  // SUBErr
452
35.9k
    4665U,  // SUBXri
453
35.9k
    4665U,  // SUBXrr
454
35.9k
    4665U,  // SUBri
455
35.9k
    4665U,  // SUBrr
456
35.9k
    1997268U, // SWAPri
457
35.9k
    1997268U, // SWAPrr
458
35.9k
    2422U,  // TA3
459
35.9k
    2427U,  // TA5
460
35.9k
    5883U,  // TADDCCTVri
461
35.9k
    5883U,  // TADDCCTVrr
462
35.9k
    4687U,  // TADDCCri
463
35.9k
    4687U,  // TADDCCrr
464
35.9k
    9873960U, // TICCri
465
35.9k
    9873960U, // TICCrr
466
35.9k
    37753544U,  // TLS_ADDXrr
467
35.9k
    37753544U,  // TLS_ADDrr
468
35.9k
    2106358U, // TLS_CALL
469
35.9k
    39746030U,  // TLS_LDXrr
470
35.9k
    39745985U,  // TLS_LDrr
471
35.9k
    5873U,  // TSUBCCTVri
472
35.9k
    5873U,  // TSUBCCTVrr
473
35.9k
    4670U,  // TSUBCCri
474
35.9k
    4670U,  // TSUBCCrr
475
35.9k
    10136104U,  // TXCCri
476
35.9k
    10136104U,  // TXCCrr
477
35.9k
    4756U,  // UDIVCCri
478
35.9k
    4756U,  // UDIVCCrr
479
35.9k
    6002U,  // UDIVXri
480
35.9k
    6002U,  // UDIVXrr
481
35.9k
    5867U,  // UDIVri
482
35.9k
    5867U,  // UDIVrr
483
35.9k
    4710U,  // UMULCCri
484
35.9k
    4710U,  // UMULCCrr
485
35.9k
    5026U,  // UMULXHI
486
35.9k
    5150U,  // UMULri
487
35.9k
    5150U,  // UMULrr
488
35.9k
    74996U, // UNIMP
489
35.9k
    6300477U, // V9FCMPD
490
35.9k
    6300397U, // V9FCMPED
491
35.9k
    6300942U, // V9FCMPEQ
492
35.9k
    6301251U, // V9FCMPES
493
35.9k
    6301000U, // V9FCMPQ
494
35.9k
    6301309U, // V9FCMPS
495
35.9k
    47614U, // V9FMOVD_FCC
496
35.9k
    47638U, // V9FMOVQ_FCC
497
35.9k
    47650U, // V9FMOVS_FCC
498
35.9k
    47658U, // V9MOVFCCri
499
35.9k
    47658U, // V9MOVFCCrr
500
35.9k
    14689692U,  // WRYri
501
35.9k
    14689692U,  // WRYrr
502
35.9k
    5953U,  // XMULX
503
35.9k
    5035U,  // XMULXHI
504
35.9k
    4733U,  // XNORCCri
505
35.9k
    4733U,  // XNORCCrr
506
35.9k
    5520U,  // XNORXrr
507
35.9k
    5520U,  // XNORri
508
35.9k
    5520U,  // XNORrr
509
35.9k
    4741U,  // XORCCri
510
35.9k
    4741U,  // XORCCrr
511
35.9k
    5527U,  // XORXri
512
35.9k
    5527U,  // XORXrr
513
35.9k
    5527U,  // XORri
514
35.9k
    5527U,  // XORrr
515
35.9k
    0U
516
35.9k
  };
517
518
35.9k
#ifndef CAPSTONE_DIET
519
35.9k
  static const char AsmStrs[] = {
520
35.9k
  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521
35.9k
  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522
35.9k
  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523
35.9k
  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524
35.9k
  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525
35.9k
  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526
35.9k
  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527
35.9k
  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528
35.9k
  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529
35.9k
  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530
35.9k
  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531
35.9k
  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532
35.9k
  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533
35.9k
  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534
35.9k
  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535
35.9k
  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536
35.9k
  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537
35.9k
  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538
35.9k
  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539
35.9k
  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540
35.9k
  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541
35.9k
  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542
35.9k
  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543
35.9k
  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544
35.9k
  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545
35.9k
  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546
35.9k
  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547
35.9k
  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548
35.9k
  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549
35.9k
  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550
35.9k
  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551
35.9k
  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552
35.9k
  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553
35.9k
  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554
35.9k
  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555
35.9k
  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556
35.9k
  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557
35.9k
  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558
35.9k
  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559
35.9k
  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560
35.9k
  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561
35.9k
  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562
35.9k
  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563
35.9k
  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564
35.9k
  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565
35.9k
  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566
35.9k
  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567
35.9k
  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568
35.9k
  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569
35.9k
  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570
35.9k
  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571
35.9k
  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572
35.9k
  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573
35.9k
  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574
35.9k
  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575
35.9k
  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576
35.9k
  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577
35.9k
  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578
35.9k
  /* 542 */ 'b', 'a', 32, 0,
579
35.9k
  /* 546 */ 's', 'r', 'a', 32, 0,
580
35.9k
  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581
35.9k
  /* 563 */ 's', 't', 'b', 32, 0,
582
35.9k
  /* 568 */ 's', 'u', 'b', 32, 0,
583
35.9k
  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584
35.9k
  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585
35.9k
  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586
35.9k
  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587
35.9k
  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588
35.9k
  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589
35.9k
  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590
35.9k
  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591
35.9k
  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592
35.9k
  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593
35.9k
  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594
35.9k
  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595
35.9k
  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596
35.9k
  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597
35.9k
  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598
35.9k
  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599
35.9k
  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600
35.9k
  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601
35.9k
  /* 711 */ 'a', 'd', 'd', 32, 0,
602
35.9k
  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603
35.9k
  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604
35.9k
  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605
35.9k
  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606
35.9k
  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607
35.9k
  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608
35.9k
  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609
35.9k
  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610
35.9k
  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611
35.9k
  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612
35.9k
  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613
35.9k
  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614
35.9k
  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615
35.9k
  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616
35.9k
  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617
35.9k
  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618
35.9k
  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619
35.9k
  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620
35.9k
  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621
35.9k
  /* 858 */ 's', 't', 'd', 32, 0,
622
35.9k
  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623
35.9k
  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624
35.9k
  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625
35.9k
  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626
35.9k
  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627
35.9k
  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628
35.9k
  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629
35.9k
  /* 917 */ 's', 't', 'h', 32, 0,
630
35.9k
  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631
35.9k
  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632
35.9k
  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633
35.9k
  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634
35.9k
  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635
35.9k
  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636
35.9k
  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637
35.9k
  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638
35.9k
  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639
35.9k
  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640
35.9k
  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641
35.9k
  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642
35.9k
  /* 1019 */ 's', 'l', 'l', 32, 0,
643
35.9k
  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644
35.9k
  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645
35.9k
  /* 1042 */ 's', 'r', 'l', 32, 0,
646
35.9k
  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647
35.9k
  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648
35.9k
  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649
35.9k
  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650
35.9k
  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651
35.9k
  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652
35.9k
  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653
35.9k
  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654
35.9k
  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655
35.9k
  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656
35.9k
  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657
35.9k
  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658
35.9k
  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659
35.9k
  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660
35.9k
  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661
35.9k
  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662
35.9k
  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663
35.9k
  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664
35.9k
  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665
35.9k
  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666
35.9k
  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667
35.9k
  /* 1242 */ 'o', 'r', 'n', 32, 0,
668
35.9k
  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669
35.9k
  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670
35.9k
  /* 1262 */ 'c', 'm', 'p', 32, 0,
671
35.9k
  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672
35.9k
  /* 1274 */ 'j', 'm', 'p', 32, 0,
673
35.9k
  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674
35.9k
  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675
35.9k
  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676
35.9k
  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677
35.9k
  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678
35.9k
  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679
35.9k
  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680
35.9k
  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681
35.9k
  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682
35.9k
  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683
35.9k
  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684
35.9k
  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685
35.9k
  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686
35.9k
  /* 1373 */ 's', 't', 'q', 32, 0,
687
35.9k
  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688
35.9k
  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689
35.9k
  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690
35.9k
  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691
35.9k
  /* 1411 */ 'f', 'o', 'r', 32, 0,
692
35.9k
  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693
35.9k
  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694
35.9k
  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695
35.9k
  /* 1435 */ 'w', 'r', 32, 0,
696
35.9k
  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697
35.9k
  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698
35.9k
  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699
35.9k
  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700
35.9k
  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701
35.9k
  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702
35.9k
  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703
35.9k
  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704
35.9k
  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705
35.9k
  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706
35.9k
  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707
35.9k
  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708
35.9k
  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709
35.9k
  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710
35.9k
  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711
35.9k
  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712
35.9k
  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713
35.9k
  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714
35.9k
  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715
35.9k
  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716
35.9k
  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717
35.9k
  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718
35.9k
  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719
35.9k
  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720
35.9k
  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721
35.9k
  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722
35.9k
  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723
35.9k
  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724
35.9k
  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725
35.9k
  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726
35.9k
  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727
35.9k
  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728
35.9k
  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729
35.9k
  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730
35.9k
  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731
35.9k
  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732
35.9k
  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733
35.9k
  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734
35.9k
  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735
35.9k
  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736
35.9k
  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737
35.9k
  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738
35.9k
  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739
35.9k
  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740
35.9k
  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741
35.9k
  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742
35.9k
  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743
35.9k
  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744
35.9k
  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745
35.9k
  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746
35.9k
  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747
35.9k
  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748
35.9k
  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749
35.9k
  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750
35.9k
  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751
35.9k
  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752
35.9k
  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753
35.9k
  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754
35.9k
  /* 1893 */ 's', 't', 'x', 32, 0,
755
35.9k
  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756
35.9k
  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757
35.9k
  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758
35.9k
  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759
35.9k
  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760
35.9k
  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761
35.9k
  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762
35.9k
  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763
35.9k
  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764
35.9k
  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765
35.9k
  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766
35.9k
  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767
35.9k
  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768
35.9k
  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769
35.9k
  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770
35.9k
  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771
35.9k
  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772
35.9k
  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773
35.9k
  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774
35.9k
  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775
35.9k
  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776
35.9k
  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777
35.9k
  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778
35.9k
  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779
35.9k
  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780
35.9k
  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781
35.9k
  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782
35.9k
  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783
35.9k
  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784
35.9k
  /* 2160 */ 'b', 'r', 'z', 32, 0,
785
35.9k
  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786
35.9k
  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787
35.9k
  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788
35.9k
  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789
35.9k
  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790
35.9k
  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791
35.9k
  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792
35.9k
  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793
35.9k
  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794
35.9k
  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795
35.9k
  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796
35.9k
  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797
35.9k
  /* 2421 */ 't', 'a', 32, '3', 0,
798
35.9k
  /* 2426 */ 't', 'a', 32, '5', 0,
799
35.9k
  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800
35.9k
  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801
35.9k
  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802
35.9k
  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803
35.9k
  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804
35.9k
  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805
35.9k
  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806
35.9k
  /* 2496 */ 'l', 'd', 32, '[', 0,
807
35.9k
  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808
35.9k
  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809
35.9k
  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810
35.9k
  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811
35.9k
  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812
35.9k
  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813
35.9k
  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814
35.9k
  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815
35.9k
  /* 2554 */ 'f', 'b', 0,
816
35.9k
  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817
35.9k
  /* 2563 */ 's', 'i', 'a', 'm', 0,
818
35.9k
  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819
35.9k
  /* 2577 */ 'n', 'o', 'p', 0,
820
35.9k
  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821
35.9k
  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822
35.9k
  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823
35.9k
  /* 2599 */ 't', 0,
824
35.9k
  /* 2601 */ 'm', 'o', 'v', 0,
825
35.9k
  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826
35.9k
  };
827
35.9k
#endif
828
829
  // Emit the opcode for the instruction.
830
35.9k
  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831
35.9k
#ifndef CAPSTONE_DIET
832
  // assert(Bits != 0 && "Cannot print this instruction.");
833
35.9k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834
35.9k
#endif
835
836
837
  // Fragment 0 encoded into 4 bits for 12 unique commands.
838
  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839
35.9k
  switch ((Bits >> 12) & 15) {
840
0
  default:   // unreachable.
841
66
  case 0:
842
    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843
66
    return;
844
0
    break;
845
5.41k
  case 1:
846
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847
5.41k
    printOperand(MI, 1, O); 
848
5.41k
    break;
849
21.8k
  case 2:
850
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851
21.8k
    printOperand(MI, 0, O); 
852
21.8k
    break;
853
3.08k
  case 3:
854
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855
3.08k
    printCCOperand(MI, 1, O); 
856
3.08k
    break;
857
78
  case 4:
858
    // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859
78
    printMemOperand(MI, 0, O, NULL); 
860
78
    return;
861
0
    break;
862
2.58k
  case 5:
863
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864
2.58k
    printCCOperand(MI, 3, O); 
865
2.58k
    break;
866
0
  case 6:
867
    // GETPCX
868
0
    printGetPCX(MI, 0, O); 
869
0
    return;
870
0
    break;
871
1.57k
  case 7:
872
    // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873
1.57k
    printMemOperand(MI, 1, O, NULL); 
874
1.57k
    break;
875
0
  case 8:
876
    // LEAX_ADDri, LEA_ADDri
877
0
    printMemOperand(MI, 1, O, "arith"); 
878
0
    SStream_concat0(O, ", "); 
879
0
    printOperand(MI, 0, O); 
880
0
    return;
881
0
    break;
882
479
  case 9:
883
    // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884
479
    printOperand(MI, 2, O); 
885
479
    SStream_concat0(O, ", ["); 
886
479
    printMemOperand(MI, 0, O, NULL); 
887
479
    SStream_concat0(O, "]"); 
888
479
    return;
889
0
    break;
890
403
  case 10:
891
    // TICCri, TICCrr, TXCCri, TXCCrr
892
403
    printCCOperand(MI, 2, O); 
893
403
    break;
894
428
  case 11:
895
    // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896
428
    printCCOperand(MI, 4, O); 
897
428
    SStream_concat0(O, " "); 
898
428
    printOperand(MI, 1, O); 
899
428
    SStream_concat0(O, ", "); 
900
428
    printOperand(MI, 2, O); 
901
428
    SStream_concat0(O, ", "); 
902
428
    printOperand(MI, 0, O); 
903
428
    return;
904
0
    break;
905
35.9k
  }
906
907
908
  // Fragment 1 encoded into 4 bits for 16 unique commands.
909
  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910
34.8k
  switch ((Bits >> 16) & 15) {
911
0
  default:   // unreachable.
912
8.58k
  case 0:
913
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914
8.58k
    SStream_concat0(O, ", "); 
915
8.58k
    break;
916
19.0k
  case 1:
917
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918
19.0k
    return;
919
0
    break;
920
1.31k
  case 2:
921
    // BCOND, BPFCC, FBCOND
922
1.31k
    SStream_concat0(O, " "); 
923
1.31k
    break;
924
681
  case 3:
925
    // BCONDA, BPFCCA, FBCONDA
926
681
    SStream_concat0(O, ",a ");
927
681
  Sparc_add_hint(MI, SPARC_HINT_A);
928
681
    break;
929
0
  case 4:
930
    // BPFCCANT
931
0
    SStream_concat0(O, ",a,pn ");
932
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933
0
    printOperand(MI, 2, O); 
934
0
    SStream_concat0(O, ", "); 
935
0
    printOperand(MI, 0, O); 
936
0
    return;
937
0
    break;
938
0
  case 5:
939
    // BPFCCNT
940
0
    SStream_concat0(O, ",pn ");
941
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
942
0
    printOperand(MI, 2, O); 
943
0
    SStream_concat0(O, ", "); 
944
0
    printOperand(MI, 0, O); 
945
0
    return;
946
0
    break;
947
2.09k
  case 6:
948
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949
2.09k
    SStream_concat0(O, " %icc, ");
950
2.09k
  Sparc_add_reg(MI, SPARC_REG_ICC);
951
2.09k
    break;
952
142
  case 7:
953
    // BPICCA
954
142
    SStream_concat0(O, ",a %icc, ");
955
142
  Sparc_add_hint(MI, SPARC_HINT_A);
956
142
  Sparc_add_reg(MI, SPARC_REG_ICC);
957
142
    printOperand(MI, 0, O); 
958
142
    return;
959
0
    break;
960
0
  case 8:
961
    // BPICCANT
962
0
    SStream_concat0(O, ",a,pn %icc, ");
963
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
965
0
    printOperand(MI, 0, O); 
966
0
    return;
967
0
    break;
968
0
  case 9:
969
    // BPICCNT
970
0
    SStream_concat0(O, ",pn %icc, ");
971
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
972
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
973
0
    printOperand(MI, 0, O); 
974
0
    return;
975
0
    break;
976
838
  case 10:
977
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978
838
    SStream_concat0(O, " %xcc, ");
979
838
  Sparc_add_reg(MI, SPARC_REG_XCC);
980
838
    break;
981
260
  case 11:
982
    // BPXCCA
983
260
    SStream_concat0(O, ",a %xcc, ");
984
260
  Sparc_add_hint(MI, SPARC_HINT_A);
985
260
  Sparc_add_reg(MI, SPARC_REG_XCC);
986
260
    printOperand(MI, 0, O); 
987
260
    return;
988
0
    break;
989
0
  case 12:
990
    // BPXCCANT
991
0
    SStream_concat0(O, ",a,pn %xcc, ");
992
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
994
0
    printOperand(MI, 0, O); 
995
0
    return;
996
0
    break;
997
0
  case 13:
998
    // BPXCCNT
999
0
    SStream_concat0(O, ",pn %xcc, ");
1000
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
1001
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
1002
0
    printOperand(MI, 0, O); 
1003
0
    return;
1004
0
    break;
1005
1.20k
  case 14:
1006
    // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007
1.20k
    SStream_concat0(O, "], "); 
1008
1.20k
    break;
1009
741
  case 15:
1010
    // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011
741
    SStream_concat0(O, " %fcc0, ");
1012
741
  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013
741
    printOperand(MI, 1, O); 
1014
741
    SStream_concat0(O, ", "); 
1015
741
    printOperand(MI, 0, O); 
1016
741
    return;
1017
0
    break;
1018
34.8k
  }
1019
1020
1021
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022
  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023
14.7k
  switch ((Bits >> 20) & 3) {
1024
0
  default:   // unreachable.
1025
4.08k
  case 0:
1026
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027
4.08k
    printOperand(MI, 2, O); 
1028
4.08k
    SStream_concat0(O, ", "); 
1029
4.08k
    printOperand(MI, 0, O); 
1030
4.08k
    break;
1031
5.99k
  case 1:
1032
    // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033
5.99k
    printOperand(MI, 0, O); 
1034
5.99k
    break;
1035
4.63k
  case 2:
1036
    // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037
4.63k
    printOperand(MI, 1, O); 
1038
4.63k
    break;
1039
14.7k
  }
1040
1041
1042
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043
  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044
14.7k
  switch ((Bits >> 22) & 3) {
1045
0
  default:   // unreachable.
1046
11.5k
  case 0:
1047
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048
11.5k
    return;
1049
0
    break;
1050
2.50k
  case 1:
1051
    // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052
2.50k
    SStream_concat0(O, ", "); 
1053
2.50k
    break;
1054
403
  case 2:
1055
    // TICCri, TICCrr, TXCCri, TXCCrr
1056
403
    SStream_concat0(O, " + ");  // qq
1057
403
    printOperand(MI, 1, O); 
1058
403
    return;
1059
0
    break;
1060
303
  case 3:
1061
    // WRYri, WRYrr
1062
303
    SStream_concat0(O, ", %y");
1063
303
  Sparc_add_reg(MI, SPARC_REG_Y);
1064
303
    return;
1065
0
    break;
1066
14.7k
  }
1067
1068
1069
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070
  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071
2.50k
  switch ((Bits >> 24) & 3) {
1072
0
  default:   // unreachable.
1073
658
  case 0:
1074
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075
658
    printOperand(MI, 2, O); 
1076
658
    return;
1077
0
    break;
1078
1.84k
  case 1:
1079
    // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080
1.84k
    printOperand(MI, 0, O); 
1081
1.84k
    return;
1082
0
    break;
1083
0
  case 2:
1084
    // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085
0
    printOperand(MI, 3, O); 
1086
0
    return;
1087
0
    break;
1088
2.50k
  }
1089
2.50k
}
1090
1091
1092
/// getRegisterName - This method is automatically generated by tblgen
1093
/// from the register set description.  This returns the assembler name
1094
/// for the specified register.
1095
static const char *getRegisterName(unsigned RegNo)
1096
41.7k
{
1097
  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098
1099
41.7k
#ifndef CAPSTONE_DIET
1100
41.7k
  static const char AsmStrs[] = {
1101
41.7k
  /* 0 */ 'f', '1', '0', 0,
1102
41.7k
  /* 4 */ 'f', '2', '0', 0,
1103
41.7k
  /* 8 */ 'f', '3', '0', 0,
1104
41.7k
  /* 12 */ 'f', '4', '0', 0,
1105
41.7k
  /* 16 */ 'f', '5', '0', 0,
1106
41.7k
  /* 20 */ 'f', '6', '0', 0,
1107
41.7k
  /* 24 */ 'f', 'c', 'c', '0', 0,
1108
41.7k
  /* 29 */ 'f', '0', 0,
1109
41.7k
  /* 32 */ 'g', '0', 0,
1110
41.7k
  /* 35 */ 'i', '0', 0,
1111
41.7k
  /* 38 */ 'l', '0', 0,
1112
41.7k
  /* 41 */ 'o', '0', 0,
1113
41.7k
  /* 44 */ 'f', '1', '1', 0,
1114
41.7k
  /* 48 */ 'f', '2', '1', 0,
1115
41.7k
  /* 52 */ 'f', '3', '1', 0,
1116
41.7k
  /* 56 */ 'f', 'c', 'c', '1', 0,
1117
41.7k
  /* 61 */ 'f', '1', 0,
1118
41.7k
  /* 64 */ 'g', '1', 0,
1119
41.7k
  /* 67 */ 'i', '1', 0,
1120
41.7k
  /* 70 */ 'l', '1', 0,
1121
41.7k
  /* 73 */ 'o', '1', 0,
1122
41.7k
  /* 76 */ 'f', '1', '2', 0,
1123
41.7k
  /* 80 */ 'f', '2', '2', 0,
1124
41.7k
  /* 84 */ 'f', '3', '2', 0,
1125
41.7k
  /* 88 */ 'f', '4', '2', 0,
1126
41.7k
  /* 92 */ 'f', '5', '2', 0,
1127
41.7k
  /* 96 */ 'f', '6', '2', 0,
1128
41.7k
  /* 100 */ 'f', 'c', 'c', '2', 0,
1129
41.7k
  /* 105 */ 'f', '2', 0,
1130
41.7k
  /* 108 */ 'g', '2', 0,
1131
41.7k
  /* 111 */ 'i', '2', 0,
1132
41.7k
  /* 114 */ 'l', '2', 0,
1133
41.7k
  /* 117 */ 'o', '2', 0,
1134
41.7k
  /* 120 */ 'f', '1', '3', 0,
1135
41.7k
  /* 124 */ 'f', '2', '3', 0,
1136
41.7k
  /* 128 */ 'f', 'c', 'c', '3', 0,
1137
41.7k
  /* 133 */ 'f', '3', 0,
1138
41.7k
  /* 136 */ 'g', '3', 0,
1139
41.7k
  /* 139 */ 'i', '3', 0,
1140
41.7k
  /* 142 */ 'l', '3', 0,
1141
41.7k
  /* 145 */ 'o', '3', 0,
1142
41.7k
  /* 148 */ 'f', '1', '4', 0,
1143
41.7k
  /* 152 */ 'f', '2', '4', 0,
1144
41.7k
  /* 156 */ 'f', '3', '4', 0,
1145
41.7k
  /* 160 */ 'f', '4', '4', 0,
1146
41.7k
  /* 164 */ 'f', '5', '4', 0,
1147
41.7k
  /* 168 */ 'f', '4', 0,
1148
41.7k
  /* 171 */ 'g', '4', 0,
1149
41.7k
  /* 174 */ 'i', '4', 0,
1150
41.7k
  /* 177 */ 'l', '4', 0,
1151
41.7k
  /* 180 */ 'o', '4', 0,
1152
41.7k
  /* 183 */ 'f', '1', '5', 0,
1153
41.7k
  /* 187 */ 'f', '2', '5', 0,
1154
41.7k
  /* 191 */ 'f', '5', 0,
1155
41.7k
  /* 194 */ 'g', '5', 0,
1156
41.7k
  /* 197 */ 'i', '5', 0,
1157
41.7k
  /* 200 */ 'l', '5', 0,
1158
41.7k
  /* 203 */ 'o', '5', 0,
1159
41.7k
  /* 206 */ 'f', '1', '6', 0,
1160
41.7k
  /* 210 */ 'f', '2', '6', 0,
1161
41.7k
  /* 214 */ 'f', '3', '6', 0,
1162
41.7k
  /* 218 */ 'f', '4', '6', 0,
1163
41.7k
  /* 222 */ 'f', '5', '6', 0,
1164
41.7k
  /* 226 */ 'f', '6', 0,
1165
41.7k
  /* 229 */ 'g', '6', 0,
1166
41.7k
  /* 232 */ 'l', '6', 0,
1167
41.7k
  /* 235 */ 'f', '1', '7', 0,
1168
41.7k
  /* 239 */ 'f', '2', '7', 0,
1169
41.7k
  /* 243 */ 'f', '7', 0,
1170
41.7k
  /* 246 */ 'g', '7', 0,
1171
41.7k
  /* 249 */ 'i', '7', 0,
1172
41.7k
  /* 252 */ 'l', '7', 0,
1173
41.7k
  /* 255 */ 'o', '7', 0,
1174
41.7k
  /* 258 */ 'f', '1', '8', 0,
1175
41.7k
  /* 262 */ 'f', '2', '8', 0,
1176
41.7k
  /* 266 */ 'f', '3', '8', 0,
1177
41.7k
  /* 270 */ 'f', '4', '8', 0,
1178
41.7k
  /* 274 */ 'f', '5', '8', 0,
1179
41.7k
  /* 278 */ 'f', '8', 0,
1180
41.7k
  /* 281 */ 'f', '1', '9', 0,
1181
41.7k
  /* 285 */ 'f', '2', '9', 0,
1182
41.7k
  /* 289 */ 'f', '9', 0,
1183
41.7k
  /* 292 */ 'i', 'c', 'c', 0,
1184
41.7k
  /* 296 */ 'f', 'p', 0,
1185
41.7k
  /* 299 */ 's', 'p', 0,
1186
41.7k
  /* 302 */ 'y', 0,
1187
41.7k
  };
1188
1189
41.7k
  static const uint16_t RegAsmOffset[] = {
1190
41.7k
    292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 
1191
41.7k
    152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 
1192
41.7k
    92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 
1193
41.7k
    278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 
1194
41.7k
    80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 
1195
41.7k
    32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 
1196
41.7k
    296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 
1197
41.7k
    180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 
1198
41.7k
    12, 160, 270, 92, 222, 20, 
1199
41.7k
  };
1200
1201
  //int i;
1202
  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203
  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204
  //printf("*************************\n");
1205
41.7k
  return AsmStrs+RegAsmOffset[RegNo-1];
1206
#else
1207
  return NULL;
1208
#endif
1209
41.7k
}
1210
1211
#ifdef PRINT_ALIAS_INSTR
1212
#undef PRINT_ALIAS_INSTR
1213
1214
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1215
  unsigned PrintMethodIdx, SStream *OS)
1216
0
{
1217
0
}
1218
1219
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1220
60.6k
{
1221
276k
  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1222
60.6k
  const char *AsmString;
1223
60.6k
  char *tmp, *AsmMnem, *AsmOps, *c;
1224
60.6k
  int OpIdx, PrintMethodIdx;
1225
60.6k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1226
60.6k
  switch (MCInst_getOpcode(MI)) {
1227
33.5k
  default: return NULL;
1228
2.01k
  case SP_BCOND:
1229
2.01k
    if (MCInst_getNumOperands(MI) == 2 &&
1230
2.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1231
2.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1232
      // (BCOND brtarget:$imm, 8)
1233
0
      AsmString = "ba $\x01";
1234
0
      break;
1235
0
    }
1236
2.01k
    if (MCInst_getNumOperands(MI) == 2 &&
1237
2.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1238
2.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1239
      // (BCOND brtarget:$imm, 0)
1240
451
      AsmString = "bn $\x01";
1241
451
      break;
1242
451
    }
1243
1.56k
    if (MCInst_getNumOperands(MI) == 2 &&
1244
1.56k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1245
1.56k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1246
      // (BCOND brtarget:$imm, 9)
1247
53
      AsmString = "bne $\x01";
1248
53
      break;
1249
53
    }
1250
1.50k
    if (MCInst_getNumOperands(MI) == 2 &&
1251
1.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1252
1.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1253
      // (BCOND brtarget:$imm, 1)
1254
42
      AsmString = "be $\x01";
1255
42
      break;
1256
42
    }
1257
1.46k
    if (MCInst_getNumOperands(MI) == 2 &&
1258
1.46k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1259
1.46k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1260
      // (BCOND brtarget:$imm, 10)
1261
243
      AsmString = "bg $\x01";
1262
243
      break;
1263
243
    }
1264
1.22k
    if (MCInst_getNumOperands(MI) == 2 &&
1265
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1266
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1267
      // (BCOND brtarget:$imm, 2)
1268
210
      AsmString = "ble $\x01";
1269
210
      break;
1270
210
    }
1271
1.01k
    if (MCInst_getNumOperands(MI) == 2 &&
1272
1.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1273
1.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1274
      // (BCOND brtarget:$imm, 11)
1275
8
      AsmString = "bge $\x01";
1276
8
      break;
1277
8
    }
1278
1.00k
    if (MCInst_getNumOperands(MI) == 2 &&
1279
1.00k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1280
1.00k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1281
      // (BCOND brtarget:$imm, 3)
1282
217
      AsmString = "bl $\x01";
1283
217
      break;
1284
217
    }
1285
788
    if (MCInst_getNumOperands(MI) == 2 &&
1286
788
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1287
788
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1288
      // (BCOND brtarget:$imm, 12)
1289
96
      AsmString = "bgu $\x01";
1290
96
      break;
1291
96
    }
1292
692
    if (MCInst_getNumOperands(MI) == 2 &&
1293
692
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1294
692
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1295
      // (BCOND brtarget:$imm, 4)
1296
171
      AsmString = "bleu $\x01";
1297
171
      break;
1298
171
    }
1299
521
    if (MCInst_getNumOperands(MI) == 2 &&
1300
521
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1301
521
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1302
      // (BCOND brtarget:$imm, 13)
1303
37
      AsmString = "bcc $\x01";
1304
37
      break;
1305
37
    }
1306
484
    if (MCInst_getNumOperands(MI) == 2 &&
1307
484
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1308
484
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1309
      // (BCOND brtarget:$imm, 5)
1310
46
      AsmString = "bcs $\x01";
1311
46
      break;
1312
46
    }
1313
438
    if (MCInst_getNumOperands(MI) == 2 &&
1314
438
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1315
438
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1316
      // (BCOND brtarget:$imm, 14)
1317
69
      AsmString = "bpos $\x01";
1318
69
      break;
1319
69
    }
1320
369
    if (MCInst_getNumOperands(MI) == 2 &&
1321
369
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1322
369
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1323
      // (BCOND brtarget:$imm, 6)
1324
184
      AsmString = "bneg $\x01";
1325
184
      break;
1326
184
    }
1327
185
    if (MCInst_getNumOperands(MI) == 2 &&
1328
185
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1329
185
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1330
      // (BCOND brtarget:$imm, 15)
1331
10
      AsmString = "bvc $\x01";
1332
10
      break;
1333
10
    }
1334
175
    if (MCInst_getNumOperands(MI) == 2 &&
1335
175
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1336
175
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1337
      // (BCOND brtarget:$imm, 7)
1338
175
      AsmString = "bvs $\x01";
1339
175
      break;
1340
175
    }
1341
0
    return NULL;
1342
1.84k
  case SP_BCONDA:
1343
1.84k
    if (MCInst_getNumOperands(MI) == 2 &&
1344
1.84k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1345
1.84k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1346
      // (BCONDA brtarget:$imm, 8)
1347
502
      AsmString = "ba,a $\x01";
1348
502
      break;
1349
502
    }
1350
1.33k
    if (MCInst_getNumOperands(MI) == 2 &&
1351
1.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1352
1.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1353
      // (BCONDA brtarget:$imm, 0)
1354
213
      AsmString = "bn,a $\x01";
1355
213
      break;
1356
213
    }
1357
1.12k
    if (MCInst_getNumOperands(MI) == 2 &&
1358
1.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1359
1.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1360
      // (BCONDA brtarget:$imm, 9)
1361
61
      AsmString = "bne,a $\x01";
1362
61
      break;
1363
61
    }
1364
1.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1365
1.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1366
1.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1367
      // (BCONDA brtarget:$imm, 1)
1368
36
      AsmString = "be,a $\x01";
1369
36
      break;
1370
36
    }
1371
1.02k
    if (MCInst_getNumOperands(MI) == 2 &&
1372
1.02k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1373
1.02k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1374
      // (BCONDA brtarget:$imm, 10)
1375
245
      AsmString = "bg,a $\x01";
1376
245
      break;
1377
245
    }
1378
784
    if (MCInst_getNumOperands(MI) == 2 &&
1379
784
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1380
784
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1381
      // (BCONDA brtarget:$imm, 2)
1382
32
      AsmString = "ble,a $\x01";
1383
32
      break;
1384
32
    }
1385
752
    if (MCInst_getNumOperands(MI) == 2 &&
1386
752
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1387
752
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1388
      // (BCONDA brtarget:$imm, 11)
1389
11
      AsmString = "bge,a $\x01";
1390
11
      break;
1391
11
    }
1392
741
    if (MCInst_getNumOperands(MI) == 2 &&
1393
741
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1394
741
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1395
      // (BCONDA brtarget:$imm, 3)
1396
23
      AsmString = "bl,a $\x01";
1397
23
      break;
1398
23
    }
1399
718
    if (MCInst_getNumOperands(MI) == 2 &&
1400
718
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1401
718
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1402
      // (BCONDA brtarget:$imm, 12)
1403
74
      AsmString = "bgu,a $\x01";
1404
74
      break;
1405
74
    }
1406
644
    if (MCInst_getNumOperands(MI) == 2 &&
1407
644
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1408
644
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1409
      // (BCONDA brtarget:$imm, 4)
1410
138
      AsmString = "bleu,a $\x01";
1411
138
      break;
1412
138
    }
1413
506
    if (MCInst_getNumOperands(MI) == 2 &&
1414
506
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1415
506
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1416
      // (BCONDA brtarget:$imm, 13)
1417
160
      AsmString = "bcc,a $\x01";
1418
160
      break;
1419
160
    }
1420
346
    if (MCInst_getNumOperands(MI) == 2 &&
1421
346
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1422
346
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1423
      // (BCONDA brtarget:$imm, 5)
1424
50
      AsmString = "bcs,a $\x01";
1425
50
      break;
1426
50
    }
1427
296
    if (MCInst_getNumOperands(MI) == 2 &&
1428
296
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1429
296
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1430
      // (BCONDA brtarget:$imm, 14)
1431
65
      AsmString = "bpos,a $\x01";
1432
65
      break;
1433
65
    }
1434
231
    if (MCInst_getNumOperands(MI) == 2 &&
1435
231
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1436
231
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1437
      // (BCONDA brtarget:$imm, 6)
1438
44
      AsmString = "bneg,a $\x01";
1439
44
      break;
1440
44
    }
1441
187
    if (MCInst_getNumOperands(MI) == 2 &&
1442
187
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1443
187
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1444
      // (BCONDA brtarget:$imm, 15)
1445
120
      AsmString = "bvc,a $\x01";
1446
120
      break;
1447
120
    }
1448
67
    if (MCInst_getNumOperands(MI) == 2 &&
1449
67
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1450
67
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1451
      // (BCONDA brtarget:$imm, 7)
1452
67
      AsmString = "bvs,a $\x01";
1453
67
      break;
1454
67
    }
1455
0
    return NULL;
1456
2.97k
  case SP_BPFCCANT:
1457
2.97k
    if (MCInst_getNumOperands(MI) == 3 &&
1458
2.97k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1459
2.97k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1460
2.97k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1461
2.97k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1462
      // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1463
161
      AsmString = "fba,a,pn $\x03, $\x01";
1464
161
      break;
1465
161
    }
1466
2.81k
    if (MCInst_getNumOperands(MI) == 3 &&
1467
2.81k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1468
2.81k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1469
2.81k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1470
2.81k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1471
      // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1472
214
      AsmString = "fbn,a,pn $\x03, $\x01";
1473
214
      break;
1474
214
    }
1475
2.60k
    if (MCInst_getNumOperands(MI) == 3 &&
1476
2.60k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1477
2.60k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1478
2.60k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1479
2.60k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1480
      // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1481
465
      AsmString = "fbu,a,pn $\x03, $\x01";
1482
465
      break;
1483
465
    }
1484
2.13k
    if (MCInst_getNumOperands(MI) == 3 &&
1485
2.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1486
2.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1487
2.13k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1488
2.13k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1489
      // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1490
87
      AsmString = "fbg,a,pn $\x03, $\x01";
1491
87
      break;
1492
87
    }
1493
2.05k
    if (MCInst_getNumOperands(MI) == 3 &&
1494
2.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1495
2.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1496
2.05k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1497
2.05k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1498
      // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1499
86
      AsmString = "fbug,a,pn $\x03, $\x01";
1500
86
      break;
1501
86
    }
1502
1.96k
    if (MCInst_getNumOperands(MI) == 3 &&
1503
1.96k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1504
1.96k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1505
1.96k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1506
1.96k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1507
      // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1508
82
      AsmString = "fbl,a,pn $\x03, $\x01";
1509
82
      break;
1510
82
    }
1511
1.88k
    if (MCInst_getNumOperands(MI) == 3 &&
1512
1.88k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1513
1.88k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1514
1.88k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1515
1.88k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1516
      // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1517
76
      AsmString = "fbul,a,pn $\x03, $\x01";
1518
76
      break;
1519
76
    }
1520
1.80k
    if (MCInst_getNumOperands(MI) == 3 &&
1521
1.80k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1522
1.80k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1523
1.80k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1524
1.80k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1525
      // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1526
211
      AsmString = "fblg,a,pn $\x03, $\x01";
1527
211
      break;
1528
211
    }
1529
1.59k
    if (MCInst_getNumOperands(MI) == 3 &&
1530
1.59k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1531
1.59k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1532
1.59k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1533
1.59k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1534
      // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1535
206
      AsmString = "fbne,a,pn $\x03, $\x01";
1536
206
      break;
1537
206
    }
1538
1.39k
    if (MCInst_getNumOperands(MI) == 3 &&
1539
1.39k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1540
1.39k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1541
1.39k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1542
1.39k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1543
      // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1544
168
      AsmString = "fbe,a,pn $\x03, $\x01";
1545
168
      break;
1546
168
    }
1547
1.22k
    if (MCInst_getNumOperands(MI) == 3 &&
1548
1.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1549
1.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1550
1.22k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1551
1.22k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1552
      // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1553
220
      AsmString = "fbue,a,pn $\x03, $\x01";
1554
220
      break;
1555
220
    }
1556
1.00k
    if (MCInst_getNumOperands(MI) == 3 &&
1557
1.00k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1558
1.00k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1559
1.00k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1560
1.00k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1561
      // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1562
150
      AsmString = "fbge,a,pn $\x03, $\x01";
1563
150
      break;
1564
150
    }
1565
853
    if (MCInst_getNumOperands(MI) == 3 &&
1566
853
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1567
853
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1568
853
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1569
853
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1570
      // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1571
143
      AsmString = "fbuge,a,pn $\x03, $\x01";
1572
143
      break;
1573
143
    }
1574
710
    if (MCInst_getNumOperands(MI) == 3 &&
1575
710
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1576
710
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1577
710
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1578
710
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1579
      // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1580
61
      AsmString = "fble,a,pn $\x03, $\x01";
1581
61
      break;
1582
61
    }
1583
649
    if (MCInst_getNumOperands(MI) == 3 &&
1584
649
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1585
649
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1586
649
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1587
649
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1588
      // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1589
567
      AsmString = "fbule,a,pn $\x03, $\x01";
1590
567
      break;
1591
567
    }
1592
82
    if (MCInst_getNumOperands(MI) == 3 &&
1593
82
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1594
82
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1595
82
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1596
82
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1597
      // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1598
82
      AsmString = "fbo,a,pn $\x03, $\x01";
1599
82
      break;
1600
82
    }
1601
0
    return NULL;
1602
2.14k
  case SP_BPFCCNT:
1603
2.14k
    if (MCInst_getNumOperands(MI) == 3 &&
1604
2.14k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1605
2.14k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1606
2.14k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1607
2.14k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1608
      // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1609
110
      AsmString = "fba,pn $\x03, $\x01";
1610
110
      break;
1611
110
    }
1612
2.03k
    if (MCInst_getNumOperands(MI) == 3 &&
1613
2.03k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1614
2.03k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1615
2.03k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1616
2.03k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1617
      // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1618
215
      AsmString = "fbn,pn $\x03, $\x01";
1619
215
      break;
1620
215
    }
1621
1.81k
    if (MCInst_getNumOperands(MI) == 3 &&
1622
1.81k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
1.81k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1624
1.81k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1625
1.81k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1626
      // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1627
49
      AsmString = "fbu,pn $\x03, $\x01";
1628
49
      break;
1629
49
    }
1630
1.76k
    if (MCInst_getNumOperands(MI) == 3 &&
1631
1.76k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1632
1.76k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1633
1.76k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1634
1.76k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1635
      // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1636
47
      AsmString = "fbg,pn $\x03, $\x01";
1637
47
      break;
1638
47
    }
1639
1.72k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
1.72k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1641
1.72k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1642
1.72k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1643
1.72k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1644
      // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1645
51
      AsmString = "fbug,pn $\x03, $\x01";
1646
51
      break;
1647
51
    }
1648
1.67k
    if (MCInst_getNumOperands(MI) == 3 &&
1649
1.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1650
1.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1651
1.67k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1652
1.67k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1653
      // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1654
226
      AsmString = "fbl,pn $\x03, $\x01";
1655
226
      break;
1656
226
    }
1657
1.44k
    if (MCInst_getNumOperands(MI) == 3 &&
1658
1.44k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1659
1.44k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1660
1.44k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1661
1.44k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1662
      // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1663
75
      AsmString = "fbul,pn $\x03, $\x01";
1664
75
      break;
1665
75
    }
1666
1.36k
    if (MCInst_getNumOperands(MI) == 3 &&
1667
1.36k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1668
1.36k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1669
1.36k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1670
1.36k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1671
      // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1672
349
      AsmString = "fblg,pn $\x03, $\x01";
1673
349
      break;
1674
349
    }
1675
1.02k
    if (MCInst_getNumOperands(MI) == 3 &&
1676
1.02k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1677
1.02k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1678
1.02k
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1679
1.02k
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1680
      // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1681
124
      AsmString = "fbne,pn $\x03, $\x01";
1682
124
      break;
1683
124
    }
1684
896
    if (MCInst_getNumOperands(MI) == 3 &&
1685
896
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1686
896
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1687
896
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1688
896
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1689
      // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1690
17
      AsmString = "fbe,pn $\x03, $\x01";
1691
17
      break;
1692
17
    }
1693
879
    if (MCInst_getNumOperands(MI) == 3 &&
1694
879
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1695
879
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1696
879
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1697
879
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1698
      // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1699
377
      AsmString = "fbue,pn $\x03, $\x01";
1700
377
      break;
1701
377
    }
1702
502
    if (MCInst_getNumOperands(MI) == 3 &&
1703
502
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1704
502
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1705
502
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1706
502
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1707
      // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1708
36
      AsmString = "fbge,pn $\x03, $\x01";
1709
36
      break;
1710
36
    }
1711
466
    if (MCInst_getNumOperands(MI) == 3 &&
1712
466
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1713
466
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1714
466
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1715
466
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1716
      // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1717
114
      AsmString = "fbuge,pn $\x03, $\x01";
1718
114
      break;
1719
114
    }
1720
352
    if (MCInst_getNumOperands(MI) == 3 &&
1721
352
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1722
352
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1723
352
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1724
352
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1725
      // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1726
33
      AsmString = "fble,pn $\x03, $\x01";
1727
33
      break;
1728
33
    }
1729
319
    if (MCInst_getNumOperands(MI) == 3 &&
1730
319
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1731
319
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1732
319
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1733
319
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1734
      // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1735
36
      AsmString = "fbule,pn $\x03, $\x01";
1736
36
      break;
1737
36
    }
1738
283
    if (MCInst_getNumOperands(MI) == 3 &&
1739
283
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1740
283
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1741
283
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1742
283
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1743
      // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1744
283
      AsmString = "fbo,pn $\x03, $\x01";
1745
283
      break;
1746
283
    }
1747
0
    return NULL;
1748
2.04k
  case SP_BPICCANT:
1749
2.04k
    if (MCInst_getNumOperands(MI) == 2 &&
1750
2.04k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1751
2.04k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1752
      // (BPICCANT brtarget:$imm, 8)
1753
516
      AsmString = "ba,a,pn %icc, $\x01";
1754
516
      break;
1755
516
    }
1756
1.52k
    if (MCInst_getNumOperands(MI) == 2 &&
1757
1.52k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
1.52k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1759
      // (BPICCANT brtarget:$imm, 0)
1760
257
      AsmString = "bn,a,pn %icc, $\x01";
1761
257
      break;
1762
257
    }
1763
1.27k
    if (MCInst_getNumOperands(MI) == 2 &&
1764
1.27k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1765
1.27k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1766
      // (BPICCANT brtarget:$imm, 9)
1767
132
      AsmString = "bne,a,pn %icc, $\x01";
1768
132
      break;
1769
132
    }
1770
1.13k
    if (MCInst_getNumOperands(MI) == 2 &&
1771
1.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1772
1.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1773
      // (BPICCANT brtarget:$imm, 1)
1774
41
      AsmString = "be,a,pn %icc, $\x01";
1775
41
      break;
1776
41
    }
1777
1.09k
    if (MCInst_getNumOperands(MI) == 2 &&
1778
1.09k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1779
1.09k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1780
      // (BPICCANT brtarget:$imm, 10)
1781
188
      AsmString = "bg,a,pn %icc, $\x01";
1782
188
      break;
1783
188
    }
1784
909
    if (MCInst_getNumOperands(MI) == 2 &&
1785
909
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1786
909
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1787
      // (BPICCANT brtarget:$imm, 2)
1788
77
      AsmString = "ble,a,pn %icc, $\x01";
1789
77
      break;
1790
77
    }
1791
832
    if (MCInst_getNumOperands(MI) == 2 &&
1792
832
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1793
832
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1794
      // (BPICCANT brtarget:$imm, 11)
1795
62
      AsmString = "bge,a,pn %icc, $\x01";
1796
62
      break;
1797
62
    }
1798
770
    if (MCInst_getNumOperands(MI) == 2 &&
1799
770
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1800
770
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1801
      // (BPICCANT brtarget:$imm, 3)
1802
16
      AsmString = "bl,a,pn %icc, $\x01";
1803
16
      break;
1804
16
    }
1805
754
    if (MCInst_getNumOperands(MI) == 2 &&
1806
754
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1807
754
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1808
      // (BPICCANT brtarget:$imm, 12)
1809
22
      AsmString = "bgu,a,pn %icc, $\x01";
1810
22
      break;
1811
22
    }
1812
732
    if (MCInst_getNumOperands(MI) == 2 &&
1813
732
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1814
732
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1815
      // (BPICCANT brtarget:$imm, 4)
1816
368
      AsmString = "bleu,a,pn %icc, $\x01";
1817
368
      break;
1818
368
    }
1819
364
    if (MCInst_getNumOperands(MI) == 2 &&
1820
364
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1821
364
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1822
      // (BPICCANT brtarget:$imm, 13)
1823
19
      AsmString = "bcc,a,pn %icc, $\x01";
1824
19
      break;
1825
19
    }
1826
345
    if (MCInst_getNumOperands(MI) == 2 &&
1827
345
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1828
345
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1829
      // (BPICCANT brtarget:$imm, 5)
1830
68
      AsmString = "bcs,a,pn %icc, $\x01";
1831
68
      break;
1832
68
    }
1833
277
    if (MCInst_getNumOperands(MI) == 2 &&
1834
277
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1835
277
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1836
      // (BPICCANT brtarget:$imm, 14)
1837
81
      AsmString = "bpos,a,pn %icc, $\x01";
1838
81
      break;
1839
81
    }
1840
196
    if (MCInst_getNumOperands(MI) == 2 &&
1841
196
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1842
196
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1843
      // (BPICCANT brtarget:$imm, 6)
1844
18
      AsmString = "bneg,a,pn %icc, $\x01";
1845
18
      break;
1846
18
    }
1847
178
    if (MCInst_getNumOperands(MI) == 2 &&
1848
178
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1849
178
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1850
      // (BPICCANT brtarget:$imm, 15)
1851
24
      AsmString = "bvc,a,pn %icc, $\x01";
1852
24
      break;
1853
24
    }
1854
154
    if (MCInst_getNumOperands(MI) == 2 &&
1855
154
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1856
154
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1857
      // (BPICCANT brtarget:$imm, 7)
1858
154
      AsmString = "bvs,a,pn %icc, $\x01";
1859
154
      break;
1860
154
    }
1861
0
    return NULL;
1862
2.61k
  case SP_BPICCNT:
1863
2.61k
    if (MCInst_getNumOperands(MI) == 2 &&
1864
2.61k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1865
2.61k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1866
      // (BPICCNT brtarget:$imm, 8)
1867
61
      AsmString = "ba,pn %icc, $\x01";
1868
61
      break;
1869
61
    }
1870
2.55k
    if (MCInst_getNumOperands(MI) == 2 &&
1871
2.55k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1872
2.55k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1873
      // (BPICCNT brtarget:$imm, 0)
1874
219
      AsmString = "bn,pn %icc, $\x01";
1875
219
      break;
1876
219
    }
1877
2.33k
    if (MCInst_getNumOperands(MI) == 2 &&
1878
2.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1879
2.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1880
      // (BPICCNT brtarget:$imm, 9)
1881
181
      AsmString = "bne,pn %icc, $\x01";
1882
181
      break;
1883
181
    }
1884
2.15k
    if (MCInst_getNumOperands(MI) == 2 &&
1885
2.15k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1886
2.15k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1887
      // (BPICCNT brtarget:$imm, 1)
1888
844
      AsmString = "be,pn %icc, $\x01";
1889
844
      break;
1890
844
    }
1891
1.30k
    if (MCInst_getNumOperands(MI) == 2 &&
1892
1.30k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1893
1.30k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1894
      // (BPICCNT brtarget:$imm, 10)
1895
30
      AsmString = "bg,pn %icc, $\x01";
1896
30
      break;
1897
30
    }
1898
1.27k
    if (MCInst_getNumOperands(MI) == 2 &&
1899
1.27k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1900
1.27k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1901
      // (BPICCNT brtarget:$imm, 2)
1902
94
      AsmString = "ble,pn %icc, $\x01";
1903
94
      break;
1904
94
    }
1905
1.18k
    if (MCInst_getNumOperands(MI) == 2 &&
1906
1.18k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1907
1.18k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1908
      // (BPICCNT brtarget:$imm, 11)
1909
74
      AsmString = "bge,pn %icc, $\x01";
1910
74
      break;
1911
74
    }
1912
1.10k
    if (MCInst_getNumOperands(MI) == 2 &&
1913
1.10k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1914
1.10k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1915
      // (BPICCNT brtarget:$imm, 3)
1916
46
      AsmString = "bl,pn %icc, $\x01";
1917
46
      break;
1918
46
    }
1919
1.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1920
1.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1921
1.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1922
      // (BPICCNT brtarget:$imm, 12)
1923
7
      AsmString = "bgu,pn %icc, $\x01";
1924
7
      break;
1925
7
    }
1926
1.05k
    if (MCInst_getNumOperands(MI) == 2 &&
1927
1.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1928
1.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1929
      // (BPICCNT brtarget:$imm, 4)
1930
281
      AsmString = "bleu,pn %icc, $\x01";
1931
281
      break;
1932
281
    }
1933
775
    if (MCInst_getNumOperands(MI) == 2 &&
1934
775
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1935
775
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1936
      // (BPICCNT brtarget:$imm, 13)
1937
77
      AsmString = "bcc,pn %icc, $\x01";
1938
77
      break;
1939
77
    }
1940
698
    if (MCInst_getNumOperands(MI) == 2 &&
1941
698
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1942
698
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1943
      // (BPICCNT brtarget:$imm, 5)
1944
56
      AsmString = "bcs,pn %icc, $\x01";
1945
56
      break;
1946
56
    }
1947
642
    if (MCInst_getNumOperands(MI) == 2 &&
1948
642
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1949
642
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1950
      // (BPICCNT brtarget:$imm, 14)
1951
22
      AsmString = "bpos,pn %icc, $\x01";
1952
22
      break;
1953
22
    }
1954
620
    if (MCInst_getNumOperands(MI) == 2 &&
1955
620
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1956
620
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1957
      // (BPICCNT brtarget:$imm, 6)
1958
92
      AsmString = "bneg,pn %icc, $\x01";
1959
92
      break;
1960
92
    }
1961
528
    if (MCInst_getNumOperands(MI) == 2 &&
1962
528
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1963
528
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1964
      // (BPICCNT brtarget:$imm, 15)
1965
195
      AsmString = "bvc,pn %icc, $\x01";
1966
195
      break;
1967
195
    }
1968
333
    if (MCInst_getNumOperands(MI) == 2 &&
1969
333
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1970
333
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1971
      // (BPICCNT brtarget:$imm, 7)
1972
333
      AsmString = "bvs,pn %icc, $\x01";
1973
333
      break;
1974
333
    }
1975
0
    return NULL;
1976
1.41k
  case SP_BPXCCANT:
1977
1.41k
    if (MCInst_getNumOperands(MI) == 2 &&
1978
1.41k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1979
1.41k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1980
      // (BPXCCANT brtarget:$imm, 8)
1981
280
      AsmString = "ba,a,pn %xcc, $\x01";
1982
280
      break;
1983
280
    }
1984
1.13k
    if (MCInst_getNumOperands(MI) == 2 &&
1985
1.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1986
1.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1987
      // (BPXCCANT brtarget:$imm, 0)
1988
39
      AsmString = "bn,a,pn %xcc, $\x01";
1989
39
      break;
1990
39
    }
1991
1.10k
    if (MCInst_getNumOperands(MI) == 2 &&
1992
1.10k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1993
1.10k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1994
      // (BPXCCANT brtarget:$imm, 9)
1995
92
      AsmString = "bne,a,pn %xcc, $\x01";
1996
92
      break;
1997
92
    }
1998
1.00k
    if (MCInst_getNumOperands(MI) == 2 &&
1999
1.00k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2000
1.00k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2001
      // (BPXCCANT brtarget:$imm, 1)
2002
95
      AsmString = "be,a,pn %xcc, $\x01";
2003
95
      break;
2004
95
    }
2005
913
    if (MCInst_getNumOperands(MI) == 2 &&
2006
913
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2007
913
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2008
      // (BPXCCANT brtarget:$imm, 10)
2009
78
      AsmString = "bg,a,pn %xcc, $\x01";
2010
78
      break;
2011
78
    }
2012
835
    if (MCInst_getNumOperands(MI) == 2 &&
2013
835
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2014
835
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2015
      // (BPXCCANT brtarget:$imm, 2)
2016
153
      AsmString = "ble,a,pn %xcc, $\x01";
2017
153
      break;
2018
153
    }
2019
682
    if (MCInst_getNumOperands(MI) == 2 &&
2020
682
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2021
682
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2022
      // (BPXCCANT brtarget:$imm, 11)
2023
44
      AsmString = "bge,a,pn %xcc, $\x01";
2024
44
      break;
2025
44
    }
2026
638
    if (MCInst_getNumOperands(MI) == 2 &&
2027
638
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2028
638
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2029
      // (BPXCCANT brtarget:$imm, 3)
2030
78
      AsmString = "bl,a,pn %xcc, $\x01";
2031
78
      break;
2032
78
    }
2033
560
    if (MCInst_getNumOperands(MI) == 2 &&
2034
560
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2035
560
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2036
      // (BPXCCANT brtarget:$imm, 12)
2037
28
      AsmString = "bgu,a,pn %xcc, $\x01";
2038
28
      break;
2039
28
    }
2040
532
    if (MCInst_getNumOperands(MI) == 2 &&
2041
532
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2042
532
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2043
      // (BPXCCANT brtarget:$imm, 4)
2044
113
      AsmString = "bleu,a,pn %xcc, $\x01";
2045
113
      break;
2046
113
    }
2047
419
    if (MCInst_getNumOperands(MI) == 2 &&
2048
419
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2049
419
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2050
      // (BPXCCANT brtarget:$imm, 13)
2051
16
      AsmString = "bcc,a,pn %xcc, $\x01";
2052
16
      break;
2053
16
    }
2054
403
    if (MCInst_getNumOperands(MI) == 2 &&
2055
403
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2056
403
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2057
      // (BPXCCANT brtarget:$imm, 5)
2058
25
      AsmString = "bcs,a,pn %xcc, $\x01";
2059
25
      break;
2060
25
    }
2061
378
    if (MCInst_getNumOperands(MI) == 2 &&
2062
378
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2063
378
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2064
      // (BPXCCANT brtarget:$imm, 14)
2065
26
      AsmString = "bpos,a,pn %xcc, $\x01";
2066
26
      break;
2067
26
    }
2068
352
    if (MCInst_getNumOperands(MI) == 2 &&
2069
352
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2070
352
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2071
      // (BPXCCANT brtarget:$imm, 6)
2072
35
      AsmString = "bneg,a,pn %xcc, $\x01";
2073
35
      break;
2074
35
    }
2075
317
    if (MCInst_getNumOperands(MI) == 2 &&
2076
317
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2077
317
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2078
      // (BPXCCANT brtarget:$imm, 15)
2079
180
      AsmString = "bvc,a,pn %xcc, $\x01";
2080
180
      break;
2081
180
    }
2082
137
    if (MCInst_getNumOperands(MI) == 2 &&
2083
137
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2084
137
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2085
      // (BPXCCANT brtarget:$imm, 7)
2086
137
      AsmString = "bvs,a,pn %xcc, $\x01";
2087
137
      break;
2088
137
    }
2089
0
    return NULL;
2090
2.34k
  case SP_BPXCCNT:
2091
2.34k
    if (MCInst_getNumOperands(MI) == 2 &&
2092
2.34k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2093
2.34k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2094
      // (BPXCCNT brtarget:$imm, 8)
2095
174
      AsmString = "ba,pn %xcc, $\x01";
2096
174
      break;
2097
174
    }
2098
2.17k
    if (MCInst_getNumOperands(MI) == 2 &&
2099
2.17k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2100
2.17k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2101
      // (BPXCCNT brtarget:$imm, 0)
2102
410
      AsmString = "bn,pn %xcc, $\x01";
2103
410
      break;
2104
410
    }
2105
1.76k
    if (MCInst_getNumOperands(MI) == 2 &&
2106
1.76k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2107
1.76k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2108
      // (BPXCCNT brtarget:$imm, 9)
2109
5
      AsmString = "bne,pn %xcc, $\x01";
2110
5
      break;
2111
5
    }
2112
1.75k
    if (MCInst_getNumOperands(MI) == 2 &&
2113
1.75k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2114
1.75k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2115
      // (BPXCCNT brtarget:$imm, 1)
2116
20
      AsmString = "be,pn %xcc, $\x01";
2117
20
      break;
2118
20
    }
2119
1.73k
    if (MCInst_getNumOperands(MI) == 2 &&
2120
1.73k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2121
1.73k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2122
      // (BPXCCNT brtarget:$imm, 10)
2123
415
      AsmString = "bg,pn %xcc, $\x01";
2124
415
      break;
2125
415
    }
2126
1.32k
    if (MCInst_getNumOperands(MI) == 2 &&
2127
1.32k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2128
1.32k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2129
      // (BPXCCNT brtarget:$imm, 2)
2130
199
      AsmString = "ble,pn %xcc, $\x01";
2131
199
      break;
2132
199
    }
2133
1.12k
    if (MCInst_getNumOperands(MI) == 2 &&
2134
1.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2135
1.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2136
      // (BPXCCNT brtarget:$imm, 11)
2137
164
      AsmString = "bge,pn %xcc, $\x01";
2138
164
      break;
2139
164
    }
2140
959
    if (MCInst_getNumOperands(MI) == 2 &&
2141
959
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2142
959
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2143
      // (BPXCCNT brtarget:$imm, 3)
2144
23
      AsmString = "bl,pn %xcc, $\x01";
2145
23
      break;
2146
23
    }
2147
936
    if (MCInst_getNumOperands(MI) == 2 &&
2148
936
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2149
936
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2150
      // (BPXCCNT brtarget:$imm, 12)
2151
223
      AsmString = "bgu,pn %xcc, $\x01";
2152
223
      break;
2153
223
    }
2154
713
    if (MCInst_getNumOperands(MI) == 2 &&
2155
713
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2156
713
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2157
      // (BPXCCNT brtarget:$imm, 4)
2158
124
      AsmString = "bleu,pn %xcc, $\x01";
2159
124
      break;
2160
124
    }
2161
589
    if (MCInst_getNumOperands(MI) == 2 &&
2162
589
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2163
589
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2164
      // (BPXCCNT brtarget:$imm, 13)
2165
70
      AsmString = "bcc,pn %xcc, $\x01";
2166
70
      break;
2167
70
    }
2168
519
    if (MCInst_getNumOperands(MI) == 2 &&
2169
519
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2170
519
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2171
      // (BPXCCNT brtarget:$imm, 5)
2172
46
      AsmString = "bcs,pn %xcc, $\x01";
2173
46
      break;
2174
46
    }
2175
473
    if (MCInst_getNumOperands(MI) == 2 &&
2176
473
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2177
473
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2178
      // (BPXCCNT brtarget:$imm, 14)
2179
36
      AsmString = "bpos,pn %xcc, $\x01";
2180
36
      break;
2181
36
    }
2182
437
    if (MCInst_getNumOperands(MI) == 2 &&
2183
437
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2184
437
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2185
      // (BPXCCNT brtarget:$imm, 6)
2186
208
      AsmString = "bneg,pn %xcc, $\x01";
2187
208
      break;
2188
208
    }
2189
229
    if (MCInst_getNumOperands(MI) == 2 &&
2190
229
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2191
229
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2192
      // (BPXCCNT brtarget:$imm, 15)
2193
191
      AsmString = "bvc,pn %xcc, $\x01";
2194
191
      break;
2195
191
    }
2196
38
    if (MCInst_getNumOperands(MI) == 2 &&
2197
38
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2198
38
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2199
      // (BPXCCNT brtarget:$imm, 7)
2200
38
      AsmString = "bvs,pn %xcc, $\x01";
2201
38
      break;
2202
38
    }
2203
0
    return NULL;
2204
176
  case SP_FMOVD_ICC:
2205
176
    if (MCInst_getNumOperands(MI) == 3 &&
2206
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2207
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2208
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2209
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2210
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2211
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2212
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2213
0
      AsmString = "fmovda %icc, $\x02, $\x01";
2214
0
      break;
2215
0
    }
2216
176
    if (MCInst_getNumOperands(MI) == 3 &&
2217
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2218
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2219
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2220
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2221
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2222
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2223
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2224
0
      AsmString = "fmovdn %icc, $\x02, $\x01";
2225
0
      break;
2226
0
    }
2227
176
    if (MCInst_getNumOperands(MI) == 3 &&
2228
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2229
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2230
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2231
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2232
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2233
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2234
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2235
0
      AsmString = "fmovdne %icc, $\x02, $\x01";
2236
0
      break;
2237
0
    }
2238
176
    if (MCInst_getNumOperands(MI) == 3 &&
2239
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2240
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2241
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2242
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2243
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2244
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2245
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2246
0
      AsmString = "fmovde %icc, $\x02, $\x01";
2247
0
      break;
2248
0
    }
2249
176
    if (MCInst_getNumOperands(MI) == 3 &&
2250
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2251
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2252
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2253
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2254
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2255
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2256
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2257
0
      AsmString = "fmovdg %icc, $\x02, $\x01";
2258
0
      break;
2259
0
    }
2260
176
    if (MCInst_getNumOperands(MI) == 3 &&
2261
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2262
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2263
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2264
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2265
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2266
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2267
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2268
0
      AsmString = "fmovdle %icc, $\x02, $\x01";
2269
0
      break;
2270
0
    }
2271
176
    if (MCInst_getNumOperands(MI) == 3 &&
2272
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2273
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2274
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2275
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2276
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2277
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2278
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2279
0
      AsmString = "fmovdge %icc, $\x02, $\x01";
2280
0
      break;
2281
0
    }
2282
176
    if (MCInst_getNumOperands(MI) == 3 &&
2283
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2285
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2287
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2288
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2289
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2290
0
      AsmString = "fmovdl %icc, $\x02, $\x01";
2291
0
      break;
2292
0
    }
2293
176
    if (MCInst_getNumOperands(MI) == 3 &&
2294
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2295
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2296
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2297
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2298
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2299
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2300
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2301
0
      AsmString = "fmovdgu %icc, $\x02, $\x01";
2302
0
      break;
2303
0
    }
2304
176
    if (MCInst_getNumOperands(MI) == 3 &&
2305
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2306
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2307
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2308
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2309
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2310
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2311
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2312
0
      AsmString = "fmovdleu %icc, $\x02, $\x01";
2313
0
      break;
2314
0
    }
2315
176
    if (MCInst_getNumOperands(MI) == 3 &&
2316
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2317
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2318
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2319
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2320
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2321
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2322
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2323
0
      AsmString = "fmovdcc %icc, $\x02, $\x01";
2324
0
      break;
2325
0
    }
2326
176
    if (MCInst_getNumOperands(MI) == 3 &&
2327
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2328
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2329
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2330
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2331
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2332
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2333
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2334
0
      AsmString = "fmovdcs %icc, $\x02, $\x01";
2335
0
      break;
2336
0
    }
2337
176
    if (MCInst_getNumOperands(MI) == 3 &&
2338
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2339
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2340
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2341
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2342
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2343
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2344
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2345
0
      AsmString = "fmovdpos %icc, $\x02, $\x01";
2346
0
      break;
2347
0
    }
2348
176
    if (MCInst_getNumOperands(MI) == 3 &&
2349
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2350
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2351
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2352
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2353
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2354
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2355
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2356
0
      AsmString = "fmovdneg %icc, $\x02, $\x01";
2357
0
      break;
2358
0
    }
2359
176
    if (MCInst_getNumOperands(MI) == 3 &&
2360
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2361
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2362
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2363
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2364
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2365
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2366
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2367
0
      AsmString = "fmovdvc %icc, $\x02, $\x01";
2368
0
      break;
2369
0
    }
2370
176
    if (MCInst_getNumOperands(MI) == 3 &&
2371
176
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2372
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2373
176
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2374
176
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2375
176
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2376
176
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2377
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2378
0
      AsmString = "fmovdvs %icc, $\x02, $\x01";
2379
0
      break;
2380
0
    }
2381
176
    return NULL;
2382
57
  case SP_FMOVD_XCC:
2383
57
    if (MCInst_getNumOperands(MI) == 3 &&
2384
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2385
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2386
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2387
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2388
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2389
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2390
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2391
0
      AsmString = "fmovda %xcc, $\x02, $\x01";
2392
0
      break;
2393
0
    }
2394
57
    if (MCInst_getNumOperands(MI) == 3 &&
2395
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2396
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2397
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2398
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2399
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2400
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2401
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2402
0
      AsmString = "fmovdn %xcc, $\x02, $\x01";
2403
0
      break;
2404
0
    }
2405
57
    if (MCInst_getNumOperands(MI) == 3 &&
2406
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2407
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2408
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2409
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2410
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2411
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2412
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2413
0
      AsmString = "fmovdne %xcc, $\x02, $\x01";
2414
0
      break;
2415
0
    }
2416
57
    if (MCInst_getNumOperands(MI) == 3 &&
2417
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2418
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2419
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2420
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2421
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2422
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2423
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2424
0
      AsmString = "fmovde %xcc, $\x02, $\x01";
2425
0
      break;
2426
0
    }
2427
57
    if (MCInst_getNumOperands(MI) == 3 &&
2428
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2429
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2430
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2431
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2432
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2433
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2434
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2435
0
      AsmString = "fmovdg %xcc, $\x02, $\x01";
2436
0
      break;
2437
0
    }
2438
57
    if (MCInst_getNumOperands(MI) == 3 &&
2439
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2440
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2441
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2442
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2443
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2444
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2445
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2446
0
      AsmString = "fmovdle %xcc, $\x02, $\x01";
2447
0
      break;
2448
0
    }
2449
57
    if (MCInst_getNumOperands(MI) == 3 &&
2450
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2451
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2452
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2453
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2454
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2455
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2456
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2457
0
      AsmString = "fmovdge %xcc, $\x02, $\x01";
2458
0
      break;
2459
0
    }
2460
57
    if (MCInst_getNumOperands(MI) == 3 &&
2461
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2462
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2463
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2464
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2465
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2466
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2467
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2468
0
      AsmString = "fmovdl %xcc, $\x02, $\x01";
2469
0
      break;
2470
0
    }
2471
57
    if (MCInst_getNumOperands(MI) == 3 &&
2472
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2473
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2474
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2475
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2476
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2477
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2478
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2479
0
      AsmString = "fmovdgu %xcc, $\x02, $\x01";
2480
0
      break;
2481
0
    }
2482
57
    if (MCInst_getNumOperands(MI) == 3 &&
2483
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2484
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2485
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2486
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2487
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2488
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2489
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2490
0
      AsmString = "fmovdleu %xcc, $\x02, $\x01";
2491
0
      break;
2492
0
    }
2493
57
    if (MCInst_getNumOperands(MI) == 3 &&
2494
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2495
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2496
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2497
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2498
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2499
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2500
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2501
0
      AsmString = "fmovdcc %xcc, $\x02, $\x01";
2502
0
      break;
2503
0
    }
2504
57
    if (MCInst_getNumOperands(MI) == 3 &&
2505
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2506
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2507
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2508
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2509
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2510
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2511
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2512
0
      AsmString = "fmovdcs %xcc, $\x02, $\x01";
2513
0
      break;
2514
0
    }
2515
57
    if (MCInst_getNumOperands(MI) == 3 &&
2516
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2518
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2519
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2520
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2521
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2522
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2523
0
      AsmString = "fmovdpos %xcc, $\x02, $\x01";
2524
0
      break;
2525
0
    }
2526
57
    if (MCInst_getNumOperands(MI) == 3 &&
2527
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2528
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2529
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2530
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2531
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2532
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2533
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2534
0
      AsmString = "fmovdneg %xcc, $\x02, $\x01";
2535
0
      break;
2536
0
    }
2537
57
    if (MCInst_getNumOperands(MI) == 3 &&
2538
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2539
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2540
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2541
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2542
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2543
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2544
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2545
0
      AsmString = "fmovdvc %xcc, $\x02, $\x01";
2546
0
      break;
2547
0
    }
2548
57
    if (MCInst_getNumOperands(MI) == 3 &&
2549
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2550
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2551
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2552
57
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2553
57
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2554
57
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2555
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2556
0
      AsmString = "fmovdvs %xcc, $\x02, $\x01";
2557
0
      break;
2558
0
    }
2559
57
    return NULL;
2560
517
  case SP_FMOVQ_ICC:
2561
517
    if (MCInst_getNumOperands(MI) == 3 &&
2562
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2563
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2564
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2565
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2566
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2567
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2568
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2569
0
      AsmString = "fmovqa %icc, $\x02, $\x01";
2570
0
      break;
2571
0
    }
2572
517
    if (MCInst_getNumOperands(MI) == 3 &&
2573
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2574
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2575
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2576
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2577
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2578
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2579
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2580
0
      AsmString = "fmovqn %icc, $\x02, $\x01";
2581
0
      break;
2582
0
    }
2583
517
    if (MCInst_getNumOperands(MI) == 3 &&
2584
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2585
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2586
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2587
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2588
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2589
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2590
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2591
0
      AsmString = "fmovqne %icc, $\x02, $\x01";
2592
0
      break;
2593
0
    }
2594
517
    if (MCInst_getNumOperands(MI) == 3 &&
2595
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2596
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2597
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2598
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2599
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2600
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2601
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2602
0
      AsmString = "fmovqe %icc, $\x02, $\x01";
2603
0
      break;
2604
0
    }
2605
517
    if (MCInst_getNumOperands(MI) == 3 &&
2606
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2607
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2608
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2609
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2610
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2611
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2612
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2613
0
      AsmString = "fmovqg %icc, $\x02, $\x01";
2614
0
      break;
2615
0
    }
2616
517
    if (MCInst_getNumOperands(MI) == 3 &&
2617
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2618
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2619
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2620
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2621
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2622
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2623
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2624
0
      AsmString = "fmovqle %icc, $\x02, $\x01";
2625
0
      break;
2626
0
    }
2627
517
    if (MCInst_getNumOperands(MI) == 3 &&
2628
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2629
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2630
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2631
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2632
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2633
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2634
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2635
0
      AsmString = "fmovqge %icc, $\x02, $\x01";
2636
0
      break;
2637
0
    }
2638
517
    if (MCInst_getNumOperands(MI) == 3 &&
2639
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2640
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2641
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2642
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2643
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2644
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2645
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2646
0
      AsmString = "fmovql %icc, $\x02, $\x01";
2647
0
      break;
2648
0
    }
2649
517
    if (MCInst_getNumOperands(MI) == 3 &&
2650
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2651
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2652
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2653
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2654
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2655
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2656
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2657
0
      AsmString = "fmovqgu %icc, $\x02, $\x01";
2658
0
      break;
2659
0
    }
2660
517
    if (MCInst_getNumOperands(MI) == 3 &&
2661
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2662
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2663
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2664
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2665
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2666
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2667
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2668
0
      AsmString = "fmovqleu %icc, $\x02, $\x01";
2669
0
      break;
2670
0
    }
2671
517
    if (MCInst_getNumOperands(MI) == 3 &&
2672
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2673
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2674
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2675
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2676
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2677
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2678
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2679
0
      AsmString = "fmovqcc %icc, $\x02, $\x01";
2680
0
      break;
2681
0
    }
2682
517
    if (MCInst_getNumOperands(MI) == 3 &&
2683
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2684
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2685
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2686
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2687
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2688
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2689
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2690
0
      AsmString = "fmovqcs %icc, $\x02, $\x01";
2691
0
      break;
2692
0
    }
2693
517
    if (MCInst_getNumOperands(MI) == 3 &&
2694
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2695
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2696
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2697
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2698
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2699
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2700
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2701
0
      AsmString = "fmovqpos %icc, $\x02, $\x01";
2702
0
      break;
2703
0
    }
2704
517
    if (MCInst_getNumOperands(MI) == 3 &&
2705
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2706
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2707
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2708
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2709
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2710
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2711
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2712
0
      AsmString = "fmovqneg %icc, $\x02, $\x01";
2713
0
      break;
2714
0
    }
2715
517
    if (MCInst_getNumOperands(MI) == 3 &&
2716
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2717
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2718
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2719
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2720
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2721
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2722
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2723
0
      AsmString = "fmovqvc %icc, $\x02, $\x01";
2724
0
      break;
2725
0
    }
2726
517
    if (MCInst_getNumOperands(MI) == 3 &&
2727
517
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2728
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2729
517
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2730
517
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2731
517
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2732
517
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2733
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2734
0
      AsmString = "fmovqvs %icc, $\x02, $\x01";
2735
0
      break;
2736
0
    }
2737
517
    return NULL;
2738
20
  case SP_FMOVQ_XCC:
2739
20
    if (MCInst_getNumOperands(MI) == 3 &&
2740
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2741
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2742
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2743
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2744
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2745
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2746
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2747
0
      AsmString = "fmovqa %xcc, $\x02, $\x01";
2748
0
      break;
2749
0
    }
2750
20
    if (MCInst_getNumOperands(MI) == 3 &&
2751
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2752
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2753
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2754
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2755
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2756
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2757
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2758
0
      AsmString = "fmovqn %xcc, $\x02, $\x01";
2759
0
      break;
2760
0
    }
2761
20
    if (MCInst_getNumOperands(MI) == 3 &&
2762
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2763
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2764
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2765
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2766
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2767
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2768
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2769
0
      AsmString = "fmovqne %xcc, $\x02, $\x01";
2770
0
      break;
2771
0
    }
2772
20
    if (MCInst_getNumOperands(MI) == 3 &&
2773
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2774
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2775
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2776
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2777
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2778
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2779
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2780
0
      AsmString = "fmovqe %xcc, $\x02, $\x01";
2781
0
      break;
2782
0
    }
2783
20
    if (MCInst_getNumOperands(MI) == 3 &&
2784
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2785
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2786
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2787
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2788
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2789
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2790
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2791
0
      AsmString = "fmovqg %xcc, $\x02, $\x01";
2792
0
      break;
2793
0
    }
2794
20
    if (MCInst_getNumOperands(MI) == 3 &&
2795
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2796
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2797
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2798
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2799
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2800
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2801
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2802
0
      AsmString = "fmovqle %xcc, $\x02, $\x01";
2803
0
      break;
2804
0
    }
2805
20
    if (MCInst_getNumOperands(MI) == 3 &&
2806
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2807
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2808
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2809
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2810
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2811
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2812
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2813
0
      AsmString = "fmovqge %xcc, $\x02, $\x01";
2814
0
      break;
2815
0
    }
2816
20
    if (MCInst_getNumOperands(MI) == 3 &&
2817
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2818
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2819
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2820
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2821
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2822
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2823
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2824
0
      AsmString = "fmovql %xcc, $\x02, $\x01";
2825
0
      break;
2826
0
    }
2827
20
    if (MCInst_getNumOperands(MI) == 3 &&
2828
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2829
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2830
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2831
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2832
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2834
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2835
0
      AsmString = "fmovqgu %xcc, $\x02, $\x01";
2836
0
      break;
2837
0
    }
2838
20
    if (MCInst_getNumOperands(MI) == 3 &&
2839
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2840
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2841
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2842
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2843
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2844
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2845
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2846
0
      AsmString = "fmovqleu %xcc, $\x02, $\x01";
2847
0
      break;
2848
0
    }
2849
20
    if (MCInst_getNumOperands(MI) == 3 &&
2850
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2851
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2852
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2853
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2854
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2855
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2856
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2857
0
      AsmString = "fmovqcc %xcc, $\x02, $\x01";
2858
0
      break;
2859
0
    }
2860
20
    if (MCInst_getNumOperands(MI) == 3 &&
2861
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2862
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2863
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2864
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2865
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2866
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2867
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2868
0
      AsmString = "fmovqcs %xcc, $\x02, $\x01";
2869
0
      break;
2870
0
    }
2871
20
    if (MCInst_getNumOperands(MI) == 3 &&
2872
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2873
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2874
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2875
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2876
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2877
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2878
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2879
0
      AsmString = "fmovqpos %xcc, $\x02, $\x01";
2880
0
      break;
2881
0
    }
2882
20
    if (MCInst_getNumOperands(MI) == 3 &&
2883
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2884
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2885
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2886
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2887
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2888
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2889
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2890
0
      AsmString = "fmovqneg %xcc, $\x02, $\x01";
2891
0
      break;
2892
0
    }
2893
20
    if (MCInst_getNumOperands(MI) == 3 &&
2894
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2895
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2896
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2897
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2898
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2899
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2900
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2901
0
      AsmString = "fmovqvc %xcc, $\x02, $\x01";
2902
0
      break;
2903
0
    }
2904
20
    if (MCInst_getNumOperands(MI) == 3 &&
2905
20
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2906
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2907
20
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2908
20
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2909
20
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2910
20
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2911
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2912
0
      AsmString = "fmovqvs %xcc, $\x02, $\x01";
2913
0
      break;
2914
0
    }
2915
20
    return NULL;
2916
34
  case SP_FMOVS_ICC:
2917
34
    if (MCInst_getNumOperands(MI) == 3 &&
2918
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2919
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2920
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2921
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2922
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2923
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2924
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2925
0
      AsmString = "fmovsa %icc, $\x02, $\x01";
2926
0
      break;
2927
0
    }
2928
34
    if (MCInst_getNumOperands(MI) == 3 &&
2929
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2930
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2931
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2932
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2933
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2934
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2935
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2936
0
      AsmString = "fmovsn %icc, $\x02, $\x01";
2937
0
      break;
2938
0
    }
2939
34
    if (MCInst_getNumOperands(MI) == 3 &&
2940
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2941
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2942
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2943
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2944
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2945
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2946
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2947
0
      AsmString = "fmovsne %icc, $\x02, $\x01";
2948
0
      break;
2949
0
    }
2950
34
    if (MCInst_getNumOperands(MI) == 3 &&
2951
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2952
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2953
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2954
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2955
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2956
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2957
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2958
0
      AsmString = "fmovse %icc, $\x02, $\x01";
2959
0
      break;
2960
0
    }
2961
34
    if (MCInst_getNumOperands(MI) == 3 &&
2962
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2963
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2964
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2965
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2966
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2967
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2968
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2969
0
      AsmString = "fmovsg %icc, $\x02, $\x01";
2970
0
      break;
2971
0
    }
2972
34
    if (MCInst_getNumOperands(MI) == 3 &&
2973
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2974
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2975
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2976
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2977
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2978
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2979
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2980
0
      AsmString = "fmovsle %icc, $\x02, $\x01";
2981
0
      break;
2982
0
    }
2983
34
    if (MCInst_getNumOperands(MI) == 3 &&
2984
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2985
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2986
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2987
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2988
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2989
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2990
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2991
0
      AsmString = "fmovsge %icc, $\x02, $\x01";
2992
0
      break;
2993
0
    }
2994
34
    if (MCInst_getNumOperands(MI) == 3 &&
2995
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2996
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2997
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2998
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2999
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3000
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3001
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3002
0
      AsmString = "fmovsl %icc, $\x02, $\x01";
3003
0
      break;
3004
0
    }
3005
34
    if (MCInst_getNumOperands(MI) == 3 &&
3006
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3007
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3008
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3009
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3010
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3011
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3012
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3013
0
      AsmString = "fmovsgu %icc, $\x02, $\x01";
3014
0
      break;
3015
0
    }
3016
34
    if (MCInst_getNumOperands(MI) == 3 &&
3017
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3018
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3019
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3020
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3021
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3022
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3023
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3024
0
      AsmString = "fmovsleu %icc, $\x02, $\x01";
3025
0
      break;
3026
0
    }
3027
34
    if (MCInst_getNumOperands(MI) == 3 &&
3028
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3029
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3030
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3031
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3032
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3033
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3034
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3035
0
      AsmString = "fmovscc %icc, $\x02, $\x01";
3036
0
      break;
3037
0
    }
3038
34
    if (MCInst_getNumOperands(MI) == 3 &&
3039
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3040
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3041
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3042
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3043
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3044
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3045
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3046
0
      AsmString = "fmovscs %icc, $\x02, $\x01";
3047
0
      break;
3048
0
    }
3049
34
    if (MCInst_getNumOperands(MI) == 3 &&
3050
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3051
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3052
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3053
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3054
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3055
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3056
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3057
0
      AsmString = "fmovspos %icc, $\x02, $\x01";
3058
0
      break;
3059
0
    }
3060
34
    if (MCInst_getNumOperands(MI) == 3 &&
3061
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3062
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3063
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3064
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3065
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3066
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3067
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3068
0
      AsmString = "fmovsneg %icc, $\x02, $\x01";
3069
0
      break;
3070
0
    }
3071
34
    if (MCInst_getNumOperands(MI) == 3 &&
3072
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3073
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3074
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3075
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3076
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3077
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3078
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3079
0
      AsmString = "fmovsvc %icc, $\x02, $\x01";
3080
0
      break;
3081
0
    }
3082
34
    if (MCInst_getNumOperands(MI) == 3 &&
3083
34
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3084
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3085
34
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3086
34
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3087
34
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3088
34
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3089
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3090
0
      AsmString = "fmovsvs %icc, $\x02, $\x01";
3091
0
      break;
3092
0
    }
3093
34
    return NULL;
3094
12
  case SP_FMOVS_XCC:
3095
12
    if (MCInst_getNumOperands(MI) == 3 &&
3096
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3097
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3098
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3099
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3100
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3101
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3102
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3103
0
      AsmString = "fmovsa %xcc, $\x02, $\x01";
3104
0
      break;
3105
0
    }
3106
12
    if (MCInst_getNumOperands(MI) == 3 &&
3107
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3108
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3109
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3110
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3111
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3112
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3113
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3114
0
      AsmString = "fmovsn %xcc, $\x02, $\x01";
3115
0
      break;
3116
0
    }
3117
12
    if (MCInst_getNumOperands(MI) == 3 &&
3118
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3119
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3120
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3121
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3122
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3123
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3124
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3125
0
      AsmString = "fmovsne %xcc, $\x02, $\x01";
3126
0
      break;
3127
0
    }
3128
12
    if (MCInst_getNumOperands(MI) == 3 &&
3129
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3130
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3131
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3132
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3133
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3134
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3135
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3136
0
      AsmString = "fmovse %xcc, $\x02, $\x01";
3137
0
      break;
3138
0
    }
3139
12
    if (MCInst_getNumOperands(MI) == 3 &&
3140
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3141
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3142
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3143
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3144
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3145
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3146
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3147
0
      AsmString = "fmovsg %xcc, $\x02, $\x01";
3148
0
      break;
3149
0
    }
3150
12
    if (MCInst_getNumOperands(MI) == 3 &&
3151
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3152
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3153
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3154
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3155
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3156
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3157
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3158
0
      AsmString = "fmovsle %xcc, $\x02, $\x01";
3159
0
      break;
3160
0
    }
3161
12
    if (MCInst_getNumOperands(MI) == 3 &&
3162
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3163
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3164
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3165
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3166
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3167
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3168
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3169
0
      AsmString = "fmovsge %xcc, $\x02, $\x01";
3170
0
      break;
3171
0
    }
3172
12
    if (MCInst_getNumOperands(MI) == 3 &&
3173
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3174
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3175
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3176
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3177
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3178
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3179
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3180
0
      AsmString = "fmovsl %xcc, $\x02, $\x01";
3181
0
      break;
3182
0
    }
3183
12
    if (MCInst_getNumOperands(MI) == 3 &&
3184
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3185
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3186
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3187
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3188
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3190
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3191
0
      AsmString = "fmovsgu %xcc, $\x02, $\x01";
3192
0
      break;
3193
0
    }
3194
12
    if (MCInst_getNumOperands(MI) == 3 &&
3195
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3196
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3197
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3198
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3199
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3200
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3201
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3202
0
      AsmString = "fmovsleu %xcc, $\x02, $\x01";
3203
0
      break;
3204
0
    }
3205
12
    if (MCInst_getNumOperands(MI) == 3 &&
3206
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3207
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3208
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3209
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3210
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3211
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3212
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3213
0
      AsmString = "fmovscc %xcc, $\x02, $\x01";
3214
0
      break;
3215
0
    }
3216
12
    if (MCInst_getNumOperands(MI) == 3 &&
3217
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3218
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3219
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3220
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3221
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3222
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3223
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3224
0
      AsmString = "fmovscs %xcc, $\x02, $\x01";
3225
0
      break;
3226
0
    }
3227
12
    if (MCInst_getNumOperands(MI) == 3 &&
3228
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3229
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3230
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3231
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3232
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3233
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3234
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3235
0
      AsmString = "fmovspos %xcc, $\x02, $\x01";
3236
0
      break;
3237
0
    }
3238
12
    if (MCInst_getNumOperands(MI) == 3 &&
3239
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3240
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3241
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3242
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3243
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3244
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3245
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3246
0
      AsmString = "fmovsneg %xcc, $\x02, $\x01";
3247
0
      break;
3248
0
    }
3249
12
    if (MCInst_getNumOperands(MI) == 3 &&
3250
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3251
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3252
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3253
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3254
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3255
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3256
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3257
0
      AsmString = "fmovsvc %xcc, $\x02, $\x01";
3258
0
      break;
3259
0
    }
3260
12
    if (MCInst_getNumOperands(MI) == 3 &&
3261
12
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3262
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3263
12
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3264
12
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3265
12
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3266
12
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3267
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3268
0
      AsmString = "fmovsvs %xcc, $\x02, $\x01";
3269
0
      break;
3270
0
    }
3271
12
    return NULL;
3272
345
  case SP_MOVICCri:
3273
345
    if (MCInst_getNumOperands(MI) == 3 &&
3274
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3275
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3276
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3277
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3278
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3279
0
      AsmString = "mova %icc, $\x02, $\x01";
3280
0
      break;
3281
0
    }
3282
345
    if (MCInst_getNumOperands(MI) == 3 &&
3283
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3284
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3285
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3286
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3287
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3288
0
      AsmString = "movn %icc, $\x02, $\x01";
3289
0
      break;
3290
0
    }
3291
345
    if (MCInst_getNumOperands(MI) == 3 &&
3292
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3293
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3294
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3295
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3296
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3297
0
      AsmString = "movne %icc, $\x02, $\x01";
3298
0
      break;
3299
0
    }
3300
345
    if (MCInst_getNumOperands(MI) == 3 &&
3301
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3302
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3303
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3304
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3305
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3306
0
      AsmString = "move %icc, $\x02, $\x01";
3307
0
      break;
3308
0
    }
3309
345
    if (MCInst_getNumOperands(MI) == 3 &&
3310
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3311
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3312
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3313
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3314
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3315
0
      AsmString = "movg %icc, $\x02, $\x01";
3316
0
      break;
3317
0
    }
3318
345
    if (MCInst_getNumOperands(MI) == 3 &&
3319
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3320
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3321
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3322
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3323
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3324
0
      AsmString = "movle %icc, $\x02, $\x01";
3325
0
      break;
3326
0
    }
3327
345
    if (MCInst_getNumOperands(MI) == 3 &&
3328
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3329
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3330
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3331
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3332
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3333
0
      AsmString = "movge %icc, $\x02, $\x01";
3334
0
      break;
3335
0
    }
3336
345
    if (MCInst_getNumOperands(MI) == 3 &&
3337
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3338
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3339
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3340
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3341
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3342
0
      AsmString = "movl %icc, $\x02, $\x01";
3343
0
      break;
3344
0
    }
3345
345
    if (MCInst_getNumOperands(MI) == 3 &&
3346
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3347
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3348
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3349
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3350
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3351
0
      AsmString = "movgu %icc, $\x02, $\x01";
3352
0
      break;
3353
0
    }
3354
345
    if (MCInst_getNumOperands(MI) == 3 &&
3355
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3356
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3357
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3358
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3359
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3360
0
      AsmString = "movleu %icc, $\x02, $\x01";
3361
0
      break;
3362
0
    }
3363
345
    if (MCInst_getNumOperands(MI) == 3 &&
3364
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3365
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3366
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3367
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3368
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3369
0
      AsmString = "movcc %icc, $\x02, $\x01";
3370
0
      break;
3371
0
    }
3372
345
    if (MCInst_getNumOperands(MI) == 3 &&
3373
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3374
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3375
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3376
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3377
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3378
0
      AsmString = "movcs %icc, $\x02, $\x01";
3379
0
      break;
3380
0
    }
3381
345
    if (MCInst_getNumOperands(MI) == 3 &&
3382
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3383
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3384
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3385
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3386
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3387
0
      AsmString = "movpos %icc, $\x02, $\x01";
3388
0
      break;
3389
0
    }
3390
345
    if (MCInst_getNumOperands(MI) == 3 &&
3391
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3392
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3393
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3394
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3395
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3396
0
      AsmString = "movneg %icc, $\x02, $\x01";
3397
0
      break;
3398
0
    }
3399
345
    if (MCInst_getNumOperands(MI) == 3 &&
3400
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3401
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3402
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3403
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3404
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3405
0
      AsmString = "movvc %icc, $\x02, $\x01";
3406
0
      break;
3407
0
    }
3408
345
    if (MCInst_getNumOperands(MI) == 3 &&
3409
345
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3410
345
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3411
345
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3412
345
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3413
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3414
0
      AsmString = "movvs %icc, $\x02, $\x01";
3415
0
      break;
3416
0
    }
3417
345
    return NULL;
3418
199
  case SP_MOVICCrr:
3419
199
    if (MCInst_getNumOperands(MI) == 3 &&
3420
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3421
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3422
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3423
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3424
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3425
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3426
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3427
0
      AsmString = "mova %icc, $\x02, $\x01";
3428
0
      break;
3429
0
    }
3430
199
    if (MCInst_getNumOperands(MI) == 3 &&
3431
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3432
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3433
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3434
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3435
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3436
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3437
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3438
0
      AsmString = "movn %icc, $\x02, $\x01";
3439
0
      break;
3440
0
    }
3441
199
    if (MCInst_getNumOperands(MI) == 3 &&
3442
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3443
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3444
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3445
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3446
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3447
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3448
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3449
0
      AsmString = "movne %icc, $\x02, $\x01";
3450
0
      break;
3451
0
    }
3452
199
    if (MCInst_getNumOperands(MI) == 3 &&
3453
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3454
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3455
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3456
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3457
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3458
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3459
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3460
0
      AsmString = "move %icc, $\x02, $\x01";
3461
0
      break;
3462
0
    }
3463
199
    if (MCInst_getNumOperands(MI) == 3 &&
3464
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3465
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3466
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3467
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3468
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3469
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3470
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3471
0
      AsmString = "movg %icc, $\x02, $\x01";
3472
0
      break;
3473
0
    }
3474
199
    if (MCInst_getNumOperands(MI) == 3 &&
3475
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3476
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3477
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3478
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3479
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3480
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3481
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3482
0
      AsmString = "movle %icc, $\x02, $\x01";
3483
0
      break;
3484
0
    }
3485
199
    if (MCInst_getNumOperands(MI) == 3 &&
3486
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3487
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3488
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3489
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3490
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3491
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3492
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3493
0
      AsmString = "movge %icc, $\x02, $\x01";
3494
0
      break;
3495
0
    }
3496
199
    if (MCInst_getNumOperands(MI) == 3 &&
3497
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3498
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3499
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3500
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3501
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3502
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3503
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3504
0
      AsmString = "movl %icc, $\x02, $\x01";
3505
0
      break;
3506
0
    }
3507
199
    if (MCInst_getNumOperands(MI) == 3 &&
3508
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3509
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3510
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3511
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3512
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3513
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3514
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3515
0
      AsmString = "movgu %icc, $\x02, $\x01";
3516
0
      break;
3517
0
    }
3518
199
    if (MCInst_getNumOperands(MI) == 3 &&
3519
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3520
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3521
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3522
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3523
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3524
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3525
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3526
0
      AsmString = "movleu %icc, $\x02, $\x01";
3527
0
      break;
3528
0
    }
3529
199
    if (MCInst_getNumOperands(MI) == 3 &&
3530
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3531
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3532
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3533
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3534
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3535
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3536
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3537
0
      AsmString = "movcc %icc, $\x02, $\x01";
3538
0
      break;
3539
0
    }
3540
199
    if (MCInst_getNumOperands(MI) == 3 &&
3541
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3542
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3543
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3544
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3545
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3546
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3547
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3548
0
      AsmString = "movcs %icc, $\x02, $\x01";
3549
0
      break;
3550
0
    }
3551
199
    if (MCInst_getNumOperands(MI) == 3 &&
3552
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3553
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3554
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3555
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3556
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3557
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3558
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3559
0
      AsmString = "movpos %icc, $\x02, $\x01";
3560
0
      break;
3561
0
    }
3562
199
    if (MCInst_getNumOperands(MI) == 3 &&
3563
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3564
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3565
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3566
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3567
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3568
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3569
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3570
0
      AsmString = "movneg %icc, $\x02, $\x01";
3571
0
      break;
3572
0
    }
3573
199
    if (MCInst_getNumOperands(MI) == 3 &&
3574
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3575
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3576
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3577
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3578
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3579
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3580
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3581
0
      AsmString = "movvc %icc, $\x02, $\x01";
3582
0
      break;
3583
0
    }
3584
199
    if (MCInst_getNumOperands(MI) == 3 &&
3585
199
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3586
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3587
199
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3588
199
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3589
199
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3590
199
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3591
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3592
0
      AsmString = "movvs %icc, $\x02, $\x01";
3593
0
      break;
3594
0
    }
3595
199
    return NULL;
3596
201
  case SP_MOVXCCri:
3597
201
    if (MCInst_getNumOperands(MI) == 3 &&
3598
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3599
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3600
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3601
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3602
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3603
0
      AsmString = "mova %xcc, $\x02, $\x01";
3604
0
      break;
3605
0
    }
3606
201
    if (MCInst_getNumOperands(MI) == 3 &&
3607
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3608
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3609
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3610
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3611
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3612
0
      AsmString = "movn %xcc, $\x02, $\x01";
3613
0
      break;
3614
0
    }
3615
201
    if (MCInst_getNumOperands(MI) == 3 &&
3616
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3617
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3618
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3619
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3620
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3621
0
      AsmString = "movne %xcc, $\x02, $\x01";
3622
0
      break;
3623
0
    }
3624
201
    if (MCInst_getNumOperands(MI) == 3 &&
3625
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3626
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3627
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3628
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3629
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3630
0
      AsmString = "move %xcc, $\x02, $\x01";
3631
0
      break;
3632
0
    }
3633
201
    if (MCInst_getNumOperands(MI) == 3 &&
3634
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3635
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3636
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3637
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3638
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3639
0
      AsmString = "movg %xcc, $\x02, $\x01";
3640
0
      break;
3641
0
    }
3642
201
    if (MCInst_getNumOperands(MI) == 3 &&
3643
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3644
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3645
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3646
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3647
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3648
0
      AsmString = "movle %xcc, $\x02, $\x01";
3649
0
      break;
3650
0
    }
3651
201
    if (MCInst_getNumOperands(MI) == 3 &&
3652
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3653
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3654
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3655
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3656
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3657
0
      AsmString = "movge %xcc, $\x02, $\x01";
3658
0
      break;
3659
0
    }
3660
201
    if (MCInst_getNumOperands(MI) == 3 &&
3661
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3662
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3663
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3664
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3665
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3666
0
      AsmString = "movl %xcc, $\x02, $\x01";
3667
0
      break;
3668
0
    }
3669
201
    if (MCInst_getNumOperands(MI) == 3 &&
3670
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3671
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3672
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3673
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3674
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3675
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3676
0
      break;
3677
0
    }
3678
201
    if (MCInst_getNumOperands(MI) == 3 &&
3679
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3680
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3681
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3682
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3683
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3684
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3685
0
      break;
3686
0
    }
3687
201
    if (MCInst_getNumOperands(MI) == 3 &&
3688
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3689
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3690
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3691
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3692
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3693
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3694
0
      break;
3695
0
    }
3696
201
    if (MCInst_getNumOperands(MI) == 3 &&
3697
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3698
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3699
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3700
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3701
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3702
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3703
0
      break;
3704
0
    }
3705
201
    if (MCInst_getNumOperands(MI) == 3 &&
3706
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3707
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3708
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3709
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3710
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3711
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3712
0
      break;
3713
0
    }
3714
201
    if (MCInst_getNumOperands(MI) == 3 &&
3715
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3716
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3717
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3718
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3719
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3720
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3721
0
      break;
3722
0
    }
3723
201
    if (MCInst_getNumOperands(MI) == 3 &&
3724
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3725
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3726
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3727
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3728
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3729
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3730
0
      break;
3731
0
    }
3732
201
    if (MCInst_getNumOperands(MI) == 3 &&
3733
201
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3734
201
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3735
201
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3736
201
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3737
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3738
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3739
0
      break;
3740
0
    }
3741
201
    return NULL;
3742
281
  case SP_MOVXCCrr:
3743
281
    if (MCInst_getNumOperands(MI) == 3 &&
3744
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3745
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3746
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3747
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3748
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3749
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3750
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3751
0
      AsmString = "mova %xcc, $\x02, $\x01";
3752
0
      break;
3753
0
    }
3754
281
    if (MCInst_getNumOperands(MI) == 3 &&
3755
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3756
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3757
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3758
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3759
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3760
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3761
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3762
0
      AsmString = "movn %xcc, $\x02, $\x01";
3763
0
      break;
3764
0
    }
3765
281
    if (MCInst_getNumOperands(MI) == 3 &&
3766
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3767
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3768
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3769
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3770
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3771
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3772
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3773
0
      AsmString = "movne %xcc, $\x02, $\x01";
3774
0
      break;
3775
0
    }
3776
281
    if (MCInst_getNumOperands(MI) == 3 &&
3777
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3778
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3779
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3780
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3781
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3782
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3783
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3784
0
      AsmString = "move %xcc, $\x02, $\x01";
3785
0
      break;
3786
0
    }
3787
281
    if (MCInst_getNumOperands(MI) == 3 &&
3788
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3789
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3790
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3791
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3792
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3793
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3794
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3795
0
      AsmString = "movg %xcc, $\x02, $\x01";
3796
0
      break;
3797
0
    }
3798
281
    if (MCInst_getNumOperands(MI) == 3 &&
3799
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3800
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3801
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3802
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3803
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3804
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3805
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3806
0
      AsmString = "movle %xcc, $\x02, $\x01";
3807
0
      break;
3808
0
    }
3809
281
    if (MCInst_getNumOperands(MI) == 3 &&
3810
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3811
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3812
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3813
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3814
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3815
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3816
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3817
0
      AsmString = "movge %xcc, $\x02, $\x01";
3818
0
      break;
3819
0
    }
3820
281
    if (MCInst_getNumOperands(MI) == 3 &&
3821
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3822
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3823
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3824
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3825
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3826
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3827
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3828
0
      AsmString = "movl %xcc, $\x02, $\x01";
3829
0
      break;
3830
0
    }
3831
281
    if (MCInst_getNumOperands(MI) == 3 &&
3832
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3833
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3834
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3835
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3836
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3837
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3838
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3839
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3840
0
      break;
3841
0
    }
3842
281
    if (MCInst_getNumOperands(MI) == 3 &&
3843
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3844
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3845
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3846
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3847
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3848
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3849
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3850
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3851
0
      break;
3852
0
    }
3853
281
    if (MCInst_getNumOperands(MI) == 3 &&
3854
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3855
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3856
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3857
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3858
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3859
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3860
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3861
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3862
0
      break;
3863
0
    }
3864
281
    if (MCInst_getNumOperands(MI) == 3 &&
3865
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3866
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3867
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3868
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3869
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3870
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3871
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3872
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3873
0
      break;
3874
0
    }
3875
281
    if (MCInst_getNumOperands(MI) == 3 &&
3876
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3877
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3878
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3879
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3880
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3881
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3882
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3883
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3884
0
      break;
3885
0
    }
3886
281
    if (MCInst_getNumOperands(MI) == 3 &&
3887
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3888
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3889
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3890
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3891
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3892
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3893
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3894
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3895
0
      break;
3896
0
    }
3897
281
    if (MCInst_getNumOperands(MI) == 3 &&
3898
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3899
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3900
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3901
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3902
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3903
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3904
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3905
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3906
0
      break;
3907
0
    }
3908
281
    if (MCInst_getNumOperands(MI) == 3 &&
3909
281
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3910
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3911
281
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3912
281
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3913
281
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3914
281
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3915
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3916
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3917
0
      break;
3918
0
    }
3919
281
    return NULL;
3920
408
  case SP_ORri:
3921
408
    if (MCInst_getNumOperands(MI) == 3 &&
3922
408
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3923
408
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3924
408
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3925
      // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3926
26
      AsmString = "mov $\x03, $\x01";
3927
26
      break;
3928
26
    }
3929
382
    return NULL;
3930
231
  case SP_ORrr:
3931
231
    if (MCInst_getNumOperands(MI) == 3 &&
3932
231
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3933
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3934
231
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3935
231
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3936
231
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3937
      // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3938
167
      AsmString = "mov $\x03, $\x01";
3939
167
      break;
3940
167
    }
3941
64
    return NULL;
3942
114
  case SP_RESTORErr:
3943
114
    if (MCInst_getNumOperands(MI) == 3 &&
3944
114
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3945
114
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3946
114
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3947
      // (RESTORErr G0, G0, G0)
3948
24
      AsmString = "restore";
3949
24
      break;
3950
24
    }
3951
90
    return NULL;
3952
0
  case SP_RET:
3953
0
    if (MCInst_getNumOperands(MI) == 1 &&
3954
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3955
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3956
      // (RET 8)
3957
0
      AsmString = "ret";
3958
0
      break;
3959
0
    }
3960
0
    return NULL;
3961
0
  case SP_RETL:
3962
0
    if (MCInst_getNumOperands(MI) == 1 &&
3963
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3964
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3965
      // (RETL 8)
3966
0
      AsmString = "retl";
3967
0
      break;
3968
0
    }
3969
0
    return NULL;
3970
2.64k
  case SP_TXCCri:
3971
2.64k
    if (MCInst_getNumOperands(MI) == 3 &&
3972
2.64k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3973
2.64k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3974
2.64k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3975
2.64k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3976
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3977
282
      AsmString = "ta %xcc, $\x01 + $\x02";
3978
282
      break;
3979
282
    }
3980
2.36k
    if (MCInst_getNumOperands(MI) == 3 &&
3981
2.36k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3982
2.36k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3983
2.36k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3984
      // (TXCCri G0, i32imm:$imm, 8)
3985
0
      AsmString = "ta %xcc, $\x02";
3986
0
      break;
3987
0
    }
3988
2.36k
    if (MCInst_getNumOperands(MI) == 3 &&
3989
2.36k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3990
2.36k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3991
2.36k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3992
2.36k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3993
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3994
213
      AsmString = "tn %xcc, $\x01 + $\x02";
3995
213
      break;
3996
213
    }
3997
2.15k
    if (MCInst_getNumOperands(MI) == 3 &&
3998
2.15k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3999
2.15k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4000
2.15k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4001
      // (TXCCri G0, i32imm:$imm, 0)
4002
0
      AsmString = "tn %xcc, $\x02";
4003
0
      break;
4004
0
    }
4005
2.15k
    if (MCInst_getNumOperands(MI) == 3 &&
4006
2.15k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4007
2.15k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4008
2.15k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4009
2.15k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4010
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4011
209
      AsmString = "tne %xcc, $\x01 + $\x02";
4012
209
      break;
4013
209
    }
4014
1.94k
    if (MCInst_getNumOperands(MI) == 3 &&
4015
1.94k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4016
1.94k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4017
1.94k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4018
      // (TXCCri G0, i32imm:$imm, 9)
4019
0
      AsmString = "tne %xcc, $\x02";
4020
0
      break;
4021
0
    }
4022
1.94k
    if (MCInst_getNumOperands(MI) == 3 &&
4023
1.94k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4024
1.94k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4025
1.94k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4026
1.94k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4027
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4028
26
      AsmString = "te %xcc, $\x01 + $\x02";
4029
26
      break;
4030
26
    }
4031
1.91k
    if (MCInst_getNumOperands(MI) == 3 &&
4032
1.91k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4033
1.91k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4034
1.91k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4035
      // (TXCCri G0, i32imm:$imm, 1)
4036
0
      AsmString = "te %xcc, $\x02";
4037
0
      break;
4038
0
    }
4039
1.91k
    if (MCInst_getNumOperands(MI) == 3 &&
4040
1.91k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4041
1.91k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4042
1.91k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4043
1.91k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4044
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4045
46
      AsmString = "tg %xcc, $\x01 + $\x02";
4046
46
      break;
4047
46
    }
4048
1.87k
    if (MCInst_getNumOperands(MI) == 3 &&
4049
1.87k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4050
1.87k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4051
1.87k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4052
      // (TXCCri G0, i32imm:$imm, 10)
4053
0
      AsmString = "tg %xcc, $\x02";
4054
0
      break;
4055
0
    }
4056
1.87k
    if (MCInst_getNumOperands(MI) == 3 &&
4057
1.87k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4058
1.87k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4059
1.87k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4060
1.87k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4061
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4062
126
      AsmString = "tle %xcc, $\x01 + $\x02";
4063
126
      break;
4064
126
    }
4065
1.74k
    if (MCInst_getNumOperands(MI) == 3 &&
4066
1.74k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4067
1.74k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4068
1.74k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4069
      // (TXCCri G0, i32imm:$imm, 2)
4070
0
      AsmString = "tle %xcc, $\x02";
4071
0
      break;
4072
0
    }
4073
1.74k
    if (MCInst_getNumOperands(MI) == 3 &&
4074
1.74k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4075
1.74k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4076
1.74k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4077
1.74k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4078
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4079
24
      AsmString = "tge %xcc, $\x01 + $\x02";
4080
24
      break;
4081
24
    }
4082
1.72k
    if (MCInst_getNumOperands(MI) == 3 &&
4083
1.72k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4084
1.72k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4085
1.72k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4086
      // (TXCCri G0, i32imm:$imm, 11)
4087
0
      AsmString = "tge %xcc, $\x02";
4088
0
      break;
4089
0
    }
4090
1.72k
    if (MCInst_getNumOperands(MI) == 3 &&
4091
1.72k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4092
1.72k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4093
1.72k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4094
1.72k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4095
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4096
84
      AsmString = "tl %xcc, $\x01 + $\x02";
4097
84
      break;
4098
84
    }
4099
1.63k
    if (MCInst_getNumOperands(MI) == 3 &&
4100
1.63k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4101
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4102
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4103
      // (TXCCri G0, i32imm:$imm, 3)
4104
0
      AsmString = "tl %xcc, $\x02";
4105
0
      break;
4106
0
    }
4107
1.63k
    if (MCInst_getNumOperands(MI) == 3 &&
4108
1.63k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4109
1.63k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4110
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4111
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4112
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4113
8
      AsmString = "tgu %xcc, $\x01 + $\x02";
4114
8
      break;
4115
8
    }
4116
1.63k
    if (MCInst_getNumOperands(MI) == 3 &&
4117
1.63k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4118
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4119
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4120
      // (TXCCri G0, i32imm:$imm, 12)
4121
0
      AsmString = "tgu %xcc, $\x02";
4122
0
      break;
4123
0
    }
4124
1.63k
    if (MCInst_getNumOperands(MI) == 3 &&
4125
1.63k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4126
1.63k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4127
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4128
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4129
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4130
37
      AsmString = "tleu %xcc, $\x01 + $\x02";
4131
37
      break;
4132
37
    }
4133
1.59k
    if (MCInst_getNumOperands(MI) == 3 &&
4134
1.59k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4135
1.59k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4136
1.59k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4137
      // (TXCCri G0, i32imm:$imm, 4)
4138
0
      AsmString = "tleu %xcc, $\x02";
4139
0
      break;
4140
0
    }
4141
1.59k
    if (MCInst_getNumOperands(MI) == 3 &&
4142
1.59k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4143
1.59k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4144
1.59k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4145
1.59k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4146
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4147
320
      AsmString = "tcc %xcc, $\x01 + $\x02";
4148
320
      break;
4149
320
    }
4150
1.27k
    if (MCInst_getNumOperands(MI) == 3 &&
4151
1.27k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4152
1.27k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4153
1.27k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4154
      // (TXCCri G0, i32imm:$imm, 13)
4155
0
      AsmString = "tcc %xcc, $\x02";
4156
0
      break;
4157
0
    }
4158
1.27k
    if (MCInst_getNumOperands(MI) == 3 &&
4159
1.27k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4160
1.27k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4161
1.27k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4162
1.27k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4163
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4164
39
      AsmString = "tcs %xcc, $\x01 + $\x02";
4165
39
      break;
4166
39
    }
4167
1.23k
    if (MCInst_getNumOperands(MI) == 3 &&
4168
1.23k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4169
1.23k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4170
1.23k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4171
      // (TXCCri G0, i32imm:$imm, 5)
4172
0
      AsmString = "tcs %xcc, $\x02";
4173
0
      break;
4174
0
    }
4175
1.23k
    if (MCInst_getNumOperands(MI) == 3 &&
4176
1.23k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4177
1.23k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4178
1.23k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4179
1.23k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4180
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4181
52
      AsmString = "tpos %xcc, $\x01 + $\x02";
4182
52
      break;
4183
52
    }
4184
1.18k
    if (MCInst_getNumOperands(MI) == 3 &&
4185
1.18k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4186
1.18k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4187
1.18k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4188
      // (TXCCri G0, i32imm:$imm, 14)
4189
0
      AsmString = "tpos %xcc, $\x02";
4190
0
      break;
4191
0
    }
4192
1.18k
    if (MCInst_getNumOperands(MI) == 3 &&
4193
1.18k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4194
1.18k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4195
1.18k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4196
1.18k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4197
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4198
77
      AsmString = "tneg %xcc, $\x01 + $\x02";
4199
77
      break;
4200
77
    }
4201
1.10k
    if (MCInst_getNumOperands(MI) == 3 &&
4202
1.10k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4203
1.10k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4204
1.10k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4205
      // (TXCCri G0, i32imm:$imm, 6)
4206
0
      AsmString = "tneg %xcc, $\x02";
4207
0
      break;
4208
0
    }
4209
1.10k
    if (MCInst_getNumOperands(MI) == 3 &&
4210
1.10k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4211
1.10k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4212
1.10k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4213
1.10k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4214
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4215
98
      AsmString = "tvc %xcc, $\x01 + $\x02";
4216
98
      break;
4217
98
    }
4218
1.00k
    if (MCInst_getNumOperands(MI) == 3 &&
4219
1.00k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4220
1.00k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4221
1.00k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4222
      // (TXCCri G0, i32imm:$imm, 15)
4223
0
      AsmString = "tvc %xcc, $\x02";
4224
0
      break;
4225
0
    }
4226
1.00k
    if (MCInst_getNumOperands(MI) == 3 &&
4227
1.00k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4228
1.00k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4229
1.00k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4230
1.00k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4231
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4232
1.00k
      AsmString = "tvs %xcc, $\x01 + $\x02";
4233
1.00k
      break;
4234
1.00k
    }
4235
0
    if (MCInst_getNumOperands(MI) == 3 &&
4236
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4237
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4238
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4239
      // (TXCCri G0, i32imm:$imm, 7)
4240
0
      AsmString = "tvs %xcc, $\x02";
4241
0
      break;
4242
0
    }
4243
0
    return NULL;
4244
2.52k
  case SP_TXCCrr:
4245
2.52k
    if (MCInst_getNumOperands(MI) == 3 &&
4246
2.52k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4247
2.52k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4248
2.52k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4249
2.52k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4250
2.52k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4251
2.52k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4252
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4253
101
      AsmString = "ta %xcc, $\x01 + $\x02";
4254
101
      break;
4255
101
    }
4256
2.42k
    if (MCInst_getNumOperands(MI) == 3 &&
4257
2.42k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4258
2.42k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4259
2.42k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4260
2.42k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4261
2.42k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4262
      // (TXCCrr G0, IntRegs:$rs2, 8)
4263
0
      AsmString = "ta %xcc, $\x02";
4264
0
      break;
4265
0
    }
4266
2.42k
    if (MCInst_getNumOperands(MI) == 3 &&
4267
2.42k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4268
2.42k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4269
2.42k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4270
2.42k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4271
2.42k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4272
2.42k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4273
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4274
25
      AsmString = "tn %xcc, $\x01 + $\x02";
4275
25
      break;
4276
25
    }
4277
2.40k
    if (MCInst_getNumOperands(MI) == 3 &&
4278
2.40k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4279
2.40k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4280
2.40k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4281
2.40k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4282
2.40k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4283
      // (TXCCrr G0, IntRegs:$rs2, 0)
4284
0
      AsmString = "tn %xcc, $\x02";
4285
0
      break;
4286
0
    }
4287
2.40k
    if (MCInst_getNumOperands(MI) == 3 &&
4288
2.40k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4289
2.40k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4290
2.40k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4291
2.40k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4292
2.40k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4293
2.40k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4294
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4295
210
      AsmString = "tne %xcc, $\x01 + $\x02";
4296
210
      break;
4297
210
    }
4298
2.19k
    if (MCInst_getNumOperands(MI) == 3 &&
4299
2.19k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4300
2.19k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4301
2.19k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4302
2.19k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4303
2.19k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4304
      // (TXCCrr G0, IntRegs:$rs2, 9)
4305
0
      AsmString = "tne %xcc, $\x02";
4306
0
      break;
4307
0
    }
4308
2.19k
    if (MCInst_getNumOperands(MI) == 3 &&
4309
2.19k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4310
2.19k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4311
2.19k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4312
2.19k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4313
2.19k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4314
2.19k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4315
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4316
91
      AsmString = "te %xcc, $\x01 + $\x02";
4317
91
      break;
4318
91
    }
4319
2.09k
    if (MCInst_getNumOperands(MI) == 3 &&
4320
2.09k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4321
2.09k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4322
2.09k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4323
2.09k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4324
2.09k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4325
      // (TXCCrr G0, IntRegs:$rs2, 1)
4326
0
      AsmString = "te %xcc, $\x02";
4327
0
      break;
4328
0
    }
4329
2.09k
    if (MCInst_getNumOperands(MI) == 3 &&
4330
2.09k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4331
2.09k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4332
2.09k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4333
2.09k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4334
2.09k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4335
2.09k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4336
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4337
87
      AsmString = "tg %xcc, $\x01 + $\x02";
4338
87
      break;
4339
87
    }
4340
2.01k
    if (MCInst_getNumOperands(MI) == 3 &&
4341
2.01k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4342
2.01k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4343
2.01k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4344
2.01k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4345
2.01k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4346
      // (TXCCrr G0, IntRegs:$rs2, 10)
4347
0
      AsmString = "tg %xcc, $\x02";
4348
0
      break;
4349
0
    }
4350
2.01k
    if (MCInst_getNumOperands(MI) == 3 &&
4351
2.01k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4352
2.01k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4353
2.01k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4354
2.01k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4355
2.01k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4356
2.01k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4357
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4358
30
      AsmString = "tle %xcc, $\x01 + $\x02";
4359
30
      break;
4360
30
    }
4361
1.98k
    if (MCInst_getNumOperands(MI) == 3 &&
4362
1.98k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4363
1.98k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4364
1.98k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4365
1.98k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4366
1.98k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4367
      // (TXCCrr G0, IntRegs:$rs2, 2)
4368
0
      AsmString = "tle %xcc, $\x02";
4369
0
      break;
4370
0
    }
4371
1.98k
    if (MCInst_getNumOperands(MI) == 3 &&
4372
1.98k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4373
1.98k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4374
1.98k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4375
1.98k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4376
1.98k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4377
1.98k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4378
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4379
29
      AsmString = "tge %xcc, $\x01 + $\x02";
4380
29
      break;
4381
29
    }
4382
1.95k
    if (MCInst_getNumOperands(MI) == 3 &&
4383
1.95k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4384
1.95k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4385
1.95k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4386
1.95k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4387
1.95k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4388
      // (TXCCrr G0, IntRegs:$rs2, 11)
4389
0
      AsmString = "tge %xcc, $\x02";
4390
0
      break;
4391
0
    }
4392
1.95k
    if (MCInst_getNumOperands(MI) == 3 &&
4393
1.95k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4394
1.95k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4395
1.95k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4396
1.95k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4397
1.95k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4398
1.95k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4399
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4400
558
      AsmString = "tl %xcc, $\x01 + $\x02";
4401
558
      break;
4402
558
    }
4403
1.39k
    if (MCInst_getNumOperands(MI) == 3 &&
4404
1.39k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4405
1.39k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4406
1.39k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4407
1.39k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4408
1.39k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4409
      // (TXCCrr G0, IntRegs:$rs2, 3)
4410
0
      AsmString = "tl %xcc, $\x02";
4411
0
      break;
4412
0
    }
4413
1.39k
    if (MCInst_getNumOperands(MI) == 3 &&
4414
1.39k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4415
1.39k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4416
1.39k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4417
1.39k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4418
1.39k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4419
1.39k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4420
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4421
6
      AsmString = "tgu %xcc, $\x01 + $\x02";
4422
6
      break;
4423
6
    }
4424
1.38k
    if (MCInst_getNumOperands(MI) == 3 &&
4425
1.38k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4426
1.38k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4427
1.38k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4428
1.38k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4429
1.38k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4430
      // (TXCCrr G0, IntRegs:$rs2, 12)
4431
0
      AsmString = "tgu %xcc, $\x02";
4432
0
      break;
4433
0
    }
4434
1.38k
    if (MCInst_getNumOperands(MI) == 3 &&
4435
1.38k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4436
1.38k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4437
1.38k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4438
1.38k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4439
1.38k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4440
1.38k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4441
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4442
23
      AsmString = "tleu %xcc, $\x01 + $\x02";
4443
23
      break;
4444
23
    }
4445
1.36k
    if (MCInst_getNumOperands(MI) == 3 &&
4446
1.36k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4447
1.36k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4448
1.36k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4449
1.36k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4450
1.36k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4451
      // (TXCCrr G0, IntRegs:$rs2, 4)
4452
0
      AsmString = "tleu %xcc, $\x02";
4453
0
      break;
4454
0
    }
4455
1.36k
    if (MCInst_getNumOperands(MI) == 3 &&
4456
1.36k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4457
1.36k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4458
1.36k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4459
1.36k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4460
1.36k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4461
1.36k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4462
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4463
67
      AsmString = "tcc %xcc, $\x01 + $\x02";
4464
67
      break;
4465
67
    }
4466
1.29k
    if (MCInst_getNumOperands(MI) == 3 &&
4467
1.29k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4468
1.29k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4469
1.29k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4470
1.29k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4471
1.29k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4472
      // (TXCCrr G0, IntRegs:$rs2, 13)
4473
0
      AsmString = "tcc %xcc, $\x02";
4474
0
      break;
4475
0
    }
4476
1.29k
    if (MCInst_getNumOperands(MI) == 3 &&
4477
1.29k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4478
1.29k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4479
1.29k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4480
1.29k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4481
1.29k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4482
1.29k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4483
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4484
366
      AsmString = "tcs %xcc, $\x01 + $\x02";
4485
366
      break;
4486
366
    }
4487
933
    if (MCInst_getNumOperands(MI) == 3 &&
4488
933
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4489
933
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4490
933
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4491
933
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4492
933
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4493
      // (TXCCrr G0, IntRegs:$rs2, 5)
4494
0
      AsmString = "tcs %xcc, $\x02";
4495
0
      break;
4496
0
    }
4497
933
    if (MCInst_getNumOperands(MI) == 3 &&
4498
933
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4499
933
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4500
933
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4501
933
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4502
933
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4503
933
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4504
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4505
73
      AsmString = "tpos %xcc, $\x01 + $\x02";
4506
73
      break;
4507
73
    }
4508
860
    if (MCInst_getNumOperands(MI) == 3 &&
4509
860
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4510
860
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4511
860
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4512
860
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4513
860
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4514
      // (TXCCrr G0, IntRegs:$rs2, 14)
4515
0
      AsmString = "tpos %xcc, $\x02";
4516
0
      break;
4517
0
    }
4518
860
    if (MCInst_getNumOperands(MI) == 3 &&
4519
860
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4520
860
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4521
860
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4522
860
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4523
860
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4524
860
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4525
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4526
10
      AsmString = "tneg %xcc, $\x01 + $\x02";
4527
10
      break;
4528
10
    }
4529
850
    if (MCInst_getNumOperands(MI) == 3 &&
4530
850
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4531
850
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4532
850
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4533
850
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4534
850
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4535
      // (TXCCrr G0, IntRegs:$rs2, 6)
4536
0
      AsmString = "tneg %xcc, $\x02";
4537
0
      break;
4538
0
    }
4539
850
    if (MCInst_getNumOperands(MI) == 3 &&
4540
850
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4541
850
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4542
850
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4543
850
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4544
850
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4545
850
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4546
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4547
45
      AsmString = "tvc %xcc, $\x01 + $\x02";
4548
45
      break;
4549
45
    }
4550
805
    if (MCInst_getNumOperands(MI) == 3 &&
4551
805
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4552
805
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4553
805
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4554
805
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4555
805
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4556
      // (TXCCrr G0, IntRegs:$rs2, 15)
4557
0
      AsmString = "tvc %xcc, $\x02";
4558
0
      break;
4559
0
    }
4560
805
    if (MCInst_getNumOperands(MI) == 3 &&
4561
805
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4562
805
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4563
805
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4564
805
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4565
805
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4566
805
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4567
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4568
805
      AsmString = "tvs %xcc, $\x01 + $\x02";
4569
805
      break;
4570
805
    }
4571
0
    if (MCInst_getNumOperands(MI) == 3 &&
4572
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4573
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4574
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4575
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4576
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4577
      // (TXCCrr G0, IntRegs:$rs2, 7)
4578
0
      AsmString = "tvs %xcc, $\x02";
4579
0
      break;
4580
0
    }
4581
0
    return NULL;
4582
56
  case SP_V9FCMPD:
4583
56
    if (MCInst_getNumOperands(MI) == 3 &&
4584
56
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4585
56
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4586
56
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4587
56
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4588
56
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4589
      // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4590
15
      AsmString = "fcmpd $\x02, $\x03";
4591
15
      break;
4592
15
    }
4593
41
    return NULL;
4594
309
  case SP_V9FCMPED:
4595
309
    if (MCInst_getNumOperands(MI) == 3 &&
4596
309
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4597
309
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4598
309
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4599
309
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4600
309
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4601
      // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4602
298
      AsmString = "fcmped $\x02, $\x03";
4603
298
      break;
4604
298
    }
4605
11
    return NULL;
4606
269
  case SP_V9FCMPEQ:
4607
269
    if (MCInst_getNumOperands(MI) == 3 &&
4608
269
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4609
269
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4610
269
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4611
269
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4612
269
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4613
      // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4614
32
      AsmString = "fcmpeq $\x02, $\x03";
4615
32
      break;
4616
32
    }
4617
237
    return NULL;
4618
426
  case SP_V9FCMPES:
4619
426
    if (MCInst_getNumOperands(MI) == 3 &&
4620
426
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4621
426
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4622
426
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4623
426
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4624
426
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4625
      // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4626
403
      AsmString = "fcmpes $\x02, $\x03";
4627
403
      break;
4628
403
    }
4629
23
    return NULL;
4630
218
  case SP_V9FCMPQ:
4631
218
    if (MCInst_getNumOperands(MI) == 3 &&
4632
218
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4633
218
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4634
218
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4635
218
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4636
218
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4637
      // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4638
27
      AsmString = "fcmpq $\x02, $\x03";
4639
27
      break;
4640
27
    }
4641
191
    return NULL;
4642
178
  case SP_V9FCMPS:
4643
178
    if (MCInst_getNumOperands(MI) == 3 &&
4644
178
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4645
178
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4646
178
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4647
178
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4648
178
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4649
      // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4650
23
      AsmString = "fcmps $\x02, $\x03";
4651
23
      break;
4652
23
    }
4653
155
    return NULL;
4654
68
  case SP_V9FMOVD_FCC:
4655
68
    if (MCInst_getNumOperands(MI) == 4 &&
4656
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4657
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4658
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4659
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4660
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4661
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4662
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4663
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4664
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4665
0
      AsmString = "fmovda $\x02, $\x03, $\x01";
4666
0
      break;
4667
0
    }
4668
68
    if (MCInst_getNumOperands(MI) == 4 &&
4669
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4670
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4671
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4672
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4673
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4674
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4675
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4676
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4677
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4678
0
      AsmString = "fmovdn $\x02, $\x03, $\x01";
4679
0
      break;
4680
0
    }
4681
68
    if (MCInst_getNumOperands(MI) == 4 &&
4682
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4683
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4684
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4685
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4686
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4687
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4688
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4689
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4690
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4691
0
      AsmString = "fmovdu $\x02, $\x03, $\x01";
4692
0
      break;
4693
0
    }
4694
68
    if (MCInst_getNumOperands(MI) == 4 &&
4695
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4696
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4697
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4698
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4699
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4700
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4701
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4702
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4703
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4704
0
      AsmString = "fmovdg $\x02, $\x03, $\x01";
4705
0
      break;
4706
0
    }
4707
68
    if (MCInst_getNumOperands(MI) == 4 &&
4708
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4709
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4710
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4711
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4712
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4713
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4714
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4715
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4716
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4717
0
      AsmString = "fmovdug $\x02, $\x03, $\x01";
4718
0
      break;
4719
0
    }
4720
68
    if (MCInst_getNumOperands(MI) == 4 &&
4721
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4722
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4723
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4724
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4725
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4726
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4727
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4728
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4729
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4730
0
      AsmString = "fmovdl $\x02, $\x03, $\x01";
4731
0
      break;
4732
0
    }
4733
68
    if (MCInst_getNumOperands(MI) == 4 &&
4734
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4735
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4736
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4737
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4738
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4739
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4740
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4741
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4742
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4743
0
      AsmString = "fmovdul $\x02, $\x03, $\x01";
4744
0
      break;
4745
0
    }
4746
68
    if (MCInst_getNumOperands(MI) == 4 &&
4747
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4748
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4749
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4750
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4751
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4752
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4753
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4754
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4755
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4756
0
      AsmString = "fmovdlg $\x02, $\x03, $\x01";
4757
0
      break;
4758
0
    }
4759
68
    if (MCInst_getNumOperands(MI) == 4 &&
4760
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4761
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4762
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4763
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4764
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4765
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4766
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4767
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4768
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4769
0
      AsmString = "fmovdne $\x02, $\x03, $\x01";
4770
0
      break;
4771
0
    }
4772
68
    if (MCInst_getNumOperands(MI) == 4 &&
4773
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4774
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4775
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4776
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4777
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4778
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4779
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4780
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4781
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4782
0
      AsmString = "fmovde $\x02, $\x03, $\x01";
4783
0
      break;
4784
0
    }
4785
68
    if (MCInst_getNumOperands(MI) == 4 &&
4786
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4787
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4788
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4789
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4790
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4791
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4792
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4793
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4794
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4795
0
      AsmString = "fmovdue $\x02, $\x03, $\x01";
4796
0
      break;
4797
0
    }
4798
68
    if (MCInst_getNumOperands(MI) == 4 &&
4799
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4800
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4801
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4802
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4803
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4804
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4805
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4806
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4807
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4808
0
      AsmString = "fmovdge $\x02, $\x03, $\x01";
4809
0
      break;
4810
0
    }
4811
68
    if (MCInst_getNumOperands(MI) == 4 &&
4812
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4813
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4814
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4815
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4816
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4817
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4818
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4819
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4820
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4821
0
      AsmString = "fmovduge $\x02, $\x03, $\x01";
4822
0
      break;
4823
0
    }
4824
68
    if (MCInst_getNumOperands(MI) == 4 &&
4825
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4826
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4827
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4828
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4829
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4830
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4831
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4832
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4833
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4834
0
      AsmString = "fmovdle $\x02, $\x03, $\x01";
4835
0
      break;
4836
0
    }
4837
68
    if (MCInst_getNumOperands(MI) == 4 &&
4838
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4839
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4840
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4841
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4842
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4843
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4844
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4845
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4846
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4847
0
      AsmString = "fmovdule $\x02, $\x03, $\x01";
4848
0
      break;
4849
0
    }
4850
68
    if (MCInst_getNumOperands(MI) == 4 &&
4851
68
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4852
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4853
68
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4854
68
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4855
68
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4856
68
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4857
68
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4858
68
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4859
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4860
0
      AsmString = "fmovdo $\x02, $\x03, $\x01";
4861
0
      break;
4862
0
    }
4863
68
    return NULL;
4864
38
  case SP_V9FMOVQ_FCC:
4865
38
    if (MCInst_getNumOperands(MI) == 4 &&
4866
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4867
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4868
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4869
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4870
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4871
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4872
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4873
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4874
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4875
0
      AsmString = "fmovqa $\x02, $\x03, $\x01";
4876
0
      break;
4877
0
    }
4878
38
    if (MCInst_getNumOperands(MI) == 4 &&
4879
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4880
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4881
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4882
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4883
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4884
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4885
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4886
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4887
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4888
0
      AsmString = "fmovqn $\x02, $\x03, $\x01";
4889
0
      break;
4890
0
    }
4891
38
    if (MCInst_getNumOperands(MI) == 4 &&
4892
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4893
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4894
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4895
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4896
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4897
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4898
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4899
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4900
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4901
0
      AsmString = "fmovqu $\x02, $\x03, $\x01";
4902
0
      break;
4903
0
    }
4904
38
    if (MCInst_getNumOperands(MI) == 4 &&
4905
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4906
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4907
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4908
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4909
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4910
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4911
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4912
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4913
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4914
0
      AsmString = "fmovqg $\x02, $\x03, $\x01";
4915
0
      break;
4916
0
    }
4917
38
    if (MCInst_getNumOperands(MI) == 4 &&
4918
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4919
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4920
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4921
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4922
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4923
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4924
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4925
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4926
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4927
0
      AsmString = "fmovqug $\x02, $\x03, $\x01";
4928
0
      break;
4929
0
    }
4930
38
    if (MCInst_getNumOperands(MI) == 4 &&
4931
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4932
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4933
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4934
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4935
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4936
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4937
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4938
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4939
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4940
0
      AsmString = "fmovql $\x02, $\x03, $\x01";
4941
0
      break;
4942
0
    }
4943
38
    if (MCInst_getNumOperands(MI) == 4 &&
4944
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4945
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4946
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4947
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4948
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4949
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4950
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4951
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4952
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4953
0
      AsmString = "fmovqul $\x02, $\x03, $\x01";
4954
0
      break;
4955
0
    }
4956
38
    if (MCInst_getNumOperands(MI) == 4 &&
4957
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4958
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4959
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4960
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4961
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4962
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4963
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4964
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4965
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4966
0
      AsmString = "fmovqlg $\x02, $\x03, $\x01";
4967
0
      break;
4968
0
    }
4969
38
    if (MCInst_getNumOperands(MI) == 4 &&
4970
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4971
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4972
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4973
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4974
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4975
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4976
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4977
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4978
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4979
0
      AsmString = "fmovqne $\x02, $\x03, $\x01";
4980
0
      break;
4981
0
    }
4982
38
    if (MCInst_getNumOperands(MI) == 4 &&
4983
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4984
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4985
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4986
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4987
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4988
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4989
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4990
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4991
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4992
0
      AsmString = "fmovqe $\x02, $\x03, $\x01";
4993
0
      break;
4994
0
    }
4995
38
    if (MCInst_getNumOperands(MI) == 4 &&
4996
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4997
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4998
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4999
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5000
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5001
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5002
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5003
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5004
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5005
0
      AsmString = "fmovque $\x02, $\x03, $\x01";
5006
0
      break;
5007
0
    }
5008
38
    if (MCInst_getNumOperands(MI) == 4 &&
5009
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5010
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5011
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5012
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5013
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5014
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5015
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5016
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5017
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5018
0
      AsmString = "fmovqge $\x02, $\x03, $\x01";
5019
0
      break;
5020
0
    }
5021
38
    if (MCInst_getNumOperands(MI) == 4 &&
5022
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5023
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5024
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5025
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5026
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5027
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5028
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5029
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5030
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5031
0
      AsmString = "fmovquge $\x02, $\x03, $\x01";
5032
0
      break;
5033
0
    }
5034
38
    if (MCInst_getNumOperands(MI) == 4 &&
5035
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5036
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5037
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5038
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5039
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5040
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5041
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5042
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5043
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5044
0
      AsmString = "fmovqle $\x02, $\x03, $\x01";
5045
0
      break;
5046
0
    }
5047
38
    if (MCInst_getNumOperands(MI) == 4 &&
5048
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5049
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5050
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5051
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5052
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5053
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5054
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5055
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5056
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5057
0
      AsmString = "fmovqule $\x02, $\x03, $\x01";
5058
0
      break;
5059
0
    }
5060
38
    if (MCInst_getNumOperands(MI) == 4 &&
5061
38
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5062
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5063
38
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5064
38
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5065
38
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5066
38
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5067
38
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5068
38
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5069
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5070
0
      AsmString = "fmovqo $\x02, $\x03, $\x01";
5071
0
      break;
5072
0
    }
5073
38
    return NULL;
5074
57
  case SP_V9FMOVS_FCC:
5075
57
    if (MCInst_getNumOperands(MI) == 4 &&
5076
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5077
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5078
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5079
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5080
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5081
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5082
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5083
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5084
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5085
0
      AsmString = "fmovsa $\x02, $\x03, $\x01";
5086
0
      break;
5087
0
    }
5088
57
    if (MCInst_getNumOperands(MI) == 4 &&
5089
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5090
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5091
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5092
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5093
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5094
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5095
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5096
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5097
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5098
0
      AsmString = "fmovsn $\x02, $\x03, $\x01";
5099
0
      break;
5100
0
    }
5101
57
    if (MCInst_getNumOperands(MI) == 4 &&
5102
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5103
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5104
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5105
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5106
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5107
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5108
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5109
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5110
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5111
0
      AsmString = "fmovsu $\x02, $\x03, $\x01";
5112
0
      break;
5113
0
    }
5114
57
    if (MCInst_getNumOperands(MI) == 4 &&
5115
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5116
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5117
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5118
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5119
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5120
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5121
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5122
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5123
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5124
0
      AsmString = "fmovsg $\x02, $\x03, $\x01";
5125
0
      break;
5126
0
    }
5127
57
    if (MCInst_getNumOperands(MI) == 4 &&
5128
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5129
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5130
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5131
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5132
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5133
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5134
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5135
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5136
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5137
0
      AsmString = "fmovsug $\x02, $\x03, $\x01";
5138
0
      break;
5139
0
    }
5140
57
    if (MCInst_getNumOperands(MI) == 4 &&
5141
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5142
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5143
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5144
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5145
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5146
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5147
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5148
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5149
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5150
0
      AsmString = "fmovsl $\x02, $\x03, $\x01";
5151
0
      break;
5152
0
    }
5153
57
    if (MCInst_getNumOperands(MI) == 4 &&
5154
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5155
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5156
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5157
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5158
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5159
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5160
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5161
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5162
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5163
0
      AsmString = "fmovsul $\x02, $\x03, $\x01";
5164
0
      break;
5165
0
    }
5166
57
    if (MCInst_getNumOperands(MI) == 4 &&
5167
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5168
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5169
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5170
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5171
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5172
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5173
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5174
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5175
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5176
0
      AsmString = "fmovslg $\x02, $\x03, $\x01";
5177
0
      break;
5178
0
    }
5179
57
    if (MCInst_getNumOperands(MI) == 4 &&
5180
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5181
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5182
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5183
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5184
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5185
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5186
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5187
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5188
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5189
0
      AsmString = "fmovsne $\x02, $\x03, $\x01";
5190
0
      break;
5191
0
    }
5192
57
    if (MCInst_getNumOperands(MI) == 4 &&
5193
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5194
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5195
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5196
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5197
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5198
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5199
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5200
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5201
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5202
0
      AsmString = "fmovse $\x02, $\x03, $\x01";
5203
0
      break;
5204
0
    }
5205
57
    if (MCInst_getNumOperands(MI) == 4 &&
5206
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5207
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5208
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5209
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5210
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5211
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5212
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5213
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5214
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5215
0
      AsmString = "fmovsue $\x02, $\x03, $\x01";
5216
0
      break;
5217
0
    }
5218
57
    if (MCInst_getNumOperands(MI) == 4 &&
5219
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5220
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5221
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5222
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5223
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5224
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5225
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5226
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5227
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5228
0
      AsmString = "fmovsge $\x02, $\x03, $\x01";
5229
0
      break;
5230
0
    }
5231
57
    if (MCInst_getNumOperands(MI) == 4 &&
5232
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5233
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5234
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5235
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5236
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5237
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5238
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5239
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5240
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5241
0
      AsmString = "fmovsuge $\x02, $\x03, $\x01";
5242
0
      break;
5243
0
    }
5244
57
    if (MCInst_getNumOperands(MI) == 4 &&
5245
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5246
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5247
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5248
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5249
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5250
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5251
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5252
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5253
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5254
0
      AsmString = "fmovsle $\x02, $\x03, $\x01";
5255
0
      break;
5256
0
    }
5257
57
    if (MCInst_getNumOperands(MI) == 4 &&
5258
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5259
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5260
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5261
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5262
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5263
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5264
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5265
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5266
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5267
0
      AsmString = "fmovsule $\x02, $\x03, $\x01";
5268
0
      break;
5269
0
    }
5270
57
    if (MCInst_getNumOperands(MI) == 4 &&
5271
57
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5272
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5273
57
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5274
57
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5275
57
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5276
57
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5277
57
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5278
57
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5279
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5280
0
      AsmString = "fmovso $\x02, $\x03, $\x01";
5281
0
      break;
5282
0
    }
5283
57
    return NULL;
5284
173
  case SP_V9MOVFCCri:
5285
173
    if (MCInst_getNumOperands(MI) == 4 &&
5286
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5287
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5288
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5289
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5290
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5291
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5292
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5293
0
      AsmString = "mova $\x02, $\x03, $\x01";
5294
0
      break;
5295
0
    }
5296
173
    if (MCInst_getNumOperands(MI) == 4 &&
5297
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5298
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5299
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5300
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5301
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5302
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5303
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5304
0
      AsmString = "movn $\x02, $\x03, $\x01";
5305
0
      break;
5306
0
    }
5307
173
    if (MCInst_getNumOperands(MI) == 4 &&
5308
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5309
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5310
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5311
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5312
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5313
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5314
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5315
0
      AsmString = "movu $\x02, $\x03, $\x01";
5316
0
      break;
5317
0
    }
5318
173
    if (MCInst_getNumOperands(MI) == 4 &&
5319
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5320
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5321
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5322
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5323
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5324
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5325
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5326
0
      AsmString = "movg $\x02, $\x03, $\x01";
5327
0
      break;
5328
0
    }
5329
173
    if (MCInst_getNumOperands(MI) == 4 &&
5330
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5331
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5332
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5333
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5334
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5335
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5336
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5337
0
      AsmString = "movug $\x02, $\x03, $\x01";
5338
0
      break;
5339
0
    }
5340
173
    if (MCInst_getNumOperands(MI) == 4 &&
5341
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5342
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5343
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5344
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5345
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5346
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5347
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5348
0
      AsmString = "movl $\x02, $\x03, $\x01";
5349
0
      break;
5350
0
    }
5351
173
    if (MCInst_getNumOperands(MI) == 4 &&
5352
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5353
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5354
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5355
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5356
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5357
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5358
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5359
0
      AsmString = "movul $\x02, $\x03, $\x01";
5360
0
      break;
5361
0
    }
5362
173
    if (MCInst_getNumOperands(MI) == 4 &&
5363
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5364
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5365
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5366
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5367
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5368
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5369
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5370
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5371
0
      break;
5372
0
    }
5373
173
    if (MCInst_getNumOperands(MI) == 4 &&
5374
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5375
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5376
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5377
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5378
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5379
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5380
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5381
0
      AsmString = "movne $\x02, $\x03, $\x01";
5382
0
      break;
5383
0
    }
5384
173
    if (MCInst_getNumOperands(MI) == 4 &&
5385
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5386
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5387
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5388
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5389
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5390
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5391
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5392
0
      AsmString = "move $\x02, $\x03, $\x01";
5393
0
      break;
5394
0
    }
5395
173
    if (MCInst_getNumOperands(MI) == 4 &&
5396
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5397
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5398
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5399
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5400
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5401
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5402
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5403
0
      AsmString = "movue $\x02, $\x03, $\x01";
5404
0
      break;
5405
0
    }
5406
173
    if (MCInst_getNumOperands(MI) == 4 &&
5407
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5408
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5409
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5410
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5411
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5412
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5413
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5414
0
      AsmString = "movge $\x02, $\x03, $\x01";
5415
0
      break;
5416
0
    }
5417
173
    if (MCInst_getNumOperands(MI) == 4 &&
5418
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5419
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5420
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5421
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5422
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5423
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5424
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5425
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5426
0
      break;
5427
0
    }
5428
173
    if (MCInst_getNumOperands(MI) == 4 &&
5429
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5430
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5431
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5432
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5433
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5434
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5435
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5436
0
      AsmString = "movle $\x02, $\x03, $\x01";
5437
0
      break;
5438
0
    }
5439
173
    if (MCInst_getNumOperands(MI) == 4 &&
5440
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5441
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5442
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5443
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5444
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5445
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5446
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5447
0
      AsmString = "movule $\x02, $\x03, $\x01";
5448
0
      break;
5449
0
    }
5450
173
    if (MCInst_getNumOperands(MI) == 4 &&
5451
173
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5452
173
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5453
173
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5454
173
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5455
173
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5456
173
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5457
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5458
0
      AsmString = "movo $\x02, $\x03, $\x01";
5459
0
      break;
5460
0
    }
5461
173
    return NULL;
5462
92
  case SP_V9MOVFCCrr:
5463
92
    if (MCInst_getNumOperands(MI) == 4 &&
5464
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5465
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5466
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5467
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5468
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5469
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5470
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5471
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5472
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5473
0
      AsmString = "mova $\x02, $\x03, $\x01";
5474
0
      break;
5475
0
    }
5476
92
    if (MCInst_getNumOperands(MI) == 4 &&
5477
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5478
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5479
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5480
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5481
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5482
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5483
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5484
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5485
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5486
0
      AsmString = "movn $\x02, $\x03, $\x01";
5487
0
      break;
5488
0
    }
5489
92
    if (MCInst_getNumOperands(MI) == 4 &&
5490
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5491
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5492
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5493
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5494
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5495
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5496
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5497
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5498
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5499
0
      AsmString = "movu $\x02, $\x03, $\x01";
5500
0
      break;
5501
0
    }
5502
92
    if (MCInst_getNumOperands(MI) == 4 &&
5503
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5504
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5505
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5506
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5507
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5508
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5509
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5510
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5511
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5512
0
      AsmString = "movg $\x02, $\x03, $\x01";
5513
0
      break;
5514
0
    }
5515
92
    if (MCInst_getNumOperands(MI) == 4 &&
5516
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5517
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5518
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5519
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5520
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5521
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5522
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5523
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5524
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5525
0
      AsmString = "movug $\x02, $\x03, $\x01";
5526
0
      break;
5527
0
    }
5528
92
    if (MCInst_getNumOperands(MI) == 4 &&
5529
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5530
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5531
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5532
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5533
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5534
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5535
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5536
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5537
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5538
0
      AsmString = "movl $\x02, $\x03, $\x01";
5539
0
      break;
5540
0
    }
5541
92
    if (MCInst_getNumOperands(MI) == 4 &&
5542
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5543
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5544
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5545
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5546
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5547
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5548
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5549
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5550
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5551
0
      AsmString = "movul $\x02, $\x03, $\x01";
5552
0
      break;
5553
0
    }
5554
92
    if (MCInst_getNumOperands(MI) == 4 &&
5555
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5556
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5557
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5558
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5559
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5560
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5561
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5562
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5563
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5564
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5565
0
      break;
5566
0
    }
5567
92
    if (MCInst_getNumOperands(MI) == 4 &&
5568
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5569
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5570
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5571
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5572
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5573
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5574
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5575
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5576
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5577
0
      AsmString = "movne $\x02, $\x03, $\x01";
5578
0
      break;
5579
0
    }
5580
92
    if (MCInst_getNumOperands(MI) == 4 &&
5581
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5582
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5583
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5584
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5585
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5586
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5587
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5588
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5589
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5590
0
      AsmString = "move $\x02, $\x03, $\x01";
5591
0
      break;
5592
0
    }
5593
92
    if (MCInst_getNumOperands(MI) == 4 &&
5594
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5595
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5596
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5597
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5598
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5599
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5600
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5601
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5602
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5603
0
      AsmString = "movue $\x02, $\x03, $\x01";
5604
0
      break;
5605
0
    }
5606
92
    if (MCInst_getNumOperands(MI) == 4 &&
5607
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5608
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5609
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5610
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5611
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5612
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5613
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5614
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5615
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5616
0
      AsmString = "movge $\x02, $\x03, $\x01";
5617
0
      break;
5618
0
    }
5619
92
    if (MCInst_getNumOperands(MI) == 4 &&
5620
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5621
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5622
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5623
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5624
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5625
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5626
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5627
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5628
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5629
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5630
0
      break;
5631
0
    }
5632
92
    if (MCInst_getNumOperands(MI) == 4 &&
5633
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5634
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5635
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5636
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5637
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5638
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5639
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5640
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5641
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5642
0
      AsmString = "movle $\x02, $\x03, $\x01";
5643
0
      break;
5644
0
    }
5645
92
    if (MCInst_getNumOperands(MI) == 4 &&
5646
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5647
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5648
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5649
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5650
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5651
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5652
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5653
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5654
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5655
0
      AsmString = "movule $\x02, $\x03, $\x01";
5656
0
      break;
5657
0
    }
5658
92
    if (MCInst_getNumOperands(MI) == 4 &&
5659
92
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5660
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5661
92
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5662
92
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5663
92
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5664
92
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5665
92
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5666
92
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5667
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5668
0
      AsmString = "movo $\x02, $\x03, $\x01";
5669
0
      break;
5670
0
    }
5671
92
    return NULL;
5672
60.6k
  }
5673
5674
23.5k
  tmp = cs_strdup(AsmString);
5675
23.5k
  AsmMnem = tmp;
5676
152k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5677
152k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
5678
23.5k
      *AsmOps = '\0';
5679
23.5k
      AsmOps++;
5680
23.5k
      break;
5681
23.5k
    }
5682
152k
  }
5683
23.5k
  SStream_concat0(OS, AsmMnem);
5684
23.5k
  if (*AsmOps) {
5685
23.5k
    SStream_concat0(OS, "\t");
5686
23.5k
    if (strstr(AsmOps, "icc"))
5687
4.65k
      Sparc_addReg(MI, SPARC_REG_ICC);
5688
23.5k
    if (strstr(AsmOps, "xcc"))
5689
8.93k
      Sparc_addReg(MI, SPARC_REG_XCC);
5690
167k
    for (c = AsmOps; *c; c++) {
5691
144k
      if (*c == '$') {
5692
34.8k
        c += 1;
5693
34.8k
        if (*c == (char)0xff) {
5694
0
          c += 1;
5695
0
          OpIdx = *c - 1;
5696
0
          c += 1;
5697
0
          PrintMethodIdx = *c - 1;
5698
0
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5699
0
        } else
5700
34.8k
          printOperand(MI, *c - 1, OS);
5701
109k
      } else {
5702
109k
        SStream_concat(OS, "%c", *c);
5703
109k
      }
5704
144k
    }
5705
23.5k
  }
5706
23.5k
  return tmp;
5707
60.6k
}
5708
5709
#endif // PRINT_ALIAS_INSTR