/src/capstonenext/arch/TMS320C64x/TMS320C64xDisassembler.c
Line | Count | Source |
1 | | /* Capstone Disassembly Engine */ |
2 | | /* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */ |
3 | | |
4 | | #ifdef CAPSTONE_HAS_TMS320C64X |
5 | | |
6 | | #include <string.h> |
7 | | |
8 | | #include "../../cs_priv.h" |
9 | | #include "../../utils.h" |
10 | | |
11 | | #include "TMS320C64xDisassembler.h" |
12 | | |
13 | | #include "../../MCInst.h" |
14 | | #include "../../MCInstrDesc.h" |
15 | | #include "../../MCFixedLenDisassembler.h" |
16 | | #include "../../MCRegisterInfo.h" |
17 | | #include "../../MCDisassembler.h" |
18 | | #include "../../MathExtras.h" |
19 | | |
20 | | static uint64_t getFeatureBits(int mode); |
21 | | |
22 | | static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
23 | | uint64_t Address, void *Decoder); |
24 | | |
25 | | static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
26 | | uint64_t Address, |
27 | | void *Decoder); |
28 | | |
29 | | static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, uint64_t Address, |
30 | | void *Decoder); |
31 | | |
32 | | static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, uint64_t Address, |
33 | | void *Decoder); |
34 | | |
35 | | static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val, |
36 | | uint64_t Address, void *Decoder); |
37 | | |
38 | | static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val, |
39 | | uint64_t Address, void *Decoder); |
40 | | |
41 | | static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val, |
42 | | uint64_t Address, void *Decoder); |
43 | | |
44 | | static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val, |
45 | | uint64_t Address, void *Decoder); |
46 | | |
47 | | static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val, |
48 | | uint64_t Address, void *Decoder); |
49 | | |
50 | | static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val, |
51 | | uint64_t Address, void *Decoder); |
52 | | |
53 | | static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val, |
54 | | uint64_t Address, void *Decoder); |
55 | | |
56 | | static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo, |
57 | | uint64_t Address, void *Decoder); |
58 | | |
59 | | static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo, |
60 | | uint64_t Address, void *Decoder); |
61 | | |
62 | | static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val, |
63 | | uint64_t Address, void *Decoder); |
64 | | |
65 | | static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val, |
66 | | uint64_t Address, void *Decoder); |
67 | | |
68 | | static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, uint64_t Address, |
69 | | void *Decoder); |
70 | | |
71 | | static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, uint64_t Address, |
72 | | void *Decoder); |
73 | | |
74 | | static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val, |
75 | | uint64_t Address, void *Decoder); |
76 | | |
77 | | static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val, |
78 | | uint64_t Address, void *Decoder); |
79 | | |
80 | | static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val, |
81 | | uint64_t Address, void *Decoder); |
82 | | |
83 | | static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, uint64_t Address, |
84 | | void *Decoder); |
85 | | |
86 | | #include "TMS320C64xGenDisassemblerTables.inc" |
87 | | |
88 | | #define GET_REGINFO_ENUM |
89 | | #define GET_REGINFO_MC_DESC |
90 | | #include "TMS320C64xGenRegisterInfo.inc" |
91 | | |
92 | | static const unsigned GPRegsDecoderTable[] = { |
93 | | TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, |
94 | | TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, |
95 | | TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, |
96 | | TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, |
97 | | TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, |
98 | | TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, |
99 | | TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, |
100 | | TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31 |
101 | | }; |
102 | | |
103 | | static const unsigned ControlRegsDecoderTable[] = { TMS320C64x_AMR, |
104 | | TMS320C64x_CSR, |
105 | | TMS320C64x_ISR, |
106 | | TMS320C64x_ICR, |
107 | | TMS320C64x_IER, |
108 | | TMS320C64x_ISTP, |
109 | | TMS320C64x_IRP, |
110 | | TMS320C64x_NRP, |
111 | | ~0U, |
112 | | ~0U, |
113 | | TMS320C64x_TSCL, |
114 | | TMS320C64x_TSCH, |
115 | | ~0U, |
116 | | TMS320C64x_ILC, |
117 | | TMS320C64x_RILC, |
118 | | TMS320C64x_REP, |
119 | | TMS320C64x_PCE1, |
120 | | TMS320C64x_DNUM, |
121 | | ~0U, |
122 | | ~0U, |
123 | | ~0U, |
124 | | TMS320C64x_SSR, |
125 | | TMS320C64x_GPLYA, |
126 | | TMS320C64x_GPLYB, |
127 | | TMS320C64x_GFPGFR, |
128 | | TMS320C64x_DIER, |
129 | | TMS320C64x_TSR, |
130 | | TMS320C64x_ITSR, |
131 | | TMS320C64x_NTSR, |
132 | | TMS320C64x_ECR, |
133 | | ~0U, |
134 | | TMS320C64x_IERR }; |
135 | | |
136 | | static uint64_t getFeatureBits(int mode) |
137 | 5.59k | { |
138 | | // support everything |
139 | 5.59k | return (uint64_t)-1; |
140 | 5.59k | } |
141 | | |
142 | | static unsigned getReg(const unsigned *RegTable, unsigned RegNo) |
143 | 9.36k | { |
144 | 9.36k | if (RegNo > 31) |
145 | 2 | return ~0U; |
146 | 9.36k | return RegTable[RegNo]; |
147 | 9.36k | } |
148 | | |
149 | | static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
150 | | uint64_t Address, void *Decoder) |
151 | 7.25k | { |
152 | 7.25k | unsigned Reg; |
153 | | |
154 | 7.25k | if (RegNo > 31) |
155 | 0 | return MCDisassembler_Fail; |
156 | | |
157 | 7.25k | Reg = getReg(GPRegsDecoderTable, RegNo); |
158 | 7.25k | if (Reg == ~0U) |
159 | 0 | return MCDisassembler_Fail; |
160 | 7.25k | MCOperand_CreateReg0(Inst, Reg); |
161 | | |
162 | 7.25k | return MCDisassembler_Success; |
163 | 7.25k | } |
164 | | |
165 | | static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
166 | | uint64_t Address, |
167 | | void *Decoder) |
168 | 292 | { |
169 | 292 | unsigned Reg; |
170 | | |
171 | 292 | if (RegNo > 31) |
172 | 0 | return MCDisassembler_Fail; |
173 | | |
174 | 292 | Reg = getReg(ControlRegsDecoderTable, RegNo); |
175 | 292 | if (Reg == ~0U) |
176 | 0 | return MCDisassembler_Fail; |
177 | 292 | MCOperand_CreateReg0(Inst, Reg); |
178 | | |
179 | 292 | return MCDisassembler_Success; |
180 | 292 | } |
181 | | |
182 | | static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, uint64_t Address, |
183 | | void *Decoder) |
184 | 1.00k | { |
185 | 1.00k | int32_t imm; |
186 | | |
187 | 1.00k | imm = Val; |
188 | | /* Sign extend 5 bit value */ |
189 | 1.00k | if (imm & (1 << (5 - 1))) |
190 | 517 | imm |= ~((1 << 5) - 1); |
191 | | |
192 | 1.00k | MCOperand_CreateImm0(Inst, imm); |
193 | | |
194 | 1.00k | return MCDisassembler_Success; |
195 | 1.00k | } |
196 | | |
197 | | static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, uint64_t Address, |
198 | | void *Decoder) |
199 | 436 | { |
200 | 436 | int32_t imm; |
201 | | |
202 | 436 | imm = Val; |
203 | | /* Sign extend 16 bit value */ |
204 | 436 | if (imm & (1 << (16 - 1))) |
205 | 270 | imm |= ~((1 << 16) - 1); |
206 | | |
207 | 436 | MCOperand_CreateImm0(Inst, imm); |
208 | | |
209 | 436 | return MCDisassembler_Success; |
210 | 436 | } |
211 | | |
212 | | static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val, |
213 | | uint64_t Address, void *Decoder) |
214 | 16 | { |
215 | 16 | int32_t imm; |
216 | | |
217 | 16 | imm = Val; |
218 | | /* Sign extend 7 bit value */ |
219 | 16 | if (imm & (1 << (7 - 1))) |
220 | 14 | imm |= ~((1 << 7) - 1); |
221 | | |
222 | | /* Address is relative to the address of the first instruction in the fetch packet */ |
223 | 16 | MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); |
224 | | |
225 | 16 | return MCDisassembler_Success; |
226 | 16 | } |
227 | | |
228 | | static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val, |
229 | | uint64_t Address, void *Decoder) |
230 | 172 | { |
231 | 172 | int32_t imm; |
232 | | |
233 | 172 | imm = Val; |
234 | | /* Sign extend 10 bit value */ |
235 | 172 | if (imm & (1 << (10 - 1))) |
236 | 8 | imm |= ~((1 << 10) - 1); |
237 | | |
238 | | /* Address is relative to the address of the first instruction in the fetch packet */ |
239 | 172 | MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); |
240 | | |
241 | 172 | return MCDisassembler_Success; |
242 | 172 | } |
243 | | |
244 | | static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val, |
245 | | uint64_t Address, void *Decoder) |
246 | 28 | { |
247 | 28 | int32_t imm; |
248 | | |
249 | 28 | imm = Val; |
250 | | /* Sign extend 12 bit value */ |
251 | 28 | if (imm & (1 << (12 - 1))) |
252 | 6 | imm |= ~((1 << 12) - 1); |
253 | | |
254 | | /* Address is relative to the address of the first instruction in the fetch packet */ |
255 | 28 | MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); |
256 | | |
257 | 28 | return MCDisassembler_Success; |
258 | 28 | } |
259 | | |
260 | | static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val, |
261 | | uint64_t Address, void *Decoder) |
262 | 269 | { |
263 | 269 | int32_t imm; |
264 | | |
265 | 269 | imm = Val; |
266 | | /* Sign extend 21 bit value */ |
267 | 269 | if (imm & (1 << (21 - 1))) |
268 | 19 | imm |= ~((1 << 21) - 1); |
269 | | |
270 | | /* Address is relative to the address of the first instruction in the fetch packet */ |
271 | 269 | MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); |
272 | | |
273 | 269 | return MCDisassembler_Success; |
274 | 269 | } |
275 | | |
276 | | static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val, |
277 | | uint64_t Address, void *Decoder) |
278 | 177 | { |
279 | 177 | return DecodeMemOperandSc(Inst, Val | (1 << 15), Address, Decoder); |
280 | 177 | } |
281 | | |
282 | | static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val, |
283 | | uint64_t Address, void *Decoder) |
284 | 223 | { |
285 | 223 | uint8_t scaled, base, offset, mode, unit; |
286 | 223 | unsigned basereg, offsetreg; |
287 | | |
288 | 223 | scaled = (Val >> 15) & 1; |
289 | 223 | base = (Val >> 10) & 0x1f; |
290 | 223 | offset = (Val >> 5) & 0x1f; |
291 | 223 | mode = (Val >> 1) & 0xf; |
292 | 223 | unit = Val & 1; |
293 | | |
294 | 223 | if ((base >= TMS320C64X_REG_A0) && (base <= TMS320C64X_REG_A31)) |
295 | 0 | base = (base - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); |
296 | | // base cannot be a B register, because it was ANDed above with 0x1f. |
297 | | // And the TMS320C64X_REG_B0 > 31 |
298 | 223 | basereg = getReg(GPRegsDecoderTable, base); |
299 | 223 | if (basereg == ~0U) |
300 | 0 | return MCDisassembler_Fail; |
301 | | |
302 | 223 | switch (mode) { |
303 | 70 | case 0: |
304 | 120 | case 1: |
305 | 124 | case 8: |
306 | 128 | case 9: |
307 | 169 | case 10: |
308 | 194 | case 11: |
309 | 194 | MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) | |
310 | 194 | (offset << 5) | (mode << 1) | |
311 | 194 | unit); |
312 | 194 | break; |
313 | 2 | case 4: |
314 | 3 | case 5: |
315 | 16 | case 12: |
316 | 16 | case 13: |
317 | 26 | case 14: |
318 | 29 | case 15: |
319 | 29 | if ((offset >= TMS320C64X_REG_A0) && |
320 | 2 | (offset <= TMS320C64X_REG_A31)) |
321 | 2 | offset = (offset - TMS320C64X_REG_A0 + |
322 | 2 | TMS320C64X_REG_B0); |
323 | | // offset cannot be a B register, because it was ANDed above with 0x1f. |
324 | | // And the TMS320C64X_REG_B0 > 31 |
325 | 29 | offsetreg = getReg(GPRegsDecoderTable, offset); |
326 | 29 | if (offsetreg == ~0U) |
327 | 2 | return MCDisassembler_Fail; |
328 | 27 | MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) | |
329 | 27 | (offsetreg << 5) | |
330 | 27 | (mode << 1) | unit); |
331 | 27 | break; |
332 | 0 | default: |
333 | 0 | return MCDisassembler_Fail; |
334 | 223 | } |
335 | | |
336 | 221 | return MCDisassembler_Success; |
337 | 223 | } |
338 | | |
339 | | static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val, |
340 | | uint64_t Address, void *Decoder) |
341 | 677 | { |
342 | 677 | uint16_t offset; |
343 | 677 | unsigned basereg; |
344 | | |
345 | 677 | if (Val & 1) |
346 | 473 | basereg = TMS320C64X_REG_B15; |
347 | 204 | else |
348 | 204 | basereg = TMS320C64X_REG_B14; |
349 | | |
350 | 677 | offset = (Val >> 1) & 0x7fff; |
351 | 677 | MCOperand_CreateImm0(Inst, (offset << 7) | basereg); |
352 | | |
353 | 677 | return MCDisassembler_Success; |
354 | 677 | } |
355 | | |
356 | | static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo, |
357 | | uint64_t Address, void *Decoder) |
358 | 1.52k | { |
359 | 1.52k | unsigned Reg; |
360 | | |
361 | 1.52k | if (RegNo > 31) |
362 | 0 | return MCDisassembler_Fail; |
363 | | |
364 | 1.52k | Reg = getReg(GPRegsDecoderTable, RegNo); |
365 | 1.52k | MCOperand_CreateReg0(Inst, Reg); |
366 | | |
367 | 1.52k | return MCDisassembler_Success; |
368 | 1.52k | } |
369 | | |
370 | | static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo, |
371 | | uint64_t Address, void *Decoder) |
372 | 46 | { |
373 | 46 | unsigned Reg; |
374 | | |
375 | 46 | if (RegNo > 15) |
376 | 0 | return MCDisassembler_Fail; |
377 | | |
378 | 46 | Reg = getReg(GPRegsDecoderTable, RegNo << 1); |
379 | 46 | MCOperand_CreateReg0(Inst, Reg); |
380 | | |
381 | 46 | return MCDisassembler_Success; |
382 | 46 | } |
383 | | |
384 | | static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val, |
385 | | uint64_t Address, void *Decoder) |
386 | 5.57k | { |
387 | 5.57k | DecodeStatus ret = MCDisassembler_Success; |
388 | | |
389 | 5.57k | if (!Inst->flat_insn->detail) |
390 | 0 | return MCDisassembler_Success; |
391 | | |
392 | 5.57k | switch (Val) { |
393 | 962 | case 0: |
394 | 1.60k | case 7: |
395 | 1.60k | Inst->flat_insn->detail->tms320c64x.condition.reg = |
396 | 1.60k | TMS320C64X_REG_INVALID; |
397 | 1.60k | break; |
398 | 499 | case 1: |
399 | 499 | Inst->flat_insn->detail->tms320c64x.condition.reg = |
400 | 499 | TMS320C64X_REG_B0; |
401 | 499 | break; |
402 | 789 | case 2: |
403 | 789 | Inst->flat_insn->detail->tms320c64x.condition.reg = |
404 | 789 | TMS320C64X_REG_B1; |
405 | 789 | break; |
406 | 769 | case 3: |
407 | 769 | Inst->flat_insn->detail->tms320c64x.condition.reg = |
408 | 769 | TMS320C64X_REG_B2; |
409 | 769 | break; |
410 | 824 | case 4: |
411 | 824 | Inst->flat_insn->detail->tms320c64x.condition.reg = |
412 | 824 | TMS320C64X_REG_A1; |
413 | 824 | break; |
414 | 646 | case 5: |
415 | 646 | Inst->flat_insn->detail->tms320c64x.condition.reg = |
416 | 646 | TMS320C64X_REG_A2; |
417 | 646 | break; |
418 | 439 | case 6: |
419 | 439 | Inst->flat_insn->detail->tms320c64x.condition.reg = |
420 | 439 | TMS320C64X_REG_A0; |
421 | 439 | break; |
422 | 0 | default: |
423 | 0 | Inst->flat_insn->detail->tms320c64x.condition.reg = |
424 | 0 | TMS320C64X_REG_INVALID; |
425 | 0 | ret = MCDisassembler_Fail; |
426 | 0 | break; |
427 | 5.57k | } |
428 | | |
429 | 5.57k | return ret; |
430 | 5.57k | } |
431 | | |
432 | | static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val, |
433 | | uint64_t Address, void *Decoder) |
434 | 5.57k | { |
435 | 5.57k | DecodeStatus ret = MCDisassembler_Success; |
436 | | |
437 | 5.57k | if (!Inst->flat_insn->detail) |
438 | 0 | return MCDisassembler_Success; |
439 | | |
440 | 5.57k | switch (Val) { |
441 | 2.64k | case 0: |
442 | 2.64k | Inst->flat_insn->detail->tms320c64x.condition.zero = 0; |
443 | 2.64k | break; |
444 | 2.92k | case 1: |
445 | 2.92k | Inst->flat_insn->detail->tms320c64x.condition.zero = 1; |
446 | 2.92k | break; |
447 | 0 | default: |
448 | 0 | Inst->flat_insn->detail->tms320c64x.condition.zero = 0; |
449 | 0 | ret = MCDisassembler_Fail; |
450 | 0 | break; |
451 | 5.57k | } |
452 | | |
453 | 5.57k | return ret; |
454 | 5.57k | } |
455 | | |
456 | | static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, uint64_t Address, |
457 | | void *Decoder) |
458 | 5.57k | { |
459 | 5.57k | DecodeStatus ret = MCDisassembler_Success; |
460 | 5.57k | MCOperand *op; |
461 | 5.57k | int i; |
462 | | |
463 | | /* This is pretty messy, probably we should find a better way */ |
464 | 5.57k | if (Val == 1) { |
465 | 7.60k | for (i = 0; i < Inst->size; i++) { |
466 | 5.34k | op = &Inst->Operands[i]; |
467 | 5.34k | if (op->Kind == kRegister) { |
468 | 3.73k | if ((op->RegVal >= TMS320C64X_REG_A0) && |
469 | 3.47k | (op->RegVal <= TMS320C64X_REG_A31)) |
470 | 3.35k | op->RegVal = (op->RegVal - |
471 | 3.35k | TMS320C64X_REG_A0 + |
472 | 3.35k | TMS320C64X_REG_B0); |
473 | 387 | else if ((op->RegVal >= TMS320C64X_REG_B0) && |
474 | 123 | (op->RegVal <= TMS320C64X_REG_B31)) |
475 | 105 | op->RegVal = (op->RegVal - |
476 | 105 | TMS320C64X_REG_B0 + |
477 | 105 | TMS320C64X_REG_A0); |
478 | 3.73k | } |
479 | 5.34k | } |
480 | 2.26k | } |
481 | | |
482 | 5.57k | if (!Inst->flat_insn->detail) |
483 | 0 | return MCDisassembler_Success; |
484 | | |
485 | 5.57k | switch (Val) { |
486 | 3.30k | case 0: |
487 | 3.30k | Inst->flat_insn->detail->tms320c64x.funit.side = 1; |
488 | 3.30k | break; |
489 | 2.26k | case 1: |
490 | 2.26k | Inst->flat_insn->detail->tms320c64x.funit.side = 2; |
491 | 2.26k | break; |
492 | 0 | default: |
493 | 0 | Inst->flat_insn->detail->tms320c64x.funit.side = 0; |
494 | 0 | ret = MCDisassembler_Fail; |
495 | 0 | break; |
496 | 5.57k | } |
497 | | |
498 | 5.57k | return ret; |
499 | 5.57k | } |
500 | | |
501 | | static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, uint64_t Address, |
502 | | void *Decoder) |
503 | 5.57k | { |
504 | 5.57k | DecodeStatus ret = MCDisassembler_Success; |
505 | | |
506 | 5.57k | if (!Inst->flat_insn->detail) |
507 | 0 | return MCDisassembler_Success; |
508 | | |
509 | 5.57k | switch (Val) { |
510 | 3.06k | case 0: |
511 | 3.06k | Inst->flat_insn->detail->tms320c64x.parallel = 0; |
512 | 3.06k | break; |
513 | 2.50k | case 1: |
514 | 2.50k | Inst->flat_insn->detail->tms320c64x.parallel = 1; |
515 | 2.50k | break; |
516 | 0 | default: |
517 | 0 | Inst->flat_insn->detail->tms320c64x.parallel = -1; |
518 | 0 | ret = MCDisassembler_Fail; |
519 | 0 | break; |
520 | 5.57k | } |
521 | | |
522 | 5.57k | return ret; |
523 | 5.57k | } |
524 | | |
525 | | static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val, |
526 | | uint64_t Address, void *Decoder) |
527 | 226 | { |
528 | 226 | DecodeStatus ret = MCDisassembler_Success; |
529 | 226 | MCOperand *op; |
530 | | |
531 | 226 | if (!Inst->flat_insn->detail) |
532 | 0 | return MCDisassembler_Success; |
533 | | |
534 | 226 | switch (Val) { |
535 | 164 | case 0: |
536 | 164 | Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0; |
537 | 164 | break; |
538 | 62 | case 1: |
539 | 62 | Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1; |
540 | 62 | op = &Inst->Operands[0]; |
541 | 62 | if (op->Kind == kRegister) { |
542 | 62 | if ((op->RegVal >= TMS320C64X_REG_A0) && |
543 | 62 | (op->RegVal <= TMS320C64X_REG_A31)) |
544 | 62 | op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + |
545 | 62 | TMS320C64X_REG_B0); |
546 | 0 | else if ((op->RegVal >= TMS320C64X_REG_B0) && |
547 | 0 | (op->RegVal <= TMS320C64X_REG_B31)) |
548 | 0 | op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + |
549 | 0 | TMS320C64X_REG_A0); |
550 | 62 | } |
551 | 62 | break; |
552 | 0 | default: |
553 | 0 | Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1; |
554 | 0 | ret = MCDisassembler_Fail; |
555 | 0 | break; |
556 | 226 | } |
557 | | |
558 | 226 | return ret; |
559 | 226 | } |
560 | | |
561 | | static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val, |
562 | | uint64_t Address, void *Decoder) |
563 | 2.07k | { |
564 | 2.07k | DecodeStatus ret = MCDisassembler_Success; |
565 | 2.07k | MCOperand *op; |
566 | | |
567 | 2.07k | if (!Inst->flat_insn->detail) |
568 | 0 | return MCDisassembler_Success; |
569 | | |
570 | 2.07k | switch (Val) { |
571 | 1.13k | case 0: |
572 | 1.13k | Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0; |
573 | 1.13k | break; |
574 | 938 | case 1: |
575 | 938 | Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1; |
576 | 938 | op = &Inst->Operands[1]; |
577 | 938 | if (op->Kind == kRegister) { |
578 | 788 | if ((op->RegVal >= TMS320C64X_REG_A0) && |
579 | 522 | (op->RegVal <= TMS320C64X_REG_A31)) |
580 | 504 | op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + |
581 | 504 | TMS320C64X_REG_B0); |
582 | 284 | else if ((op->RegVal >= TMS320C64X_REG_B0) && |
583 | 18 | (op->RegVal <= TMS320C64X_REG_B31)) |
584 | 0 | op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + |
585 | 0 | TMS320C64X_REG_A0); |
586 | 788 | } |
587 | 938 | break; |
588 | 0 | default: |
589 | 0 | Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1; |
590 | 0 | ret = MCDisassembler_Fail; |
591 | 0 | break; |
592 | 2.07k | } |
593 | | |
594 | 2.07k | return ret; |
595 | 2.07k | } |
596 | | |
597 | | static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val, |
598 | | uint64_t Address, void *Decoder) |
599 | 1.17k | { |
600 | 1.17k | DecodeStatus ret = MCDisassembler_Success; |
601 | 1.17k | MCOperand *op; |
602 | | |
603 | 1.17k | if (!Inst->flat_insn->detail) |
604 | 0 | return MCDisassembler_Success; |
605 | | |
606 | 1.17k | switch (Val) { |
607 | 493 | case 0: |
608 | 493 | Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0; |
609 | 493 | break; |
610 | 679 | case 1: |
611 | 679 | Inst->flat_insn->detail->tms320c64x.funit.crosspath = 2; |
612 | 679 | op = &Inst->Operands[2]; |
613 | 679 | if (op->Kind == kRegister) { |
614 | 25 | if ((op->RegVal >= TMS320C64X_REG_A0) && |
615 | 25 | (op->RegVal <= TMS320C64X_REG_A31)) |
616 | 25 | op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + |
617 | 25 | TMS320C64X_REG_B0); |
618 | 0 | else if ((op->RegVal >= TMS320C64X_REG_B0) && |
619 | 0 | (op->RegVal <= TMS320C64X_REG_B31)) |
620 | 0 | op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + |
621 | 0 | TMS320C64X_REG_A0); |
622 | 25 | } |
623 | 679 | break; |
624 | 0 | default: |
625 | 0 | Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1; |
626 | 0 | ret = MCDisassembler_Fail; |
627 | 0 | break; |
628 | 1.17k | } |
629 | | |
630 | 1.17k | return ret; |
631 | 1.17k | } |
632 | | |
633 | | static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, uint64_t Address, |
634 | | void *Decoder) |
635 | 151 | { |
636 | 151 | MCOperand_CreateImm0(Inst, Val + 1); |
637 | | |
638 | 151 | return MCDisassembler_Success; |
639 | 151 | } |
640 | | |
641 | | #define GET_INSTRINFO_ENUM |
642 | | #include "TMS320C64xGenInstrInfo.inc" |
643 | | |
644 | | bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len, |
645 | | MCInst *MI, uint16_t *size, uint64_t address, |
646 | | void *info) |
647 | 5.64k | { |
648 | 5.64k | uint32_t insn; |
649 | 5.64k | DecodeStatus result; |
650 | | |
651 | 5.64k | if (code_len < 4) { |
652 | 56 | *size = 0; |
653 | 56 | return MCDisassembler_Fail; |
654 | 56 | } |
655 | | |
656 | 5.59k | if (MI->flat_insn->detail) |
657 | 5.59k | memset(MI->flat_insn->detail, 0, |
658 | 5.59k | offsetof(cs_detail, tms320c64x) + sizeof(cs_tms320c64x)); |
659 | | |
660 | 5.59k | insn = readBytes32(MI, code); |
661 | 5.59k | result = |
662 | 5.59k | decodeInstruction_4(DecoderTable32, MI, insn, address, info, 0); |
663 | | |
664 | 5.59k | if (result == MCDisassembler_Success) { |
665 | 5.57k | *size = 4; |
666 | 5.57k | return true; |
667 | 5.57k | } |
668 | | |
669 | 20 | MCInst_clear(MI); |
670 | 20 | *size = 0; |
671 | 20 | return false; |
672 | 5.59k | } |
673 | | |
674 | | void TMS320C64x_init(MCRegisterInfo *MRI) |
675 | 167 | { |
676 | 167 | MCRegisterInfo_InitMCRegisterInfo(MRI, TMS320C64xRegDesc, 90, 0, 0, |
677 | 167 | TMS320C64xMCRegisterClasses, 7, 0, 0, |
678 | 167 | TMS320C64xRegDiffLists, 0, |
679 | 167 | TMS320C64xSubRegIdxLists, 1, 0); |
680 | 167 | } |
681 | | |
682 | | #endif |