/src/capstonev5/arch/ARM/ARMGenSystemRegister.inc

Source

/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|*                                                                            *|
|* GenSystemRegister Source Fragment                                          *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


enum BankedRegValues {
  elr_hyp = 0,
  lr_abt = 1,
  lr_fiq = 2,
  lr_irq = 3,
  lr_mon = 4,
  lr_svc = 5,
  lr_und = 6,
  lr_usr = 7,
  r10_fiq = 8,
  r10_usr = 9,
  r11_fiq = 10,
  r11_usr = 11,
  r12_fiq = 12,
  r12_usr = 13,
  r8_fiq = 14,
  r8_usr = 15,
  r9_fiq = 16,
  r9_usr = 17,
  sp_abt = 18,
  sp_fiq = 19,
  sp_hyp = 20,
  sp_irq = 21,
  sp_mon = 22,
  sp_svc = 23,
  sp_und = 24,
  sp_usr = 25,
  spsr_abt = 26,
  spsr_fiq = 27,
  spsr_hyp = 28,
  spsr_irq = 29,
  spsr_mon = 30,
  spsr_svc = 31,
  spsr_und = 32,
};

static const MClassSysReg MClassSysRegsList[] = {
  { "apsr_g", ARM_SYSREG_APSR_G, 0x400, 0x0, 0x400,  {ARM_FeatureDSP}  }, // 0
  { "apsr_nzcvqg", ARM_SYSREG_APSR_NZCVQG, 0xC00, 0x300, 0xC00,  {ARM_FeatureDSP}  }, // 1
  { "iapsr_g", ARM_SYSREG_IAPSR_G, 0x401, 0x1, 0x401,  {ARM_FeatureDSP}  }, // 2
  { "iapsr_nzcvqg", ARM_SYSREG_IAPSR_NZCVQG, 0xC01, 0x301, 0xC01,  {ARM_FeatureDSP}  }, // 3
  { "eapsr_g", ARM_SYSREG_EAPSR_G, 0x402, 0x2, 0x402,  {ARM_FeatureDSP}  }, // 4
  { "eapsr_nzcvqg", ARM_SYSREG_EAPSR_NZCVQG, 0xC02, 0x302, 0xC02,  {ARM_FeatureDSP}  }, // 5
  { "xpsr_g", ARM_SYSREG_XPSR_G, 0x403, 0x3, 0x403,  {ARM_FeatureDSP}  }, // 6
  { "xpsr_nzcvqg", ARM_SYSREG_XPSR_NZCVQG, 0xC03, 0x303, 0xC03,  {ARM_FeatureDSP}  }, // 7
  { "apsr", ARM_SYSREG_APSR, 0x800, 0x100, 0x800,  { 0 }  }, // 8
  { "apsr_nzcvq", ARM_SYSREG_APSR_NZCVQ, 0x1800, 0x200, 0x800,  { 0 }  }, // 9
  { "iapsr", ARM_SYSREG_IAPSR, 0x801, 0x101, 0x801,  { 0 }  }, // 10
  { "iapsr_nzcvq", ARM_SYSREG_IAPSR_NZCVQ, 0x1801, 0x201, 0x801,  { 0 }  }, // 11
  { "eapsr", ARM_SYSREG_EAPSR, 0x802, 0x102, 0x802,  { 0 }  }, // 12
  { "eapsr_nzcvq", ARM_SYSREG_EAPSR_NZCVQ, 0x1802, 0x202, 0x802,  { 0 }  }, // 13
  { "xpsr", ARM_SYSREG_XPSR, 0x803, 0x103, 0x803,  { 0 }  }, // 14
  { "xpsr_nzcvq", ARM_SYSREG_XPSR_NZCVQ, 0x1803, 0x203, 0x803,  { 0 }  }, // 15
  { "ipsr", ARM_SYSREG_IPSR, 0x805, 0x105, 0x805,  { 0 }  }, // 16
  { "epsr", ARM_SYSREG_EPSR, 0x806, 0x106, 0x806,  { 0 }  }, // 17
  { "iepsr", ARM_SYSREG_IEPSR, 0x807, 0x107, 0x807,  { 0 }  }, // 18
  { "msp", ARM_SYSREG_MSP, 0x808, 0x108, 0x808,  { 0 }  }, // 19
  { "psp", ARM_SYSREG_PSP, 0x809, 0x109, 0x809,  { 0 }  }, // 20
  { "msplim", ARM_SYSREG_MSPLIM, 0x80A, 0x10A, 0x80A,  {ARM_HasV8MBaselineOps}  }, // 21
  { "psplim", ARM_SYSREG_PSPLIM, 0x80B, 0x10B, 0x80B,  {ARM_HasV8MBaselineOps}  }, // 22
  { "primask", ARM_SYSREG_PRIMASK, 0x810, 0x110, 0x810,  { 0 }  }, // 23
  { "basepri", ARM_SYSREG_BASEPRI, 0x811, 0x111, 0x811,  {ARM_HasV7Ops}  }, // 24
  { "basepri_max", ARM_SYSREG_BASEPRI_MAX, 0x812, 0x112, 0x812,  {ARM_HasV7Ops}  }, // 25
  { "faultmask", ARM_SYSREG_FAULTMASK, 0x813, 0x113, 0x813,  {ARM_HasV7Ops}  }, // 26
  { "control", ARM_SYSREG_CONTROL, 0x814, 0x114, 0x814,  { 0 }  }, // 27
  { "msp_ns", ARM_SYSREG_MSP_NS, 0x888, 0x188, 0x888,  {ARM_Feature8MSecExt}  }, // 28
  { "psp_ns", ARM_SYSREG_PSP_NS, 0x889, 0x189, 0x889,  {ARM_Feature8MSecExt}  }, // 29
  { "msplim_ns", ARM_SYSREG_MSPLIM_NS, 0x88A, 0x18A, 0x88A,  {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}  }, // 30
  { "psplim_ns", ARM_SYSREG_PSPLIM_NS, 0x88B, 0x18B, 0x88B,  {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}  }, // 31
  { "primask_ns", ARM_SYSREG_PRIMASK_NS, 0x890, 0x190, 0x890,  { 0 }  }, // 32
  { "basepri_ns", ARM_SYSREG_BASEPRI_NS, 0x891, 0x191, 0x891,  {ARM_Feature8MSecExt, ARM_HasV7Ops}  }, // 33
  { "faultmask_ns", ARM_SYSREG_FAULTMASK_NS, 0x893, 0x193, 0x893,  {ARM_Feature8MSecExt, ARM_HasV7Ops}  }, // 34
  { "control_ns", ARM_SYSREG_CONTROL_NS, 0x894, 0x194, 0x894,  {ARM_Feature8MSecExt}  }, // 35
  { "sp_ns", ARM_SYSREG_SP_NS, 0x898, 0x198, 0x898,  {ARM_Feature8MSecExt}  }, // 36
};

static const BankedReg BankedRegsList[] = {
  { "r8_usr", ARM_SYSREG_R8_USR, 0x0 }, // 0
  { "r9_usr", ARM_SYSREG_R9_USR, 0x1 }, // 1
  { "r10_usr", ARM_SYSREG_R10_USR, 0x2 }, // 2
  { "r11_usr", ARM_SYSREG_R11_USR, 0x3 }, // 3
  { "r12_usr", ARM_SYSREG_R12_USR, 0x4 }, // 4
  { "sp_usr", ARM_SYSREG_SP_USR, 0x5 }, // 5
  { "lr_usr", ARM_SYSREG_LR_USR, 0x6 }, // 6
  { "r8_fiq", ARM_SYSREG_R8_FIQ, 0x8 }, // 7
  { "r9_fiq", ARM_SYSREG_R9_FIQ, 0x9 }, // 8
  { "r10_fiq", ARM_SYSREG_R10_FIQ, 0xA }, // 9
  { "r11_fiq", ARM_SYSREG_R11_FIQ, 0xB }, // 10
  { "r12_fiq", ARM_SYSREG_R12_FIQ, 0xC }, // 11
  { "sp_fiq", ARM_SYSREG_SP_FIQ, 0xD }, // 12
  { "lr_fiq", ARM_SYSREG_LR_FIQ, 0xE }, // 13
  { "lr_irq", ARM_SYSREG_LR_IRQ, 0x10 }, // 14
  { "sp_irq", ARM_SYSREG_SP_IRQ, 0x11 }, // 15
  { "lr_svc", ARM_SYSREG_LR_SVC, 0x12 }, // 16
  { "sp_svc", ARM_SYSREG_SP_SVC, 0x13 }, // 17
  { "lr_abt", ARM_SYSREG_LR_ABT, 0x14 }, // 18
  { "sp_abt", ARM_SYSREG_SP_ABT, 0x15 }, // 19
  { "lr_und", ARM_SYSREG_LR_UND, 0x16 }, // 20
  { "sp_und", ARM_SYSREG_SP_UND, 0x17 }, // 21
  { "lr_mon", ARM_SYSREG_LR_MON, 0x1C }, // 22
  { "sp_mon", ARM_SYSREG_SP_MON, 0x1D }, // 23
  { "elr_hyp", ARM_SYSREG_ELR_HYP, 0x1E }, // 24
  { "sp_hyp", ARM_SYSREG_SP_HYP, 0x1F }, // 25
  { "spsr_fiq", ARM_SYSREG_SPSR_FIQ, 0x2E }, // 26
  { "spsr_irq", ARM_SYSREG_SPSR_IRQ, 0x30 }, // 27
  { "spsr_svc", ARM_SYSREG_SPSR_SVC, 0x32 }, // 28
  { "spsr_abt", ARM_SYSREG_SPSR_ABT, 0x34 }, // 29
  { "spsr_und", ARM_SYSREG_SPSR_UND, 0x36 }, // 30
  { "spsr_mon", ARM_SYSREG_SPSR_MON, 0x3C }, // 31
  { "spsr_hyp", ARM_SYSREG_SPSR_HYP, 0x3E }, // 32
};

const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)
{
  unsigned int i;
  static const struct IndexType Index[] = {
    { 0x0, 0 },
    { 0x1, 2 },
    { 0x2, 4 },
    { 0x3, 6 },
    { 0x100, 8 },
    { 0x101, 10 },
    { 0x102, 12 },
    { 0x103, 14 },
    { 0x105, 16 },
    { 0x106, 17 },
    { 0x107, 18 },
    { 0x108, 19 },
    { 0x109, 20 },
    { 0x10A, 21 },
    { 0x10B, 22 },
    { 0x110, 23 },
    { 0x111, 24 },
    { 0x112, 25 },
    { 0x113, 26 },
    { 0x114, 27 },
    { 0x188, 28 },
    { 0x189, 29 },
    { 0x18A, 30 },
    { 0x18B, 31 },
    { 0x190, 32 },
    { 0x191, 33 },
    { 0x193, 34 },
    { 0x194, 35 },
    { 0x198, 36 },
    { 0x200, 9 },
    { 0x201, 11 },
    { 0x202, 13 },
    { 0x203, 15 },
    { 0x300, 1 },
    { 0x301, 3 },
    { 0x302, 5 },
    { 0x303, 7 },
  };

  i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding);
  if (i == -1)
    return NULL;
  else
    return &MClassSysRegsList[Index[i].index];
}

const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)
{
  unsigned int i;
  static const struct IndexType Index[] = {
    { 0x400, 0 },
    { 0x401, 2 },
    { 0x402, 4 },
    { 0x403, 6 },
    { 0x800, 8 },
    { 0x801, 10 },
    { 0x802, 12 },
    { 0x803, 14 },
    { 0x805, 16 },
    { 0x806, 17 },
    { 0x807, 18 },
    { 0x808, 19 },
    { 0x809, 20 },
    { 0x80A, 21 },
    { 0x80B, 22 },
    { 0x810, 23 },
    { 0x811, 24 },
    { 0x812, 25 },
    { 0x813, 26 },
    { 0x814, 27 },
    { 0x888, 28 },
    { 0x889, 29 },
    { 0x88A, 30 },
    { 0x88B, 31 },
    { 0x890, 32 },
    { 0x891, 33 },
    { 0x893, 34 },
    { 0x894, 35 },
    { 0x898, 36 },
    { 0xC00, 1 },
    { 0xC01, 3 },
    { 0xC02, 5 },
    { 0xC03, 7 },
    { 0x1800, 9 },
    { 0x1801, 11 },
    { 0x1802, 13 },
    { 0x1803, 15 },
  };

  i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding);
  if (i == -1)
    return NULL;
  else
    return &MClassSysRegsList[Index[i].index];
}

const BankedReg *lookupBankedRegByEncoding(uint8_t encoding)
{
  unsigned int i;
  static const struct IndexType Index[] = {
    { 0x0, 0 },
    { 0x1, 1 },
    { 0x2, 2 },
    { 0x3, 3 },
    { 0x4, 4 },
    { 0x5, 5 },
    { 0x6, 6 },
    { 0x8, 7 },
    { 0x9, 8 },
    { 0xA, 9 },
    { 0xB, 10 },
    { 0xC, 11 },
    { 0xD, 12 },
    { 0xE, 13 },
    { 0x10, 14 },
    { 0x11, 15 },
    { 0x12, 16 },
    { 0x13, 17 },
    { 0x14, 18 },
    { 0x15, 19 },
    { 0x16, 20 },
    { 0x17, 21 },
    { 0x1C, 22 },
    { 0x1D, 23 },
    { 0x1E, 24 },
    { 0x1F, 25 },
    { 0x2E, 26 },
    { 0x30, 27 },
    { 0x32, 28 },
    { 0x34, 29 },
    { 0x36, 30 },
    { 0x3C, 31 },
    { 0x3E, 32 },
  };

  i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding);
  if (i == -1)
    return NULL;
  else
    return &BankedRegsList[Index[i].index];
}


Coverage Report

Created: 2025-11-11 06:33

Line	Count	Source
1
2		/* Capstone Disassembly Engine, http://www.capstone-engine.org */
3		/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
4
5		/===- TableGen'erated file -------------------------------------- C++ --===\|* *\|
6		\|* GenSystemRegister Source Fragment *\|
7		\|* *\|
8		\|* Automatically generated file, do not edit! *\|
9		\|* *\|
10		\===----------------------------------------------------------------------===/
11
12
13		enum BankedRegValues {
14		elr_hyp = 0,
15		lr_abt = 1,
16		lr_fiq = 2,
17		lr_irq = 3,
18		lr_mon = 4,
19		lr_svc = 5,
20		lr_und = 6,
21		lr_usr = 7,
22		r10_fiq = 8,
23		r10_usr = 9,
24		r11_fiq = 10,
25		r11_usr = 11,
26		r12_fiq = 12,
27		r12_usr = 13,
28		r8_fiq = 14,
29		r8_usr = 15,
30		r9_fiq = 16,
31		r9_usr = 17,
32		sp_abt = 18,
33		sp_fiq = 19,
34		sp_hyp = 20,
35		sp_irq = 21,
36		sp_mon = 22,
37		sp_svc = 23,
38		sp_und = 24,
39		sp_usr = 25,
40		spsr_abt = 26,
41		spsr_fiq = 27,
42		spsr_hyp = 28,
43		spsr_irq = 29,
44		spsr_mon = 30,
45		spsr_svc = 31,
46		spsr_und = 32,
47		};
48
49		static const MClassSysReg MClassSysRegsList[] = {
50		{ "apsr_g", ARM_SYSREG_APSR_G, 0x400, 0x0, 0x400, {ARM_FeatureDSP} }, // 0
51		{ "apsr_nzcvqg", ARM_SYSREG_APSR_NZCVQG, 0xC00, 0x300, 0xC00, {ARM_FeatureDSP} }, // 1
52		{ "iapsr_g", ARM_SYSREG_IAPSR_G, 0x401, 0x1, 0x401, {ARM_FeatureDSP} }, // 2
53		{ "iapsr_nzcvqg", ARM_SYSREG_IAPSR_NZCVQG, 0xC01, 0x301, 0xC01, {ARM_FeatureDSP} }, // 3
54		{ "eapsr_g", ARM_SYSREG_EAPSR_G, 0x402, 0x2, 0x402, {ARM_FeatureDSP} }, // 4
55		{ "eapsr_nzcvqg", ARM_SYSREG_EAPSR_NZCVQG, 0xC02, 0x302, 0xC02, {ARM_FeatureDSP} }, // 5
56		{ "xpsr_g", ARM_SYSREG_XPSR_G, 0x403, 0x3, 0x403, {ARM_FeatureDSP} }, // 6
57		{ "xpsr_nzcvqg", ARM_SYSREG_XPSR_NZCVQG, 0xC03, 0x303, 0xC03, {ARM_FeatureDSP} }, // 7
58		{ "apsr", ARM_SYSREG_APSR, 0x800, 0x100, 0x800, { 0 } }, // 8
59		{ "apsr_nzcvq", ARM_SYSREG_APSR_NZCVQ, 0x1800, 0x200, 0x800, { 0 } }, // 9
60		{ "iapsr", ARM_SYSREG_IAPSR, 0x801, 0x101, 0x801, { 0 } }, // 10
61		{ "iapsr_nzcvq", ARM_SYSREG_IAPSR_NZCVQ, 0x1801, 0x201, 0x801, { 0 } }, // 11
62		{ "eapsr", ARM_SYSREG_EAPSR, 0x802, 0x102, 0x802, { 0 } }, // 12
63		{ "eapsr_nzcvq", ARM_SYSREG_EAPSR_NZCVQ, 0x1802, 0x202, 0x802, { 0 } }, // 13
64		{ "xpsr", ARM_SYSREG_XPSR, 0x803, 0x103, 0x803, { 0 } }, // 14
65		{ "xpsr_nzcvq", ARM_SYSREG_XPSR_NZCVQ, 0x1803, 0x203, 0x803, { 0 } }, // 15
66		{ "ipsr", ARM_SYSREG_IPSR, 0x805, 0x105, 0x805, { 0 } }, // 16
67		{ "epsr", ARM_SYSREG_EPSR, 0x806, 0x106, 0x806, { 0 } }, // 17
68		{ "iepsr", ARM_SYSREG_IEPSR, 0x807, 0x107, 0x807, { 0 } }, // 18
69		{ "msp", ARM_SYSREG_MSP, 0x808, 0x108, 0x808, { 0 } }, // 19
70		{ "psp", ARM_SYSREG_PSP, 0x809, 0x109, 0x809, { 0 } }, // 20
71		{ "msplim", ARM_SYSREG_MSPLIM, 0x80A, 0x10A, 0x80A, {ARM_HasV8MBaselineOps} }, // 21
72		{ "psplim", ARM_SYSREG_PSPLIM, 0x80B, 0x10B, 0x80B, {ARM_HasV8MBaselineOps} }, // 22
73		{ "primask", ARM_SYSREG_PRIMASK, 0x810, 0x110, 0x810, { 0 } }, // 23
74		{ "basepri", ARM_SYSREG_BASEPRI, 0x811, 0x111, 0x811, {ARM_HasV7Ops} }, // 24
75		{ "basepri_max", ARM_SYSREG_BASEPRI_MAX, 0x812, 0x112, 0x812, {ARM_HasV7Ops} }, // 25
76		{ "faultmask", ARM_SYSREG_FAULTMASK, 0x813, 0x113, 0x813, {ARM_HasV7Ops} }, // 26
77		{ "control", ARM_SYSREG_CONTROL, 0x814, 0x114, 0x814, { 0 } }, // 27
78		{ "msp_ns", ARM_SYSREG_MSP_NS, 0x888, 0x188, 0x888, {ARM_Feature8MSecExt} }, // 28
79		{ "psp_ns", ARM_SYSREG_PSP_NS, 0x889, 0x189, 0x889, {ARM_Feature8MSecExt} }, // 29
80		{ "msplim_ns", ARM_SYSREG_MSPLIM_NS, 0x88A, 0x18A, 0x88A, {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps} }, // 30
81		{ "psplim_ns", ARM_SYSREG_PSPLIM_NS, 0x88B, 0x18B, 0x88B, {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps} }, // 31
82		{ "primask_ns", ARM_SYSREG_PRIMASK_NS, 0x890, 0x190, 0x890, { 0 } }, // 32
83		{ "basepri_ns", ARM_SYSREG_BASEPRI_NS, 0x891, 0x191, 0x891, {ARM_Feature8MSecExt, ARM_HasV7Ops} }, // 33
84		{ "faultmask_ns", ARM_SYSREG_FAULTMASK_NS, 0x893, 0x193, 0x893, {ARM_Feature8MSecExt, ARM_HasV7Ops} }, // 34
85		{ "control_ns", ARM_SYSREG_CONTROL_NS, 0x894, 0x194, 0x894, {ARM_Feature8MSecExt} }, // 35
86		{ "sp_ns", ARM_SYSREG_SP_NS, 0x898, 0x198, 0x898, {ARM_Feature8MSecExt} }, // 36
87		};
88
89		static const BankedReg BankedRegsList[] = {
90		{ "r8_usr", ARM_SYSREG_R8_USR, 0x0 }, // 0
91		{ "r9_usr", ARM_SYSREG_R9_USR, 0x1 }, // 1
92		{ "r10_usr", ARM_SYSREG_R10_USR, 0x2 }, // 2
93		{ "r11_usr", ARM_SYSREG_R11_USR, 0x3 }, // 3
94		{ "r12_usr", ARM_SYSREG_R12_USR, 0x4 }, // 4
95		{ "sp_usr", ARM_SYSREG_SP_USR, 0x5 }, // 5
96		{ "lr_usr", ARM_SYSREG_LR_USR, 0x6 }, // 6
97		{ "r8_fiq", ARM_SYSREG_R8_FIQ, 0x8 }, // 7
98		{ "r9_fiq", ARM_SYSREG_R9_FIQ, 0x9 }, // 8
99		{ "r10_fiq", ARM_SYSREG_R10_FIQ, 0xA }, // 9
100		{ "r11_fiq", ARM_SYSREG_R11_FIQ, 0xB }, // 10
101		{ "r12_fiq", ARM_SYSREG_R12_FIQ, 0xC }, // 11
102		{ "sp_fiq", ARM_SYSREG_SP_FIQ, 0xD }, // 12
103		{ "lr_fiq", ARM_SYSREG_LR_FIQ, 0xE }, // 13
104		{ "lr_irq", ARM_SYSREG_LR_IRQ, 0x10 }, // 14
105		{ "sp_irq", ARM_SYSREG_SP_IRQ, 0x11 }, // 15
106		{ "lr_svc", ARM_SYSREG_LR_SVC, 0x12 }, // 16
107		{ "sp_svc", ARM_SYSREG_SP_SVC, 0x13 }, // 17
108		{ "lr_abt", ARM_SYSREG_LR_ABT, 0x14 }, // 18
109		{ "sp_abt", ARM_SYSREG_SP_ABT, 0x15 }, // 19
110		{ "lr_und", ARM_SYSREG_LR_UND, 0x16 }, // 20
111		{ "sp_und", ARM_SYSREG_SP_UND, 0x17 }, // 21
112		{ "lr_mon", ARM_SYSREG_LR_MON, 0x1C }, // 22
113		{ "sp_mon", ARM_SYSREG_SP_MON, 0x1D }, // 23
114		{ "elr_hyp", ARM_SYSREG_ELR_HYP, 0x1E }, // 24
115		{ "sp_hyp", ARM_SYSREG_SP_HYP, 0x1F }, // 25
116		{ "spsr_fiq", ARM_SYSREG_SPSR_FIQ, 0x2E }, // 26
117		{ "spsr_irq", ARM_SYSREG_SPSR_IRQ, 0x30 }, // 27
118		{ "spsr_svc", ARM_SYSREG_SPSR_SVC, 0x32 }, // 28
119		{ "spsr_abt", ARM_SYSREG_SPSR_ABT, 0x34 }, // 29
120		{ "spsr_und", ARM_SYSREG_SPSR_UND, 0x36 }, // 30
121		{ "spsr_mon", ARM_SYSREG_SPSR_MON, 0x3C }, // 31
122		{ "spsr_hyp", ARM_SYSREG_SPSR_HYP, 0x3E }, // 32
123		};
124
125		const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)
126	8.28k	{
127	8.28k	unsigned int i;
128	8.28k	static const struct IndexType Index[] = {
129	8.28k	{ 0x0, 0 },
130	8.28k	{ 0x1, 2 },
131	8.28k	{ 0x2, 4 },
132	8.28k	{ 0x3, 6 },
133	8.28k	{ 0x100, 8 },
134	8.28k	{ 0x101, 10 },
135	8.28k	{ 0x102, 12 },
136	8.28k	{ 0x103, 14 },
137	8.28k	{ 0x105, 16 },
138	8.28k	{ 0x106, 17 },
139	8.28k	{ 0x107, 18 },
140	8.28k	{ 0x108, 19 },
141	8.28k	{ 0x109, 20 },
142	8.28k	{ 0x10A, 21 },
143	8.28k	{ 0x10B, 22 },
144	8.28k	{ 0x110, 23 },
145	8.28k	{ 0x111, 24 },
146	8.28k	{ 0x112, 25 },
147	8.28k	{ 0x113, 26 },
148	8.28k	{ 0x114, 27 },
149	8.28k	{ 0x188, 28 },
150	8.28k	{ 0x189, 29 },
151	8.28k	{ 0x18A, 30 },
152	8.28k	{ 0x18B, 31 },
153	8.28k	{ 0x190, 32 },
154	8.28k	{ 0x191, 33 },
155	8.28k	{ 0x193, 34 },
156	8.28k	{ 0x194, 35 },
157	8.28k	{ 0x198, 36 },
158	8.28k	{ 0x200, 9 },
159	8.28k	{ 0x201, 11 },
160	8.28k	{ 0x202, 13 },
161	8.28k	{ 0x203, 15 },
162	8.28k	{ 0x300, 1 },
163	8.28k	{ 0x301, 3 },
164	8.28k	{ 0x302, 5 },
165	8.28k	{ 0x303, 7 },
166	8.28k	};
167
168	8.28k	i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding);
169	8.28k	if (i == -1)
170	4.05k	return NULL;
171	4.22k	else
172	4.22k	return &MClassSysRegsList[Index[i].index];
173	8.28k	}
174
175		const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)
176	4.61k	{
177	4.61k	unsigned int i;
178	4.61k	static const struct IndexType Index[] = {
179	4.61k	{ 0x400, 0 },
180	4.61k	{ 0x401, 2 },
181	4.61k	{ 0x402, 4 },
182	4.61k	{ 0x403, 6 },
183	4.61k	{ 0x800, 8 },
184	4.61k	{ 0x801, 10 },
185	4.61k	{ 0x802, 12 },
186	4.61k	{ 0x803, 14 },
187	4.61k	{ 0x805, 16 },
188	4.61k	{ 0x806, 17 },
189	4.61k	{ 0x807, 18 },
190	4.61k	{ 0x808, 19 },
191	4.61k	{ 0x809, 20 },
192	4.61k	{ 0x80A, 21 },
193	4.61k	{ 0x80B, 22 },
194	4.61k	{ 0x810, 23 },
195	4.61k	{ 0x811, 24 },
196	4.61k	{ 0x812, 25 },
197	4.61k	{ 0x813, 26 },
198	4.61k	{ 0x814, 27 },
199	4.61k	{ 0x888, 28 },
200	4.61k	{ 0x889, 29 },
201	4.61k	{ 0x88A, 30 },
202	4.61k	{ 0x88B, 31 },
203	4.61k	{ 0x890, 32 },
204	4.61k	{ 0x891, 33 },
205	4.61k	{ 0x893, 34 },
206	4.61k	{ 0x894, 35 },
207	4.61k	{ 0x898, 36 },
208	4.61k	{ 0xC00, 1 },
209	4.61k	{ 0xC01, 3 },
210	4.61k	{ 0xC02, 5 },
211	4.61k	{ 0xC03, 7 },
212	4.61k	{ 0x1800, 9 },
213	4.61k	{ 0x1801, 11 },
214	4.61k	{ 0x1802, 13 },
215	4.61k	{ 0x1803, 15 },
216	4.61k	};
217
218	4.61k	i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding);
219	4.61k	if (i == -1)
220	2.63k	return NULL;
221	1.98k	else
222	1.98k	return &MClassSysRegsList[Index[i].index];
223	4.61k	}
224
225		const BankedReg *lookupBankedRegByEncoding(uint8_t encoding)
226	1.77k	{
227	1.77k	unsigned int i;
228	1.77k	static const struct IndexType Index[] = {
229	1.77k	{ 0x0, 0 },
230	1.77k	{ 0x1, 1 },
231	1.77k	{ 0x2, 2 },
232	1.77k	{ 0x3, 3 },
233	1.77k	{ 0x4, 4 },
234	1.77k	{ 0x5, 5 },
235	1.77k	{ 0x6, 6 },
236	1.77k	{ 0x8, 7 },
237	1.77k	{ 0x9, 8 },
238	1.77k	{ 0xA, 9 },
239	1.77k	{ 0xB, 10 },
240	1.77k	{ 0xC, 11 },
241	1.77k	{ 0xD, 12 },
242	1.77k	{ 0xE, 13 },
243	1.77k	{ 0x10, 14 },
244	1.77k	{ 0x11, 15 },
245	1.77k	{ 0x12, 16 },
246	1.77k	{ 0x13, 17 },
247	1.77k	{ 0x14, 18 },
248	1.77k	{ 0x15, 19 },
249	1.77k	{ 0x16, 20 },
250	1.77k	{ 0x17, 21 },
251	1.77k	{ 0x1C, 22 },
252	1.77k	{ 0x1D, 23 },
253	1.77k	{ 0x1E, 24 },
254	1.77k	{ 0x1F, 25 },
255	1.77k	{ 0x2E, 26 },
256	1.77k	{ 0x30, 27 },
257	1.77k	{ 0x32, 28 },
258	1.77k	{ 0x34, 29 },
259	1.77k	{ 0x36, 30 },
260	1.77k	{ 0x3C, 31 },
261	1.77k	{ 0x3E, 32 },
262	1.77k	};
263
264	1.77k	i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding);
265	1.77k	if (i == -1)
266	78	return NULL;
267	1.69k	else
268	1.69k	return &BankedRegsList[Index[i].index];
269	1.77k	}
270