/src/capstonenext/arch/TMS320C64x/TMS320C64xInstPrinter.c

Source
/* Capstone Disassembly Engine */
/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */

#ifdef CAPSTONE_HAS_TMS320C64X

#include <ctype.h>
#include <string.h>

#include "TMS320C64xInstPrinter.h"
#include "../../MCInst.h"
#include "../../utils.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "../../MathExtras.h"
#include "TMS320C64xMapping.h"

#include "capstone/tms320c64x.h"

static const char *getRegisterName(unsigned RegNo);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O);
static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O);

void TMS320C64x_post_printer(csh ud, cs_insn *insn, SStream *insn_asm,
           MCInst *mci)
{
  SStream ss;
  const char *op_str_ptr, *p2;
  char tmp[8] = { 0 };
  unsigned int unit = 0;
  int i;
  cs_tms320c64x *tms320c64x;

  if (mci->csh->detail_opt) {
    tms320c64x = &mci->flat_insn->detail->tms320c64x;

    for (i = 0; i < insn->detail->groups_count; i++) {
      switch (insn->detail->groups[i]) {
      case TMS320C64X_GRP_FUNIT_D:
        unit = TMS320C64X_FUNIT_D;
        break;
      case TMS320C64X_GRP_FUNIT_L:
        unit = TMS320C64X_FUNIT_L;
        break;
      case TMS320C64X_GRP_FUNIT_M:
        unit = TMS320C64X_FUNIT_M;
        break;
      case TMS320C64X_GRP_FUNIT_S:
        unit = TMS320C64X_FUNIT_S;
        break;
      case TMS320C64X_GRP_FUNIT_NO:
        unit = TMS320C64X_FUNIT_NO;
        break;
      }
      if (unit != 0)
        break;
    }
    tms320c64x->funit.unit = unit;

    SStream_Init(&ss);
    if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
      SStream_concat(
        &ss, "[%c%s]|",
        (tms320c64x->condition.zero == 1) ? '!' : '|',
        cs_reg_name(ud, tms320c64x->condition.reg));

    // Sorry for all the fixes below. I don't have time to add more helper SStream functions.
    // Before that they messed around with the private buffer of the stream.
    // So it is better now. But still not efficient.
    op_str_ptr = strchr(SStream_rbuf(insn_asm), '\t');

    if ((op_str_ptr != NULL) &&
        (((p2 = strchr(op_str_ptr, '[')) != NULL) ||
         ((p2 = strchr(op_str_ptr, '(')) != NULL))) {
      while ((p2 > op_str_ptr) &&
             ((*p2 != 'a') && (*p2 != 'b')))
        p2--;
      if (p2 == op_str_ptr) {
        SStream_Flush(insn_asm, NULL);
        SStream_concat0(insn_asm, "Invalid!");
        return;
      }
      if (*p2 == 'a')
        strncpy(tmp, "1T", sizeof(tmp));
      else
        strncpy(tmp, "2T", sizeof(tmp));
    } else {
      tmp[0] = '\0';
    }
    SStream mnem_post = { 0 };
    SStream_Init(&mnem_post);
    switch (tms320c64x->funit.unit) {
    case TMS320C64X_FUNIT_D:
      SStream_concat(&mnem_post, ".D%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_L:
      SStream_concat(&mnem_post, ".L%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_M:
      SStream_concat(&mnem_post, ".M%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_S:
      SStream_concat(&mnem_post, ".S%s%u", tmp,
               tms320c64x->funit.side);
      break;
    }
    if (tms320c64x->funit.crosspath > 0)
      SStream_concat0(&mnem_post, "X");

    if (op_str_ptr != NULL) {
      // There is an op_str
      SStream_concat1(&mnem_post, '\t');
      SStream_replc_str(insn_asm, '\t',
            SStream_rbuf(&mnem_post));
    }

    if (tms320c64x->parallel != 0)
      SStream_concat0(insn_asm, "\t||");
    SStream_concat0(&ss, SStream_rbuf(insn_asm));
    SStream_Flush(insn_asm, NULL);
    SStream_concat0(insn_asm, SStream_rbuf(&ss));
  }
}

#define PRINT_ALIAS_INSTR
#include "TMS320C64xGenAsmWriter.inc"

#define GET_INSTRINFO_ENUM
#include "TMS320C64xGenInstrInfo.inc"

static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg;

  if (MCOperand_isReg(Op)) {
    reg = MCOperand_getReg(Op);
    if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) &&
        (OpNo == 1)) {
      switch (reg) {
      case TMS320C64X_REG_EFR:
        SStream_concat0(O, "EFR");
        break;
      case TMS320C64X_REG_IFR:
        SStream_concat0(O, "IFR");
        break;
      default:
        SStream_concat0(O, getRegisterName(reg));
        break;
      }
    } else {
      SStream_concat0(O, getRegisterName(reg));
    }

    if (MI->csh->detail_opt) {
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .type = TMS320C64X_OP_REG;
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .reg = reg;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  } else if (MCOperand_isImm(Op)) {
    int64_t Imm = MCOperand_getImm(Op);

    if (Imm >= 0) {
      if (Imm > HEX_THRESHOLD)
        SStream_concat(O, "0x%" PRIx64, Imm);
      else
        SStream_concat(O, "%" PRIu64, Imm);
    } else {
      if (Imm < -HEX_THRESHOLD)
        SStream_concat(O, "-0x%" PRIx64, -Imm);
      else
        SStream_concat(O, "-%" PRIu64, -Imm);
    }

    if (MI->csh->detail_opt) {
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .type = TMS320C64X_OP_IMM;
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .imm = Imm;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  }
}

static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  unsigned scaled, base, offset, mode, unit;
  cs_tms320c64x *tms320c64x;
  char st, nd;

  scaled = (Val >> 19) & 1;
  base = (Val >> 12) & 0x7f;
  offset = (Val >> 5) & 0x7f;
  mode = (Val >> 1) & 0xf;
  unit = Val & 1;

  if (scaled) {
    st = '[';
    nd = ']';
  } else {
    st = '(';
    nd = ')';
  }

  switch (mode) {
  case 0:
    SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 1:
    SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 4:
    SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 5:
    SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 8:
    SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 9:
    SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 10:
    SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 11:
    SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 12:
    SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 13:
    SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 14:
    SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 15:
    SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  }

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = base;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
    tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
    switch (mode) {
    case 0:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 1:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 4:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 5:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 8:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 9:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 10:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 11:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 12:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 13:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 14:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 15:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    }
    tms320c64x->op_count++;
  }
}

static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  uint16_t offset;
  unsigned basereg;
  cs_tms320c64x *tms320c64x;

  basereg = Val & 0x7f;
  offset = (Val >> 7) & 0x7fff;
  SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.disptype =
      TMS320C64X_MEM_DISP_CONSTANT;
    tms320c64x->operands[tms320c64x->op_count].mem.direction =
      TMS320C64X_MEM_DIR_FW;
    tms320c64x->operands[tms320c64x->op_count].mem.modify =
      TMS320C64X_MEM_MOD_NO;
    tms320c64x->op_count++;
  }
}

static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg = MCOperand_getReg(Op);
  cs_tms320c64x *tms320c64x;

  SStream_concat(O, "%s:%s", getRegisterName(reg + 1),
           getRegisterName(reg));

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_REGPAIR;
    tms320c64x->operands[tms320c64x->op_count].reg = reg;
    tms320c64x->op_count++;
  }
}

static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
{
  unsigned opcode = MCInst_getOpcode(MI);
  MCOperand *op;

  switch (opcode) {
  /* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
  case TMS320C64x_ADD_d2_rir:
  /* ADD.L -i, x, y -> SUB.L x, i, y */
  case TMS320C64x_ADD_l1_irr:
  case TMS320C64x_ADD_l1_ipp:
  /* ADD.S -i, x, y -> SUB.S x, i, y */
  case TMS320C64x_ADD_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
      op = MCInst_getOperand(MI, 2);
      MCOperand_setImm(op, -MCOperand_getImm(op));

      SStream_concat0(O, "SUB\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 2, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* ADD.D 0, x, y -> MV.D x, y */
  case TMS320C64x_ADD_d1_rir:
  /* OR.D x, 0, y -> MV.D x, y */
  case TMS320C64x_OR_d2_rir:
  /* ADD.L 0, x, y -> MV.L x, y */
  case TMS320C64x_ADD_l1_irr:
  case TMS320C64x_ADD_l1_ipp:
  /* OR.L 0, x, y -> MV.L x, y */
  case TMS320C64x_OR_l1_irr:
  /* ADD.S 0, x, y -> MV.S x, y */
  case TMS320C64x_ADD_s1_irr:
  /* OR.S 0, x, y -> MV.S x, y */
  case TMS320C64x_OR_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
      MI->size--;

      SStream_concat0(O, "MV\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* XOR.D -1, x, y -> NOT.D x, y */
  case TMS320C64x_XOR_d2_rir:
  /* XOR.L -1, x, y -> NOT.L x, y */
  case TMS320C64x_XOR_l1_irr:
  /* XOR.S -1, x, y -> NOT.S x, y */
  case TMS320C64x_XOR_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
      MI->size--;

      SStream_concat0(O, "NOT\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* MVK.D 0, x -> ZERO.D x */
  case TMS320C64x_MVK_d1_rr:
  /* MVK.L 0, x -> ZERO.L x */
  case TMS320C64x_MVK_l2_ir:
    if ((MCInst_getNumOperands(MI) == 2) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
      MI->size--;

      SStream_concat0(O, "ZERO\t");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* SUB.L x, x, y -> ZERO.L y */
  case TMS320C64x_SUB_l1_rrp_x1:
  /* SUB.S x, x, y -> ZERO.S y */
  case TMS320C64x_SUB_s1_rrr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
         MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
      MI->size -= 2;

      SStream_concat0(O, "ZERO\t");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* SUB.L 0, x, y -> NEG.L x, y */
  case TMS320C64x_SUB_l1_irr:
  case TMS320C64x_SUB_l1_ipp:
  /* SUB.S 0, x, y -> NEG.S x, y */
  case TMS320C64x_SUB_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
      MI->size--;

      SStream_concat0(O, "NEG\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* PACKLH2.L x, x, y -> SWAP2.L x, y */
  case TMS320C64x_PACKLH2_l1_rrr_x2:
  /* PACKLH2.S x, x, y -> SWAP2.S x, y */
  case TMS320C64x_PACKLH2_s1_rrr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
         MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
      MI->size--;

      SStream_concat0(O, "SWAP2\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* NOP 16 -> IDLE */
  /* NOP 1 -> NOP */
  case TMS320C64x_NOP_n:
    if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
      MI->size--;

      SStream_concat0(O, "IDLE");

      return true;
    }
    if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
      MI->size--;

      SStream_concat0(O, "NOP");

      return true;
    }
    break;
  }

  return false;
}

void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info)
{
  if (!printAliasInstruction(MI, O, Info))
    printInstruction(MI, O, Info);
}

#endif

Coverage Report

Created: 2025-11-16 06:38

Line	Count	Source
1		/* Capstone Disassembly Engine */
2		/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
3
4		#ifdef CAPSTONE_HAS_TMS320C64X
5
6		#include <ctype.h>
7		#include <string.h>
8
9		#include "TMS320C64xInstPrinter.h"
10		#include "../../MCInst.h"
11		#include "../../utils.h"
12		#include "../../SStream.h"
13		#include "../../MCRegisterInfo.h"
14		#include "../../MathExtras.h"
15		#include "TMS320C64xMapping.h"
16
17		#include "capstone/tms320c64x.h"
18
19		static const char *getRegisterName(unsigned RegNo);
20		static void printOperand(MCInst MI, unsigned OpNo, SStream O);
21		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O);
22		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O);
23		static void printRegPair(MCInst MI, unsigned OpNo, SStream O);
24
25		void TMS320C64x_post_printer(csh ud, cs_insn insn, SStream insn_asm,
26		MCInst *mci)
27	41.6k	{
28	41.6k	SStream ss;
29	41.6k	const char op_str_ptr, p2;
30	41.6k	char tmp[8] = { 0 };
31	41.6k	unsigned int unit = 0;
32	41.6k	int i;
33	41.6k	cs_tms320c64x *tms320c64x;
34
35	41.6k	if (mci->csh->detail_opt) {
36	41.6k	tms320c64x = &mci->flat_insn->detail->tms320c64x;
37
38	41.6k	for (i = 0; i < insn->detail->groups_count; i++) {
39	41.6k	switch (insn->detail->groups[i]) {
40	12.0k	case TMS320C64X_GRP_FUNIT_D:
41	12.0k	unit = TMS320C64X_FUNIT_D;
42	12.0k	break;
43	9.21k	case TMS320C64X_GRP_FUNIT_L:
44	9.21k	unit = TMS320C64X_FUNIT_L;
45	9.21k	break;
46	1.81k	case TMS320C64X_GRP_FUNIT_M:
47	1.81k	unit = TMS320C64X_FUNIT_M;
48	1.81k	break;
49	17.8k	case TMS320C64X_GRP_FUNIT_S:
50	17.8k	unit = TMS320C64X_FUNIT_S;
51	17.8k	break;
52	774	case TMS320C64X_GRP_FUNIT_NO:
53	774	unit = TMS320C64X_FUNIT_NO;
54	774	break;
55	41.6k	}
56	41.6k	if (unit != 0)
57	41.6k	break;
58	41.6k	}
59	41.6k	tms320c64x->funit.unit = unit;
60
61	41.6k	SStream_Init(&ss);
62	41.6k	if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
63	26.8k	SStream_concat(
64	26.8k	&ss, "[%c%s]\|",
65	26.8k	(tms320c64x->condition.zero == 1) ? '!' : '\|',
66	26.8k	cs_reg_name(ud, tms320c64x->condition.reg));
67
68		// Sorry for all the fixes below. I don't have time to add more helper SStream functions.
69		// Before that they messed around with the private buffer of the stream.
70		// So it is better now. But still not efficient.
71	41.6k	op_str_ptr = strchr(SStream_rbuf(insn_asm), '\t');
72
73	41.6k	if ((op_str_ptr != NULL) &&
74	41.0k	(((p2 = strchr(op_str_ptr, '[')) != NULL) \|\|
75	32.7k	((p2 = strchr(op_str_ptr, '(')) != NULL))) {
76	36.8k	while ((p2 > op_str_ptr) &&
77	36.8k	((p2 != 'a') && (p2 != 'b')))
78	28.1k	p2--;
79	8.76k	if (p2 == op_str_ptr) {
80	0	SStream_Flush(insn_asm, NULL);
81	0	SStream_concat0(insn_asm, "Invalid!");
82	0	return;
83	0	}
84	8.76k	if (*p2 == 'a')
85	4.53k	strncpy(tmp, "1T", sizeof(tmp));
86	4.23k	else
87	4.23k	strncpy(tmp, "2T", sizeof(tmp));
88	32.8k	} else {
89	32.8k	tmp[0] = '\0';
90	32.8k	}
91	41.6k	SStream mnem_post = { 0 };
92	41.6k	SStream_Init(&mnem_post);
93	41.6k	switch (tms320c64x->funit.unit) {
94	12.0k	case TMS320C64X_FUNIT_D:
95	12.0k	SStream_concat(&mnem_post, ".D%s%u", tmp,
96	12.0k	tms320c64x->funit.side);
97	12.0k	break;
98	9.21k	case TMS320C64X_FUNIT_L:
99	9.21k	SStream_concat(&mnem_post, ".L%s%u", tmp,
100	9.21k	tms320c64x->funit.side);
101	9.21k	break;
102	1.81k	case TMS320C64X_FUNIT_M:
103	1.81k	SStream_concat(&mnem_post, ".M%s%u", tmp,
104	1.81k	tms320c64x->funit.side);
105	1.81k	break;
106	17.8k	case TMS320C64X_FUNIT_S:
107	17.8k	SStream_concat(&mnem_post, ".S%s%u", tmp,
108	17.8k	tms320c64x->funit.side);
109	17.8k	break;
110	41.6k	}
111	41.6k	if (tms320c64x->funit.crosspath > 0)
112	12.0k	SStream_concat0(&mnem_post, "X");
113
114	41.6k	if (op_str_ptr != NULL) {
115		// There is an op_str
116	41.0k	SStream_concat1(&mnem_post, '\t');
117	41.0k	SStream_replc_str(insn_asm, '\t',
118	41.0k	SStream_rbuf(&mnem_post));
119	41.0k	}
120
121	41.6k	if (tms320c64x->parallel != 0)
122	19.4k	SStream_concat0(insn_asm, "\t\|\|");
123	41.6k	SStream_concat0(&ss, SStream_rbuf(insn_asm));
124	41.6k	SStream_Flush(insn_asm, NULL);
125	41.6k	SStream_concat0(insn_asm, SStream_rbuf(&ss));
126	41.6k	}
127	41.6k	}
128
129		#define PRINT_ALIAS_INSTR
130		#include "TMS320C64xGenAsmWriter.inc"
131
132		#define GET_INSTRINFO_ENUM
133		#include "TMS320C64xGenInstrInfo.inc"
134
135		static void printOperand(MCInst MI, unsigned OpNo, SStream O)
136	77.2k	{
137	77.2k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
138	77.2k	unsigned reg;
139
140	77.2k	if (MCOperand_isReg(Op)) {
141	55.9k	reg = MCOperand_getReg(Op);
142	55.9k	if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) &&
143	4.13k	(OpNo == 1)) {
144	2.06k	switch (reg) {
145	1.11k	case TMS320C64X_REG_EFR:
146	1.11k	SStream_concat0(O, "EFR");
147	1.11k	break;
148	426	case TMS320C64X_REG_IFR:
149	426	SStream_concat0(O, "IFR");
150	426	break;
151	523	default:
152	523	SStream_concat0(O, getRegisterName(reg));
153	523	break;
154	2.06k	}
155	53.9k	} else {
156	53.9k	SStream_concat0(O, getRegisterName(reg));
157	53.9k	}
158
159	55.9k	if (MI->csh->detail_opt) {
160	55.9k	MI->flat_insn->detail->tms320c64x
161	55.9k	.operands[MI->flat_insn->detail->tms320c64x
162	55.9k	.op_count]
163	55.9k	.type = TMS320C64X_OP_REG;
164	55.9k	MI->flat_insn->detail->tms320c64x
165	55.9k	.operands[MI->flat_insn->detail->tms320c64x
166	55.9k	.op_count]
167	55.9k	.reg = reg;
168	55.9k	MI->flat_insn->detail->tms320c64x.op_count++;
169	55.9k	}
170	55.9k	} else if (MCOperand_isImm(Op)) {
171	21.2k	int64_t Imm = MCOperand_getImm(Op);
172
173	21.2k	if (Imm >= 0) {
174	16.7k	if (Imm > HEX_THRESHOLD)
175	10.5k	SStream_concat(O, "0x%" PRIx64, Imm);
176	6.28k	else
177	6.28k	SStream_concat(O, "%" PRIu64, Imm);
178	16.7k	} else {
179	4.48k	if (Imm < -HEX_THRESHOLD)
180	3.28k	SStream_concat(O, "-0x%" PRIx64, -Imm);
181	1.20k	else
182	1.20k	SStream_concat(O, "-%" PRIu64, -Imm);
183	4.48k	}
184
185	21.2k	if (MI->csh->detail_opt) {
186	21.2k	MI->flat_insn->detail->tms320c64x
187	21.2k	.operands[MI->flat_insn->detail->tms320c64x
188	21.2k	.op_count]
189	21.2k	.type = TMS320C64X_OP_IMM;
190	21.2k	MI->flat_insn->detail->tms320c64x
191	21.2k	.operands[MI->flat_insn->detail->tms320c64x
192	21.2k	.op_count]
193	21.2k	.imm = Imm;
194	21.2k	MI->flat_insn->detail->tms320c64x.op_count++;
195	21.2k	}
196	21.2k	}
197	77.2k	}
198
199		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O)
200	4.53k	{
201	4.53k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
202	4.53k	int64_t Val = MCOperand_getImm(Op);
203	4.53k	unsigned scaled, base, offset, mode, unit;
204	4.53k	cs_tms320c64x *tms320c64x;
205	4.53k	char st, nd;
206
207	4.53k	scaled = (Val >> 19) & 1;
208	4.53k	base = (Val >> 12) & 0x7f;
209	4.53k	offset = (Val >> 5) & 0x7f;
210	4.53k	mode = (Val >> 1) & 0xf;
211	4.53k	unit = Val & 1;
212
213	4.53k	if (scaled) {
214	4.07k	st = '[';
215	4.07k	nd = ']';
216	4.07k	} else {
217	462	st = '(';
218	462	nd = ')';
219	462	}
220
221	4.53k	switch (mode) {
222	735	case 0:
223	735	SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st,
224	735	offset, nd);
225	735	break;
226	279	case 1:
227	279	SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st,
228	279	offset, nd);
229	279	break;
230	302	case 4:
231	302	SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st,
232	302	getRegisterName(offset), nd);
233	302	break;
234	405	case 5:
235	405	SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st,
236	405	getRegisterName(offset), nd);
237	405	break;
238	642	case 8:
239	642	SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st,
240	642	offset, nd);
241	642	break;
242	317	case 9:
243	317	SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st,
244	317	offset, nd);
245	317	break;
246	458	case 10:
247	458	SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st,
248	458	offset, nd);
249	458	break;
250	611	case 11:
251	611	SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st,
252	611	offset, nd);
253	611	break;
254	114	case 12:
255	114	SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st,
256	114	getRegisterName(offset), nd);
257	114	break;
258	94	case 13:
259	94	SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st,
260	94	getRegisterName(offset), nd);
261	94	break;
262	268	case 14:
263	268	SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st,
264	268	getRegisterName(offset), nd);
265	268	break;
266	310	case 15:
267	310	SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st,
268	310	getRegisterName(offset), nd);
269	310	break;
270	4.53k	}
271
272	4.53k	if (MI->csh->detail_opt) {
273	4.53k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
274
275	4.53k	tms320c64x->operands[tms320c64x->op_count].type =
276	4.53k	TMS320C64X_OP_MEM;
277	4.53k	tms320c64x->operands[tms320c64x->op_count].mem.base = base;
278	4.53k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
279	4.53k	tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
280	4.53k	tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
281	4.53k	switch (mode) {
282	735	case 0:
283	735	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
284	735	TMS320C64X_MEM_DISP_CONSTANT;
285	735	tms320c64x->operands[tms320c64x->op_count]
286	735	.mem.direction = TMS320C64X_MEM_DIR_BW;
287	735	tms320c64x->operands[tms320c64x->op_count].mem.modify =
288	735	TMS320C64X_MEM_MOD_NO;
289	735	break;
290	279	case 1:
291	279	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
292	279	TMS320C64X_MEM_DISP_CONSTANT;
293	279	tms320c64x->operands[tms320c64x->op_count]
294	279	.mem.direction = TMS320C64X_MEM_DIR_FW;
295	279	tms320c64x->operands[tms320c64x->op_count].mem.modify =
296	279	TMS320C64X_MEM_MOD_NO;
297	279	break;
298	302	case 4:
299	302	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
300	302	TMS320C64X_MEM_DISP_REGISTER;
301	302	tms320c64x->operands[tms320c64x->op_count]
302	302	.mem.direction = TMS320C64X_MEM_DIR_BW;
303	302	tms320c64x->operands[tms320c64x->op_count].mem.modify =
304	302	TMS320C64X_MEM_MOD_NO;
305	302	break;
306	405	case 5:
307	405	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
308	405	TMS320C64X_MEM_DISP_REGISTER;
309	405	tms320c64x->operands[tms320c64x->op_count]
310	405	.mem.direction = TMS320C64X_MEM_DIR_FW;
311	405	tms320c64x->operands[tms320c64x->op_count].mem.modify =
312	405	TMS320C64X_MEM_MOD_NO;
313	405	break;
314	642	case 8:
315	642	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
316	642	TMS320C64X_MEM_DISP_CONSTANT;
317	642	tms320c64x->operands[tms320c64x->op_count]
318	642	.mem.direction = TMS320C64X_MEM_DIR_BW;
319	642	tms320c64x->operands[tms320c64x->op_count].mem.modify =
320	642	TMS320C64X_MEM_MOD_PRE;
321	642	break;
322	317	case 9:
323	317	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
324	317	TMS320C64X_MEM_DISP_CONSTANT;
325	317	tms320c64x->operands[tms320c64x->op_count]
326	317	.mem.direction = TMS320C64X_MEM_DIR_FW;
327	317	tms320c64x->operands[tms320c64x->op_count].mem.modify =
328	317	TMS320C64X_MEM_MOD_PRE;
329	317	break;
330	458	case 10:
331	458	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
332	458	TMS320C64X_MEM_DISP_CONSTANT;
333	458	tms320c64x->operands[tms320c64x->op_count]
334	458	.mem.direction = TMS320C64X_MEM_DIR_BW;
335	458	tms320c64x->operands[tms320c64x->op_count].mem.modify =
336	458	TMS320C64X_MEM_MOD_POST;
337	458	break;
338	611	case 11:
339	611	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
340	611	TMS320C64X_MEM_DISP_CONSTANT;
341	611	tms320c64x->operands[tms320c64x->op_count]
342	611	.mem.direction = TMS320C64X_MEM_DIR_FW;
343	611	tms320c64x->operands[tms320c64x->op_count].mem.modify =
344	611	TMS320C64X_MEM_MOD_POST;
345	611	break;
346	114	case 12:
347	114	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
348	114	TMS320C64X_MEM_DISP_REGISTER;
349	114	tms320c64x->operands[tms320c64x->op_count]
350	114	.mem.direction = TMS320C64X_MEM_DIR_BW;
351	114	tms320c64x->operands[tms320c64x->op_count].mem.modify =
352	114	TMS320C64X_MEM_MOD_PRE;
353	114	break;
354	94	case 13:
355	94	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
356	94	TMS320C64X_MEM_DISP_REGISTER;
357	94	tms320c64x->operands[tms320c64x->op_count]
358	94	.mem.direction = TMS320C64X_MEM_DIR_FW;
359	94	tms320c64x->operands[tms320c64x->op_count].mem.modify =
360	94	TMS320C64X_MEM_MOD_PRE;
361	94	break;
362	268	case 14:
363	268	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
364	268	TMS320C64X_MEM_DISP_REGISTER;
365	268	tms320c64x->operands[tms320c64x->op_count]
366	268	.mem.direction = TMS320C64X_MEM_DIR_BW;
367	268	tms320c64x->operands[tms320c64x->op_count].mem.modify =
368	268	TMS320C64X_MEM_MOD_POST;
369	268	break;
370	310	case 15:
371	310	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
372	310	TMS320C64X_MEM_DISP_REGISTER;
373	310	tms320c64x->operands[tms320c64x->op_count]
374	310	.mem.direction = TMS320C64X_MEM_DIR_FW;
375	310	tms320c64x->operands[tms320c64x->op_count].mem.modify =
376	310	TMS320C64X_MEM_MOD_POST;
377	310	break;
378	4.53k	}
379	4.53k	tms320c64x->op_count++;
380	4.53k	}
381	4.53k	}
382
383		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O)
384	4.23k	{
385	4.23k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
386	4.23k	int64_t Val = MCOperand_getImm(Op);
387	4.23k	uint16_t offset;
388	4.23k	unsigned basereg;
389	4.23k	cs_tms320c64x *tms320c64x;
390
391	4.23k	basereg = Val & 0x7f;
392	4.23k	offset = (Val >> 7) & 0x7fff;
393	4.23k	SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);
394
395	4.23k	if (MI->csh->detail_opt) {
396	4.23k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
397
398	4.23k	tms320c64x->operands[tms320c64x->op_count].type =
399	4.23k	TMS320C64X_OP_MEM;
400	4.23k	tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
401	4.23k	tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
402	4.23k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
403	4.23k	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
404	4.23k	TMS320C64X_MEM_DISP_CONSTANT;
405	4.23k	tms320c64x->operands[tms320c64x->op_count].mem.direction =
406	4.23k	TMS320C64X_MEM_DIR_FW;
407	4.23k	tms320c64x->operands[tms320c64x->op_count].mem.modify =
408	4.23k	TMS320C64X_MEM_MOD_NO;
409	4.23k	tms320c64x->op_count++;
410	4.23k	}
411	4.23k	}
412
413		static void printRegPair(MCInst MI, unsigned OpNo, SStream O)
414	13.2k	{
415	13.2k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
416	13.2k	unsigned reg = MCOperand_getReg(Op);
417	13.2k	cs_tms320c64x *tms320c64x;
418
419	13.2k	SStream_concat(O, "%s:%s", getRegisterName(reg + 1),
420	13.2k	getRegisterName(reg));
421
422	13.2k	if (MI->csh->detail_opt) {
423	13.2k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
424
425	13.2k	tms320c64x->operands[tms320c64x->op_count].type =
426	13.2k	TMS320C64X_OP_REGPAIR;
427	13.2k	tms320c64x->operands[tms320c64x->op_count].reg = reg;
428	13.2k	tms320c64x->op_count++;
429	13.2k	}
430	13.2k	}
431
432		static bool printAliasInstruction(MCInst MI, SStream O, MCRegisterInfo *MRI)
433	41.6k	{
434	41.6k	unsigned opcode = MCInst_getOpcode(MI);
435	41.6k	MCOperand *op;
436
437	41.6k	switch (opcode) {
438		/* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
439	193	case TMS320C64x_ADD_d2_rir:
440		/* ADD.L -i, x, y -> SUB.L x, i, y */
441	553	case TMS320C64x_ADD_l1_irr:
442	833	case TMS320C64x_ADD_l1_ipp:
443		/* ADD.S -i, x, y -> SUB.S x, i, y */
444	1.43k	case TMS320C64x_ADD_s1_irr:
445	1.43k	if ((MCInst_getNumOperands(MI) == 3) &&
446	1.43k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
447	1.43k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
448	1.43k	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
449	1.43k	(MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
450	564	MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
451	564	op = MCInst_getOperand(MI, 2);
452	564	MCOperand_setImm(op, -MCOperand_getImm(op));
453
454	564	SStream_concat0(O, "SUB\t");
455	564	printOperand(MI, 1, O);
456	564	SStream_concat0(O, ", ");
457	564	printOperand(MI, 2, O);
458	564	SStream_concat0(O, ", ");
459	564	printOperand(MI, 0, O);
460
461	564	return true;
462	564	}
463	875	break;
464	41.6k	}
465	41.0k	switch (opcode) {
466		/* ADD.D 0, x, y -> MV.D x, y */
467	93	case TMS320C64x_ADD_d1_rir:
468		/* OR.D x, 0, y -> MV.D x, y */
469	321	case TMS320C64x_OR_d2_rir:
470		/* ADD.L 0, x, y -> MV.L x, y */
471	637	case TMS320C64x_ADD_l1_irr:
472	717	case TMS320C64x_ADD_l1_ipp:
473		/* OR.L 0, x, y -> MV.L x, y */
474	817	case TMS320C64x_OR_l1_irr:
475		/* ADD.S 0, x, y -> MV.S x, y */
476	1.19k	case TMS320C64x_ADD_s1_irr:
477		/* OR.S 0, x, y -> MV.S x, y */
478	1.24k	case TMS320C64x_OR_s1_irr:
479	1.24k	if ((MCInst_getNumOperands(MI) == 3) &&
480	1.24k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
481	1.24k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
482	1.24k	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
483	1.24k	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
484	448	MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
485	448	MI->size--;
486
487	448	SStream_concat0(O, "MV\t");
488	448	printOperand(MI, 1, O);
489	448	SStream_concat0(O, ", ");
490	448	printOperand(MI, 0, O);
491
492	448	return true;
493	448	}
494	799	break;
495	41.0k	}
496	40.6k	switch (opcode) {
497		/* XOR.D -1, x, y -> NOT.D x, y */
498	223	case TMS320C64x_XOR_d2_rir:
499		/* XOR.L -1, x, y -> NOT.L x, y */
500	463	case TMS320C64x_XOR_l1_irr:
501		/* XOR.S -1, x, y -> NOT.S x, y */
502	673	case TMS320C64x_XOR_s1_irr:
503	673	if ((MCInst_getNumOperands(MI) == 3) &&
504	673	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
505	673	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
506	673	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
507	673	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
508	68	MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
509	68	MI->size--;
510
511	68	SStream_concat0(O, "NOT\t");
512	68	printOperand(MI, 1, O);
513	68	SStream_concat0(O, ", ");
514	68	printOperand(MI, 0, O);
515
516	68	return true;
517	68	}
518	605	break;
519	40.6k	}
520	40.5k	switch (opcode) {
521		/* MVK.D 0, x -> ZERO.D x */
522	528	case TMS320C64x_MVK_d1_rr:
523		/* MVK.L 0, x -> ZERO.L x */
524	1.35k	case TMS320C64x_MVK_l2_ir:
525	1.35k	if ((MCInst_getNumOperands(MI) == 2) &&
526	1.35k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
527	1.35k	MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
528	1.35k	(MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
529	180	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
530	180	MI->size--;
531
532	180	SStream_concat0(O, "ZERO\t");
533	180	printOperand(MI, 0, O);
534
535	180	return true;
536	180	}
537	1.17k	break;
538	40.5k	}
539	40.3k	switch (opcode) {
540		/* SUB.L x, x, y -> ZERO.L y */
541	108	case TMS320C64x_SUB_l1_rrp_x1:
542		/* SUB.S x, x, y -> ZERO.S y */
543	226	case TMS320C64x_SUB_s1_rrr:
544	226	if ((MCInst_getNumOperands(MI) == 3) &&
545	226	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
546	226	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
547	226	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
548	226	(MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
549	226	MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
550	71	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
551	71	MI->size -= 2;
552
553	71	SStream_concat0(O, "ZERO\t");
554	71	printOperand(MI, 0, O);
555
556	71	return true;
557	71	}
558	155	break;
559	40.3k	}
560	40.3k	switch (opcode) {
561		/* SUB.L 0, x, y -> NEG.L x, y */
562	139	case TMS320C64x_SUB_l1_irr:
563	532	case TMS320C64x_SUB_l1_ipp:
564		/* SUB.S 0, x, y -> NEG.S x, y */
565	618	case TMS320C64x_SUB_s1_irr:
566	618	if ((MCInst_getNumOperands(MI) == 3) &&
567	618	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
568	618	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
569	618	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
570	618	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
571	118	MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
572	118	MI->size--;
573
574	118	SStream_concat0(O, "NEG\t");
575	118	printOperand(MI, 1, O);
576	118	SStream_concat0(O, ", ");
577	118	printOperand(MI, 0, O);
578
579	118	return true;
580	118	}
581	500	break;
582	40.3k	}
583	40.2k	switch (opcode) {
584		/* PACKLH2.L x, x, y -> SWAP2.L x, y */
585	265	case TMS320C64x_PACKLH2_l1_rrr_x2:
586		/* PACKLH2.S x, x, y -> SWAP2.S x, y */
587	597	case TMS320C64x_PACKLH2_s1_rrr:
588	597	if ((MCInst_getNumOperands(MI) == 3) &&
589	597	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
590	597	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
591	597	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
592	597	(MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
593	597	MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
594	70	MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
595	70	MI->size--;
596
597	70	SStream_concat0(O, "SWAP2\t");
598	70	printOperand(MI, 1, O);
599	70	SStream_concat0(O, ", ");
600	70	printOperand(MI, 0, O);
601
602	70	return true;
603	70	}
604	527	break;
605	40.2k	}
606	40.1k	switch (opcode) {
607		/* NOP 16 -> IDLE */
608		/* NOP 1 -> NOP */
609	774	case TMS320C64x_NOP_n:
610	774	if ((MCInst_getNumOperands(MI) == 1) &&
611	774	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
612	774	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
613	73	MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
614	73	MI->size--;
615
616	73	SStream_concat0(O, "IDLE");
617
618	73	return true;
619	73	}
620	701	if ((MCInst_getNumOperands(MI) == 1) &&
621	701	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
622	701	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
623	523	MI->size--;
624
625	523	SStream_concat0(O, "NOP");
626
627	523	return true;
628	523	}
629	178	break;
630	40.1k	}
631
632	39.5k	return false;
633	40.1k	}
634
635		void TMS320C64x_printInst(MCInst MI, SStream O, void *Info)
636	41.6k	{
637	41.6k	if (!printAliasInstruction(MI, O, Info))
638	39.5k	printInstruction(MI, O, Info);
639	41.6k	}
640
641		#endif