/src/capstonenext/arch/SystemZ/SystemZMapping.c

Source
/* Capstone Disassembly Engine */
/* By Rot127 <unisono@quyllur.org> 2022-2023 */

#ifdef CAPSTONE_HAS_SYSTEMZ

#include <stdio.h> // debug
#include <string.h>

#include "../../Mapping.h"
#include "../../utils.h"
#include "../../cs_simple_types.h"
#include <capstone/cs_operand.h>

#include "SystemZMCTargetDesc.h"
#include "SystemZMapping.h"
#include "SystemZLinkage.h"

#ifndef CAPSTONE_DIET

static const char *const insn_name_maps[] = {
#include "SystemZGenCSMappingInsnName.inc"
};

static const name_map insn_alias_mnem_map[] = {
#include "SystemZGenCSAliasMnemMap.inc"
  { SYSTEMZ_INS_ALIAS_END, NULL },
};

static const map_insn_ops insn_operands[] = {
#include "SystemZGenCSMappingInsnOp.inc"
};

#endif

#define GET_REGINFO_MC_DESC
#include "SystemZGenRegisterInfo.inc"

const insn_map systemz_insns[] = {
#include "SystemZGenCSMappingInsn.inc"
};

void SystemZ_set_instr_map_data(MCInst *MI, const uint8_t *Bytes,
        size_t BytesLen)
{
  map_cs_id(MI, systemz_insns, ARR_SIZE(systemz_insns));
  map_implicit_reads(MI, systemz_insns);
  map_implicit_writes(MI, systemz_insns);
  map_groups(MI, systemz_insns);
  const systemz_suppl_info *suppl_info =
    map_get_suppl_info(MI, systemz_insns);
  if (suppl_info) {
    SystemZ_get_detail(MI)->format = suppl_info->form;
  }
}

void SystemZ_init_mri(MCRegisterInfo *MRI)
{
  MCRegisterInfo_InitMCRegisterInfo(
    MRI, SystemZRegDesc, AARCH64_REG_ENDING, 0, 0,
    SystemZMCRegisterClasses, ARR_SIZE(SystemZMCRegisterClasses), 0,
    0, SystemZRegDiffLists, 0, SystemZSubRegIdxLists,
    ARR_SIZE(SystemZSubRegIdxLists), 0);
}

const char *SystemZ_reg_name(csh handle, unsigned int reg)
{
  return SystemZ_LLVM_getRegisterName(reg);
}

void SystemZ_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
{
  MI->MRI = (MCRegisterInfo *)info;
  MI->fillDetailOps = detail_is_set(MI);
  SystemZ_LLVM_printInstruction(MI, "", O);
#ifndef CAPSTONE_DIET
  map_set_alias_id(MI, O, insn_alias_mnem_map,
       ARR_SIZE(insn_alias_mnem_map));
#endif
}

void SystemZ_init_cs_detail(MCInst *MI)
{
  if (!detail_is_set(MI)) {
    return;
  }
  memset(get_detail(MI), 0, sizeof(cs_detail));
  if (detail_is_set(MI)) {
    SystemZ_get_detail(MI)->cc = SYSTEMZ_CC_INVALID;
  }
}

bool SystemZ_getInstruction(csh handle, const uint8_t *bytes, size_t bytes_len,
          MCInst *MI, uint16_t *size, uint64_t address,
          void *info)
{
  SystemZ_init_cs_detail(MI);
  MI->MRI = (MCRegisterInfo *)info;
  DecodeStatus Result = SystemZ_LLVM_getInstruction(
    handle, bytes, bytes_len, MI, size, address, info);
  SystemZ_set_instr_map_data(MI, bytes, bytes_len);
  if (Result == MCDisassembler_SoftFail) {
    MCInst_setSoftFail(MI);
  }
  return Result != MCDisassembler_Fail;
}

// given internal insn id, return public instruction info
void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
  // We do this after Instruction disassembly.
}

const char *SystemZ_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
  if (id < SYSTEMZ_INS_ALIAS_END && id > SYSTEMZ_INS_ALIAS_BEGIN) {
    if (id - SYSTEMZ_INS_ALIAS_BEGIN >=
        ARR_SIZE(insn_alias_mnem_map))
      return NULL;

    return insn_alias_mnem_map[id - SYSTEMZ_INS_ALIAS_BEGIN - 1]
      .name;
  }
  if (id >= SYSTEMZ_INS_ENDING)
    return NULL;

  if (id < ARR_SIZE(insn_name_maps))
    return insn_name_maps[id];

  // not found
  return NULL;
#else
  return NULL;
#endif
}

#ifndef CAPSTONE_DIET
static const name_map group_name_maps[] = {
  // generic groups
  { SYSTEMZ_GRP_INVALID, NULL },
  { SYSTEMZ_GRP_JUMP, "jump" },
  { SYSTEMZ_GRP_CALL, "call" },
  { SYSTEMZ_GRP_RET, "return" },
  { SYSTEMZ_GRP_INT, "int" },
  { SYSTEMZ_GRP_IRET, "iret" },
  { SYSTEMZ_GRP_PRIVILEGE, "privilege" },
  { SYSTEMZ_GRP_BRANCH_RELATIVE, "branch_relative" },

#include "SystemZGenCSFeatureName.inc"
};
#endif

const char *SystemZ_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
  return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else
  return NULL;
#endif
}

void SystemZ_add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group,
         va_list args)
{
#ifndef CAPSTONE_DIET
  if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
    return;

  unsigned op_num = va_arg(args, unsigned);

  switch (op_group) {
  default:
    printf("Operand group %d not handled\n", op_group);
    break;
  case SystemZ_OP_GROUP_Operand: {
    cs_op_type secondary_op_type = map_get_op_type(MI, op_num) &
                 ~(CS_OP_MEM | CS_OP_BOUND);
    if (secondary_op_type == CS_OP_IMM) {
      SystemZ_set_detail_op_imm(
        MI, op_num, MCInst_getOpVal(MI, op_num), 0);
    } else if (secondary_op_type == CS_OP_REG) {
      SystemZ_set_detail_op_reg(MI, op_num,
              MCInst_getOpVal(MI, op_num));
    } else {
      CS_ASSERT_RET(0 && "Op type not handled.");
    }
    break;
  }
  case SystemZ_OP_GROUP_Cond4Operand: {
    systemz_cc cc = MCInst_getOpVal(MI, op_num);
    SystemZ_get_detail(MI)->cc = cc;
    break;
  }
  case SystemZ_OP_GROUP_BDAddrOperand:
    CS_ASSERT_RET(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
    CS_ASSERT_RET(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
    CS_ASSERT_RET(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
    CS_ASSERT_RET(
      MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
    SystemZ_set_detail_op_mem(MI, op_num,
            MCInst_getOpVal(MI, (op_num)),
            MCInst_getOpVal(MI, (op_num + 1)), 0,
            0, SYSTEMZ_AM_BD);
    break;
  case SystemZ_OP_GROUP_BDVAddrOperand:
  case SystemZ_OP_GROUP_BDXAddrOperand: {
    CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
    CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
    CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
    CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
    CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
    CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2))));
    SystemZ_set_detail_op_mem(
      MI, op_num, MCInst_getOpVal(MI, (op_num)),
      MCInst_getOpVal(MI, (op_num + 1)), 0,
      MCInst_getOpVal(MI, (op_num + 2)),
      (op_group == SystemZ_OP_GROUP_BDXAddrOperand ?
         SYSTEMZ_AM_BDX :
         SYSTEMZ_AM_BDV));
    break;
  }
  case SystemZ_OP_GROUP_BDLAddrOperand:
    CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
    CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
    CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
    CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
    CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
    CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 2))));
    SystemZ_set_detail_op_mem(MI, op_num,
            MCInst_getOpVal(MI, (op_num)),
            MCInst_getOpVal(MI, (op_num + 1)),
            MCInst_getOpVal(MI, (op_num + 2)), 0,
            SYSTEMZ_AM_BDL);
    break;
  case SystemZ_OP_GROUP_BDRAddrOperand:
    CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
    CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
    CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
    CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
    CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
    CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2))));
    SystemZ_set_detail_op_mem(MI, op_num,
            MCInst_getOpVal(MI, (op_num)),
            MCInst_getOpVal(MI, (op_num + 1)),
            MCInst_getOpVal(MI, (op_num + 2)), 0,
            SYSTEMZ_AM_BDL);
    break;
  case SystemZ_OP_GROUP_PCRelOperand:
    SystemZ_set_detail_op_imm(MI, op_num,
            MCInst_getOpVal(MI, op_num), 0);
    break;
  case SystemZ_OP_GROUP_U1ImmOperand:
    SystemZ_set_detail_op_imm(MI, op_num,
            MCInst_getOpVal(MI, op_num), 1);
    break;
  case SystemZ_OP_GROUP_U2ImmOperand:
    SystemZ_set_detail_op_imm(MI, op_num,
            MCInst_getOpVal(MI, op_num), 2);
    break;
  case SystemZ_OP_GROUP_U3ImmOperand:
    SystemZ_set_detail_op_imm(MI, op_num,
            MCInst_getOpVal(MI, op_num), 3);
    break;
  case SystemZ_OP_GROUP_U4ImmOperand:
    SystemZ_set_detail_op_imm(MI, op_num,
            MCInst_getOpVal(MI, op_num), 4);
    break;
  case SystemZ_OP_GROUP_U8ImmOperand:
  case SystemZ_OP_GROUP_S8ImmOperand:
    SystemZ_set_detail_op_imm(MI, op_num,
            MCInst_getOpVal(MI, op_num), 8);
    break;
  case SystemZ_OP_GROUP_U12ImmOperand:
    SystemZ_set_detail_op_imm(MI, op_num,
            MCInst_getOpVal(MI, op_num), 12);
    break;
  case SystemZ_OP_GROUP_U16ImmOperand:
  case SystemZ_OP_GROUP_S16ImmOperand:
    SystemZ_set_detail_op_imm(MI, op_num,
            MCInst_getOpVal(MI, op_num), 16);
    break;
  case SystemZ_OP_GROUP_U32ImmOperand:
  case SystemZ_OP_GROUP_S32ImmOperand:
    SystemZ_set_detail_op_imm(MI, op_num,
            MCInst_getOpVal(MI, op_num), 32);
    break;
  case SystemZ_OP_GROUP_U48ImmOperand:
    SystemZ_set_detail_op_imm(MI, op_num,
            MCInst_getOpVal(MI, op_num), 48);
    break;
  }
#endif
}

#ifndef CAPSTONE_DIET

void SystemZ_set_detail_op_imm(MCInst *MI, unsigned op_num, int64_t Imm,
             size_t width)
{
  if (!detail_is_set(MI))
    return;
  CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_IMM);

  SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_IMM;
  SystemZ_get_detail_op(MI, 0)->imm = Imm;
  SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
  SystemZ_get_detail_op(MI, 0)->imm_width = width;
  SystemZ_inc_op_count(MI);
}

void SystemZ_set_detail_op_reg(MCInst *MI, unsigned op_num, systemz_reg Reg)
{
  if (!detail_is_set(MI))
    return;
  CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_REG);
  if (Reg == SYSTEMZ_REG_INVALID) {
    // This case is legal. The ISA says:
    // "
    // When the R1 field is not zero, bits 8-15 of the instruction designated
    // by the second-operand address are ORed with bits 56-63 of
    // general register R1. [...] When the R1 field is zero, no ORing takes place
    // "
    // This means we just save the neutral element for ORing, so 0.
    SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_IMM;
    SystemZ_get_detail_op(MI, 0)->imm = 0;
    SystemZ_get_detail_op(MI, 0)->access =
      map_get_op_access(MI, op_num);
    SystemZ_get_detail_op(MI, 0)->imm_width = 0;
    SystemZ_inc_op_count(MI);
    return;
  }

  SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_REG;
  SystemZ_get_detail_op(MI, 0)->reg = Reg;
  SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
  SystemZ_inc_op_count(MI);
}

void SystemZ_set_detail_op_mem(MCInst *MI, unsigned op_num, systemz_reg base,
             int64_t disp, uint64_t length, systemz_reg index,
             systemz_addr_mode am)
{
  if (!detail_is_set(MI))
    return;
  SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_MEM;
  SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
  SystemZ_get_detail_op(MI, 0)->mem.am = am;
  switch (am) {
  default:
    CS_ASSERT(0 && "Address mode not handled\n");
    break;
  case SYSTEMZ_AM_BD:
    SystemZ_get_detail_op(MI, 0)->mem.base = base;
    SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
    break;
  case SYSTEMZ_AM_BDX:
  case SYSTEMZ_AM_BDV:
    SystemZ_get_detail_op(MI, 0)->mem.base = base;
    SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
    SystemZ_get_detail_op(MI, 0)->mem.index = index;
    break;
  case SYSTEMZ_AM_BDL:
    SystemZ_get_detail_op(MI, 0)->mem.base = base;
    SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
    SystemZ_get_detail_op(MI, 0)->mem.length = length;
    break;
  case SYSTEMZ_AM_BDR:
    SystemZ_get_detail_op(MI, 0)->mem.base = base;
    SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
    SystemZ_get_detail_op(MI, 0)->mem.length = length;
    break;
  }
  SystemZ_inc_op_count(MI);
}

#endif

#endif

Coverage Report

Created: 2025-11-24 06:12

Line	Count	Source
1		/* Capstone Disassembly Engine */
2		/* By Rot127 <unisono@quyllur.org> 2022-2023 */
3
4		#ifdef CAPSTONE_HAS_SYSTEMZ
5
6		#include <stdio.h> // debug
7		#include <string.h>
8
9		#include "../../Mapping.h"
10		#include "../../utils.h"
11		#include "../../cs_simple_types.h"
12		#include <capstone/cs_operand.h>
13
14		#include "SystemZMCTargetDesc.h"
15		#include "SystemZMapping.h"
16		#include "SystemZLinkage.h"
17
18		#ifndef CAPSTONE_DIET
19
20		static const char *const insn_name_maps[] = {
21		#include "SystemZGenCSMappingInsnName.inc"
22		};
23
24		static const name_map insn_alias_mnem_map[] = {
25		#include "SystemZGenCSAliasMnemMap.inc"
26		{ SYSTEMZ_INS_ALIAS_END, NULL },
27		};
28
29		static const map_insn_ops insn_operands[] = {
30		#include "SystemZGenCSMappingInsnOp.inc"
31		};
32
33		#endif
34
35		#define GET_REGINFO_MC_DESC
36		#include "SystemZGenRegisterInfo.inc"
37
38		const insn_map systemz_insns[] = {
39		#include "SystemZGenCSMappingInsn.inc"
40		};
41
42		void SystemZ_set_instr_map_data(MCInst MI, const uint8_t Bytes,
43		size_t BytesLen)
44	189k	{
45	189k	map_cs_id(MI, systemz_insns, ARR_SIZE(systemz_insns));
46	189k	map_implicit_reads(MI, systemz_insns);
47	189k	map_implicit_writes(MI, systemz_insns);
48	189k	map_groups(MI, systemz_insns);
49	189k	const systemz_suppl_info *suppl_info =
50	189k	map_get_suppl_info(MI, systemz_insns);
51	189k	if (suppl_info) {
52	189k	SystemZ_get_detail(MI)->format = suppl_info->form;
53	189k	}
54	189k	}
55
56		void SystemZ_init_mri(MCRegisterInfo *MRI)
57	4.48k	{
58	4.48k	MCRegisterInfo_InitMCRegisterInfo(
59	4.48k	MRI, SystemZRegDesc, AARCH64_REG_ENDING, 0, 0,
60	4.48k	SystemZMCRegisterClasses, ARR_SIZE(SystemZMCRegisterClasses), 0,
61	4.48k	0, SystemZRegDiffLists, 0, SystemZSubRegIdxLists,
62	4.48k	ARR_SIZE(SystemZSubRegIdxLists), 0);
63	4.48k	}
64
65		const char *SystemZ_reg_name(csh handle, unsigned int reg)
66	113k	{
67	113k	return SystemZ_LLVM_getRegisterName(reg);
68	113k	}
69
70		void SystemZ_printer(MCInst MI, SStream O, void * /* MCRegisterInfo* */ info)
71	187k	{
72	187k	MI->MRI = (MCRegisterInfo *)info;
73	187k	MI->fillDetailOps = detail_is_set(MI);
74	187k	SystemZ_LLVM_printInstruction(MI, "", O);
75	187k	#ifndef CAPSTONE_DIET
76	187k	map_set_alias_id(MI, O, insn_alias_mnem_map,
77	187k	ARR_SIZE(insn_alias_mnem_map));
78	187k	#endif
79	187k	}
80
81		void SystemZ_init_cs_detail(MCInst *MI)
82	189k	{
83	189k	if (!detail_is_set(MI)) {
84	0	return;
85	0	}
86	189k	memset(get_detail(MI), 0, sizeof(cs_detail));
87	189k	if (detail_is_set(MI)) {
88	189k	SystemZ_get_detail(MI)->cc = SYSTEMZ_CC_INVALID;
89	189k	}
90	189k	}
91
92		bool SystemZ_getInstruction(csh handle, const uint8_t *bytes, size_t bytes_len,
93		MCInst MI, uint16_t size, uint64_t address,
94		void *info)
95	189k	{
96	189k	SystemZ_init_cs_detail(MI);
97	189k	MI->MRI = (MCRegisterInfo *)info;
98	189k	DecodeStatus Result = SystemZ_LLVM_getInstruction(
99	189k	handle, bytes, bytes_len, MI, size, address, info);
100	189k	SystemZ_set_instr_map_data(MI, bytes, bytes_len);
101	189k	if (Result == MCDisassembler_SoftFail) {
102	0	MCInst_setSoftFail(MI);
103	0	}
104	189k	return Result != MCDisassembler_Fail;
105	189k	}
106
107		// given internal insn id, return public instruction info
108		void SystemZ_get_insn_id(cs_struct h, cs_insn insn, unsigned int id)
109	187k	{
110		// We do this after Instruction disassembly.
111	187k	}
112
113		const char *SystemZ_insn_name(csh handle, unsigned int id)
114	187k	{
115	187k	#ifndef CAPSTONE_DIET
116	187k	if (id < SYSTEMZ_INS_ALIAS_END && id > SYSTEMZ_INS_ALIAS_BEGIN) {
117	0	if (id - SYSTEMZ_INS_ALIAS_BEGIN >=
118	0	ARR_SIZE(insn_alias_mnem_map))
119	0	return NULL;
120
121	0	return insn_alias_mnem_map[id - SYSTEMZ_INS_ALIAS_BEGIN - 1]
122	0	.name;
123	0	}
124	187k	if (id >= SYSTEMZ_INS_ENDING)
125	0	return NULL;
126
127	187k	if (id < ARR_SIZE(insn_name_maps))
128	187k	return insn_name_maps[id];
129
130		// not found
131	0	return NULL;
132		#else
133		return NULL;
134		#endif
135	187k	}
136
137		#ifndef CAPSTONE_DIET
138		static const name_map group_name_maps[] = {
139		// generic groups
140		{ SYSTEMZ_GRP_INVALID, NULL },
141		{ SYSTEMZ_GRP_JUMP, "jump" },
142		{ SYSTEMZ_GRP_CALL, "call" },
143		{ SYSTEMZ_GRP_RET, "return" },
144		{ SYSTEMZ_GRP_INT, "int" },
145		{ SYSTEMZ_GRP_IRET, "iret" },
146		{ SYSTEMZ_GRP_PRIVILEGE, "privilege" },
147		{ SYSTEMZ_GRP_BRANCH_RELATIVE, "branch_relative" },
148
149		#include "SystemZGenCSFeatureName.inc"
150		};
151		#endif
152
153		const char *SystemZ_group_name(csh handle, unsigned int id)
154	75.8k	{
155	75.8k	#ifndef CAPSTONE_DIET
156	75.8k	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
157		#else
158		return NULL;
159		#endif
160	75.8k	}
161
162		void SystemZ_add_cs_detail(MCInst MI, int / aarch64_op_group */ op_group,
163		va_list args)
164	457k	{
165	457k	#ifndef CAPSTONE_DIET
166	457k	if (!detail_is_set(MI) \|\| !map_fill_detail_ops(MI))
167	0	return;
168
169	457k	unsigned op_num = va_arg(args, unsigned);
170
171	457k	switch (op_group) {
172	0	default:
173	0	printf("Operand group %d not handled\n", op_group);
174	0	break;
175	260k	case SystemZ_OP_GROUP_Operand: {
176	260k	cs_op_type secondary_op_type = map_get_op_type(MI, op_num) &
177	260k	~(CS_OP_MEM \| CS_OP_BOUND);
178	260k	if (secondary_op_type == CS_OP_IMM) {
179	0	SystemZ_set_detail_op_imm(
180	0	MI, op_num, MCInst_getOpVal(MI, op_num), 0);
181	260k	} else if (secondary_op_type == CS_OP_REG) {
182	260k	SystemZ_set_detail_op_reg(MI, op_num,
183	260k	MCInst_getOpVal(MI, op_num));
184	260k	} else {
185	0	CS_ASSERT_RET(0 && "Op type not handled.");
186	0	}
187	260k	break;
188	260k	}
189	260k	case SystemZ_OP_GROUP_Cond4Operand: {
190	0	systemz_cc cc = MCInst_getOpVal(MI, op_num);
191	0	SystemZ_get_detail(MI)->cc = cc;
192	0	break;
193	260k	}
194	51.1k	case SystemZ_OP_GROUP_BDAddrOperand:
195	51.1k	CS_ASSERT_RET(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
196	51.1k	CS_ASSERT_RET(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
197	51.1k	CS_ASSERT_RET(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
198	51.1k	CS_ASSERT_RET(
199	51.1k	MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
200	51.1k	SystemZ_set_detail_op_mem(MI, op_num,
201	51.1k	MCInst_getOpVal(MI, (op_num)),
202	51.1k	MCInst_getOpVal(MI, (op_num + 1)), 0,
203	51.1k	0, SYSTEMZ_AM_BD);
204	51.1k	break;
205	2.30k	case SystemZ_OP_GROUP_BDVAddrOperand:
206	50.9k	case SystemZ_OP_GROUP_BDXAddrOperand: {
207	50.9k	CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
208	50.9k	CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
209	50.9k	CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
210	50.9k	CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
211	50.9k	CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
212	50.9k	CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2))));
213	50.9k	SystemZ_set_detail_op_mem(
214	50.9k	MI, op_num, MCInst_getOpVal(MI, (op_num)),
215	50.9k	MCInst_getOpVal(MI, (op_num + 1)), 0,
216	50.9k	MCInst_getOpVal(MI, (op_num + 2)),
217	50.9k	(op_group == SystemZ_OP_GROUP_BDXAddrOperand ?
218	48.6k	SYSTEMZ_AM_BDX :
219	50.9k	SYSTEMZ_AM_BDV));
220	50.9k	break;
221	2.30k	}
222	16.5k	case SystemZ_OP_GROUP_BDLAddrOperand:
223	16.5k	CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
224	16.5k	CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
225	16.5k	CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
226	16.5k	CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
227	16.5k	CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
228	16.5k	CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 2))));
229	16.5k	SystemZ_set_detail_op_mem(MI, op_num,
230	16.5k	MCInst_getOpVal(MI, (op_num)),
231	16.5k	MCInst_getOpVal(MI, (op_num + 1)),
232	16.5k	MCInst_getOpVal(MI, (op_num + 2)), 0,
233	16.5k	SYSTEMZ_AM_BDL);
234	16.5k	break;
235	935	case SystemZ_OP_GROUP_BDRAddrOperand:
236	935	CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
237	935	CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
238	935	CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
239	935	CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
240	935	CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
241	935	CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2))));
242	935	SystemZ_set_detail_op_mem(MI, op_num,
243	935	MCInst_getOpVal(MI, (op_num)),
244	935	MCInst_getOpVal(MI, (op_num + 1)),
245	935	MCInst_getOpVal(MI, (op_num + 2)), 0,
246	935	SYSTEMZ_AM_BDL);
247	935	break;
248	6.61k	case SystemZ_OP_GROUP_PCRelOperand:
249	6.61k	SystemZ_set_detail_op_imm(MI, op_num,
250	6.61k	MCInst_getOpVal(MI, op_num), 0);
251	6.61k	break;
252	3.80k	case SystemZ_OP_GROUP_U1ImmOperand:
253	3.80k	SystemZ_set_detail_op_imm(MI, op_num,
254	3.80k	MCInst_getOpVal(MI, op_num), 1);
255	3.80k	break;
256	1.44k	case SystemZ_OP_GROUP_U2ImmOperand:
257	1.44k	SystemZ_set_detail_op_imm(MI, op_num,
258	1.44k	MCInst_getOpVal(MI, op_num), 2);
259	1.44k	break;
260	2.32k	case SystemZ_OP_GROUP_U3ImmOperand:
261	2.32k	SystemZ_set_detail_op_imm(MI, op_num,
262	2.32k	MCInst_getOpVal(MI, op_num), 3);
263	2.32k	break;
264	37.1k	case SystemZ_OP_GROUP_U4ImmOperand:
265	37.1k	SystemZ_set_detail_op_imm(MI, op_num,
266	37.1k	MCInst_getOpVal(MI, op_num), 4);
267	37.1k	break;
268	12.7k	case SystemZ_OP_GROUP_U8ImmOperand:
269	16.5k	case SystemZ_OP_GROUP_S8ImmOperand:
270	16.5k	SystemZ_set_detail_op_imm(MI, op_num,
271	16.5k	MCInst_getOpVal(MI, op_num), 8);
272	16.5k	break;
273	476	case SystemZ_OP_GROUP_U12ImmOperand:
274	476	SystemZ_set_detail_op_imm(MI, op_num,
275	476	MCInst_getOpVal(MI, op_num), 12);
276	476	break;
277	1.89k	case SystemZ_OP_GROUP_U16ImmOperand:
278	6.41k	case SystemZ_OP_GROUP_S16ImmOperand:
279	6.41k	SystemZ_set_detail_op_imm(MI, op_num,
280	6.41k	MCInst_getOpVal(MI, op_num), 16);
281	6.41k	break;
282	2.11k	case SystemZ_OP_GROUP_U32ImmOperand:
283	3.11k	case SystemZ_OP_GROUP_S32ImmOperand:
284	3.11k	SystemZ_set_detail_op_imm(MI, op_num,
285	3.11k	MCInst_getOpVal(MI, op_num), 32);
286	3.11k	break;
287	0	case SystemZ_OP_GROUP_U48ImmOperand:
288	0	SystemZ_set_detail_op_imm(MI, op_num,
289	0	MCInst_getOpVal(MI, op_num), 48);
290	0	break;
291	457k	}
292	457k	#endif
293	457k	}
294
295		#ifndef CAPSTONE_DIET
296
297		void SystemZ_set_detail_op_imm(MCInst *MI, unsigned op_num, int64_t Imm,
298		size_t width)
299	77.9k	{
300	77.9k	if (!detail_is_set(MI))
301	0	return;
302	77.9k	CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_IMM);
303
304	77.9k	SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_IMM;
305	77.9k	SystemZ_get_detail_op(MI, 0)->imm = Imm;
306	77.9k	SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
307	77.9k	SystemZ_get_detail_op(MI, 0)->imm_width = width;
308	77.9k	SystemZ_inc_op_count(MI);
309	77.9k	}
310
311		void SystemZ_set_detail_op_reg(MCInst *MI, unsigned op_num, systemz_reg Reg)
312	260k	{
313	260k	if (!detail_is_set(MI))
314	0	return;
315	260k	CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_REG);
316	260k	if (Reg == SYSTEMZ_REG_INVALID) {
317		// This case is legal. The ISA says:
318		// "
319		// When the R1 field is not zero, bits 8-15 of the instruction designated
320		// by the second-operand address are ORed with bits 56-63 of
321		// general register R1. [...] When the R1 field is zero, no ORing takes place
322		// "
323		// This means we just save the neutral element for ORing, so 0.
324	815	SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_IMM;
325	815	SystemZ_get_detail_op(MI, 0)->imm = 0;
326	815	SystemZ_get_detail_op(MI, 0)->access =
327	815	map_get_op_access(MI, op_num);
328	815	SystemZ_get_detail_op(MI, 0)->imm_width = 0;
329	815	SystemZ_inc_op_count(MI);
330	815	return;
331	815	}
332
333	259k	SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_REG;
334	259k	SystemZ_get_detail_op(MI, 0)->reg = Reg;
335	259k	SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
336	259k	SystemZ_inc_op_count(MI);
337	259k	}
338
339		void SystemZ_set_detail_op_mem(MCInst *MI, unsigned op_num, systemz_reg base,
340		int64_t disp, uint64_t length, systemz_reg index,
341		systemz_addr_mode am)
342	119k	{
343	119k	if (!detail_is_set(MI))
344	0	return;
345	119k	SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_MEM;
346	119k	SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
347	119k	SystemZ_get_detail_op(MI, 0)->mem.am = am;
348	119k	switch (am) {
349	0	default:
350	0	CS_ASSERT(0 && "Address mode not handled\n");
351	0	break;
352	51.1k	case SYSTEMZ_AM_BD:
353	51.1k	SystemZ_get_detail_op(MI, 0)->mem.base = base;
354	51.1k	SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
355	51.1k	break;
356	48.6k	case SYSTEMZ_AM_BDX:
357	50.9k	case SYSTEMZ_AM_BDV:
358	50.9k	SystemZ_get_detail_op(MI, 0)->mem.base = base;
359	50.9k	SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
360	50.9k	SystemZ_get_detail_op(MI, 0)->mem.index = index;
361	50.9k	break;
362	17.4k	case SYSTEMZ_AM_BDL:
363	17.4k	SystemZ_get_detail_op(MI, 0)->mem.base = base;
364	17.4k	SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
365	17.4k	SystemZ_get_detail_op(MI, 0)->mem.length = length;
366	17.4k	break;
367	0	case SYSTEMZ_AM_BDR:
368	0	SystemZ_get_detail_op(MI, 0)->mem.base = base;
369	0	SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
370	0	SystemZ_get_detail_op(MI, 0)->mem.length = length;
371	0	break;
372	119k	}
373	119k	SystemZ_inc_op_count(MI);
374	119k	}
375
376		#endif
377
378		#endif