/src/capstonev5/arch/Sparc/SparcDisassembler.c

Source
//===------ SparcDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//

/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

#ifdef CAPSTONE_HAS_SPARC

#include <stdio.h>  // DEBUG
#include <stdlib.h>
#include <string.h>

#include "../../cs_priv.h"
#include "../../utils.h"

#include "SparcDisassembler.h"

#include "../../MCInst.h"
#include "../../MCInstrDesc.h"
#include "../../MCFixedLenDisassembler.h"
#include "../../MCRegisterInfo.h"
#include "../../MCDisassembler.h"
#include "../../MathExtras.h"


#define GET_REGINFO_MC_DESC
#define GET_REGINFO_ENUM
#include "SparcGenRegisterInfo.inc"
static const unsigned IntRegDecoderTable[] = {
  SP_G0,  SP_G1,  SP_G2,  SP_G3,
  SP_G4,  SP_G5,  SP_G6,  SP_G7,
  SP_O0,  SP_O1,  SP_O2,  SP_O3,
  SP_O4,  SP_O5,  SP_O6,  SP_O7,
  SP_L0,  SP_L1,  SP_L2,  SP_L3,
  SP_L4,  SP_L5,  SP_L6,  SP_L7,
  SP_I0,  SP_I1,  SP_I2,  SP_I3,
  SP_I4,  SP_I5,  SP_I6,  SP_I7
};

static const unsigned FPRegDecoderTable[] = {
  SP_F0,   SP_F1,   SP_F2,   SP_F3,
  SP_F4,   SP_F5,   SP_F6,   SP_F7,
  SP_F8,   SP_F9,   SP_F10,  SP_F11,
  SP_F12,  SP_F13,  SP_F14,  SP_F15,
  SP_F16,  SP_F17,  SP_F18,  SP_F19,
  SP_F20,  SP_F21,  SP_F22,  SP_F23,
  SP_F24,  SP_F25,  SP_F26,  SP_F27,
  SP_F28,  SP_F29,  SP_F30,  SP_F31
};

static const unsigned DFPRegDecoderTable[] = {
  SP_D0,   SP_D16,  SP_D1,   SP_D17,
  SP_D2,   SP_D18,  SP_D3,   SP_D19,
  SP_D4,   SP_D20,  SP_D5,   SP_D21,
  SP_D6,   SP_D22,  SP_D7,   SP_D23,
  SP_D8,   SP_D24,  SP_D9,   SP_D25,
  SP_D10,  SP_D26,  SP_D11,  SP_D27,
  SP_D12,  SP_D28,  SP_D13,  SP_D29,
  SP_D14,  SP_D30,  SP_D15,  SP_D31
};

static const unsigned QFPRegDecoderTable[] = {
  SP_Q0,  SP_Q8,   ~0U,  ~0U,
  SP_Q1,  SP_Q9,   ~0U,  ~0U,
  SP_Q2,  SP_Q10,  ~0U,  ~0U,
  SP_Q3,  SP_Q11,  ~0U,  ~0U,
  SP_Q4,  SP_Q12,  ~0U,  ~0U,
  SP_Q5,  SP_Q13,  ~0U,  ~0U,
  SP_Q6,  SP_Q14,  ~0U,  ~0U,
  SP_Q7,  SP_Q15,  ~0U,  ~0U
};

static const unsigned FCCRegDecoderTable[] = {
  SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3
};

static uint64_t getFeatureBits(int mode)
{
  // support everything
  return (uint64_t)-1;
}

static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo,
    uint64_t Address, const void *Decoder)
{
  unsigned Reg;

  if (RegNo > 31)
    return MCDisassembler_Fail;

  Reg = IntRegDecoderTable[RegNo];
  MCOperand_CreateReg0(Inst, Reg);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo,
    uint64_t Address, const void *Decoder)
{
  unsigned Reg;

  if (RegNo > 31)
    return MCDisassembler_Fail;

  Reg = IntRegDecoderTable[RegNo];
  MCOperand_CreateReg0(Inst, Reg);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
    uint64_t Address, const void *Decoder)
{
  unsigned Reg;

  if (RegNo > 31)
    return MCDisassembler_Fail;

  Reg = FPRegDecoderTable[RegNo];
  MCOperand_CreateReg0(Inst, Reg);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
    uint64_t Address, const void *Decoder)
{
  unsigned Reg;

  if (RegNo > 31)
    return MCDisassembler_Fail;

  Reg = DFPRegDecoderTable[RegNo];
  MCOperand_CreateReg0(Inst, Reg);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
    uint64_t Address, const void *Decoder)
{
  unsigned Reg;

  if (RegNo > 31)
    return MCDisassembler_Fail;

  Reg = QFPRegDecoderTable[RegNo];
  if (Reg == ~0U)
    return MCDisassembler_Fail;

  MCOperand_CreateReg0(Inst, Reg);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo,
    uint64_t Address, const void *Decoder)
{
  if (RegNo > 3)
    return MCDisassembler_Fail;

  MCOperand_CreateReg0(Inst, FCCRegDecoderTable[RegNo]);

  return MCDisassembler_Success;
}


static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address,
    const void *Decoder);
static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address,
    const void *Decoder);
static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address,
    const void *Decoder);
static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address,
    const void *Decoder);
static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn,
    uint64_t Address, const void *Decoder);
static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn,
    uint64_t Address, const void *Decoder);
static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn,
    uint64_t Address, const void *Decoder);
static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn,
    uint64_t Address, const void *Decoder);
static DecodeStatus DecodeCall(MCInst *Inst, unsigned insn,
    uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSIMM13(MCInst *Inst, unsigned insn,
    uint64_t Address, const void *Decoder);
static DecodeStatus DecodeJMPL(MCInst *Inst, unsigned insn, uint64_t Address,
    const void *Decoder);
static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address,
    const void *Decoder);
static DecodeStatus DecodeSWAP(MCInst *Inst, unsigned insn, uint64_t Address,
    const void *Decoder);


#define GET_SUBTARGETINFO_ENUM
#include "SparcGenSubtargetInfo.inc"
#include "SparcGenDisassemblerTables.inc"

/// readInstruction - read four bytes and return 32 bit word.
static DecodeStatus readInstruction32(const uint8_t *code, size_t len, uint32_t *Insn)
{
  if (len < 4)
    // not enough data
    return MCDisassembler_Fail;

  // Encoded as a big-endian 32-bit word in the stream.
  *Insn = (code[3] <<  0) |
    (code[2] <<  8) |
    (code[1] << 16) |
    ((uint32_t) code[0] << 24);

  return MCDisassembler_Success;
}

bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,
    uint16_t *size, uint64_t address, void *info)
{
  uint32_t Insn;
  DecodeStatus Result;
  
  Result = readInstruction32(code, code_len, &Insn);
  if (Result == MCDisassembler_Fail)
    return false;

  if (MI->flat_insn->detail) {
    memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sparc)+sizeof(cs_sparc));
  }

  Result = decodeInstruction_4(DecoderTableSparc32, MI, Insn, address,
      (MCRegisterInfo *)info, 0);
  if (Result != MCDisassembler_Fail) {
    *size = 4;
    return true;
  }

  return false;
}

typedef DecodeStatus (*DecodeFunc)(MCInst *MI, unsigned insn, uint64_t Address,
    const void *Decoder);

static DecodeStatus DecodeMem(MCInst *MI, unsigned insn, uint64_t Address,
    const void *Decoder,
    bool isLoad, DecodeFunc DecodeRD)
{
  DecodeStatus status;
  unsigned rd = fieldFromInstruction_4(insn, 25, 5);
  unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
  bool isImm = fieldFromInstruction_4(insn, 13, 1) != 0;
  unsigned rs2 = 0;
  unsigned simm13 = 0;

  if (isImm)
    simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
  else
    rs2 = fieldFromInstruction_4(insn, 0, 5);

  if (isLoad) {
    status = DecodeRD(MI, rd, Address, Decoder);
    if (status != MCDisassembler_Success)
      return status;
  }

  // Decode rs1.
  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
  if (status != MCDisassembler_Success)
    return status;

  // Decode imm|rs2.
  if (isImm)
    MCOperand_CreateImm0(MI, simm13);
  else {
    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
    if (status != MCDisassembler_Success)
      return status;
  }

  if (!isLoad) {
    status = DecodeRD(MI, rd, Address, Decoder);
    if (status != MCDisassembler_Success)
      return status;
  }

  return MCDisassembler_Success;
}

static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address,
    const void *Decoder)
{
  return DecodeMem(Inst, insn, Address, Decoder, true,
      DecodeIntRegsRegisterClass);
}

static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address,
    const void *Decoder)
{
  return DecodeMem(Inst, insn, Address, Decoder, true,
      DecodeFPRegsRegisterClass);
}

static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address,
    const void *Decoder)
{
  return DecodeMem(Inst, insn, Address, Decoder, true,
      DecodeDFPRegsRegisterClass);
}

static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address,
    const void *Decoder)
{
  return DecodeMem(Inst, insn, Address, Decoder, true,
      DecodeQFPRegsRegisterClass);
}

static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn,
    uint64_t Address, const void *Decoder)
{
  return DecodeMem(Inst, insn, Address, Decoder, false,
      DecodeIntRegsRegisterClass);
}

static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, uint64_t Address,
    const void *Decoder)
{
  return DecodeMem(Inst, insn, Address, Decoder, false,
      DecodeFPRegsRegisterClass);
}

static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn,
    uint64_t Address, const void *Decoder)
{
  return DecodeMem(Inst, insn, Address, Decoder, false,
      DecodeDFPRegsRegisterClass);
}

static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn,
    uint64_t Address, const void *Decoder)
{
  return DecodeMem(Inst, insn, Address, Decoder, false,
      DecodeQFPRegsRegisterClass);
}

static DecodeStatus DecodeCall(MCInst *MI, unsigned insn,
    uint64_t Address, const void *Decoder)
{
  unsigned tgt = fieldFromInstruction_4(insn, 0, 30);
  tgt <<= 2;

  MCOperand_CreateImm0(MI, tgt);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeSIMM13(MCInst *MI, unsigned insn,
    uint64_t Address, const void *Decoder)
{
  unsigned tgt = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);

  MCOperand_CreateImm0(MI, tgt);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeJMPL(MCInst *MI, unsigned insn, uint64_t Address,
    const void *Decoder)
{
  DecodeStatus status;
  unsigned rd = fieldFromInstruction_4(insn, 25, 5);
  unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
  unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
  unsigned rs2 = 0;
  unsigned simm13 = 0;

  if (isImm)
    simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
  else
    rs2 = fieldFromInstruction_4(insn, 0, 5);

  // Decode RD.
  status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
  if (status != MCDisassembler_Success)
    return status;

  // Decode RS1.
  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
  if (status != MCDisassembler_Success)
    return status;

  // Decode RS1 | SIMM13.
  if (isImm)
    MCOperand_CreateImm0(MI, simm13);
  else {
    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
    if (status != MCDisassembler_Success)
      return status;
  }

  return MCDisassembler_Success;
}

static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address,
    const void *Decoder)
{
  DecodeStatus status;
  unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
  unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
  unsigned rs2 = 0;
  unsigned simm13 = 0;
  if (isImm)
    simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
  else
    rs2 = fieldFromInstruction_4(insn, 0, 5);

  // Decode RS1.
  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
  if (status != MCDisassembler_Success)
    return status;

  // Decode RS2 | SIMM13.
  if (isImm)
    MCOperand_CreateImm0(MI, simm13);
  else {
    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
    if (status != MCDisassembler_Success)
      return status;
  }

  return MCDisassembler_Success;
}

static DecodeStatus DecodeSWAP(MCInst *MI, unsigned insn, uint64_t Address,
    const void *Decoder)
{
  DecodeStatus status;
  unsigned rd = fieldFromInstruction_4(insn, 25, 5);
  unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
  unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
  unsigned rs2 = 0;
  unsigned simm13 = 0;

  if (isImm)
    simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
  else
    rs2 = fieldFromInstruction_4(insn, 0, 5);

  // Decode RD.
  status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
  if (status != MCDisassembler_Success)
    return status;

  // Decode RS1.
  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
  if (status != MCDisassembler_Success)
    return status;

  // Decode RS1 | SIMM13.
  if (isImm)
    MCOperand_CreateImm0(MI, simm13);
  else {
    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
    if (status != MCDisassembler_Success)
      return status;
  }

  return MCDisassembler_Success;
}

void Sparc_init(MCRegisterInfo *MRI)
{
  /*
  InitMCRegisterInfo(SparcRegDesc, 119, RA, PC,
      SparcMCRegisterClasses, 8,
      SparcRegUnitRoots,
      86,
      SparcRegDiffLists,
      SparcRegStrings,
      SparcSubRegIdxLists,
      7,
      SparcSubRegIdxRanges,
      SparcRegEncodingTable);
  */

  MCRegisterInfo_InitMCRegisterInfo(MRI, SparcRegDesc, 119,
      0, 0,
      SparcMCRegisterClasses, 8,
      0, 0,
      SparcRegDiffLists,
      0,
      SparcSubRegIdxLists, 7,
      0);
}

#endif

Coverage Report

Created: 2025-11-24 06:12

Line	Count	Source
1		//===------ SparcDisassembler.cpp - Disassembler for PowerPC ------- C++ --===//
2		//
3		// The LLVM Compiler Infrastructure
4		//
5		// This file is distributed under the University of Illinois Open Source
6		// License. See LICENSE.TXT for details.
7		//
8		//===----------------------------------------------------------------------===//
9
10		/* Capstone Disassembly Engine */
11		/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
12
13		#ifdef CAPSTONE_HAS_SPARC
14
15		#include <stdio.h> // DEBUG
16		#include <stdlib.h>
17		#include <string.h>
18
19		#include "../../cs_priv.h"
20		#include "../../utils.h"
21
22		#include "SparcDisassembler.h"
23
24		#include "../../MCInst.h"
25		#include "../../MCInstrDesc.h"
26		#include "../../MCFixedLenDisassembler.h"
27		#include "../../MCRegisterInfo.h"
28		#include "../../MCDisassembler.h"
29		#include "../../MathExtras.h"
30
31
32		#define GET_REGINFO_MC_DESC
33		#define GET_REGINFO_ENUM
34		#include "SparcGenRegisterInfo.inc"
35		static const unsigned IntRegDecoderTable[] = {
36		SP_G0, SP_G1, SP_G2, SP_G3,
37		SP_G4, SP_G5, SP_G6, SP_G7,
38		SP_O0, SP_O1, SP_O2, SP_O3,
39		SP_O4, SP_O5, SP_O6, SP_O7,
40		SP_L0, SP_L1, SP_L2, SP_L3,
41		SP_L4, SP_L5, SP_L6, SP_L7,
42		SP_I0, SP_I1, SP_I2, SP_I3,
43		SP_I4, SP_I5, SP_I6, SP_I7
44		};
45
46		static const unsigned FPRegDecoderTable[] = {
47		SP_F0, SP_F1, SP_F2, SP_F3,
48		SP_F4, SP_F5, SP_F6, SP_F7,
49		SP_F8, SP_F9, SP_F10, SP_F11,
50		SP_F12, SP_F13, SP_F14, SP_F15,
51		SP_F16, SP_F17, SP_F18, SP_F19,
52		SP_F20, SP_F21, SP_F22, SP_F23,
53		SP_F24, SP_F25, SP_F26, SP_F27,
54		SP_F28, SP_F29, SP_F30, SP_F31
55		};
56
57		static const unsigned DFPRegDecoderTable[] = {
58		SP_D0, SP_D16, SP_D1, SP_D17,
59		SP_D2, SP_D18, SP_D3, SP_D19,
60		SP_D4, SP_D20, SP_D5, SP_D21,
61		SP_D6, SP_D22, SP_D7, SP_D23,
62		SP_D8, SP_D24, SP_D9, SP_D25,
63		SP_D10, SP_D26, SP_D11, SP_D27,
64		SP_D12, SP_D28, SP_D13, SP_D29,
65		SP_D14, SP_D30, SP_D15, SP_D31
66		};
67
68		static const unsigned QFPRegDecoderTable[] = {
69		SP_Q0, SP_Q8, ~0U, ~0U,
70		SP_Q1, SP_Q9, ~0U, ~0U,
71		SP_Q2, SP_Q10, ~0U, ~0U,
72		SP_Q3, SP_Q11, ~0U, ~0U,
73		SP_Q4, SP_Q12, ~0U, ~0U,
74		SP_Q5, SP_Q13, ~0U, ~0U,
75		SP_Q6, SP_Q14, ~0U, ~0U,
76		SP_Q7, SP_Q15, ~0U, ~0U
77		};
78
79		static const unsigned FCCRegDecoderTable[] = {
80		SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3
81		};
82
83		static uint64_t getFeatureBits(int mode)
84	15.9k	{
85		// support everything
86	15.9k	return (uint64_t)-1;
87	15.9k	}
88
89		static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo,
90		uint64_t Address, const void *Decoder)
91	6.61k	{
92	6.61k	unsigned Reg;
93
94	6.61k	if (RegNo > 31)
95	0	return MCDisassembler_Fail;
96
97	6.61k	Reg = IntRegDecoderTable[RegNo];
98	6.61k	MCOperand_CreateReg0(Inst, Reg);
99
100	6.61k	return MCDisassembler_Success;
101	6.61k	}
102
103		static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo,
104		uint64_t Address, const void *Decoder)
105	1.38k	{
106	1.38k	unsigned Reg;
107
108	1.38k	if (RegNo > 31)
109	0	return MCDisassembler_Fail;
110
111	1.38k	Reg = IntRegDecoderTable[RegNo];
112	1.38k	MCOperand_CreateReg0(Inst, Reg);
113
114	1.38k	return MCDisassembler_Success;
115	1.38k	}
116
117		static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
118		uint64_t Address, const void *Decoder)
119	770	{
120	770	unsigned Reg;
121
122	770	if (RegNo > 31)
123	0	return MCDisassembler_Fail;
124
125	770	Reg = FPRegDecoderTable[RegNo];
126	770	MCOperand_CreateReg0(Inst, Reg);
127
128	770	return MCDisassembler_Success;
129	770	}
130
131		static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
132		uint64_t Address, const void *Decoder)
133	650	{
134	650	unsigned Reg;
135
136	650	if (RegNo > 31)
137	0	return MCDisassembler_Fail;
138
139	650	Reg = DFPRegDecoderTable[RegNo];
140	650	MCOperand_CreateReg0(Inst, Reg);
141
142	650	return MCDisassembler_Success;
143	650	}
144
145		static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
146		uint64_t Address, const void *Decoder)
147	738	{
148	738	unsigned Reg;
149
150	738	if (RegNo > 31)
151	0	return MCDisassembler_Fail;
152
153	738	Reg = QFPRegDecoderTable[RegNo];
154	738	if (Reg == ~0U)
155	4	return MCDisassembler_Fail;
156
157	734	MCOperand_CreateReg0(Inst, Reg);
158
159	734	return MCDisassembler_Success;
160	738	}
161
162		static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo,
163		uint64_t Address, const void *Decoder)
164	1.43k	{
165	1.43k	if (RegNo > 3)
166	1	return MCDisassembler_Fail;
167
168	1.43k	MCOperand_CreateReg0(Inst, FCCRegDecoderTable[RegNo]);
169
170	1.43k	return MCDisassembler_Success;
171	1.43k	}
172
173
174		static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address,
175		const void *Decoder);
176		static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address,
177		const void *Decoder);
178		static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address,
179		const void *Decoder);
180		static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address,
181		const void *Decoder);
182		static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn,
183		uint64_t Address, const void *Decoder);
184		static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn,
185		uint64_t Address, const void *Decoder);
186		static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn,
187		uint64_t Address, const void *Decoder);
188		static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn,
189		uint64_t Address, const void *Decoder);
190		static DecodeStatus DecodeCall(MCInst *Inst, unsigned insn,
191		uint64_t Address, const void *Decoder);
192		static DecodeStatus DecodeSIMM13(MCInst *Inst, unsigned insn,
193		uint64_t Address, const void *Decoder);
194		static DecodeStatus DecodeJMPL(MCInst *Inst, unsigned insn, uint64_t Address,
195		const void *Decoder);
196		static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address,
197		const void *Decoder);
198		static DecodeStatus DecodeSWAP(MCInst *Inst, unsigned insn, uint64_t Address,
199		const void *Decoder);
200
201
202		#define GET_SUBTARGETINFO_ENUM
203		#include "SparcGenSubtargetInfo.inc"
204		#include "SparcGenDisassemblerTables.inc"
205
206		/// readInstruction - read four bytes and return 32 bit word.
207		static DecodeStatus readInstruction32(const uint8_t code, size_t len, uint32_t Insn)
208	15.9k	{
209	15.9k	if (len < 4)
210		// not enough data
211	67	return MCDisassembler_Fail;
212
213		// Encoded as a big-endian 32-bit word in the stream.
214	15.9k	*Insn = (code[3] << 0) \|
215	15.9k	(code[2] << 8) \|
216	15.9k	(code[1] << 16) \|
217	15.9k	((uint32_t) code[0] << 24);
218
219	15.9k	return MCDisassembler_Success;
220	15.9k	}
221
222		bool Sparc_getInstruction(csh ud, const uint8_t code, size_t code_len, MCInst MI,
223		uint16_t size, uint64_t address, void info)
224	15.9k	{
225	15.9k	uint32_t Insn;
226	15.9k	DecodeStatus Result;
227
228	15.9k	Result = readInstruction32(code, code_len, &Insn);
229	15.9k	if (Result == MCDisassembler_Fail)
230	67	return false;
231
232	15.9k	if (MI->flat_insn->detail) {
233	15.9k	memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sparc)+sizeof(cs_sparc));
234	15.9k	}
235
236	15.9k	Result = decodeInstruction_4(DecoderTableSparc32, MI, Insn, address,
237	15.9k	(MCRegisterInfo *)info, 0);
238	15.9k	if (Result != MCDisassembler_Fail) {
239	15.8k	*size = 4;
240	15.8k	return true;
241	15.8k	}
242
243	31	return false;
244	15.9k	}
245
246		typedef DecodeStatus (DecodeFunc)(MCInst MI, unsigned insn, uint64_t Address,
247		const void *Decoder);
248
249		static DecodeStatus DecodeMem(MCInst *MI, unsigned insn, uint64_t Address,
250		const void *Decoder,
251		bool isLoad, DecodeFunc DecodeRD)
252	428	{
253	428	DecodeStatus status;
254	428	unsigned rd = fieldFromInstruction_4(insn, 25, 5);
255	428	unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
256	428	bool isImm = fieldFromInstruction_4(insn, 13, 1) != 0;
257	428	unsigned rs2 = 0;
258	428	unsigned simm13 = 0;
259
260	428	if (isImm)
261	324	simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
262	104	else
263	104	rs2 = fieldFromInstruction_4(insn, 0, 5);
264
265	428	if (isLoad) {
266	377	status = DecodeRD(MI, rd, Address, Decoder);
267	377	if (status != MCDisassembler_Success)
268	1	return status;
269	377	}
270
271		// Decode rs1.
272	427	status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
273	427	if (status != MCDisassembler_Success)
274	0	return status;
275
276		// Decode imm\|rs2.
277	427	if (isImm)
278	323	MCOperand_CreateImm0(MI, simm13);
279	104	else {
280	104	status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
281	104	if (status != MCDisassembler_Success)
282	0	return status;
283	104	}
284
285	427	if (!isLoad) {
286	51	status = DecodeRD(MI, rd, Address, Decoder);
287	51	if (status != MCDisassembler_Success)
288	0	return status;
289	51	}
290
291	427	return MCDisassembler_Success;
292	427	}
293
294		static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address,
295		const void *Decoder)
296	122	{
297	122	return DecodeMem(Inst, insn, Address, Decoder, true,
298	122	DecodeIntRegsRegisterClass);
299	122	}
300
301		static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address,
302		const void *Decoder)
303	140	{
304	140	return DecodeMem(Inst, insn, Address, Decoder, true,
305	140	DecodeFPRegsRegisterClass);
306	140	}
307
308		static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address,
309		const void *Decoder)
310	111	{
311	111	return DecodeMem(Inst, insn, Address, Decoder, true,
312	111	DecodeDFPRegsRegisterClass);
313	111	}
314
315		static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address,
316		const void *Decoder)
317	4	{
318	4	return DecodeMem(Inst, insn, Address, Decoder, true,
319	4	DecodeQFPRegsRegisterClass);
320	4	}
321
322		static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn,
323		uint64_t Address, const void *Decoder)
324	11	{
325	11	return DecodeMem(Inst, insn, Address, Decoder, false,
326	11	DecodeIntRegsRegisterClass);
327	11	}
328
329		static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, uint64_t Address,
330		const void *Decoder)
331	34	{
332	34	return DecodeMem(Inst, insn, Address, Decoder, false,
333	34	DecodeFPRegsRegisterClass);
334	34	}
335
336		static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn,
337		uint64_t Address, const void *Decoder)
338	3	{
339	3	return DecodeMem(Inst, insn, Address, Decoder, false,
340	3	DecodeDFPRegsRegisterClass);
341	3	}
342
343		static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn,
344		uint64_t Address, const void *Decoder)
345	3	{
346	3	return DecodeMem(Inst, insn, Address, Decoder, false,
347	3	DecodeQFPRegsRegisterClass);
348	3	}
349
350		static DecodeStatus DecodeCall(MCInst *MI, unsigned insn,
351		uint64_t Address, const void *Decoder)
352	4.13k	{
353	4.13k	unsigned tgt = fieldFromInstruction_4(insn, 0, 30);
354	4.13k	tgt <<= 2;
355
356	4.13k	MCOperand_CreateImm0(MI, tgt);
357
358	4.13k	return MCDisassembler_Success;
359	4.13k	}
360
361		static DecodeStatus DecodeSIMM13(MCInst *MI, unsigned insn,
362		uint64_t Address, const void *Decoder)
363	674	{
364	674	unsigned tgt = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
365
366	674	MCOperand_CreateImm0(MI, tgt);
367
368	674	return MCDisassembler_Success;
369	674	}
370
371		static DecodeStatus DecodeJMPL(MCInst *MI, unsigned insn, uint64_t Address,
372		const void *Decoder)
373	112	{
374	112	DecodeStatus status;
375	112	unsigned rd = fieldFromInstruction_4(insn, 25, 5);
376	112	unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
377	112	unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
378	112	unsigned rs2 = 0;
379	112	unsigned simm13 = 0;
380
381	112	if (isImm)
382	69	simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
383	43	else
384	43	rs2 = fieldFromInstruction_4(insn, 0, 5);
385
386		// Decode RD.
387	112	status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
388	112	if (status != MCDisassembler_Success)
389	0	return status;
390
391		// Decode RS1.
392	112	status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
393	112	if (status != MCDisassembler_Success)
394	0	return status;
395
396		// Decode RS1 \| SIMM13.
397	112	if (isImm)
398	69	MCOperand_CreateImm0(MI, simm13);
399	43	else {
400	43	status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
401	43	if (status != MCDisassembler_Success)
402	0	return status;
403	43	}
404
405	112	return MCDisassembler_Success;
406	112	}
407
408		static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address,
409		const void *Decoder)
410	17	{
411	17	DecodeStatus status;
412	17	unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
413	17	unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
414	17	unsigned rs2 = 0;
415	17	unsigned simm13 = 0;
416	17	if (isImm)
417	17	simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
418	0	else
419	0	rs2 = fieldFromInstruction_4(insn, 0, 5);
420
421		// Decode RS1.
422	17	status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
423	17	if (status != MCDisassembler_Success)
424	0	return status;
425
426		// Decode RS2 \| SIMM13.
427	17	if (isImm)
428	17	MCOperand_CreateImm0(MI, simm13);
429	0	else {
430	0	status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
431	0	if (status != MCDisassembler_Success)
432	0	return status;
433	0	}
434
435	17	return MCDisassembler_Success;
436	17	}
437
438		static DecodeStatus DecodeSWAP(MCInst *MI, unsigned insn, uint64_t Address,
439		const void *Decoder)
440	4	{
441	4	DecodeStatus status;
442	4	unsigned rd = fieldFromInstruction_4(insn, 25, 5);
443	4	unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
444	4	unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
445	4	unsigned rs2 = 0;
446	4	unsigned simm13 = 0;
447
448	4	if (isImm)
449	3	simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
450	1	else
451	1	rs2 = fieldFromInstruction_4(insn, 0, 5);
452
453		// Decode RD.
454	4	status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
455	4	if (status != MCDisassembler_Success)
456	0	return status;
457
458		// Decode RS1.
459	4	status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
460	4	if (status != MCDisassembler_Success)
461	0	return status;
462
463		// Decode RS1 \| SIMM13.
464	4	if (isImm)
465	3	MCOperand_CreateImm0(MI, simm13);
466	1	else {
467	1	status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
468	1	if (status != MCDisassembler_Success)
469	0	return status;
470	1	}
471
472	4	return MCDisassembler_Success;
473	4	}
474
475		void Sparc_init(MCRegisterInfo *MRI)
476	346	{
477		/*
478		InitMCRegisterInfo(SparcRegDesc, 119, RA, PC,
479		SparcMCRegisterClasses, 8,
480		SparcRegUnitRoots,
481		86,
482		SparcRegDiffLists,
483		SparcRegStrings,
484		SparcSubRegIdxLists,
485		7,
486		SparcSubRegIdxRanges,
487		SparcRegEncodingTable);
488		*/
489
490	346	MCRegisterInfo_InitMCRegisterInfo(MRI, SparcRegDesc, 119,
491	346	0, 0,
492	346	SparcMCRegisterClasses, 8,
493	346	0, 0,
494	346	SparcRegDiffLists,
495	346	0,
496	346	SparcSubRegIdxLists, 7,
497	346	0);
498	346	}
499
500		#endif