/src/capstonenext/arch/TMS320C64x/TMS320C64xInstPrinter.c

Source
/* Capstone Disassembly Engine */
/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */

#ifdef CAPSTONE_HAS_TMS320C64X

#include <ctype.h>
#include <string.h>

#include "TMS320C64xInstPrinter.h"
#include "../../MCInst.h"
#include "../../utils.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "../../MathExtras.h"
#include "TMS320C64xMapping.h"

#include "capstone/tms320c64x.h"

static const char *getRegisterName(unsigned RegNo);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O);
static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O);

void TMS320C64x_post_printer(csh ud, cs_insn *insn, SStream *insn_asm,
           MCInst *mci)
{
  SStream ss;
  const char *op_str_ptr, *p2;
  char tmp[8] = { 0 };
  unsigned int unit = 0;
  int i;
  cs_tms320c64x *tms320c64x;

  if (mci->csh->detail_opt) {
    tms320c64x = &mci->flat_insn->detail->tms320c64x;

    for (i = 0; i < insn->detail->groups_count; i++) {
      switch (insn->detail->groups[i]) {
      case TMS320C64X_GRP_FUNIT_D:
        unit = TMS320C64X_FUNIT_D;
        break;
      case TMS320C64X_GRP_FUNIT_L:
        unit = TMS320C64X_FUNIT_L;
        break;
      case TMS320C64X_GRP_FUNIT_M:
        unit = TMS320C64X_FUNIT_M;
        break;
      case TMS320C64X_GRP_FUNIT_S:
        unit = TMS320C64X_FUNIT_S;
        break;
      case TMS320C64X_GRP_FUNIT_NO:
        unit = TMS320C64X_FUNIT_NO;
        break;
      }
      if (unit != 0)
        break;
    }
    tms320c64x->funit.unit = unit;

    SStream_Init(&ss);
    if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
      SStream_concat(
        &ss, "[%c%s]|",
        (tms320c64x->condition.zero == 1) ? '!' : '|',
        cs_reg_name(ud, tms320c64x->condition.reg));

    // Sorry for all the fixes below. I don't have time to add more helper SStream functions.
    // Before that they messed around with the private buffer of the stream.
    // So it is better now. But still not efficient.
    op_str_ptr = strchr(SStream_rbuf(insn_asm), '\t');

    if ((op_str_ptr != NULL) &&
        (((p2 = strchr(op_str_ptr, '[')) != NULL) ||
         ((p2 = strchr(op_str_ptr, '(')) != NULL))) {
      while ((p2 > op_str_ptr) &&
             ((*p2 != 'a') && (*p2 != 'b')))
        p2--;
      if (p2 == op_str_ptr) {
        SStream_Flush(insn_asm, NULL);
        SStream_concat0(insn_asm, "Invalid!");
        return;
      }
      if (*p2 == 'a')
        strncpy(tmp, "1T", sizeof(tmp));
      else
        strncpy(tmp, "2T", sizeof(tmp));
    } else {
      tmp[0] = '\0';
    }
    SStream mnem_post = { 0 };
    SStream_Init(&mnem_post);
    switch (tms320c64x->funit.unit) {
    case TMS320C64X_FUNIT_D:
      SStream_concat(&mnem_post, ".D%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_L:
      SStream_concat(&mnem_post, ".L%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_M:
      SStream_concat(&mnem_post, ".M%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_S:
      SStream_concat(&mnem_post, ".S%s%u", tmp,
               tms320c64x->funit.side);
      break;
    }
    if (tms320c64x->funit.crosspath > 0)
      SStream_concat0(&mnem_post, "X");

    if (op_str_ptr != NULL) {
      // There is an op_str
      SStream_concat1(&mnem_post, '\t');
      SStream_replc_str(insn_asm, '\t',
            SStream_rbuf(&mnem_post));
    }

    if (tms320c64x->parallel != 0)
      SStream_concat0(insn_asm, "\t||");
    SStream_concat0(&ss, SStream_rbuf(insn_asm));
    SStream_Flush(insn_asm, NULL);
    SStream_concat0(insn_asm, SStream_rbuf(&ss));
  }
}

#define PRINT_ALIAS_INSTR
#include "TMS320C64xGenAsmWriter.inc"

#define GET_INSTRINFO_ENUM
#include "TMS320C64xGenInstrInfo.inc"

static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg;

  if (MCOperand_isReg(Op)) {
    reg = MCOperand_getReg(Op);
    if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) &&
        (OpNo == 1)) {
      switch (reg) {
      case TMS320C64X_REG_EFR:
        SStream_concat0(O, "EFR");
        break;
      case TMS320C64X_REG_IFR:
        SStream_concat0(O, "IFR");
        break;
      default:
        SStream_concat0(O, getRegisterName(reg));
        break;
      }
    } else {
      SStream_concat0(O, getRegisterName(reg));
    }

    if (MI->csh->detail_opt) {
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .type = TMS320C64X_OP_REG;
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .reg = reg;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  } else if (MCOperand_isImm(Op)) {
    int64_t Imm = MCOperand_getImm(Op);

    if (Imm >= 0) {
      if (Imm > HEX_THRESHOLD)
        SStream_concat(O, "0x%" PRIx64, Imm);
      else
        SStream_concat(O, "%" PRIu64, Imm);
    } else {
      if (Imm < -HEX_THRESHOLD)
        SStream_concat(O, "-0x%" PRIx64, -Imm);
      else
        SStream_concat(O, "-%" PRIu64, -Imm);
    }

    if (MI->csh->detail_opt) {
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .type = TMS320C64X_OP_IMM;
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .imm = Imm;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  }
}

static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  unsigned scaled, base, offset, mode, unit;
  cs_tms320c64x *tms320c64x;
  char st, nd;

  scaled = (Val >> 19) & 1;
  base = (Val >> 12) & 0x7f;
  offset = (Val >> 5) & 0x7f;
  mode = (Val >> 1) & 0xf;
  unit = Val & 1;

  if (scaled) {
    st = '[';
    nd = ']';
  } else {
    st = '(';
    nd = ')';
  }

  switch (mode) {
  case 0:
    SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 1:
    SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 4:
    SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 5:
    SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 8:
    SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 9:
    SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 10:
    SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 11:
    SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 12:
    SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 13:
    SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 14:
    SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 15:
    SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  }

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = base;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
    tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
    switch (mode) {
    case 0:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 1:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 4:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 5:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 8:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 9:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 10:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 11:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 12:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 13:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 14:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 15:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    }
    tms320c64x->op_count++;
  }
}

static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  uint16_t offset;
  unsigned basereg;
  cs_tms320c64x *tms320c64x;

  basereg = Val & 0x7f;
  offset = (Val >> 7) & 0x7fff;
  SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.disptype =
      TMS320C64X_MEM_DISP_CONSTANT;
    tms320c64x->operands[tms320c64x->op_count].mem.direction =
      TMS320C64X_MEM_DIR_FW;
    tms320c64x->operands[tms320c64x->op_count].mem.modify =
      TMS320C64X_MEM_MOD_NO;
    tms320c64x->op_count++;
  }
}

static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg = MCOperand_getReg(Op);
  cs_tms320c64x *tms320c64x;

  SStream_concat(O, "%s:%s", getRegisterName(reg + 1),
           getRegisterName(reg));

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_REGPAIR;
    tms320c64x->operands[tms320c64x->op_count].reg = reg;
    tms320c64x->op_count++;
  }
}

static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
{
  unsigned opcode = MCInst_getOpcode(MI);
  MCOperand *op;

  switch (opcode) {
  /* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
  case TMS320C64x_ADD_d2_rir:
  /* ADD.L -i, x, y -> SUB.L x, i, y */
  case TMS320C64x_ADD_l1_irr:
  case TMS320C64x_ADD_l1_ipp:
  /* ADD.S -i, x, y -> SUB.S x, i, y */
  case TMS320C64x_ADD_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
      op = MCInst_getOperand(MI, 2);
      MCOperand_setImm(op, -MCOperand_getImm(op));

      SStream_concat0(O, "SUB\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 2, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* ADD.D 0, x, y -> MV.D x, y */
  case TMS320C64x_ADD_d1_rir:
  /* OR.D x, 0, y -> MV.D x, y */
  case TMS320C64x_OR_d2_rir:
  /* ADD.L 0, x, y -> MV.L x, y */
  case TMS320C64x_ADD_l1_irr:
  case TMS320C64x_ADD_l1_ipp:
  /* OR.L 0, x, y -> MV.L x, y */
  case TMS320C64x_OR_l1_irr:
  /* ADD.S 0, x, y -> MV.S x, y */
  case TMS320C64x_ADD_s1_irr:
  /* OR.S 0, x, y -> MV.S x, y */
  case TMS320C64x_OR_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
      MI->size--;

      SStream_concat0(O, "MV\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* XOR.D -1, x, y -> NOT.D x, y */
  case TMS320C64x_XOR_d2_rir:
  /* XOR.L -1, x, y -> NOT.L x, y */
  case TMS320C64x_XOR_l1_irr:
  /* XOR.S -1, x, y -> NOT.S x, y */
  case TMS320C64x_XOR_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
      MI->size--;

      SStream_concat0(O, "NOT\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* MVK.D 0, x -> ZERO.D x */
  case TMS320C64x_MVK_d1_rr:
  /* MVK.L 0, x -> ZERO.L x */
  case TMS320C64x_MVK_l2_ir:
    if ((MCInst_getNumOperands(MI) == 2) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
      MI->size--;

      SStream_concat0(O, "ZERO\t");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* SUB.L x, x, y -> ZERO.L y */
  case TMS320C64x_SUB_l1_rrp_x1:
  /* SUB.S x, x, y -> ZERO.S y */
  case TMS320C64x_SUB_s1_rrr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
         MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
      MI->size -= 2;

      SStream_concat0(O, "ZERO\t");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* SUB.L 0, x, y -> NEG.L x, y */
  case TMS320C64x_SUB_l1_irr:
  case TMS320C64x_SUB_l1_ipp:
  /* SUB.S 0, x, y -> NEG.S x, y */
  case TMS320C64x_SUB_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
      MI->size--;

      SStream_concat0(O, "NEG\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* PACKLH2.L x, x, y -> SWAP2.L x, y */
  case TMS320C64x_PACKLH2_l1_rrr_x2:
  /* PACKLH2.S x, x, y -> SWAP2.S x, y */
  case TMS320C64x_PACKLH2_s1_rrr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
         MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
      MI->size--;

      SStream_concat0(O, "SWAP2\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* NOP 16 -> IDLE */
  /* NOP 1 -> NOP */
  case TMS320C64x_NOP_n:
    if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
      MI->size--;

      SStream_concat0(O, "IDLE");

      return true;
    }
    if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
      MI->size--;

      SStream_concat0(O, "NOP");

      return true;
    }
    break;
  }

  return false;
}

void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info)
{
  if (!printAliasInstruction(MI, O, Info))
    printInstruction(MI, O, Info);
}

#endif

Coverage Report

Created: 2025-12-14 06:36

Line	Count	Source
1		/* Capstone Disassembly Engine */
2		/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
3
4		#ifdef CAPSTONE_HAS_TMS320C64X
5
6		#include <ctype.h>
7		#include <string.h>
8
9		#include "TMS320C64xInstPrinter.h"
10		#include "../../MCInst.h"
11		#include "../../utils.h"
12		#include "../../SStream.h"
13		#include "../../MCRegisterInfo.h"
14		#include "../../MathExtras.h"
15		#include "TMS320C64xMapping.h"
16
17		#include "capstone/tms320c64x.h"
18
19		static const char *getRegisterName(unsigned RegNo);
20		static void printOperand(MCInst MI, unsigned OpNo, SStream O);
21		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O);
22		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O);
23		static void printRegPair(MCInst MI, unsigned OpNo, SStream O);
24
25		void TMS320C64x_post_printer(csh ud, cs_insn insn, SStream insn_asm,
26		MCInst *mci)
27	41.9k	{
28	41.9k	SStream ss;
29	41.9k	const char op_str_ptr, p2;
30	41.9k	char tmp[8] = { 0 };
31	41.9k	unsigned int unit = 0;
32	41.9k	int i;
33	41.9k	cs_tms320c64x *tms320c64x;
34
35	41.9k	if (mci->csh->detail_opt) {
36	41.9k	tms320c64x = &mci->flat_insn->detail->tms320c64x;
37
38	41.9k	for (i = 0; i < insn->detail->groups_count; i++) {
39	41.9k	switch (insn->detail->groups[i]) {
40	11.1k	case TMS320C64X_GRP_FUNIT_D:
41	11.1k	unit = TMS320C64X_FUNIT_D;
42	11.1k	break;
43	9.38k	case TMS320C64X_GRP_FUNIT_L:
44	9.38k	unit = TMS320C64X_FUNIT_L;
45	9.38k	break;
46	2.22k	case TMS320C64X_GRP_FUNIT_M:
47	2.22k	unit = TMS320C64X_FUNIT_M;
48	2.22k	break;
49	18.2k	case TMS320C64X_GRP_FUNIT_S:
50	18.2k	unit = TMS320C64X_FUNIT_S;
51	18.2k	break;
52	921	case TMS320C64X_GRP_FUNIT_NO:
53	921	unit = TMS320C64X_FUNIT_NO;
54	921	break;
55	41.9k	}
56	41.9k	if (unit != 0)
57	41.9k	break;
58	41.9k	}
59	41.9k	tms320c64x->funit.unit = unit;
60
61	41.9k	SStream_Init(&ss);
62	41.9k	if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
63	27.0k	SStream_concat(
64	27.0k	&ss, "[%c%s]\|",
65	27.0k	(tms320c64x->condition.zero == 1) ? '!' : '\|',
66	27.0k	cs_reg_name(ud, tms320c64x->condition.reg));
67
68		// Sorry for all the fixes below. I don't have time to add more helper SStream functions.
69		// Before that they messed around with the private buffer of the stream.
70		// So it is better now. But still not efficient.
71	41.9k	op_str_ptr = strchr(SStream_rbuf(insn_asm), '\t');
72
73	41.9k	if ((op_str_ptr != NULL) &&
74	41.3k	(((p2 = strchr(op_str_ptr, '[')) != NULL) \|\|
75	34.0k	((p2 = strchr(op_str_ptr, '(')) != NULL))) {
76	32.6k	while ((p2 > op_str_ptr) &&
77	32.6k	((p2 != 'a') && (p2 != 'b')))
78	24.7k	p2--;
79	7.87k	if (p2 == op_str_ptr) {
80	0	SStream_Flush(insn_asm, NULL);
81	0	SStream_concat0(insn_asm, "Invalid!");
82	0	return;
83	0	}
84	7.87k	if (*p2 == 'a')
85	4.11k	strncpy(tmp, "1T", sizeof(tmp));
86	3.76k	else
87	3.76k	strncpy(tmp, "2T", sizeof(tmp));
88	34.1k	} else {
89	34.1k	tmp[0] = '\0';
90	34.1k	}
91	41.9k	SStream mnem_post = { 0 };
92	41.9k	SStream_Init(&mnem_post);
93	41.9k	switch (tms320c64x->funit.unit) {
94	11.1k	case TMS320C64X_FUNIT_D:
95	11.1k	SStream_concat(&mnem_post, ".D%s%u", tmp,
96	11.1k	tms320c64x->funit.side);
97	11.1k	break;
98	9.38k	case TMS320C64X_FUNIT_L:
99	9.38k	SStream_concat(&mnem_post, ".L%s%u", tmp,
100	9.38k	tms320c64x->funit.side);
101	9.38k	break;
102	2.22k	case TMS320C64X_FUNIT_M:
103	2.22k	SStream_concat(&mnem_post, ".M%s%u", tmp,
104	2.22k	tms320c64x->funit.side);
105	2.22k	break;
106	18.2k	case TMS320C64X_FUNIT_S:
107	18.2k	SStream_concat(&mnem_post, ".S%s%u", tmp,
108	18.2k	tms320c64x->funit.side);
109	18.2k	break;
110	41.9k	}
111	41.9k	if (tms320c64x->funit.crosspath > 0)
112	12.6k	SStream_concat0(&mnem_post, "X");
113
114	41.9k	if (op_str_ptr != NULL) {
115		// There is an op_str
116	41.3k	SStream_concat1(&mnem_post, '\t');
117	41.3k	SStream_replc_str(insn_asm, '\t',
118	41.3k	SStream_rbuf(&mnem_post));
119	41.3k	}
120
121	41.9k	if (tms320c64x->parallel != 0)
122	21.7k	SStream_concat0(insn_asm, "\t\|\|");
123	41.9k	SStream_concat0(&ss, SStream_rbuf(insn_asm));
124	41.9k	SStream_Flush(insn_asm, NULL);
125	41.9k	SStream_concat0(insn_asm, SStream_rbuf(&ss));
126	41.9k	}
127	41.9k	}
128
129		#define PRINT_ALIAS_INSTR
130		#include "TMS320C64xGenAsmWriter.inc"
131
132		#define GET_INSTRINFO_ENUM
133		#include "TMS320C64xGenInstrInfo.inc"
134
135		static void printOperand(MCInst MI, unsigned OpNo, SStream O)
136	74.8k	{
137	74.8k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
138	74.8k	unsigned reg;
139
140	74.8k	if (MCOperand_isReg(Op)) {
141	54.8k	reg = MCOperand_getReg(Op);
142	54.8k	if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) &&
143	5.24k	(OpNo == 1)) {
144	2.62k	switch (reg) {
145	1.60k	case TMS320C64X_REG_EFR:
146	1.60k	SStream_concat0(O, "EFR");
147	1.60k	break;
148	665	case TMS320C64X_REG_IFR:
149	665	SStream_concat0(O, "IFR");
150	665	break;
151	349	default:
152	349	SStream_concat0(O, getRegisterName(reg));
153	349	break;
154	2.62k	}
155	52.2k	} else {
156	52.2k	SStream_concat0(O, getRegisterName(reg));
157	52.2k	}
158
159	54.8k	if (MI->csh->detail_opt) {
160	54.8k	MI->flat_insn->detail->tms320c64x
161	54.8k	.operands[MI->flat_insn->detail->tms320c64x
162	54.8k	.op_count]
163	54.8k	.type = TMS320C64X_OP_REG;
164	54.8k	MI->flat_insn->detail->tms320c64x
165	54.8k	.operands[MI->flat_insn->detail->tms320c64x
166	54.8k	.op_count]
167	54.8k	.reg = reg;
168	54.8k	MI->flat_insn->detail->tms320c64x.op_count++;
169	54.8k	}
170	54.8k	} else if (MCOperand_isImm(Op)) {
171	20.0k	int64_t Imm = MCOperand_getImm(Op);
172
173	20.0k	if (Imm >= 0) {
174	16.2k	if (Imm > HEX_THRESHOLD)
175	10.4k	SStream_concat(O, "0x%" PRIx64, Imm);
176	5.78k	else
177	5.78k	SStream_concat(O, "%" PRIu64, Imm);
178	16.2k	} else {
179	3.79k	if (Imm < -HEX_THRESHOLD)
180	2.57k	SStream_concat(O, "-0x%" PRIx64, -Imm);
181	1.21k	else
182	1.21k	SStream_concat(O, "-%" PRIu64, -Imm);
183	3.79k	}
184
185	20.0k	if (MI->csh->detail_opt) {
186	20.0k	MI->flat_insn->detail->tms320c64x
187	20.0k	.operands[MI->flat_insn->detail->tms320c64x
188	20.0k	.op_count]
189	20.0k	.type = TMS320C64X_OP_IMM;
190	20.0k	MI->flat_insn->detail->tms320c64x
191	20.0k	.operands[MI->flat_insn->detail->tms320c64x
192	20.0k	.op_count]
193	20.0k	.imm = Imm;
194	20.0k	MI->flat_insn->detail->tms320c64x.op_count++;
195	20.0k	}
196	20.0k	}
197	74.8k	}
198
199		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O)
200	4.11k	{
201	4.11k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
202	4.11k	int64_t Val = MCOperand_getImm(Op);
203	4.11k	unsigned scaled, base, offset, mode, unit;
204	4.11k	cs_tms320c64x *tms320c64x;
205	4.11k	char st, nd;
206
207	4.11k	scaled = (Val >> 19) & 1;
208	4.11k	base = (Val >> 12) & 0x7f;
209	4.11k	offset = (Val >> 5) & 0x7f;
210	4.11k	mode = (Val >> 1) & 0xf;
211	4.11k	unit = Val & 1;
212
213	4.11k	if (scaled) {
214	3.49k	st = '[';
215	3.49k	nd = ']';
216	3.49k	} else {
217	621	st = '(';
218	621	nd = ')';
219	621	}
220
221	4.11k	switch (mode) {
222	396	case 0:
223	396	SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st,
224	396	offset, nd);
225	396	break;
226	469	case 1:
227	469	SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st,
228	469	offset, nd);
229	469	break;
230	223	case 4:
231	223	SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st,
232	223	getRegisterName(offset), nd);
233	223	break;
234	208	case 5:
235	208	SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st,
236	208	getRegisterName(offset), nd);
237	208	break;
238	323	case 8:
239	323	SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st,
240	323	offset, nd);
241	323	break;
242	429	case 9:
243	429	SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st,
244	429	offset, nd);
245	429	break;
246	385	case 10:
247	385	SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st,
248	385	offset, nd);
249	385	break;
250	483	case 11:
251	483	SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st,
252	483	offset, nd);
253	483	break;
254	250	case 12:
255	250	SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st,
256	250	getRegisterName(offset), nd);
257	250	break;
258	276	case 13:
259	276	SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st,
260	276	getRegisterName(offset), nd);
261	276	break;
262	269	case 14:
263	269	SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st,
264	269	getRegisterName(offset), nd);
265	269	break;
266	400	case 15:
267	400	SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st,
268	400	getRegisterName(offset), nd);
269	400	break;
270	4.11k	}
271
272	4.11k	if (MI->csh->detail_opt) {
273	4.11k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
274
275	4.11k	tms320c64x->operands[tms320c64x->op_count].type =
276	4.11k	TMS320C64X_OP_MEM;
277	4.11k	tms320c64x->operands[tms320c64x->op_count].mem.base = base;
278	4.11k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
279	4.11k	tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
280	4.11k	tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
281	4.11k	switch (mode) {
282	396	case 0:
283	396	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
284	396	TMS320C64X_MEM_DISP_CONSTANT;
285	396	tms320c64x->operands[tms320c64x->op_count]
286	396	.mem.direction = TMS320C64X_MEM_DIR_BW;
287	396	tms320c64x->operands[tms320c64x->op_count].mem.modify =
288	396	TMS320C64X_MEM_MOD_NO;
289	396	break;
290	469	case 1:
291	469	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
292	469	TMS320C64X_MEM_DISP_CONSTANT;
293	469	tms320c64x->operands[tms320c64x->op_count]
294	469	.mem.direction = TMS320C64X_MEM_DIR_FW;
295	469	tms320c64x->operands[tms320c64x->op_count].mem.modify =
296	469	TMS320C64X_MEM_MOD_NO;
297	469	break;
298	223	case 4:
299	223	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
300	223	TMS320C64X_MEM_DISP_REGISTER;
301	223	tms320c64x->operands[tms320c64x->op_count]
302	223	.mem.direction = TMS320C64X_MEM_DIR_BW;
303	223	tms320c64x->operands[tms320c64x->op_count].mem.modify =
304	223	TMS320C64X_MEM_MOD_NO;
305	223	break;
306	208	case 5:
307	208	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
308	208	TMS320C64X_MEM_DISP_REGISTER;
309	208	tms320c64x->operands[tms320c64x->op_count]
310	208	.mem.direction = TMS320C64X_MEM_DIR_FW;
311	208	tms320c64x->operands[tms320c64x->op_count].mem.modify =
312	208	TMS320C64X_MEM_MOD_NO;
313	208	break;
314	323	case 8:
315	323	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
316	323	TMS320C64X_MEM_DISP_CONSTANT;
317	323	tms320c64x->operands[tms320c64x->op_count]
318	323	.mem.direction = TMS320C64X_MEM_DIR_BW;
319	323	tms320c64x->operands[tms320c64x->op_count].mem.modify =
320	323	TMS320C64X_MEM_MOD_PRE;
321	323	break;
322	429	case 9:
323	429	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
324	429	TMS320C64X_MEM_DISP_CONSTANT;
325	429	tms320c64x->operands[tms320c64x->op_count]
326	429	.mem.direction = TMS320C64X_MEM_DIR_FW;
327	429	tms320c64x->operands[tms320c64x->op_count].mem.modify =
328	429	TMS320C64X_MEM_MOD_PRE;
329	429	break;
330	385	case 10:
331	385	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
332	385	TMS320C64X_MEM_DISP_CONSTANT;
333	385	tms320c64x->operands[tms320c64x->op_count]
334	385	.mem.direction = TMS320C64X_MEM_DIR_BW;
335	385	tms320c64x->operands[tms320c64x->op_count].mem.modify =
336	385	TMS320C64X_MEM_MOD_POST;
337	385	break;
338	483	case 11:
339	483	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
340	483	TMS320C64X_MEM_DISP_CONSTANT;
341	483	tms320c64x->operands[tms320c64x->op_count]
342	483	.mem.direction = TMS320C64X_MEM_DIR_FW;
343	483	tms320c64x->operands[tms320c64x->op_count].mem.modify =
344	483	TMS320C64X_MEM_MOD_POST;
345	483	break;
346	250	case 12:
347	250	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
348	250	TMS320C64X_MEM_DISP_REGISTER;
349	250	tms320c64x->operands[tms320c64x->op_count]
350	250	.mem.direction = TMS320C64X_MEM_DIR_BW;
351	250	tms320c64x->operands[tms320c64x->op_count].mem.modify =
352	250	TMS320C64X_MEM_MOD_PRE;
353	250	break;
354	276	case 13:
355	276	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
356	276	TMS320C64X_MEM_DISP_REGISTER;
357	276	tms320c64x->operands[tms320c64x->op_count]
358	276	.mem.direction = TMS320C64X_MEM_DIR_FW;
359	276	tms320c64x->operands[tms320c64x->op_count].mem.modify =
360	276	TMS320C64X_MEM_MOD_PRE;
361	276	break;
362	269	case 14:
363	269	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
364	269	TMS320C64X_MEM_DISP_REGISTER;
365	269	tms320c64x->operands[tms320c64x->op_count]
366	269	.mem.direction = TMS320C64X_MEM_DIR_BW;
367	269	tms320c64x->operands[tms320c64x->op_count].mem.modify =
368	269	TMS320C64X_MEM_MOD_POST;
369	269	break;
370	400	case 15:
371	400	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
372	400	TMS320C64X_MEM_DISP_REGISTER;
373	400	tms320c64x->operands[tms320c64x->op_count]
374	400	.mem.direction = TMS320C64X_MEM_DIR_FW;
375	400	tms320c64x->operands[tms320c64x->op_count].mem.modify =
376	400	TMS320C64X_MEM_MOD_POST;
377	400	break;
378	4.11k	}
379	4.11k	tms320c64x->op_count++;
380	4.11k	}
381	4.11k	}
382
383		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O)
384	3.76k	{
385	3.76k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
386	3.76k	int64_t Val = MCOperand_getImm(Op);
387	3.76k	uint16_t offset;
388	3.76k	unsigned basereg;
389	3.76k	cs_tms320c64x *tms320c64x;
390
391	3.76k	basereg = Val & 0x7f;
392	3.76k	offset = (Val >> 7) & 0x7fff;
393	3.76k	SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);
394
395	3.76k	if (MI->csh->detail_opt) {
396	3.76k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
397
398	3.76k	tms320c64x->operands[tms320c64x->op_count].type =
399	3.76k	TMS320C64X_OP_MEM;
400	3.76k	tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
401	3.76k	tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
402	3.76k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
403	3.76k	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
404	3.76k	TMS320C64X_MEM_DISP_CONSTANT;
405	3.76k	tms320c64x->operands[tms320c64x->op_count].mem.direction =
406	3.76k	TMS320C64X_MEM_DIR_FW;
407	3.76k	tms320c64x->operands[tms320c64x->op_count].mem.modify =
408	3.76k	TMS320C64X_MEM_MOD_NO;
409	3.76k	tms320c64x->op_count++;
410	3.76k	}
411	3.76k	}
412
413		static void printRegPair(MCInst MI, unsigned OpNo, SStream O)
414	12.4k	{
415	12.4k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
416	12.4k	unsigned reg = MCOperand_getReg(Op);
417	12.4k	cs_tms320c64x *tms320c64x;
418
419	12.4k	SStream_concat(O, "%s:%s", getRegisterName(reg + 1),
420	12.4k	getRegisterName(reg));
421
422	12.4k	if (MI->csh->detail_opt) {
423	12.4k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
424
425	12.4k	tms320c64x->operands[tms320c64x->op_count].type =
426	12.4k	TMS320C64X_OP_REGPAIR;
427	12.4k	tms320c64x->operands[tms320c64x->op_count].reg = reg;
428	12.4k	tms320c64x->op_count++;
429	12.4k	}
430	12.4k	}
431
432		static bool printAliasInstruction(MCInst MI, SStream O, MCRegisterInfo *MRI)
433	41.9k	{
434	41.9k	unsigned opcode = MCInst_getOpcode(MI);
435	41.9k	MCOperand *op;
436
437	41.9k	switch (opcode) {
438		/* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
439	333	case TMS320C64x_ADD_d2_rir:
440		/* ADD.L -i, x, y -> SUB.L x, i, y */
441	554	case TMS320C64x_ADD_l1_irr:
442	767	case TMS320C64x_ADD_l1_ipp:
443		/* ADD.S -i, x, y -> SUB.S x, i, y */
444	1.05k	case TMS320C64x_ADD_s1_irr:
445	1.05k	if ((MCInst_getNumOperands(MI) == 3) &&
446	1.05k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
447	1.05k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
448	1.05k	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
449	1.05k	(MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
450	436	MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
451	436	op = MCInst_getOperand(MI, 2);
452	436	MCOperand_setImm(op, -MCOperand_getImm(op));
453
454	436	SStream_concat0(O, "SUB\t");
455	436	printOperand(MI, 1, O);
456	436	SStream_concat0(O, ", ");
457	436	printOperand(MI, 2, O);
458	436	SStream_concat0(O, ", ");
459	436	printOperand(MI, 0, O);
460
461	436	return true;
462	436	}
463	615	break;
464	41.9k	}
465	41.5k	switch (opcode) {
466		/* ADD.D 0, x, y -> MV.D x, y */
467	208	case TMS320C64x_ADD_d1_rir:
468		/* OR.D x, 0, y -> MV.D x, y */
469	287	case TMS320C64x_OR_d2_rir:
470		/* ADD.L 0, x, y -> MV.L x, y */
471	486	case TMS320C64x_ADD_l1_irr:
472	558	case TMS320C64x_ADD_l1_ipp:
473		/* OR.L 0, x, y -> MV.L x, y */
474	755	case TMS320C64x_OR_l1_irr:
475		/* ADD.S 0, x, y -> MV.S x, y */
476	1.02k	case TMS320C64x_ADD_s1_irr:
477		/* OR.S 0, x, y -> MV.S x, y */
478	1.41k	case TMS320C64x_OR_s1_irr:
479	1.41k	if ((MCInst_getNumOperands(MI) == 3) &&
480	1.41k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
481	1.41k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
482	1.41k	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
483	1.41k	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
484	208	MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
485	208	MI->size--;
486
487	208	SStream_concat0(O, "MV\t");
488	208	printOperand(MI, 1, O);
489	208	SStream_concat0(O, ", ");
490	208	printOperand(MI, 0, O);
491
492	208	return true;
493	208	}
494	1.20k	break;
495	41.5k	}
496	41.3k	switch (opcode) {
497		/* XOR.D -1, x, y -> NOT.D x, y */
498	234	case TMS320C64x_XOR_d2_rir:
499		/* XOR.L -1, x, y -> NOT.L x, y */
500	309	case TMS320C64x_XOR_l1_irr:
501		/* XOR.S -1, x, y -> NOT.S x, y */
502	504	case TMS320C64x_XOR_s1_irr:
503	504	if ((MCInst_getNumOperands(MI) == 3) &&
504	504	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
505	504	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
506	504	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
507	504	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
508	74	MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
509	74	MI->size--;
510
511	74	SStream_concat0(O, "NOT\t");
512	74	printOperand(MI, 1, O);
513	74	SStream_concat0(O, ", ");
514	74	printOperand(MI, 0, O);
515
516	74	return true;
517	74	}
518	430	break;
519	41.3k	}
520	41.2k	switch (opcode) {
521		/* MVK.D 0, x -> ZERO.D x */
522	783	case TMS320C64x_MVK_d1_rr:
523		/* MVK.L 0, x -> ZERO.L x */
524	1.38k	case TMS320C64x_MVK_l2_ir:
525	1.38k	if ((MCInst_getNumOperands(MI) == 2) &&
526	1.38k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
527	1.38k	MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
528	1.38k	(MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
529	106	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
530	106	MI->size--;
531
532	106	SStream_concat0(O, "ZERO\t");
533	106	printOperand(MI, 0, O);
534
535	106	return true;
536	106	}
537	1.28k	break;
538	41.2k	}
539	41.1k	switch (opcode) {
540		/* SUB.L x, x, y -> ZERO.L y */
541	100	case TMS320C64x_SUB_l1_rrp_x1:
542		/* SUB.S x, x, y -> ZERO.S y */
543	208	case TMS320C64x_SUB_s1_rrr:
544	208	if ((MCInst_getNumOperands(MI) == 3) &&
545	208	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
546	208	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
547	208	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
548	208	(MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
549	208	MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
550	95	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
551	95	MI->size -= 2;
552
553	95	SStream_concat0(O, "ZERO\t");
554	95	printOperand(MI, 0, O);
555
556	95	return true;
557	95	}
558	113	break;
559	41.1k	}
560	41.0k	switch (opcode) {
561		/* SUB.L 0, x, y -> NEG.L x, y */
562	341	case TMS320C64x_SUB_l1_irr:
563	603	case TMS320C64x_SUB_l1_ipp:
564		/* SUB.S 0, x, y -> NEG.S x, y */
565	804	case TMS320C64x_SUB_s1_irr:
566	804	if ((MCInst_getNumOperands(MI) == 3) &&
567	804	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
568	804	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
569	804	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
570	804	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
571	220	MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
572	220	MI->size--;
573
574	220	SStream_concat0(O, "NEG\t");
575	220	printOperand(MI, 1, O);
576	220	SStream_concat0(O, ", ");
577	220	printOperand(MI, 0, O);
578
579	220	return true;
580	220	}
581	584	break;
582	41.0k	}
583	40.8k	switch (opcode) {
584		/* PACKLH2.L x, x, y -> SWAP2.L x, y */
585	374	case TMS320C64x_PACKLH2_l1_rrr_x2:
586		/* PACKLH2.S x, x, y -> SWAP2.S x, y */
587	643	case TMS320C64x_PACKLH2_s1_rrr:
588	643	if ((MCInst_getNumOperands(MI) == 3) &&
589	643	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
590	643	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
591	643	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
592	643	(MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
593	643	MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
594	74	MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
595	74	MI->size--;
596
597	74	SStream_concat0(O, "SWAP2\t");
598	74	printOperand(MI, 1, O);
599	74	SStream_concat0(O, ", ");
600	74	printOperand(MI, 0, O);
601
602	74	return true;
603	74	}
604	569	break;
605	40.8k	}
606	40.7k	switch (opcode) {
607		/* NOP 16 -> IDLE */
608		/* NOP 1 -> NOP */
609	921	case TMS320C64x_NOP_n:
610	921	if ((MCInst_getNumOperands(MI) == 1) &&
611	921	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
612	921	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
613	81	MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
614	81	MI->size--;
615
616	81	SStream_concat0(O, "IDLE");
617
618	81	return true;
619	81	}
620	840	if ((MCInst_getNumOperands(MI) == 1) &&
621	840	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
622	840	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
623	579	MI->size--;
624
625	579	SStream_concat0(O, "NOP");
626
627	579	return true;
628	579	}
629	261	break;
630	40.7k	}
631
632	40.1k	return false;
633	40.7k	}
634
635		void TMS320C64x_printInst(MCInst MI, SStream O, void *Info)
636	41.9k	{
637	41.9k	if (!printAliasInstruction(MI, O, Info))
638	40.1k	printInstruction(MI, O, Info);
639	41.9k	}
640
641		#endif