Coverage Report

Created: 2026-01-17 06:58

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/capstonenext/arch/ARM/ARMGenAsmWriter.inc
Line
Count
Source
1
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
2
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
3
/*    Rot127 <unisono@quyllur.org> 2022-2024 */
4
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
5
6
/* LLVM-commit: <commit> */
7
/* LLVM-tag: <tag> */
8
9
/* Do not edit. */
10
11
/* Capstone's LLVM TableGen Backends: */
12
/* https://github.com/capstone-engine/llvm-capstone */
13
14
#include <capstone/platform.h>
15
#include "../../cs_priv.h"
16
17
/// getMnemonic - This method is automatically generated by tablegen
18
/// from the instruction set description.
19
1.14M
static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
20
1.14M
#ifndef CAPSTONE_DIET
21
1.14M
  static const char AsmStrs[] = {
22
1.14M
  /* 0 */ "vcx1\t\0"
23
1.14M
  /* 6 */ "vld20.32\t\0"
24
1.14M
  /* 16 */ "vst20.32\t\0"
25
1.14M
  /* 26 */ "vld40.32\t\0"
26
1.14M
  /* 36 */ "vst40.32\t\0"
27
1.14M
  /* 46 */ "sha1su0.32\t\0"
28
1.14M
  /* 58 */ "sha256su0.32\t\0"
29
1.14M
  /* 72 */ "vld21.32\t\0"
30
1.14M
  /* 82 */ "vst21.32\t\0"
31
1.14M
  /* 92 */ "vld41.32\t\0"
32
1.14M
  /* 102 */ "vst41.32\t\0"
33
1.14M
  /* 112 */ "sha1su1.32\t\0"
34
1.14M
  /* 124 */ "sha256su1.32\t\0"
35
1.14M
  /* 138 */ "vld42.32\t\0"
36
1.14M
  /* 148 */ "vst42.32\t\0"
37
1.14M
  /* 158 */ "sha256h2.32\t\0"
38
1.14M
  /* 171 */ "vld43.32\t\0"
39
1.14M
  /* 181 */ "vst43.32\t\0"
40
1.14M
  /* 191 */ "sha1c.32\t\0"
41
1.14M
  /* 201 */ "sha1h.32\t\0"
42
1.14M
  /* 211 */ "sha256h.32\t\0"
43
1.14M
  /* 223 */ "sha1m.32\t\0"
44
1.14M
  /* 233 */ "sha1p.32\t\0"
45
1.14M
  /* 243 */ "dlstp.32\t\0"
46
1.14M
  /* 253 */ "wlstp.32\t\0"
47
1.14M
  /* 263 */ "vcvta.s32.f32\t\0"
48
1.14M
  /* 278 */ "vcvtm.s32.f32\t\0"
49
1.14M
  /* 293 */ "vcvtn.s32.f32\t\0"
50
1.14M
  /* 308 */ "vcvtp.s32.f32\t\0"
51
1.14M
  /* 323 */ "vcvta.u32.f32\t\0"
52
1.14M
  /* 338 */ "vcvtm.u32.f32\t\0"
53
1.14M
  /* 353 */ "vcvtn.u32.f32\t\0"
54
1.14M
  /* 368 */ "vcvtp.u32.f32\t\0"
55
1.14M
  /* 383 */ "vcmla.f32\t\0"
56
1.14M
  /* 394 */ "vrinta.f32\t\0"
57
1.14M
  /* 406 */ "vcadd.f32\t\0"
58
1.14M
  /* 417 */ "vselge.f32\t\0"
59
1.14M
  /* 429 */ "vminnm.f32\t\0"
60
1.14M
  /* 441 */ "vmaxnm.f32\t\0"
61
1.14M
  /* 453 */ "vrintm.f32\t\0"
62
1.14M
  /* 465 */ "vrintn.f32\t\0"
63
1.14M
  /* 477 */ "vrintp.f32\t\0"
64
1.14M
  /* 489 */ "vseleq.f32\t\0"
65
1.14M
  /* 501 */ "vselvs.f32\t\0"
66
1.14M
  /* 513 */ "vselgt.f32\t\0"
67
1.14M
  /* 525 */ "vrintx.f32\t\0"
68
1.14M
  /* 537 */ "vrintz.f32\t\0"
69
1.14M
  /* 549 */ "ldc2\t\0"
70
1.14M
  /* 555 */ "mrc2\t\0"
71
1.14M
  /* 561 */ "mrrc2\t\0"
72
1.14M
  /* 568 */ "stc2\t\0"
73
1.14M
  /* 574 */ "cdp2\t\0"
74
1.14M
  /* 580 */ "mcr2\t\0"
75
1.14M
  /* 586 */ "mcrr2\t\0"
76
1.14M
  /* 593 */ "vcx2\t\0"
77
1.14M
  /* 599 */ "vcx3\t\0"
78
1.14M
  /* 605 */ "dlstp.64\t\0"
79
1.14M
  /* 615 */ "wlstp.64\t\0"
80
1.14M
  /* 625 */ "vcvta.s32.f64\t\0"
81
1.14M
  /* 640 */ "vcvtm.s32.f64\t\0"
82
1.14M
  /* 655 */ "vcvtn.s32.f64\t\0"
83
1.14M
  /* 670 */ "vcvtp.s32.f64\t\0"
84
1.14M
  /* 685 */ "vcvta.u32.f64\t\0"
85
1.14M
  /* 700 */ "vcvtm.u32.f64\t\0"
86
1.14M
  /* 715 */ "vcvtn.u32.f64\t\0"
87
1.14M
  /* 730 */ "vcvtp.u32.f64\t\0"
88
1.14M
  /* 745 */ "vrinta.f64\t\0"
89
1.14M
  /* 757 */ "vselge.f64\t\0"
90
1.14M
  /* 769 */ "vminnm.f64\t\0"
91
1.14M
  /* 781 */ "vmaxnm.f64\t\0"
92
1.14M
  /* 793 */ "vrintm.f64\t\0"
93
1.14M
  /* 805 */ "vrintn.f64\t\0"
94
1.14M
  /* 817 */ "vrintp.f64\t\0"
95
1.14M
  /* 829 */ "vseleq.f64\t\0"
96
1.14M
  /* 841 */ "vselvs.f64\t\0"
97
1.14M
  /* 853 */ "vselgt.f64\t\0"
98
1.14M
  /* 865 */ "vmull.p64\t\0"
99
1.14M
  /* 876 */ "vld20.16\t\0"
100
1.14M
  /* 886 */ "vst20.16\t\0"
101
1.14M
  /* 896 */ "vld40.16\t\0"
102
1.14M
  /* 906 */ "vst40.16\t\0"
103
1.14M
  /* 916 */ "vld21.16\t\0"
104
1.14M
  /* 926 */ "vst21.16\t\0"
105
1.14M
  /* 936 */ "vld41.16\t\0"
106
1.14M
  /* 946 */ "vst41.16\t\0"
107
1.14M
  /* 956 */ "vld42.16\t\0"
108
1.14M
  /* 966 */ "vst42.16\t\0"
109
1.14M
  /* 976 */ "vld43.16\t\0"
110
1.14M
  /* 986 */ "vst43.16\t\0"
111
1.14M
  /* 996 */ "dlstp.16\t\0"
112
1.14M
  /* 1006 */ "wlstp.16\t\0"
113
1.14M
  /* 1016 */ "vcvta.s32.f16\t\0"
114
1.14M
  /* 1031 */ "vcvtm.s32.f16\t\0"
115
1.14M
  /* 1046 */ "vcvtn.s32.f16\t\0"
116
1.14M
  /* 1061 */ "vcvtp.s32.f16\t\0"
117
1.14M
  /* 1076 */ "vcvta.u32.f16\t\0"
118
1.14M
  /* 1091 */ "vcvtm.u32.f16\t\0"
119
1.14M
  /* 1106 */ "vcvtn.u32.f16\t\0"
120
1.14M
  /* 1121 */ "vcvtp.u32.f16\t\0"
121
1.14M
  /* 1136 */ "vcvta.s16.f16\t\0"
122
1.14M
  /* 1151 */ "vcvtm.s16.f16\t\0"
123
1.14M
  /* 1166 */ "vcvtn.s16.f16\t\0"
124
1.14M
  /* 1181 */ "vcvtp.s16.f16\t\0"
125
1.14M
  /* 1196 */ "vcvta.u16.f16\t\0"
126
1.14M
  /* 1211 */ "vcvtm.u16.f16\t\0"
127
1.14M
  /* 1226 */ "vcvtn.u16.f16\t\0"
128
1.14M
  /* 1241 */ "vcvtp.u16.f16\t\0"
129
1.14M
  /* 1256 */ "vcmla.f16\t\0"
130
1.14M
  /* 1267 */ "vrinta.f16\t\0"
131
1.14M
  /* 1279 */ "vcadd.f16\t\0"
132
1.14M
  /* 1290 */ "vselge.f16\t\0"
133
1.14M
  /* 1302 */ "vfmal.f16\t\0"
134
1.14M
  /* 1313 */ "vfmsl.f16\t\0"
135
1.14M
  /* 1324 */ "vminnm.f16\t\0"
136
1.14M
  /* 1336 */ "vmaxnm.f16\t\0"
137
1.14M
  /* 1348 */ "vrintm.f16\t\0"
138
1.14M
  /* 1360 */ "vrintn.f16\t\0"
139
1.14M
  /* 1372 */ "vrintp.f16\t\0"
140
1.14M
  /* 1384 */ "vseleq.f16\t\0"
141
1.14M
  /* 1396 */ "vins.f16\t\0"
142
1.14M
  /* 1406 */ "vselvs.f16\t\0"
143
1.14M
  /* 1418 */ "vselgt.f16\t\0"
144
1.14M
  /* 1430 */ "vrintx.f16\t\0"
145
1.14M
  /* 1442 */ "vmovx.f16\t\0"
146
1.14M
  /* 1453 */ "vrintz.f16\t\0"
147
1.14M
  /* 1465 */ "vmmla.bf16\t\0"
148
1.14M
  /* 1477 */ "vfmab.bf16\t\0"
149
1.14M
  /* 1489 */ "vfmat.bf16\t\0"
150
1.14M
  /* 1501 */ "vdot.bf16\t\0"
151
1.14M
  /* 1512 */ "vld20.8\t\0"
152
1.14M
  /* 1521 */ "vst20.8\t\0"
153
1.14M
  /* 1530 */ "vld40.8\t\0"
154
1.14M
  /* 1539 */ "vst40.8\t\0"
155
1.14M
  /* 1548 */ "vld21.8\t\0"
156
1.14M
  /* 1557 */ "vst21.8\t\0"
157
1.14M
  /* 1566 */ "vld41.8\t\0"
158
1.14M
  /* 1575 */ "vst41.8\t\0"
159
1.14M
  /* 1584 */ "vld42.8\t\0"
160
1.14M
  /* 1593 */ "vst42.8\t\0"
161
1.14M
  /* 1602 */ "vld43.8\t\0"
162
1.14M
  /* 1611 */ "vst43.8\t\0"
163
1.14M
  /* 1620 */ "aesimc.8\t\0"
164
1.14M
  /* 1630 */ "aesmc.8\t\0"
165
1.14M
  /* 1639 */ "aesd.8\t\0"
166
1.14M
  /* 1647 */ "aese.8\t\0"
167
1.14M
  /* 1655 */ "dlstp.8\t\0"
168
1.14M
  /* 1664 */ "wlstp.8\t\0"
169
1.14M
  /* 1673 */ "vusmmla.s8\t\0"
170
1.14M
  /* 1685 */ "vsmmla.s8\t\0"
171
1.14M
  /* 1696 */ "vusdot.s8\t\0"
172
1.14M
  /* 1707 */ "vsdot.s8\t\0"
173
1.14M
  /* 1717 */ "vummla.u8\t\0"
174
1.14M
  /* 1728 */ "vsudot.u8\t\0"
175
1.14M
  /* 1739 */ "vudot.u8\t\0"
176
1.14M
  /* 1749 */ "vcx1a\t\0"
177
1.14M
  /* 1756 */ "vcx2a\t\0"
178
1.14M
  /* 1763 */ "vcx3a\t\0"
179
1.14M
  /* 1770 */ "rfeda\t\0"
180
1.14M
  /* 1777 */ "rfeia\t\0"
181
1.14M
  /* 1784 */ "crc32b\t\0"
182
1.14M
  /* 1792 */ "crc32cb\t\0"
183
1.14M
  /* 1801 */ "rfedb\t\0"
184
1.14M
  /* 1808 */ "rfeib\t\0"
185
1.14M
  /* 1815 */ "dmb\t\0"
186
1.14M
  /* 1820 */ "dsb\t\0"
187
1.14M
  /* 1825 */ "isb\t\0"
188
1.14M
  /* 1830 */ "tsb\t\0"
189
1.14M
  /* 1835 */ "csinc\t\0"
190
1.14M
  /* 1842 */ "hvc\t\0"
191
1.14M
  /* 1847 */ "cx1d\t\0"
192
1.14M
  /* 1853 */ "cx2d\t\0"
193
1.14M
  /* 1859 */ "cx3d\t\0"
194
1.14M
  /* 1865 */ "pld\t\0"
195
1.14M
  /* 1870 */ "setend\t\0"
196
1.14M
  /* 1878 */ "le\t\0"
197
1.14M
  /* 1882 */ "udf\t\0"
198
1.14M
  /* 1887 */ "csneg\t\0"
199
1.14M
  /* 1894 */ "crc32h\t\0"
200
1.14M
  /* 1902 */ "crc32ch\t\0"
201
1.14M
  /* 1911 */ "pli\t\0"
202
1.14M
  /* 1916 */ "bti\t\0"
203
1.14M
  /* 1921 */ "ldc2l\t\0"
204
1.14M
  /* 1928 */ "stc2l\t\0"
205
1.14M
  /* 1935 */ "bl\t\0"
206
1.14M
  /* 1939 */ "bfcsel\t\0"
207
1.14M
  /* 1947 */ "setpan\t\0"
208
1.14M
  /* 1955 */ "letp\t\0"
209
1.14M
  /* 1961 */ "dls\t\0"
210
1.14M
  /* 1966 */ "wls\t\0"
211
1.14M
  /* 1971 */ "cps\t\0"
212
1.14M
  /* 1976 */ "movs\t\0"
213
1.14M
  /* 1982 */ "hlt\t\0"
214
1.14M
  /* 1987 */ "bkpt\t\0"
215
1.14M
  /* 1993 */ "csinv\t\0"
216
1.14M
  /* 2000 */ "hvc.w\t\0"
217
1.14M
  /* 2007 */ "udf.w\t\0"
218
1.14M
  /* 2014 */ "crc32w\t\0"
219
1.14M
  /* 2022 */ "crc32cw\t\0"
220
1.14M
  /* 2031 */ "pldw\t\0"
221
1.14M
  /* 2037 */ "bx\t\0"
222
1.14M
  /* 2041 */ "blx\t\0"
223
1.14M
  /* 2046 */ "cbz\t\0"
224
1.14M
  /* 2051 */ "cbnz\t\0"
225
1.14M
  /* 2057 */ "srsda\tsp!, \0"
226
1.14M
  /* 2069 */ "srsia\tsp!, \0"
227
1.14M
  /* 2081 */ "srsdb\tsp!, \0"
228
1.14M
  /* 2093 */ "srsib\tsp!, \0"
229
1.14M
  /* 2105 */ "srsda\tsp, \0"
230
1.14M
  /* 2116 */ "srsia\tsp, \0"
231
1.14M
  /* 2127 */ "srsdb\tsp, \0"
232
1.14M
  /* 2138 */ "srsib\tsp, \0"
233
1.14M
  /* 2149 */ "# XRay Function Patchable RET.\0"
234
1.14M
  /* 2180 */ "# XRay Typed Event Log.\0"
235
1.14M
  /* 2204 */ "# XRay Custom Event Log.\0"
236
1.14M
  /* 2229 */ "# XRay Function Enter.\0"
237
1.14M
  /* 2252 */ "# XRay Tail Call Exit.\0"
238
1.14M
  /* 2275 */ "# XRay Function Exit.\0"
239
1.14M
  /* 2297 */ "__brkdiv0\0"
240
1.14M
  /* 2307 */ "vld1\0"
241
1.14M
  /* 2312 */ "dcps1\0"
242
1.14M
  /* 2318 */ "vst1\0"
243
1.14M
  /* 2323 */ "vcx1\0"
244
1.14M
  /* 2328 */ "vrev32\0"
245
1.14M
  /* 2335 */ "ldc2\0"
246
1.14M
  /* 2340 */ "mrc2\0"
247
1.14M
  /* 2345 */ "mrrc2\0"
248
1.14M
  /* 2351 */ "stc2\0"
249
1.14M
  /* 2356 */ "vld2\0"
250
1.14M
  /* 2361 */ "cdp2\0"
251
1.14M
  /* 2366 */ "mcr2\0"
252
1.14M
  /* 2371 */ "mcrr2\0"
253
1.14M
  /* 2377 */ "dcps2\0"
254
1.14M
  /* 2383 */ "vst2\0"
255
1.14M
  /* 2388 */ "vcx2\0"
256
1.14M
  /* 2393 */ "vld3\0"
257
1.14M
  /* 2398 */ "dcps3\0"
258
1.14M
  /* 2404 */ "vst3\0"
259
1.14M
  /* 2409 */ "vcx3\0"
260
1.14M
  /* 2414 */ "vrev64\0"
261
1.14M
  /* 2421 */ "vld4\0"
262
1.14M
  /* 2426 */ "vst4\0"
263
1.14M
  /* 2431 */ "sxtab16\0"
264
1.14M
  /* 2439 */ "uxtab16\0"
265
1.14M
  /* 2447 */ "sxtb16\0"
266
1.14M
  /* 2454 */ "uxtb16\0"
267
1.14M
  /* 2461 */ "shsub16\0"
268
1.14M
  /* 2469 */ "uhsub16\0"
269
1.14M
  /* 2477 */ "uqsub16\0"
270
1.14M
  /* 2485 */ "ssub16\0"
271
1.14M
  /* 2492 */ "usub16\0"
272
1.14M
  /* 2499 */ "shadd16\0"
273
1.14M
  /* 2507 */ "uhadd16\0"
274
1.14M
  /* 2515 */ "uqadd16\0"
275
1.14M
  /* 2523 */ "sadd16\0"
276
1.14M
  /* 2530 */ "uadd16\0"
277
1.14M
  /* 2537 */ "ssat16\0"
278
1.14M
  /* 2544 */ "usat16\0"
279
1.14M
  /* 2551 */ "vrev16\0"
280
1.14M
  /* 2558 */ "usada8\0"
281
1.14M
  /* 2565 */ "shsub8\0"
282
1.14M
  /* 2572 */ "uhsub8\0"
283
1.14M
  /* 2579 */ "uqsub8\0"
284
1.14M
  /* 2586 */ "ssub8\0"
285
1.14M
  /* 2592 */ "usub8\0"
286
1.14M
  /* 2598 */ "usad8\0"
287
1.14M
  /* 2604 */ "shadd8\0"
288
1.14M
  /* 2611 */ "uhadd8\0"
289
1.14M
  /* 2618 */ "uqadd8\0"
290
1.14M
  /* 2625 */ "sadd8\0"
291
1.14M
  /* 2631 */ "uadd8\0"
292
1.14M
  /* 2637 */ "LIFETIME_END\0"
293
1.14M
  /* 2650 */ "PSEUDO_PROBE\0"
294
1.14M
  /* 2663 */ "BUNDLE\0"
295
1.14M
  /* 2670 */ "DBG_VALUE\0"
296
1.14M
  /* 2680 */ "DBG_INSTR_REF\0"
297
1.14M
  /* 2694 */ "DBG_PHI\0"
298
1.14M
  /* 2702 */ "DBG_LABEL\0"
299
1.14M
  /* 2712 */ "LIFETIME_START\0"
300
1.14M
  /* 2727 */ "DBG_VALUE_LIST\0"
301
1.14M
  /* 2742 */ "vcx1a\0"
302
1.14M
  /* 2748 */ "vcx2a\0"
303
1.14M
  /* 2754 */ "vcx3a\0"
304
1.14M
  /* 2760 */ "vaba\0"
305
1.14M
  /* 2765 */ "cx1da\0"
306
1.14M
  /* 2771 */ "cx2da\0"
307
1.14M
  /* 2777 */ "cx3da\0"
308
1.14M
  /* 2783 */ "lda\0"
309
1.14M
  /* 2787 */ "ldmda\0"
310
1.14M
  /* 2793 */ "stmda\0"
311
1.14M
  /* 2799 */ "vrmlaldavha\0"
312
1.14M
  /* 2811 */ "vrmlsldavha\0"
313
1.14M
  /* 2823 */ "rfeia\0"
314
1.14M
  /* 2829 */ "vldmia\0"
315
1.14M
  /* 2836 */ "vstmia\0"
316
1.14M
  /* 2843 */ "srsia\0"
317
1.14M
  /* 2849 */ "vcmla\0"
318
1.14M
  /* 2855 */ "smmla\0"
319
1.14M
  /* 2861 */ "vnmla\0"
320
1.14M
  /* 2867 */ "vmla\0"
321
1.14M
  /* 2872 */ "vfma\0"
322
1.14M
  /* 2877 */ "vfnma\0"
323
1.14M
  /* 2883 */ "vminnma\0"
324
1.14M
  /* 2891 */ "vmaxnma\0"
325
1.14M
  /* 2899 */ "vmina\0"
326
1.14M
  /* 2905 */ "vrsra\0"
327
1.14M
  /* 2911 */ "vsra\0"
328
1.14M
  /* 2916 */ "vrinta\0"
329
1.14M
  /* 2923 */ "tta\0"
330
1.14M
  /* 2927 */ "vcvta\0"
331
1.14M
  /* 2933 */ "vmladava\0"
332
1.14M
  /* 2942 */ "vmlaldava\0"
333
1.14M
  /* 2952 */ "vmlsldava\0"
334
1.14M
  /* 2962 */ "vmlsdava\0"
335
1.14M
  /* 2971 */ "vaddva\0"
336
1.14M
  /* 2978 */ "vaddlva\0"
337
1.14M
  /* 2986 */ "vmaxa\0"
338
1.14M
  /* 2992 */ "ldab\0"
339
1.14M
  /* 2997 */ "sxtab\0"
340
1.14M
  /* 3003 */ "uxtab\0"
341
1.14M
  /* 3009 */ "smlabb\0"
342
1.14M
  /* 3016 */ "smlalbb\0"
343
1.14M
  /* 3024 */ "smulbb\0"
344
1.14M
  /* 3031 */ "tbb\0"
345
1.14M
  /* 3035 */ "rfedb\0"
346
1.14M
  /* 3041 */ "vldmdb\0"
347
1.14M
  /* 3048 */ "vstmdb\0"
348
1.14M
  /* 3055 */ "srsdb\0"
349
1.14M
  /* 3061 */ "ldmib\0"
350
1.14M
  /* 3067 */ "stmib\0"
351
1.14M
  /* 3073 */ "vshllb\0"
352
1.14M
  /* 3080 */ "vqdmullb\0"
353
1.14M
  /* 3089 */ "vmullb\0"
354
1.14M
  /* 3096 */ "stlb\0"
355
1.14M
  /* 3101 */ "vmovlb\0"
356
1.14M
  /* 3108 */ "dmb\0"
357
1.14M
  /* 3112 */ "vqshrnb\0"
358
1.14M
  /* 3120 */ "vqrshrnb\0"
359
1.14M
  /* 3129 */ "vrshrnb\0"
360
1.14M
  /* 3137 */ "vshrnb\0"
361
1.14M
  /* 3144 */ "vqshrunb\0"
362
1.14M
  /* 3153 */ "vqrshrunb\0"
363
1.14M
  /* 3163 */ "vqmovunb\0"
364
1.14M
  /* 3172 */ "vqmovnb\0"
365
1.14M
  /* 3180 */ "vmovnb\0"
366
1.14M
  /* 3187 */ "swpb\0"
367
1.14M
  /* 3192 */ "vldrb\0"
368
1.14M
  /* 3198 */ "vstrb\0"
369
1.14M
  /* 3204 */ "dsb\0"
370
1.14M
  /* 3208 */ "isb\0"
371
1.14M
  /* 3212 */ "ldrsb\0"
372
1.14M
  /* 3218 */ "tsb\0"
373
1.14M
  /* 3222 */ "smlatb\0"
374
1.14M
  /* 3229 */ "pkhtb\0"
375
1.14M
  /* 3235 */ "smlaltb\0"
376
1.14M
  /* 3243 */ "smultb\0"
377
1.14M
  /* 3250 */ "vcvtb\0"
378
1.14M
  /* 3256 */ "sxtb\0"
379
1.14M
  /* 3261 */ "uxtb\0"
380
1.14M
  /* 3266 */ "qdsub\0"
381
1.14M
  /* 3272 */ "vhsub\0"
382
1.14M
  /* 3278 */ "vqsub\0"
383
1.14M
  /* 3284 */ "vsub\0"
384
1.14M
  /* 3289 */ "smlawb\0"
385
1.14M
  /* 3296 */ "smulwb\0"
386
1.14M
  /* 3303 */ "ldaexb\0"
387
1.14M
  /* 3310 */ "stlexb\0"
388
1.14M
  /* 3317 */ "ldrexb\0"
389
1.14M
  /* 3324 */ "strexb\0"
390
1.14M
  /* 3331 */ "vsbc\0"
391
1.14M
  /* 3336 */ "vadc\0"
392
1.14M
  /* 3341 */ "ldc\0"
393
1.14M
  /* 3345 */ "bfc\0"
394
1.14M
  /* 3349 */ "vbic\0"
395
1.14M
  /* 3354 */ "vshlc\0"
396
1.14M
  /* 3360 */ "smc\0"
397
1.14M
  /* 3364 */ "mrc\0"
398
1.14M
  /* 3368 */ "mrrc\0"
399
1.14M
  /* 3373 */ "rsc\0"
400
1.14M
  /* 3377 */ "stc\0"
401
1.14M
  /* 3381 */ "svc\0"
402
1.14M
  /* 3385 */ "smlad\0"
403
1.14M
  /* 3391 */ "smuad\0"
404
1.14M
  /* 3397 */ "vabd\0"
405
1.14M
  /* 3402 */ "vhcadd\0"
406
1.14M
  /* 3409 */ "vcadd\0"
407
1.14M
  /* 3415 */ "qdadd\0"
408
1.14M
  /* 3421 */ "vrhadd\0"
409
1.14M
  /* 3428 */ "vhadd\0"
410
1.14M
  /* 3434 */ "vpadd\0"
411
1.14M
  /* 3440 */ "vqadd\0"
412
1.14M
  /* 3446 */ "vadd\0"
413
1.14M
  /* 3451 */ "smlald\0"
414
1.14M
  /* 3458 */ "pld\0"
415
1.14M
  /* 3462 */ "smlsld\0"
416
1.14M
  /* 3469 */ "vand\0"
417
1.14M
  /* 3474 */ "vldrd\0"
418
1.14M
  /* 3480 */ "vstrd\0"
419
1.14M
  /* 3486 */ "smlsd\0"
420
1.14M
  /* 3492 */ "smusd\0"
421
1.14M
  /* 3498 */ "ldaexd\0"
422
1.14M
  /* 3505 */ "stlexd\0"
423
1.14M
  /* 3512 */ "ldrexd\0"
424
1.14M
  /* 3519 */ "strexd\0"
425
1.14M
  /* 3526 */ "vacge\0"
426
1.14M
  /* 3532 */ "vcge\0"
427
1.14M
  /* 3537 */ "vcle\0"
428
1.14M
  /* 3542 */ "vrecpe\0"
429
1.14M
  /* 3549 */ "vcmpe\0"
430
1.14M
  /* 3555 */ "vrsqrte\0"
431
1.14M
  /* 3563 */ "bf\0"
432
1.14M
  /* 3566 */ "vbif\0"
433
1.14M
  /* 3571 */ "dbg\0"
434
1.14M
  /* 3575 */ "pacg\0"
435
1.14M
  /* 3580 */ "vqneg\0"
436
1.14M
  /* 3586 */ "vneg\0"
437
1.14M
  /* 3591 */ "sg\0"
438
1.14M
  /* 3594 */ "autg\0"
439
1.14M
  /* 3599 */ "ldah\0"
440
1.14M
  /* 3604 */ "vqdmlah\0"
441
1.14M
  /* 3612 */ "vqrdmlah\0"
442
1.14M
  /* 3621 */ "sxtah\0"
443
1.14M
  /* 3627 */ "uxtah\0"
444
1.14M
  /* 3633 */ "tbh\0"
445
1.14M
  /* 3637 */ "vqdmladh\0"
446
1.14M
  /* 3646 */ "vqrdmladh\0"
447
1.14M
  /* 3656 */ "vqdmlsdh\0"
448
1.14M
  /* 3665 */ "vqrdmlsdh\0"
449
1.14M
  /* 3675 */ "stlh\0"
450
1.14M
  /* 3680 */ "vqdmulh\0"
451
1.14M
  /* 3688 */ "vqrdmulh\0"
452
1.14M
  /* 3697 */ "vrmulh\0"
453
1.14M
  /* 3704 */ "vmulh\0"
454
1.14M
  /* 3710 */ "vldrh\0"
455
1.14M
  /* 3716 */ "vstrh\0"
456
1.14M
  /* 3722 */ "vqdmlash\0"
457
1.14M
  /* 3731 */ "vqrdmlash\0"
458
1.14M
  /* 3741 */ "vqrdmlsh\0"
459
1.14M
  /* 3750 */ "ldrsh\0"
460
1.14M
  /* 3756 */ "push\0"
461
1.14M
  /* 3761 */ "revsh\0"
462
1.14M
  /* 3767 */ "sxth\0"
463
1.14M
  /* 3772 */ "uxth\0"
464
1.14M
  /* 3777 */ "vrmlaldavh\0"
465
1.14M
  /* 3788 */ "vrmlsldavh\0"
466
1.14M
  /* 3799 */ "ldaexh\0"
467
1.14M
  /* 3806 */ "stlexh\0"
468
1.14M
  /* 3813 */ "ldrexh\0"
469
1.14M
  /* 3820 */ "strexh\0"
470
1.14M
  /* 3827 */ "vsbci\0"
471
1.14M
  /* 3833 */ "vadci\0"
472
1.14M
  /* 3839 */ "bfi\0"
473
1.14M
  /* 3843 */ "pli\0"
474
1.14M
  /* 3847 */ "vsli\0"
475
1.14M
  /* 3852 */ "vsri\0"
476
1.14M
  /* 3857 */ "bxj\0"
477
1.14M
  /* 3861 */ "ldc2l\0"
478
1.14M
  /* 3867 */ "stc2l\0"
479
1.14M
  /* 3873 */ "umaal\0"
480
1.14M
  /* 3879 */ "vabal\0"
481
1.14M
  /* 3885 */ "vpadal\0"
482
1.14M
  /* 3892 */ "vqdmlal\0"
483
1.14M
  /* 3900 */ "smlal\0"
484
1.14M
  /* 3906 */ "umlal\0"
485
1.14M
  /* 3912 */ "vmlal\0"
486
1.14M
  /* 3918 */ "vtbl\0"
487
1.14M
  /* 3923 */ "vsubl\0"
488
1.14M
  /* 3929 */ "ldcl\0"
489
1.14M
  /* 3934 */ "stcl\0"
490
1.14M
  /* 3939 */ "vabdl\0"
491
1.14M
  /* 3945 */ "vpaddl\0"
492
1.14M
  /* 3952 */ "vaddl\0"
493
1.14M
  /* 3958 */ "vpsel\0"
494
1.14M
  /* 3964 */ "bfl\0"
495
1.14M
  /* 3968 */ "sqshl\0"
496
1.14M
  /* 3974 */ "uqshl\0"
497
1.14M
  /* 3980 */ "vqshl\0"
498
1.14M
  /* 3986 */ "uqrshl\0"
499
1.14M
  /* 3993 */ "vqrshl\0"
500
1.14M
  /* 4000 */ "vrshl\0"
501
1.14M
  /* 4006 */ "vshl\0"
502
1.14M
  /* 4011 */ "# FEntry call\0"
503
1.14M
  /* 4025 */ "sqshll\0"
504
1.14M
  /* 4032 */ "uqshll\0"
505
1.14M
  /* 4039 */ "uqrshll\0"
506
1.14M
  /* 4047 */ "vshll\0"
507
1.14M
  /* 4053 */ "lsll\0"
508
1.14M
  /* 4058 */ "vqdmull\0"
509
1.14M
  /* 4066 */ "smull\0"
510
1.14M
  /* 4072 */ "umull\0"
511
1.14M
  /* 4078 */ "vmull\0"
512
1.14M
  /* 4084 */ "sqrshrl\0"
513
1.14M
  /* 4092 */ "srshrl\0"
514
1.14M
  /* 4099 */ "urshrl\0"
515
1.14M
  /* 4106 */ "asrl\0"
516
1.14M
  /* 4111 */ "lsrl\0"
517
1.14M
  /* 4116 */ "vbsl\0"
518
1.14M
  /* 4121 */ "vqdmlsl\0"
519
1.14M
  /* 4129 */ "vmlsl\0"
520
1.14M
  /* 4135 */ "stl\0"
521
1.14M
  /* 4139 */ "vcmul\0"
522
1.14M
  /* 4145 */ "smmul\0"
523
1.14M
  /* 4151 */ "vnmul\0"
524
1.14M
  /* 4157 */ "vmul\0"
525
1.14M
  /* 4162 */ "vmovl\0"
526
1.14M
  /* 4168 */ "vlldm\0"
527
1.14M
  /* 4174 */ "vminnm\0"
528
1.14M
  /* 4181 */ "vmaxnm\0"
529
1.14M
  /* 4188 */ "vscclrm\0"
530
1.14M
  /* 4196 */ "vrintm\0"
531
1.14M
  /* 4203 */ "vlstm\0"
532
1.14M
  /* 4209 */ "vcvtm\0"
533
1.14M
  /* 4215 */ "vrsubhn\0"
534
1.14M
  /* 4223 */ "vsubhn\0"
535
1.14M
  /* 4230 */ "vraddhn\0"
536
1.14M
  /* 4238 */ "vaddhn\0"
537
1.14M
  /* 4245 */ "vpmin\0"
538
1.14M
  /* 4251 */ "vmin\0"
539
1.14M
  /* 4256 */ "cmn\0"
540
1.14M
  /* 4260 */ "vqshrn\0"
541
1.14M
  /* 4267 */ "vqrshrn\0"
542
1.14M
  /* 4275 */ "vrshrn\0"
543
1.14M
  /* 4282 */ "vshrn\0"
544
1.14M
  /* 4288 */ "vorn\0"
545
1.14M
  /* 4293 */ "vtrn\0"
546
1.14M
  /* 4298 */ "vrintn\0"
547
1.14M
  /* 4305 */ "vcvtn\0"
548
1.14M
  /* 4311 */ "vqshrun\0"
549
1.14M
  /* 4319 */ "vqrshrun\0"
550
1.14M
  /* 4328 */ "vqmovun\0"
551
1.14M
  /* 4336 */ "vmvn\0"
552
1.14M
  /* 4341 */ "vqmovn\0"
553
1.14M
  /* 4348 */ "vmovn\0"
554
1.14M
  /* 4354 */ "trap\0"
555
1.14M
  /* 4359 */ "cdp\0"
556
1.14M
  /* 4363 */ "vzip\0"
557
1.14M
  /* 4368 */ "vcmp\0"
558
1.14M
  /* 4373 */ "pop\0"
559
1.14M
  /* 4377 */ "pac\tr12, lr, sp\0"
560
1.14M
  /* 4393 */ "pacbti\tr12, lr, sp\0"
561
1.14M
  /* 4412 */ "aut\tr12, lr, sp\0"
562
1.14M
  /* 4428 */ "lctp\0"
563
1.14M
  /* 4433 */ "vctp\0"
564
1.14M
  /* 4438 */ "vrintp\0"
565
1.14M
  /* 4445 */ "vcvtp\0"
566
1.14M
  /* 4451 */ "vddup\0"
567
1.14M
  /* 4457 */ "vidup\0"
568
1.14M
  /* 4463 */ "vdup\0"
569
1.14M
  /* 4468 */ "vdwdup\0"
570
1.14M
  /* 4475 */ "viwdup\0"
571
1.14M
  /* 4482 */ "vswp\0"
572
1.14M
  /* 4487 */ "vuzp\0"
573
1.14M
  /* 4492 */ "vceq\0"
574
1.14M
  /* 4497 */ "teq\0"
575
1.14M
  /* 4501 */ "smmlar\0"
576
1.14M
  /* 4508 */ "mcr\0"
577
1.14M
  /* 4512 */ "adr\0"
578
1.14M
  /* 4516 */ "vldr\0"
579
1.14M
  /* 4521 */ "sqrshr\0"
580
1.14M
  /* 4528 */ "srshr\0"
581
1.14M
  /* 4534 */ "urshr\0"
582
1.14M
  /* 4540 */ "vrshr\0"
583
1.14M
  /* 4546 */ "vshr\0"
584
1.14M
  /* 4551 */ "smmulr\0"
585
1.14M
  /* 4558 */ "veor\0"
586
1.14M
  /* 4563 */ "ror\0"
587
1.14M
  /* 4567 */ "mcrr\0"
588
1.14M
  /* 4572 */ "vorr\0"
589
1.14M
  /* 4577 */ "asr\0"
590
1.14M
  /* 4581 */ "smmlsr\0"
591
1.14M
  /* 4588 */ "vmsr\0"
592
1.14M
  /* 4593 */ "vbrsr\0"
593
1.14M
  /* 4599 */ "vrintr\0"
594
1.14M
  /* 4606 */ "vstr\0"
595
1.14M
  /* 4611 */ "vcvtr\0"
596
1.14M
  /* 4617 */ "vmlas\0"
597
1.14M
  /* 4623 */ "vfmas\0"
598
1.14M
  /* 4629 */ "vqabs\0"
599
1.14M
  /* 4635 */ "vabs\0"
600
1.14M
  /* 4640 */ "subs\0"
601
1.14M
  /* 4645 */ "vcls\0"
602
1.14M
  /* 4650 */ "smmls\0"
603
1.14M
  /* 4656 */ "vnmls\0"
604
1.14M
  /* 4662 */ "vmls\0"
605
1.14M
  /* 4667 */ "vfms\0"
606
1.14M
  /* 4672 */ "vfnms\0"
607
1.14M
  /* 4678 */ "bxns\0"
608
1.14M
  /* 4683 */ "blxns\0"
609
1.14M
  /* 4689 */ "vrecps\0"
610
1.14M
  /* 4696 */ "vmrs\0"
611
1.14M
  /* 4701 */ "asrs\0"
612
1.14M
  /* 4706 */ "lsrs\0"
613
1.14M
  /* 4711 */ "vrsqrts\0"
614
1.14M
  /* 4719 */ "movs\0"
615
1.14M
  /* 4724 */ "ssat\0"
616
1.14M
  /* 4729 */ "usat\0"
617
1.14M
  /* 4734 */ "ttat\0"
618
1.14M
  /* 4739 */ "smlabt\0"
619
1.14M
  /* 4746 */ "pkhbt\0"
620
1.14M
  /* 4752 */ "smlalbt\0"
621
1.14M
  /* 4760 */ "smulbt\0"
622
1.14M
  /* 4767 */ "ldrbt\0"
623
1.14M
  /* 4773 */ "strbt\0"
624
1.14M
  /* 4779 */ "ldrsbt\0"
625
1.14M
  /* 4786 */ "eret\0"
626
1.14M
  /* 4791 */ "vacgt\0"
627
1.14M
  /* 4797 */ "vcgt\0"
628
1.14M
  /* 4802 */ "ldrht\0"
629
1.14M
  /* 4808 */ "strht\0"
630
1.14M
  /* 4814 */ "ldrsht\0"
631
1.14M
  /* 4821 */ "rbit\0"
632
1.14M
  /* 4826 */ "vbit\0"
633
1.14M
  /* 4831 */ "vclt\0"
634
1.14M
  /* 4836 */ "vshllt\0"
635
1.14M
  /* 4843 */ "vqdmullt\0"
636
1.14M
  /* 4852 */ "vmullt\0"
637
1.14M
  /* 4859 */ "vmovlt\0"
638
1.14M
  /* 4866 */ "vcnt\0"
639
1.14M
  /* 4871 */ "hint\0"
640
1.14M
  /* 4876 */ "vqshrnt\0"
641
1.14M
  /* 4884 */ "vqrshrnt\0"
642
1.14M
  /* 4893 */ "vrshrnt\0"
643
1.14M
  /* 4901 */ "vshrnt\0"
644
1.14M
  /* 4908 */ "vqshrunt\0"
645
1.14M
  /* 4917 */ "vqrshrunt\0"
646
1.14M
  /* 4927 */ "vqmovunt\0"
647
1.14M
  /* 4936 */ "vqmovnt\0"
648
1.14M
  /* 4944 */ "vmovnt\0"
649
1.14M
  /* 4951 */ "vpnot\0"
650
1.14M
  /* 4957 */ "vpt\0"
651
1.14M
  /* 4961 */ "ldrt\0"
652
1.14M
  /* 4966 */ "vsqrt\0"
653
1.14M
  /* 4972 */ "strt\0"
654
1.14M
  /* 4977 */ "vpst\0"
655
1.14M
  /* 4982 */ "vtst\0"
656
1.14M
  /* 4987 */ "smlatt\0"
657
1.14M
  /* 4994 */ "smlaltt\0"
658
1.14M
  /* 5002 */ "smultt\0"
659
1.14M
  /* 5009 */ "ttt\0"
660
1.14M
  /* 5013 */ "vcvtt\0"
661
1.14M
  /* 5019 */ "bxaut\0"
662
1.14M
  /* 5025 */ "vjcvt\0"
663
1.14M
  /* 5031 */ "vcvt\0"
664
1.14M
  /* 5036 */ "movt\0"
665
1.14M
  /* 5041 */ "smlawt\0"
666
1.14M
  /* 5048 */ "smulwt\0"
667
1.14M
  /* 5055 */ "vext\0"
668
1.14M
  /* 5060 */ "vqshlu\0"
669
1.14M
  /* 5067 */ "vabav\0"
670
1.14M
  /* 5073 */ "vmladav\0"
671
1.14M
  /* 5081 */ "vmlaldav\0"
672
1.14M
  /* 5090 */ "vmlsldav\0"
673
1.14M
  /* 5099 */ "vmlsdav\0"
674
1.14M
  /* 5107 */ "vminnmav\0"
675
1.14M
  /* 5116 */ "vmaxnmav\0"
676
1.14M
  /* 5125 */ "vminav\0"
677
1.14M
  /* 5132 */ "vmaxav\0"
678
1.14M
  /* 5139 */ "vaddv\0"
679
1.14M
  /* 5145 */ "rev\0"
680
1.14M
  /* 5149 */ "sdiv\0"
681
1.14M
  /* 5154 */ "udiv\0"
682
1.14M
  /* 5159 */ "vdiv\0"
683
1.14M
  /* 5164 */ "vaddlv\0"
684
1.14M
  /* 5171 */ "vminnmv\0"
685
1.14M
  /* 5179 */ "vmaxnmv\0"
686
1.14M
  /* 5187 */ "vminv\0"
687
1.14M
  /* 5193 */ "vmov\0"
688
1.14M
  /* 5198 */ "vmaxv\0"
689
1.14M
  /* 5204 */ "vsubw\0"
690
1.14M
  /* 5210 */ "vaddw\0"
691
1.14M
  /* 5216 */ "pldw\0"
692
1.14M
  /* 5221 */ "vldrw\0"
693
1.14M
  /* 5227 */ "vstrw\0"
694
1.14M
  /* 5233 */ "movw\0"
695
1.14M
  /* 5238 */ "vrmlaldavhax\0"
696
1.14M
  /* 5251 */ "vrmlsldavhax\0"
697
1.14M
  /* 5264 */ "fldmiax\0"
698
1.14M
  /* 5272 */ "fstmiax\0"
699
1.14M
  /* 5280 */ "vpmax\0"
700
1.14M
  /* 5286 */ "vmax\0"
701
1.14M
  /* 5291 */ "shsax\0"
702
1.14M
  /* 5297 */ "uhsax\0"
703
1.14M
  /* 5303 */ "uqsax\0"
704
1.14M
  /* 5309 */ "ssax\0"
705
1.14M
  /* 5314 */ "usax\0"
706
1.14M
  /* 5319 */ "vmladavax\0"
707
1.14M
  /* 5329 */ "vmlaldavax\0"
708
1.14M
  /* 5340 */ "vmlsldavax\0"
709
1.14M
  /* 5351 */ "vmlsdavax\0"
710
1.14M
  /* 5361 */ "fldmdbx\0"
711
1.14M
  /* 5369 */ "fstmdbx\0"
712
1.14M
  /* 5377 */ "vtbx\0"
713
1.14M
  /* 5382 */ "smladx\0"
714
1.14M
  /* 5389 */ "smuadx\0"
715
1.14M
  /* 5396 */ "smlaldx\0"
716
1.14M
  /* 5404 */ "smlsldx\0"
717
1.14M
  /* 5412 */ "smlsdx\0"
718
1.14M
  /* 5419 */ "smusdx\0"
719
1.14M
  /* 5426 */ "ldaex\0"
720
1.14M
  /* 5432 */ "stlex\0"
721
1.14M
  /* 5438 */ "ldrex\0"
722
1.14M
  /* 5444 */ "clrex\0"
723
1.14M
  /* 5450 */ "strex\0"
724
1.14M
  /* 5456 */ "sbfx\0"
725
1.14M
  /* 5461 */ "ubfx\0"
726
1.14M
  /* 5466 */ "vqdmladhx\0"
727
1.14M
  /* 5476 */ "vqrdmladhx\0"
728
1.14M
  /* 5487 */ "vqdmlsdhx\0"
729
1.14M
  /* 5497 */ "vqrdmlsdhx\0"
730
1.14M
  /* 5508 */ "vrmlaldavhx\0"
731
1.14M
  /* 5520 */ "vrmlsldavhx\0"
732
1.14M
  /* 5532 */ "blx\0"
733
1.14M
  /* 5536 */ "bflx\0"
734
1.14M
  /* 5541 */ "rrx\0"
735
1.14M
  /* 5545 */ "shasx\0"
736
1.14M
  /* 5551 */ "uhasx\0"
737
1.14M
  /* 5557 */ "uqasx\0"
738
1.14M
  /* 5563 */ "sasx\0"
739
1.14M
  /* 5568 */ "uasx\0"
740
1.14M
  /* 5573 */ "vrintx\0"
741
1.14M
  /* 5580 */ "vmladavx\0"
742
1.14M
  /* 5589 */ "vmlaldavx\0"
743
1.14M
  /* 5599 */ "vmlsldavx\0"
744
1.14M
  /* 5609 */ "vmlsdavx\0"
745
1.14M
  /* 5618 */ "vclz\0"
746
1.14M
  /* 5623 */ "vrintz\0"
747
1.14M
};
748
1.14M
#endif // CAPSTONE_DIET
749
750
1.14M
  static const uint32_t OpInfo0[] = {
751
1.14M
    0U, // PHI
752
1.14M
    0U, // INLINEASM
753
1.14M
    0U, // INLINEASM_BR
754
1.14M
    0U, // CFI_INSTRUCTION
755
1.14M
    0U, // EH_LABEL
756
1.14M
    0U, // GC_LABEL
757
1.14M
    0U, // ANNOTATION_LABEL
758
1.14M
    0U, // KILL
759
1.14M
    0U, // EXTRACT_SUBREG
760
1.14M
    0U, // INSERT_SUBREG
761
1.14M
    0U, // IMPLICIT_DEF
762
1.14M
    0U, // SUBREG_TO_REG
763
1.14M
    0U, // COPY_TO_REGCLASS
764
1.14M
    2671U,  // DBG_VALUE
765
1.14M
    2728U,  // DBG_VALUE_LIST
766
1.14M
    2681U,  // DBG_INSTR_REF
767
1.14M
    2695U,  // DBG_PHI
768
1.14M
    2703U,  // DBG_LABEL
769
1.14M
    0U, // REG_SEQUENCE
770
1.14M
    0U, // COPY
771
1.14M
    2664U,  // BUNDLE
772
1.14M
    2713U,  // LIFETIME_START
773
1.14M
    2638U,  // LIFETIME_END
774
1.14M
    2651U,  // PSEUDO_PROBE
775
1.14M
    0U, // ARITH_FENCE
776
1.14M
    0U, // STACKMAP
777
1.14M
    4012U,  // FENTRY_CALL
778
1.14M
    0U, // PATCHPOINT
779
1.14M
    0U, // LOAD_STACK_GUARD
780
1.14M
    0U, // PREALLOCATED_SETUP
781
1.14M
    0U, // PREALLOCATED_ARG
782
1.14M
    0U, // STATEPOINT
783
1.14M
    0U, // LOCAL_ESCAPE
784
1.14M
    0U, // FAULTING_OP
785
1.14M
    0U, // PATCHABLE_OP
786
1.14M
    2230U,  // PATCHABLE_FUNCTION_ENTER
787
1.14M
    2150U,  // PATCHABLE_RET
788
1.14M
    2276U,  // PATCHABLE_FUNCTION_EXIT
789
1.14M
    2253U,  // PATCHABLE_TAIL_CALL
790
1.14M
    2205U,  // PATCHABLE_EVENT_CALL
791
1.14M
    2181U,  // PATCHABLE_TYPED_EVENT_CALL
792
1.14M
    0U, // ICALL_BRANCH_FUNNEL
793
1.14M
    0U, // MEMBARRIER
794
1.14M
    0U, // JUMP_TABLE_DEBUG_INFO
795
1.14M
    0U, // G_ASSERT_SEXT
796
1.14M
    0U, // G_ASSERT_ZEXT
797
1.14M
    0U, // G_ASSERT_ALIGN
798
1.14M
    0U, // G_ADD
799
1.14M
    0U, // G_SUB
800
1.14M
    0U, // G_MUL
801
1.14M
    0U, // G_SDIV
802
1.14M
    0U, // G_UDIV
803
1.14M
    0U, // G_SREM
804
1.14M
    0U, // G_UREM
805
1.14M
    0U, // G_SDIVREM
806
1.14M
    0U, // G_UDIVREM
807
1.14M
    0U, // G_AND
808
1.14M
    0U, // G_OR
809
1.14M
    0U, // G_XOR
810
1.14M
    0U, // G_IMPLICIT_DEF
811
1.14M
    0U, // G_PHI
812
1.14M
    0U, // G_FRAME_INDEX
813
1.14M
    0U, // G_GLOBAL_VALUE
814
1.14M
    0U, // G_CONSTANT_POOL
815
1.14M
    0U, // G_EXTRACT
816
1.14M
    0U, // G_UNMERGE_VALUES
817
1.14M
    0U, // G_INSERT
818
1.14M
    0U, // G_MERGE_VALUES
819
1.14M
    0U, // G_BUILD_VECTOR
820
1.14M
    0U, // G_BUILD_VECTOR_TRUNC
821
1.14M
    0U, // G_CONCAT_VECTORS
822
1.14M
    0U, // G_PTRTOINT
823
1.14M
    0U, // G_INTTOPTR
824
1.14M
    0U, // G_BITCAST
825
1.14M
    0U, // G_FREEZE
826
1.14M
    0U, // G_CONSTANT_FOLD_BARRIER
827
1.14M
    0U, // G_INTRINSIC_FPTRUNC_ROUND
828
1.14M
    0U, // G_INTRINSIC_TRUNC
829
1.14M
    0U, // G_INTRINSIC_ROUND
830
1.14M
    0U, // G_INTRINSIC_LRINT
831
1.14M
    0U, // G_INTRINSIC_ROUNDEVEN
832
1.14M
    0U, // G_READCYCLECOUNTER
833
1.14M
    0U, // G_LOAD
834
1.14M
    0U, // G_SEXTLOAD
835
1.14M
    0U, // G_ZEXTLOAD
836
1.14M
    0U, // G_INDEXED_LOAD
837
1.14M
    0U, // G_INDEXED_SEXTLOAD
838
1.14M
    0U, // G_INDEXED_ZEXTLOAD
839
1.14M
    0U, // G_STORE
840
1.14M
    0U, // G_INDEXED_STORE
841
1.14M
    0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
842
1.14M
    0U, // G_ATOMIC_CMPXCHG
843
1.14M
    0U, // G_ATOMICRMW_XCHG
844
1.14M
    0U, // G_ATOMICRMW_ADD
845
1.14M
    0U, // G_ATOMICRMW_SUB
846
1.14M
    0U, // G_ATOMICRMW_AND
847
1.14M
    0U, // G_ATOMICRMW_NAND
848
1.14M
    0U, // G_ATOMICRMW_OR
849
1.14M
    0U, // G_ATOMICRMW_XOR
850
1.14M
    0U, // G_ATOMICRMW_MAX
851
1.14M
    0U, // G_ATOMICRMW_MIN
852
1.14M
    0U, // G_ATOMICRMW_UMAX
853
1.14M
    0U, // G_ATOMICRMW_UMIN
854
1.14M
    0U, // G_ATOMICRMW_FADD
855
1.14M
    0U, // G_ATOMICRMW_FSUB
856
1.14M
    0U, // G_ATOMICRMW_FMAX
857
1.14M
    0U, // G_ATOMICRMW_FMIN
858
1.14M
    0U, // G_ATOMICRMW_UINC_WRAP
859
1.14M
    0U, // G_ATOMICRMW_UDEC_WRAP
860
1.14M
    0U, // G_FENCE
861
1.14M
    0U, // G_PREFETCH
862
1.14M
    0U, // G_BRCOND
863
1.14M
    0U, // G_BRINDIRECT
864
1.14M
    0U, // G_INVOKE_REGION_START
865
1.14M
    0U, // G_INTRINSIC
866
1.14M
    0U, // G_INTRINSIC_W_SIDE_EFFECTS
867
1.14M
    0U, // G_INTRINSIC_CONVERGENT
868
1.14M
    0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
869
1.14M
    0U, // G_ANYEXT
870
1.14M
    0U, // G_TRUNC
871
1.14M
    0U, // G_CONSTANT
872
1.14M
    0U, // G_FCONSTANT
873
1.14M
    0U, // G_VASTART
874
1.14M
    0U, // G_VAARG
875
1.14M
    0U, // G_SEXT
876
1.14M
    0U, // G_SEXT_INREG
877
1.14M
    0U, // G_ZEXT
878
1.14M
    0U, // G_SHL
879
1.14M
    0U, // G_LSHR
880
1.14M
    0U, // G_ASHR
881
1.14M
    0U, // G_FSHL
882
1.14M
    0U, // G_FSHR
883
1.14M
    0U, // G_ROTR
884
1.14M
    0U, // G_ROTL
885
1.14M
    0U, // G_ICMP
886
1.14M
    0U, // G_FCMP
887
1.14M
    0U, // G_SELECT
888
1.14M
    0U, // G_UADDO
889
1.14M
    0U, // G_UADDE
890
1.14M
    0U, // G_USUBO
891
1.14M
    0U, // G_USUBE
892
1.14M
    0U, // G_SADDO
893
1.14M
    0U, // G_SADDE
894
1.14M
    0U, // G_SSUBO
895
1.14M
    0U, // G_SSUBE
896
1.14M
    0U, // G_UMULO
897
1.14M
    0U, // G_SMULO
898
1.14M
    0U, // G_UMULH
899
1.14M
    0U, // G_SMULH
900
1.14M
    0U, // G_UADDSAT
901
1.14M
    0U, // G_SADDSAT
902
1.14M
    0U, // G_USUBSAT
903
1.14M
    0U, // G_SSUBSAT
904
1.14M
    0U, // G_USHLSAT
905
1.14M
    0U, // G_SSHLSAT
906
1.14M
    0U, // G_SMULFIX
907
1.14M
    0U, // G_UMULFIX
908
1.14M
    0U, // G_SMULFIXSAT
909
1.14M
    0U, // G_UMULFIXSAT
910
1.14M
    0U, // G_SDIVFIX
911
1.14M
    0U, // G_UDIVFIX
912
1.14M
    0U, // G_SDIVFIXSAT
913
1.14M
    0U, // G_UDIVFIXSAT
914
1.14M
    0U, // G_FADD
915
1.14M
    0U, // G_FSUB
916
1.14M
    0U, // G_FMUL
917
1.14M
    0U, // G_FMA
918
1.14M
    0U, // G_FMAD
919
1.14M
    0U, // G_FDIV
920
1.14M
    0U, // G_FREM
921
1.14M
    0U, // G_FPOW
922
1.14M
    0U, // G_FPOWI
923
1.14M
    0U, // G_FEXP
924
1.14M
    0U, // G_FEXP2
925
1.14M
    0U, // G_FEXP10
926
1.14M
    0U, // G_FLOG
927
1.14M
    0U, // G_FLOG2
928
1.14M
    0U, // G_FLOG10
929
1.14M
    0U, // G_FLDEXP
930
1.14M
    0U, // G_FFREXP
931
1.14M
    0U, // G_FNEG
932
1.14M
    0U, // G_FPEXT
933
1.14M
    0U, // G_FPTRUNC
934
1.14M
    0U, // G_FPTOSI
935
1.14M
    0U, // G_FPTOUI
936
1.14M
    0U, // G_SITOFP
937
1.14M
    0U, // G_UITOFP
938
1.14M
    0U, // G_FABS
939
1.14M
    0U, // G_FCOPYSIGN
940
1.14M
    0U, // G_IS_FPCLASS
941
1.14M
    0U, // G_FCANONICALIZE
942
1.14M
    0U, // G_FMINNUM
943
1.14M
    0U, // G_FMAXNUM
944
1.14M
    0U, // G_FMINNUM_IEEE
945
1.14M
    0U, // G_FMAXNUM_IEEE
946
1.14M
    0U, // G_FMINIMUM
947
1.14M
    0U, // G_FMAXIMUM
948
1.14M
    0U, // G_GET_FPENV
949
1.14M
    0U, // G_SET_FPENV
950
1.14M
    0U, // G_RESET_FPENV
951
1.14M
    0U, // G_GET_FPMODE
952
1.14M
    0U, // G_SET_FPMODE
953
1.14M
    0U, // G_RESET_FPMODE
954
1.14M
    0U, // G_PTR_ADD
955
1.14M
    0U, // G_PTRMASK
956
1.14M
    0U, // G_SMIN
957
1.14M
    0U, // G_SMAX
958
1.14M
    0U, // G_UMIN
959
1.14M
    0U, // G_UMAX
960
1.14M
    0U, // G_ABS
961
1.14M
    0U, // G_LROUND
962
1.14M
    0U, // G_LLROUND
963
1.14M
    0U, // G_BR
964
1.14M
    0U, // G_BRJT
965
1.14M
    0U, // G_INSERT_VECTOR_ELT
966
1.14M
    0U, // G_EXTRACT_VECTOR_ELT
967
1.14M
    0U, // G_SHUFFLE_VECTOR
968
1.14M
    0U, // G_CTTZ
969
1.14M
    0U, // G_CTTZ_ZERO_UNDEF
970
1.14M
    0U, // G_CTLZ
971
1.14M
    0U, // G_CTLZ_ZERO_UNDEF
972
1.14M
    0U, // G_CTPOP
973
1.14M
    0U, // G_BSWAP
974
1.14M
    0U, // G_BITREVERSE
975
1.14M
    0U, // G_FCEIL
976
1.14M
    0U, // G_FCOS
977
1.14M
    0U, // G_FSIN
978
1.14M
    0U, // G_FSQRT
979
1.14M
    0U, // G_FFLOOR
980
1.14M
    0U, // G_FRINT
981
1.14M
    0U, // G_FNEARBYINT
982
1.14M
    0U, // G_ADDRSPACE_CAST
983
1.14M
    0U, // G_BLOCK_ADDR
984
1.14M
    0U, // G_JUMP_TABLE
985
1.14M
    0U, // G_DYN_STACKALLOC
986
1.14M
    0U, // G_STACKSAVE
987
1.14M
    0U, // G_STACKRESTORE
988
1.14M
    0U, // G_STRICT_FADD
989
1.14M
    0U, // G_STRICT_FSUB
990
1.14M
    0U, // G_STRICT_FMUL
991
1.14M
    0U, // G_STRICT_FDIV
992
1.14M
    0U, // G_STRICT_FREM
993
1.14M
    0U, // G_STRICT_FMA
994
1.14M
    0U, // G_STRICT_FSQRT
995
1.14M
    0U, // G_STRICT_FLDEXP
996
1.14M
    0U, // G_READ_REGISTER
997
1.14M
    0U, // G_WRITE_REGISTER
998
1.14M
    0U, // G_MEMCPY
999
1.14M
    0U, // G_MEMCPY_INLINE
1000
1.14M
    0U, // G_MEMMOVE
1001
1.14M
    0U, // G_MEMSET
1002
1.14M
    0U, // G_BZERO
1003
1.14M
    0U, // G_VECREDUCE_SEQ_FADD
1004
1.14M
    0U, // G_VECREDUCE_SEQ_FMUL
1005
1.14M
    0U, // G_VECREDUCE_FADD
1006
1.14M
    0U, // G_VECREDUCE_FMUL
1007
1.14M
    0U, // G_VECREDUCE_FMAX
1008
1.14M
    0U, // G_VECREDUCE_FMIN
1009
1.14M
    0U, // G_VECREDUCE_FMAXIMUM
1010
1.14M
    0U, // G_VECREDUCE_FMINIMUM
1011
1.14M
    0U, // G_VECREDUCE_ADD
1012
1.14M
    0U, // G_VECREDUCE_MUL
1013
1.14M
    0U, // G_VECREDUCE_AND
1014
1.14M
    0U, // G_VECREDUCE_OR
1015
1.14M
    0U, // G_VECREDUCE_XOR
1016
1.14M
    0U, // G_VECREDUCE_SMAX
1017
1.14M
    0U, // G_VECREDUCE_SMIN
1018
1.14M
    0U, // G_VECREDUCE_UMAX
1019
1.14M
    0U, // G_VECREDUCE_UMIN
1020
1.14M
    0U, // G_SBFX
1021
1.14M
    0U, // G_UBFX
1022
1.14M
    0U, // ABS
1023
1.14M
    0U, // ADDSri
1024
1.14M
    0U, // ADDSrr
1025
1.14M
    0U, // ADDSrsi
1026
1.14M
    0U, // ADDSrsr
1027
1.14M
    0U, // ADJCALLSTACKDOWN
1028
1.14M
    0U, // ADJCALLSTACKUP
1029
1.14M
    12770U, // ASRi
1030
1.14M
    12770U, // ASRr
1031
1.14M
    0U, // B
1032
1.14M
    0U, // BCCZi64
1033
1.14M
    0U, // BCCi64
1034
1.14M
    0U, // BLX_noip
1035
1.14M
    0U, // BLX_pred_noip
1036
1.14M
    0U, // BL_PUSHLR
1037
1.14M
    0U, // BMOVPCB_CALL
1038
1.14M
    0U, // BMOVPCRX_CALL
1039
1.14M
    0U, // BR_JTadd
1040
1.14M
    0U, // BR_JTm_i12
1041
1.14M
    0U, // BR_JTm_rs
1042
1.14M
    0U, // BR_JTr
1043
1.14M
    0U, // BX_CALL
1044
1.14M
    0U, // CMP_SWAP_16
1045
1.14M
    0U, // CMP_SWAP_32
1046
1.14M
    0U, // CMP_SWAP_64
1047
1.14M
    0U, // CMP_SWAP_8
1048
1.14M
    0U, // CONSTPOOL_ENTRY
1049
1.14M
    0U, // COPY_STRUCT_BYVAL_I32
1050
1.14M
    67130072U,  // ITasm
1051
1.14M
    0U, // Int_eh_sjlj_dispatchsetup
1052
1.14M
    0U, // Int_eh_sjlj_longjmp
1053
1.14M
    0U, // Int_eh_sjlj_setjmp
1054
1.14M
    0U, // Int_eh_sjlj_setjmp_nofp
1055
1.14M
    0U, // Int_eh_sjlj_setup_dispatch
1056
1.14M
    0U, // JUMPTABLE_ADDRS
1057
1.14M
    0U, // JUMPTABLE_INSTS
1058
1.14M
    0U, // JUMPTABLE_TBB
1059
1.14M
    0U, // JUMPTABLE_TBH
1060
1.14M
    0U, // LDMIA_RET
1061
1.14M
    29344U, // LDRBT_POST
1062
1.14M
    29094U, // LDRConstPool
1063
1.14M
    29379U, // LDRHTii
1064
1.14M
    0U, // LDRLIT_ga_abs
1065
1.14M
    0U, // LDRLIT_ga_pcrel
1066
1.14M
    0U, // LDRLIT_ga_pcrel_ldr
1067
1.14M
    29356U, // LDRSBTii
1068
1.14M
    29391U, // LDRSHTii
1069
1.14M
    29538U, // LDRT_POST
1070
1.14M
    0U, // LEApcrel
1071
1.14M
    0U, // LEApcrelJT
1072
1.14M
    0U, // LOADDUAL
1073
1.14M
    12318U, // LSLi
1074
1.14M
    12318U, // LSLr
1075
1.14M
    12777U, // LSRi
1076
1.14M
    12777U, // LSRr
1077
1.14M
    0U, // MEMCPY
1078
1.14M
    0U, // MLAv5
1079
1.14M
    0U, // MOVCCi
1080
1.14M
    0U, // MOVCCi16
1081
1.14M
    0U, // MOVCCi32imm
1082
1.14M
    0U, // MOVCCr
1083
1.14M
    0U, // MOVCCsi
1084
1.14M
    0U, // MOVCCsr
1085
1.14M
    0U, // MOVPCRX
1086
1.14M
    0U, // MOVTi16_ga_pcrel
1087
1.14M
    0U, // MOV_ga_pcrel
1088
1.14M
    0U, // MOV_ga_pcrel_ldr
1089
1.14M
    0U, // MOVi16_ga_pcrel
1090
1.14M
    0U, // MOVi32imm
1091
1.14M
    0U, // MOVsra_glue
1092
1.14M
    0U, // MOVsrl_glue
1093
1.14M
    0U, // MQPRCopy
1094
1.14M
    0U, // MQQPRLoad
1095
1.14M
    0U, // MQQPRStore
1096
1.14M
    0U, // MQQQQPRLoad
1097
1.14M
    0U, // MQQQQPRStore
1098
1.14M
    0U, // MULv5
1099
1.14M
    0U, // MVE_MEMCPYLOOPINST
1100
1.14M
    0U, // MVE_MEMSETLOOPINST
1101
1.14M
    0U, // MVNCCi
1102
1.14M
    0U, // PICADD
1103
1.14M
    0U, // PICLDR
1104
1.14M
    0U, // PICLDRB
1105
1.14M
    0U, // PICLDRH
1106
1.14M
    0U, // PICLDRSB
1107
1.14M
    0U, // PICLDRSH
1108
1.14M
    0U, // PICSTR
1109
1.14M
    0U, // PICSTRB
1110
1.14M
    0U, // PICSTRH
1111
1.14M
    12756U, // RORi
1112
1.14M
    12756U, // RORr
1113
1.14M
    0U, // RRX
1114
1.14M
    38310U, // RRXi
1115
1.14M
    0U, // RSBSri
1116
1.14M
    0U, // RSBSrsi
1117
1.14M
    0U, // RSBSrsr
1118
1.14M
    0U, // SEH_EpilogEnd
1119
1.14M
    0U, // SEH_EpilogStart
1120
1.14M
    0U, // SEH_Nop
1121
1.14M
    0U, // SEH_Nop_Ret
1122
1.14M
    0U, // SEH_PrologEnd
1123
1.14M
    0U, // SEH_SaveFRegs
1124
1.14M
    0U, // SEH_SaveLR
1125
1.14M
    0U, // SEH_SaveRegs
1126
1.14M
    0U, // SEH_SaveRegs_Ret
1127
1.14M
    0U, // SEH_SaveSP
1128
1.14M
    0U, // SEH_StackAlloc
1129
1.14M
    0U, // SMLALv5
1130
1.14M
    0U, // SMULLv5
1131
1.14M
    0U, // SPACE
1132
1.14M
    0U, // STOREDUAL
1133
1.14M
    29350U, // STRBT_POST
1134
1.14M
    0U, // STRBi_preidx
1135
1.14M
    0U, // STRBr_preidx
1136
1.14M
    0U, // STRH_preidx
1137
1.14M
    29549U, // STRT_POST
1138
1.14M
    0U, // STRi_preidx
1139
1.14M
    0U, // STRr_preidx
1140
1.14M
    0U, // SUBS_PC_LR
1141
1.14M
    0U, // SUBSri
1142
1.14M
    0U, // SUBSrr
1143
1.14M
    0U, // SUBSrsi
1144
1.14M
    0U, // SUBSrsr
1145
1.14M
    0U, // SpeculationBarrierISBDSBEndBB
1146
1.14M
    0U, // SpeculationBarrierSBEndBB
1147
1.14M
    0U, // TAILJMPd
1148
1.14M
    0U, // TAILJMPr
1149
1.14M
    0U, // TAILJMPr4
1150
1.14M
    0U, // TCRETURNdi
1151
1.14M
    0U, // TCRETURNri
1152
1.14M
    0U, // TPsoft
1153
1.14M
    0U, // UMLALv5
1154
1.14M
    0U, // UMULLv5
1155
1.14M
    567556U,  // VLD1LNdAsm_16
1156
1.14M
    1091844U, // VLD1LNdAsm_32
1157
1.14M
    1616132U, // VLD1LNdAsm_8
1158
1.14M
    567556U,  // VLD1LNdWB_fixed_Asm_16
1159
1.14M
    1091844U, // VLD1LNdWB_fixed_Asm_32
1160
1.14M
    1616132U, // VLD1LNdWB_fixed_Asm_8
1161
1.14M
    575748U,  // VLD1LNdWB_register_Asm_16
1162
1.14M
    1100036U, // VLD1LNdWB_register_Asm_32
1163
1.14M
    1624324U, // VLD1LNdWB_register_Asm_8
1164
1.14M
    567605U,  // VLD2LNdAsm_16
1165
1.14M
    1091893U, // VLD2LNdAsm_32
1166
1.14M
    1616181U, // VLD2LNdAsm_8
1167
1.14M
    567605U,  // VLD2LNdWB_fixed_Asm_16
1168
1.14M
    1091893U, // VLD2LNdWB_fixed_Asm_32
1169
1.14M
    1616181U, // VLD2LNdWB_fixed_Asm_8
1170
1.14M
    575797U,  // VLD2LNdWB_register_Asm_16
1171
1.14M
    1100085U, // VLD2LNdWB_register_Asm_32
1172
1.14M
    1624373U, // VLD2LNdWB_register_Asm_8
1173
1.14M
    567605U,  // VLD2LNqAsm_16
1174
1.14M
    1091893U, // VLD2LNqAsm_32
1175
1.14M
    567605U,  // VLD2LNqWB_fixed_Asm_16
1176
1.14M
    1091893U, // VLD2LNqWB_fixed_Asm_32
1177
1.14M
    575797U,  // VLD2LNqWB_register_Asm_16
1178
1.14M
    1100085U, // VLD2LNqWB_register_Asm_32
1179
1.14M
    134801754U, // VLD3DUPdAsm_16
1180
1.14M
    135326042U, // VLD3DUPdAsm_32
1181
1.14M
    135850330U, // VLD3DUPdAsm_8
1182
1.14M
    134801754U, // VLD3DUPdWB_fixed_Asm_16
1183
1.14M
    135326042U, // VLD3DUPdWB_fixed_Asm_32
1184
1.14M
    135850330U, // VLD3DUPdWB_fixed_Asm_8
1185
1.14M
    134785370U, // VLD3DUPdWB_register_Asm_16
1186
1.14M
    135309658U, // VLD3DUPdWB_register_Asm_32
1187
1.14M
    135833946U, // VLD3DUPdWB_register_Asm_8
1188
1.14M
    201910618U, // VLD3DUPqAsm_16
1189
1.14M
    202434906U, // VLD3DUPqAsm_32
1190
1.14M
    202959194U, // VLD3DUPqAsm_8
1191
1.14M
    201910618U, // VLD3DUPqWB_fixed_Asm_16
1192
1.14M
    202434906U, // VLD3DUPqWB_fixed_Asm_32
1193
1.14M
    202959194U, // VLD3DUPqWB_fixed_Asm_8
1194
1.14M
    201894234U, // VLD3DUPqWB_register_Asm_16
1195
1.14M
    202418522U, // VLD3DUPqWB_register_Asm_32
1196
1.14M
    202942810U, // VLD3DUPqWB_register_Asm_8
1197
1.14M
    567642U,  // VLD3LNdAsm_16
1198
1.14M
    1091930U, // VLD3LNdAsm_32
1199
1.14M
    1616218U, // VLD3LNdAsm_8
1200
1.14M
    567642U,  // VLD3LNdWB_fixed_Asm_16
1201
1.14M
    1091930U, // VLD3LNdWB_fixed_Asm_32
1202
1.14M
    1616218U, // VLD3LNdWB_fixed_Asm_8
1203
1.14M
    575834U,  // VLD3LNdWB_register_Asm_16
1204
1.14M
    1100122U, // VLD3LNdWB_register_Asm_32
1205
1.14M
    1624410U, // VLD3LNdWB_register_Asm_8
1206
1.14M
    567642U,  // VLD3LNqAsm_16
1207
1.14M
    1091930U, // VLD3LNqAsm_32
1208
1.14M
    567642U,  // VLD3LNqWB_fixed_Asm_16
1209
1.14M
    1091930U, // VLD3LNqWB_fixed_Asm_32
1210
1.14M
    575834U,  // VLD3LNqWB_register_Asm_16
1211
1.14M
    1100122U, // VLD3LNqWB_register_Asm_32
1212
1.14M
    269019482U, // VLD3dAsm_16
1213
1.14M
    269543770U, // VLD3dAsm_32
1214
1.14M
    270068058U, // VLD3dAsm_8
1215
1.14M
    269019482U, // VLD3dWB_fixed_Asm_16
1216
1.14M
    269543770U, // VLD3dWB_fixed_Asm_32
1217
1.14M
    270068058U, // VLD3dWB_fixed_Asm_8
1218
1.14M
    269003098U, // VLD3dWB_register_Asm_16
1219
1.14M
    269527386U, // VLD3dWB_register_Asm_32
1220
1.14M
    270051674U, // VLD3dWB_register_Asm_8
1221
1.14M
    336128346U, // VLD3qAsm_16
1222
1.14M
    336652634U, // VLD3qAsm_32
1223
1.14M
    337176922U, // VLD3qAsm_8
1224
1.14M
    336128346U, // VLD3qWB_fixed_Asm_16
1225
1.14M
    336652634U, // VLD3qWB_fixed_Asm_32
1226
1.14M
    337176922U, // VLD3qWB_fixed_Asm_8
1227
1.14M
    336111962U, // VLD3qWB_register_Asm_16
1228
1.14M
    336636250U, // VLD3qWB_register_Asm_32
1229
1.14M
    337160538U, // VLD3qWB_register_Asm_8
1230
1.14M
    403237238U, // VLD4DUPdAsm_16
1231
1.14M
    403761526U, // VLD4DUPdAsm_32
1232
1.14M
    404285814U, // VLD4DUPdAsm_8
1233
1.14M
    403237238U, // VLD4DUPdWB_fixed_Asm_16
1234
1.14M
    403761526U, // VLD4DUPdWB_fixed_Asm_32
1235
1.14M
    404285814U, // VLD4DUPdWB_fixed_Asm_8
1236
1.14M
    403220854U, // VLD4DUPdWB_register_Asm_16
1237
1.14M
    403745142U, // VLD4DUPdWB_register_Asm_32
1238
1.14M
    404269430U, // VLD4DUPdWB_register_Asm_8
1239
1.14M
    470346102U, // VLD4DUPqAsm_16
1240
1.14M
    470870390U, // VLD4DUPqAsm_32
1241
1.14M
    471394678U, // VLD4DUPqAsm_8
1242
1.14M
    470346102U, // VLD4DUPqWB_fixed_Asm_16
1243
1.14M
    470870390U, // VLD4DUPqWB_fixed_Asm_32
1244
1.14M
    471394678U, // VLD4DUPqWB_fixed_Asm_8
1245
1.14M
    470329718U, // VLD4DUPqWB_register_Asm_16
1246
1.14M
    470854006U, // VLD4DUPqWB_register_Asm_32
1247
1.14M
    471378294U, // VLD4DUPqWB_register_Asm_8
1248
1.14M
    567670U,  // VLD4LNdAsm_16
1249
1.14M
    1091958U, // VLD4LNdAsm_32
1250
1.14M
    1616246U, // VLD4LNdAsm_8
1251
1.14M
    567670U,  // VLD4LNdWB_fixed_Asm_16
1252
1.14M
    1091958U, // VLD4LNdWB_fixed_Asm_32
1253
1.14M
    1616246U, // VLD4LNdWB_fixed_Asm_8
1254
1.14M
    575862U,  // VLD4LNdWB_register_Asm_16
1255
1.14M
    1100150U, // VLD4LNdWB_register_Asm_32
1256
1.14M
    1624438U, // VLD4LNdWB_register_Asm_8
1257
1.14M
    567670U,  // VLD4LNqAsm_16
1258
1.14M
    1091958U, // VLD4LNqAsm_32
1259
1.14M
    567670U,  // VLD4LNqWB_fixed_Asm_16
1260
1.14M
    1091958U, // VLD4LNqWB_fixed_Asm_32
1261
1.14M
    575862U,  // VLD4LNqWB_register_Asm_16
1262
1.14M
    1100150U, // VLD4LNqWB_register_Asm_32
1263
1.14M
    537454966U, // VLD4dAsm_16
1264
1.14M
    537979254U, // VLD4dAsm_32
1265
1.14M
    538503542U, // VLD4dAsm_8
1266
1.14M
    537454966U, // VLD4dWB_fixed_Asm_16
1267
1.14M
    537979254U, // VLD4dWB_fixed_Asm_32
1268
1.14M
    538503542U, // VLD4dWB_fixed_Asm_8
1269
1.14M
    537438582U, // VLD4dWB_register_Asm_16
1270
1.14M
    537962870U, // VLD4dWB_register_Asm_32
1271
1.14M
    538487158U, // VLD4dWB_register_Asm_8
1272
1.14M
    604563830U, // VLD4qAsm_16
1273
1.14M
    605088118U, // VLD4qAsm_32
1274
1.14M
    605612406U, // VLD4qAsm_8
1275
1.14M
    604563830U, // VLD4qWB_fixed_Asm_16
1276
1.14M
    605088118U, // VLD4qWB_fixed_Asm_32
1277
1.14M
    605612406U, // VLD4qWB_fixed_Asm_8
1278
1.14M
    604547446U, // VLD4qWB_register_Asm_16
1279
1.14M
    605071734U, // VLD4qWB_register_Asm_32
1280
1.14M
    605596022U, // VLD4qWB_register_Asm_8
1281
1.14M
    0U, // VMOVD0
1282
1.14M
    0U, // VMOVDcc
1283
1.14M
    0U, // VMOVHcc
1284
1.14M
    0U, // VMOVQ0
1285
1.14M
    0U, // VMOVScc
1286
1.14M
    567567U,  // VST1LNdAsm_16
1287
1.14M
    1091855U, // VST1LNdAsm_32
1288
1.14M
    1616143U, // VST1LNdAsm_8
1289
1.14M
    567567U,  // VST1LNdWB_fixed_Asm_16
1290
1.14M
    1091855U, // VST1LNdWB_fixed_Asm_32
1291
1.14M
    1616143U, // VST1LNdWB_fixed_Asm_8
1292
1.14M
    575759U,  // VST1LNdWB_register_Asm_16
1293
1.14M
    1100047U, // VST1LNdWB_register_Asm_32
1294
1.14M
    1624335U, // VST1LNdWB_register_Asm_8
1295
1.14M
    567632U,  // VST2LNdAsm_16
1296
1.14M
    1091920U, // VST2LNdAsm_32
1297
1.14M
    1616208U, // VST2LNdAsm_8
1298
1.14M
    567632U,  // VST2LNdWB_fixed_Asm_16
1299
1.14M
    1091920U, // VST2LNdWB_fixed_Asm_32
1300
1.14M
    1616208U, // VST2LNdWB_fixed_Asm_8
1301
1.14M
    575824U,  // VST2LNdWB_register_Asm_16
1302
1.14M
    1100112U, // VST2LNdWB_register_Asm_32
1303
1.14M
    1624400U, // VST2LNdWB_register_Asm_8
1304
1.14M
    567632U,  // VST2LNqAsm_16
1305
1.14M
    1091920U, // VST2LNqAsm_32
1306
1.14M
    567632U,  // VST2LNqWB_fixed_Asm_16
1307
1.14M
    1091920U, // VST2LNqWB_fixed_Asm_32
1308
1.14M
    575824U,  // VST2LNqWB_register_Asm_16
1309
1.14M
    1100112U, // VST2LNqWB_register_Asm_32
1310
1.14M
    567653U,  // VST3LNdAsm_16
1311
1.14M
    1091941U, // VST3LNdAsm_32
1312
1.14M
    1616229U, // VST3LNdAsm_8
1313
1.14M
    567653U,  // VST3LNdWB_fixed_Asm_16
1314
1.14M
    1091941U, // VST3LNdWB_fixed_Asm_32
1315
1.14M
    1616229U, // VST3LNdWB_fixed_Asm_8
1316
1.14M
    575845U,  // VST3LNdWB_register_Asm_16
1317
1.14M
    1100133U, // VST3LNdWB_register_Asm_32
1318
1.14M
    1624421U, // VST3LNdWB_register_Asm_8
1319
1.14M
    567653U,  // VST3LNqAsm_16
1320
1.14M
    1091941U, // VST3LNqAsm_32
1321
1.14M
    567653U,  // VST3LNqWB_fixed_Asm_16
1322
1.14M
    1091941U, // VST3LNqWB_fixed_Asm_32
1323
1.14M
    575845U,  // VST3LNqWB_register_Asm_16
1324
1.14M
    1100133U, // VST3LNqWB_register_Asm_32
1325
1.14M
    269019493U, // VST3dAsm_16
1326
1.14M
    269543781U, // VST3dAsm_32
1327
1.14M
    270068069U, // VST3dAsm_8
1328
1.14M
    269019493U, // VST3dWB_fixed_Asm_16
1329
1.14M
    269543781U, // VST3dWB_fixed_Asm_32
1330
1.14M
    270068069U, // VST3dWB_fixed_Asm_8
1331
1.14M
    269003109U, // VST3dWB_register_Asm_16
1332
1.14M
    269527397U, // VST3dWB_register_Asm_32
1333
1.14M
    270051685U, // VST3dWB_register_Asm_8
1334
1.14M
    336128357U, // VST3qAsm_16
1335
1.14M
    336652645U, // VST3qAsm_32
1336
1.14M
    337176933U, // VST3qAsm_8
1337
1.14M
    336128357U, // VST3qWB_fixed_Asm_16
1338
1.14M
    336652645U, // VST3qWB_fixed_Asm_32
1339
1.14M
    337176933U, // VST3qWB_fixed_Asm_8
1340
1.14M
    336111973U, // VST3qWB_register_Asm_16
1341
1.14M
    336636261U, // VST3qWB_register_Asm_32
1342
1.14M
    337160549U, // VST3qWB_register_Asm_8
1343
1.14M
    567675U,  // VST4LNdAsm_16
1344
1.14M
    1091963U, // VST4LNdAsm_32
1345
1.14M
    1616251U, // VST4LNdAsm_8
1346
1.14M
    567675U,  // VST4LNdWB_fixed_Asm_16
1347
1.14M
    1091963U, // VST4LNdWB_fixed_Asm_32
1348
1.14M
    1616251U, // VST4LNdWB_fixed_Asm_8
1349
1.14M
    575867U,  // VST4LNdWB_register_Asm_16
1350
1.14M
    1100155U, // VST4LNdWB_register_Asm_32
1351
1.14M
    1624443U, // VST4LNdWB_register_Asm_8
1352
1.14M
    567675U,  // VST4LNqAsm_16
1353
1.14M
    1091963U, // VST4LNqAsm_32
1354
1.14M
    567675U,  // VST4LNqWB_fixed_Asm_16
1355
1.14M
    1091963U, // VST4LNqWB_fixed_Asm_32
1356
1.14M
    575867U,  // VST4LNqWB_register_Asm_16
1357
1.14M
    1100155U, // VST4LNqWB_register_Asm_32
1358
1.14M
    537454971U, // VST4dAsm_16
1359
1.14M
    537979259U, // VST4dAsm_32
1360
1.14M
    538503547U, // VST4dAsm_8
1361
1.14M
    537454971U, // VST4dWB_fixed_Asm_16
1362
1.14M
    537979259U, // VST4dWB_fixed_Asm_32
1363
1.14M
    538503547U, // VST4dWB_fixed_Asm_8
1364
1.14M
    537438587U, // VST4dWB_register_Asm_16
1365
1.14M
    537962875U, // VST4dWB_register_Asm_32
1366
1.14M
    538487163U, // VST4dWB_register_Asm_8
1367
1.14M
    604563835U, // VST4qAsm_16
1368
1.14M
    605088123U, // VST4qAsm_32
1369
1.14M
    605612411U, // VST4qAsm_8
1370
1.14M
    604563835U, // VST4qWB_fixed_Asm_16
1371
1.14M
    605088123U, // VST4qWB_fixed_Asm_32
1372
1.14M
    605612411U, // VST4qWB_fixed_Asm_8
1373
1.14M
    604547451U, // VST4qWB_register_Asm_16
1374
1.14M
    605071739U, // VST4qWB_register_Asm_32
1375
1.14M
    605596027U, // VST4qWB_register_Asm_8
1376
1.14M
    0U, // WIN__CHKSTK
1377
1.14M
    0U, // WIN__DBZCHK
1378
1.14M
    0U, // t2ABS
1379
1.14M
    0U, // t2ADDSri
1380
1.14M
    0U, // t2ADDSrr
1381
1.14M
    0U, // t2ADDSrs
1382
1.14M
    0U, // t2BF_LabelPseudo
1383
1.14M
    0U, // t2BR_JT
1384
1.14M
    0U, // t2CALL_BTI
1385
1.14M
    0U, // t2DoLoopStart
1386
1.14M
    0U, // t2DoLoopStartTP
1387
1.14M
    0U, // t2LDMIA_RET
1388
1.14M
    673246330U, // t2LDRB_OFFSET_imm
1389
1.14M
    740355194U, // t2LDRB_POST_imm
1390
1.14M
    807464058U, // t2LDRB_PRE_imm
1391
1.14M
    27770U, // t2LDRBpcrel
1392
1.14M
    29094U, // t2LDRConstPool
1393
1.14M
    673246848U, // t2LDRH_OFFSET_imm
1394
1.14M
    740355712U, // t2LDRH_POST_imm
1395
1.14M
    807464576U, // t2LDRH_PRE_imm
1396
1.14M
    28288U, // t2LDRHpcrel
1397
1.14M
    0U, // t2LDRLIT_ga_pcrel
1398
1.14M
    673246349U, // t2LDRSB_OFFSET_imm
1399
1.14M
    740355213U, // t2LDRSB_POST_imm
1400
1.14M
    807464077U, // t2LDRSB_PRE_imm
1401
1.14M
    27789U, // t2LDRSBpcrel
1402
1.14M
    673246887U, // t2LDRSH_OFFSET_imm
1403
1.14M
    740355751U, // t2LDRSH_POST_imm
1404
1.14M
    807464615U, // t2LDRSH_PRE_imm
1405
1.14M
    28327U, // t2LDRSHpcrel
1406
1.14M
    740356518U, // t2LDR_POST_imm
1407
1.14M
    807465382U, // t2LDR_PRE_imm
1408
1.14M
    0U, // t2LDRpci_pic
1409
1.14M
    29094U, // t2LDRpcrel
1410
1.14M
    0U, // t2LEApcrel
1411
1.14M
    0U, // t2LEApcrelJT
1412
1.14M
    0U, // t2LoopDec
1413
1.14M
    0U, // t2LoopEnd
1414
1.14M
    0U, // t2LoopEndDec
1415
1.14M
    0U, // t2MOVCCasr
1416
1.14M
    0U, // t2MOVCCi
1417
1.14M
    0U, // t2MOVCCi16
1418
1.14M
    0U, // t2MOVCCi32imm
1419
1.14M
    0U, // t2MOVCClsl
1420
1.14M
    0U, // t2MOVCClsr
1421
1.14M
    0U, // t2MOVCCr
1422
1.14M
    0U, // t2MOVCCror
1423
1.14M
    62064U, // t2MOVSsi
1424
1.14M
    45680U, // t2MOVSsr
1425
1.14M
    0U, // t2MOVTi16_ga_pcrel
1426
1.14M
    0U, // t2MOV_ga_pcrel
1427
1.14M
    0U, // t2MOVi16_ga_pcrel
1428
1.14M
    0U, // t2MOVi32imm
1429
1.14M
    62539U, // t2MOVsi
1430
1.14M
    46155U, // t2MOVsr
1431
1.14M
    0U, // t2MVNCCi
1432
1.14M
    0U, // t2RSBSri
1433
1.14M
    0U, // t2RSBSrs
1434
1.14M
    673246336U, // t2STRB_OFFSET_imm
1435
1.14M
    740355200U, // t2STRB_POST_imm
1436
1.14M
    807464064U, // t2STRB_PRE_imm
1437
1.14M
    0U, // t2STRB_preidx
1438
1.14M
    673246854U, // t2STRH_OFFSET_imm
1439
1.14M
    740355718U, // t2STRH_POST_imm
1440
1.14M
    807464582U, // t2STRH_PRE_imm
1441
1.14M
    0U, // t2STRH_preidx
1442
1.14M
    740356608U, // t2STR_POST_imm
1443
1.14M
    807465472U, // t2STR_PRE_imm
1444
1.14M
    0U, // t2STR_preidx
1445
1.14M
    0U, // t2SUBSri
1446
1.14M
    0U, // t2SUBSrr
1447
1.14M
    0U, // t2SUBSrs
1448
1.14M
    0U, // t2SpeculationBarrierISBDSBEndBB
1449
1.14M
    0U, // t2SpeculationBarrierSBEndBB
1450
1.14M
    0U, // t2TBB_JT
1451
1.14M
    0U, // t2TBH_JT
1452
1.14M
    0U, // t2WhileLoopSetup
1453
1.14M
    0U, // t2WhileLoopStart
1454
1.14M
    0U, // t2WhileLoopStartLR
1455
1.14M
    0U, // t2WhileLoopStartTP
1456
1.14M
    0U, // tADCS
1457
1.14M
    0U, // tADDSi3
1458
1.14M
    0U, // tADDSi8
1459
1.14M
    0U, // tADDSrr
1460
1.14M
    0U, // tADDframe
1461
1.14M
    0U, // tADJCALLSTACKDOWN
1462
1.14M
    0U, // tADJCALLSTACKUP
1463
1.14M
    0U, // tBLXNS_CALL
1464
1.14M
    0U, // tBLXr_noip
1465
1.14M
    0U, // tBL_PUSHLR
1466
1.14M
    0U, // tBRIND
1467
1.14M
    0U, // tBR_JTr
1468
1.14M
    0U, // tBXNS_RET
1469
1.14M
    0U, // tBX_CALL
1470
1.14M
    0U, // tBX_RET
1471
1.14M
    0U, // tBX_RET_vararg
1472
1.14M
    0U, // tBfar
1473
1.14M
    0U, // tCMP_SWAP_16
1474
1.14M
    0U, // tCMP_SWAP_32
1475
1.14M
    0U, // tCMP_SWAP_8
1476
1.14M
    0U, // tLDMIA_UPD
1477
1.14M
    29094U, // tLDRConstPool
1478
1.14M
    0U, // tLDRLIT_ga_abs
1479
1.14M
    0U, // tLDRLIT_ga_pcrel
1480
1.14M
    0U, // tLDR_postidx
1481
1.14M
    0U, // tLDRpci_pic
1482
1.14M
    0U, // tLEApcrel
1483
1.14M
    0U, // tLEApcrelJT
1484
1.14M
    0U, // tLSLSri
1485
1.14M
    0U, // tMOVCCr_pseudo
1486
1.14M
    0U, // tMOVi32imm
1487
1.14M
    0U, // tPOP_RET
1488
1.14M
    0U, // tRSBS
1489
1.14M
    0U, // tSBCS
1490
1.14M
    0U, // tSUBSi3
1491
1.14M
    0U, // tSUBSi8
1492
1.14M
    0U, // tSUBSrr
1493
1.14M
    0U, // tTAILJMPd
1494
1.14M
    0U, // tTAILJMPdND
1495
1.14M
    0U, // tTAILJMPr
1496
1.14M
    0U, // tTBB_JT
1497
1.14M
    0U, // tTBH_JT
1498
1.14M
    0U, // tTPsoft
1499
1.14M
    2632970U, // ADCri
1500
1.14M
    2632970U, // ADCrr
1501
1.14M
    2690314U, // ADCrsi
1502
1.14M
    77066U, // ADCrsr
1503
1.14M
    2633038U, // ADDri
1504
1.14M
    2633038U, // ADDrr
1505
1.14M
    2690382U, // ADDrsi
1506
1.14M
    77134U, // ADDrsr
1507
1.14M
    2650529U, // ADR
1508
1.14M
    875644520U, // AESD
1509
1.14M
    875644528U, // AESE
1510
1.14M
    942753365U, // AESIMC
1511
1.14M
    942753375U, // AESMC
1512
1.14M
    2633103U, // ANDri
1513
1.14M
    2633103U, // ANDrr
1514
1.14M
    2690447U, // ANDrsi
1515
1.14M
    77199U, // ANDrsr
1516
1.14M
    1010394590U,  // BF16VDOTI_VDOTD
1517
1.14M
    1010394590U,  // BF16VDOTI_VDOTQ
1518
1.14M
    1010394590U,  // BF16VDOTS_VDOTD
1519
1.14M
    1010394590U,  // BF16VDOTS_VDOTQ
1520
1.14M
    943748008U, // BF16_VCVT
1521
1.14M
    876670131U, // BF16_VCVTB
1522
1.14M
    876671894U, // BF16_VCVTT
1523
1.14M
    2682130U, // BFC
1524
1.14M
    2666240U, // BFI
1525
1.14M
    2632983U, // BICri
1526
1.14M
    2632983U, // BICrr
1527
1.14M
    2690327U, // BICrsi
1528
1.14M
    77079U, // BICrsr
1529
1.14M
    4802500U, // BKPT
1530
1.14M
    4818832U, // BL
1531
1.14M
    4802554U, // BLX
1532
1.14M
    2733469U, // BLX_pred
1533
1.14M
    4818938U, // BLXi
1534
1.14M
    1076473681U,  // BL_pred
1535
1.14M
    4802550U, // BX
1536
1.14M
    2731794U, // BXJ
1537
1.14M
    5362935U, // BX_RET
1538
1.14M
    2733303U, // BX_pred
1539
1.14M
    1076472756U,  // Bcc
1540
1.14M
    878305282U, // CDE_CX1
1541
1.14M
    1143515832U,  // CDE_CX1A
1542
1.14M
    1214375736U,  // CDE_CX1D
1543
1.14M
    1143515854U,  // CDE_CX1DA
1544
1.14M
    878305875U, // CDE_CX2
1545
1.14M
    1143524030U,  // CDE_CX2A
1546
1.14M
    1281484606U,  // CDE_CX2D
1547
1.14M
    1143524052U,  // CDE_CX2DA
1548
1.14M
    878305881U, // CDE_CX3
1549
1.14M
    1143605956U,  // CDE_CX3A
1550
1.14M
    1281484612U,  // CDE_CX3D
1551
1.14M
    1143605978U,  // CDE_CX3DA
1552
1.14M
    1012524758U,  // CDE_VCX1A_fpdp
1553
1.14M
    1012524758U,  // CDE_VCX1A_fpsp
1554
1.14M
    1143614135U,  // CDE_VCX1A_vec
1555
1.14M
    878305281U, // CDE_VCX1_fpdp
1556
1.14M
    878305281U, // CDE_VCX1_fpsp
1557
1.14M
    1143621908U,  // CDE_VCX1_vec
1558
1.14M
    1012524765U,  // CDE_VCX2A_fpdp
1559
1.14M
    1012524765U,  // CDE_VCX2A_fpsp
1560
1.14M
    1143630525U,  // CDE_VCX2A_vec
1561
1.14M
    878305874U, // CDE_VCX2_fpdp
1562
1.14M
    878305874U, // CDE_VCX2_fpsp
1563
1.14M
    1143613781U,  // CDE_VCX2_vec
1564
1.14M
    1012524772U,  // CDE_VCX3A_fpdp
1565
1.14M
    1012524772U,  // CDE_VCX3A_fpsp
1566
1.14M
    1143638723U,  // CDE_VCX3A_vec
1567
1.14M
    878305880U, // CDE_VCX3_fpdp
1568
1.14M
    878305880U, // CDE_VCX3_fpsp
1569
1.14M
    1143630186U,  // CDE_VCX3_vec
1570
1.14M
    1344934152U,  // CDP
1571
1.14M
    1416274495U,  // CDP2
1572
1.14M
    5445U,  // CLREX
1573
1.14M
    2651636U, // CLZ
1574
1.14M
    2650273U, // CMNri
1575
1.14M
    2650273U, // CMNzrr
1576
1.14M
    2683041U, // CMNzrsi
1577
1.14M
    2666657U, // CMNzrsr
1578
1.14M
    2650386U, // CMPri
1579
1.14M
    2650386U, // CMPrr
1580
1.14M
    2683154U, // CMPrsi
1581
1.14M
    2666770U, // CMPrsr
1582
1.14M
    4802484U, // CPS1p
1583
1.14M
    1479201365U,  // CPS2p
1584
1.14M
    1479201365U,  // CPS3p
1585
1.14M
    942753529U, // CRC32B
1586
1.14M
    942753537U, // CRC32CB
1587
1.14M
    942753647U, // CRC32CH
1588
1.14M
    942753767U, // CRC32CW
1589
1.14M
    942753639U, // CRC32H
1590
1.14M
    942753759U, // CRC32W
1591
1.14M
    2731508U, // DBG
1592
1.14M
    190232U,  // DMB
1593
1.14M
    190237U,  // DSB
1594
1.14M
    2634192U, // EORri
1595
1.14M
    2634192U, // EORrr
1596
1.14M
    2691536U, // EORrsi
1597
1.14M
    78288U, // EORrsr
1598
1.14M
    4838067U, // ERET
1599
1.14M
    1282438218U,  // FCONSTD
1600
1.14M
    7894090U, // FCONSTH
1601
1.14M
    8418378U, // FCONSTS
1602
1.14M
    942175474U, // FLDMXDB_UPD
1603
1.14M
    2733201U, // FLDMXIA
1604
1.14M
    942175377U, // FLDMXIA_UPD
1605
1.14M
    9032281U, // FMSTAT
1606
1.14M
    942175482U, // FSTMXDB_UPD
1607
1.14M
    2733209U, // FSTMXIA
1608
1.14M
    942175385U, // FSTMXIA_UPD
1609
1.14M
    2732808U, // HINT
1610
1.14M
    4802495U, // HLT
1611
1.14M
    4802355U, // HVC
1612
1.14M
    198434U,  // ISB
1613
1.14M
    2648800U, // LDA
1614
1.14M
    2649009U, // LDAB
1615
1.14M
    2651443U, // LDAEX
1616
1.14M
    2649320U, // LDAEXB
1617
1.14M
    1546153387U,  // LDAEXD
1618
1.14M
    2649816U, // LDAEXH
1619
1.14M
    2649616U, // LDAH
1620
1.14M
    1620223874U,  // LDC2L_OFFSET
1621
1.14M
    1687332738U,  // LDC2L_OPTION
1622
1.14M
    1687332738U,  // LDC2L_POST
1623
1.14M
    1754441602U,  // LDC2L_PRE
1624
1.14M
    1620222502U,  // LDC2_OFFSET
1625
1.14M
    1687331366U,  // LDC2_OPTION
1626
1.14M
    1687331366U,  // LDC2_POST
1627
1.14M
    1754440230U,  // LDC2_PRE
1628
1.14M
    1344843610U,  // LDCL_OFFSET
1629
1.14M
    1344843610U,  // LDCL_OPTION
1630
1.14M
    1344843610U,  // LDCL_POST
1631
1.14M
    1344843610U,  // LDCL_PRE
1632
1.14M
    1344843022U,  // LDC_OFFSET
1633
1.14M
    1344843022U,  // LDC_OPTION
1634
1.14M
    1344843022U,  // LDC_POST
1635
1.14M
    1344843022U,  // LDC_PRE
1636
1.14M
    2730724U, // LDMDA
1637
1.14M
    942172900U, // LDMDA_UPD
1638
1.14M
    2730979U, // LDMDB
1639
1.14M
    942173155U, // LDMDB_UPD
1640
1.14M
    2732107U, // LDMIA
1641
1.14M
    942174283U, // LDMIA_UPD
1642
1.14M
    2730998U, // LDMIB
1643
1.14M
    942173174U, // LDMIB_UPD
1644
1.14M
    2675360U, // LDRBT_POST_IMM
1645
1.14M
    2675360U, // LDRBT_POST_REG
1646
1.14M
    2673786U, // LDRB_POST_IMM
1647
1.14M
    2673786U, // LDRB_POST_REG
1648
1.14M
    2665594U, // LDRB_PRE_IMM
1649
1.14M
    2673786U, // LDRB_PRE_REG
1650
1.14M
    2681978U, // LDRBi12
1651
1.14M
    2665594U, // LDRBrs
1652
1.14M
    2674068U, // LDRD
1653
1.14M
    2755988U, // LDRD_POST
1654
1.14M
    2755988U, // LDRD_PRE
1655
1.14M
    2651455U, // LDREX
1656
1.14M
    2649334U, // LDREXB
1657
1.14M
    1546153401U,  // LDREXD
1658
1.14M
    2649830U, // LDREXH
1659
1.14M
    2666112U, // LDRH
1660
1.14M
    2667203U, // LDRHTi
1661
1.14M
    2675395U, // LDRHTr
1662
1.14M
    2674304U, // LDRH_POST
1663
1.14M
    2674304U, // LDRH_PRE
1664
1.14M
    2665613U, // LDRSB
1665
1.14M
    2667180U, // LDRSBTi
1666
1.14M
    2675372U, // LDRSBTr
1667
1.14M
    2673805U, // LDRSB_POST
1668
1.14M
    2673805U, // LDRSB_PRE
1669
1.14M
    2666151U, // LDRSH
1670
1.14M
    2667215U, // LDRSHTi
1671
1.14M
    2675407U, // LDRSHTr
1672
1.14M
    2674343U, // LDRSH_POST
1673
1.14M
    2674343U, // LDRSH_PRE
1674
1.14M
    2675554U, // LDRT_POST_IMM
1675
1.14M
    2675554U, // LDRT_POST_REG
1676
1.14M
    2675110U, // LDR_POST_IMM
1677
1.14M
    2675110U, // LDR_POST_REG
1678
1.14M
    2666918U, // LDR_PRE_IMM
1679
1.14M
    2675110U, // LDR_PRE_REG
1680
1.14M
    2683302U, // LDRcp
1681
1.14M
    2683302U, // LDRi12
1682
1.14M
    2666918U, // LDRrs
1683
1.14M
    1344934301U,  // MCR
1684
1.14M
    879403589U, // MCR2
1685
1.14M
    1344852440U,  // MCRR
1686
1.14M
    879403595U, // MCRR2
1687
1.14M
    2689828U, // MLA
1688
1.14M
    2667053U, // MLS
1689
1.14M
    10081355U,  // MOVPCLR
1690
1.14M
    2683821U, // MOVTi16
1691
1.14M
    2659403U, // MOVi
1692
1.14M
    2651250U, // MOVi16
1693
1.14M
    2659403U, // MOVr
1694
1.14M
    2659403U, // MOVr_TC
1695
1.14M
    2634827U, // MOVsi
1696
1.14M
    2692171U, // MOVsr
1697
1.14M
    1143606565U,  // MRC
1698
1.14M
    3793452U, // MRC2
1699
1.14M
    1814613289U,  // MRRC
1700
1.14M
    205362U,  // MRRC2
1701
1.14M
    2732634U, // MRS
1702
1.14M
    2650714U, // MRSbanked
1703
1.14M
    2732634U, // MRSsys
1704
1.14M
    1881698798U,  // MSR
1705
1.14M
    1948807662U,  // MSRbanked
1706
1.14M
    1881698798U,  // MSRi
1707
1.14M
    2633774U, // MUL
1708
1.14M
    2674699U, // MVE_ASRLi
1709
1.14M
    2674699U, // MVE_ASRLr
1710
1.14M
    942752741U, // MVE_DLSTP_16
1711
1.14M
    942751988U, // MVE_DLSTP_32
1712
1.14M
    942752350U, // MVE_DLSTP_64
1713
1.14M
    942753400U, // MVE_DLSTP_8
1714
1.14M
    1210700109U,  // MVE_LCTP
1715
1.14M
    10577828U,  // MVE_LETP
1716
1.14M
    2674646U, // MVE_LSLLi
1717
1.14M
    2674646U, // MVE_LSLLr
1718
1.14M
    2674704U, // MVE_LSRL
1719
1.14M
    942207402U, // MVE_SQRSHR
1720
1.14M
    2756597U, // MVE_SQRSHRL
1721
1.14M
    942206849U, // MVE_SQSHL
1722
1.14M
    2674618U, // MVE_SQSHLL
1723
1.14M
    942207409U, // MVE_SRSHR
1724
1.14M
    2674685U, // MVE_SRSHRL
1725
1.14M
    942206867U, // MVE_UQRSHL
1726
1.14M
    2756552U, // MVE_UQRSHLL
1727
1.14M
    942206855U, // MVE_UQSHL
1728
1.14M
    2674625U, // MVE_UQSHLL
1729
1.14M
    942207415U, // MVE_URSHR
1730
1.14M
    2674692U, // MVE_URSHRL
1731
1.14M
    11154380U,  // MVE_VABAVs16
1732
1.14M
    11678668U,  // MVE_VABAVs32
1733
1.14M
    12202956U,  // MVE_VABAVs8
1734
1.14M
    12727244U,  // MVE_VABAVu16
1735
1.14M
    13251532U,  // MVE_VABAVu32
1736
1.14M
    13775820U,  // MVE_VABAVu8
1737
1.14M
    8015174U, // MVE_VABDf16
1738
1.14M
    8539462U, // MVE_VABDf32
1739
1.14M
    11160902U,  // MVE_VABDs16
1740
1.14M
    11685190U,  // MVE_VABDs32
1741
1.14M
    12209478U,  // MVE_VABDs8
1742
1.14M
    12733766U,  // MVE_VABDu16
1743
1.14M
    13258054U,  // MVE_VABDu32
1744
1.14M
    13782342U,  // MVE_VABDu8
1745
1.14M
    8081948U, // MVE_VABSf16
1746
1.14M
    8606236U, // MVE_VABSf32
1747
1.14M
    11227676U,  // MVE_VABSs16
1748
1.14M
    11751964U,  // MVE_VABSs32
1749
1.14M
    12276252U,  // MVE_VABSs8
1750
1.14M
    14314761U,  // MVE_VADC
1751
1.14M
    14298874U,  // MVE_VADCI
1752
1.14M
    11692963U,  // MVE_VADDLVs32acc
1753
1.14M
    11686957U,  // MVE_VADDLVs32no_acc
1754
1.14M
    13265827U,  // MVE_VADDLVu32acc
1755
1.14M
    13259821U,  // MVE_VADDLVu32no_acc
1756
1.14M
    11160476U,  // MVE_VADDVs16acc
1757
1.14M
    11228180U,  // MVE_VADDVs16no_acc
1758
1.14M
    11684764U,  // MVE_VADDVs32acc
1759
1.14M
    11752468U,  // MVE_VADDVs32no_acc
1760
1.14M
    12209052U,  // MVE_VADDVs8acc
1761
1.14M
    12276756U,  // MVE_VADDVs8no_acc
1762
1.14M
    12733340U,  // MVE_VADDVu16acc
1763
1.14M
    12801044U,  // MVE_VADDVu16no_acc
1764
1.14M
    13257628U,  // MVE_VADDVu32acc
1765
1.14M
    13325332U,  // MVE_VADDVu32no_acc
1766
1.14M
    13781916U,  // MVE_VADDVu8acc
1767
1.14M
    13849620U,  // MVE_VADDVu8no_acc
1768
1.14M
    8015223U, // MVE_VADD_qr_f16
1769
1.14M
    8539511U, // MVE_VADD_qr_f32
1770
1.14M
    14830967U,  // MVE_VADD_qr_i16
1771
1.14M
    14306679U,  // MVE_VADD_qr_i32
1772
1.14M
    15355255U,  // MVE_VADD_qr_i8
1773
1.14M
    8015223U, // MVE_VADDf16
1774
1.14M
    8539511U, // MVE_VADDf32
1775
1.14M
    14830967U,  // MVE_VADDi16
1776
1.14M
    14306679U,  // MVE_VADDi32
1777
1.14M
    15355255U,  // MVE_VADDi8
1778
1.14M
    2772366U, // MVE_VAND
1779
1.14M
    2772246U, // MVE_VBIC
1780
1.14M
    14830870U,  // MVE_VBICimmi16
1781
1.14M
    14306582U,  // MVE_VBICimmi32
1782
1.14M
    676338U,  // MVE_VBRSR16
1783
1.14M
    1200626U, // MVE_VBRSR32
1784
1.14M
    1724914U, // MVE_VBRSR8
1785
1.14M
    8006994U, // MVE_VCADDf16
1786
1.14M
    8531282U, // MVE_VCADDf32
1787
1.14M
    14822738U,  // MVE_VCADDi16
1788
1.14M
    14298450U,  // MVE_VCADDi32
1789
1.14M
    15347026U,  // MVE_VCADDi8
1790
1.14M
    11227686U,  // MVE_VCLSs16
1791
1.14M
    11751974U,  // MVE_VCLSs32
1792
1.14M
    12276262U,  // MVE_VCLSs8
1793
1.14M
    14898675U,  // MVE_VCLZs16
1794
1.14M
    14374387U,  // MVE_VCLZs32
1795
1.14M
    15422963U,  // MVE_VCLZs8
1796
1.14M
    8022818U, // MVE_VCMLAf16
1797
1.14M
    8547106U, // MVE_VCMLAf32
1798
1.14M
    2021273873U,  // MVE_VCMPf16
1799
1.14M
    2021273873U,  // MVE_VCMPf16r
1800
1.14M
    2021798161U,  // MVE_VCMPf32
1801
1.14M
    2021798161U,  // MVE_VCMPf32r
1802
1.14M
    2028089617U,  // MVE_VCMPi16
1803
1.14M
    2028089617U,  // MVE_VCMPi16r
1804
1.14M
    2027565329U,  // MVE_VCMPi32
1805
1.14M
    2027565329U,  // MVE_VCMPi32r
1806
1.14M
    2028613905U,  // MVE_VCMPi8
1807
1.14M
    2028613905U,  // MVE_VCMPi8r
1808
1.14M
    2024419601U,  // MVE_VCMPs16
1809
1.14M
    2024419601U,  // MVE_VCMPs16r
1810
1.14M
    2024943889U,  // MVE_VCMPs32
1811
1.14M
    2024943889U,  // MVE_VCMPs32r
1812
1.14M
    2025468177U,  // MVE_VCMPs8
1813
1.14M
    2025468177U,  // MVE_VCMPs8r
1814
1.14M
    2025992465U,  // MVE_VCMPu16
1815
1.14M
    2025992465U,  // MVE_VCMPu16r
1816
1.14M
    2026516753U,  // MVE_VCMPu32
1817
1.14M
    2026516753U,  // MVE_VCMPu32r
1818
1.14M
    2027041041U,  // MVE_VCMPu8
1819
1.14M
    2027041041U,  // MVE_VCMPu8r
1820
1.14M
    8007724U, // MVE_VCMULf16
1821
1.14M
    8532012U, // MVE_VCMULf32
1822
1.14M
    940265810U, // MVE_VCTP16
1823
1.14M
    940790098U, // MVE_VCTP32
1824
1.14M
    955470162U, // MVE_VCTP64
1825
1.14M
    941314386U, // MVE_VCTP8
1826
1.14M
    888818867U, // MVE_VCVTf16f32bh
1827
1.14M
    888820630U, // MVE_VCVTf16f32th
1828
1.14M
    1291998120U,  // MVE_VCVTf16s16_fix
1829
1.14M
    1224954792U,  // MVE_VCVTf16s16n
1830
1.14M
    1292522408U,  // MVE_VCVTf16u16_fix
1831
1.14M
    1225479080U,  // MVE_VCVTf16u16n
1832
1.14M
    18042035U,  // MVE_VCVTf32f16bh
1833
1.14M
    18043798U,  // MVE_VCVTf32f16th
1834
1.14M
    1293570984U,  // MVE_VCVTf32s32_fix
1835
1.14M
    1226527656U,  // MVE_VCVTf32s32n
1836
1.14M
    1294095272U,  // MVE_VCVTf32u32_fix
1837
1.14M
    1227051944U,  // MVE_VCVTf32u32n
1838
1.14M
    1294619560U,  // MVE_VCVTs16f16_fix
1839
1.14M
    1227574128U,  // MVE_VCVTs16f16a
1840
1.14M
    1227575410U,  // MVE_VCVTs16f16m
1841
1.14M
    1227575506U,  // MVE_VCVTs16f16n
1842
1.14M
    1227575646U,  // MVE_VCVTs16f16p
1843
1.14M
    1227576232U,  // MVE_VCVTs16f16z
1844
1.14M
    1295143848U,  // MVE_VCVTs32f32_fix
1845
1.14M
    1228098416U,  // MVE_VCVTs32f32a
1846
1.14M
    1228099698U,  // MVE_VCVTs32f32m
1847
1.14M
    1228099794U,  // MVE_VCVTs32f32n
1848
1.14M
    1228099934U,  // MVE_VCVTs32f32p
1849
1.14M
    1228100520U,  // MVE_VCVTs32f32z
1850
1.14M
    1295668136U,  // MVE_VCVTu16f16_fix
1851
1.14M
    1228622704U,  // MVE_VCVTu16f16a
1852
1.14M
    1228623986U,  // MVE_VCVTu16f16m
1853
1.14M
    1228624082U,  // MVE_VCVTu16f16n
1854
1.14M
    1228624222U,  // MVE_VCVTu16f16p
1855
1.14M
    1228624808U,  // MVE_VCVTu16f16z
1856
1.14M
    1296192424U,  // MVE_VCVTu32f32_fix
1857
1.14M
    1229146992U,  // MVE_VCVTu32f32a
1858
1.14M
    1229148274U,  // MVE_VCVTu32f32m
1859
1.14M
    1229148370U,  // MVE_VCVTu32f32n
1860
1.14M
    1229148510U,  // MVE_VCVTu32f32p
1861
1.14M
    1229149096U,  // MVE_VCVTu32f32z
1862
1.14M
    12726628U,  // MVE_VDDUPu16
1863
1.14M
    13250916U,  // MVE_VDDUPu32
1864
1.14M
    13775204U,  // MVE_VDDUPu8
1865
1.14M
    741744U,  // MVE_VDUP16
1866
1.14M
    1266032U, // MVE_VDUP32
1867
1.14M
    1790320U, // MVE_VDUP8
1868
1.14M
    12743029U,  // MVE_VDWDUPu16
1869
1.14M
    13267317U,  // MVE_VDWDUPu32
1870
1.14M
    13791605U,  // MVE_VDWDUPu8
1871
1.14M
    2773455U, // MVE_VEOR
1872
1.14M
    8008208U, // MVE_VFMA_qr_Sf16
1873
1.14M
    8532496U, // MVE_VFMA_qr_Sf32
1874
1.14M
    8006457U, // MVE_VFMA_qr_f16
1875
1.14M
    8530745U, // MVE_VFMA_qr_f32
1876
1.14M
    8006457U, // MVE_VFMAf16
1877
1.14M
    8530745U, // MVE_VFMAf32
1878
1.14M
    8008252U, // MVE_VFMSf16
1879
1.14M
    8532540U, // MVE_VFMSf32
1880
1.14M
    11160933U,  // MVE_VHADD_qr_s16
1881
1.14M
    11685221U,  // MVE_VHADD_qr_s32
1882
1.14M
    12209509U,  // MVE_VHADD_qr_s8
1883
1.14M
    12733797U,  // MVE_VHADD_qr_u16
1884
1.14M
    13258085U,  // MVE_VHADD_qr_u32
1885
1.14M
    13782373U,  // MVE_VHADD_qr_u8
1886
1.14M
    11160933U,  // MVE_VHADDs16
1887
1.14M
    11685221U,  // MVE_VHADDs32
1888
1.14M
    12209509U,  // MVE_VHADDs8
1889
1.14M
    12733797U,  // MVE_VHADDu16
1890
1.14M
    13258085U,  // MVE_VHADDu32
1891
1.14M
    13782373U,  // MVE_VHADDu8
1892
1.14M
    11152715U,  // MVE_VHCADDs16
1893
1.14M
    11677003U,  // MVE_VHCADDs32
1894
1.14M
    12201291U,  // MVE_VHCADDs8
1895
1.14M
    11160777U,  // MVE_VHSUB_qr_s16
1896
1.14M
    11685065U,  // MVE_VHSUB_qr_s32
1897
1.14M
    12209353U,  // MVE_VHSUB_qr_s8
1898
1.14M
    12733641U,  // MVE_VHSUB_qr_u16
1899
1.14M
    13257929U,  // MVE_VHSUB_qr_u32
1900
1.14M
    13782217U,  // MVE_VHSUB_qr_u8
1901
1.14M
    11160777U,  // MVE_VHSUBs16
1902
1.14M
    11685065U,  // MVE_VHSUBs32
1903
1.14M
    12209353U,  // MVE_VHSUBs8
1904
1.14M
    12733641U,  // MVE_VHSUBu16
1905
1.14M
    13257929U,  // MVE_VHSUBu32
1906
1.14M
    13782217U,  // MVE_VHSUBu8
1907
1.14M
    12726634U,  // MVE_VIDUPu16
1908
1.14M
    13250922U,  // MVE_VIDUPu32
1909
1.14M
    13775210U,  // MVE_VIDUPu8
1910
1.14M
    12743036U,  // MVE_VIWDUPu16
1911
1.14M
    13267324U,  // MVE_VIWDUPu32
1912
1.14M
    13791612U,  // MVE_VIWDUPu8
1913
1.14M
    21717869U,  // MVE_VLD20_16
1914
1.14M
    22242157U,  // MVE_VLD20_16_wb
1915
1.14M
    21716999U,  // MVE_VLD20_32
1916
1.14M
    22241287U,  // MVE_VLD20_32_wb
1917
1.14M
    21718505U,  // MVE_VLD20_8
1918
1.14M
    22242793U,  // MVE_VLD20_8_wb
1919
1.14M
    21717909U,  // MVE_VLD21_16
1920
1.14M
    22242197U,  // MVE_VLD21_16_wb
1921
1.14M
    21717065U,  // MVE_VLD21_32
1922
1.14M
    22241353U,  // MVE_VLD21_32_wb
1923
1.14M
    21718541U,  // MVE_VLD21_8
1924
1.14M
    22242829U,  // MVE_VLD21_8_wb
1925
1.14M
    21726081U,  // MVE_VLD40_16
1926
1.14M
    22250369U,  // MVE_VLD40_16_wb
1927
1.14M
    21725211U,  // MVE_VLD40_32
1928
1.14M
    22249499U,  // MVE_VLD40_32_wb
1929
1.14M
    21726715U,  // MVE_VLD40_8
1930
1.14M
    22251003U,  // MVE_VLD40_8_wb
1931
1.14M
    21726121U,  // MVE_VLD41_16
1932
1.14M
    22250409U,  // MVE_VLD41_16_wb
1933
1.14M
    21725277U,  // MVE_VLD41_32
1934
1.14M
    22249565U,  // MVE_VLD41_32_wb
1935
1.14M
    21726751U,  // MVE_VLD41_8
1936
1.14M
    22251039U,  // MVE_VLD41_8_wb
1937
1.14M
    21726141U,  // MVE_VLD42_16
1938
1.14M
    22250429U,  // MVE_VLD42_16_wb
1939
1.14M
    21725323U,  // MVE_VLD42_32
1940
1.14M
    22249611U,  // MVE_VLD42_32_wb
1941
1.14M
    21726769U,  // MVE_VLD42_8
1942
1.14M
    22251057U,  // MVE_VLD42_8_wb
1943
1.14M
    21726161U,  // MVE_VLD43_16
1944
1.14M
    22250449U,  // MVE_VLD43_16_wb
1945
1.14M
    21725356U,  // MVE_VLD43_32
1946
1.14M
    22249644U,  // MVE_VLD43_32_wb
1947
1.14M
    21726787U,  // MVE_VLD43_8
1948
1.14M
    22251075U,  // MVE_VLD43_8_wb
1949
1.14M
    11160697U,  // MVE_VLDRBS16
1950
1.14M
    950676601U, // MVE_VLDRBS16_post
1951
1.14M
    950676601U, // MVE_VLDRBS16_pre
1952
1.14M
    11160697U,  // MVE_VLDRBS16_rq
1953
1.14M
    11684985U,  // MVE_VLDRBS32
1954
1.14M
    951200889U, // MVE_VLDRBS32_post
1955
1.14M
    951200889U, // MVE_VLDRBS32_pre
1956
1.14M
    11684985U,  // MVE_VLDRBS32_rq
1957
1.14M
    12733561U,  // MVE_VLDRBU16
1958
1.14M
    952249465U, // MVE_VLDRBU16_post
1959
1.14M
    952249465U, // MVE_VLDRBU16_pre
1960
1.14M
    12733561U,  // MVE_VLDRBU16_rq
1961
1.14M
    13257849U,  // MVE_VLDRBU32
1962
1.14M
    952773753U, // MVE_VLDRBU32_post
1963
1.14M
    952773753U, // MVE_VLDRBU32_pre
1964
1.14M
    13257849U,  // MVE_VLDRBU32_rq
1965
1.14M
    13782137U,  // MVE_VLDRBU8
1966
1.14M
    953298041U, // MVE_VLDRBU8_post
1967
1.14M
    953298041U, // MVE_VLDRBU8_pre
1968
1.14M
    13782137U,  // MVE_VLDRBU8_rq
1969
1.14M
    22695315U,  // MVE_VLDRDU64_qi
1970
1.14M
    962211219U, // MVE_VLDRDU64_qi_pre
1971
1.14M
    22695315U,  // MVE_VLDRDU64_rq
1972
1.14M
    22695315U,  // MVE_VLDRDU64_rq_u
1973
1.14M
    11685503U,  // MVE_VLDRHS32
1974
1.14M
    951201407U, // MVE_VLDRHS32_post
1975
1.14M
    951201407U, // MVE_VLDRHS32_pre
1976
1.14M
    11685503U,  // MVE_VLDRHS32_rq
1977
1.14M
    11685503U,  // MVE_VLDRHS32_rq_u
1978
1.14M
    12734079U,  // MVE_VLDRHU16
1979
1.14M
    952249983U, // MVE_VLDRHU16_post
1980
1.14M
    952249983U, // MVE_VLDRHU16_pre
1981
1.14M
    12734079U,  // MVE_VLDRHU16_rq
1982
1.14M
    12734079U,  // MVE_VLDRHU16_rq_u
1983
1.14M
    13258367U,  // MVE_VLDRHU32
1984
1.14M
    952774271U, // MVE_VLDRHU32_post
1985
1.14M
    952774271U, // MVE_VLDRHU32_pre
1986
1.14M
    13258367U,  // MVE_VLDRHU32_rq
1987
1.14M
    13258367U,  // MVE_VLDRHU32_rq_u
1988
1.14M
    13259878U,  // MVE_VLDRWU32
1989
1.14M
    952775782U, // MVE_VLDRWU32_post
1990
1.14M
    952775782U, // MVE_VLDRWU32_pre
1991
1.14M
    13259878U,  // MVE_VLDRWU32_qi
1992
1.14M
    952775782U, // MVE_VLDRWU32_qi_pre
1993
1.14M
    13259878U,  // MVE_VLDRWU32_rq
1994
1.14M
    13259878U,  // MVE_VLDRWU32_rq_u
1995
1.14M
    950686733U, // MVE_VMAXAVs16
1996
1.14M
    951211021U, // MVE_VMAXAVs32
1997
1.14M
    951735309U, // MVE_VMAXAVs8
1998
1.14M
    11160491U,  // MVE_VMAXAs16
1999
1.14M
    11684779U,  // MVE_VMAXAs32
2000
1.14M
    12209067U,  // MVE_VMAXAs8
2001
1.14M
    947540989U, // MVE_VMAXNMAVf16
2002
1.14M
    948065277U, // MVE_VMAXNMAVf32
2003
1.14M
    8014668U, // MVE_VMAXNMAf16
2004
1.14M
    8538956U, // MVE_VMAXNMAf32
2005
1.14M
    947541052U, // MVE_VMAXNMVf16
2006
1.14M
    948065340U, // MVE_VMAXNMVf32
2007
1.14M
    8015958U, // MVE_VMAXNMf16
2008
1.14M
    8540246U, // MVE_VMAXNMf32
2009
1.14M
    950686799U, // MVE_VMAXVs16
2010
1.14M
    951211087U, // MVE_VMAXVs32
2011
1.14M
    951735375U, // MVE_VMAXVs8
2012
1.14M
    952259663U, // MVE_VMAXVu16
2013
1.14M
    952783951U, // MVE_VMAXVu32
2014
1.14M
    953308239U, // MVE_VMAXVu8
2015
1.14M
    11162791U,  // MVE_VMAXs16
2016
1.14M
    11687079U,  // MVE_VMAXs32
2017
1.14M
    12211367U,  // MVE_VMAXs8
2018
1.14M
    12735655U,  // MVE_VMAXu16
2019
1.14M
    13259943U,  // MVE_VMAXu32
2020
1.14M
    13784231U,  // MVE_VMAXu8
2021
1.14M
    950686726U, // MVE_VMINAVs16
2022
1.14M
    951211014U, // MVE_VMINAVs32
2023
1.14M
    951735302U, // MVE_VMINAVs8
2024
1.14M
    11160404U,  // MVE_VMINAs16
2025
1.14M
    11684692U,  // MVE_VMINAs32
2026
1.14M
    12208980U,  // MVE_VMINAs8
2027
1.14M
    947540980U, // MVE_VMINNMAVf16
2028
1.14M
    948065268U, // MVE_VMINNMAVf32
2029
1.14M
    8014660U, // MVE_VMINNMAf16
2030
1.14M
    8538948U, // MVE_VMINNMAf32
2031
1.14M
    947541044U, // MVE_VMINNMVf16
2032
1.14M
    948065332U, // MVE_VMINNMVf32
2033
1.14M
    8015951U, // MVE_VMINNMf16
2034
1.14M
    8540239U, // MVE_VMINNMf32
2035
1.14M
    950686788U, // MVE_VMINVs16
2036
1.14M
    951211076U, // MVE_VMINVs32
2037
1.14M
    951735364U, // MVE_VMINVs8
2038
1.14M
    952259652U, // MVE_VMINVu16
2039
1.14M
    952783940U, // MVE_VMINVu32
2040
1.14M
    953308228U, // MVE_VMINVu8
2041
1.14M
    11161756U,  // MVE_VMINs16
2042
1.14M
    11686044U,  // MVE_VMINs32
2043
1.14M
    12210332U,  // MVE_VMINs8
2044
1.14M
    12734620U,  // MVE_VMINu16
2045
1.14M
    13258908U,  // MVE_VMINu32
2046
1.14M
    13783196U,  // MVE_VMINu8
2047
1.14M
    11152246U,  // MVE_VMLADAVas16
2048
1.14M
    11676534U,  // MVE_VMLADAVas32
2049
1.14M
    12200822U,  // MVE_VMLADAVas8
2050
1.14M
    12725110U,  // MVE_VMLADAVau16
2051
1.14M
    13249398U,  // MVE_VMLADAVau32
2052
1.14M
    13773686U,  // MVE_VMLADAVau8
2053
1.14M
    11154632U,  // MVE_VMLADAVaxs16
2054
1.14M
    11678920U,  // MVE_VMLADAVaxs32
2055
1.14M
    12203208U,  // MVE_VMLADAVaxs8
2056
1.14M
    11162578U,  // MVE_VMLADAVs16
2057
1.14M
    11686866U,  // MVE_VMLADAVs32
2058
1.14M
    12211154U,  // MVE_VMLADAVs8
2059
1.14M
    12735442U,  // MVE_VMLADAVu16
2060
1.14M
    13259730U,  // MVE_VMLADAVu32
2061
1.14M
    13784018U,  // MVE_VMLADAVu8
2062
1.14M
    11163085U,  // MVE_VMLADAVxs16
2063
1.14M
    11687373U,  // MVE_VMLADAVxs32
2064
1.14M
    12211661U,  // MVE_VMLADAVxs8
2065
1.14M
    11176831U,  // MVE_VMLALDAVas16
2066
1.14M
    11701119U,  // MVE_VMLALDAVas32
2067
1.14M
    12749695U,  // MVE_VMLALDAVau16
2068
1.14M
    13273983U,  // MVE_VMLALDAVau32
2069
1.14M
    11179218U,  // MVE_VMLALDAVaxs16
2070
1.14M
    11703506U,  // MVE_VMLALDAVaxs32
2071
1.14M
    11154394U,  // MVE_VMLALDAVs16
2072
1.14M
    11678682U,  // MVE_VMLALDAVs32
2073
1.14M
    12727258U,  // MVE_VMLALDAVu16
2074
1.14M
    13251546U,  // MVE_VMLALDAVu32
2075
1.14M
    11154902U,  // MVE_VMLALDAVxs16
2076
1.14M
    11679190U,  // MVE_VMLALDAVxs32
2077
1.14M
    14823946U,  // MVE_VMLAS_qr_i16
2078
1.14M
    14299658U,  // MVE_VMLAS_qr_i32
2079
1.14M
    15348234U,  // MVE_VMLAS_qr_i8
2080
1.14M
    14822196U,  // MVE_VMLA_qr_i16
2081
1.14M
    14297908U,  // MVE_VMLA_qr_i32
2082
1.14M
    15346484U,  // MVE_VMLA_qr_i8
2083
1.14M
    11152275U,  // MVE_VMLSDAVas16
2084
1.14M
    11676563U,  // MVE_VMLSDAVas32
2085
1.14M
    12200851U,  // MVE_VMLSDAVas8
2086
1.14M
    11154664U,  // MVE_VMLSDAVaxs16
2087
1.14M
    11678952U,  // MVE_VMLSDAVaxs32
2088
1.14M
    12203240U,  // MVE_VMLSDAVaxs8
2089
1.14M
    11162604U,  // MVE_VMLSDAVs16
2090
1.14M
    11686892U,  // MVE_VMLSDAVs32
2091
1.14M
    12211180U,  // MVE_VMLSDAVs8
2092
1.14M
    11163114U,  // MVE_VMLSDAVxs16
2093
1.14M
    11687402U,  // MVE_VMLSDAVxs32
2094
1.14M
    12211690U,  // MVE_VMLSDAVxs8
2095
1.14M
    11176841U,  // MVE_VMLSLDAVas16
2096
1.14M
    11701129U,  // MVE_VMLSLDAVas32
2097
1.14M
    11179229U,  // MVE_VMLSLDAVaxs16
2098
1.14M
    11703517U,  // MVE_VMLSLDAVaxs32
2099
1.14M
    11154403U,  // MVE_VMLSLDAVs16
2100
1.14M
    11678691U,  // MVE_VMLSLDAVs32
2101
1.14M
    11154912U,  // MVE_VMLSLDAVxs16
2102
1.14M
    11679200U,  // MVE_VMLSLDAVxs32
2103
1.14M
    11226142U,  // MVE_VMOVLs16bh
2104
1.14M
    11227900U,  // MVE_VMOVLs16th
2105
1.14M
    12274718U,  // MVE_VMOVLs8bh
2106
1.14M
    12276476U,  // MVE_VMOVLs8th
2107
1.14M
    12799006U,  // MVE_VMOVLu16bh
2108
1.14M
    12800764U,  // MVE_VMOVLu16th
2109
1.14M
    13847582U,  // MVE_VMOVLu8bh
2110
1.14M
    13849340U,  // MVE_VMOVLu8th
2111
1.14M
    14830701U,  // MVE_VMOVNi16bh
2112
1.14M
    14832465U,  // MVE_VMOVNi16th
2113
1.14M
    14306413U,  // MVE_VMOVNi32bh
2114
1.14M
    14308177U,  // MVE_VMOVNi32th
2115
1.14M
    1111114U, // MVE_VMOV_from_lane_32
2116
1.14M
    11072586U,  // MVE_VMOV_from_lane_s16
2117
1.14M
    12121162U,  // MVE_VMOV_from_lane_s8
2118
1.14M
    12645450U,  // MVE_VMOV_from_lane_u16
2119
1.14M
    13694026U,  // MVE_VMOV_from_lane_u8
2120
1.14M
    2757706U, // MVE_VMOV_q_rr
2121
1.14M
    2675786U, // MVE_VMOV_rr_q
2122
1.14M
    570442U,  // MVE_VMOV_to_lane_16
2123
1.14M
    1094730U, // MVE_VMOV_to_lane_32
2124
1.14M
    1619018U, // MVE_VMOV_to_lane_8
2125
1.14M
    8606794U, // MVE_VMOVimmf32
2126
1.14M
    14898250U,  // MVE_VMOVimmi16
2127
1.14M
    14373962U,  // MVE_VMOVimmi32
2128
1.14M
    2103661642U,  // MVE_VMOVimmi64
2129
1.14M
    15422538U,  // MVE_VMOVimmi8
2130
1.14M
    11161209U,  // MVE_VMULHs16
2131
1.14M
    11685497U,  // MVE_VMULHs32
2132
1.14M
    12209785U,  // MVE_VMULHs8
2133
1.14M
    12734073U,  // MVE_VMULHu16
2134
1.14M
    13258361U,  // MVE_VMULHu32
2135
1.14M
    13782649U,  // MVE_VMULHu8
2136
1.14M
    23743506U,  // MVE_VMULLBp16
2137
1.14M
    24267794U,  // MVE_VMULLBp8
2138
1.14M
    11160594U,  // MVE_VMULLBs16
2139
1.14M
    11684882U,  // MVE_VMULLBs32
2140
1.14M
    12209170U,  // MVE_VMULLBs8
2141
1.14M
    12733458U,  // MVE_VMULLBu16
2142
1.14M
    13257746U,  // MVE_VMULLBu32
2143
1.14M
    13782034U,  // MVE_VMULLBu8
2144
1.14M
    23745269U,  // MVE_VMULLTp16
2145
1.14M
    24269557U,  // MVE_VMULLTp8
2146
1.14M
    11162357U,  // MVE_VMULLTs16
2147
1.14M
    11686645U,  // MVE_VMULLTs32
2148
1.14M
    12210933U,  // MVE_VMULLTs8
2149
1.14M
    12735221U,  // MVE_VMULLTu16
2150
1.14M
    13259509U,  // MVE_VMULLTu32
2151
1.14M
    13783797U,  // MVE_VMULLTu8
2152
1.14M
    8015934U, // MVE_VMUL_qr_f16
2153
1.14M
    8540222U, // MVE_VMUL_qr_f32
2154
1.14M
    14831678U,  // MVE_VMUL_qr_i16
2155
1.14M
    14307390U,  // MVE_VMUL_qr_i32
2156
1.14M
    15355966U,  // MVE_VMUL_qr_i8
2157
1.14M
    8015934U, // MVE_VMULf16
2158
1.14M
    8540222U, // MVE_VMULf32
2159
1.14M
    14831678U,  // MVE_VMULi16
2160
1.14M
    14307390U,  // MVE_VMULi32
2161
1.14M
    15355966U,  // MVE_VMULi8
2162
1.14M
    2838769U, // MVE_VMVN
2163
1.14M
    14897393U,  // MVE_VMVNimmi16
2164
1.14M
    14373105U,  // MVE_VMVNimmi32
2165
1.14M
    8080899U, // MVE_VNEGf16
2166
1.14M
    8605187U, // MVE_VNEGf32
2167
1.14M
    11226627U,  // MVE_VNEGs16
2168
1.14M
    11750915U,  // MVE_VNEGs32
2169
1.14M
    12275203U,  // MVE_VNEGs8
2170
1.14M
    2773185U, // MVE_VORN
2171
1.14M
    2773469U, // MVE_VORR
2172
1.14M
    14832093U,  // MVE_VORRimmi16
2173
1.14M
    14307805U,  // MVE_VORRimmi32
2174
1.14M
    1210798936U,  // MVE_VPNOT
2175
1.14M
    2772855U, // MVE_VPSEL
2176
1.14M
    1210823538U,  // MVE_VPST
2177
1.14M
    2028712798U,  // MVE_VPTv16i8
2178
1.14M
    2028712798U,  // MVE_VPTv16i8r
2179
1.14M
    2025567070U,  // MVE_VPTv16s8
2180
1.14M
    2025567070U,  // MVE_VPTv16s8r
2181
1.14M
    2027139934U,  // MVE_VPTv16u8
2182
1.14M
    2027139934U,  // MVE_VPTv16u8r
2183
1.14M
    2021897054U,  // MVE_VPTv4f32
2184
1.14M
    2021897054U,  // MVE_VPTv4f32r
2185
1.14M
    2027664222U,  // MVE_VPTv4i32
2186
1.14M
    2027664222U,  // MVE_VPTv4i32r
2187
1.14M
    2025042782U,  // MVE_VPTv4s32
2188
1.14M
    2025042782U,  // MVE_VPTv4s32r
2189
1.14M
    2026615646U,  // MVE_VPTv4u32
2190
1.14M
    2026615646U,  // MVE_VPTv4u32r
2191
1.14M
    2021372766U,  // MVE_VPTv8f16
2192
1.14M
    2021372766U,  // MVE_VPTv8f16r
2193
1.14M
    2028188510U,  // MVE_VPTv8i16
2194
1.14M
    2028188510U,  // MVE_VPTv8i16r
2195
1.14M
    2024518494U,  // MVE_VPTv8s16
2196
1.14M
    2024518494U,  // MVE_VPTv8s16r
2197
1.14M
    2026091358U,  // MVE_VPTv8u16
2198
1.14M
    2026091358U,  // MVE_VPTv8u16r
2199
1.14M
    11227670U,  // MVE_VQABSs16
2200
1.14M
    11751958U,  // MVE_VQABSs32
2201
1.14M
    12276246U,  // MVE_VQABSs8
2202
1.14M
    11160945U,  // MVE_VQADD_qr_s16
2203
1.14M
    11685233U,  // MVE_VQADD_qr_s32
2204
1.14M
    12209521U,  // MVE_VQADD_qr_s8
2205
1.14M
    12733809U,  // MVE_VQADD_qr_u16
2206
1.14M
    13258097U,  // MVE_VQADD_qr_u32
2207
1.14M
    13782385U,  // MVE_VQADD_qr_u8
2208
1.14M
    11160945U,  // MVE_VQADDs16
2209
1.14M
    11685233U,  // MVE_VQADDs32
2210
1.14M
    12209521U,  // MVE_VQADDs8
2211
1.14M
    12733809U,  // MVE_VQADDu16
2212
1.14M
    13258097U,  // MVE_VQADDu32
2213
1.14M
    13782385U,  // MVE_VQADDu8
2214
1.14M
    11154779U,  // MVE_VQDMLADHXs16
2215
1.14M
    11679067U,  // MVE_VQDMLADHXs32
2216
1.14M
    12203355U,  // MVE_VQDMLADHXs8
2217
1.14M
    11152950U,  // MVE_VQDMLADHs16
2218
1.14M
    11677238U,  // MVE_VQDMLADHs32
2219
1.14M
    12201526U,  // MVE_VQDMLADHs8
2220
1.14M
    11152917U,  // MVE_VQDMLAH_qrs16
2221
1.14M
    11677205U,  // MVE_VQDMLAH_qrs32
2222
1.14M
    12201493U,  // MVE_VQDMLAH_qrs8
2223
1.14M
    11153035U,  // MVE_VQDMLASH_qrs16
2224
1.14M
    11677323U,  // MVE_VQDMLASH_qrs32
2225
1.14M
    12201611U,  // MVE_VQDMLASH_qrs8
2226
1.14M
    11154800U,  // MVE_VQDMLSDHXs16
2227
1.14M
    11679088U,  // MVE_VQDMLSDHXs32
2228
1.14M
    12203376U,  // MVE_VQDMLSDHXs8
2229
1.14M
    11152969U,  // MVE_VQDMLSDHs16
2230
1.14M
    11677257U,  // MVE_VQDMLSDHs32
2231
1.14M
    12201545U,  // MVE_VQDMLSDHs8
2232
1.14M
    11161185U,  // MVE_VQDMULH_qr_s16
2233
1.14M
    11685473U,  // MVE_VQDMULH_qr_s32
2234
1.14M
    12209761U,  // MVE_VQDMULH_qr_s8
2235
1.14M
    11161185U,  // MVE_VQDMULHi16
2236
1.14M
    11685473U,  // MVE_VQDMULHi32
2237
1.14M
    12209761U,  // MVE_VQDMULHi8
2238
1.14M
    11160585U,  // MVE_VQDMULL_qr_s16bh
2239
1.14M
    11162348U,  // MVE_VQDMULL_qr_s16th
2240
1.14M
    11684873U,  // MVE_VQDMULL_qr_s32bh
2241
1.14M
    11686636U,  // MVE_VQDMULL_qr_s32th
2242
1.14M
    11160585U,  // MVE_VQDMULLs16bh
2243
1.14M
    11162348U,  // MVE_VQDMULLs16th
2244
1.14M
    11684873U,  // MVE_VQDMULLs32bh
2245
1.14M
    11686636U,  // MVE_VQDMULLs32th
2246
1.14M
    11160677U,  // MVE_VQMOVNs16bh
2247
1.14M
    11162441U,  // MVE_VQMOVNs16th
2248
1.14M
    11684965U,  // MVE_VQMOVNs32bh
2249
1.14M
    11686729U,  // MVE_VQMOVNs32th
2250
1.14M
    12733541U,  // MVE_VQMOVNu16bh
2251
1.14M
    12735305U,  // MVE_VQMOVNu16th
2252
1.14M
    13257829U,  // MVE_VQMOVNu32bh
2253
1.14M
    13259593U,  // MVE_VQMOVNu32th
2254
1.14M
    11160668U,  // MVE_VQMOVUNs16bh
2255
1.14M
    11162432U,  // MVE_VQMOVUNs16th
2256
1.14M
    11684956U,  // MVE_VQMOVUNs32bh
2257
1.14M
    11686720U,  // MVE_VQMOVUNs32th
2258
1.14M
    11226621U,  // MVE_VQNEGs16
2259
1.14M
    11750909U,  // MVE_VQNEGs32
2260
1.14M
    12275197U,  // MVE_VQNEGs8
2261
1.14M
    11154789U,  // MVE_VQRDMLADHXs16
2262
1.14M
    11679077U,  // MVE_VQRDMLADHXs32
2263
1.14M
    12203365U,  // MVE_VQRDMLADHXs8
2264
1.14M
    11152959U,  // MVE_VQRDMLADHs16
2265
1.14M
    11677247U,  // MVE_VQRDMLADHs32
2266
1.14M
    12201535U,  // MVE_VQRDMLADHs8
2267
1.14M
    11152925U,  // MVE_VQRDMLAH_qrs16
2268
1.14M
    11677213U,  // MVE_VQRDMLAH_qrs32
2269
1.14M
    12201501U,  // MVE_VQRDMLAH_qrs8
2270
1.14M
    11153044U,  // MVE_VQRDMLASH_qrs16
2271
1.14M
    11677332U,  // MVE_VQRDMLASH_qrs32
2272
1.14M
    12201620U,  // MVE_VQRDMLASH_qrs8
2273
1.14M
    11154810U,  // MVE_VQRDMLSDHXs16
2274
1.14M
    11679098U,  // MVE_VQRDMLSDHXs32
2275
1.14M
    12203386U,  // MVE_VQRDMLSDHXs8
2276
1.14M
    11152978U,  // MVE_VQRDMLSDHs16
2277
1.14M
    11677266U,  // MVE_VQRDMLSDHs32
2278
1.14M
    12201554U,  // MVE_VQRDMLSDHs8
2279
1.14M
    11161193U,  // MVE_VQRDMULH_qr_s16
2280
1.14M
    11685481U,  // MVE_VQRDMULH_qr_s32
2281
1.14M
    12209769U,  // MVE_VQRDMULH_qr_s8
2282
1.14M
    11161193U,  // MVE_VQRDMULHi16
2283
1.14M
    11685481U,  // MVE_VQRDMULHi32
2284
1.14M
    12209769U,  // MVE_VQRDMULHi8
2285
1.14M
    11161498U,  // MVE_VQRSHL_by_vecs16
2286
1.14M
    11685786U,  // MVE_VQRSHL_by_vecs32
2287
1.14M
    12210074U,  // MVE_VQRSHL_by_vecs8
2288
1.14M
    12734362U,  // MVE_VQRSHL_by_vecu16
2289
1.14M
    13258650U,  // MVE_VQRSHL_by_vecu32
2290
1.14M
    13782938U,  // MVE_VQRSHL_by_vecu8
2291
1.14M
    11161498U,  // MVE_VQRSHL_qrs16
2292
1.14M
    11685786U,  // MVE_VQRSHL_qrs32
2293
1.14M
    12210074U,  // MVE_VQRSHL_qrs8
2294
1.14M
    12734362U,  // MVE_VQRSHL_qru16
2295
1.14M
    13258650U,  // MVE_VQRSHL_qru32
2296
1.14M
    13782938U,  // MVE_VQRSHL_qru8
2297
1.14M
    11152433U,  // MVE_VQRSHRNbhs16
2298
1.14M
    11676721U,  // MVE_VQRSHRNbhs32
2299
1.14M
    12725297U,  // MVE_VQRSHRNbhu16
2300
1.14M
    13249585U,  // MVE_VQRSHRNbhu32
2301
1.14M
    11154197U,  // MVE_VQRSHRNths16
2302
1.14M
    11678485U,  // MVE_VQRSHRNths32
2303
1.14M
    12727061U,  // MVE_VQRSHRNthu16
2304
1.14M
    13251349U,  // MVE_VQRSHRNthu32
2305
1.14M
    11152466U,  // MVE_VQRSHRUNs16bh
2306
1.14M
    11154230U,  // MVE_VQRSHRUNs16th
2307
1.14M
    11676754U,  // MVE_VQRSHRUNs32bh
2308
1.14M
    11678518U,  // MVE_VQRSHRUNs32th
2309
1.14M
    11162565U,  // MVE_VQSHLU_imms16
2310
1.14M
    11686853U,  // MVE_VQSHLU_imms32
2311
1.14M
    12211141U,  // MVE_VQSHLU_imms8
2312
1.14M
    11161485U,  // MVE_VQSHL_by_vecs16
2313
1.14M
    11685773U,  // MVE_VQSHL_by_vecs32
2314
1.14M
    12210061U,  // MVE_VQSHL_by_vecs8
2315
1.14M
    12734349U,  // MVE_VQSHL_by_vecu16
2316
1.14M
    13258637U,  // MVE_VQSHL_by_vecu32
2317
1.14M
    13782925U,  // MVE_VQSHL_by_vecu8
2318
1.14M
    11161485U,  // MVE_VQSHL_qrs16
2319
1.14M
    11685773U,  // MVE_VQSHL_qrs32
2320
1.14M
    12210061U,  // MVE_VQSHL_qrs8
2321
1.14M
    12734349U,  // MVE_VQSHL_qru16
2322
1.14M
    13258637U,  // MVE_VQSHL_qru32
2323
1.14M
    13782925U,  // MVE_VQSHL_qru8
2324
1.14M
    11161485U,  // MVE_VQSHLimms16
2325
1.14M
    11685773U,  // MVE_VQSHLimms32
2326
1.14M
    12210061U,  // MVE_VQSHLimms8
2327
1.14M
    12734349U,  // MVE_VQSHLimmu16
2328
1.14M
    13258637U,  // MVE_VQSHLimmu32
2329
1.14M
    13782925U,  // MVE_VQSHLimmu8
2330
1.14M
    11152425U,  // MVE_VQSHRNbhs16
2331
1.14M
    11676713U,  // MVE_VQSHRNbhs32
2332
1.14M
    12725289U,  // MVE_VQSHRNbhu16
2333
1.14M
    13249577U,  // MVE_VQSHRNbhu32
2334
1.14M
    11154189U,  // MVE_VQSHRNths16
2335
1.14M
    11678477U,  // MVE_VQSHRNths32
2336
1.14M
    12727053U,  // MVE_VQSHRNthu16
2337
1.14M
    13251341U,  // MVE_VQSHRNthu32
2338
1.14M
    11152457U,  // MVE_VQSHRUNs16bh
2339
1.14M
    11154221U,  // MVE_VQSHRUNs16th
2340
1.14M
    11676745U,  // MVE_VQSHRUNs32bh
2341
1.14M
    11678509U,  // MVE_VQSHRUNs32th
2342
1.14M
    11160783U,  // MVE_VQSUB_qr_s16
2343
1.14M
    11685071U,  // MVE_VQSUB_qr_s32
2344
1.14M
    12209359U,  // MVE_VQSUB_qr_s8
2345
1.14M
    12733647U,  // MVE_VQSUB_qr_u16
2346
1.14M
    13257935U,  // MVE_VQSUB_qr_u32
2347
1.14M
    13782223U,  // MVE_VQSUB_qr_u8
2348
1.14M
    11160783U,  // MVE_VQSUBs16
2349
1.14M
    11685071U,  // MVE_VQSUBs32
2350
1.14M
    12209359U,  // MVE_VQSUBs8
2351
1.14M
    12733647U,  // MVE_VQSUBu16
2352
1.14M
    13257935U,  // MVE_VQSUBu32
2353
1.14M
    13782223U,  // MVE_VQSUBu8
2354
1.14M
    1788408U, // MVE_VREV16_8
2355
1.14M
    739609U,  // MVE_VREV32_16
2356
1.14M
    1788185U, // MVE_VREV32_8
2357
1.14M
    739695U,  // MVE_VREV64_16
2358
1.14M
    1263983U, // MVE_VREV64_32
2359
1.14M
    1788271U, // MVE_VREV64_8
2360
1.14M
    11160926U,  // MVE_VRHADDs16
2361
1.14M
    11685214U,  // MVE_VRHADDs32
2362
1.14M
    12209502U,  // MVE_VRHADDs8
2363
1.14M
    12733790U,  // MVE_VRHADDu16
2364
1.14M
    13258078U,  // MVE_VRHADDu32
2365
1.14M
    13782366U,  // MVE_VRHADDu8
2366
1.14M
    8080229U, // MVE_VRINTf16A
2367
1.14M
    8081509U, // MVE_VRINTf16M
2368
1.14M
    8081611U, // MVE_VRINTf16N
2369
1.14M
    8081751U, // MVE_VRINTf16P
2370
1.14M
    8082886U, // MVE_VRINTf16X
2371
1.14M
    8082936U, // MVE_VRINTf16Z
2372
1.14M
    8604517U, // MVE_VRINTf32A
2373
1.14M
    8605797U, // MVE_VRINTf32M
2374
1.14M
    8605899U, // MVE_VRINTf32N
2375
1.14M
    8606039U, // MVE_VRINTf32P
2376
1.14M
    8607174U, // MVE_VRINTf32X
2377
1.14M
    8607224U, // MVE_VRINTf32Z
2378
1.14M
    11700976U,  // MVE_VRMLALDAVHas32
2379
1.14M
    13273840U,  // MVE_VRMLALDAVHau32
2380
1.14M
    11703415U,  // MVE_VRMLALDAVHaxs32
2381
1.14M
    11677378U,  // MVE_VRMLALDAVHs32
2382
1.14M
    13250242U,  // MVE_VRMLALDAVHu32
2383
1.14M
    11679109U,  // MVE_VRMLALDAVHxs32
2384
1.14M
    11700988U,  // MVE_VRMLSLDAVHas32
2385
1.14M
    11703428U,  // MVE_VRMLSLDAVHaxs32
2386
1.14M
    11677389U,  // MVE_VRMLSLDAVHs32
2387
1.14M
    11679121U,  // MVE_VRMLSLDAVHxs32
2388
1.14M
    11161202U,  // MVE_VRMULHs16
2389
1.14M
    11685490U,  // MVE_VRMULHs32
2390
1.14M
    12209778U,  // MVE_VRMULHs8
2391
1.14M
    12734066U,  // MVE_VRMULHu16
2392
1.14M
    13258354U,  // MVE_VRMULHu32
2393
1.14M
    13782642U,  // MVE_VRMULHu8
2394
1.14M
    11161505U,  // MVE_VRSHL_by_vecs16
2395
1.14M
    11685793U,  // MVE_VRSHL_by_vecs32
2396
1.14M
    12210081U,  // MVE_VRSHL_by_vecs8
2397
1.14M
    12734369U,  // MVE_VRSHL_by_vecu16
2398
1.14M
    13258657U,  // MVE_VRSHL_by_vecu32
2399
1.14M
    13782945U,  // MVE_VRSHL_by_vecu8
2400
1.14M
    11161505U,  // MVE_VRSHL_qrs16
2401
1.14M
    11685793U,  // MVE_VRSHL_qrs32
2402
1.14M
    12210081U,  // MVE_VRSHL_qrs8
2403
1.14M
    12734369U,  // MVE_VRSHL_qru16
2404
1.14M
    13258657U,  // MVE_VRSHL_qru32
2405
1.14M
    13782945U,  // MVE_VRSHL_qru8
2406
1.14M
    14822458U,  // MVE_VRSHRNi16bh
2407
1.14M
    14824222U,  // MVE_VRSHRNi16th
2408
1.14M
    14298170U,  // MVE_VRSHRNi32bh
2409
1.14M
    14299934U,  // MVE_VRSHRNi32th
2410
1.14M
    11162045U,  // MVE_VRSHR_imms16
2411
1.14M
    11686333U,  // MVE_VRSHR_imms32
2412
1.14M
    12210621U,  // MVE_VRSHR_imms8
2413
1.14M
    12734909U,  // MVE_VRSHR_immu16
2414
1.14M
    13259197U,  // MVE_VRSHR_immu32
2415
1.14M
    13783485U,  // MVE_VRSHR_immu8
2416
1.14M
    14314756U,  // MVE_VSBC
2417
1.14M
    14298868U,  // MVE_VSBCI
2418
1.14M
    875195675U, // MVE_VSHLC
2419
1.14M
    11160578U,  // MVE_VSHLL_imms16bh
2420
1.14M
    11162341U,  // MVE_VSHLL_imms16th
2421
1.14M
    12209154U,  // MVE_VSHLL_imms8bh
2422
1.14M
    12210917U,  // MVE_VSHLL_imms8th
2423
1.14M
    12733442U,  // MVE_VSHLL_immu16bh
2424
1.14M
    12735205U,  // MVE_VSHLL_immu16th
2425
1.14M
    13782018U,  // MVE_VSHLL_immu8bh
2426
1.14M
    13783781U,  // MVE_VSHLL_immu8th
2427
1.14M
    11226114U,  // MVE_VSHLL_lws16bh
2428
1.14M
    11227877U,  // MVE_VSHLL_lws16th
2429
1.14M
    12274690U,  // MVE_VSHLL_lws8bh
2430
1.14M
    12276453U,  // MVE_VSHLL_lws8th
2431
1.14M
    12798978U,  // MVE_VSHLL_lwu16bh
2432
1.14M
    12800741U,  // MVE_VSHLL_lwu16th
2433
1.14M
    13847554U,  // MVE_VSHLL_lwu8bh
2434
1.14M
    13849317U,  // MVE_VSHLL_lwu8th
2435
1.14M
    11161511U,  // MVE_VSHL_by_vecs16
2436
1.14M
    11685799U,  // MVE_VSHL_by_vecs32
2437
1.14M
    12210087U,  // MVE_VSHL_by_vecs8
2438
1.14M
    12734375U,  // MVE_VSHL_by_vecu16
2439
1.14M
    13258663U,  // MVE_VSHL_by_vecu32
2440
1.14M
    13782951U,  // MVE_VSHL_by_vecu8
2441
1.14M
    14831527U,  // MVE_VSHL_immi16
2442
1.14M
    14307239U,  // MVE_VSHL_immi32
2443
1.14M
    15355815U,  // MVE_VSHL_immi8
2444
1.14M
    11161511U,  // MVE_VSHL_qrs16
2445
1.14M
    11685799U,  // MVE_VSHL_qrs32
2446
1.14M
    12210087U,  // MVE_VSHL_qrs8
2447
1.14M
    12734375U,  // MVE_VSHL_qru16
2448
1.14M
    13258663U,  // MVE_VSHL_qru32
2449
1.14M
    13782951U,  // MVE_VSHL_qru8
2450
1.14M
    14822466U,  // MVE_VSHRNi16bh
2451
1.14M
    14824230U,  // MVE_VSHRNi16th
2452
1.14M
    14298178U,  // MVE_VSHRNi32bh
2453
1.14M
    14299942U,  // MVE_VSHRNi32th
2454
1.14M
    11162051U,  // MVE_VSHR_imms16
2455
1.14M
    11686339U,  // MVE_VSHR_imms32
2456
1.14M
    12210627U,  // MVE_VSHR_imms8
2457
1.14M
    12734915U,  // MVE_VSHR_immu16
2458
1.14M
    13259203U,  // MVE_VSHR_immu32
2459
1.14M
    13783491U,  // MVE_VSHR_immu8
2460
1.14M
    667400U,  // MVE_VSLIimm16
2461
1.14M
    1191688U, // MVE_VSLIimm32
2462
1.14M
    1715976U, // MVE_VSLIimm8
2463
1.14M
    667405U,  // MVE_VSRIimm16
2464
1.14M
    1191693U, // MVE_VSRIimm32
2465
1.14M
    1715981U, // MVE_VSRIimm8
2466
1.14M
    24863607U,  // MVE_VST20_16
2467
1.14M
    246647U,  // MVE_VST20_16_wb
2468
1.14M
    24862737U,  // MVE_VST20_32
2469
1.14M
    245777U,  // MVE_VST20_32_wb
2470
1.14M
    24864242U,  // MVE_VST20_8
2471
1.14M
    247282U,  // MVE_VST20_8_wb
2472
1.14M
    24863647U,  // MVE_VST21_16
2473
1.14M
    246687U,  // MVE_VST21_16_wb
2474
1.14M
    24862803U,  // MVE_VST21_32
2475
1.14M
    245843U,  // MVE_VST21_32_wb
2476
1.14M
    24864278U,  // MVE_VST21_8
2477
1.14M
    247318U,  // MVE_VST21_8_wb
2478
1.14M
    24871819U,  // MVE_VST40_16
2479
1.14M
    254859U,  // MVE_VST40_16_wb
2480
1.14M
    24870949U,  // MVE_VST40_32
2481
1.14M
    253989U,  // MVE_VST40_32_wb
2482
1.14M
    24872452U,  // MVE_VST40_8
2483
1.14M
    255492U,  // MVE_VST40_8_wb
2484
1.14M
    24871859U,  // MVE_VST41_16
2485
1.14M
    254899U,  // MVE_VST41_16_wb
2486
1.14M
    24871015U,  // MVE_VST41_32
2487
1.14M
    254055U,  // MVE_VST41_32_wb
2488
1.14M
    24872488U,  // MVE_VST41_8
2489
1.14M
    255528U,  // MVE_VST41_8_wb
2490
1.14M
    24871879U,  // MVE_VST42_16
2491
1.14M
    254919U,  // MVE_VST42_16_wb
2492
1.14M
    24871061U,  // MVE_VST42_32
2493
1.14M
    254101U,  // MVE_VST42_32_wb
2494
1.14M
    24872506U,  // MVE_VST42_8
2495
1.14M
    255546U,  // MVE_VST42_8_wb
2496
1.14M
    24871899U,  // MVE_VST43_16
2497
1.14M
    254939U,  // MVE_VST43_16_wb
2498
1.14M
    24871094U,  // MVE_VST43_32
2499
1.14M
    254134U,  // MVE_VST43_32_wb
2500
1.14M
    24872524U,  // MVE_VST43_8
2501
1.14M
    255564U,  // MVE_VST43_8_wb
2502
1.14M
    674943U,  // MVE_VSTRB16
2503
1.14M
    940190847U, // MVE_VSTRB16_post
2504
1.14M
    940190847U, // MVE_VSTRB16_pre
2505
1.14M
    674943U,  // MVE_VSTRB16_rq
2506
1.14M
    1199231U, // MVE_VSTRB32
2507
1.14M
    940715135U, // MVE_VSTRB32_post
2508
1.14M
    940715135U, // MVE_VSTRB32_pre
2509
1.14M
    1199231U, // MVE_VSTRB32_rq
2510
1.14M
    1723519U, // MVE_VSTRB8_rq
2511
1.14M
    1723519U, // MVE_VSTRBU8
2512
1.14M
    941239423U, // MVE_VSTRBU8_post
2513
1.14M
    941239423U, // MVE_VSTRBU8_pre
2514
1.14M
    15879577U,  // MVE_VSTRD64_qi
2515
1.14M
    955395481U, // MVE_VSTRD64_qi_pre
2516
1.14M
    15879577U,  // MVE_VSTRD64_rq
2517
1.14M
    15879577U,  // MVE_VSTRD64_rq_u
2518
1.14M
    675461U,  // MVE_VSTRH16_rq
2519
1.14M
    675461U,  // MVE_VSTRH16_rq_u
2520
1.14M
    1199749U, // MVE_VSTRH32
2521
1.14M
    940715653U, // MVE_VSTRH32_post
2522
1.14M
    940715653U, // MVE_VSTRH32_pre
2523
1.14M
    1199749U, // MVE_VSTRH32_rq
2524
1.14M
    1199749U, // MVE_VSTRH32_rq_u
2525
1.14M
    675461U,  // MVE_VSTRHU16
2526
1.14M
    940191365U, // MVE_VSTRHU16_post
2527
1.14M
    940191365U, // MVE_VSTRHU16_pre
2528
1.14M
    1201260U, // MVE_VSTRW32_qi
2529
1.14M
    940717164U, // MVE_VSTRW32_qi_pre
2530
1.14M
    1201260U, // MVE_VSTRW32_rq
2531
1.14M
    1201260U, // MVE_VSTRW32_rq_u
2532
1.14M
    1201260U, // MVE_VSTRWU32
2533
1.14M
    940717164U, // MVE_VSTRWU32_post
2534
1.14M
    940717164U, // MVE_VSTRWU32_pre
2535
1.14M
    8015061U, // MVE_VSUB_qr_f16
2536
1.14M
    8539349U, // MVE_VSUB_qr_f32
2537
1.14M
    14830805U,  // MVE_VSUB_qr_i16
2538
1.14M
    14306517U,  // MVE_VSUB_qr_i32
2539
1.14M
    15355093U,  // MVE_VSUB_qr_i8
2540
1.14M
    8015061U, // MVE_VSUBf16
2541
1.14M
    8539349U, // MVE_VSUBf32
2542
1.14M
    14830805U,  // MVE_VSUBi16
2543
1.14M
    14306517U,  // MVE_VSUBi32
2544
1.14M
    15355093U,  // MVE_VSUBi8
2545
1.14M
    942752751U, // MVE_WLSTP_16
2546
1.14M
    942751998U, // MVE_WLSTP_32
2547
1.14M
    942752360U, // MVE_WLSTP_64
2548
1.14M
    942753409U, // MVE_WLSTP_8
2549
1.14M
    2658546U, // MVNi
2550
1.14M
    2658546U, // MVNr
2551
1.14M
    2633970U, // MVNsi
2552
1.14M
    2691314U, // MVNsr
2553
1.14M
    942752186U, // NEON_VMAXNMNDf
2554
1.14M
    942753081U, // NEON_VMAXNMNDh
2555
1.14M
    942752186U, // NEON_VMAXNMNQf
2556
1.14M
    942753081U, // NEON_VMAXNMNQh
2557
1.14M
    942752174U, // NEON_VMINNMNDf
2558
1.14M
    942753069U, // NEON_VMINNMNDh
2559
1.14M
    942752174U, // NEON_VMINNMNQf
2560
1.14M
    942753069U, // NEON_VMINNMNQh
2561
1.14M
    2634206U, // ORRri
2562
1.14M
    2634206U, // ORRrr
2563
1.14M
    2691550U, // ORRrsi
2564
1.14M
    78302U, // ORRrsr
2565
1.14M
    2667147U, // PKHBT
2566
1.14M
    2665630U, // PKHTB
2567
1.14M
    264176U,  // PLDWi12
2568
1.14M
    272368U,  // PLDWrs
2569
1.14M
    264010U,  // PLDi12
2570
1.14M
    272202U,  // PLDrs
2571
1.14M
    264056U,  // PLIi12
2572
1.14M
    272248U,  // PLIrs
2573
1.14M
    2682226U, // QADD
2574
1.14M
    2681301U, // QADD16
2575
1.14M
    2681404U, // QADD8
2576
1.14M
    2684343U, // QASX
2577
1.14M
    2682200U, // QDADD
2578
1.14M
    2682051U, // QDSUB
2579
1.14M
    2684089U, // QSAX
2580
1.14M
    2682064U, // QSUB
2581
1.14M
    2681263U, // QSUB16
2582
1.14M
    2681365U, // QSUB8
2583
1.14M
    2650838U, // RBIT
2584
1.14M
    2651162U, // REV
2585
1.14M
    2648569U, // REV16
2586
1.14M
    2649778U, // REVSH
2587
1.14M
    4802283U, // RFEDA
2588
1.14M
    25249515U,  // RFEDA_UPD
2589
1.14M
    4802314U, // RFEDB
2590
1.14M
    25249546U,  // RFEDB_UPD
2591
1.14M
    4802290U, // RFEIA
2592
1.14M
    25249522U,  // RFEIA_UPD
2593
1.14M
    4802321U, // RFEIB
2594
1.14M
    25249553U,  // RFEIB_UPD
2595
1.14M
    2632847U, // RSBri
2596
1.14M
    2632847U, // RSBrr
2597
1.14M
    2690191U, // RSBrsi
2598
1.14M
    76943U, // RSBrsr
2599
1.14M
    2633006U, // RSCri
2600
1.14M
    2633006U, // RSCrr
2601
1.14M
    2690350U, // RSCrsi
2602
1.14M
    77102U, // RSCrsr
2603
1.14M
    2681308U, // SADD16
2604
1.14M
    2681410U, // SADD8
2605
1.14M
    2684348U, // SASX
2606
1.14M
    3206U,  // SB
2607
1.14M
    2632965U, // SBCri
2608
1.14M
    2632965U, // SBCrr
2609
1.14M
    2690309U, // SBCrsi
2610
1.14M
    77061U, // SBCrsr
2611
1.14M
    2667857U, // SBFX
2612
1.14M
    2683934U, // SDIV
2613
1.14M
    2682745U, // SEL
2614
1.14M
    280399U,  // SETEND
2615
1.14M
    4802460U, // SETPAN
2616
1.14M
    875643072U, // SHA1C
2617
1.14M
    942751946U, // SHA1H
2618
1.14M
    875643104U, // SHA1M
2619
1.14M
    875643114U, // SHA1P
2620
1.14M
    875642927U, // SHA1SU0
2621
1.14M
    875642993U, // SHA1SU1
2622
1.14M
    875643092U, // SHA256H
2623
1.14M
    875643039U, // SHA256H2
2624
1.14M
    875642939U, // SHA256SU0
2625
1.14M
    875643005U, // SHA256SU1
2626
1.14M
    2681284U, // SHADD16
2627
1.14M
    2681389U, // SHADD8
2628
1.14M
    2684330U, // SHASX
2629
1.14M
    2684076U, // SHSAX
2630
1.14M
    2681246U, // SHSUB16
2631
1.14M
    2681350U, // SHSUB8
2632
1.14M
    2731297U, // SMC
2633
1.14M
    2665410U, // SMLABB
2634
1.14M
    2667140U, // SMLABT
2635
1.14M
    2665786U, // SMLAD
2636
1.14M
    2667783U, // SMLADX
2637
1.14M
    290621U,  // SMLAL
2638
1.14M
    2755529U, // SMLALBB
2639
1.14M
    2757265U, // SMLALBT
2640
1.14M
    2755964U, // SMLALD
2641
1.14M
    2757909U, // SMLALDX
2642
1.14M
    2755748U, // SMLALTB
2643
1.14M
    2757507U, // SMLALTT
2644
1.14M
    2665623U, // SMLATB
2645
1.14M
    2667388U, // SMLATT
2646
1.14M
    2665690U, // SMLAWB
2647
1.14M
    2667442U, // SMLAWT
2648
1.14M
    2665887U, // SMLSD
2649
1.14M
    2667813U, // SMLSDX
2650
1.14M
    2755975U, // SMLSLD
2651
1.14M
    2757917U, // SMLSLDX
2652
1.14M
    2665256U, // SMMLA
2653
1.14M
    2666902U, // SMMLAR
2654
1.14M
    2667051U, // SMMLS
2655
1.14M
    2666982U, // SMMLSR
2656
1.14M
    2682930U, // SMMUL
2657
1.14M
    2683336U, // SMMULR
2658
1.14M
    2682176U, // SMUAD
2659
1.14M
    2684174U, // SMUADX
2660
1.14M
    2681809U, // SMULBB
2661
1.14M
    2683545U, // SMULBT
2662
1.14M
    2691043U, // SMULL
2663
1.14M
    2682028U, // SMULTB
2664
1.14M
    2683787U, // SMULTT
2665
1.14M
    2682081U, // SMULWB
2666
1.14M
    2683833U, // SMULWT
2667
1.14M
    2682277U, // SMUSD
2668
1.14M
    2684204U, // SMUSDX
2669
1.14M
    4802618U, // SRSDA
2670
1.14M
    4802570U, // SRSDA_UPD
2671
1.14M
    4802640U, // SRSDB
2672
1.14M
    4802594U, // SRSDB_UPD
2673
1.14M
    4802629U, // SRSIA
2674
1.14M
    4802582U, // SRSIA_UPD
2675
1.14M
    4802651U, // SRSIB
2676
1.14M
    4802606U, // SRSIB_UPD
2677
1.14M
    2667125U, // SSAT
2678
1.14M
    2681322U, // SSAT16
2679
1.14M
    2684094U, // SSAX
2680
1.14M
    2681270U, // SSUB16
2681
1.14M
    2681371U, // SSUB8
2682
1.14M
    1620223881U,  // STC2L_OFFSET
2683
1.14M
    1687332745U,  // STC2L_OPTION
2684
1.14M
    1687332745U,  // STC2L_POST
2685
1.14M
    1754441609U,  // STC2L_PRE
2686
1.14M
    1620222521U,  // STC2_OFFSET
2687
1.14M
    1687331385U,  // STC2_OPTION
2688
1.14M
    1687331385U,  // STC2_POST
2689
1.14M
    1754440249U,  // STC2_PRE
2690
1.14M
    1344843615U,  // STCL_OFFSET
2691
1.14M
    1344843615U,  // STCL_OPTION
2692
1.14M
    1344843615U,  // STCL_POST
2693
1.14M
    1344843615U,  // STCL_PRE
2694
1.14M
    1344843058U,  // STC_OFFSET
2695
1.14M
    1344843058U,  // STC_OPTION
2696
1.14M
    1344843058U,  // STC_POST
2697
1.14M
    1344843058U,  // STC_PRE
2698
1.14M
    2650152U, // STL
2699
1.14M
    2649113U, // STLB
2700
1.14M
    2684217U, // STLEX
2701
1.14M
    2682095U, // STLEXB
2702
1.14M
    2682290U, // STLEXD
2703
1.14M
    2682591U, // STLEXH
2704
1.14M
    2649692U, // STLH
2705
1.14M
    2730730U, // STMDA
2706
1.14M
    942172906U, // STMDA_UPD
2707
1.14M
    2730986U, // STMDB
2708
1.14M
    942173162U, // STMDB_UPD
2709
1.14M
    2732142U, // STMIA
2710
1.14M
    942174318U, // STMIA_UPD
2711
1.14M
    2731004U, // STMIB
2712
1.14M
    942173180U, // STMIB_UPD
2713
1.14M
    942199462U, // STRBT_POST_IMM
2714
1.14M
    942199462U, // STRBT_POST_REG
2715
1.14M
    942197888U, // STRB_POST_IMM
2716
1.14M
    942197888U, // STRB_POST_REG
2717
1.14M
    942189696U, // STRB_PRE_IMM
2718
1.14M
    942197888U, // STRB_PRE_REG
2719
1.14M
    2681984U, // STRBi12
2720
1.14M
    2665600U, // STRBrs
2721
1.14M
    2674074U, // STRD
2722
1.14M
    942280090U, // STRD_POST
2723
1.14M
    942280090U, // STRD_PRE
2724
1.14M
    2684235U, // STREX
2725
1.14M
    2682109U, // STREXB
2726
1.14M
    2682304U, // STREXD
2727
1.14M
    2682605U, // STREXH
2728
1.14M
    2666118U, // STRH
2729
1.14M
    942191305U, // STRHTi
2730
1.14M
    942199497U, // STRHTr
2731
1.14M
    942198406U, // STRH_POST
2732
1.14M
    942198406U, // STRH_PRE
2733
1.14M
    942199661U, // STRT_POST_IMM
2734
1.14M
    942199661U, // STRT_POST_REG
2735
1.14M
    942199296U, // STR_POST_IMM
2736
1.14M
    942199296U, // STR_POST_REG
2737
1.14M
    942191104U, // STR_PRE_IMM
2738
1.14M
    942199296U, // STR_PRE_REG
2739
1.14M
    2683392U, // STRi12
2740
1.14M
    2667008U, // STRrs
2741
1.14M
    2632901U, // SUBri
2742
1.14M
    2632901U, // SUBrr
2743
1.14M
    2690245U, // SUBrsi
2744
1.14M
    76997U, // SUBrsr
2745
1.14M
    2731318U, // SVC
2746
1.14M
    2683268U, // SWP
2747
1.14M
    2681972U, // SWPB
2748
1.14M
    2665398U, // SXTAB
2749
1.14M
    2664832U, // SXTAB16
2750
1.14M
    2666022U, // SXTAH
2751
1.14M
    2682041U, // SXTB
2752
1.14M
    2681232U, // SXTB16
2753
1.14M
    2682552U, // SXTH
2754
1.14M
    2650514U, // TEQri
2755
1.14M
    2650514U, // TEQrr
2756
1.14M
    2683282U, // TEQrsi
2757
1.14M
    2666898U, // TEQrsr
2758
1.14M
    4355U,  // TRAP
2759
1.14M
    4355U,  // TRAPNaCl
2760
1.14M
    296743U,  // TSB
2761
1.14M
    2651000U, // TSTri
2762
1.14M
    2651000U, // TSTrr
2763
1.14M
    2683768U, // TSTrsi
2764
1.14M
    2667384U, // TSTrsr
2765
1.14M
    2681315U, // UADD16
2766
1.14M
    2681416U, // UADD8
2767
1.14M
    2684353U, // UASX
2768
1.14M
    2667862U, // UBFX
2769
1.14M
    4802395U, // UDF
2770
1.14M
    2683939U, // UDIV
2771
1.14M
    2681292U, // UHADD16
2772
1.14M
    2681396U, // UHADD8
2773
1.14M
    2684336U, // UHASX
2774
1.14M
    2684082U, // UHSAX
2775
1.14M
    2681254U, // UHSUB16
2776
1.14M
    2681357U, // UHSUB8
2777
1.14M
    2756386U, // UMAAL
2778
1.14M
    290627U,  // UMLAL
2779
1.14M
    2691049U, // UMULL
2780
1.14M
    2681300U, // UQADD16
2781
1.14M
    2681403U, // UQADD8
2782
1.14M
    2684342U, // UQASX
2783
1.14M
    2684088U, // UQSAX
2784
1.14M
    2681262U, // UQSUB16
2785
1.14M
    2681364U, // UQSUB8
2786
1.14M
    2681383U, // USAD8
2787
1.14M
    2664959U, // USADA8
2788
1.14M
    2667130U, // USAT
2789
1.14M
    2681329U, // USAT16
2790
1.14M
    2684099U, // USAX
2791
1.14M
    2681277U, // USUB16
2792
1.14M
    2681377U, // USUB8
2793
1.14M
    2665404U, // UXTAB
2794
1.14M
    2664840U, // UXTAB16
2795
1.14M
    2666028U, // UXTAH
2796
1.14M
    2682046U, // UXTB
2797
1.14M
    2681239U, // UXTB16
2798
1.14M
    2682557U, // UXTH
2799
1.14M
    11579176U,  // VABALsv2i64
2800
1.14M
    11054888U,  // VABALsv4i32
2801
1.14M
    12103464U,  // VABALsv8i16
2802
1.14M
    13152040U,  // VABALuv2i64
2803
1.14M
    12627752U,  // VABALuv4i32
2804
1.14M
    13676328U,  // VABALuv8i16
2805
1.14M
    12102345U,  // VABAsv16i8
2806
1.14M
    11578057U,  // VABAsv2i32
2807
1.14M
    11053769U,  // VABAsv4i16
2808
1.14M
    11578057U,  // VABAsv4i32
2809
1.14M
    11053769U,  // VABAsv8i16
2810
1.14M
    12102345U,  // VABAsv8i8
2811
1.14M
    13675209U,  // VABAuv16i8
2812
1.14M
    13150921U,  // VABAuv2i32
2813
1.14M
    12626633U,  // VABAuv4i16
2814
1.14M
    13150921U,  // VABAuv4i32
2815
1.14M
    12626633U,  // VABAuv8i16
2816
1.14M
    13675209U,  // VABAuv8i8
2817
1.14M
    11595620U,  // VABDLsv2i64
2818
1.14M
    11071332U,  // VABDLsv4i32
2819
1.14M
    12119908U,  // VABDLsv8i16
2820
1.14M
    13168484U,  // VABDLuv2i64
2821
1.14M
    12644196U,  // VABDLuv4i32
2822
1.14M
    13692772U,  // VABDLuv8i16
2823
1.14M
    8449350U, // VABDfd
2824
1.14M
    8449350U, // VABDfq
2825
1.14M
    7925062U, // VABDhd
2826
1.14M
    7925062U, // VABDhq
2827
1.14M
    12119366U,  // VABDsv16i8
2828
1.14M
    11595078U,  // VABDsv2i32
2829
1.14M
    11070790U,  // VABDsv4i16
2830
1.14M
    11595078U,  // VABDsv4i32
2831
1.14M
    11070790U,  // VABDsv8i16
2832
1.14M
    12119366U,  // VABDsv8i8
2833
1.14M
    13692230U,  // VABDuv16i8
2834
1.14M
    13167942U,  // VABDuv2i32
2835
1.14M
    12643654U,  // VABDuv4i16
2836
1.14M
    13167942U,  // VABDuv4i32
2837
1.14M
    12643654U,  // VABDuv8i16
2838
1.14M
    13692230U,  // VABDuv8i8
2839
1.14M
    1282437660U,  // VABSD
2840
1.14M
    7893532U, // VABSH
2841
1.14M
    8417820U, // VABSS
2842
1.14M
    8417820U, // VABSfd
2843
1.14M
    8417820U, // VABSfq
2844
1.14M
    7893532U, // VABShd
2845
1.14M
    7893532U, // VABShq
2846
1.14M
    12087836U,  // VABSv16i8
2847
1.14M
    11563548U,  // VABSv2i32
2848
1.14M
    11039260U,  // VABSv4i16
2849
1.14M
    11563548U,  // VABSv4i32
2850
1.14M
    11039260U,  // VABSv8i16
2851
1.14M
    12087836U,  // VABSv8i8
2852
1.14M
    8449479U, // VACGEfd
2853
1.14M
    8449479U, // VACGEfq
2854
1.14M
    7925191U, // VACGEhd
2855
1.14M
    7925191U, // VACGEhq
2856
1.14M
    8450744U, // VACGTfd
2857
1.14M
    8450744U, // VACGTfq
2858
1.14M
    7926456U, // VACGThd
2859
1.14M
    7926456U, // VACGThq
2860
1.14M
    1282469239U,  // VADDD
2861
1.14M
    7925111U, // VADDH
2862
1.14M
    962654351U, // VADDHNv2i32
2863
1.14M
    14217359U,  // VADDHNv4i16
2864
1.14M
    14741647U,  // VADDHNv8i8
2865
1.14M
    11595633U,  // VADDLsv2i64
2866
1.14M
    11071345U,  // VADDLsv4i32
2867
1.14M
    12119921U,  // VADDLsv8i16
2868
1.14M
    13168497U,  // VADDLuv2i64
2869
1.14M
    12644209U,  // VADDLuv4i32
2870
1.14M
    13692785U,  // VADDLuv8i16
2871
1.14M
    8449399U, // VADDS
2872
1.14M
    11596891U,  // VADDWsv2i64
2873
1.14M
    11072603U,  // VADDWsv4i32
2874
1.14M
    12121179U,  // VADDWsv8i16
2875
1.14M
    13169755U,  // VADDWuv2i64
2876
1.14M
    12645467U,  // VADDWuv4i32
2877
1.14M
    13694043U,  // VADDWuv8i16
2878
1.14M
    8449399U, // VADDfd
2879
1.14M
    8449399U, // VADDfq
2880
1.14M
    7925111U, // VADDhd
2881
1.14M
    7925111U, // VADDhq
2882
1.14M
    15265143U,  // VADDv16i8
2883
1.14M
    962653559U, // VADDv1i64
2884
1.14M
    14216567U,  // VADDv2i32
2885
1.14M
    962653559U, // VADDv2i64
2886
1.14M
    14740855U,  // VADDv4i16
2887
1.14M
    14216567U,  // VADDv4i32
2888
1.14M
    14740855U,  // VADDv8i16
2889
1.14M
    15265143U,  // VADDv8i8
2890
1.14M
    2682254U, // VANDd
2891
1.14M
    2682254U, // VANDq
2892
1.14M
    1010394566U,  // VBF16MALBQ
2893
1.14M
    1010394566U,  // VBF16MALBQI
2894
1.14M
    1010394578U,  // VBF16MALTQ
2895
1.14M
    1010394578U,  // VBF16MALTQI
2896
1.14M
    2682134U, // VBICd
2897
1.14M
    14216470U,  // VBICiv2i32
2898
1.14M
    14740758U,  // VBICiv4i16
2899
1.14M
    14216470U,  // VBICiv4i32
2900
1.14M
    14740758U,  // VBICiv8i16
2901
1.14M
    2682134U, // VBICq
2902
1.14M
    2665967U, // VBIFd
2903
1.14M
    2665967U, // VBIFq
2904
1.14M
    2667227U, // VBITd
2905
1.14M
    2667227U, // VBITq
2906
1.14M
    2666517U, // VBSLd
2907
1.14M
    2666517U, // VBSLq
2908
1.14M
    0U, // VBSPd
2909
1.14M
    0U, // VBSPq
2910
1.14M
    942752151U, // VCADDv2f32
2911
1.14M
    942753024U, // VCADDv4f16
2912
1.14M
    942752151U, // VCADDv4f32
2913
1.14M
    942753024U, // VCADDv8f16
2914
1.14M
    8450445U, // VCEQfd
2915
1.14M
    8450445U, // VCEQfq
2916
1.14M
    7926157U, // VCEQhd
2917
1.14M
    7926157U, // VCEQhq
2918
1.14M
    15266189U,  // VCEQv16i8
2919
1.14M
    14217613U,  // VCEQv2i32
2920
1.14M
    14741901U,  // VCEQv4i16
2921
1.14M
    14217613U,  // VCEQv4i32
2922
1.14M
    14741901U,  // VCEQv8i16
2923
1.14M
    15266189U,  // VCEQv8i8
2924
1.14M
    15233421U,  // VCEQzv16i8
2925
1.14M
    8417677U, // VCEQzv2f32
2926
1.14M
    14184845U,  // VCEQzv2i32
2927
1.14M
    7893389U, // VCEQzv4f16
2928
1.14M
    8417677U, // VCEQzv4f32
2929
1.14M
    14709133U,  // VCEQzv4i16
2930
1.14M
    14184845U,  // VCEQzv4i32
2931
1.14M
    7893389U, // VCEQzv8f16
2932
1.14M
    14709133U,  // VCEQzv8i16
2933
1.14M
    15233421U,  // VCEQzv8i8
2934
1.14M
    8449485U, // VCGEfd
2935
1.14M
    8449485U, // VCGEfq
2936
1.14M
    7925197U, // VCGEhd
2937
1.14M
    7925197U, // VCGEhq
2938
1.14M
    12119501U,  // VCGEsv16i8
2939
1.14M
    11595213U,  // VCGEsv2i32
2940
1.14M
    11070925U,  // VCGEsv4i16
2941
1.14M
    11595213U,  // VCGEsv4i32
2942
1.14M
    11070925U,  // VCGEsv8i16
2943
1.14M
    12119501U,  // VCGEsv8i8
2944
1.14M
    13692365U,  // VCGEuv16i8
2945
1.14M
    13168077U,  // VCGEuv2i32
2946
1.14M
    12643789U,  // VCGEuv4i16
2947
1.14M
    13168077U,  // VCGEuv4i32
2948
1.14M
    12643789U,  // VCGEuv8i16
2949
1.14M
    13692365U,  // VCGEuv8i8
2950
1.14M
    12086733U,  // VCGEzv16i8
2951
1.14M
    8416717U, // VCGEzv2f32
2952
1.14M
    11562445U,  // VCGEzv2i32
2953
1.14M
    7892429U, // VCGEzv4f16
2954
1.14M
    8416717U, // VCGEzv4f32
2955
1.14M
    11038157U,  // VCGEzv4i16
2956
1.14M
    11562445U,  // VCGEzv4i32
2957
1.14M
    7892429U, // VCGEzv8f16
2958
1.14M
    11038157U,  // VCGEzv8i16
2959
1.14M
    12086733U,  // VCGEzv8i8
2960
1.14M
    8450750U, // VCGTfd
2961
1.14M
    8450750U, // VCGTfq
2962
1.14M
    7926462U, // VCGThd
2963
1.14M
    7926462U, // VCGThq
2964
1.14M
    12120766U,  // VCGTsv16i8
2965
1.14M
    11596478U,  // VCGTsv2i32
2966
1.14M
    11072190U,  // VCGTsv4i16
2967
1.14M
    11596478U,  // VCGTsv4i32
2968
1.14M
    11072190U,  // VCGTsv8i16
2969
1.14M
    12120766U,  // VCGTsv8i8
2970
1.14M
    13693630U,  // VCGTuv16i8
2971
1.14M
    13169342U,  // VCGTuv2i32
2972
1.14M
    12645054U,  // VCGTuv4i16
2973
1.14M
    13169342U,  // VCGTuv4i32
2974
1.14M
    12645054U,  // VCGTuv8i16
2975
1.14M
    13693630U,  // VCGTuv8i8
2976
1.14M
    12087998U,  // VCGTzv16i8
2977
1.14M
    8417982U, // VCGTzv2f32
2978
1.14M
    11563710U,  // VCGTzv2i32
2979
1.14M
    7893694U, // VCGTzv4f16
2980
1.14M
    8417982U, // VCGTzv4f32
2981
1.14M
    11039422U,  // VCGTzv4i16
2982
1.14M
    11563710U,  // VCGTzv4i32
2983
1.14M
    7893694U, // VCGTzv8f16
2984
1.14M
    11039422U,  // VCGTzv8i16
2985
1.14M
    12087998U,  // VCGTzv8i8
2986
1.14M
    12086738U,  // VCLEzv16i8
2987
1.14M
    8416722U, // VCLEzv2f32
2988
1.14M
    11562450U,  // VCLEzv2i32
2989
1.14M
    7892434U, // VCLEzv4f16
2990
1.14M
    8416722U, // VCLEzv4f32
2991
1.14M
    11038162U,  // VCLEzv4i16
2992
1.14M
    11562450U,  // VCLEzv4i32
2993
1.14M
    7892434U, // VCLEzv8f16
2994
1.14M
    11038162U,  // VCLEzv8i16
2995
1.14M
    12086738U,  // VCLEzv8i8
2996
1.14M
    12087846U,  // VCLSv16i8
2997
1.14M
    11563558U,  // VCLSv2i32
2998
1.14M
    11039270U,  // VCLSv4i16
2999
1.14M
    11563558U,  // VCLSv4i32
3000
1.14M
    11039270U,  // VCLSv8i16
3001
1.14M
    12087846U,  // VCLSv8i8
3002
1.14M
    12088032U,  // VCLTzv16i8
3003
1.14M
    8418016U, // VCLTzv2f32
3004
1.14M
    11563744U,  // VCLTzv2i32
3005
1.14M
    7893728U, // VCLTzv4f16
3006
1.14M
    8418016U, // VCLTzv4f32
3007
1.14M
    11039456U,  // VCLTzv4i16
3008
1.14M
    11563744U,  // VCLTzv4i32
3009
1.14M
    7893728U, // VCLTzv8f16
3010
1.14M
    11039456U,  // VCLTzv8i16
3011
1.14M
    12088032U,  // VCLTzv8i8
3012
1.14M
    15234547U,  // VCLZv16i8
3013
1.14M
    14185971U,  // VCLZv2i32
3014
1.14M
    14710259U,  // VCLZv4i16
3015
1.14M
    14185971U,  // VCLZv4i32
3016
1.14M
    14710259U,  // VCLZv8i16
3017
1.14M
    15234547U,  // VCLZv8i8
3018
1.14M
    875643264U, // VCMLAv2f32
3019
1.14M
    875643264U, // VCMLAv2f32_indexed
3020
1.14M
    875644137U, // VCMLAv4f16
3021
1.14M
    875644137U, // VCMLAv4f16_indexed
3022
1.14M
    875643264U, // VCMLAv4f32
3023
1.14M
    875643264U, // VCMLAv4f32_indexed
3024
1.14M
    875644137U, // VCMLAv8f16
3025
1.14M
    875644137U, // VCMLAv8f16_indexed
3026
1.14M
    1282437393U,  // VCMPD
3027
1.14M
    1282436574U,  // VCMPED
3028
1.14M
    7892446U, // VCMPEH
3029
1.14M
    8416734U, // VCMPES
3030
1.14M
    2154933726U,  // VCMPEZD
3031
1.14M
    7974366U, // VCMPEZH
3032
1.14M
    8498654U, // VCMPEZS
3033
1.14M
    7893265U, // VCMPH
3034
1.14M
    8417553U, // VCMPS
3035
1.14M
    2154934545U,  // VCMPZD
3036
1.14M
    7975185U, // VCMPZH
3037
1.14M
    8499473U, // VCMPZS
3038
1.14M
    1602307U, // VCNTd
3039
1.14M
    1602307U, // VCNTq
3040
1.14M
    942752008U, // VCVTANSDf
3041
1.14M
    942752881U, // VCVTANSDh
3042
1.14M
    942752008U, // VCVTANSQf
3043
1.14M
    942752881U, // VCVTANSQh
3044
1.14M
    942752068U, // VCVTANUDf
3045
1.14M
    942752941U, // VCVTANUDh
3046
1.14M
    942752068U, // VCVTANUQf
3047
1.14M
    942752941U, // VCVTANUQh
3048
1.14M
    942752370U, // VCVTASD
3049
1.14M
    942752761U, // VCVTASH
3050
1.14M
    942752008U, // VCVTASS
3051
1.14M
    942752430U, // VCVTAUD
3052
1.14M
    942752821U, // VCVTAUH
3053
1.14M
    942752068U, // VCVTAUS
3054
1.14M
    25750707U,  // VCVTBDH
3055
1.14M
    26242227U,  // VCVTBHD
3056
1.14M
    17853619U,  // VCVTBHS
3057
1.14M
    888728755U, // VCVTBSH
3058
1.14M
    26768296U,  // VCVTDS
3059
1.14M
    942752023U, // VCVTMNSDf
3060
1.14M
    942752896U, // VCVTMNSDh
3061
1.14M
    942752023U, // VCVTMNSQf
3062
1.14M
    942752896U, // VCVTMNSQh
3063
1.14M
    942752083U, // VCVTMNUDf
3064
1.14M
    942752956U, // VCVTMNUDh
3065
1.14M
    942752083U, // VCVTMNUQf
3066
1.14M
    942752956U, // VCVTMNUQh
3067
1.14M
    942752385U, // VCVTMSD
3068
1.14M
    942752776U, // VCVTMSH
3069
1.14M
    942752023U, // VCVTMSS
3070
1.14M
    942752445U, // VCVTMUD
3071
1.14M
    942752836U, // VCVTMUH
3072
1.14M
    942752083U, // VCVTMUS
3073
1.14M
    942752038U, // VCVTNNSDf
3074
1.14M
    942752911U, // VCVTNNSDh
3075
1.14M
    942752038U, // VCVTNNSQf
3076
1.14M
    942752911U, // VCVTNNSQh
3077
1.14M
    942752098U, // VCVTNNUDf
3078
1.14M
    942752971U, // VCVTNNUDh
3079
1.14M
    942752098U, // VCVTNNUQf
3080
1.14M
    942752971U, // VCVTNNUQh
3081
1.14M
    942752400U, // VCVTNSD
3082
1.14M
    942752791U, // VCVTNSH
3083
1.14M
    942752038U, // VCVTNSS
3084
1.14M
    942752460U, // VCVTNUD
3085
1.14M
    942752851U, // VCVTNUH
3086
1.14M
    942752098U, // VCVTNUS
3087
1.14M
    942752053U, // VCVTPNSDf
3088
1.14M
    942752926U, // VCVTPNSDh
3089
1.14M
    942752053U, // VCVTPNSQf
3090
1.14M
    942752926U, // VCVTPNSQh
3091
1.14M
    942752113U, // VCVTPNUDf
3092
1.14M
    942752986U, // VCVTPNUDh
3093
1.14M
    942752113U, // VCVTPNUQf
3094
1.14M
    942752986U, // VCVTPNUQh
3095
1.14M
    942752415U, // VCVTPSD
3096
1.14M
    942752806U, // VCVTPSH
3097
1.14M
    942752053U, // VCVTPSS
3098
1.14M
    942752475U, // VCVTPUD
3099
1.14M
    942752866U, // VCVTPUH
3100
1.14M
    942752113U, // VCVTPUS
3101
1.14M
    27292584U,  // VCVTSD
3102
1.14M
    25752470U,  // VCVTTDH
3103
1.14M
    26243990U,  // VCVTTHD
3104
1.14M
    17855382U,  // VCVTTHS
3105
1.14M
    888730518U, // VCVTTSH
3106
1.14M
    955806632U, // VCVTf2h
3107
1.14M
    1227912104U,  // VCVTf2sd
3108
1.14M
    1227912104U,  // VCVTf2sq
3109
1.14M
    1228960680U,  // VCVTf2ud
3110
1.14M
    1228960680U,  // VCVTf2uq
3111
1.14M
    1295053736U,  // VCVTf2xsd
3112
1.14M
    1295053736U,  // VCVTf2xsq
3113
1.14M
    1296102312U,  // VCVTf2xud
3114
1.14M
    1296102312U,  // VCVTf2xuq
3115
1.14M
    17855400U,  // VCVTh2f
3116
1.14M
    1227387816U,  // VCVTh2sd
3117
1.14M
    1227387816U,  // VCVTh2sq
3118
1.14M
    1228436392U,  // VCVTh2ud
3119
1.14M
    1228436392U,  // VCVTh2uq
3120
1.14M
    1294529448U,  // VCVTh2xsd
3121
1.14M
    1294529448U,  // VCVTh2xsq
3122
1.14M
    1295578024U,  // VCVTh2xud
3123
1.14M
    1295578024U,  // VCVTh2xuq
3124
1.14M
    1226339240U,  // VCVTs2fd
3125
1.14M
    1226339240U,  // VCVTs2fq
3126
1.14M
    1224766376U,  // VCVTs2hd
3127
1.14M
    1224766376U,  // VCVTs2hq
3128
1.14M
    1226863528U,  // VCVTu2fd
3129
1.14M
    1226863528U,  // VCVTu2fq
3130
1.14M
    1225290664U,  // VCVTu2hd
3131
1.14M
    1225290664U,  // VCVTu2hq
3132
1.14M
    1293480872U,  // VCVTxs2fd
3133
1.14M
    1293480872U,  // VCVTxs2fq
3134
1.14M
    1291908008U,  // VCVTxs2hd
3135
1.14M
    1291908008U,  // VCVTxs2hq
3136
1.14M
    1294005160U,  // VCVTxu2fd
3137
1.14M
    1294005160U,  // VCVTxu2fq
3138
1.14M
    1292432296U,  // VCVTxu2hd
3139
1.14M
    1292432296U,  // VCVTxu2hq
3140
1.14M
    1282470952U,  // VDIVD
3141
1.14M
    7926824U, // VDIVH
3142
1.14M
    8451112U, // VDIVS
3143
1.14M
    553328U,  // VDUP16d
3144
1.14M
    553328U,  // VDUP16q
3145
1.14M
    1077616U, // VDUP32d
3146
1.14M
    1077616U, // VDUP32q
3147
1.14M
    1601904U, // VDUP8d
3148
1.14M
    1601904U, // VDUP8q
3149
1.14M
    586096U,  // VDUPLN16d
3150
1.14M
    586096U,  // VDUPLN16q
3151
1.14M
    1110384U, // VDUPLN32d
3152
1.14M
    1110384U, // VDUPLN32q
3153
1.14M
    1634672U, // VDUPLN8d
3154
1.14M
    1634672U, // VDUPLN8q
3155
1.14M
    2683343U, // VEORd
3156
1.14M
    2683343U, // VEORq
3157
1.14M
    570304U,  // VEXTd16
3158
1.14M
    1094592U, // VEXTd32
3159
1.14M
    1618880U, // VEXTd8
3160
1.14M
    570304U,  // VEXTq16
3161
1.14M
    1094592U, // VEXTq32
3162
1.14M
    15774656U,  // VEXTq64
3163
1.14M
    1618880U, // VEXTq8
3164
1.14M
    1282452281U,  // VFMAD
3165
1.14M
    7908153U, // VFMAH
3166
1.14M
    942753047U, // VFMALD
3167
1.14M
    942753047U, // VFMALDI
3168
1.14M
    942753047U, // VFMALQ
3169
1.14M
    942753047U, // VFMALQI
3170
1.14M
    8432441U, // VFMAS
3171
1.14M
    8432441U, // VFMAfd
3172
1.14M
    8432441U, // VFMAfq
3173
1.14M
    7908153U, // VFMAhd
3174
1.14M
    7908153U, // VFMAhq
3175
1.14M
    1282454076U,  // VFMSD
3176
1.14M
    7909948U, // VFMSH
3177
1.14M
    942753058U, // VFMSLD
3178
1.14M
    942753058U, // VFMSLDI
3179
1.14M
    942753058U, // VFMSLQ
3180
1.14M
    942753058U, // VFMSLQI
3181
1.14M
    8434236U, // VFMSS
3182
1.14M
    8434236U, // VFMSfd
3183
1.14M
    8434236U, // VFMSfq
3184
1.14M
    7909948U, // VFMShd
3185
1.14M
    7909948U, // VFMShq
3186
1.14M
    1282452286U,  // VFNMAD
3187
1.14M
    7908158U, // VFNMAH
3188
1.14M
    8432446U, // VFNMAS
3189
1.14M
    1282454081U,  // VFNMSD
3190
1.14M
    7909953U, // VFNMSH
3191
1.14M
    8434241U, // VFNMSS
3192
1.14M
    942752526U, // VFP_VMAXNMD
3193
1.14M
    942753081U, // VFP_VMAXNMH
3194
1.14M
    942752186U, // VFP_VMAXNMS
3195
1.14M
    942752514U, // VFP_VMINNMD
3196
1.14M
    942753069U, // VFP_VMINNMH
3197
1.14M
    942752174U, // VFP_VMINNMS
3198
1.14M
    1111114U, // VGETLNi32
3199
1.14M
    11072586U,  // VGETLNs16
3200
1.14M
    12121162U,  // VGETLNs8
3201
1.14M
    12645450U,  // VGETLNu16
3202
1.14M
    13694026U,  // VGETLNu8
3203
1.14M
    12119397U,  // VHADDsv16i8
3204
1.14M
    11595109U,  // VHADDsv2i32
3205
1.14M
    11070821U,  // VHADDsv4i16
3206
1.14M
    11595109U,  // VHADDsv4i32
3207
1.14M
    11070821U,  // VHADDsv8i16
3208
1.14M
    12119397U,  // VHADDsv8i8
3209
1.14M
    13692261U,  // VHADDuv16i8
3210
1.14M
    13167973U,  // VHADDuv2i32
3211
1.14M
    12643685U,  // VHADDuv4i16
3212
1.14M
    13167973U,  // VHADDuv4i32
3213
1.14M
    12643685U,  // VHADDuv8i16
3214
1.14M
    13692261U,  // VHADDuv8i8
3215
1.14M
    12119241U,  // VHSUBsv16i8
3216
1.14M
    11594953U,  // VHSUBsv2i32
3217
1.14M
    11070665U,  // VHSUBsv4i16
3218
1.14M
    11594953U,  // VHSUBsv4i32
3219
1.14M
    11070665U,  // VHSUBsv8i16
3220
1.14M
    12119241U,  // VHSUBsv8i8
3221
1.14M
    13692105U,  // VHSUBuv16i8
3222
1.14M
    13167817U,  // VHSUBuv2i32
3223
1.14M
    12643529U,  // VHSUBuv4i16
3224
1.14M
    13167817U,  // VHSUBuv4i32
3225
1.14M
    12643529U,  // VHSUBuv8i16
3226
1.14M
    13692105U,  // VHSUBuv8i8
3227
1.14M
    875644277U, // VINSH
3228
1.14M
    1235776418U,  // VJCVT
3229
1.14M
    2215176452U,  // VLD1DUPd16
3230
1.14M
    2215160068U,  // VLD1DUPd16wb_fixed
3231
1.14M
    2215168260U,  // VLD1DUPd16wb_register
3232
1.14M
    2215700740U,  // VLD1DUPd32
3233
1.14M
    2215684356U,  // VLD1DUPd32wb_fixed
3234
1.14M
    2215692548U,  // VLD1DUPd32wb_register
3235
1.14M
    2216225028U,  // VLD1DUPd8
3236
1.14M
    2216208644U,  // VLD1DUPd8wb_fixed
3237
1.14M
    2216216836U,  // VLD1DUPd8wb_register
3238
1.14M
    2282285316U,  // VLD1DUPq16
3239
1.14M
    2282268932U,  // VLD1DUPq16wb_fixed
3240
1.14M
    2282277124U,  // VLD1DUPq16wb_register
3241
1.14M
    2282809604U,  // VLD1DUPq32
3242
1.14M
    2282793220U,  // VLD1DUPq32wb_fixed
3243
1.14M
    2282801412U,  // VLD1DUPq32wb_register
3244
1.14M
    2283333892U,  // VLD1DUPq8
3245
1.14M
    2283317508U,  // VLD1DUPq8wb_fixed
3246
1.14M
    2283325700U,  // VLD1DUPq8wb_register
3247
1.14M
    28363012U,  // VLD1LNd16
3248
1.14M
    28616964U,  // VLD1LNd16_UPD
3249
1.14M
    28887300U,  // VLD1LNd32
3250
1.14M
    29141252U,  // VLD1LNd32_UPD
3251
1.14M
    29411588U,  // VLD1LNd8
3252
1.14M
    29665540U,  // VLD1LNd8_UPD
3253
1.14M
    0U, // VLD1LNq16Pseudo
3254
1.14M
    0U, // VLD1LNq16Pseudo_UPD
3255
1.14M
    0U, // VLD1LNq32Pseudo
3256
1.14M
    0U, // VLD1LNq32Pseudo_UPD
3257
1.14M
    0U, // VLD1LNq8Pseudo
3258
1.14M
    0U, // VLD1LNq8Pseudo_UPD
3259
1.14M
    2349394180U,  // VLD1d16
3260
1.14M
    537454852U, // VLD1d16Q
3261
1.14M
    0U, // VLD1d16QPseudo
3262
1.14M
    0U, // VLD1d16QPseudoWB_fixed
3263
1.14M
    0U, // VLD1d16QPseudoWB_register
3264
1.14M
    537438468U, // VLD1d16Qwb_fixed
3265
1.14M
    537446660U, // VLD1d16Qwb_register
3266
1.14M
    269019396U, // VLD1d16T
3267
1.14M
    0U, // VLD1d16TPseudo
3268
1.14M
    0U, // VLD1d16TPseudoWB_fixed
3269
1.14M
    0U, // VLD1d16TPseudoWB_register
3270
1.14M
    269003012U, // VLD1d16Twb_fixed
3271
1.14M
    269011204U, // VLD1d16Twb_register
3272
1.14M
    2349377796U,  // VLD1d16wb_fixed
3273
1.14M
    2349385988U,  // VLD1d16wb_register
3274
1.14M
    2349918468U,  // VLD1d32
3275
1.14M
    537979140U, // VLD1d32Q
3276
1.14M
    0U, // VLD1d32QPseudo
3277
1.14M
    0U, // VLD1d32QPseudoWB_fixed
3278
1.14M
    0U, // VLD1d32QPseudoWB_register
3279
1.14M
    537962756U, // VLD1d32Qwb_fixed
3280
1.14M
    537970948U, // VLD1d32Qwb_register
3281
1.14M
    269543684U, // VLD1d32T
3282
1.14M
    0U, // VLD1d32TPseudo
3283
1.14M
    0U, // VLD1d32TPseudoWB_fixed
3284
1.14M
    0U, // VLD1d32TPseudoWB_register
3285
1.14M
    269527300U, // VLD1d32Twb_fixed
3286
1.14M
    269535492U, // VLD1d32Twb_register
3287
1.14M
    2349902084U,  // VLD1d32wb_fixed
3288
1.14M
    2349910276U,  // VLD1d32wb_register
3289
1.14M
    2364598532U,  // VLD1d64
3290
1.14M
    552659204U, // VLD1d64Q
3291
1.14M
    0U, // VLD1d64QPseudo
3292
1.14M
    0U, // VLD1d64QPseudoWB_fixed
3293
1.14M
    0U, // VLD1d64QPseudoWB_register
3294
1.14M
    552642820U, // VLD1d64Qwb_fixed
3295
1.14M
    552651012U, // VLD1d64Qwb_register
3296
1.14M
    284223748U, // VLD1d64T
3297
1.14M
    0U, // VLD1d64TPseudo
3298
1.14M
    0U, // VLD1d64TPseudoWB_fixed
3299
1.14M
    0U, // VLD1d64TPseudoWB_register
3300
1.14M
    284207364U, // VLD1d64Twb_fixed
3301
1.14M
    284215556U, // VLD1d64Twb_register
3302
1.14M
    2364582148U,  // VLD1d64wb_fixed
3303
1.14M
    2364590340U,  // VLD1d64wb_register
3304
1.14M
    2350442756U,  // VLD1d8
3305
1.14M
    538503428U, // VLD1d8Q
3306
1.14M
    0U, // VLD1d8QPseudo
3307
1.14M
    0U, // VLD1d8QPseudoWB_fixed
3308
1.14M
    0U, // VLD1d8QPseudoWB_register
3309
1.14M
    538487044U, // VLD1d8Qwb_fixed
3310
1.14M
    538495236U, // VLD1d8Qwb_register
3311
1.14M
    270067972U, // VLD1d8T
3312
1.14M
    0U, // VLD1d8TPseudo
3313
1.14M
    0U, // VLD1d8TPseudoWB_fixed
3314
1.14M
    0U, // VLD1d8TPseudoWB_register
3315
1.14M
    270051588U, // VLD1d8Twb_fixed
3316
1.14M
    270059780U, // VLD1d8Twb_register
3317
1.14M
    2350426372U,  // VLD1d8wb_fixed
3318
1.14M
    2350434564U,  // VLD1d8wb_register
3319
1.14M
    2416503044U,  // VLD1q16
3320
1.14M
    0U, // VLD1q16HighQPseudo
3321
1.14M
    0U, // VLD1q16HighQPseudo_UPD
3322
1.14M
    0U, // VLD1q16HighTPseudo
3323
1.14M
    0U, // VLD1q16HighTPseudo_UPD
3324
1.14M
    0U, // VLD1q16LowQPseudo_UPD
3325
1.14M
    0U, // VLD1q16LowTPseudo_UPD
3326
1.14M
    2416486660U,  // VLD1q16wb_fixed
3327
1.14M
    2416494852U,  // VLD1q16wb_register
3328
1.14M
    2417027332U,  // VLD1q32
3329
1.14M
    0U, // VLD1q32HighQPseudo
3330
1.14M
    0U, // VLD1q32HighQPseudo_UPD
3331
1.14M
    0U, // VLD1q32HighTPseudo
3332
1.14M
    0U, // VLD1q32HighTPseudo_UPD
3333
1.14M
    0U, // VLD1q32LowQPseudo_UPD
3334
1.14M
    0U, // VLD1q32LowTPseudo_UPD
3335
1.14M
    2417010948U,  // VLD1q32wb_fixed
3336
1.14M
    2417019140U,  // VLD1q32wb_register
3337
1.14M
    2431707396U,  // VLD1q64
3338
1.14M
    0U, // VLD1q64HighQPseudo
3339
1.14M
    0U, // VLD1q64HighQPseudo_UPD
3340
1.14M
    0U, // VLD1q64HighTPseudo
3341
1.14M
    0U, // VLD1q64HighTPseudo_UPD
3342
1.14M
    0U, // VLD1q64LowQPseudo_UPD
3343
1.14M
    0U, // VLD1q64LowTPseudo_UPD
3344
1.14M
    2431691012U,  // VLD1q64wb_fixed
3345
1.14M
    2431699204U,  // VLD1q64wb_register
3346
1.14M
    2417551620U,  // VLD1q8
3347
1.14M
    0U, // VLD1q8HighQPseudo
3348
1.14M
    0U, // VLD1q8HighQPseudo_UPD
3349
1.14M
    0U, // VLD1q8HighTPseudo
3350
1.14M
    0U, // VLD1q8HighTPseudo_UPD
3351
1.14M
    0U, // VLD1q8LowQPseudo_UPD
3352
1.14M
    0U, // VLD1q8LowTPseudo_UPD
3353
1.14M
    2417535236U,  // VLD1q8wb_fixed
3354
1.14M
    2417543428U,  // VLD1q8wb_register
3355
1.14M
    2282285365U,  // VLD2DUPd16
3356
1.14M
    2282268981U,  // VLD2DUPd16wb_fixed
3357
1.14M
    2282277173U,  // VLD2DUPd16wb_register
3358
1.14M
    2483611957U,  // VLD2DUPd16x2
3359
1.14M
    2483595573U,  // VLD2DUPd16x2wb_fixed
3360
1.14M
    2483603765U,  // VLD2DUPd16x2wb_register
3361
1.14M
    2282809653U,  // VLD2DUPd32
3362
1.14M
    2282793269U,  // VLD2DUPd32wb_fixed
3363
1.14M
    2282801461U,  // VLD2DUPd32wb_register
3364
1.14M
    2484136245U,  // VLD2DUPd32x2
3365
1.14M
    2484119861U,  // VLD2DUPd32x2wb_fixed
3366
1.14M
    2484128053U,  // VLD2DUPd32x2wb_register
3367
1.14M
    2283333941U,  // VLD2DUPd8
3368
1.14M
    2283317557U,  // VLD2DUPd8wb_fixed
3369
1.14M
    2283325749U,  // VLD2DUPd8wb_register
3370
1.14M
    2484660533U,  // VLD2DUPd8x2
3371
1.14M
    2484644149U,  // VLD2DUPd8x2wb_fixed
3372
1.14M
    2484652341U,  // VLD2DUPd8x2wb_register
3373
1.14M
    0U, // VLD2DUPq16EvenPseudo
3374
1.14M
    0U, // VLD2DUPq16OddPseudo
3375
1.14M
    0U, // VLD2DUPq16OddPseudoWB_fixed
3376
1.14M
    0U, // VLD2DUPq16OddPseudoWB_register
3377
1.14M
    0U, // VLD2DUPq32EvenPseudo
3378
1.14M
    0U, // VLD2DUPq32OddPseudo
3379
1.14M
    0U, // VLD2DUPq32OddPseudoWB_fixed
3380
1.14M
    0U, // VLD2DUPq32OddPseudoWB_register
3381
1.14M
    0U, // VLD2DUPq8EvenPseudo
3382
1.14M
    0U, // VLD2DUPq8OddPseudo
3383
1.14M
    0U, // VLD2DUPq8OddPseudoWB_fixed
3384
1.14M
    0U, // VLD2DUPq8OddPseudoWB_register
3385
1.14M
    28617013U,  // VLD2LNd16
3386
1.14M
    0U, // VLD2LNd16Pseudo
3387
1.14M
    0U, // VLD2LNd16Pseudo_UPD
3388
1.14M
    28625205U,  // VLD2LNd16_UPD
3389
1.14M
    29141301U,  // VLD2LNd32
3390
1.14M
    0U, // VLD2LNd32Pseudo
3391
1.14M
    0U, // VLD2LNd32Pseudo_UPD
3392
1.14M
    29149493U,  // VLD2LNd32_UPD
3393
1.14M
    29665589U,  // VLD2LNd8
3394
1.14M
    0U, // VLD2LNd8Pseudo
3395
1.14M
    0U, // VLD2LNd8Pseudo_UPD
3396
1.14M
    29673781U,  // VLD2LNd8_UPD
3397
1.14M
    28617013U,  // VLD2LNq16
3398
1.14M
    0U, // VLD2LNq16Pseudo
3399
1.14M
    0U, // VLD2LNq16Pseudo_UPD
3400
1.14M
    28625205U,  // VLD2LNq16_UPD
3401
1.14M
    29141301U,  // VLD2LNq32
3402
1.14M
    0U, // VLD2LNq32Pseudo
3403
1.14M
    0U, // VLD2LNq32Pseudo_UPD
3404
1.14M
    29149493U,  // VLD2LNq32_UPD
3405
1.14M
    2550720821U,  // VLD2b16
3406
1.14M
    2550704437U,  // VLD2b16wb_fixed
3407
1.14M
    2550712629U,  // VLD2b16wb_register
3408
1.14M
    2551245109U,  // VLD2b32
3409
1.14M
    2551228725U,  // VLD2b32wb_fixed
3410
1.14M
    2551236917U,  // VLD2b32wb_register
3411
1.14M
    2551769397U,  // VLD2b8
3412
1.14M
    2551753013U,  // VLD2b8wb_fixed
3413
1.14M
    2551761205U,  // VLD2b8wb_register
3414
1.14M
    2416503093U,  // VLD2d16
3415
1.14M
    2416486709U,  // VLD2d16wb_fixed
3416
1.14M
    2416494901U,  // VLD2d16wb_register
3417
1.14M
    2417027381U,  // VLD2d32
3418
1.14M
    2417010997U,  // VLD2d32wb_fixed
3419
1.14M
    2417019189U,  // VLD2d32wb_register
3420
1.14M
    2417551669U,  // VLD2d8
3421
1.14M
    2417535285U,  // VLD2d8wb_fixed
3422
1.14M
    2417543477U,  // VLD2d8wb_register
3423
1.14M
    537454901U, // VLD2q16
3424
1.14M
    0U, // VLD2q16Pseudo
3425
1.14M
    0U, // VLD2q16PseudoWB_fixed
3426
1.14M
    0U, // VLD2q16PseudoWB_register
3427
1.14M
    537438517U, // VLD2q16wb_fixed
3428
1.14M
    537446709U, // VLD2q16wb_register
3429
1.14M
    537979189U, // VLD2q32
3430
1.14M
    0U, // VLD2q32Pseudo
3431
1.14M
    0U, // VLD2q32PseudoWB_fixed
3432
1.14M
    0U, // VLD2q32PseudoWB_register
3433
1.14M
    537962805U, // VLD2q32wb_fixed
3434
1.14M
    537970997U, // VLD2q32wb_register
3435
1.14M
    538503477U, // VLD2q8
3436
1.14M
    0U, // VLD2q8Pseudo
3437
1.14M
    0U, // VLD2q8PseudoWB_fixed
3438
1.14M
    0U, // VLD2q8PseudoWB_register
3439
1.14M
    538487093U, // VLD2q8wb_fixed
3440
1.14M
    538495285U, // VLD2q8wb_register
3441
1.14M
    28363098U,  // VLD3DUPd16
3442
1.14M
    0U, // VLD3DUPd16Pseudo
3443
1.14M
    0U, // VLD3DUPd16Pseudo_UPD
3444
1.14M
    28617050U,  // VLD3DUPd16_UPD
3445
1.14M
    28887386U,  // VLD3DUPd32
3446
1.14M
    0U, // VLD3DUPd32Pseudo
3447
1.14M
    0U, // VLD3DUPd32Pseudo_UPD
3448
1.14M
    29141338U,  // VLD3DUPd32_UPD
3449
1.14M
    29411674U,  // VLD3DUPd8
3450
1.14M
    0U, // VLD3DUPd8Pseudo
3451
1.14M
    0U, // VLD3DUPd8Pseudo_UPD
3452
1.14M
    29665626U,  // VLD3DUPd8_UPD
3453
1.14M
    28363098U,  // VLD3DUPq16
3454
1.14M
    0U, // VLD3DUPq16EvenPseudo
3455
1.14M
    0U, // VLD3DUPq16OddPseudo
3456
1.14M
    0U, // VLD3DUPq16OddPseudo_UPD
3457
1.14M
    28617050U,  // VLD3DUPq16_UPD
3458
1.14M
    28887386U,  // VLD3DUPq32
3459
1.14M
    0U, // VLD3DUPq32EvenPseudo
3460
1.14M
    0U, // VLD3DUPq32OddPseudo
3461
1.14M
    0U, // VLD3DUPq32OddPseudo_UPD
3462
1.14M
    29141338U,  // VLD3DUPq32_UPD
3463
1.14M
    29411674U,  // VLD3DUPq8
3464
1.14M
    0U, // VLD3DUPq8EvenPseudo
3465
1.14M
    0U, // VLD3DUPq8OddPseudo
3466
1.14M
    0U, // VLD3DUPq8OddPseudo_UPD
3467
1.14M
    29665626U,  // VLD3DUPq8_UPD
3468
1.14M
    28625242U,  // VLD3LNd16
3469
1.14M
    0U, // VLD3LNd16Pseudo
3470
1.14M
    0U, // VLD3LNd16Pseudo_UPD
3471
1.14M
    28633434U,  // VLD3LNd16_UPD
3472
1.14M
    29149530U,  // VLD3LNd32
3473
1.14M
    0U, // VLD3LNd32Pseudo
3474
1.14M
    0U, // VLD3LNd32Pseudo_UPD
3475
1.14M
    29157722U,  // VLD3LNd32_UPD
3476
1.14M
    29673818U,  // VLD3LNd8
3477
1.14M
    0U, // VLD3LNd8Pseudo
3478
1.14M
    0U, // VLD3LNd8Pseudo_UPD
3479
1.14M
    29682010U,  // VLD3LNd8_UPD
3480
1.14M
    28625242U,  // VLD3LNq16
3481
1.14M
    0U, // VLD3LNq16Pseudo
3482
1.14M
    0U, // VLD3LNq16Pseudo_UPD
3483
1.14M
    28633434U,  // VLD3LNq16_UPD
3484
1.14M
    29149530U,  // VLD3LNq32
3485
1.14M
    0U, // VLD3LNq32Pseudo
3486
1.14M
    0U, // VLD3LNq32Pseudo_UPD
3487
1.14M
    29157722U,  // VLD3LNq32_UPD
3488
1.14M
    28363098U,  // VLD3d16
3489
1.14M
    0U, // VLD3d16Pseudo
3490
1.14M
    0U, // VLD3d16Pseudo_UPD
3491
1.14M
    28617050U,  // VLD3d16_UPD
3492
1.14M
    28887386U,  // VLD3d32
3493
1.14M
    0U, // VLD3d32Pseudo
3494
1.14M
    0U, // VLD3d32Pseudo_UPD
3495
1.14M
    29141338U,  // VLD3d32_UPD
3496
1.14M
    29411674U,  // VLD3d8
3497
1.14M
    0U, // VLD3d8Pseudo
3498
1.14M
    0U, // VLD3d8Pseudo_UPD
3499
1.14M
    29665626U,  // VLD3d8_UPD
3500
1.14M
    28363098U,  // VLD3q16
3501
1.14M
    0U, // VLD3q16Pseudo_UPD
3502
1.14M
    28617050U,  // VLD3q16_UPD
3503
1.14M
    0U, // VLD3q16oddPseudo
3504
1.14M
    0U, // VLD3q16oddPseudo_UPD
3505
1.14M
    28887386U,  // VLD3q32
3506
1.14M
    0U, // VLD3q32Pseudo_UPD
3507
1.14M
    29141338U,  // VLD3q32_UPD
3508
1.14M
    0U, // VLD3q32oddPseudo
3509
1.14M
    0U, // VLD3q32oddPseudo_UPD
3510
1.14M
    29411674U,  // VLD3q8
3511
1.14M
    0U, // VLD3q8Pseudo_UPD
3512
1.14M
    29665626U,  // VLD3q8_UPD
3513
1.14M
    0U, // VLD3q8oddPseudo
3514
1.14M
    0U, // VLD3q8oddPseudo_UPD
3515
1.14M
    28445046U,  // VLD4DUPd16
3516
1.14M
    0U, // VLD4DUPd16Pseudo
3517
1.14M
    0U, // VLD4DUPd16Pseudo_UPD
3518
1.14M
    28641654U,  // VLD4DUPd16_UPD
3519
1.14M
    28969334U,  // VLD4DUPd32
3520
1.14M
    0U, // VLD4DUPd32Pseudo
3521
1.14M
    0U, // VLD4DUPd32Pseudo_UPD
3522
1.14M
    29165942U,  // VLD4DUPd32_UPD
3523
1.14M
    29493622U,  // VLD4DUPd8
3524
1.14M
    0U, // VLD4DUPd8Pseudo
3525
1.14M
    0U, // VLD4DUPd8Pseudo_UPD
3526
1.14M
    29690230U,  // VLD4DUPd8_UPD
3527
1.14M
    28445046U,  // VLD4DUPq16
3528
1.14M
    0U, // VLD4DUPq16EvenPseudo
3529
1.14M
    0U, // VLD4DUPq16OddPseudo
3530
1.14M
    0U, // VLD4DUPq16OddPseudo_UPD
3531
1.14M
    28641654U,  // VLD4DUPq16_UPD
3532
1.14M
    28969334U,  // VLD4DUPq32
3533
1.14M
    0U, // VLD4DUPq32EvenPseudo
3534
1.14M
    0U, // VLD4DUPq32OddPseudo
3535
1.14M
    0U, // VLD4DUPq32OddPseudo_UPD
3536
1.14M
    29165942U,  // VLD4DUPq32_UPD
3537
1.14M
    29493622U,  // VLD4DUPq8
3538
1.14M
    0U, // VLD4DUPq8EvenPseudo
3539
1.14M
    0U, // VLD4DUPq8OddPseudo
3540
1.14M
    0U, // VLD4DUPq8OddPseudo_UPD
3541
1.14M
    29690230U,  // VLD4DUPq8_UPD
3542
1.14M
    28633462U,  // VLD4LNd16
3543
1.14M
    0U, // VLD4LNd16Pseudo
3544
1.14M
    0U, // VLD4LNd16Pseudo_UPD
3545
1.14M
    28649846U,  // VLD4LNd16_UPD
3546
1.14M
    29157750U,  // VLD4LNd32
3547
1.14M
    0U, // VLD4LNd32Pseudo
3548
1.14M
    0U, // VLD4LNd32Pseudo_UPD
3549
1.14M
    29174134U,  // VLD4LNd32_UPD
3550
1.14M
    29682038U,  // VLD4LNd8
3551
1.14M
    0U, // VLD4LNd8Pseudo
3552
1.14M
    0U, // VLD4LNd8Pseudo_UPD
3553
1.14M
    29698422U,  // VLD4LNd8_UPD
3554
1.14M
    28633462U,  // VLD4LNq16
3555
1.14M
    0U, // VLD4LNq16Pseudo
3556
1.14M
    0U, // VLD4LNq16Pseudo_UPD
3557
1.14M
    28649846U,  // VLD4LNq16_UPD
3558
1.14M
    29157750U,  // VLD4LNq32
3559
1.14M
    0U, // VLD4LNq32Pseudo
3560
1.14M
    0U, // VLD4LNq32Pseudo_UPD
3561
1.14M
    29174134U,  // VLD4LNq32_UPD
3562
1.14M
    28445046U,  // VLD4d16
3563
1.14M
    0U, // VLD4d16Pseudo
3564
1.14M
    0U, // VLD4d16Pseudo_UPD
3565
1.14M
    28641654U,  // VLD4d16_UPD
3566
1.14M
    28969334U,  // VLD4d32
3567
1.14M
    0U, // VLD4d32Pseudo
3568
1.14M
    0U, // VLD4d32Pseudo_UPD
3569
1.14M
    29165942U,  // VLD4d32_UPD
3570
1.14M
    29493622U,  // VLD4d8
3571
1.14M
    0U, // VLD4d8Pseudo
3572
1.14M
    0U, // VLD4d8Pseudo_UPD
3573
1.14M
    29690230U,  // VLD4d8_UPD
3574
1.14M
    28445046U,  // VLD4q16
3575
1.14M
    0U, // VLD4q16Pseudo_UPD
3576
1.14M
    28641654U,  // VLD4q16_UPD
3577
1.14M
    0U, // VLD4q16oddPseudo
3578
1.14M
    0U, // VLD4q16oddPseudo_UPD
3579
1.14M
    28969334U,  // VLD4q32
3580
1.14M
    0U, // VLD4q32Pseudo_UPD
3581
1.14M
    29165942U,  // VLD4q32_UPD
3582
1.14M
    0U, // VLD4q32oddPseudo
3583
1.14M
    0U, // VLD4q32oddPseudo_UPD
3584
1.14M
    29493622U,  // VLD4q8
3585
1.14M
    0U, // VLD4q8Pseudo_UPD
3586
1.14M
    29690230U,  // VLD4q8_UPD
3587
1.14M
    0U, // VLD4q8oddPseudo
3588
1.14M
    0U, // VLD4q8oddPseudo_UPD
3589
1.14M
    942173154U, // VLDMDDB_UPD
3590
1.14M
    2730766U, // VLDMDIA
3591
1.14M
    942172942U, // VLDMDIA_UPD
3592
1.14M
    0U, // VLDMQIA
3593
1.14M
    942173154U, // VLDMSDB_UPD
3594
1.14M
    2730766U, // VLDMSIA
3595
1.14M
    942172942U, // VLDMSIA_UPD
3596
1.14M
    2683301U, // VLDRD
3597
1.14M
    586149U,  // VLDRH
3598
1.14M
    2683301U, // VLDRS
3599
1.14M
    2647159205U,  // VLDR_FPCXTNS_off
3600
1.14M
    768143781U, // VLDR_FPCXTNS_post
3601
1.14M
    2714300837U,  // VLDR_FPCXTNS_pre
3602
1.14M
    2647683493U,  // VLDR_FPCXTS_off
3603
1.14M
    768668069U, // VLDR_FPCXTS_post
3604
1.14M
    2714825125U,  // VLDR_FPCXTS_pre
3605
1.14M
    2648207781U,  // VLDR_FPSCR_NZCVQC_off
3606
1.14M
    769192357U, // VLDR_FPSCR_NZCVQC_post
3607
1.14M
    2715349413U,  // VLDR_FPSCR_NZCVQC_pre
3608
1.14M
    2648732069U,  // VLDR_FPSCR_off
3609
1.14M
    769716645U, // VLDR_FPSCR_post
3610
1.14M
    2715873701U,  // VLDR_FPSCR_pre
3611
1.14M
    2783506853U,  // VLDR_P0_off
3612
1.14M
    1709748645U,  // VLDR_P0_post
3613
1.14M
    2850599333U,  // VLDR_P0_pre
3614
1.14M
    2649780645U,  // VLDR_VPR_off
3615
1.14M
    770765221U, // VLDR_VPR_post
3616
1.14M
    2716922277U,  // VLDR_VPR_pre
3617
1.14M
    2732105U, // VLLDM
3618
1.14M
    2732140U, // VLSTM
3619
1.14M
    8451239U, // VMAXfd
3620
1.14M
    8451239U, // VMAXfq
3621
1.14M
    7926951U, // VMAXhd
3622
1.14M
    7926951U, // VMAXhq
3623
1.14M
    12121255U,  // VMAXsv16i8
3624
1.14M
    11596967U,  // VMAXsv2i32
3625
1.14M
    11072679U,  // VMAXsv4i16
3626
1.14M
    11596967U,  // VMAXsv4i32
3627
1.14M
    11072679U,  // VMAXsv8i16
3628
1.14M
    12121255U,  // VMAXsv8i8
3629
1.14M
    13694119U,  // VMAXuv16i8
3630
1.14M
    13169831U,  // VMAXuv2i32
3631
1.14M
    12645543U,  // VMAXuv4i16
3632
1.14M
    13169831U,  // VMAXuv4i32
3633
1.14M
    12645543U,  // VMAXuv8i16
3634
1.14M
    13694119U,  // VMAXuv8i8
3635
1.14M
    8450204U, // VMINfd
3636
1.14M
    8450204U, // VMINfq
3637
1.14M
    7925916U, // VMINhd
3638
1.14M
    7925916U, // VMINhq
3639
1.14M
    12120220U,  // VMINsv16i8
3640
1.14M
    11595932U,  // VMINsv2i32
3641
1.14M
    11071644U,  // VMINsv4i16
3642
1.14M
    11595932U,  // VMINsv4i32
3643
1.14M
    11071644U,  // VMINsv8i16
3644
1.14M
    12120220U,  // VMINsv8i8
3645
1.14M
    13693084U,  // VMINuv16i8
3646
1.14M
    13168796U,  // VMINuv2i32
3647
1.14M
    12644508U,  // VMINuv4i16
3648
1.14M
    13168796U,  // VMINuv4i32
3649
1.14M
    12644508U,  // VMINuv8i16
3650
1.14M
    13693084U,  // VMINuv8i8
3651
1.14M
    1282452276U,  // VMLAD
3652
1.14M
    7908148U, // VMLAH
3653
1.14M
    11587401U,  // VMLALslsv2i32
3654
1.14M
    11063113U,  // VMLALslsv4i16
3655
1.14M
    13160265U,  // VMLALsluv2i32
3656
1.14M
    12635977U,  // VMLALsluv4i16
3657
1.14M
    11579209U,  // VMLALsv2i64
3658
1.14M
    11054921U,  // VMLALsv4i32
3659
1.14M
    12103497U,  // VMLALsv8i16
3660
1.14M
    13152073U,  // VMLALuv2i64
3661
1.14M
    12627785U,  // VMLALuv4i32
3662
1.14M
    13676361U,  // VMLALuv8i16
3663
1.14M
    8432436U, // VMLAS
3664
1.14M
    8432436U, // VMLAfd
3665
1.14M
    8432436U, // VMLAfq
3666
1.14M
    7908148U, // VMLAhd
3667
1.14M
    7908148U, // VMLAhq
3668
1.14M
    8440628U, // VMLAslfd
3669
1.14M
    8440628U, // VMLAslfq
3670
1.14M
    7916340U, // VMLAslhd
3671
1.14M
    7916340U, // VMLAslhq
3672
1.14M
    14207796U,  // VMLAslv2i32
3673
1.14M
    14732084U,  // VMLAslv4i16
3674
1.14M
    14207796U,  // VMLAslv4i32
3675
1.14M
    14732084U,  // VMLAslv8i16
3676
1.14M
    15248180U,  // VMLAv16i8
3677
1.14M
    14199604U,  // VMLAv2i32
3678
1.14M
    14723892U,  // VMLAv4i16
3679
1.14M
    14199604U,  // VMLAv4i32
3680
1.14M
    14723892U,  // VMLAv8i16
3681
1.14M
    15248180U,  // VMLAv8i8
3682
1.14M
    1282454071U,  // VMLSD
3683
1.14M
    7909943U, // VMLSH
3684
1.14M
    11587618U,  // VMLSLslsv2i32
3685
1.14M
    11063330U,  // VMLSLslsv4i16
3686
1.14M
    13160482U,  // VMLSLsluv2i32
3687
1.14M
    12636194U,  // VMLSLsluv4i16
3688
1.14M
    11579426U,  // VMLSLsv2i64
3689
1.14M
    11055138U,  // VMLSLsv4i32
3690
1.14M
    12103714U,  // VMLSLsv8i16
3691
1.14M
    13152290U,  // VMLSLuv2i64
3692
1.14M
    12628002U,  // VMLSLuv4i32
3693
1.14M
    13676578U,  // VMLSLuv8i16
3694
1.14M
    8434231U, // VMLSS
3695
1.14M
    8434231U, // VMLSfd
3696
1.14M
    8434231U, // VMLSfq
3697
1.14M
    7909943U, // VMLShd
3698
1.14M
    7909943U, // VMLShq
3699
1.14M
    8442423U, // VMLSslfd
3700
1.14M
    8442423U, // VMLSslfq
3701
1.14M
    7918135U, // VMLSslhd
3702
1.14M
    7918135U, // VMLSslhq
3703
1.14M
    14209591U,  // VMLSslv2i32
3704
1.14M
    14733879U,  // VMLSslv4i16
3705
1.14M
    14209591U,  // VMLSslv4i32
3706
1.14M
    14733879U,  // VMLSslv8i16
3707
1.14M
    15249975U,  // VMLSv16i8
3708
1.14M
    14201399U,  // VMLSv2i32
3709
1.14M
    14725687U,  // VMLSv4i16
3710
1.14M
    14201399U,  // VMLSv4i32
3711
1.14M
    14725687U,  // VMLSv8i16
3712
1.14M
    15249975U,  // VMLSv8i8
3713
1.14M
    1010394554U,  // VMMLA
3714
1.14M
    1282438218U,  // VMOVD
3715
1.14M
    2683978U, // VMOVDRR
3716
1.14M
    942753187U, // VMOVH
3717
1.14M
    7894090U, // VMOVHR
3718
1.14M
    11563075U,  // VMOVLsv2i64
3719
1.14M
    11038787U,  // VMOVLsv4i32
3720
1.14M
    12087363U,  // VMOVLsv8i16
3721
1.14M
    13135939U,  // VMOVLuv2i64
3722
1.14M
    12611651U,  // VMOVLuv4i32
3723
1.14M
    13660227U,  // VMOVLuv8i16
3724
1.14M
    962621693U, // VMOVNv2i32
3725
1.14M
    14184701U,  // VMOVNv4i16
3726
1.14M
    14708989U,  // VMOVNv8i8
3727
1.14M
    7894090U, // VMOVRH
3728
1.14M
    2683978U, // VMOVRRD
3729
1.14M
    2667594U, // VMOVRRS
3730
1.14M
    2651210U, // VMOVRS
3731
1.14M
    8418378U, // VMOVS
3732
1.14M
    2651210U, // VMOVSR
3733
1.14M
    2667594U, // VMOVSRR
3734
1.14M
    15234122U,  // VMOVv16i8
3735
1.14M
    2103473226U,  // VMOVv1i64
3736
1.14M
    8418378U, // VMOVv2f32
3737
1.14M
    14185546U,  // VMOVv2i32
3738
1.14M
    2103473226U,  // VMOVv2i64
3739
1.14M
    8418378U, // VMOVv4f32
3740
1.14M
    14709834U,  // VMOVv4i16
3741
1.14M
    14185546U,  // VMOVv4i32
3742
1.14M
    14709834U,  // VMOVv8i16
3743
1.14M
    15234122U,  // VMOVv8i8
3744
1.14M
    2732633U, // VMRS
3745
1.14M
    2732633U, // VMRS_FPCXTNS
3746
1.14M
    2732633U, // VMRS_FPCXTS
3747
1.14M
    2732633U, // VMRS_FPEXC
3748
1.14M
    2732633U, // VMRS_FPINST
3749
1.14M
    2732633U, // VMRS_FPINST2
3750
1.14M
    2650713U, // VMRS_FPSCR_NZCVQC
3751
1.14M
    2732633U, // VMRS_FPSID
3752
1.14M
    2732633U, // VMRS_MVFR0
3753
1.14M
    2732633U, // VMRS_MVFR1
3754
1.14M
    2732633U, // VMRS_MVFR2
3755
1.14M
    2650713U, // VMRS_P0
3756
1.14M
    2732633U, // VMRS_VPR
3757
1.14M
    31568365U,  // VMSR
3758
1.14M
    29995501U,  // VMSR_FPCXTNS
3759
1.14M
    30519789U,  // VMSR_FPCXTS
3760
1.14M
    33141229U,  // VMSR_FPEXC
3761
1.14M
    33665517U,  // VMSR_FPINST
3762
1.14M
    34189805U,  // VMSR_FPINST2
3763
1.14M
    970486253U, // VMSR_FPSCR_NZCVQC
3764
1.14M
    34714093U,  // VMSR_FPSID
3765
1.14M
    971534829U, // VMSR_P0
3766
1.14M
    32616941U,  // VMSR_VPR
3767
1.14M
    1282469950U,  // VMULD
3768
1.14M
    7925822U, // VMULH
3769
1.14M
    942752610U, // VMULLp64
3770
1.14M
    24178671U,  // VMULLp8
3771
1.14M
    11579375U,  // VMULLslsv2i32
3772
1.14M
    11055087U,  // VMULLslsv4i16
3773
1.14M
    13152239U,  // VMULLsluv2i32
3774
1.14M
    12627951U,  // VMULLsluv4i16
3775
1.14M
    11595759U,  // VMULLsv2i64
3776
1.14M
    11071471U,  // VMULLsv4i32
3777
1.14M
    12120047U,  // VMULLsv8i16
3778
1.14M
    13168623U,  // VMULLuv2i64
3779
1.14M
    12644335U,  // VMULLuv4i32
3780
1.14M
    13692911U,  // VMULLuv8i16
3781
1.14M
    8450110U, // VMULS
3782
1.14M
    8450110U, // VMULfd
3783
1.14M
    8450110U, // VMULfq
3784
1.14M
    7925822U, // VMULhd
3785
1.14M
    7925822U, // VMULhq
3786
1.14M
    24178750U,  // VMULpd
3787
1.14M
    24178750U,  // VMULpq
3788
1.14M
    8433726U, // VMULslfd
3789
1.14M
    8433726U, // VMULslfq
3790
1.14M
    7909438U, // VMULslhd
3791
1.14M
    7909438U, // VMULslhq
3792
1.14M
    14200894U,  // VMULslv2i32
3793
1.14M
    14725182U,  // VMULslv4i16
3794
1.14M
    14200894U,  // VMULslv4i32
3795
1.14M
    14725182U,  // VMULslv8i16
3796
1.14M
    15265854U,  // VMULv16i8
3797
1.14M
    14217278U,  // VMULv2i32
3798
1.14M
    14741566U,  // VMULv4i16
3799
1.14M
    14217278U,  // VMULv4i32
3800
1.14M
    14741566U,  // VMULv8i16
3801
1.14M
    15265854U,  // VMULv8i8
3802
1.14M
    2650353U, // VMVNd
3803
1.14M
    2650353U, // VMVNq
3804
1.14M
    14184689U,  // VMVNv2i32
3805
1.14M
    14708977U,  // VMVNv4i16
3806
1.14M
    14184689U,  // VMVNv4i32
3807
1.14M
    14708977U,  // VMVNv8i16
3808
1.14M
    1282436611U,  // VNEGD
3809
1.14M
    7892483U, // VNEGH
3810
1.14M
    8416771U, // VNEGS
3811
1.14M
    8416771U, // VNEGf32q
3812
1.14M
    8416771U, // VNEGfd
3813
1.14M
    7892483U, // VNEGhd
3814
1.14M
    7892483U, // VNEGhq
3815
1.14M
    11038211U,  // VNEGs16d
3816
1.14M
    11038211U,  // VNEGs16q
3817
1.14M
    11562499U,  // VNEGs32d
3818
1.14M
    11562499U,  // VNEGs32q
3819
1.14M
    12086787U,  // VNEGs8d
3820
1.14M
    12086787U,  // VNEGs8q
3821
1.14M
    1282452270U,  // VNMLAD
3822
1.14M
    7908142U, // VNMLAH
3823
1.14M
    8432430U, // VNMLAS
3824
1.14M
    1282454065U,  // VNMLSD
3825
1.14M
    7909937U, // VNMLSH
3826
1.14M
    8434225U, // VNMLSS
3827
1.14M
    1282469944U,  // VNMULD
3828
1.14M
    7925816U, // VNMULH
3829
1.14M
    8450104U, // VNMULS
3830
1.14M
    2683073U, // VORNd
3831
1.14M
    2683073U, // VORNq
3832
1.14M
    2683357U, // VORRd
3833
1.14M
    14217693U,  // VORRiv2i32
3834
1.14M
    14741981U,  // VORRiv4i16
3835
1.14M
    14217693U,  // VORRiv4i32
3836
1.14M
    14741981U,  // VORRiv8i16
3837
1.14M
    2683357U, // VORRq
3838
1.14M
    12119854U,  // VPADALsv16i8
3839
1.14M
    11595566U,  // VPADALsv2i32
3840
1.14M
    11071278U,  // VPADALsv4i16
3841
1.14M
    11595566U,  // VPADALsv4i32
3842
1.14M
    11071278U,  // VPADALsv8i16
3843
1.14M
    12119854U,  // VPADALsv8i8
3844
1.14M
    13692718U,  // VPADALuv16i8
3845
1.14M
    13168430U,  // VPADALuv2i32
3846
1.14M
    12644142U,  // VPADALuv4i16
3847
1.14M
    13168430U,  // VPADALuv4i32
3848
1.14M
    12644142U,  // VPADALuv8i16
3849
1.14M
    13692718U,  // VPADALuv8i8
3850
1.14M
    12087146U,  // VPADDLsv16i8
3851
1.14M
    11562858U,  // VPADDLsv2i32
3852
1.14M
    11038570U,  // VPADDLsv4i16
3853
1.14M
    11562858U,  // VPADDLsv4i32
3854
1.14M
    11038570U,  // VPADDLsv8i16
3855
1.14M
    12087146U,  // VPADDLsv8i8
3856
1.14M
    13660010U,  // VPADDLuv16i8
3857
1.14M
    13135722U,  // VPADDLuv2i32
3858
1.14M
    12611434U,  // VPADDLuv4i16
3859
1.14M
    13135722U,  // VPADDLuv4i32
3860
1.14M
    12611434U,  // VPADDLuv8i16
3861
1.14M
    13660010U,  // VPADDLuv8i8
3862
1.14M
    8449387U, // VPADDf
3863
1.14M
    7925099U, // VPADDh
3864
1.14M
    14740843U,  // VPADDi16
3865
1.14M
    14216555U,  // VPADDi32
3866
1.14M
    15265131U,  // VPADDi8
3867
1.14M
    8451233U, // VPMAXf
3868
1.14M
    7926945U, // VPMAXh
3869
1.14M
    11072673U,  // VPMAXs16
3870
1.14M
    11596961U,  // VPMAXs32
3871
1.14M
    12121249U,  // VPMAXs8
3872
1.14M
    12645537U,  // VPMAXu16
3873
1.14M
    13169825U,  // VPMAXu32
3874
1.14M
    13694113U,  // VPMAXu8
3875
1.14M
    8450198U, // VPMINf
3876
1.14M
    7925910U, // VPMINh
3877
1.14M
    11071638U,  // VPMINs16
3878
1.14M
    11595926U,  // VPMINs32
3879
1.14M
    12120214U,  // VPMINs8
3880
1.14M
    12644502U,  // VPMINu16
3881
1.14M
    13168790U,  // VPMINu32
3882
1.14M
    13693078U,  // VPMINu8
3883
1.14M
    12087830U,  // VQABSv16i8
3884
1.14M
    11563542U,  // VQABSv2i32
3885
1.14M
    11039254U,  // VQABSv4i16
3886
1.14M
    11563542U,  // VQABSv4i32
3887
1.14M
    11039254U,  // VQABSv8i16
3888
1.14M
    12087830U,  // VQABSv8i8
3889
1.14M
    12119409U,  // VQADDsv16i8
3890
1.14M
    974712177U, // VQADDsv1i64
3891
1.14M
    11595121U,  // VQADDsv2i32
3892
1.14M
    974712177U, // VQADDsv2i64
3893
1.14M
    11070833U,  // VQADDsv4i16
3894
1.14M
    11595121U,  // VQADDsv4i32
3895
1.14M
    11070833U,  // VQADDsv8i16
3896
1.14M
    12119409U,  // VQADDsv8i8
3897
1.14M
    13692273U,  // VQADDuv16i8
3898
1.14M
    22605169U,  // VQADDuv1i64
3899
1.14M
    13167985U,  // VQADDuv2i32
3900
1.14M
    22605169U,  // VQADDuv2i64
3901
1.14M
    12643697U,  // VQADDuv4i16
3902
1.14M
    13167985U,  // VQADDuv4i32
3903
1.14M
    12643697U,  // VQADDuv8i16
3904
1.14M
    13692273U,  // VQADDuv8i8
3905
1.14M
    11587381U,  // VQDMLALslv2i32
3906
1.14M
    11063093U,  // VQDMLALslv4i16
3907
1.14M
    11579189U,  // VQDMLALv2i64
3908
1.14M
    11054901U,  // VQDMLALv4i32
3909
1.14M
    11587610U,  // VQDMLSLslv2i32
3910
1.14M
    11063322U,  // VQDMLSLslv4i16
3911
1.14M
    11579418U,  // VQDMLSLv2i64
3912
1.14M
    11055130U,  // VQDMLSLv4i32
3913
1.14M
    11578977U,  // VQDMULHslv2i32
3914
1.14M
    11054689U,  // VQDMULHslv4i16
3915
1.14M
    11578977U,  // VQDMULHslv4i32
3916
1.14M
    11054689U,  // VQDMULHslv8i16
3917
1.14M
    11595361U,  // VQDMULHv2i32
3918
1.14M
    11071073U,  // VQDMULHv4i16
3919
1.14M
    11595361U,  // VQDMULHv4i32
3920
1.14M
    11071073U,  // VQDMULHv8i16
3921
1.14M
    11579355U,  // VQDMULLslv2i32
3922
1.14M
    11055067U,  // VQDMULLslv4i16
3923
1.14M
    11595739U,  // VQDMULLv2i64
3924
1.14M
    11071451U,  // VQDMULLv4i32
3925
1.14M
    974680297U, // VQMOVNsuv2i32
3926
1.14M
    11563241U,  // VQMOVNsuv4i16
3927
1.14M
    11038953U,  // VQMOVNsuv8i8
3928
1.14M
    974680310U, // VQMOVNsv2i32
3929
1.14M
    11563254U,  // VQMOVNsv4i16
3930
1.14M
    11038966U,  // VQMOVNsv8i8
3931
1.14M
    22573302U,  // VQMOVNuv2i32
3932
1.14M
    13136118U,  // VQMOVNuv4i16
3933
1.14M
    12611830U,  // VQMOVNuv8i8
3934
1.14M
    12086781U,  // VQNEGv16i8
3935
1.14M
    11562493U,  // VQNEGv2i32
3936
1.14M
    11038205U,  // VQNEGv4i16
3937
1.14M
    11562493U,  // VQNEGv4i32
3938
1.14M
    11038205U,  // VQNEGv8i16
3939
1.14M
    12086781U,  // VQNEGv8i8
3940
1.14M
    11587101U,  // VQRDMLAHslv2i32
3941
1.14M
    11062813U,  // VQRDMLAHslv4i16
3942
1.14M
    11587101U,  // VQRDMLAHslv4i32
3943
1.14M
    11062813U,  // VQRDMLAHslv8i16
3944
1.14M
    11578909U,  // VQRDMLAHv2i32
3945
1.14M
    11054621U,  // VQRDMLAHv4i16
3946
1.14M
    11578909U,  // VQRDMLAHv4i32
3947
1.14M
    11054621U,  // VQRDMLAHv8i16
3948
1.14M
    11587230U,  // VQRDMLSHslv2i32
3949
1.14M
    11062942U,  // VQRDMLSHslv4i16
3950
1.14M
    11587230U,  // VQRDMLSHslv4i32
3951
1.14M
    11062942U,  // VQRDMLSHslv8i16
3952
1.14M
    11579038U,  // VQRDMLSHv2i32
3953
1.14M
    11054750U,  // VQRDMLSHv4i16
3954
1.14M
    11579038U,  // VQRDMLSHv4i32
3955
1.14M
    11054750U,  // VQRDMLSHv8i16
3956
1.14M
    11578985U,  // VQRDMULHslv2i32
3957
1.14M
    11054697U,  // VQRDMULHslv4i16
3958
1.14M
    11578985U,  // VQRDMULHslv4i32
3959
1.14M
    11054697U,  // VQRDMULHslv8i16
3960
1.14M
    11595369U,  // VQRDMULHv2i32
3961
1.14M
    11071081U,  // VQRDMULHv4i16
3962
1.14M
    11595369U,  // VQRDMULHv4i32
3963
1.14M
    11071081U,  // VQRDMULHv8i16
3964
1.14M
    12119962U,  // VQRSHLsv16i8
3965
1.14M
    974712730U, // VQRSHLsv1i64
3966
1.14M
    11595674U,  // VQRSHLsv2i32
3967
1.14M
    974712730U, // VQRSHLsv2i64
3968
1.14M
    11071386U,  // VQRSHLsv4i16
3969
1.14M
    11595674U,  // VQRSHLsv4i32
3970
1.14M
    11071386U,  // VQRSHLsv8i16
3971
1.14M
    12119962U,  // VQRSHLsv8i8
3972
1.14M
    13692826U,  // VQRSHLuv16i8
3973
1.14M
    22605722U,  // VQRSHLuv1i64
3974
1.14M
    13168538U,  // VQRSHLuv2i32
3975
1.14M
    22605722U,  // VQRSHLuv2i64
3976
1.14M
    12644250U,  // VQRSHLuv4i16
3977
1.14M
    13168538U,  // VQRSHLuv4i32
3978
1.14M
    12644250U,  // VQRSHLuv8i16
3979
1.14M
    13692826U,  // VQRSHLuv8i8
3980
1.14M
    974713004U, // VQRSHRNsv2i32
3981
1.14M
    11595948U,  // VQRSHRNsv4i16
3982
1.14M
    11071660U,  // VQRSHRNsv8i8
3983
1.14M
    22605996U,  // VQRSHRNuv2i32
3984
1.14M
    13168812U,  // VQRSHRNuv4i16
3985
1.14M
    12644524U,  // VQRSHRNuv8i8
3986
1.14M
    974713056U, // VQRSHRUNv2i32
3987
1.14M
    11596000U,  // VQRSHRUNv4i16
3988
1.14M
    11071712U,  // VQRSHRUNv8i8
3989
1.14M
    12119949U,  // VQSHLsiv16i8
3990
1.14M
    974712717U, // VQSHLsiv1i64
3991
1.14M
    11595661U,  // VQSHLsiv2i32
3992
1.14M
    974712717U, // VQSHLsiv2i64
3993
1.14M
    11071373U,  // VQSHLsiv4i16
3994
1.14M
    11595661U,  // VQSHLsiv4i32
3995
1.14M
    11071373U,  // VQSHLsiv8i16
3996
1.14M
    12119949U,  // VQSHLsiv8i8
3997
1.14M
    12121029U,  // VQSHLsuv16i8
3998
1.14M
    974713797U, // VQSHLsuv1i64
3999
1.14M
    11596741U,  // VQSHLsuv2i32
4000
1.14M
    974713797U, // VQSHLsuv2i64
4001
1.14M
    11072453U,  // VQSHLsuv4i16
4002
1.14M
    11596741U,  // VQSHLsuv4i32
4003
1.14M
    11072453U,  // VQSHLsuv8i16
4004
1.14M
    12121029U,  // VQSHLsuv8i8
4005
1.14M
    12119949U,  // VQSHLsv16i8
4006
1.14M
    974712717U, // VQSHLsv1i64
4007
1.14M
    11595661U,  // VQSHLsv2i32
4008
1.14M
    974712717U, // VQSHLsv2i64
4009
1.14M
    11071373U,  // VQSHLsv4i16
4010
1.14M
    11595661U,  // VQSHLsv4i32
4011
1.14M
    11071373U,  // VQSHLsv8i16
4012
1.14M
    12119949U,  // VQSHLsv8i8
4013
1.14M
    13692813U,  // VQSHLuiv16i8
4014
1.14M
    22605709U,  // VQSHLuiv1i64
4015
1.14M
    13168525U,  // VQSHLuiv2i32
4016
1.14M
    22605709U,  // VQSHLuiv2i64
4017
1.14M
    12644237U,  // VQSHLuiv4i16
4018
1.14M
    13168525U,  // VQSHLuiv4i32
4019
1.14M
    12644237U,  // VQSHLuiv8i16
4020
1.14M
    13692813U,  // VQSHLuiv8i8
4021
1.14M
    13692813U,  // VQSHLuv16i8
4022
1.14M
    22605709U,  // VQSHLuv1i64
4023
1.14M
    13168525U,  // VQSHLuv2i32
4024
1.14M
    22605709U,  // VQSHLuv2i64
4025
1.14M
    12644237U,  // VQSHLuv4i16
4026
1.14M
    13168525U,  // VQSHLuv4i32
4027
1.14M
    12644237U,  // VQSHLuv8i16
4028
1.14M
    13692813U,  // VQSHLuv8i8
4029
1.14M
    974712997U, // VQSHRNsv2i32
4030
1.14M
    11595941U,  // VQSHRNsv4i16
4031
1.14M
    11071653U,  // VQSHRNsv8i8
4032
1.14M
    22605989U,  // VQSHRNuv2i32
4033
1.14M
    13168805U,  // VQSHRNuv4i16
4034
1.14M
    12644517U,  // VQSHRNuv8i8
4035
1.14M
    974713048U, // VQSHRUNv2i32
4036
1.14M
    11595992U,  // VQSHRUNv4i16
4037
1.14M
    11071704U,  // VQSHRUNv8i8
4038
1.14M
    12119247U,  // VQSUBsv16i8
4039
1.14M
    974712015U, // VQSUBsv1i64
4040
1.14M
    11594959U,  // VQSUBsv2i32
4041
1.14M
    974712015U, // VQSUBsv2i64
4042
1.14M
    11070671U,  // VQSUBsv4i16
4043
1.14M
    11594959U,  // VQSUBsv4i32
4044
1.14M
    11070671U,  // VQSUBsv8i16
4045
1.14M
    12119247U,  // VQSUBsv8i8
4046
1.14M
    13692111U,  // VQSUBuv16i8
4047
1.14M
    22605007U,  // VQSUBuv1i64
4048
1.14M
    13167823U,  // VQSUBuv2i32
4049
1.14M
    22605007U,  // VQSUBuv2i64
4050
1.14M
    12643535U,  // VQSUBuv4i16
4051
1.14M
    13167823U,  // VQSUBuv4i32
4052
1.14M
    12643535U,  // VQSUBuv8i16
4053
1.14M
    13692111U,  // VQSUBuv8i8
4054
1.14M
    962654343U, // VRADDHNv2i32
4055
1.14M
    14217351U,  // VRADDHNv4i16
4056
1.14M
    14741639U,  // VRADDHNv8i8
4057
1.14M
    13135319U,  // VRECPEd
4058
1.14M
    8416727U, // VRECPEfd
4059
1.14M
    8416727U, // VRECPEfq
4060
1.14M
    7892439U, // VRECPEhd
4061
1.14M
    7892439U, // VRECPEhq
4062
1.14M
    13135319U,  // VRECPEq
4063
1.14M
    8450642U, // VRECPSfd
4064
1.14M
    8450642U, // VRECPSfq
4065
1.14M
    7926354U, // VRECPShd
4066
1.14M
    7926354U, // VRECPShq
4067
1.14M
    1599992U, // VREV16d8
4068
1.14M
    1599992U, // VREV16q8
4069
1.14M
    551193U,  // VREV32d16
4070
1.14M
    1599769U, // VREV32d8
4071
1.14M
    551193U,  // VREV32q16
4072
1.14M
    1599769U, // VREV32q8
4073
1.14M
    551279U,  // VREV64d16
4074
1.14M
    1075567U, // VREV64d32
4075
1.14M
    1599855U, // VREV64d8
4076
1.14M
    551279U,  // VREV64q16
4077
1.14M
    1075567U, // VREV64q32
4078
1.14M
    1599855U, // VREV64q8
4079
1.14M
    12119390U,  // VRHADDsv16i8
4080
1.14M
    11595102U,  // VRHADDsv2i32
4081
1.14M
    11070814U,  // VRHADDsv4i16
4082
1.14M
    11595102U,  // VRHADDsv4i32
4083
1.14M
    11070814U,  // VRHADDsv8i16
4084
1.14M
    12119390U,  // VRHADDsv8i8
4085
1.14M
    13692254U,  // VRHADDuv16i8
4086
1.14M
    13167966U,  // VRHADDuv2i32
4087
1.14M
    12643678U,  // VRHADDuv4i16
4088
1.14M
    13167966U,  // VRHADDuv4i32
4089
1.14M
    12643678U,  // VRHADDuv8i16
4090
1.14M
    13692254U,  // VRHADDuv8i8
4091
1.14M
    942752490U, // VRINTAD
4092
1.14M
    942753012U, // VRINTAH
4093
1.14M
    942752139U, // VRINTANDf
4094
1.14M
    942753012U, // VRINTANDh
4095
1.14M
    942752139U, // VRINTANQf
4096
1.14M
    942753012U, // VRINTANQh
4097
1.14M
    942752139U, // VRINTAS
4098
1.14M
    942752538U, // VRINTMD
4099
1.14M
    942753093U, // VRINTMH
4100
1.14M
    942752198U, // VRINTMNDf
4101
1.14M
    942753093U, // VRINTMNDh
4102
1.14M
    942752198U, // VRINTMNQf
4103
1.14M
    942753093U, // VRINTMNQh
4104
1.14M
    942752198U, // VRINTMS
4105
1.14M
    942752550U, // VRINTND
4106
1.14M
    942753105U, // VRINTNH
4107
1.14M
    942752210U, // VRINTNNDf
4108
1.14M
    942753105U, // VRINTNNDh
4109
1.14M
    942752210U, // VRINTNNQf
4110
1.14M
    942753105U, // VRINTNNQh
4111
1.14M
    942752210U, // VRINTNS
4112
1.14M
    942752562U, // VRINTPD
4113
1.14M
    942753117U, // VRINTPH
4114
1.14M
    942752222U, // VRINTPNDf
4115
1.14M
    942753117U, // VRINTPNDh
4116
1.14M
    942752222U, // VRINTPNQf
4117
1.14M
    942753117U, // VRINTPNQh
4118
1.14M
    942752222U, // VRINTPS
4119
1.14M
    1282437624U,  // VRINTRD
4120
1.14M
    7893496U, // VRINTRH
4121
1.14M
    8417784U, // VRINTRS
4122
1.14M
    1282438598U,  // VRINTXD
4123
1.14M
    7894470U, // VRINTXH
4124
1.14M
    942752270U, // VRINTXNDf
4125
1.14M
    942753175U, // VRINTXNDh
4126
1.14M
    942752270U, // VRINTXNQf
4127
1.14M
    942753175U, // VRINTXNQh
4128
1.14M
    8418758U, // VRINTXS
4129
1.14M
    1282438648U,  // VRINTZD
4130
1.14M
    7894520U, // VRINTZH
4131
1.14M
    942752282U, // VRINTZNDf
4132
1.14M
    942753198U, // VRINTZNDh
4133
1.14M
    942752282U, // VRINTZNQf
4134
1.14M
    942753198U, // VRINTZNQh
4135
1.14M
    8418808U, // VRINTZS
4136
1.14M
    12119969U,  // VRSHLsv16i8
4137
1.14M
    974712737U, // VRSHLsv1i64
4138
1.14M
    11595681U,  // VRSHLsv2i32
4139
1.14M
    974712737U, // VRSHLsv2i64
4140
1.14M
    11071393U,  // VRSHLsv4i16
4141
1.14M
    11595681U,  // VRSHLsv4i32
4142
1.14M
    11071393U,  // VRSHLsv8i16
4143
1.14M
    12119969U,  // VRSHLsv8i8
4144
1.14M
    13692833U,  // VRSHLuv16i8
4145
1.14M
    22605729U,  // VRSHLuv1i64
4146
1.14M
    13168545U,  // VRSHLuv2i32
4147
1.14M
    22605729U,  // VRSHLuv2i64
4148
1.14M
    12644257U,  // VRSHLuv4i16
4149
1.14M
    13168545U,  // VRSHLuv4i32
4150
1.14M
    12644257U,  // VRSHLuv8i16
4151
1.14M
    13692833U,  // VRSHLuv8i8
4152
1.14M
    962654388U, // VRSHRNv2i32
4153
1.14M
    14217396U,  // VRSHRNv4i16
4154
1.14M
    14741684U,  // VRSHRNv8i8
4155
1.14M
    12120509U,  // VRSHRsv16i8
4156
1.14M
    974713277U, // VRSHRsv1i64
4157
1.14M
    11596221U,  // VRSHRsv2i32
4158
1.14M
    974713277U, // VRSHRsv2i64
4159
1.14M
    11071933U,  // VRSHRsv4i16
4160
1.14M
    11596221U,  // VRSHRsv4i32
4161
1.14M
    11071933U,  // VRSHRsv8i16
4162
1.14M
    12120509U,  // VRSHRsv8i8
4163
1.14M
    13693373U,  // VRSHRuv16i8
4164
1.14M
    22606269U,  // VRSHRuv1i64
4165
1.14M
    13169085U,  // VRSHRuv2i32
4166
1.14M
    22606269U,  // VRSHRuv2i64
4167
1.14M
    12644797U,  // VRSHRuv4i16
4168
1.14M
    13169085U,  // VRSHRuv4i32
4169
1.14M
    12644797U,  // VRSHRuv8i16
4170
1.14M
    13693373U,  // VRSHRuv8i8
4171
1.14M
    13135332U,  // VRSQRTEd
4172
1.14M
    8416740U, // VRSQRTEfd
4173
1.14M
    8416740U, // VRSQRTEfq
4174
1.14M
    7892452U, // VRSQRTEhd
4175
1.14M
    7892452U, // VRSQRTEhq
4176
1.14M
    13135332U,  // VRSQRTEq
4177
1.14M
    8450664U, // VRSQRTSfd
4178
1.14M
    8450664U, // VRSQRTSfq
4179
1.14M
    7926376U, // VRSQRTShd
4180
1.14M
    7926376U, // VRSQRTShq
4181
1.14M
    12102490U,  // VRSRAsv16i8
4182
1.14M
    907586394U, // VRSRAsv1i64
4183
1.14M
    11578202U,  // VRSRAsv2i32
4184
1.14M
    907586394U, // VRSRAsv2i64
4185
1.14M
    11053914U,  // VRSRAsv4i16
4186
1.14M
    11578202U,  // VRSRAsv4i32
4187
1.14M
    11053914U,  // VRSRAsv8i16
4188
1.14M
    12102490U,  // VRSRAsv8i8
4189
1.14M
    13675354U,  // VRSRAuv16i8
4190
1.14M
    22588250U,  // VRSRAuv1i64
4191
1.14M
    13151066U,  // VRSRAuv2i32
4192
1.14M
    22588250U,  // VRSRAuv2i64
4193
1.14M
    12626778U,  // VRSRAuv4i16
4194
1.14M
    13151066U,  // VRSRAuv4i32
4195
1.14M
    12626778U,  // VRSRAuv8i16
4196
1.14M
    13675354U,  // VRSRAuv8i8
4197
1.14M
    962654328U, // VRSUBHNv2i32
4198
1.14M
    14217336U,  // VRSUBHNv4i16
4199
1.14M
    14741624U,  // VRSUBHNv8i8
4200
1.14M
    2888421469U,  // VSCCLRMD
4201
1.14M
    2888421469U,  // VSCCLRMS
4202
1.14M
    1010394796U,  // VSDOTD
4203
1.14M
    1010394796U,  // VSDOTDI
4204
1.14M
    1010394796U,  // VSDOTQ
4205
1.14M
    1010394796U,  // VSDOTQI
4206
1.14M
    942752574U, // VSELEQD
4207
1.14M
    942753129U, // VSELEQH
4208
1.14M
    942752234U, // VSELEQS
4209
1.14M
    942752502U, // VSELGED
4210
1.14M
    942753035U, // VSELGEH
4211
1.14M
    942752162U, // VSELGES
4212
1.14M
    942752598U, // VSELGTD
4213
1.14M
    942753163U, // VSELGTH
4214
1.14M
    942752258U, // VSELGTS
4215
1.14M
    942752586U, // VSELVSD
4216
1.14M
    942753151U, // VSELVSH
4217
1.14M
    942752246U, // VSELVSS
4218
1.14M
    570442U,  // VSETLNi16
4219
1.14M
    1094730U, // VSETLNi32
4220
1.14M
    1619018U, // VSETLNi8
4221
1.14M
    14741456U,  // VSHLLi16
4222
1.14M
    14217168U,  // VSHLLi32
4223
1.14M
    15265744U,  // VSHLLi8
4224
1.14M
    11595728U,  // VSHLLsv2i64
4225
1.14M
    11071440U,  // VSHLLsv4i32
4226
1.14M
    12120016U,  // VSHLLsv8i16
4227
1.14M
    13168592U,  // VSHLLuv2i64
4228
1.14M
    12644304U,  // VSHLLuv4i32
4229
1.14M
    13692880U,  // VSHLLuv8i16
4230
1.14M
    15265703U,  // VSHLiv16i8
4231
1.14M
    962654119U, // VSHLiv1i64
4232
1.14M
    14217127U,  // VSHLiv2i32
4233
1.14M
    962654119U, // VSHLiv2i64
4234
1.14M
    14741415U,  // VSHLiv4i16
4235
1.14M
    14217127U,  // VSHLiv4i32
4236
1.14M
    14741415U,  // VSHLiv8i16
4237
1.14M
    15265703U,  // VSHLiv8i8
4238
1.14M
    12119975U,  // VSHLsv16i8
4239
1.14M
    974712743U, // VSHLsv1i64
4240
1.14M
    11595687U,  // VSHLsv2i32
4241
1.14M
    974712743U, // VSHLsv2i64
4242
1.14M
    11071399U,  // VSHLsv4i16
4243
1.14M
    11595687U,  // VSHLsv4i32
4244
1.14M
    11071399U,  // VSHLsv8i16
4245
1.14M
    12119975U,  // VSHLsv8i8
4246
1.14M
    13692839U,  // VSHLuv16i8
4247
1.14M
    22605735U,  // VSHLuv1i64
4248
1.14M
    13168551U,  // VSHLuv2i32
4249
1.14M
    22605735U,  // VSHLuv2i64
4250
1.14M
    12644263U,  // VSHLuv4i16
4251
1.14M
    13168551U,  // VSHLuv4i32
4252
1.14M
    12644263U,  // VSHLuv8i16
4253
1.14M
    13692839U,  // VSHLuv8i8
4254
1.14M
    962654395U, // VSHRNv2i32
4255
1.14M
    14217403U,  // VSHRNv4i16
4256
1.14M
    14741691U,  // VSHRNv8i8
4257
1.14M
    12120515U,  // VSHRsv16i8
4258
1.14M
    974713283U, // VSHRsv1i64
4259
1.14M
    11596227U,  // VSHRsv2i32
4260
1.14M
    974713283U, // VSHRsv2i64
4261
1.14M
    11071939U,  // VSHRsv4i16
4262
1.14M
    11596227U,  // VSHRsv4i32
4263
1.14M
    11071939U,  // VSHRsv8i16
4264
1.14M
    12120515U,  // VSHRsv8i8
4265
1.14M
    13693379U,  // VSHRuv16i8
4266
1.14M
    22606275U,  // VSHRuv1i64
4267
1.14M
    13169091U,  // VSHRuv2i32
4268
1.14M
    22606275U,  // VSHRuv2i64
4269
1.14M
    12644803U,  // VSHRuv4i16
4270
1.14M
    13169091U,  // VSHRuv4i32
4271
1.14M
    12644803U,  // VSHRuv8i16
4272
1.14M
    13693379U,  // VSHRuv8i8
4273
1.14M
    35713960U,  // VSHTOD
4274
1.14M
    1291908008U,  // VSHTOH
4275
1.14M
    36238248U,  // VSHTOS
4276
1.14M
    1244689320U,  // VSITOD
4277
1.14M
    1245213608U,  // VSITOH
4278
1.14M
    1226339240U,  // VSITOS
4279
1.14M
    1617672U, // VSLIv16i8
4280
1.14M
    15773448U,  // VSLIv1i64
4281
1.14M
    1093384U, // VSLIv2i32
4282
1.14M
    15773448U,  // VSLIv2i64
4283
1.14M
    569096U,  // VSLIv4i16
4284
1.14M
    1093384U, // VSLIv4i32
4285
1.14M
    569096U,  // VSLIv8i16
4286
1.14M
    1617672U, // VSLIv8i8
4287
1.14M
    1311830952U,  // VSLTOD
4288
1.14M
    1312355240U,  // VSLTOH
4289
1.14M
    1293480872U,  // VSLTOS
4290
1.14M
    1010394774U,  // VSMMLA
4291
1.14M
    1282437991U,  // VSQRTD
4292
1.14M
    7893863U, // VSQRTH
4293
1.14M
    8418151U, // VSQRTS
4294
1.14M
    12102496U,  // VSRAsv16i8
4295
1.14M
    907586400U, // VSRAsv1i64
4296
1.14M
    11578208U,  // VSRAsv2i32
4297
1.14M
    907586400U, // VSRAsv2i64
4298
1.14M
    11053920U,  // VSRAsv4i16
4299
1.14M
    11578208U,  // VSRAsv4i32
4300
1.14M
    11053920U,  // VSRAsv8i16
4301
1.14M
    12102496U,  // VSRAsv8i8
4302
1.14M
    13675360U,  // VSRAuv16i8
4303
1.14M
    22588256U,  // VSRAuv1i64
4304
1.14M
    13151072U,  // VSRAuv2i32
4305
1.14M
    22588256U,  // VSRAuv2i64
4306
1.14M
    12626784U,  // VSRAuv4i16
4307
1.14M
    13151072U,  // VSRAuv4i32
4308
1.14M
    12626784U,  // VSRAuv8i16
4309
1.14M
    13675360U,  // VSRAuv8i8
4310
1.14M
    1617677U, // VSRIv16i8
4311
1.14M
    15773453U,  // VSRIv1i64
4312
1.14M
    1093389U, // VSRIv2i32
4313
1.14M
    15773453U,  // VSRIv2i64
4314
1.14M
    569101U,  // VSRIv4i16
4315
1.14M
    1093389U, // VSRIv4i32
4316
1.14M
    569101U,  // VSRIv8i16
4317
1.14M
    1617677U, // VSRIv8i8
4318
1.14M
    900770063U, // VST1LNd16
4319
1.14M
    2981234959U,  // VST1LNd16_UPD
4320
1.14M
    901294351U, // VST1LNd32
4321
1.14M
    2981759247U,  // VST1LNd32_UPD
4322
1.14M
    901818639U, // VST1LNd8
4323
1.14M
    2982283535U,  // VST1LNd8_UPD
4324
1.14M
    0U, // VST1LNq16Pseudo
4325
1.14M
    0U, // VST1LNq16Pseudo_UPD
4326
1.14M
    0U, // VST1LNq32Pseudo
4327
1.14M
    0U, // VST1LNq32Pseudo_UPD
4328
1.14M
    0U, // VST1LNq8Pseudo
4329
1.14M
    0U, // VST1LNq8Pseudo_UPD
4330
1.14M
    3020482831U,  // VST1d16
4331
1.14M
    3087591695U,  // VST1d16Q
4332
1.14M
    0U, // VST1d16QPseudo
4333
1.14M
    0U, // VST1d16QPseudoWB_fixed
4334
1.14M
    0U, // VST1d16QPseudoWB_register
4335
1.14M
    3154684175U,  // VST1d16Qwb_fixed
4336
1.14M
    3221801231U,  // VST1d16Qwb_register
4337
1.14M
    3288918287U,  // VST1d16T
4338
1.14M
    0U, // VST1d16TPseudo
4339
1.14M
    0U, // VST1d16TPseudoWB_fixed
4340
1.14M
    0U, // VST1d16TPseudoWB_register
4341
1.14M
    3356010767U,  // VST1d16Twb_fixed
4342
1.14M
    3423127823U,  // VST1d16Twb_register
4343
1.14M
    3490228495U,  // VST1d16wb_fixed
4344
1.14M
    3557345551U,  // VST1d16wb_register
4345
1.14M
    3021007119U,  // VST1d32
4346
1.14M
    3088115983U,  // VST1d32Q
4347
1.14M
    0U, // VST1d32QPseudo
4348
1.14M
    0U, // VST1d32QPseudoWB_fixed
4349
1.14M
    0U, // VST1d32QPseudoWB_register
4350
1.14M
    3155208463U,  // VST1d32Qwb_fixed
4351
1.14M
    3222325519U,  // VST1d32Qwb_register
4352
1.14M
    3289442575U,  // VST1d32T
4353
1.14M
    0U, // VST1d32TPseudo
4354
1.14M
    0U, // VST1d32TPseudoWB_fixed
4355
1.14M
    0U, // VST1d32TPseudoWB_register
4356
1.14M
    3356535055U,  // VST1d32Twb_fixed
4357
1.14M
    3423652111U,  // VST1d32Twb_register
4358
1.14M
    3490752783U,  // VST1d32wb_fixed
4359
1.14M
    3557869839U,  // VST1d32wb_register
4360
1.14M
    3035687183U,  // VST1d64
4361
1.14M
    3102796047U,  // VST1d64Q
4362
1.14M
    0U, // VST1d64QPseudo
4363
1.14M
    0U, // VST1d64QPseudoWB_fixed
4364
1.14M
    0U, // VST1d64QPseudoWB_register
4365
1.14M
    3169888527U,  // VST1d64Qwb_fixed
4366
1.14M
    3237005583U,  // VST1d64Qwb_register
4367
1.14M
    3304122639U,  // VST1d64T
4368
1.14M
    0U, // VST1d64TPseudo
4369
1.14M
    0U, // VST1d64TPseudoWB_fixed
4370
1.14M
    0U, // VST1d64TPseudoWB_register
4371
1.14M
    3371215119U,  // VST1d64Twb_fixed
4372
1.14M
    3438332175U,  // VST1d64Twb_register
4373
1.14M
    3505432847U,  // VST1d64wb_fixed
4374
1.14M
    3572549903U,  // VST1d64wb_register
4375
1.14M
    3021531407U,  // VST1d8
4376
1.14M
    3088640271U,  // VST1d8Q
4377
1.14M
    0U, // VST1d8QPseudo
4378
1.14M
    0U, // VST1d8QPseudoWB_fixed
4379
1.14M
    0U, // VST1d8QPseudoWB_register
4380
1.14M
    3155732751U,  // VST1d8Qwb_fixed
4381
1.14M
    3222849807U,  // VST1d8Qwb_register
4382
1.14M
    3289966863U,  // VST1d8T
4383
1.14M
    0U, // VST1d8TPseudo
4384
1.14M
    0U, // VST1d8TPseudoWB_fixed
4385
1.14M
    0U, // VST1d8TPseudoWB_register
4386
1.14M
    3357059343U,  // VST1d8Twb_fixed
4387
1.14M
    3424176399U,  // VST1d8Twb_register
4388
1.14M
    3491277071U,  // VST1d8wb_fixed
4389
1.14M
    3558394127U,  // VST1d8wb_register
4390
1.14M
    3624462607U,  // VST1q16
4391
1.14M
    0U, // VST1q16HighQPseudo
4392
1.14M
    0U, // VST1q16HighQPseudo_UPD
4393
1.14M
    0U, // VST1q16HighTPseudo
4394
1.14M
    0U, // VST1q16HighTPseudo_UPD
4395
1.14M
    0U, // VST1q16LowQPseudo_UPD
4396
1.14M
    0U, // VST1q16LowTPseudo_UPD
4397
1.14M
    3691555087U,  // VST1q16wb_fixed
4398
1.14M
    3758672143U,  // VST1q16wb_register
4399
1.14M
    3624986895U,  // VST1q32
4400
1.14M
    0U, // VST1q32HighQPseudo
4401
1.14M
    0U, // VST1q32HighQPseudo_UPD
4402
1.14M
    0U, // VST1q32HighTPseudo
4403
1.14M
    0U, // VST1q32HighTPseudo_UPD
4404
1.14M
    0U, // VST1q32LowQPseudo_UPD
4405
1.14M
    0U, // VST1q32LowTPseudo_UPD
4406
1.14M
    3692079375U,  // VST1q32wb_fixed
4407
1.14M
    3759196431U,  // VST1q32wb_register
4408
1.14M
    3639666959U,  // VST1q64
4409
1.14M
    0U, // VST1q64HighQPseudo
4410
1.14M
    0U, // VST1q64HighQPseudo_UPD
4411
1.14M
    0U, // VST1q64HighTPseudo
4412
1.14M
    0U, // VST1q64HighTPseudo_UPD
4413
1.14M
    0U, // VST1q64LowQPseudo_UPD
4414
1.14M
    0U, // VST1q64LowTPseudo_UPD
4415
1.14M
    3706759439U,  // VST1q64wb_fixed
4416
1.14M
    3773876495U,  // VST1q64wb_register
4417
1.14M
    3625511183U,  // VST1q8
4418
1.14M
    0U, // VST1q8HighQPseudo
4419
1.14M
    0U, // VST1q8HighQPseudo_UPD
4420
1.14M
    0U, // VST1q8HighTPseudo
4421
1.14M
    0U, // VST1q8HighTPseudo_UPD
4422
1.14M
    0U, // VST1q8LowQPseudo_UPD
4423
1.14M
    0U, // VST1q8LowTPseudo_UPD
4424
1.14M
    3692603663U,  // VST1q8wb_fixed
4425
1.14M
    3759720719U,  // VST1q8wb_register
4426
1.14M
    900778320U, // VST2LNd16
4427
1.14M
    0U, // VST2LNd16Pseudo
4428
1.14M
    0U, // VST2LNd16Pseudo_UPD
4429
1.14M
    2981407056U,  // VST2LNd16_UPD
4430
1.14M
    901302608U, // VST2LNd32
4431
1.14M
    0U, // VST2LNd32Pseudo
4432
1.14M
    0U, // VST2LNd32Pseudo_UPD
4433
1.14M
    2981931344U,  // VST2LNd32_UPD
4434
1.14M
    901826896U, // VST2LNd8
4435
1.14M
    0U, // VST2LNd8Pseudo
4436
1.14M
    0U, // VST2LNd8Pseudo_UPD
4437
1.14M
    2982455632U,  // VST2LNd8_UPD
4438
1.14M
    900778320U, // VST2LNq16
4439
1.14M
    0U, // VST2LNq16Pseudo
4440
1.14M
    0U, // VST2LNq16Pseudo_UPD
4441
1.14M
    2981407056U,  // VST2LNq16_UPD
4442
1.14M
    901302608U, // VST2LNq32
4443
1.14M
    0U, // VST2LNq32Pseudo
4444
1.14M
    0U, // VST2LNq32Pseudo_UPD
4445
1.14M
    2981931344U,  // VST2LNq32_UPD
4446
1.14M
    3825789264U,  // VST2b16
4447
1.14M
    3892881744U,  // VST2b16wb_fixed
4448
1.14M
    3959998800U,  // VST2b16wb_register
4449
1.14M
    3826313552U,  // VST2b32
4450
1.14M
    3893406032U,  // VST2b32wb_fixed
4451
1.14M
    3960523088U,  // VST2b32wb_register
4452
1.14M
    3826837840U,  // VST2b8
4453
1.14M
    3893930320U,  // VST2b8wb_fixed
4454
1.14M
    3961047376U,  // VST2b8wb_register
4455
1.14M
    3624462672U,  // VST2d16
4456
1.14M
    3691555152U,  // VST2d16wb_fixed
4457
1.14M
    3758672208U,  // VST2d16wb_register
4458
1.14M
    3624986960U,  // VST2d32
4459
1.14M
    3692079440U,  // VST2d32wb_fixed
4460
1.14M
    3759196496U,  // VST2d32wb_register
4461
1.14M
    3625511248U,  // VST2d8
4462
1.14M
    3692603728U,  // VST2d8wb_fixed
4463
1.14M
    3759720784U,  // VST2d8wb_register
4464
1.14M
    3087591760U,  // VST2q16
4465
1.14M
    0U, // VST2q16Pseudo
4466
1.14M
    0U, // VST2q16PseudoWB_fixed
4467
1.14M
    0U, // VST2q16PseudoWB_register
4468
1.14M
    3154684240U,  // VST2q16wb_fixed
4469
1.14M
    3221801296U,  // VST2q16wb_register
4470
1.14M
    3088116048U,  // VST2q32
4471
1.14M
    0U, // VST2q32Pseudo
4472
1.14M
    0U, // VST2q32PseudoWB_fixed
4473
1.14M
    0U, // VST2q32PseudoWB_register
4474
1.14M
    3155208528U,  // VST2q32wb_fixed
4475
1.14M
    3222325584U,  // VST2q32wb_register
4476
1.14M
    3088640336U,  // VST2q8
4477
1.14M
    0U, // VST2q8Pseudo
4478
1.14M
    0U, // VST2q8PseudoWB_fixed
4479
1.14M
    0U, // VST2q8PseudoWB_register
4480
1.14M
    3155732816U,  // VST2q8wb_fixed
4481
1.14M
    3222849872U,  // VST2q8wb_register
4482
1.14M
    900860261U, // VST3LNd16
4483
1.14M
    0U, // VST3LNd16Pseudo
4484
1.14M
    0U, // VST3LNd16Pseudo_UPD
4485
1.14M
    2981431653U,  // VST3LNd16_UPD
4486
1.14M
    901384549U, // VST3LNd32
4487
1.14M
    0U, // VST3LNd32Pseudo
4488
1.14M
    0U, // VST3LNd32Pseudo_UPD
4489
1.14M
    2981955941U,  // VST3LNd32_UPD
4490
1.14M
    901908837U, // VST3LNd8
4491
1.14M
    0U, // VST3LNd8Pseudo
4492
1.14M
    0U, // VST3LNd8Pseudo_UPD
4493
1.14M
    2982480229U,  // VST3LNd8_UPD
4494
1.14M
    900860261U, // VST3LNq16
4495
1.14M
    0U, // VST3LNq16Pseudo
4496
1.14M
    0U, // VST3LNq16Pseudo_UPD
4497
1.14M
    2981431653U,  // VST3LNq16_UPD
4498
1.14M
    901384549U, // VST3LNq32
4499
1.14M
    0U, // VST3LNq32Pseudo
4500
1.14M
    0U, // VST3LNq32Pseudo_UPD
4501
1.14M
    2981955941U,  // VST3LNq32_UPD
4502
1.14M
    900778341U, // VST3d16
4503
1.14M
    0U, // VST3d16Pseudo
4504
1.14M
    0U, // VST3d16Pseudo_UPD
4505
1.14M
    2981407077U,  // VST3d16_UPD
4506
1.14M
    901302629U, // VST3d32
4507
1.14M
    0U, // VST3d32Pseudo
4508
1.14M
    0U, // VST3d32Pseudo_UPD
4509
1.14M
    2981931365U,  // VST3d32_UPD
4510
1.14M
    901826917U, // VST3d8
4511
1.14M
    0U, // VST3d8Pseudo
4512
1.14M
    0U, // VST3d8Pseudo_UPD
4513
1.14M
    2982455653U,  // VST3d8_UPD
4514
1.14M
    900778341U, // VST3q16
4515
1.14M
    0U, // VST3q16Pseudo_UPD
4516
1.14M
    2981407077U,  // VST3q16_UPD
4517
1.14M
    0U, // VST3q16oddPseudo
4518
1.14M
    0U, // VST3q16oddPseudo_UPD
4519
1.14M
    901302629U, // VST3q32
4520
1.14M
    0U, // VST3q32Pseudo_UPD
4521
1.14M
    2981931365U,  // VST3q32_UPD
4522
1.14M
    0U, // VST3q32oddPseudo
4523
1.14M
    0U, // VST3q32oddPseudo_UPD
4524
1.14M
    901826917U, // VST3q8
4525
1.14M
    0U, // VST3q8Pseudo_UPD
4526
1.14M
    2982455653U,  // VST3q8_UPD
4527
1.14M
    0U, // VST3q8oddPseudo
4528
1.14M
    0U, // VST3q8oddPseudo_UPD
4529
1.14M
    901032315U, // VST4LNd16
4530
1.14M
    0U, // VST4LNd16Pseudo
4531
1.14M
    0U, // VST4LNd16Pseudo_UPD
4532
1.14M
    2981415291U,  // VST4LNd16_UPD
4533
1.14M
    901556603U, // VST4LNd32
4534
1.14M
    0U, // VST4LNd32Pseudo
4535
1.14M
    0U, // VST4LNd32Pseudo_UPD
4536
1.14M
    2981939579U,  // VST4LNd32_UPD
4537
1.14M
    902080891U, // VST4LNd8
4538
1.14M
    0U, // VST4LNd8Pseudo
4539
1.14M
    0U, // VST4LNd8Pseudo_UPD
4540
1.14M
    2982463867U,  // VST4LNd8_UPD
4541
1.14M
    901032315U, // VST4LNq16
4542
1.14M
    0U, // VST4LNq16Pseudo
4543
1.14M
    0U, // VST4LNq16Pseudo_UPD
4544
1.14M
    2981415291U,  // VST4LNq16_UPD
4545
1.14M
    901556603U, // VST4LNq32
4546
1.14M
    0U, // VST4LNq32Pseudo
4547
1.14M
    0U, // VST4LNq32Pseudo_UPD
4548
1.14M
    2981939579U,  // VST4LNq32_UPD
4549
1.14M
    900860283U, // VST4d16
4550
1.14M
    0U, // VST4d16Pseudo
4551
1.14M
    0U, // VST4d16Pseudo_UPD
4552
1.14M
    2981431675U,  // VST4d16_UPD
4553
1.14M
    901384571U, // VST4d32
4554
1.14M
    0U, // VST4d32Pseudo
4555
1.14M
    0U, // VST4d32Pseudo_UPD
4556
1.14M
    2981955963U,  // VST4d32_UPD
4557
1.14M
    901908859U, // VST4d8
4558
1.14M
    0U, // VST4d8Pseudo
4559
1.14M
    0U, // VST4d8Pseudo_UPD
4560
1.14M
    2982480251U,  // VST4d8_UPD
4561
1.14M
    900860283U, // VST4q16
4562
1.14M
    0U, // VST4q16Pseudo_UPD
4563
1.14M
    2981431675U,  // VST4q16_UPD
4564
1.14M
    0U, // VST4q16oddPseudo
4565
1.14M
    0U, // VST4q16oddPseudo_UPD
4566
1.14M
    901384571U, // VST4q32
4567
1.14M
    0U, // VST4q32Pseudo_UPD
4568
1.14M
    2981955963U,  // VST4q32_UPD
4569
1.14M
    0U, // VST4q32oddPseudo
4570
1.14M
    0U, // VST4q32oddPseudo_UPD
4571
1.14M
    901908859U, // VST4q8
4572
1.14M
    0U, // VST4q8Pseudo_UPD
4573
1.14M
    2982480251U,  // VST4q8_UPD
4574
1.14M
    0U, // VST4q8oddPseudo
4575
1.14M
    0U, // VST4q8oddPseudo_UPD
4576
1.14M
    942173161U, // VSTMDDB_UPD
4577
1.14M
    2730773U, // VSTMDIA
4578
1.14M
    942172949U, // VSTMDIA_UPD
4579
1.14M
    0U, // VSTMQIA
4580
1.14M
    942173161U, // VSTMSDB_UPD
4581
1.14M
    2730773U, // VSTMSIA
4582
1.14M
    942172949U, // VSTMSIA_UPD
4583
1.14M
    2683391U, // VSTRD
4584
1.14M
    586239U,  // VSTRH
4585
1.14M
    2683391U, // VSTRS
4586
1.14M
    2647159295U,  // VSTR_FPCXTNS_off
4587
1.14M
    768143871U, // VSTR_FPCXTNS_post
4588
1.14M
    2714300927U,  // VSTR_FPCXTNS_pre
4589
1.14M
    2647683583U,  // VSTR_FPCXTS_off
4590
1.14M
    768668159U, // VSTR_FPCXTS_post
4591
1.14M
    2714825215U,  // VSTR_FPCXTS_pre
4592
1.14M
    2648207871U,  // VSTR_FPSCR_NZCVQC_off
4593
1.14M
    769192447U, // VSTR_FPSCR_NZCVQC_post
4594
1.14M
    2715349503U,  // VSTR_FPSCR_NZCVQC_pre
4595
1.14M
    2648732159U,  // VSTR_FPSCR_off
4596
1.14M
    769716735U, // VSTR_FPSCR_post
4597
1.14M
    2715873791U,  // VSTR_FPSCR_pre
4598
1.14M
    2783506943U,  // VSTR_P0_off
4599
1.14M
    1709748735U,  // VSTR_P0_post
4600
1.14M
    2850599423U,  // VSTR_P0_pre
4601
1.14M
    2649780735U,  // VSTR_VPR_off
4602
1.14M
    770765311U, // VSTR_VPR_post
4603
1.14M
    2716922367U,  // VSTR_VPR_pre
4604
1.14M
    1282469077U,  // VSUBD
4605
1.14M
    7924949U, // VSUBH
4606
1.14M
    962654336U, // VSUBHNv2i32
4607
1.14M
    14217344U,  // VSUBHNv4i16
4608
1.14M
    14741632U,  // VSUBHNv8i8
4609
1.14M
    11595604U,  // VSUBLsv2i64
4610
1.14M
    11071316U,  // VSUBLsv4i32
4611
1.14M
    12119892U,  // VSUBLsv8i16
4612
1.14M
    13168468U,  // VSUBLuv2i64
4613
1.14M
    12644180U,  // VSUBLuv4i32
4614
1.14M
    13692756U,  // VSUBLuv8i16
4615
1.14M
    8449237U, // VSUBS
4616
1.14M
    11596885U,  // VSUBWsv2i64
4617
1.14M
    11072597U,  // VSUBWsv4i32
4618
1.14M
    12121173U,  // VSUBWsv8i16
4619
1.14M
    13169749U,  // VSUBWuv2i64
4620
1.14M
    12645461U,  // VSUBWuv4i32
4621
1.14M
    13694037U,  // VSUBWuv8i16
4622
1.14M
    8449237U, // VSUBfd
4623
1.14M
    8449237U, // VSUBfq
4624
1.14M
    7924949U, // VSUBhd
4625
1.14M
    7924949U, // VSUBhq
4626
1.14M
    15264981U,  // VSUBv16i8
4627
1.14M
    962653397U, // VSUBv1i64
4628
1.14M
    14216405U,  // VSUBv2i32
4629
1.14M
    962653397U, // VSUBv2i64
4630
1.14M
    14740693U,  // VSUBv4i16
4631
1.14M
    14216405U,  // VSUBv4i32
4632
1.14M
    14740693U,  // VSUBv8i16
4633
1.14M
    15264981U,  // VSUBv8i8
4634
1.14M
    1010394817U,  // VSUDOTDI
4635
1.14M
    1010394817U,  // VSUDOTQI
4636
1.14M
    2666883U, // VSWPd
4637
1.14M
    2666883U, // VSWPq
4638
1.14M
    1634127U, // VTBL1
4639
1.14M
    1634127U, // VTBL2
4640
1.14M
    1634127U, // VTBL3
4641
1.14M
    0U, // VTBL3Pseudo
4642
1.14M
    1634127U, // VTBL4
4643
1.14M
    0U, // VTBL4Pseudo
4644
1.14M
    1619202U, // VTBX1
4645
1.14M
    1619202U, // VTBX2
4646
1.14M
    1619202U, // VTBX3
4647
1.14M
    0U, // VTBX3Pseudo
4648
1.14M
    1619202U, // VTBX4
4649
1.14M
    0U, // VTBX4Pseudo
4650
1.14M
    37811112U,  // VTOSHD
4651
1.14M
    1294529448U,  // VTOSHH
4652
1.14M
    38335400U,  // VTOSHS
4653
1.14M
    1235776004U,  // VTOSIRD
4654
1.14M
    1246786052U,  // VTOSIRH
4655
1.14M
    1227911684U,  // VTOSIRS
4656
1.14M
    1235776424U,  // VTOSIZD
4657
1.14M
    1246786472U,  // VTOSIZH
4658
1.14M
    1227912104U,  // VTOSIZS
4659
1.14M
    1302918056U,  // VTOSLD
4660
1.14M
    1313928104U,  // VTOSLH
4661
1.14M
    1295053736U,  // VTOSLS
4662
1.14M
    39383976U,  // VTOUHD
4663
1.14M
    1295578024U,  // VTOUHH
4664
1.14M
    39908264U,  // VTOUHS
4665
1.14M
    1248358916U,  // VTOUIRD
4666
1.14M
    1248883204U,  // VTOUIRH
4667
1.14M
    1228960260U,  // VTOUIRS
4668
1.14M
    1248359336U,  // VTOUIZD
4669
1.14M
    1248883624U,  // VTOUIZH
4670
1.14M
    1228960680U,  // VTOUIZS
4671
1.14M
    1315500968U,  // VTOULD
4672
1.14M
    1316025256U,  // VTOULH
4673
1.14M
    1296102312U,  // VTOULS
4674
1.14M
    569542U,  // VTRNd16
4675
1.14M
    1093830U, // VTRNd32
4676
1.14M
    1618118U, // VTRNd8
4677
1.14M
    569542U,  // VTRNq16
4678
1.14M
    1093830U, // VTRNq32
4679
1.14M
    1618118U, // VTRNq8
4680
1.14M
    1635191U, // VTSTv16i8
4681
1.14M
    1110903U, // VTSTv2i32
4682
1.14M
    586615U,  // VTSTv4i16
4683
1.14M
    1110903U, // VTSTv4i32
4684
1.14M
    586615U,  // VTSTv8i16
4685
1.14M
    1635191U, // VTSTv8i8
4686
1.14M
    1010394828U,  // VUDOTD
4687
1.14M
    1010394828U,  // VUDOTDI
4688
1.14M
    1010394828U,  // VUDOTQ
4689
1.14M
    1010394828U,  // VUDOTQI
4690
1.14M
    41481128U,  // VUHTOD
4691
1.14M
    1292432296U,  // VUHTOH
4692
1.14M
    42005416U,  // VUHTOS
4693
1.14M
    1250456488U,  // VUITOD
4694
1.14M
    1250980776U,  // VUITOH
4695
1.14M
    1226863528U,  // VUITOS
4696
1.14M
    1317598120U,  // VULTOD
4697
1.14M
    1318122408U,  // VULTOH
4698
1.14M
    1294005160U,  // VULTOS
4699
1.14M
    1010394806U,  // VUMMLA
4700
1.14M
    1010394785U,  // VUSDOTD
4701
1.14M
    1010394785U,  // VUSDOTDI
4702
1.14M
    1010394785U,  // VUSDOTQ
4703
1.14M
    1010394785U,  // VUSDOTQI
4704
1.14M
    1010394762U,  // VUSMMLA
4705
1.14M
    569736U,  // VUZPd16
4706
1.14M
    1618312U, // VUZPd8
4707
1.14M
    569736U,  // VUZPq16
4708
1.14M
    1094024U, // VUZPq32
4709
1.14M
    1618312U, // VUZPq8
4710
1.14M
    569612U,  // VZIPd16
4711
1.14M
    1618188U, // VZIPd8
4712
1.14M
    569612U,  // VZIPq16
4713
1.14M
    1093900U, // VZIPq32
4714
1.14M
    1618188U, // VZIPq8
4715
1.14M
    2730724U, // sysLDMDA
4716
1.14M
    942172900U, // sysLDMDA_UPD
4717
1.14M
    2730979U, // sysLDMDB
4718
1.14M
    942173155U, // sysLDMDB_UPD
4719
1.14M
    2732107U, // sysLDMIA
4720
1.14M
    942174283U, // sysLDMIA_UPD
4721
1.14M
    2730998U, // sysLDMIB
4722
1.14M
    942173174U, // sysLDMIB_UPD
4723
1.14M
    2730730U, // sysSTMDA
4724
1.14M
    942172906U, // sysSTMDA_UPD
4725
1.14M
    2730986U, // sysSTMDB
4726
1.14M
    942173162U, // sysSTMDB_UPD
4727
1.14M
    2732142U, // sysSTMIA
4728
1.14M
    942174318U, // sysSTMIA_UPD
4729
1.14M
    2731004U, // sysSTMIB
4730
1.14M
    942173180U, // sysSTMIB_UPD
4731
1.14M
    2632970U, // t2ADCri
4732
1.14M
    43527434U,  // t2ADCrr
4733
1.14M
    43584778U,  // t2ADCrs
4734
1.14M
    43527502U,  // t2ADDri
4735
1.14M
    2683996U, // t2ADDri12
4736
1.14M
    43527502U,  // t2ADDrr
4737
1.14M
    43584846U,  // t2ADDrs
4738
1.14M
    43527502U,  // t2ADDspImm
4739
1.14M
    2683996U, // t2ADDspImm12
4740
1.14M
    43544993U,  // t2ADR
4741
1.14M
    2633103U, // t2ANDri
4742
1.14M
    43527567U,  // t2ANDrr
4743
1.14M
    43584911U,  // t2ANDrs
4744
1.14M
    43528674U,  // t2ASRri
4745
1.14M
    43528674U,  // t2ASRrr
4746
1.14M
    4413U,  // t2AUT
4747
1.14M
    875154955U, // t2AUTG
4748
1.14M
    1117367220U,  // t2B
4749
1.14M
    2682130U, // t2BFC
4750
1.14M
    2666240U, // t2BFI
4751
1.14M
    1076391805U,  // t2BFLi
4752
1.14M
    1076393377U,  // t2BFLr
4753
1.14M
    1076391404U,  // t2BFi
4754
1.14M
    4029777812U,  // t2BFic
4755
1.14M
    1076393298U,  // t2BFr
4756
1.14M
    2632983U, // t2BICri
4757
1.14M
    43527447U,  // t2BICrr
4758
1.14M
    43584791U,  // t2BICrs
4759
1.14M
    1917U,  // t2BTI
4760
1.14M
    875156380U, // t2BXAUT
4761
1.14M
    2731794U, // t2BXJ
4762
1.14M
    1117367220U,  // t2Bcc
4763
1.14M
    1344934152U,  // t2CDP
4764
1.14M
    1344932154U,  // t2CDP2
4765
1.14M
    4838725U, // t2CLREX
4766
1.14M
    2888421472U,  // t2CLRM
4767
1.14M
    2651636U, // t2CLZ
4768
1.14M
    43544737U,  // t2CMNri
4769
1.14M
    43544737U,  // t2CMNzrr
4770
1.14M
    43577505U,  // t2CMNzrs
4771
1.14M
    43544850U,  // t2CMPri
4772
1.14M
    43544850U,  // t2CMPrr
4773
1.14M
    43577618U,  // t2CMPrs
4774
1.14M
    4802484U, // t2CPS1p
4775
1.14M
    1520095829U,  // t2CPS2p
4776
1.14M
    1479201365U,  // t2CPS3p
4777
1.14M
    942753529U, // t2CRC32B
4778
1.14M
    942753537U, // t2CRC32CB
4779
1.14M
    942753647U, // t2CRC32CH
4780
1.14M
    942753767U, // t2CRC32CW
4781
1.14M
    942753639U, // t2CRC32H
4782
1.14M
    942753759U, // t2CRC32W
4783
1.14M
    942753686U, // t2CSEL
4784
1.14M
    942753580U, // t2CSINC
4785
1.14M
    942753738U, // t2CSINV
4786
1.14M
    942753632U, // t2CSNEG
4787
1.14M
    2731508U, // t2DBG
4788
1.14M
    4835593U, // t2DCPS1
4789
1.14M
    4835658U, // t2DCPS2
4790
1.14M
    4835679U, // t2DCPS3
4791
1.14M
    942753706U, // t2DLS
4792
1.14M
    4096371749U,  // t2DMB
4793
1.14M
    4096371845U,  // t2DSB
4794
1.14M
    2634192U, // t2EORri
4795
1.14M
    43528656U,  // t2EORrr
4796
1.14M
    43586000U,  // t2EORrs
4797
1.14M
    43627272U,  // t2HINT
4798
1.14M
    4802513U, // t2HVC
4799
1.14M
    4163480713U,  // t2ISB
4800
1.14M
    69751512U,  // t2IT
4801
1.14M
    0U, // t2Int_eh_sjlj_setjmp
4802
1.14M
    0U, // t2Int_eh_sjlj_setjmp_nofp
4803
1.14M
    2648800U, // t2LDA
4804
1.14M
    2649009U, // t2LDAB
4805
1.14M
    2651443U, // t2LDAEX
4806
1.14M
    2649320U, // t2LDAEXB
4807
1.14M
    2682283U, // t2LDAEXD
4808
1.14M
    2649816U, // t2LDAEXH
4809
1.14M
    2649616U, // t2LDAH
4810
1.14M
    1344843542U,  // t2LDC2L_OFFSET
4811
1.14M
    1344843542U,  // t2LDC2L_OPTION
4812
1.14M
    1344843542U,  // t2LDC2L_POST
4813
1.14M
    1344843542U,  // t2LDC2L_PRE
4814
1.14M
    1344842016U,  // t2LDC2_OFFSET
4815
1.14M
    1344842016U,  // t2LDC2_OPTION
4816
1.14M
    1344842016U,  // t2LDC2_POST
4817
1.14M
    1344842016U,  // t2LDC2_PRE
4818
1.14M
    1344843610U,  // t2LDCL_OFFSET
4819
1.14M
    1344843610U,  // t2LDCL_OPTION
4820
1.14M
    1344843610U,  // t2LDCL_POST
4821
1.14M
    1344843610U,  // t2LDCL_PRE
4822
1.14M
    1344843022U,  // t2LDC_OFFSET
4823
1.14M
    1344843022U,  // t2LDC_OPTION
4824
1.14M
    1344843022U,  // t2LDC_POST
4825
1.14M
    1344843022U,  // t2LDC_PRE
4826
1.14M
    2730979U, // t2LDMDB
4827
1.14M
    942173155U, // t2LDMDB_UPD
4828
1.14M
    43626571U,  // t2LDMIA
4829
1.14M
    983068747U, // t2LDMIA_UPD
4830
1.14M
    2683552U, // t2LDRBT
4831
1.14M
    2665594U, // t2LDRB_POST
4832
1.14M
    2665594U, // t2LDRB_PRE
4833
1.14M
    43576442U,  // t2LDRBi12
4834
1.14M
    2681978U, // t2LDRBi8
4835
1.14M
    43543674U,  // t2LDRBpci
4836
1.14M
    43560058U,  // t2LDRBs
4837
1.14M
    2674068U, // t2LDRD_POST
4838
1.14M
    2674068U, // t2LDRD_PRE
4839
1.14M
    2665876U, // t2LDRDi8
4840
1.14M
    2684223U, // t2LDREX
4841
1.14M
    2649334U, // t2LDREXB
4842
1.14M
    2682297U, // t2LDREXD
4843
1.14M
    2649830U, // t2LDREXH
4844
1.14M
    2683587U, // t2LDRHT
4845
1.14M
    2666112U, // t2LDRH_POST
4846
1.14M
    2666112U, // t2LDRH_PRE
4847
1.14M
    43576960U,  // t2LDRHi12
4848
1.14M
    2682496U, // t2LDRHi8
4849
1.14M
    43544192U,  // t2LDRHpci
4850
1.14M
    43560576U,  // t2LDRHs
4851
1.14M
    2683564U, // t2LDRSBT
4852
1.14M
    2665613U, // t2LDRSB_POST
4853
1.14M
    2665613U, // t2LDRSB_PRE
4854
1.14M
    43576461U,  // t2LDRSBi12
4855
1.14M
    2681997U, // t2LDRSBi8
4856
1.14M
    43543693U,  // t2LDRSBpci
4857
1.14M
    43560077U,  // t2LDRSBs
4858
1.14M
    2683599U, // t2LDRSHT
4859
1.14M
    2666151U, // t2LDRSH_POST
4860
1.14M
    2666151U, // t2LDRSH_PRE
4861
1.14M
    43576999U,  // t2LDRSHi12
4862
1.14M
    2682535U, // t2LDRSHi8
4863
1.14M
    43544231U,  // t2LDRSHpci
4864
1.14M
    43560615U,  // t2LDRSHs
4865
1.14M
    2683746U, // t2LDRT
4866
1.14M
    2666918U, // t2LDR_POST
4867
1.14M
    2666918U, // t2LDR_PRE
4868
1.14M
    43577766U,  // t2LDRi12
4869
1.14M
    2683302U, // t2LDRi8
4870
1.14M
    43544998U,  // t2LDRpci
4871
1.14M
    43561382U,  // t2LDRs
4872
1.14M
    4818775U, // t2LE
4873
1.14M
    10577751U,  // t2LEUpdate
4874
1.14M
    43528222U,  // t2LSLri
4875
1.14M
    43528222U,  // t2LSLrr
4876
1.14M
    43528681U,  // t2LSRri
4877
1.14M
    43528681U,  // t2LSRrr
4878
1.14M
    1344934301U,  // t2MCR
4879
1.14M
    1344932159U,  // t2MCR2
4880
1.14M
    1344852440U,  // t2MCRR
4881
1.14M
    1344850244U,  // t2MCRR2
4882
1.14M
    2665252U, // t2MLA
4883
1.14M
    2667053U, // t2MLS
4884
1.14M
    2683821U, // t2MOVTi16
4885
1.14M
    43553867U,  // t2MOVi
4886
1.14M
    2651250U, // t2MOVi16
4887
1.14M
    43553867U,  // t2MOVr
4888
1.14M
    43545182U,  // t2MOVsra_glue
4889
1.14M
    43545187U,  // t2MOVsrl_glue
4890
1.14M
    1143606565U,  // t2MRC
4891
1.14M
    1143605541U,  // t2MRC2
4892
1.14M
    1814613289U,  // t2MRRC
4893
1.14M
    1814612266U,  // t2MRRC2
4894
1.14M
    2732634U, // t2MRS_AR
4895
1.14M
    2650714U, // t2MRS_M
4896
1.14M
    2650714U, // t2MRSbanked
4897
1.14M
    2732634U, // t2MRSsys_AR
4898
1.14M
    1881698798U,  // t2MSR_AR
4899
1.14M
    1881698798U,  // t2MSR_M
4900
1.14M
    1948807662U,  // t2MSRbanked
4901
1.14M
    2682926U, // t2MUL
4902
1.14M
    2658546U, // t2MVNi
4903
1.14M
    43553010U,  // t2MVNr
4904
1.14M
    43528434U,  // t2MVNs
4905
1.14M
    2633922U, // t2ORNri
4906
1.14M
    2633922U, // t2ORNrr
4907
1.14M
    2691266U, // t2ORNrs
4908
1.14M
    2634206U, // t2ORRri
4909
1.14M
    43528670U,  // t2ORRrr
4910
1.14M
    43586014U,  // t2ORRrs
4911
1.14M
    4378U,  // t2PAC
4912
1.14M
    4394U,  // t2PACBTI
4913
1.14M
    2731512U, // t2PACG
4914
1.14M
    2667147U, // t2PKHBT
4915
1.14M
    2665630U, // t2PKHTB
4916
1.14M
    4230509665U,  // t2PLDWi12
4917
1.14M
    2651233U, // t2PLDWi8
4918
1.14M
    69792865U,  // t2PLDWs
4919
1.14M
    4230507907U,  // t2PLDi12
4920
1.14M
    2649475U, // t2PLDi8
4921
1.14M
    136949123U, // t2PLDpci
4922
1.14M
    69791107U,  // t2PLDs
4923
1.14M
    4230508292U,  // t2PLIi12
4924
1.14M
    2649860U, // t2PLIi8
4925
1.14M
    136949508U, // t2PLIpci
4926
1.14M
    69791492U,  // t2PLIs
4927
1.14M
    2682226U, // t2QADD
4928
1.14M
    2681301U, // t2QADD16
4929
1.14M
    2681404U, // t2QADD8
4930
1.14M
    2684343U, // t2QASX
4931
1.14M
    2682200U, // t2QDADD
4932
1.14M
    2682051U, // t2QDSUB
4933
1.14M
    2684089U, // t2QSAX
4934
1.14M
    2682064U, // t2QSUB
4935
1.14M
    2681263U, // t2QSUB16
4936
1.14M
    2681365U, // t2QSUB8
4937
1.14M
    2650838U, // t2RBIT
4938
1.14M
    43545626U,  // t2REV
4939
1.14M
    43543033U,  // t2REV16
4940
1.14M
    43544242U,  // t2REVSH
4941
1.14M
    2730972U, // t2RFEDB
4942
1.14M
    2730972U, // t2RFEDBW
4943
1.14M
    2730760U, // t2RFEIA
4944
1.14M
    2730760U, // t2RFEIAW
4945
1.14M
    43528660U,  // t2RORri
4946
1.14M
    43528660U,  // t2RORrr
4947
1.14M
    2659750U, // t2RRX
4948
1.14M
    43527311U,  // t2RSBri
4949
1.14M
    2632847U, // t2RSBrr
4950
1.14M
    2690191U, // t2RSBrs
4951
1.14M
    2681308U, // t2SADD16
4952
1.14M
    2681410U, // t2SADD8
4953
1.14M
    2684348U, // t2SASX
4954
1.14M
    3206U,  // t2SB
4955
1.14M
    2632965U, // t2SBCri
4956
1.14M
    43527429U,  // t2SBCrr
4957
1.14M
    43584773U,  // t2SBCrs
4958
1.14M
    2667857U, // t2SBFX
4959
1.14M
    2683934U, // t2SDIV
4960
1.14M
    2682745U, // t2SEL
4961
1.14M
    4802460U, // t2SETPAN
4962
1.14M
    4836872U, // t2SG
4963
1.14M
    2681284U, // t2SHADD16
4964
1.14M
    2681389U, // t2SHADD8
4965
1.14M
    2684330U, // t2SHASX
4966
1.14M
    2684076U, // t2SHSAX
4967
1.14M
    2681246U, // t2SHSUB16
4968
1.14M
    2681350U, // t2SHSUB8
4969
1.14M
    2731297U, // t2SMC
4970
1.14M
    2665410U, // t2SMLABB
4971
1.14M
    2667140U, // t2SMLABT
4972
1.14M
    2665786U, // t2SMLAD
4973
1.14M
    2667783U, // t2SMLADX
4974
1.14M
    2756413U, // t2SMLAL
4975
1.14M
    2755529U, // t2SMLALBB
4976
1.14M
    2757265U, // t2SMLALBT
4977
1.14M
    2755964U, // t2SMLALD
4978
1.14M
    2757909U, // t2SMLALDX
4979
1.14M
    2755748U, // t2SMLALTB
4980
1.14M
    2757507U, // t2SMLALTT
4981
1.14M
    2665623U, // t2SMLATB
4982
1.14M
    2667388U, // t2SMLATT
4983
1.14M
    2665690U, // t2SMLAWB
4984
1.14M
    2667442U, // t2SMLAWT
4985
1.14M
    2665887U, // t2SMLSD
4986
1.14M
    2667813U, // t2SMLSDX
4987
1.14M
    2755975U, // t2SMLSLD
4988
1.14M
    2757917U, // t2SMLSLDX
4989
1.14M
    2665256U, // t2SMMLA
4990
1.14M
    2666902U, // t2SMMLAR
4991
1.14M
    2667051U, // t2SMMLS
4992
1.14M
    2666982U, // t2SMMLSR
4993
1.14M
    2682930U, // t2SMMUL
4994
1.14M
    2683336U, // t2SMMULR
4995
1.14M
    2682176U, // t2SMUAD
4996
1.14M
    2684174U, // t2SMUADX
4997
1.14M
    2681809U, // t2SMULBB
4998
1.14M
    2683545U, // t2SMULBT
4999
1.14M
    2666467U, // t2SMULL
5000
1.14M
    2682028U, // t2SMULTB
5001
1.14M
    2683787U, // t2SMULTT
5002
1.14M
    2682081U, // t2SMULWB
5003
1.14M
    2683833U, // t2SMULWT
5004
1.14M
    2682277U, // t2SMUSD
5005
1.14M
    2684204U, // t2SMUSDX
5006
1.14M
    44149744U,  // t2SRSDB
5007
1.14M
    44674032U,  // t2SRSDB_UPD
5008
1.14M
    44149532U,  // t2SRSIA
5009
1.14M
    44673820U,  // t2SRSIA_UPD
5010
1.14M
    2667125U, // t2SSAT
5011
1.14M
    2681322U, // t2SSAT16
5012
1.14M
    2684094U, // t2SSAX
5013
1.14M
    2681270U, // t2SSUB16
5014
1.14M
    2681371U, // t2SSUB8
5015
1.14M
    1344843548U,  // t2STC2L_OFFSET
5016
1.14M
    1344843548U,  // t2STC2L_OPTION
5017
1.14M
    1344843548U,  // t2STC2L_POST
5018
1.14M
    1344843548U,  // t2STC2L_PRE
5019
1.14M
    1344842032U,  // t2STC2_OFFSET
5020
1.14M
    1344842032U,  // t2STC2_OPTION
5021
1.14M
    1344842032U,  // t2STC2_POST
5022
1.14M
    1344842032U,  // t2STC2_PRE
5023
1.14M
    1344843615U,  // t2STCL_OFFSET
5024
1.14M
    1344843615U,  // t2STCL_OPTION
5025
1.14M
    1344843615U,  // t2STCL_POST
5026
1.14M
    1344843615U,  // t2STCL_PRE
5027
1.14M
    1344843058U,  // t2STC_OFFSET
5028
1.14M
    1344843058U,  // t2STC_OPTION
5029
1.14M
    1344843058U,  // t2STC_POST
5030
1.14M
    1344843058U,  // t2STC_PRE
5031
1.14M
    2650152U, // t2STL
5032
1.14M
    2649113U, // t2STLB
5033
1.14M
    2684217U, // t2STLEX
5034
1.14M
    2682095U, // t2STLEXB
5035
1.14M
    2665906U, // t2STLEXD
5036
1.14M
    2682591U, // t2STLEXH
5037
1.14M
    2649692U, // t2STLH
5038
1.14M
    2730986U, // t2STMDB
5039
1.14M
    942173162U, // t2STMDB_UPD
5040
1.14M
    43626606U,  // t2STMIA
5041
1.14M
    983068782U, // t2STMIA_UPD
5042
1.14M
    2683558U, // t2STRBT
5043
1.14M
    942189696U, // t2STRB_POST
5044
1.14M
    942189696U, // t2STRB_PRE
5045
1.14M
    43576448U,  // t2STRBi12
5046
1.14M
    2681984U, // t2STRBi8
5047
1.14M
    43560064U,  // t2STRBs
5048
1.14M
    942198170U, // t2STRD_POST
5049
1.14M
    942198170U, // t2STRD_PRE
5050
1.14M
    2665882U, // t2STRDi8
5051
1.14M
    2667851U, // t2STREX
5052
1.14M
    2682109U, // t2STREXB
5053
1.14M
    2665920U, // t2STREXD
5054
1.14M
    2682605U, // t2STREXH
5055
1.14M
    2683593U, // t2STRHT
5056
1.14M
    942190214U, // t2STRH_POST
5057
1.14M
    942190214U, // t2STRH_PRE
5058
1.14M
    43576966U,  // t2STRHi12
5059
1.14M
    2682502U, // t2STRHi8
5060
1.14M
    43560582U,  // t2STRHs
5061
1.14M
    2683757U, // t2STRT
5062
1.14M
    942191104U, // t2STR_POST
5063
1.14M
    942191104U, // t2STR_PRE
5064
1.14M
    43577856U,  // t2STRi12
5065
1.14M
    2683392U, // t2STRi8
5066
1.14M
    43561472U,  // t2STRs
5067
1.14M
    45199905U,  // t2SUBS_PC_LR
5068
1.14M
    43527365U,  // t2SUBri
5069
1.14M
    2683990U, // t2SUBri12
5070
1.14M
    43527365U,  // t2SUBrr
5071
1.14M
    43584709U,  // t2SUBrs
5072
1.14M
    43527365U,  // t2SUBspImm
5073
1.14M
    2683990U, // t2SUBspImm12
5074
1.14M
    2665398U, // t2SXTAB
5075
1.14M
    2664832U, // t2SXTAB16
5076
1.14M
    2666022U, // t2SXTAH
5077
1.14M
    43576505U,  // t2SXTB
5078
1.14M
    2681232U, // t2SXTB16
5079
1.14M
    43577016U,  // t2SXTH
5080
1.14M
    203975640U, // t2TBB
5081
1.14M
    271085106U, // t2TBH
5082
1.14M
    43544978U,  // t2TEQri
5083
1.14M
    43544978U,  // t2TEQrr
5084
1.14M
    43577746U,  // t2TEQrs
5085
1.14M
    338275475U, // t2TSB
5086
1.14M
    43545464U,  // t2TSTri
5087
1.14M
    43545464U,  // t2TSTrr
5088
1.14M
    43578232U,  // t2TSTrs
5089
1.14M
    2651008U, // t2TT
5090
1.14M
    2648940U, // t2TTA
5091
1.14M
    2650751U, // t2TTAT
5092
1.14M
    2651026U, // t2TTT
5093
1.14M
    2681315U, // t2UADD16
5094
1.14M
    2681416U, // t2UADD8
5095
1.14M
    2684353U, // t2UASX
5096
1.14M
    2667862U, // t2UBFX
5097
1.14M
    4802520U, // t2UDF
5098
1.14M
    2683939U, // t2UDIV
5099
1.14M
    2681292U, // t2UHADD16
5100
1.14M
    2681396U, // t2UHADD8
5101
1.14M
    2684336U, // t2UHASX
5102
1.14M
    2684082U, // t2UHSAX
5103
1.14M
    2681254U, // t2UHSUB16
5104
1.14M
    2681357U, // t2UHSUB8
5105
1.14M
    2756386U, // t2UMAAL
5106
1.14M
    2756419U, // t2UMLAL
5107
1.14M
    2666473U, // t2UMULL
5108
1.14M
    2681300U, // t2UQADD16
5109
1.14M
    2681403U, // t2UQADD8
5110
1.14M
    2684342U, // t2UQASX
5111
1.14M
    2684088U, // t2UQSAX
5112
1.14M
    2681262U, // t2UQSUB16
5113
1.14M
    2681364U, // t2UQSUB8
5114
1.14M
    2681383U, // t2USAD8
5115
1.14M
    2664959U, // t2USADA8
5116
1.14M
    2667130U, // t2USAT
5117
1.14M
    2681329U, // t2USAT16
5118
1.14M
    2684099U, // t2USAX
5119
1.14M
    2681277U, // t2USUB16
5120
1.14M
    2681377U, // t2USUB8
5121
1.14M
    2665404U, // t2UXTAB
5122
1.14M
    2664840U, // t2UXTAB16
5123
1.14M
    2666028U, // t2UXTAH
5124
1.14M
    43576510U,  // t2UXTB
5125
1.14M
    2681239U, // t2UXTB16
5126
1.14M
    43577021U,  // t2UXTH
5127
1.14M
    942753711U, // t2WLS
5128
1.14M
    1052593418U,  // tADC
5129
1.14M
    2682190U, // tADDhirr
5130
1.14M
    918375758U, // tADDi3
5131
1.14M
    1052593486U,  // tADDi8
5132
1.14M
    2682190U, // tADDrSP
5133
1.14M
    2682190U, // tADDrSPi
5134
1.14M
    918375758U, // tADDrr
5135
1.14M
    2682190U, // tADDspi
5136
1.14M
    2682190U, // tADDspr
5137
1.14M
    2650529U, // tADR
5138
1.14M
    1052593551U,  // tAND
5139
1.14M
    918376930U, // tASRri
5140
1.14M
    1052594658U,  // tASRrr
5141
1.14M
    1076472756U,  // tB
5142
1.14M
    1052593431U,  // tBIC
5143
1.14M
    4802500U, // tBKPT
5144
1.14M
    405393233U, // tBL
5145
1.14M
    875156044U, // tBLXNSr
5146
1.14M
    405394845U, // tBLXi
5147
1.14M
    875156893U, // tBLXr
5148
1.14M
    2733303U, // tBX
5149
1.14M
    2732615U, // tBXNS
5150
1.14M
    1076472756U,  // tBcc
5151
1.14M
    4029761540U,  // tCBNZ
5152
1.14M
    4029761535U,  // tCBZ
5153
1.14M
    2650273U, // tCMNz
5154
1.14M
    2650386U, // tCMPhir
5155
1.14M
    2650386U, // tCMPi8
5156
1.14M
    2650386U, // tCMPr
5157
1.14M
    1476579925U,  // tCPS
5158
1.14M
    1052594640U,  // tEOR
5159
1.14M
    2732808U, // tHINT
5160
1.14M
    4802495U, // tHLT
5161
1.14M
    0U, // tInt_WIN_eh_sjlj_longjmp
5162
1.14M
    0U, // tInt_eh_sjlj_longjmp
5163
1.14M
    0U, // tInt_eh_sjlj_setjmp
5164
1.14M
    2732107U, // tLDMIA
5165
1.14M
    2681978U, // tLDRBi
5166
1.14M
    2681978U, // tLDRBr
5167
1.14M
    2682496U, // tLDRHi
5168
1.14M
    2682496U, // tLDRHr
5169
1.14M
    2681997U, // tLDRSB
5170
1.14M
    2682535U, // tLDRSH
5171
1.14M
    2683302U, // tLDRi
5172
1.14M
    2650534U, // tLDRpci
5173
1.14M
    2683302U, // tLDRr
5174
1.14M
    2683302U, // tLDRspi
5175
1.14M
    918376478U, // tLSLri
5176
1.14M
    1052594206U,  // tLSLrr
5177
1.14M
    918376937U, // tLSRri
5178
1.14M
    1052594665U,  // tLSRrr
5179
1.14M
    942753721U, // tMOVSr
5180
1.14M
    1254446155U,  // tMOVi8
5181
1.14M
    2651211U, // tMOVr
5182
1.14M
    918376494U, // tMUL
5183
1.14M
    1254445298U,  // tMVN
5184
1.14M
    1052594654U,  // tORR
5185
1.14M
    0U, // tPICADD
5186
1.14M
    2888421654U,  // tPOP
5187
1.14M
    2888421037U,  // tPUSH
5188
1.14M
    2651162U, // tREV
5189
1.14M
    2648569U, // tREV16
5190
1.14M
    2649778U, // tREVSH
5191
1.14M
    1052594644U,  // tROR
5192
1.14M
    2193968271U,  // tRSB
5193
1.14M
    1052593413U,  // tSBC
5194
1.14M
    280399U,  // tSETEND
5195
1.14M
    942174318U, // tSTMIA_UPD
5196
1.14M
    2681984U, // tSTRBi
5197
1.14M
    2681984U, // tSTRBr
5198
1.14M
    2682502U, // tSTRHi
5199
1.14M
    2682502U, // tSTRHr
5200
1.14M
    2683392U, // tSTRi
5201
1.14M
    2683392U, // tSTRr
5202
1.14M
    2683392U, // tSTRspi
5203
1.14M
    918375621U, // tSUBi3
5204
1.14M
    1052593349U,  // tSUBi8
5205
1.14M
    918375621U, // tSUBrr
5206
1.14M
    2682053U, // tSUBspi
5207
1.14M
    2731318U, // tSVC
5208
1.14M
    2649273U, // tSXTB
5209
1.14M
    2649784U, // tSXTH
5210
1.14M
    4355U,  // tTRAP
5211
1.14M
    2651000U, // tTST
5212
1.14M
    4802395U, // tUDF
5213
1.14M
    2649278U, // tUXTB
5214
1.14M
    2649789U, // tUXTH
5215
1.14M
    2298U,  // t__brkdiv0
5216
1.14M
  };
5217
5218
1.14M
  static const uint32_t OpInfo1[] = {
5219
1.14M
    0U, // PHI
5220
1.14M
    0U, // INLINEASM
5221
1.14M
    0U, // INLINEASM_BR
5222
1.14M
    0U, // CFI_INSTRUCTION
5223
1.14M
    0U, // EH_LABEL
5224
1.14M
    0U, // GC_LABEL
5225
1.14M
    0U, // ANNOTATION_LABEL
5226
1.14M
    0U, // KILL
5227
1.14M
    0U, // EXTRACT_SUBREG
5228
1.14M
    0U, // INSERT_SUBREG
5229
1.14M
    0U, // IMPLICIT_DEF
5230
1.14M
    0U, // SUBREG_TO_REG
5231
1.14M
    0U, // COPY_TO_REGCLASS
5232
1.14M
    0U, // DBG_VALUE
5233
1.14M
    0U, // DBG_VALUE_LIST
5234
1.14M
    0U, // DBG_INSTR_REF
5235
1.14M
    0U, // DBG_PHI
5236
1.14M
    0U, // DBG_LABEL
5237
1.14M
    0U, // REG_SEQUENCE
5238
1.14M
    0U, // COPY
5239
1.14M
    0U, // BUNDLE
5240
1.14M
    0U, // LIFETIME_START
5241
1.14M
    0U, // LIFETIME_END
5242
1.14M
    0U, // PSEUDO_PROBE
5243
1.14M
    0U, // ARITH_FENCE
5244
1.14M
    0U, // STACKMAP
5245
1.14M
    0U, // FENTRY_CALL
5246
1.14M
    0U, // PATCHPOINT
5247
1.14M
    0U, // LOAD_STACK_GUARD
5248
1.14M
    0U, // PREALLOCATED_SETUP
5249
1.14M
    0U, // PREALLOCATED_ARG
5250
1.14M
    0U, // STATEPOINT
5251
1.14M
    0U, // LOCAL_ESCAPE
5252
1.14M
    0U, // FAULTING_OP
5253
1.14M
    0U, // PATCHABLE_OP
5254
1.14M
    0U, // PATCHABLE_FUNCTION_ENTER
5255
1.14M
    0U, // PATCHABLE_RET
5256
1.14M
    0U, // PATCHABLE_FUNCTION_EXIT
5257
1.14M
    0U, // PATCHABLE_TAIL_CALL
5258
1.14M
    0U, // PATCHABLE_EVENT_CALL
5259
1.14M
    0U, // PATCHABLE_TYPED_EVENT_CALL
5260
1.14M
    0U, // ICALL_BRANCH_FUNNEL
5261
1.14M
    0U, // MEMBARRIER
5262
1.14M
    0U, // JUMP_TABLE_DEBUG_INFO
5263
1.14M
    0U, // G_ASSERT_SEXT
5264
1.14M
    0U, // G_ASSERT_ZEXT
5265
1.14M
    0U, // G_ASSERT_ALIGN
5266
1.14M
    0U, // G_ADD
5267
1.14M
    0U, // G_SUB
5268
1.14M
    0U, // G_MUL
5269
1.14M
    0U, // G_SDIV
5270
1.14M
    0U, // G_UDIV
5271
1.14M
    0U, // G_SREM
5272
1.14M
    0U, // G_UREM
5273
1.14M
    0U, // G_SDIVREM
5274
1.14M
    0U, // G_UDIVREM
5275
1.14M
    0U, // G_AND
5276
1.14M
    0U, // G_OR
5277
1.14M
    0U, // G_XOR
5278
1.14M
    0U, // G_IMPLICIT_DEF
5279
1.14M
    0U, // G_PHI
5280
1.14M
    0U, // G_FRAME_INDEX
5281
1.14M
    0U, // G_GLOBAL_VALUE
5282
1.14M
    0U, // G_CONSTANT_POOL
5283
1.14M
    0U, // G_EXTRACT
5284
1.14M
    0U, // G_UNMERGE_VALUES
5285
1.14M
    0U, // G_INSERT
5286
1.14M
    0U, // G_MERGE_VALUES
5287
1.14M
    0U, // G_BUILD_VECTOR
5288
1.14M
    0U, // G_BUILD_VECTOR_TRUNC
5289
1.14M
    0U, // G_CONCAT_VECTORS
5290
1.14M
    0U, // G_PTRTOINT
5291
1.14M
    0U, // G_INTTOPTR
5292
1.14M
    0U, // G_BITCAST
5293
1.14M
    0U, // G_FREEZE
5294
1.14M
    0U, // G_CONSTANT_FOLD_BARRIER
5295
1.14M
    0U, // G_INTRINSIC_FPTRUNC_ROUND
5296
1.14M
    0U, // G_INTRINSIC_TRUNC
5297
1.14M
    0U, // G_INTRINSIC_ROUND
5298
1.14M
    0U, // G_INTRINSIC_LRINT
5299
1.14M
    0U, // G_INTRINSIC_ROUNDEVEN
5300
1.14M
    0U, // G_READCYCLECOUNTER
5301
1.14M
    0U, // G_LOAD
5302
1.14M
    0U, // G_SEXTLOAD
5303
1.14M
    0U, // G_ZEXTLOAD
5304
1.14M
    0U, // G_INDEXED_LOAD
5305
1.14M
    0U, // G_INDEXED_SEXTLOAD
5306
1.14M
    0U, // G_INDEXED_ZEXTLOAD
5307
1.14M
    0U, // G_STORE
5308
1.14M
    0U, // G_INDEXED_STORE
5309
1.14M
    0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
5310
1.14M
    0U, // G_ATOMIC_CMPXCHG
5311
1.14M
    0U, // G_ATOMICRMW_XCHG
5312
1.14M
    0U, // G_ATOMICRMW_ADD
5313
1.14M
    0U, // G_ATOMICRMW_SUB
5314
1.14M
    0U, // G_ATOMICRMW_AND
5315
1.14M
    0U, // G_ATOMICRMW_NAND
5316
1.14M
    0U, // G_ATOMICRMW_OR
5317
1.14M
    0U, // G_ATOMICRMW_XOR
5318
1.14M
    0U, // G_ATOMICRMW_MAX
5319
1.14M
    0U, // G_ATOMICRMW_MIN
5320
1.14M
    0U, // G_ATOMICRMW_UMAX
5321
1.14M
    0U, // G_ATOMICRMW_UMIN
5322
1.14M
    0U, // G_ATOMICRMW_FADD
5323
1.14M
    0U, // G_ATOMICRMW_FSUB
5324
1.14M
    0U, // G_ATOMICRMW_FMAX
5325
1.14M
    0U, // G_ATOMICRMW_FMIN
5326
1.14M
    0U, // G_ATOMICRMW_UINC_WRAP
5327
1.14M
    0U, // G_ATOMICRMW_UDEC_WRAP
5328
1.14M
    0U, // G_FENCE
5329
1.14M
    0U, // G_PREFETCH
5330
1.14M
    0U, // G_BRCOND
5331
1.14M
    0U, // G_BRINDIRECT
5332
1.14M
    0U, // G_INVOKE_REGION_START
5333
1.14M
    0U, // G_INTRINSIC
5334
1.14M
    0U, // G_INTRINSIC_W_SIDE_EFFECTS
5335
1.14M
    0U, // G_INTRINSIC_CONVERGENT
5336
1.14M
    0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
5337
1.14M
    0U, // G_ANYEXT
5338
1.14M
    0U, // G_TRUNC
5339
1.14M
    0U, // G_CONSTANT
5340
1.14M
    0U, // G_FCONSTANT
5341
1.14M
    0U, // G_VASTART
5342
1.14M
    0U, // G_VAARG
5343
1.14M
    0U, // G_SEXT
5344
1.14M
    0U, // G_SEXT_INREG
5345
1.14M
    0U, // G_ZEXT
5346
1.14M
    0U, // G_SHL
5347
1.14M
    0U, // G_LSHR
5348
1.14M
    0U, // G_ASHR
5349
1.14M
    0U, // G_FSHL
5350
1.14M
    0U, // G_FSHR
5351
1.14M
    0U, // G_ROTR
5352
1.14M
    0U, // G_ROTL
5353
1.14M
    0U, // G_ICMP
5354
1.14M
    0U, // G_FCMP
5355
1.14M
    0U, // G_SELECT
5356
1.14M
    0U, // G_UADDO
5357
1.14M
    0U, // G_UADDE
5358
1.14M
    0U, // G_USUBO
5359
1.14M
    0U, // G_USUBE
5360
1.14M
    0U, // G_SADDO
5361
1.14M
    0U, // G_SADDE
5362
1.14M
    0U, // G_SSUBO
5363
1.14M
    0U, // G_SSUBE
5364
1.14M
    0U, // G_UMULO
5365
1.14M
    0U, // G_SMULO
5366
1.14M
    0U, // G_UMULH
5367
1.14M
    0U, // G_SMULH
5368
1.14M
    0U, // G_UADDSAT
5369
1.14M
    0U, // G_SADDSAT
5370
1.14M
    0U, // G_USUBSAT
5371
1.14M
    0U, // G_SSUBSAT
5372
1.14M
    0U, // G_USHLSAT
5373
1.14M
    0U, // G_SSHLSAT
5374
1.14M
    0U, // G_SMULFIX
5375
1.14M
    0U, // G_UMULFIX
5376
1.14M
    0U, // G_SMULFIXSAT
5377
1.14M
    0U, // G_UMULFIXSAT
5378
1.14M
    0U, // G_SDIVFIX
5379
1.14M
    0U, // G_UDIVFIX
5380
1.14M
    0U, // G_SDIVFIXSAT
5381
1.14M
    0U, // G_UDIVFIXSAT
5382
1.14M
    0U, // G_FADD
5383
1.14M
    0U, // G_FSUB
5384
1.14M
    0U, // G_FMUL
5385
1.14M
    0U, // G_FMA
5386
1.14M
    0U, // G_FMAD
5387
1.14M
    0U, // G_FDIV
5388
1.14M
    0U, // G_FREM
5389
1.14M
    0U, // G_FPOW
5390
1.14M
    0U, // G_FPOWI
5391
1.14M
    0U, // G_FEXP
5392
1.14M
    0U, // G_FEXP2
5393
1.14M
    0U, // G_FEXP10
5394
1.14M
    0U, // G_FLOG
5395
1.14M
    0U, // G_FLOG2
5396
1.14M
    0U, // G_FLOG10
5397
1.14M
    0U, // G_FLDEXP
5398
1.14M
    0U, // G_FFREXP
5399
1.14M
    0U, // G_FNEG
5400
1.14M
    0U, // G_FPEXT
5401
1.14M
    0U, // G_FPTRUNC
5402
1.14M
    0U, // G_FPTOSI
5403
1.14M
    0U, // G_FPTOUI
5404
1.14M
    0U, // G_SITOFP
5405
1.14M
    0U, // G_UITOFP
5406
1.14M
    0U, // G_FABS
5407
1.14M
    0U, // G_FCOPYSIGN
5408
1.14M
    0U, // G_IS_FPCLASS
5409
1.14M
    0U, // G_FCANONICALIZE
5410
1.14M
    0U, // G_FMINNUM
5411
1.14M
    0U, // G_FMAXNUM
5412
1.14M
    0U, // G_FMINNUM_IEEE
5413
1.14M
    0U, // G_FMAXNUM_IEEE
5414
1.14M
    0U, // G_FMINIMUM
5415
1.14M
    0U, // G_FMAXIMUM
5416
1.14M
    0U, // G_GET_FPENV
5417
1.14M
    0U, // G_SET_FPENV
5418
1.14M
    0U, // G_RESET_FPENV
5419
1.14M
    0U, // G_GET_FPMODE
5420
1.14M
    0U, // G_SET_FPMODE
5421
1.14M
    0U, // G_RESET_FPMODE
5422
1.14M
    0U, // G_PTR_ADD
5423
1.14M
    0U, // G_PTRMASK
5424
1.14M
    0U, // G_SMIN
5425
1.14M
    0U, // G_SMAX
5426
1.14M
    0U, // G_UMIN
5427
1.14M
    0U, // G_UMAX
5428
1.14M
    0U, // G_ABS
5429
1.14M
    0U, // G_LROUND
5430
1.14M
    0U, // G_LLROUND
5431
1.14M
    0U, // G_BR
5432
1.14M
    0U, // G_BRJT
5433
1.14M
    0U, // G_INSERT_VECTOR_ELT
5434
1.14M
    0U, // G_EXTRACT_VECTOR_ELT
5435
1.14M
    0U, // G_SHUFFLE_VECTOR
5436
1.14M
    0U, // G_CTTZ
5437
1.14M
    0U, // G_CTTZ_ZERO_UNDEF
5438
1.14M
    0U, // G_CTLZ
5439
1.14M
    0U, // G_CTLZ_ZERO_UNDEF
5440
1.14M
    0U, // G_CTPOP
5441
1.14M
    0U, // G_BSWAP
5442
1.14M
    0U, // G_BITREVERSE
5443
1.14M
    0U, // G_FCEIL
5444
1.14M
    0U, // G_FCOS
5445
1.14M
    0U, // G_FSIN
5446
1.14M
    0U, // G_FSQRT
5447
1.14M
    0U, // G_FFLOOR
5448
1.14M
    0U, // G_FRINT
5449
1.14M
    0U, // G_FNEARBYINT
5450
1.14M
    0U, // G_ADDRSPACE_CAST
5451
1.14M
    0U, // G_BLOCK_ADDR
5452
1.14M
    0U, // G_JUMP_TABLE
5453
1.14M
    0U, // G_DYN_STACKALLOC
5454
1.14M
    0U, // G_STACKSAVE
5455
1.14M
    0U, // G_STACKRESTORE
5456
1.14M
    0U, // G_STRICT_FADD
5457
1.14M
    0U, // G_STRICT_FSUB
5458
1.14M
    0U, // G_STRICT_FMUL
5459
1.14M
    0U, // G_STRICT_FDIV
5460
1.14M
    0U, // G_STRICT_FREM
5461
1.14M
    0U, // G_STRICT_FMA
5462
1.14M
    0U, // G_STRICT_FSQRT
5463
1.14M
    0U, // G_STRICT_FLDEXP
5464
1.14M
    0U, // G_READ_REGISTER
5465
1.14M
    0U, // G_WRITE_REGISTER
5466
1.14M
    0U, // G_MEMCPY
5467
1.14M
    0U, // G_MEMCPY_INLINE
5468
1.14M
    0U, // G_MEMMOVE
5469
1.14M
    0U, // G_MEMSET
5470
1.14M
    0U, // G_BZERO
5471
1.14M
    0U, // G_VECREDUCE_SEQ_FADD
5472
1.14M
    0U, // G_VECREDUCE_SEQ_FMUL
5473
1.14M
    0U, // G_VECREDUCE_FADD
5474
1.14M
    0U, // G_VECREDUCE_FMUL
5475
1.14M
    0U, // G_VECREDUCE_FMAX
5476
1.14M
    0U, // G_VECREDUCE_FMIN
5477
1.14M
    0U, // G_VECREDUCE_FMAXIMUM
5478
1.14M
    0U, // G_VECREDUCE_FMINIMUM
5479
1.14M
    0U, // G_VECREDUCE_ADD
5480
1.14M
    0U, // G_VECREDUCE_MUL
5481
1.14M
    0U, // G_VECREDUCE_AND
5482
1.14M
    0U, // G_VECREDUCE_OR
5483
1.14M
    0U, // G_VECREDUCE_XOR
5484
1.14M
    0U, // G_VECREDUCE_SMAX
5485
1.14M
    0U, // G_VECREDUCE_SMIN
5486
1.14M
    0U, // G_VECREDUCE_UMAX
5487
1.14M
    0U, // G_VECREDUCE_UMIN
5488
1.14M
    0U, // G_SBFX
5489
1.14M
    0U, // G_UBFX
5490
1.14M
    0U, // ABS
5491
1.14M
    0U, // ADDSri
5492
1.14M
    0U, // ADDSrr
5493
1.14M
    0U, // ADDSrsi
5494
1.14M
    0U, // ADDSrsr
5495
1.14M
    0U, // ADJCALLSTACKDOWN
5496
1.14M
    0U, // ADJCALLSTACKUP
5497
1.14M
    0U, // ASRi
5498
1.14M
    0U, // ASRr
5499
1.14M
    0U, // B
5500
1.14M
    0U, // BCCZi64
5501
1.14M
    0U, // BCCi64
5502
1.14M
    0U, // BLX_noip
5503
1.14M
    0U, // BLX_pred_noip
5504
1.14M
    0U, // BL_PUSHLR
5505
1.14M
    0U, // BMOVPCB_CALL
5506
1.14M
    0U, // BMOVPCRX_CALL
5507
1.14M
    0U, // BR_JTadd
5508
1.14M
    0U, // BR_JTm_i12
5509
1.14M
    0U, // BR_JTm_rs
5510
1.14M
    0U, // BR_JTr
5511
1.14M
    0U, // BX_CALL
5512
1.14M
    0U, // CMP_SWAP_16
5513
1.14M
    0U, // CMP_SWAP_32
5514
1.14M
    0U, // CMP_SWAP_64
5515
1.14M
    0U, // CMP_SWAP_8
5516
1.14M
    0U, // CONSTPOOL_ENTRY
5517
1.14M
    0U, // COPY_STRUCT_BYVAL_I32
5518
1.14M
    0U, // ITasm
5519
1.14M
    0U, // Int_eh_sjlj_dispatchsetup
5520
1.14M
    0U, // Int_eh_sjlj_longjmp
5521
1.14M
    0U, // Int_eh_sjlj_setjmp
5522
1.14M
    0U, // Int_eh_sjlj_setjmp_nofp
5523
1.14M
    0U, // Int_eh_sjlj_setup_dispatch
5524
1.14M
    0U, // JUMPTABLE_ADDRS
5525
1.14M
    0U, // JUMPTABLE_INSTS
5526
1.14M
    0U, // JUMPTABLE_TBB
5527
1.14M
    0U, // JUMPTABLE_TBH
5528
1.14M
    0U, // LDMIA_RET
5529
1.14M
    128U, // LDRBT_POST
5530
1.14M
    16384U, // LDRConstPool
5531
1.14M
    128U, // LDRHTii
5532
1.14M
    0U, // LDRLIT_ga_abs
5533
1.14M
    0U, // LDRLIT_ga_pcrel
5534
1.14M
    0U, // LDRLIT_ga_pcrel_ldr
5535
1.14M
    128U, // LDRSBTii
5536
1.14M
    128U, // LDRSHTii
5537
1.14M
    128U, // LDRT_POST
5538
1.14M
    0U, // LEApcrel
5539
1.14M
    0U, // LEApcrelJT
5540
1.14M
    0U, // LOADDUAL
5541
1.14M
    0U, // LSLi
5542
1.14M
    0U, // LSLr
5543
1.14M
    0U, // LSRi
5544
1.14M
    0U, // LSRr
5545
1.14M
    0U, // MEMCPY
5546
1.14M
    0U, // MLAv5
5547
1.14M
    0U, // MOVCCi
5548
1.14M
    0U, // MOVCCi16
5549
1.14M
    0U, // MOVCCi32imm
5550
1.14M
    0U, // MOVCCr
5551
1.14M
    0U, // MOVCCsi
5552
1.14M
    0U, // MOVCCsr
5553
1.14M
    0U, // MOVPCRX
5554
1.14M
    0U, // MOVTi16_ga_pcrel
5555
1.14M
    0U, // MOV_ga_pcrel
5556
1.14M
    0U, // MOV_ga_pcrel_ldr
5557
1.14M
    0U, // MOVi16_ga_pcrel
5558
1.14M
    0U, // MOVi32imm
5559
1.14M
    0U, // MOVsra_glue
5560
1.14M
    0U, // MOVsrl_glue
5561
1.14M
    0U, // MQPRCopy
5562
1.14M
    0U, // MQQPRLoad
5563
1.14M
    0U, // MQQPRStore
5564
1.14M
    0U, // MQQQQPRLoad
5565
1.14M
    0U, // MQQQQPRStore
5566
1.14M
    0U, // MULv5
5567
1.14M
    0U, // MVE_MEMCPYLOOPINST
5568
1.14M
    0U, // MVE_MEMSETLOOPINST
5569
1.14M
    0U, // MVNCCi
5570
1.14M
    0U, // PICADD
5571
1.14M
    0U, // PICLDR
5572
1.14M
    0U, // PICLDRB
5573
1.14M
    0U, // PICLDRH
5574
1.14M
    0U, // PICLDRSB
5575
1.14M
    0U, // PICLDRSH
5576
1.14M
    0U, // PICSTR
5577
1.14M
    0U, // PICSTRB
5578
1.14M
    0U, // PICSTRH
5579
1.14M
    0U, // RORi
5580
1.14M
    0U, // RORr
5581
1.14M
    0U, // RRX
5582
1.14M
    16384U, // RRXi
5583
1.14M
    0U, // RSBSri
5584
1.14M
    0U, // RSBSrsi
5585
1.14M
    0U, // RSBSrsr
5586
1.14M
    0U, // SEH_EpilogEnd
5587
1.14M
    0U, // SEH_EpilogStart
5588
1.14M
    0U, // SEH_Nop
5589
1.14M
    0U, // SEH_Nop_Ret
5590
1.14M
    0U, // SEH_PrologEnd
5591
1.14M
    0U, // SEH_SaveFRegs
5592
1.14M
    0U, // SEH_SaveLR
5593
1.14M
    0U, // SEH_SaveRegs
5594
1.14M
    0U, // SEH_SaveRegs_Ret
5595
1.14M
    0U, // SEH_SaveSP
5596
1.14M
    0U, // SEH_StackAlloc
5597
1.14M
    0U, // SMLALv5
5598
1.14M
    0U, // SMULLv5
5599
1.14M
    0U, // SPACE
5600
1.14M
    0U, // STOREDUAL
5601
1.14M
    128U, // STRBT_POST
5602
1.14M
    0U, // STRBi_preidx
5603
1.14M
    0U, // STRBr_preidx
5604
1.14M
    0U, // STRH_preidx
5605
1.14M
    128U, // STRT_POST
5606
1.14M
    0U, // STRi_preidx
5607
1.14M
    0U, // STRr_preidx
5608
1.14M
    0U, // SUBS_PC_LR
5609
1.14M
    0U, // SUBSri
5610
1.14M
    0U, // SUBSrr
5611
1.14M
    0U, // SUBSrsi
5612
1.14M
    0U, // SUBSrsr
5613
1.14M
    0U, // SpeculationBarrierISBDSBEndBB
5614
1.14M
    0U, // SpeculationBarrierSBEndBB
5615
1.14M
    0U, // TAILJMPd
5616
1.14M
    0U, // TAILJMPr
5617
1.14M
    0U, // TAILJMPr4
5618
1.14M
    0U, // TCRETURNdi
5619
1.14M
    0U, // TCRETURNri
5620
1.14M
    0U, // TPsoft
5621
1.14M
    0U, // UMLALv5
5622
1.14M
    0U, // UMULLv5
5623
1.14M
    16640U, // VLD1LNdAsm_16
5624
1.14M
    16640U, // VLD1LNdAsm_32
5625
1.14M
    16640U, // VLD1LNdAsm_8
5626
1.14M
    33024U, // VLD1LNdWB_fixed_Asm_16
5627
1.14M
    33024U, // VLD1LNdWB_fixed_Asm_32
5628
1.14M
    33024U, // VLD1LNdWB_fixed_Asm_8
5629
1.14M
    524544U,  // VLD1LNdWB_register_Asm_16
5630
1.14M
    524544U,  // VLD1LNdWB_register_Asm_32
5631
1.14M
    524544U,  // VLD1LNdWB_register_Asm_8
5632
1.14M
    16640U, // VLD2LNdAsm_16
5633
1.14M
    16640U, // VLD2LNdAsm_32
5634
1.14M
    16640U, // VLD2LNdAsm_8
5635
1.14M
    33024U, // VLD2LNdWB_fixed_Asm_16
5636
1.14M
    33024U, // VLD2LNdWB_fixed_Asm_32
5637
1.14M
    33024U, // VLD2LNdWB_fixed_Asm_8
5638
1.14M
    524544U,  // VLD2LNdWB_register_Asm_16
5639
1.14M
    524544U,  // VLD2LNdWB_register_Asm_32
5640
1.14M
    524544U,  // VLD2LNdWB_register_Asm_8
5641
1.14M
    16640U, // VLD2LNqAsm_16
5642
1.14M
    16640U, // VLD2LNqAsm_32
5643
1.14M
    33024U, // VLD2LNqWB_fixed_Asm_16
5644
1.14M
    33024U, // VLD2LNqWB_fixed_Asm_32
5645
1.14M
    524544U,  // VLD2LNqWB_register_Asm_16
5646
1.14M
    524544U,  // VLD2LNqWB_register_Asm_32
5647
1.14M
    2U, // VLD3DUPdAsm_16
5648
1.14M
    2U, // VLD3DUPdAsm_32
5649
1.14M
    2U, // VLD3DUPdAsm_8
5650
1.14M
    4U, // VLD3DUPdWB_fixed_Asm_16
5651
1.14M
    4U, // VLD3DUPdWB_fixed_Asm_32
5652
1.14M
    4U, // VLD3DUPdWB_fixed_Asm_8
5653
1.14M
    16768U, // VLD3DUPdWB_register_Asm_16
5654
1.14M
    16768U, // VLD3DUPdWB_register_Asm_32
5655
1.14M
    16768U, // VLD3DUPdWB_register_Asm_8
5656
1.14M
    2U, // VLD3DUPqAsm_16
5657
1.14M
    2U, // VLD3DUPqAsm_32
5658
1.14M
    2U, // VLD3DUPqAsm_8
5659
1.14M
    4U, // VLD3DUPqWB_fixed_Asm_16
5660
1.14M
    4U, // VLD3DUPqWB_fixed_Asm_32
5661
1.14M
    4U, // VLD3DUPqWB_fixed_Asm_8
5662
1.14M
    16768U, // VLD3DUPqWB_register_Asm_16
5663
1.14M
    16768U, // VLD3DUPqWB_register_Asm_32
5664
1.14M
    16768U, // VLD3DUPqWB_register_Asm_8
5665
1.14M
    16640U, // VLD3LNdAsm_16
5666
1.14M
    16640U, // VLD3LNdAsm_32
5667
1.14M
    16640U, // VLD3LNdAsm_8
5668
1.14M
    33024U, // VLD3LNdWB_fixed_Asm_16
5669
1.14M
    33024U, // VLD3LNdWB_fixed_Asm_32
5670
1.14M
    33024U, // VLD3LNdWB_fixed_Asm_8
5671
1.14M
    524544U,  // VLD3LNdWB_register_Asm_16
5672
1.14M
    524544U,  // VLD3LNdWB_register_Asm_32
5673
1.14M
    524544U,  // VLD3LNdWB_register_Asm_8
5674
1.14M
    16640U, // VLD3LNqAsm_16
5675
1.14M
    16640U, // VLD3LNqAsm_32
5676
1.14M
    33024U, // VLD3LNqWB_fixed_Asm_16
5677
1.14M
    33024U, // VLD3LNqWB_fixed_Asm_32
5678
1.14M
    524544U,  // VLD3LNqWB_register_Asm_16
5679
1.14M
    524544U,  // VLD3LNqWB_register_Asm_32
5680
1.14M
    518U, // VLD3dAsm_16
5681
1.14M
    518U, // VLD3dAsm_32
5682
1.14M
    518U, // VLD3dAsm_8
5683
1.14M
    646U, // VLD3dWB_fixed_Asm_16
5684
1.14M
    646U, // VLD3dWB_fixed_Asm_32
5685
1.14M
    646U, // VLD3dWB_fixed_Asm_8
5686
1.14M
    49926U, // VLD3dWB_register_Asm_16
5687
1.14M
    49926U, // VLD3dWB_register_Asm_32
5688
1.14M
    49926U, // VLD3dWB_register_Asm_8
5689
1.14M
    2U, // VLD3qAsm_16
5690
1.14M
    2U, // VLD3qAsm_32
5691
1.14M
    2U, // VLD3qAsm_8
5692
1.14M
    4U, // VLD3qWB_fixed_Asm_16
5693
1.14M
    4U, // VLD3qWB_fixed_Asm_32
5694
1.14M
    4U, // VLD3qWB_fixed_Asm_8
5695
1.14M
    16768U, // VLD3qWB_register_Asm_16
5696
1.14M
    16768U, // VLD3qWB_register_Asm_32
5697
1.14M
    16768U, // VLD3qWB_register_Asm_8
5698
1.14M
    2U, // VLD4DUPdAsm_16
5699
1.14M
    2U, // VLD4DUPdAsm_32
5700
1.14M
    2U, // VLD4DUPdAsm_8
5701
1.14M
    4U, // VLD4DUPdWB_fixed_Asm_16
5702
1.14M
    4U, // VLD4DUPdWB_fixed_Asm_32
5703
1.14M
    4U, // VLD4DUPdWB_fixed_Asm_8
5704
1.14M
    16768U, // VLD4DUPdWB_register_Asm_16
5705
1.14M
    16768U, // VLD4DUPdWB_register_Asm_32
5706
1.14M
    16768U, // VLD4DUPdWB_register_Asm_8
5707
1.14M
    2U, // VLD4DUPqAsm_16
5708
1.14M
    2U, // VLD4DUPqAsm_32
5709
1.14M
    2U, // VLD4DUPqAsm_8
5710
1.14M
    4U, // VLD4DUPqWB_fixed_Asm_16
5711
1.14M
    4U, // VLD4DUPqWB_fixed_Asm_32
5712
1.14M
    4U, // VLD4DUPqWB_fixed_Asm_8
5713
1.14M
    16768U, // VLD4DUPqWB_register_Asm_16
5714
1.14M
    16768U, // VLD4DUPqWB_register_Asm_32
5715
1.14M
    16768U, // VLD4DUPqWB_register_Asm_8
5716
1.14M
    16640U, // VLD4LNdAsm_16
5717
1.14M
    16640U, // VLD4LNdAsm_32
5718
1.14M
    16640U, // VLD4LNdAsm_8
5719
1.14M
    33024U, // VLD4LNdWB_fixed_Asm_16
5720
1.14M
    33024U, // VLD4LNdWB_fixed_Asm_32
5721
1.14M
    33024U, // VLD4LNdWB_fixed_Asm_8
5722
1.14M
    524544U,  // VLD4LNdWB_register_Asm_16
5723
1.14M
    524544U,  // VLD4LNdWB_register_Asm_32
5724
1.14M
    524544U,  // VLD4LNdWB_register_Asm_8
5725
1.14M
    16640U, // VLD4LNqAsm_16
5726
1.14M
    16640U, // VLD4LNqAsm_32
5727
1.14M
    33024U, // VLD4LNqWB_fixed_Asm_16
5728
1.14M
    33024U, // VLD4LNqWB_fixed_Asm_32
5729
1.14M
    524544U,  // VLD4LNqWB_register_Asm_16
5730
1.14M
    524544U,  // VLD4LNqWB_register_Asm_32
5731
1.14M
    518U, // VLD4dAsm_16
5732
1.14M
    518U, // VLD4dAsm_32
5733
1.14M
    518U, // VLD4dAsm_8
5734
1.14M
    646U, // VLD4dWB_fixed_Asm_16
5735
1.14M
    646U, // VLD4dWB_fixed_Asm_32
5736
1.14M
    646U, // VLD4dWB_fixed_Asm_8
5737
1.14M
    49926U, // VLD4dWB_register_Asm_16
5738
1.14M
    49926U, // VLD4dWB_register_Asm_32
5739
1.14M
    49926U, // VLD4dWB_register_Asm_8
5740
1.14M
    2U, // VLD4qAsm_16
5741
1.14M
    2U, // VLD4qAsm_32
5742
1.14M
    2U, // VLD4qAsm_8
5743
1.14M
    4U, // VLD4qWB_fixed_Asm_16
5744
1.14M
    4U, // VLD4qWB_fixed_Asm_32
5745
1.14M
    4U, // VLD4qWB_fixed_Asm_8
5746
1.14M
    16768U, // VLD4qWB_register_Asm_16
5747
1.14M
    16768U, // VLD4qWB_register_Asm_32
5748
1.14M
    16768U, // VLD4qWB_register_Asm_8
5749
1.14M
    0U, // VMOVD0
5750
1.14M
    0U, // VMOVDcc
5751
1.14M
    0U, // VMOVHcc
5752
1.14M
    0U, // VMOVQ0
5753
1.14M
    0U, // VMOVScc
5754
1.14M
    16640U, // VST1LNdAsm_16
5755
1.14M
    16640U, // VST1LNdAsm_32
5756
1.14M
    16640U, // VST1LNdAsm_8
5757
1.14M
    33024U, // VST1LNdWB_fixed_Asm_16
5758
1.14M
    33024U, // VST1LNdWB_fixed_Asm_32
5759
1.14M
    33024U, // VST1LNdWB_fixed_Asm_8
5760
1.14M
    524544U,  // VST1LNdWB_register_Asm_16
5761
1.14M
    524544U,  // VST1LNdWB_register_Asm_32
5762
1.14M
    524544U,  // VST1LNdWB_register_Asm_8
5763
1.14M
    16640U, // VST2LNdAsm_16
5764
1.14M
    16640U, // VST2LNdAsm_32
5765
1.14M
    16640U, // VST2LNdAsm_8
5766
1.14M
    33024U, // VST2LNdWB_fixed_Asm_16
5767
1.14M
    33024U, // VST2LNdWB_fixed_Asm_32
5768
1.14M
    33024U, // VST2LNdWB_fixed_Asm_8
5769
1.14M
    524544U,  // VST2LNdWB_register_Asm_16
5770
1.14M
    524544U,  // VST2LNdWB_register_Asm_32
5771
1.14M
    524544U,  // VST2LNdWB_register_Asm_8
5772
1.14M
    16640U, // VST2LNqAsm_16
5773
1.14M
    16640U, // VST2LNqAsm_32
5774
1.14M
    33024U, // VST2LNqWB_fixed_Asm_16
5775
1.14M
    33024U, // VST2LNqWB_fixed_Asm_32
5776
1.14M
    524544U,  // VST2LNqWB_register_Asm_16
5777
1.14M
    524544U,  // VST2LNqWB_register_Asm_32
5778
1.14M
    16640U, // VST3LNdAsm_16
5779
1.14M
    16640U, // VST3LNdAsm_32
5780
1.14M
    16640U, // VST3LNdAsm_8
5781
1.14M
    33024U, // VST3LNdWB_fixed_Asm_16
5782
1.14M
    33024U, // VST3LNdWB_fixed_Asm_32
5783
1.14M
    33024U, // VST3LNdWB_fixed_Asm_8
5784
1.14M
    524544U,  // VST3LNdWB_register_Asm_16
5785
1.14M
    524544U,  // VST3LNdWB_register_Asm_32
5786
1.14M
    524544U,  // VST3LNdWB_register_Asm_8
5787
1.14M
    16640U, // VST3LNqAsm_16
5788
1.14M
    16640U, // VST3LNqAsm_32
5789
1.14M
    33024U, // VST3LNqWB_fixed_Asm_16
5790
1.14M
    33024U, // VST3LNqWB_fixed_Asm_32
5791
1.14M
    524544U,  // VST3LNqWB_register_Asm_16
5792
1.14M
    524544U,  // VST3LNqWB_register_Asm_32
5793
1.14M
    518U, // VST3dAsm_16
5794
1.14M
    518U, // VST3dAsm_32
5795
1.14M
    518U, // VST3dAsm_8
5796
1.14M
    646U, // VST3dWB_fixed_Asm_16
5797
1.14M
    646U, // VST3dWB_fixed_Asm_32
5798
1.14M
    646U, // VST3dWB_fixed_Asm_8
5799
1.14M
    49926U, // VST3dWB_register_Asm_16
5800
1.14M
    49926U, // VST3dWB_register_Asm_32
5801
1.14M
    49926U, // VST3dWB_register_Asm_8
5802
1.14M
    2U, // VST3qAsm_16
5803
1.14M
    2U, // VST3qAsm_32
5804
1.14M
    2U, // VST3qAsm_8
5805
1.14M
    4U, // VST3qWB_fixed_Asm_16
5806
1.14M
    4U, // VST3qWB_fixed_Asm_32
5807
1.14M
    4U, // VST3qWB_fixed_Asm_8
5808
1.14M
    16768U, // VST3qWB_register_Asm_16
5809
1.14M
    16768U, // VST3qWB_register_Asm_32
5810
1.14M
    16768U, // VST3qWB_register_Asm_8
5811
1.14M
    16640U, // VST4LNdAsm_16
5812
1.14M
    16640U, // VST4LNdAsm_32
5813
1.14M
    16640U, // VST4LNdAsm_8
5814
1.14M
    33024U, // VST4LNdWB_fixed_Asm_16
5815
1.14M
    33024U, // VST4LNdWB_fixed_Asm_32
5816
1.14M
    33024U, // VST4LNdWB_fixed_Asm_8
5817
1.14M
    524544U,  // VST4LNdWB_register_Asm_16
5818
1.14M
    524544U,  // VST4LNdWB_register_Asm_32
5819
1.14M
    524544U,  // VST4LNdWB_register_Asm_8
5820
1.14M
    16640U, // VST4LNqAsm_16
5821
1.14M
    16640U, // VST4LNqAsm_32
5822
1.14M
    33024U, // VST4LNqWB_fixed_Asm_16
5823
1.14M
    33024U, // VST4LNqWB_fixed_Asm_32
5824
1.14M
    524544U,  // VST4LNqWB_register_Asm_16
5825
1.14M
    524544U,  // VST4LNqWB_register_Asm_32
5826
1.14M
    518U, // VST4dAsm_16
5827
1.14M
    518U, // VST4dAsm_32
5828
1.14M
    518U, // VST4dAsm_8
5829
1.14M
    646U, // VST4dWB_fixed_Asm_16
5830
1.14M
    646U, // VST4dWB_fixed_Asm_32
5831
1.14M
    646U, // VST4dWB_fixed_Asm_8
5832
1.14M
    49926U, // VST4dWB_register_Asm_16
5833
1.14M
    49926U, // VST4dWB_register_Asm_32
5834
1.14M
    49926U, // VST4dWB_register_Asm_8
5835
1.14M
    2U, // VST4qAsm_16
5836
1.14M
    2U, // VST4qAsm_32
5837
1.14M
    2U, // VST4qAsm_8
5838
1.14M
    4U, // VST4qWB_fixed_Asm_16
5839
1.14M
    4U, // VST4qWB_fixed_Asm_32
5840
1.14M
    4U, // VST4qWB_fixed_Asm_8
5841
1.14M
    16768U, // VST4qWB_register_Asm_16
5842
1.14M
    16768U, // VST4qWB_register_Asm_32
5843
1.14M
    16768U, // VST4qWB_register_Asm_8
5844
1.14M
    0U, // WIN__CHKSTK
5845
1.14M
    0U, // WIN__DBZCHK
5846
1.14M
    0U, // t2ABS
5847
1.14M
    0U, // t2ADDSri
5848
1.14M
    0U, // t2ADDSrr
5849
1.14M
    0U, // t2ADDSrs
5850
1.14M
    0U, // t2BF_LabelPseudo
5851
1.14M
    0U, // t2BR_JT
5852
1.14M
    0U, // t2CALL_BTI
5853
1.14M
    0U, // t2DoLoopStart
5854
1.14M
    0U, // t2DoLoopStartTP
5855
1.14M
    0U, // t2LDMIA_RET
5856
1.14M
    0U, // t2LDRB_OFFSET_imm
5857
1.14M
    896U, // t2LDRB_POST_imm
5858
1.14M
    0U, // t2LDRB_PRE_imm
5859
1.14M
    16384U, // t2LDRBpcrel
5860
1.14M
    16384U, // t2LDRConstPool
5861
1.14M
    0U, // t2LDRH_OFFSET_imm
5862
1.14M
    896U, // t2LDRH_POST_imm
5863
1.14M
    0U, // t2LDRH_PRE_imm
5864
1.14M
    16384U, // t2LDRHpcrel
5865
1.14M
    0U, // t2LDRLIT_ga_pcrel
5866
1.14M
    0U, // t2LDRSB_OFFSET_imm
5867
1.14M
    896U, // t2LDRSB_POST_imm
5868
1.14M
    0U, // t2LDRSB_PRE_imm
5869
1.14M
    16384U, // t2LDRSBpcrel
5870
1.14M
    0U, // t2LDRSH_OFFSET_imm
5871
1.14M
    896U, // t2LDRSH_POST_imm
5872
1.14M
    0U, // t2LDRSH_PRE_imm
5873
1.14M
    16384U, // t2LDRSHpcrel
5874
1.14M
    896U, // t2LDR_POST_imm
5875
1.14M
    0U, // t2LDR_PRE_imm
5876
1.14M
    0U, // t2LDRpci_pic
5877
1.14M
    16384U, // t2LDRpcrel
5878
1.14M
    0U, // t2LEApcrel
5879
1.14M
    0U, // t2LEApcrelJT
5880
1.14M
    0U, // t2LoopDec
5881
1.14M
    0U, // t2LoopEnd
5882
1.14M
    0U, // t2LoopEndDec
5883
1.14M
    0U, // t2MOVCCasr
5884
1.14M
    0U, // t2MOVCCi
5885
1.14M
    0U, // t2MOVCCi16
5886
1.14M
    0U, // t2MOVCCi32imm
5887
1.14M
    0U, // t2MOVCClsl
5888
1.14M
    0U, // t2MOVCClsr
5889
1.14M
    0U, // t2MOVCCr
5890
1.14M
    0U, // t2MOVCCror
5891
1.14M
    1024U,  // t2MOVSsi
5892
1.14M
    1152U,  // t2MOVSsr
5893
1.14M
    0U, // t2MOVTi16_ga_pcrel
5894
1.14M
    0U, // t2MOV_ga_pcrel
5895
1.14M
    0U, // t2MOVi16_ga_pcrel
5896
1.14M
    0U, // t2MOVi32imm
5897
1.14M
    1024U,  // t2MOVsi
5898
1.14M
    1152U,  // t2MOVsr
5899
1.14M
    0U, // t2MVNCCi
5900
1.14M
    0U, // t2RSBSri
5901
1.14M
    0U, // t2RSBSrs
5902
1.14M
    0U, // t2STRB_OFFSET_imm
5903
1.14M
    896U, // t2STRB_POST_imm
5904
1.14M
    0U, // t2STRB_PRE_imm
5905
1.14M
    0U, // t2STRB_preidx
5906
1.14M
    0U, // t2STRH_OFFSET_imm
5907
1.14M
    896U, // t2STRH_POST_imm
5908
1.14M
    0U, // t2STRH_PRE_imm
5909
1.14M
    0U, // t2STRH_preidx
5910
1.14M
    896U, // t2STR_POST_imm
5911
1.14M
    0U, // t2STR_PRE_imm
5912
1.14M
    0U, // t2STR_preidx
5913
1.14M
    0U, // t2SUBSri
5914
1.14M
    0U, // t2SUBSrr
5915
1.14M
    0U, // t2SUBSrs
5916
1.14M
    0U, // t2SpeculationBarrierISBDSBEndBB
5917
1.14M
    0U, // t2SpeculationBarrierSBEndBB
5918
1.14M
    0U, // t2TBB_JT
5919
1.14M
    0U, // t2TBH_JT
5920
1.14M
    0U, // t2WhileLoopSetup
5921
1.14M
    0U, // t2WhileLoopStart
5922
1.14M
    0U, // t2WhileLoopStartLR
5923
1.14M
    0U, // t2WhileLoopStartTP
5924
1.14M
    0U, // tADCS
5925
1.14M
    0U, // tADDSi3
5926
1.14M
    0U, // tADDSi8
5927
1.14M
    0U, // tADDSrr
5928
1.14M
    0U, // tADDframe
5929
1.14M
    0U, // tADJCALLSTACKDOWN
5930
1.14M
    0U, // tADJCALLSTACKUP
5931
1.14M
    0U, // tBLXNS_CALL
5932
1.14M
    0U, // tBLXr_noip
5933
1.14M
    0U, // tBL_PUSHLR
5934
1.14M
    0U, // tBRIND
5935
1.14M
    0U, // tBR_JTr
5936
1.14M
    0U, // tBXNS_RET
5937
1.14M
    0U, // tBX_CALL
5938
1.14M
    0U, // tBX_RET
5939
1.14M
    0U, // tBX_RET_vararg
5940
1.14M
    0U, // tBfar
5941
1.14M
    0U, // tCMP_SWAP_16
5942
1.14M
    0U, // tCMP_SWAP_32
5943
1.14M
    0U, // tCMP_SWAP_8
5944
1.14M
    0U, // tLDMIA_UPD
5945
1.14M
    16384U, // tLDRConstPool
5946
1.14M
    0U, // tLDRLIT_ga_abs
5947
1.14M
    0U, // tLDRLIT_ga_pcrel
5948
1.14M
    0U, // tLDR_postidx
5949
1.14M
    0U, // tLDRpci_pic
5950
1.14M
    0U, // tLEApcrel
5951
1.14M
    0U, // tLEApcrelJT
5952
1.14M
    0U, // tLSLSri
5953
1.14M
    0U, // tMOVCCr_pseudo
5954
1.14M
    0U, // tMOVi32imm
5955
1.14M
    0U, // tPOP_RET
5956
1.14M
    0U, // tRSBS
5957
1.14M
    0U, // tSBCS
5958
1.14M
    0U, // tSUBSi3
5959
1.14M
    0U, // tSUBSi8
5960
1.14M
    0U, // tSUBSrr
5961
1.14M
    0U, // tTAILJMPd
5962
1.14M
    0U, // tTAILJMPdND
5963
1.14M
    0U, // tTAILJMPr
5964
1.14M
    0U, // tTBB_JT
5965
1.14M
    0U, // tTBH_JT
5966
1.14M
    0U, // tTPsoft
5967
1.14M
    1048576U, // ADCri
5968
1.14M
    0U, // ADCrr
5969
1.14M
    1572864U, // ADCrsi
5970
1.14M
    0U, // ADCrsr
5971
1.14M
    1048576U, // ADDri
5972
1.14M
    0U, // ADDrr
5973
1.14M
    1572864U, // ADDrsi
5974
1.14M
    0U, // ADDrsr
5975
1.14M
    1280U,  // ADR
5976
1.14M
    2U, // AESD
5977
1.14M
    2U, // AESE
5978
1.14M
    2U, // AESIMC
5979
1.14M
    2U, // AESMC
5980
1.14M
    1048576U, // ANDri
5981
1.14M
    0U, // ANDrr
5982
1.14M
    1572864U, // ANDrsi
5983
1.14M
    0U, // ANDrsr
5984
1.14M
    520U, // BF16VDOTI_VDOTD
5985
1.14M
    520U, // BF16VDOTI_VDOTQ
5986
1.14M
    2U, // BF16VDOTS_VDOTD
5987
1.14M
    2U, // BF16VDOTS_VDOTQ
5988
1.14M
    2U, // BF16_VCVT
5989
1.14M
    2U, // BF16_VCVTB
5990
1.14M
    2U, // BF16_VCVTT
5991
1.14M
    1408U,  // BFC
5992
1.14M
    2098688U, // BFI
5993
1.14M
    1048576U, // BICri
5994
1.14M
    0U, // BICrr
5995
1.14M
    1572864U, // BICrsi
5996
1.14M
    0U, // BICrsr
5997
1.14M
    0U, // BKPT
5998
1.14M
    0U, // BL
5999
1.14M
    0U, // BLX
6000
1.14M
    2U, // BLX_pred
6001
1.14M
    0U, // BLXi
6002
1.14M
    2U, // BL_pred
6003
1.14M
    0U, // BX
6004
1.14M
    2U, // BXJ
6005
1.14M
    0U, // BX_RET
6006
1.14M
    2U, // BX_pred
6007
1.14M
    2U, // Bcc
6008
1.14M
    2U, // CDE_CX1
6009
1.14M
    16778U, // CDE_CX1A
6010
1.14M
    0U, // CDE_CX1D
6011
1.14M
    524U, // CDE_CX1DA
6012
1.14M
    16768U, // CDE_CX2
6013
1.14M
    524682U,  // CDE_CX2A
6014
1.14M
    526U, // CDE_CX2D
6015
1.14M
    2687756U, // CDE_CX2DA
6016
1.14M
    524672U,  // CDE_CX3
6017
1.14M
    34079114U,  // CDE_CX3A
6018
1.14M
    2687758U, // CDE_CX3D
6019
1.14M
    70320908U,  // CDE_CX3DA
6020
1.14M
    2U, // CDE_VCX1A_fpdp
6021
1.14M
    2U, // CDE_VCX1A_fpsp
6022
1.14M
    16778U, // CDE_VCX1A_vec
6023
1.14M
    2U, // CDE_VCX1_fpdp
6024
1.14M
    2U, // CDE_VCX1_fpsp
6025
1.14M
    17930U, // CDE_VCX1_vec
6026
1.14M
    18048U, // CDE_VCX2A_fpdp
6027
1.14M
    18048U, // CDE_VCX2A_fpsp
6028
1.14M
    524682U,  // CDE_VCX2A_vec
6029
1.14M
    16768U, // CDE_VCX2_fpdp
6030
1.14M
    16768U, // CDE_VCX2_fpsp
6031
1.14M
    3671562U, // CDE_VCX2_vec
6032
1.14M
    4195968U, // CDE_VCX3A_fpdp
6033
1.14M
    4195968U, // CDE_VCX3A_fpsp
6034
1.14M
    34079114U,  // CDE_VCX3A_vec
6035
1.14M
    524672U,  // CDE_VCX3_fpdp
6036
1.14M
    524672U,  // CDE_VCX3_fpsp
6037
1.14M
    37225994U,  // CDE_VCX3_vec
6038
1.14M
    82704U, // CDP
6039
1.14M
    0U, // CDP2
6040
1.14M
    0U, // CLREX
6041
1.14M
    16384U, // CLZ
6042
1.14M
    1792U,  // CMNri
6043
1.14M
    16384U, // CMNzrr
6044
1.14M
    1920U,  // CMNzrsi
6045
1.14M
    1152U,  // CMNzrsr
6046
1.14M
    1792U,  // CMPri
6047
1.14M
    16384U, // CMPrr
6048
1.14M
    1920U,  // CMPrsi
6049
1.14M
    1152U,  // CMPrsr
6050
1.14M
    0U, // CPS1p
6051
1.14M
    2U, // CPS2p
6052
1.14M
    17920U, // CPS3p
6053
1.14M
    17920U, // CRC32B
6054
1.14M
    17920U, // CRC32CB
6055
1.14M
    17920U, // CRC32CH
6056
1.14M
    17920U, // CRC32CW
6057
1.14M
    17920U, // CRC32H
6058
1.14M
    17920U, // CRC32W
6059
1.14M
    2U, // DBG
6060
1.14M
    0U, // DMB
6061
1.14M
    0U, // DSB
6062
1.14M
    1048576U, // EORri
6063
1.14M
    0U, // EORrr
6064
1.14M
    1572864U, // EORrsi
6065
1.14M
    0U, // EORrsr
6066
1.14M
    0U, // ERET
6067
1.14M
    18U,  // FCONSTD
6068
1.14M
    2048U,  // FCONSTH
6069
1.14M
    2048U,  // FCONSTS
6070
1.14M
    532U, // FLDMXDB_UPD
6071
1.14M
    18560U, // FLDMXIA
6072
1.14M
    532U, // FLDMXIA_UPD
6073
1.14M
    0U, // FMSTAT
6074
1.14M
    532U, // FSTMXDB_UPD
6075
1.14M
    18560U, // FSTMXIA
6076
1.14M
    532U, // FSTMXIA_UPD
6077
1.14M
    2U, // HINT
6078
1.14M
    0U, // HLT
6079
1.14M
    0U, // HVC
6080
1.14M
    0U, // ISB
6081
1.14M
    128U, // LDA
6082
1.14M
    128U, // LDAB
6083
1.14M
    128U, // LDAEX
6084
1.14M
    128U, // LDAEXB
6085
1.14M
    0U, // LDAEXD
6086
1.14M
    128U, // LDAEXH
6087
1.14M
    128U, // LDAH
6088
1.14M
    0U, // LDC2L_OFFSET
6089
1.14M
    2304U,  // LDC2L_OPTION
6090
1.14M
    2432U,  // LDC2L_POST
6091
1.14M
    0U, // LDC2L_PRE
6092
1.14M
    0U, // LDC2_OFFSET
6093
1.14M
    2304U,  // LDC2_OPTION
6094
1.14M
    2432U,  // LDC2_POST
6095
1.14M
    0U, // LDC2_PRE
6096
1.14M
    2582U,  // LDCL_OFFSET
6097
1.14M
    4721302U, // LDCL_OPTION
6098
1.14M
    5245590U, // LDCL_POST
6099
1.14M
    2838U,  // LDCL_PRE
6100
1.14M
    2582U,  // LDC_OFFSET
6101
1.14M
    4721302U, // LDC_OPTION
6102
1.14M
    5245590U, // LDC_POST
6103
1.14M
    2838U,  // LDC_PRE
6104
1.14M
    18560U, // LDMDA
6105
1.14M
    532U, // LDMDA_UPD
6106
1.14M
    18560U, // LDMDB
6107
1.14M
    532U, // LDMDB_UPD
6108
1.14M
    18560U, // LDMIA
6109
1.14M
    532U, // LDMIA_UPD
6110
1.14M
    18560U, // LDMIB
6111
1.14M
    532U, // LDMIB_UPD
6112
1.14M
    5769856U, // LDRBT_POST_IMM
6113
1.14M
    5769856U, // LDRBT_POST_REG
6114
1.14M
    5769856U, // LDRB_POST_IMM
6115
1.14M
    5769856U, // LDRB_POST_REG
6116
1.14M
    2944U,  // LDRB_PRE_IMM
6117
1.14M
    3072U,  // LDRB_PRE_REG
6118
1.14M
    3200U,  // LDRBi12
6119
1.14M
    3328U,  // LDRBrs
6120
1.14M
    6291456U, // LDRD
6121
1.14M
    40370176U,  // LDRD_POST
6122
1.14M
    7340032U, // LDRD_PRE
6123
1.14M
    128U, // LDREX
6124
1.14M
    128U, // LDREXB
6125
1.14M
    0U, // LDREXD
6126
1.14M
    128U, // LDREXH
6127
1.14M
    3456U,  // LDRH
6128
1.14M
    7867008U, // LDRHTi
6129
1.14M
    8391296U, // LDRHTr
6130
1.14M
    8915584U, // LDRH_POST
6131
1.14M
    3584U,  // LDRH_PRE
6132
1.14M
    3456U,  // LDRSB
6133
1.14M
    7867008U, // LDRSBTi
6134
1.14M
    8391296U, // LDRSBTr
6135
1.14M
    8915584U, // LDRSB_POST
6136
1.14M
    3584U,  // LDRSB_PRE
6137
1.14M
    3456U,  // LDRSH
6138
1.14M
    7867008U, // LDRSHTi
6139
1.14M
    8391296U, // LDRSHTr
6140
1.14M
    8915584U, // LDRSH_POST
6141
1.14M
    3584U,  // LDRSH_PRE
6142
1.14M
    5769856U, // LDRT_POST_IMM
6143
1.14M
    5769856U, // LDRT_POST_REG
6144
1.14M
    5769856U, // LDR_POST_IMM
6145
1.14M
    5769856U, // LDR_POST_REG
6146
1.14M
    2944U,  // LDR_PRE_IMM
6147
1.14M
    3072U,  // LDR_PRE_REG
6148
1.14M
    3200U,  // LDRcp
6149
1.14M
    3200U,  // LDRi12
6150
1.14M
    3328U,  // LDRrs
6151
1.14M
    103908112U, // MCR
6152
1.14M
    3712U,  // MCR2
6153
1.14M
    137462544U, // MCRR
6154
1.14M
    9437568U, // MCRR2
6155
1.14M
    33554432U,  // MLA
6156
1.14M
    33554432U,  // MLS
6157
1.14M
    0U, // MOVPCLR
6158
1.14M
    17920U, // MOVTi16
6159
1.14M
    1792U,  // MOVi
6160
1.14M
    16384U, // MOVi16
6161
1.14M
    16384U, // MOVr
6162
1.14M
    16384U, // MOVr_TC
6163
1.14M
    1920U,  // MOVsi
6164
1.14M
    1152U,  // MOVsr
6165
1.14M
    115480U,  // MRC
6166
1.14M
    3712U,  // MRC2
6167
1.14M
    0U, // MRRC
6168
1.14M
    0U, // MRRC2
6169
1.14M
    26U,  // MRS
6170
1.14M
    3840U,  // MRSbanked
6171
1.14M
    28U,  // MRSsys
6172
1.14M
    528U, // MSR
6173
1.14M
    0U, // MSRbanked
6174
1.14M
    30U,  // MSRi
6175
1.14M
    0U, // MUL
6176
1.14M
    524288U,  // MVE_ASRLi
6177
1.14M
    524288U,  // MVE_ASRLr
6178
1.14M
    2U, // MVE_DLSTP_16
6179
1.14M
    2U, // MVE_DLSTP_32
6180
1.14M
    2U, // MVE_DLSTP_64
6181
1.14M
    2U, // MVE_DLSTP_8
6182
1.14M
    0U, // MVE_LCTP
6183
1.14M
    0U, // MVE_LETP
6184
1.14M
    524288U,  // MVE_LSLLi
6185
1.14M
    524288U,  // MVE_LSLLr
6186
1.14M
    524288U,  // MVE_LSRL
6187
1.14M
    17920U, // MVE_SQRSHR
6188
1.14M
    9961472U, // MVE_SQRSHRL
6189
1.14M
    17920U, // MVE_SQSHL
6190
1.14M
    524288U,  // MVE_SQSHLL
6191
1.14M
    17920U, // MVE_SRSHR
6192
1.14M
    524288U,  // MVE_SRSHRL
6193
1.14M
    17920U, // MVE_UQRSHL
6194
1.14M
    9961472U, // MVE_UQRSHLL
6195
1.14M
    17920U, // MVE_UQSHL
6196
1.14M
    524288U,  // MVE_UQSHLL
6197
1.14M
    17920U, // MVE_URSHR
6198
1.14M
    524288U,  // MVE_URSHRL
6199
1.14M
    3671552U, // MVE_VABAVs16
6200
1.14M
    3671552U, // MVE_VABAVs32
6201
1.14M
    3671552U, // MVE_VABAVs8
6202
1.14M
    3671552U, // MVE_VABAVu16
6203
1.14M
    3671552U, // MVE_VABAVu32
6204
1.14M
    3671552U, // MVE_VABAVu8
6205
1.14M
    0U, // MVE_VABDf16
6206
1.14M
    0U, // MVE_VABDf32
6207
1.14M
    0U, // MVE_VABDs16
6208
1.14M
    0U, // MVE_VABDs32
6209
1.14M
    0U, // MVE_VABDs8
6210
1.14M
    0U, // MVE_VABDu16
6211
1.14M
    0U, // MVE_VABDu32
6212
1.14M
    0U, // MVE_VABDu8
6213
1.14M
    16384U, // MVE_VABSf16
6214
1.14M
    16384U, // MVE_VABSf32
6215
1.14M
    16384U, // MVE_VABSs16
6216
1.14M
    16384U, // MVE_VABSs32
6217
1.14M
    16384U, // MVE_VABSs8
6218
1.14M
    3671552U, // MVE_VADC
6219
1.14M
    3671552U, // MVE_VADCI
6220
1.14M
    524288U,  // MVE_VADDLVs32acc
6221
1.14M
    0U, // MVE_VADDLVs32no_acc
6222
1.14M
    524288U,  // MVE_VADDLVu32acc
6223
1.14M
    0U, // MVE_VADDLVu32no_acc
6224
1.14M
    17920U, // MVE_VADDVs16acc
6225
1.14M
    16384U, // MVE_VADDVs16no_acc
6226
1.14M
    17920U, // MVE_VADDVs32acc
6227
1.14M
    16384U, // MVE_VADDVs32no_acc
6228
1.14M
    17920U, // MVE_VADDVs8acc
6229
1.14M
    16384U, // MVE_VADDVs8no_acc
6230
1.14M
    17920U, // MVE_VADDVu16acc
6231
1.14M
    16384U, // MVE_VADDVu16no_acc
6232
1.14M
    17920U, // MVE_VADDVu32acc
6233
1.14M
    16384U, // MVE_VADDVu32no_acc
6234
1.14M
    17920U, // MVE_VADDVu8acc
6235
1.14M
    16384U, // MVE_VADDVu8no_acc
6236
1.14M
    0U, // MVE_VADD_qr_f16
6237
1.14M
    0U, // MVE_VADD_qr_f32
6238
1.14M
    0U, // MVE_VADD_qr_i16
6239
1.14M
    0U, // MVE_VADD_qr_i32
6240
1.14M
    0U, // MVE_VADD_qr_i8
6241
1.14M
    0U, // MVE_VADDf16
6242
1.14M
    0U, // MVE_VADDf32
6243
1.14M
    0U, // MVE_VADDi16
6244
1.14M
    0U, // MVE_VADDi32
6245
1.14M
    0U, // MVE_VADDi8
6246
1.14M
    0U, // MVE_VAND
6247
1.14M
    0U, // MVE_VBIC
6248
1.14M
    3968U,  // MVE_VBICimmi16
6249
1.14M
    3968U,  // MVE_VBICimmi32
6250
1.14M
    0U, // MVE_VBRSR16
6251
1.14M
    0U, // MVE_VBRSR32
6252
1.14M
    0U, // MVE_VBRSR8
6253
1.14M
    33554432U,  // MVE_VCADDf16
6254
1.14M
    33554432U,  // MVE_VCADDf32
6255
1.14M
    33554432U,  // MVE_VCADDi16
6256
1.14M
    33554432U,  // MVE_VCADDi32
6257
1.14M
    33554432U,  // MVE_VCADDi8
6258
1.14M
    16384U, // MVE_VCLSs16
6259
1.14M
    16384U, // MVE_VCLSs32
6260
1.14M
    16384U, // MVE_VCLSs8
6261
1.14M
    16384U, // MVE_VCLZs16
6262
1.14M
    16384U, // MVE_VCLZs32
6263
1.14M
    16384U, // MVE_VCLZs8
6264
1.14M
    37225984U,  // MVE_VCMLAf16
6265
1.14M
    37225984U,  // MVE_VCMLAf32
6266
1.14M
    0U, // MVE_VCMPf16
6267
1.14M
    0U, // MVE_VCMPf16r
6268
1.14M
    0U, // MVE_VCMPf32
6269
1.14M
    0U, // MVE_VCMPf32r
6270
1.14M
    0U, // MVE_VCMPi16
6271
1.14M
    0U, // MVE_VCMPi16r
6272
1.14M
    0U, // MVE_VCMPi32
6273
1.14M
    0U, // MVE_VCMPi32r
6274
1.14M
    0U, // MVE_VCMPi8
6275
1.14M
    0U, // MVE_VCMPi8r
6276
1.14M
    0U, // MVE_VCMPs16
6277
1.14M
    0U, // MVE_VCMPs16r
6278
1.14M
    0U, // MVE_VCMPs32
6279
1.14M
    0U, // MVE_VCMPs32r
6280
1.14M
    0U, // MVE_VCMPs8
6281
1.14M
    0U, // MVE_VCMPs8r
6282
1.14M
    0U, // MVE_VCMPu16
6283
1.14M
    0U, // MVE_VCMPu16r
6284
1.14M
    0U, // MVE_VCMPu32
6285
1.14M
    0U, // MVE_VCMPu32r
6286
1.14M
    0U, // MVE_VCMPu8
6287
1.14M
    0U, // MVE_VCMPu8r
6288
1.14M
    33554432U,  // MVE_VCMULf16
6289
1.14M
    33554432U,  // MVE_VCMULf32
6290
1.14M
    2U, // MVE_VCTP16
6291
1.14M
    2U, // MVE_VCTP32
6292
1.14M
    2U, // MVE_VCTP64
6293
1.14M
    2U, // MVE_VCTP8
6294
1.14M
    2U, // MVE_VCVTf16f32bh
6295
1.14M
    2U, // MVE_VCVTf16f32th
6296
1.14M
    536U, // MVE_VCVTf16s16_fix
6297
1.14M
    0U, // MVE_VCVTf16s16n
6298
1.14M
    536U, // MVE_VCVTf16u16_fix
6299
1.14M
    0U, // MVE_VCVTf16u16n
6300
1.14M
    0U, // MVE_VCVTf32f16bh
6301
1.14M
    0U, // MVE_VCVTf32f16th
6302
1.14M
    536U, // MVE_VCVTf32s32_fix
6303
1.14M
    0U, // MVE_VCVTf32s32n
6304
1.14M
    536U, // MVE_VCVTf32u32_fix
6305
1.14M
    0U, // MVE_VCVTf32u32n
6306
1.14M
    536U, // MVE_VCVTs16f16_fix
6307
1.14M
    0U, // MVE_VCVTs16f16a
6308
1.14M
    0U, // MVE_VCVTs16f16m
6309
1.14M
    0U, // MVE_VCVTs16f16n
6310
1.14M
    0U, // MVE_VCVTs16f16p
6311
1.14M
    0U, // MVE_VCVTs16f16z
6312
1.14M
    536U, // MVE_VCVTs32f32_fix
6313
1.14M
    0U, // MVE_VCVTs32f32a
6314
1.14M
    0U, // MVE_VCVTs32f32m
6315
1.14M
    0U, // MVE_VCVTs32f32n
6316
1.14M
    0U, // MVE_VCVTs32f32p
6317
1.14M
    0U, // MVE_VCVTs32f32z
6318
1.14M
    536U, // MVE_VCVTu16f16_fix
6319
1.14M
    0U, // MVE_VCVTu16f16a
6320
1.14M
    0U, // MVE_VCVTu16f16m
6321
1.14M
    0U, // MVE_VCVTu16f16n
6322
1.14M
    0U, // MVE_VCVTu16f16p
6323
1.14M
    0U, // MVE_VCVTu16f16z
6324
1.14M
    536U, // MVE_VCVTu32f32_fix
6325
1.14M
    0U, // MVE_VCVTu32f32a
6326
1.14M
    0U, // MVE_VCVTu32f32m
6327
1.14M
    0U, // MVE_VCVTu32f32n
6328
1.14M
    0U, // MVE_VCVTu32f32p
6329
1.14M
    0U, // MVE_VCVTu32f32z
6330
1.14M
    3670016U, // MVE_VDDUPu16
6331
1.14M
    3670016U, // MVE_VDDUPu32
6332
1.14M
    3670016U, // MVE_VDDUPu8
6333
1.14M
    16384U, // MVE_VDUP16
6334
1.14M
    16384U, // MVE_VDUP32
6335
1.14M
    16384U, // MVE_VDUP8
6336
1.14M
    37224448U,  // MVE_VDWDUPu16
6337
1.14M
    37224448U,  // MVE_VDWDUPu32
6338
1.14M
    37224448U,  // MVE_VDWDUPu8
6339
1.14M
    0U, // MVE_VEOR
6340
1.14M
    3671552U, // MVE_VFMA_qr_Sf16
6341
1.14M
    3671552U, // MVE_VFMA_qr_Sf32
6342
1.14M
    3671552U, // MVE_VFMA_qr_f16
6343
1.14M
    3671552U, // MVE_VFMA_qr_f32
6344
1.14M
    3671552U, // MVE_VFMAf16
6345
1.14M
    3671552U, // MVE_VFMAf32
6346
1.14M
    3671552U, // MVE_VFMSf16
6347
1.14M
    3671552U, // MVE_VFMSf32
6348
1.14M
    0U, // MVE_VHADD_qr_s16
6349
1.14M
    0U, // MVE_VHADD_qr_s32
6350
1.14M
    0U, // MVE_VHADD_qr_s8
6351
1.14M
    0U, // MVE_VHADD_qr_u16
6352
1.14M
    0U, // MVE_VHADD_qr_u32
6353
1.14M
    0U, // MVE_VHADD_qr_u8
6354
1.14M
    0U, // MVE_VHADDs16
6355
1.14M
    0U, // MVE_VHADDs32
6356
1.14M
    0U, // MVE_VHADDs8
6357
1.14M
    0U, // MVE_VHADDu16
6358
1.14M
    0U, // MVE_VHADDu32
6359
1.14M
    0U, // MVE_VHADDu8
6360
1.14M
    33554432U,  // MVE_VHCADDs16
6361
1.14M
    33554432U,  // MVE_VHCADDs32
6362
1.14M
    33554432U,  // MVE_VHCADDs8
6363
1.14M
    0U, // MVE_VHSUB_qr_s16
6364
1.14M
    0U, // MVE_VHSUB_qr_s32
6365
1.14M
    0U, // MVE_VHSUB_qr_s8
6366
1.14M
    0U, // MVE_VHSUB_qr_u16
6367
1.14M
    0U, // MVE_VHSUB_qr_u32
6368
1.14M
    0U, // MVE_VHSUB_qr_u8
6369
1.14M
    0U, // MVE_VHSUBs16
6370
1.14M
    0U, // MVE_VHSUBs32
6371
1.14M
    0U, // MVE_VHSUBs8
6372
1.14M
    0U, // MVE_VHSUBu16
6373
1.14M
    0U, // MVE_VHSUBu32
6374
1.14M
    0U, // MVE_VHSUBu8
6375
1.14M
    3670016U, // MVE_VIDUPu16
6376
1.14M
    3670016U, // MVE_VIDUPu32
6377
1.14M
    3670016U, // MVE_VIDUPu8
6378
1.14M
    37224448U,  // MVE_VIWDUPu16
6379
1.14M
    37224448U,  // MVE_VIWDUPu32
6380
1.14M
    37224448U,  // MVE_VIWDUPu8
6381
1.14M
    0U, // MVE_VLD20_16
6382
1.14M
    0U, // MVE_VLD20_16_wb
6383
1.14M
    0U, // MVE_VLD20_32
6384
1.14M
    0U, // MVE_VLD20_32_wb
6385
1.14M
    0U, // MVE_VLD20_8
6386
1.14M
    0U, // MVE_VLD20_8_wb
6387
1.14M
    0U, // MVE_VLD21_16
6388
1.14M
    0U, // MVE_VLD21_16_wb
6389
1.14M
    0U, // MVE_VLD21_32
6390
1.14M
    0U, // MVE_VLD21_32_wb
6391
1.14M
    0U, // MVE_VLD21_8
6392
1.14M
    0U, // MVE_VLD21_8_wb
6393
1.14M
    0U, // MVE_VLD40_16
6394
1.14M
    0U, // MVE_VLD40_16_wb
6395
1.14M
    0U, // MVE_VLD40_32
6396
1.14M
    0U, // MVE_VLD40_32_wb
6397
1.14M
    0U, // MVE_VLD40_8
6398
1.14M
    0U, // MVE_VLD40_8_wb
6399
1.14M
    0U, // MVE_VLD41_16
6400
1.14M
    0U, // MVE_VLD41_16_wb
6401
1.14M
    0U, // MVE_VLD41_32
6402
1.14M
    0U, // MVE_VLD41_32_wb
6403
1.14M
    0U, // MVE_VLD41_8
6404
1.14M
    0U, // MVE_VLD41_8_wb
6405
1.14M
    0U, // MVE_VLD42_16
6406
1.14M
    0U, // MVE_VLD42_16_wb
6407
1.14M
    0U, // MVE_VLD42_32
6408
1.14M
    0U, // MVE_VLD42_32_wb
6409
1.14M
    0U, // MVE_VLD42_8
6410
1.14M
    0U, // MVE_VLD42_8_wb
6411
1.14M
    0U, // MVE_VLD43_16
6412
1.14M
    0U, // MVE_VLD43_16_wb
6413
1.14M
    0U, // MVE_VLD43_32
6414
1.14M
    0U, // MVE_VLD43_32_wb
6415
1.14M
    0U, // MVE_VLD43_8
6416
1.14M
    0U, // MVE_VLD43_8_wb
6417
1.14M
    4096U,  // MVE_VLDRBS16
6418
1.14M
    133760U,  // MVE_VLDRBS16_post
6419
1.14M
    4224U,  // MVE_VLDRBS16_pre
6420
1.14M
    4352U,  // MVE_VLDRBS16_rq
6421
1.14M
    4096U,  // MVE_VLDRBS32
6422
1.14M
    133760U,  // MVE_VLDRBS32_post
6423
1.14M
    4224U,  // MVE_VLDRBS32_pre
6424
1.14M
    4352U,  // MVE_VLDRBS32_rq
6425
1.14M
    4096U,  // MVE_VLDRBU16
6426
1.14M
    133760U,  // MVE_VLDRBU16_post
6427
1.14M
    4224U,  // MVE_VLDRBU16_pre
6428
1.14M
    4352U,  // MVE_VLDRBU16_rq
6429
1.14M
    4096U,  // MVE_VLDRBU32
6430
1.14M
    133760U,  // MVE_VLDRBU32_post
6431
1.14M
    4224U,  // MVE_VLDRBU32_pre
6432
1.14M
    4352U,  // MVE_VLDRBU32_rq
6433
1.14M
    4096U,  // MVE_VLDRBU8
6434
1.14M
    133760U,  // MVE_VLDRBU8_post
6435
1.14M
    4480U,  // MVE_VLDRBU8_pre
6436
1.14M
    4352U,  // MVE_VLDRBU8_rq
6437
1.14M
    4096U,  // MVE_VLDRDU64_qi
6438
1.14M
    4224U,  // MVE_VLDRDU64_qi_pre
6439
1.14M
    4608U,  // MVE_VLDRDU64_rq
6440
1.14M
    4352U,  // MVE_VLDRDU64_rq_u
6441
1.14M
    4096U,  // MVE_VLDRHS32
6442
1.14M
    133760U,  // MVE_VLDRHS32_post
6443
1.14M
    4224U,  // MVE_VLDRHS32_pre
6444
1.14M
    4736U,  // MVE_VLDRHS32_rq
6445
1.14M
    4352U,  // MVE_VLDRHS32_rq_u
6446
1.14M
    4096U,  // MVE_VLDRHU16
6447
1.14M
    133760U,  // MVE_VLDRHU16_post
6448
1.14M
    4480U,  // MVE_VLDRHU16_pre
6449
1.14M
    4736U,  // MVE_VLDRHU16_rq
6450
1.14M
    4352U,  // MVE_VLDRHU16_rq_u
6451
1.14M
    4096U,  // MVE_VLDRHU32
6452
1.14M
    133760U,  // MVE_VLDRHU32_post
6453
1.14M
    4224U,  // MVE_VLDRHU32_pre
6454
1.14M
    4736U,  // MVE_VLDRHU32_rq
6455
1.14M
    4352U,  // MVE_VLDRHU32_rq_u
6456
1.14M
    4096U,  // MVE_VLDRWU32
6457
1.14M
    133760U,  // MVE_VLDRWU32_post
6458
1.14M
    4480U,  // MVE_VLDRWU32_pre
6459
1.14M
    4096U,  // MVE_VLDRWU32_qi
6460
1.14M
    4224U,  // MVE_VLDRWU32_qi_pre
6461
1.14M
    4864U,  // MVE_VLDRWU32_rq
6462
1.14M
    4352U,  // MVE_VLDRWU32_rq_u
6463
1.14M
    17920U, // MVE_VMAXAVs16
6464
1.14M
    17920U, // MVE_VMAXAVs32
6465
1.14M
    17920U, // MVE_VMAXAVs8
6466
1.14M
    17920U, // MVE_VMAXAs16
6467
1.14M
    17920U, // MVE_VMAXAs32
6468
1.14M
    17920U, // MVE_VMAXAs8
6469
1.14M
    17920U, // MVE_VMAXNMAVf16
6470
1.14M
    17920U, // MVE_VMAXNMAVf32
6471
1.14M
    17920U, // MVE_VMAXNMAf16
6472
1.14M
    17920U, // MVE_VMAXNMAf32
6473
1.14M
    17920U, // MVE_VMAXNMVf16
6474
1.14M
    17920U, // MVE_VMAXNMVf32
6475
1.14M
    0U, // MVE_VMAXNMf16
6476
1.14M
    0U, // MVE_VMAXNMf32
6477
1.14M
    17920U, // MVE_VMAXVs16
6478
1.14M
    17920U, // MVE_VMAXVs32
6479
1.14M
    17920U, // MVE_VMAXVs8
6480
1.14M
    17920U, // MVE_VMAXVu16
6481
1.14M
    17920U, // MVE_VMAXVu32
6482
1.14M
    17920U, // MVE_VMAXVu8
6483
1.14M
    0U, // MVE_VMAXs16
6484
1.14M
    0U, // MVE_VMAXs32
6485
1.14M
    0U, // MVE_VMAXs8
6486
1.14M
    0U, // MVE_VMAXu16
6487
1.14M
    0U, // MVE_VMAXu32
6488
1.14M
    0U, // MVE_VMAXu8
6489
1.14M
    17920U, // MVE_VMINAVs16
6490
1.14M
    17920U, // MVE_VMINAVs32
6491
1.14M
    17920U, // MVE_VMINAVs8
6492
1.14M
    17920U, // MVE_VMINAs16
6493
1.14M
    17920U, // MVE_VMINAs32
6494
1.14M
    17920U, // MVE_VMINAs8
6495
1.14M
    17920U, // MVE_VMINNMAVf16
6496
1.14M
    17920U, // MVE_VMINNMAVf32
6497
1.14M
    17920U, // MVE_VMINNMAf16
6498
1.14M
    17920U, // MVE_VMINNMAf32
6499
1.14M
    17920U, // MVE_VMINNMVf16
6500
1.14M
    17920U, // MVE_VMINNMVf32
6501
1.14M
    0U, // MVE_VMINNMf16
6502
1.14M
    0U, // MVE_VMINNMf32
6503
1.14M
    17920U, // MVE_VMINVs16
6504
1.14M
    17920U, // MVE_VMINVs32
6505
1.14M
    17920U, // MVE_VMINVs8
6506
1.14M
    17920U, // MVE_VMINVu16
6507
1.14M
    17920U, // MVE_VMINVu32
6508
1.14M
    17920U, // MVE_VMINVu8
6509
1.14M
    0U, // MVE_VMINs16
6510
1.14M
    0U, // MVE_VMINs32
6511
1.14M
    0U, // MVE_VMINs8
6512
1.14M
    0U, // MVE_VMINu16
6513
1.14M
    0U, // MVE_VMINu32
6514
1.14M
    0U, // MVE_VMINu8
6515
1.14M
    3671552U, // MVE_VMLADAVas16
6516
1.14M
    3671552U, // MVE_VMLADAVas32
6517
1.14M
    3671552U, // MVE_VMLADAVas8
6518
1.14M
    3671552U, // MVE_VMLADAVau16
6519
1.14M
    3671552U, // MVE_VMLADAVau32
6520
1.14M
    3671552U, // MVE_VMLADAVau8
6521
1.14M
    3671552U, // MVE_VMLADAVaxs16
6522
1.14M
    3671552U, // MVE_VMLADAVaxs32
6523
1.14M
    3671552U, // MVE_VMLADAVaxs8
6524
1.14M
    0U, // MVE_VMLADAVs16
6525
1.14M
    0U, // MVE_VMLADAVs32
6526
1.14M
    0U, // MVE_VMLADAVs8
6527
1.14M
    0U, // MVE_VMLADAVu16
6528
1.14M
    0U, // MVE_VMLADAVu32
6529
1.14M
    0U, // MVE_VMLADAVu8
6530
1.14M
    0U, // MVE_VMLADAVxs16
6531
1.14M
    0U, // MVE_VMLADAVxs32
6532
1.14M
    0U, // MVE_VMLADAVxs8
6533
1.14M
    34078720U,  // MVE_VMLALDAVas16
6534
1.14M
    34078720U,  // MVE_VMLALDAVas32
6535
1.14M
    34078720U,  // MVE_VMLALDAVau16
6536
1.14M
    34078720U,  // MVE_VMLALDAVau32
6537
1.14M
    34078720U,  // MVE_VMLALDAVaxs16
6538
1.14M
    34078720U,  // MVE_VMLALDAVaxs32
6539
1.14M
    33554432U,  // MVE_VMLALDAVs16
6540
1.14M
    33554432U,  // MVE_VMLALDAVs32
6541
1.14M
    33554432U,  // MVE_VMLALDAVu16
6542
1.14M
    33554432U,  // MVE_VMLALDAVu32
6543
1.14M
    33554432U,  // MVE_VMLALDAVxs16
6544
1.14M
    33554432U,  // MVE_VMLALDAVxs32
6545
1.14M
    3671552U, // MVE_VMLAS_qr_i16
6546
1.14M
    3671552U, // MVE_VMLAS_qr_i32
6547
1.14M
    3671552U, // MVE_VMLAS_qr_i8
6548
1.14M
    3671552U, // MVE_VMLA_qr_i16
6549
1.14M
    3671552U, // MVE_VMLA_qr_i32
6550
1.14M
    3671552U, // MVE_VMLA_qr_i8
6551
1.14M
    3671552U, // MVE_VMLSDAVas16
6552
1.14M
    3671552U, // MVE_VMLSDAVas32
6553
1.14M
    3671552U, // MVE_VMLSDAVas8
6554
1.14M
    3671552U, // MVE_VMLSDAVaxs16
6555
1.14M
    3671552U, // MVE_VMLSDAVaxs32
6556
1.14M
    3671552U, // MVE_VMLSDAVaxs8
6557
1.14M
    0U, // MVE_VMLSDAVs16
6558
1.14M
    0U, // MVE_VMLSDAVs32
6559
1.14M
    0U, // MVE_VMLSDAVs8
6560
1.14M
    0U, // MVE_VMLSDAVxs16
6561
1.14M
    0U, // MVE_VMLSDAVxs32
6562
1.14M
    0U, // MVE_VMLSDAVxs8
6563
1.14M
    34078720U,  // MVE_VMLSLDAVas16
6564
1.14M
    34078720U,  // MVE_VMLSLDAVas32
6565
1.14M
    34078720U,  // MVE_VMLSLDAVaxs16
6566
1.14M
    34078720U,  // MVE_VMLSLDAVaxs32
6567
1.14M
    33554432U,  // MVE_VMLSLDAVs16
6568
1.14M
    33554432U,  // MVE_VMLSLDAVs32
6569
1.14M
    33554432U,  // MVE_VMLSLDAVxs16
6570
1.14M
    33554432U,  // MVE_VMLSLDAVxs32
6571
1.14M
    16384U, // MVE_VMOVLs16bh
6572
1.14M
    16384U, // MVE_VMOVLs16th
6573
1.14M
    16384U, // MVE_VMOVLs8bh
6574
1.14M
    16384U, // MVE_VMOVLs8th
6575
1.14M
    16384U, // MVE_VMOVLu16bh
6576
1.14M
    16384U, // MVE_VMOVLu16th
6577
1.14M
    16384U, // MVE_VMOVLu8bh
6578
1.14M
    16384U, // MVE_VMOVLu8th
6579
1.14M
    17920U, // MVE_VMOVNi16bh
6580
1.14M
    17920U, // MVE_VMOVNi16th
6581
1.14M
    17920U, // MVE_VMOVNi32bh
6582
1.14M
    17920U, // MVE_VMOVNi32th
6583
1.14M
    147456U,  // MVE_VMOV_from_lane_32
6584
1.14M
    147456U,  // MVE_VMOV_from_lane_s16
6585
1.14M
    147456U,  // MVE_VMOV_from_lane_s8
6586
1.14M
    147456U,  // MVE_VMOV_from_lane_u16
6587
1.14M
    147456U,  // MVE_VMOV_from_lane_u8
6588
1.14M
    10650376U,  // MVE_VMOV_q_rr
6589
1.14M
    167772160U, // MVE_VMOV_rr_q
6590
1.14M
    32U,  // MVE_VMOV_to_lane_16
6591
1.14M
    32U,  // MVE_VMOV_to_lane_32
6592
1.14M
    32U,  // MVE_VMOV_to_lane_8
6593
1.14M
    2048U,  // MVE_VMOVimmf32
6594
1.14M
    4992U,  // MVE_VMOVimmi16
6595
1.14M
    4992U,  // MVE_VMOVimmi32
6596
1.14M
    0U, // MVE_VMOVimmi64
6597
1.14M
    4992U,  // MVE_VMOVimmi8
6598
1.14M
    0U, // MVE_VMULHs16
6599
1.14M
    0U, // MVE_VMULHs32
6600
1.14M
    0U, // MVE_VMULHs8
6601
1.14M
    0U, // MVE_VMULHu16
6602
1.14M
    0U, // MVE_VMULHu32
6603
1.14M
    0U, // MVE_VMULHu8
6604
1.14M
    0U, // MVE_VMULLBp16
6605
1.14M
    0U, // MVE_VMULLBp8
6606
1.14M
    0U, // MVE_VMULLBs16
6607
1.14M
    0U, // MVE_VMULLBs32
6608
1.14M
    0U, // MVE_VMULLBs8
6609
1.14M
    0U, // MVE_VMULLBu16
6610
1.14M
    0U, // MVE_VMULLBu32
6611
1.14M
    0U, // MVE_VMULLBu8
6612
1.14M
    0U, // MVE_VMULLTp16
6613
1.14M
    0U, // MVE_VMULLTp8
6614
1.14M
    0U, // MVE_VMULLTs16
6615
1.14M
    0U, // MVE_VMULLTs32
6616
1.14M
    0U, // MVE_VMULLTs8
6617
1.14M
    0U, // MVE_VMULLTu16
6618
1.14M
    0U, // MVE_VMULLTu32
6619
1.14M
    0U, // MVE_VMULLTu8
6620
1.14M
    0U, // MVE_VMUL_qr_f16
6621
1.14M
    0U, // MVE_VMUL_qr_f32
6622
1.14M
    0U, // MVE_VMUL_qr_i16
6623
1.14M
    0U, // MVE_VMUL_qr_i32
6624
1.14M
    0U, // MVE_VMUL_qr_i8
6625
1.14M
    0U, // MVE_VMULf16
6626
1.14M
    0U, // MVE_VMULf32
6627
1.14M
    0U, // MVE_VMULi16
6628
1.14M
    0U, // MVE_VMULi32
6629
1.14M
    0U, // MVE_VMULi8
6630
1.14M
    16384U, // MVE_VMVN
6631
1.14M
    4992U,  // MVE_VMVNimmi16
6632
1.14M
    4992U,  // MVE_VMVNimmi32
6633
1.14M
    16384U, // MVE_VNEGf16
6634
1.14M
    16384U, // MVE_VNEGf32
6635
1.14M
    16384U, // MVE_VNEGs16
6636
1.14M
    16384U, // MVE_VNEGs32
6637
1.14M
    16384U, // MVE_VNEGs8
6638
1.14M
    0U, // MVE_VORN
6639
1.14M
    0U, // MVE_VORR
6640
1.14M
    3968U,  // MVE_VORRimmi16
6641
1.14M
    3968U,  // MVE_VORRimmi32
6642
1.14M
    0U, // MVE_VPNOT
6643
1.14M
    0U, // MVE_VPSEL
6644
1.14M
    0U, // MVE_VPST
6645
1.14M
    0U, // MVE_VPTv16i8
6646
1.14M
    0U, // MVE_VPTv16i8r
6647
1.14M
    0U, // MVE_VPTv16s8
6648
1.14M
    0U, // MVE_VPTv16s8r
6649
1.14M
    0U, // MVE_VPTv16u8
6650
1.14M
    0U, // MVE_VPTv16u8r
6651
1.14M
    0U, // MVE_VPTv4f32
6652
1.14M
    0U, // MVE_VPTv4f32r
6653
1.14M
    0U, // MVE_VPTv4i32
6654
1.14M
    0U, // MVE_VPTv4i32r
6655
1.14M
    0U, // MVE_VPTv4s32
6656
1.14M
    0U, // MVE_VPTv4s32r
6657
1.14M
    0U, // MVE_VPTv4u32
6658
1.14M
    0U, // MVE_VPTv4u32r
6659
1.14M
    0U, // MVE_VPTv8f16
6660
1.14M
    0U, // MVE_VPTv8f16r
6661
1.14M
    0U, // MVE_VPTv8i16
6662
1.14M
    0U, // MVE_VPTv8i16r
6663
1.14M
    0U, // MVE_VPTv8s16
6664
1.14M
    0U, // MVE_VPTv8s16r
6665
1.14M
    0U, // MVE_VPTv8u16
6666
1.14M
    0U, // MVE_VPTv8u16r
6667
1.14M
    16384U, // MVE_VQABSs16
6668
1.14M
    16384U, // MVE_VQABSs32
6669
1.14M
    16384U, // MVE_VQABSs8
6670
1.14M
    0U, // MVE_VQADD_qr_s16
6671
1.14M
    0U, // MVE_VQADD_qr_s32
6672
1.14M
    0U, // MVE_VQADD_qr_s8
6673
1.14M
    0U, // MVE_VQADD_qr_u16
6674
1.14M
    0U, // MVE_VQADD_qr_u32
6675
1.14M
    0U, // MVE_VQADD_qr_u8
6676
1.14M
    0U, // MVE_VQADDs16
6677
1.14M
    0U, // MVE_VQADDs32
6678
1.14M
    0U, // MVE_VQADDs8
6679
1.14M
    0U, // MVE_VQADDu16
6680
1.14M
    0U, // MVE_VQADDu32
6681
1.14M
    0U, // MVE_VQADDu8
6682
1.14M
    3671552U, // MVE_VQDMLADHXs16
6683
1.14M
    3671552U, // MVE_VQDMLADHXs32
6684
1.14M
    3671552U, // MVE_VQDMLADHXs8
6685
1.14M
    3671552U, // MVE_VQDMLADHs16
6686
1.14M
    3671552U, // MVE_VQDMLADHs32
6687
1.14M
    3671552U, // MVE_VQDMLADHs8
6688
1.14M
    3671552U, // MVE_VQDMLAH_qrs16
6689
1.14M
    3671552U, // MVE_VQDMLAH_qrs32
6690
1.14M
    3671552U, // MVE_VQDMLAH_qrs8
6691
1.14M
    3671552U, // MVE_VQDMLASH_qrs16
6692
1.14M
    3671552U, // MVE_VQDMLASH_qrs32
6693
1.14M
    3671552U, // MVE_VQDMLASH_qrs8
6694
1.14M
    3671552U, // MVE_VQDMLSDHXs16
6695
1.14M
    3671552U, // MVE_VQDMLSDHXs32
6696
1.14M
    3671552U, // MVE_VQDMLSDHXs8
6697
1.14M
    3671552U, // MVE_VQDMLSDHs16
6698
1.14M
    3671552U, // MVE_VQDMLSDHs32
6699
1.14M
    3671552U, // MVE_VQDMLSDHs8
6700
1.14M
    0U, // MVE_VQDMULH_qr_s16
6701
1.14M
    0U, // MVE_VQDMULH_qr_s32
6702
1.14M
    0U, // MVE_VQDMULH_qr_s8
6703
1.14M
    0U, // MVE_VQDMULHi16
6704
1.14M
    0U, // MVE_VQDMULHi32
6705
1.14M
    0U, // MVE_VQDMULHi8
6706
1.14M
    0U, // MVE_VQDMULL_qr_s16bh
6707
1.14M
    0U, // MVE_VQDMULL_qr_s16th
6708
1.14M
    0U, // MVE_VQDMULL_qr_s32bh
6709
1.14M
    0U, // MVE_VQDMULL_qr_s32th
6710
1.14M
    0U, // MVE_VQDMULLs16bh
6711
1.14M
    0U, // MVE_VQDMULLs16th
6712
1.14M
    0U, // MVE_VQDMULLs32bh
6713
1.14M
    0U, // MVE_VQDMULLs32th
6714
1.14M
    17920U, // MVE_VQMOVNs16bh
6715
1.14M
    17920U, // MVE_VQMOVNs16th
6716
1.14M
    17920U, // MVE_VQMOVNs32bh
6717
1.14M
    17920U, // MVE_VQMOVNs32th
6718
1.14M
    17920U, // MVE_VQMOVNu16bh
6719
1.14M
    17920U, // MVE_VQMOVNu16th
6720
1.14M
    17920U, // MVE_VQMOVNu32bh
6721
1.14M
    17920U, // MVE_VQMOVNu32th
6722
1.14M
    17920U, // MVE_VQMOVUNs16bh
6723
1.14M
    17920U, // MVE_VQMOVUNs16th
6724
1.14M
    17920U, // MVE_VQMOVUNs32bh
6725
1.14M
    17920U, // MVE_VQMOVUNs32th
6726
1.14M
    16384U, // MVE_VQNEGs16
6727
1.14M
    16384U, // MVE_VQNEGs32
6728
1.14M
    16384U, // MVE_VQNEGs8
6729
1.14M
    3671552U, // MVE_VQRDMLADHXs16
6730
1.14M
    3671552U, // MVE_VQRDMLADHXs32
6731
1.14M
    3671552U, // MVE_VQRDMLADHXs8
6732
1.14M
    3671552U, // MVE_VQRDMLADHs16
6733
1.14M
    3671552U, // MVE_VQRDMLADHs32
6734
1.14M
    3671552U, // MVE_VQRDMLADHs8
6735
1.14M
    3671552U, // MVE_VQRDMLAH_qrs16
6736
1.14M
    3671552U, // MVE_VQRDMLAH_qrs32
6737
1.14M
    3671552U, // MVE_VQRDMLAH_qrs8
6738
1.14M
    3671552U, // MVE_VQRDMLASH_qrs16
6739
1.14M
    3671552U, // MVE_VQRDMLASH_qrs32
6740
1.14M
    3671552U, // MVE_VQRDMLASH_qrs8
6741
1.14M
    3671552U, // MVE_VQRDMLSDHXs16
6742
1.14M
    3671552U, // MVE_VQRDMLSDHXs32
6743
1.14M
    3671552U, // MVE_VQRDMLSDHXs8
6744
1.14M
    3671552U, // MVE_VQRDMLSDHs16
6745
1.14M
    3671552U, // MVE_VQRDMLSDHs32
6746
1.14M
    3671552U, // MVE_VQRDMLSDHs8
6747
1.14M
    0U, // MVE_VQRDMULH_qr_s16
6748
1.14M
    0U, // MVE_VQRDMULH_qr_s32
6749
1.14M
    0U, // MVE_VQRDMULH_qr_s8
6750
1.14M
    0U, // MVE_VQRDMULHi16
6751
1.14M
    0U, // MVE_VQRDMULHi32
6752
1.14M
    0U, // MVE_VQRDMULHi8
6753
1.14M
    0U, // MVE_VQRSHL_by_vecs16
6754
1.14M
    0U, // MVE_VQRSHL_by_vecs32
6755
1.14M
    0U, // MVE_VQRSHL_by_vecs8
6756
1.14M
    0U, // MVE_VQRSHL_by_vecu16
6757
1.14M
    0U, // MVE_VQRSHL_by_vecu32
6758
1.14M
    0U, // MVE_VQRSHL_by_vecu8
6759
1.14M
    17920U, // MVE_VQRSHL_qrs16
6760
1.14M
    17920U, // MVE_VQRSHL_qrs32
6761
1.14M
    17920U, // MVE_VQRSHL_qrs8
6762
1.14M
    17920U, // MVE_VQRSHL_qru16
6763
1.14M
    17920U, // MVE_VQRSHL_qru32
6764
1.14M
    17920U, // MVE_VQRSHL_qru8
6765
1.14M
    3671552U, // MVE_VQRSHRNbhs16
6766
1.14M
    3671552U, // MVE_VQRSHRNbhs32
6767
1.14M
    3671552U, // MVE_VQRSHRNbhu16
6768
1.14M
    3671552U, // MVE_VQRSHRNbhu32
6769
1.14M
    3671552U, // MVE_VQRSHRNths16
6770
1.14M
    3671552U, // MVE_VQRSHRNths32
6771
1.14M
    3671552U, // MVE_VQRSHRNthu16
6772
1.14M
    3671552U, // MVE_VQRSHRNthu32
6773
1.14M
    3671552U, // MVE_VQRSHRUNs16bh
6774
1.14M
    3671552U, // MVE_VQRSHRUNs16th
6775
1.14M
    3671552U, // MVE_VQRSHRUNs32bh
6776
1.14M
    3671552U, // MVE_VQRSHRUNs32th
6777
1.14M
    0U, // MVE_VQSHLU_imms16
6778
1.14M
    0U, // MVE_VQSHLU_imms32
6779
1.14M
    0U, // MVE_VQSHLU_imms8
6780
1.14M
    0U, // MVE_VQSHL_by_vecs16
6781
1.14M
    0U, // MVE_VQSHL_by_vecs32
6782
1.14M
    0U, // MVE_VQSHL_by_vecs8
6783
1.14M
    0U, // MVE_VQSHL_by_vecu16
6784
1.14M
    0U, // MVE_VQSHL_by_vecu32
6785
1.14M
    0U, // MVE_VQSHL_by_vecu8
6786
1.14M
    17920U, // MVE_VQSHL_qrs16
6787
1.14M
    17920U, // MVE_VQSHL_qrs32
6788
1.14M
    17920U, // MVE_VQSHL_qrs8
6789
1.14M
    17920U, // MVE_VQSHL_qru16
6790
1.14M
    17920U, // MVE_VQSHL_qru32
6791
1.14M
    17920U, // MVE_VQSHL_qru8
6792
1.14M
    0U, // MVE_VQSHLimms16
6793
1.14M
    0U, // MVE_VQSHLimms32
6794
1.14M
    0U, // MVE_VQSHLimms8
6795
1.14M
    0U, // MVE_VQSHLimmu16
6796
1.14M
    0U, // MVE_VQSHLimmu32
6797
1.14M
    0U, // MVE_VQSHLimmu8
6798
1.14M
    3671552U, // MVE_VQSHRNbhs16
6799
1.14M
    3671552U, // MVE_VQSHRNbhs32
6800
1.14M
    3671552U, // MVE_VQSHRNbhu16
6801
1.14M
    3671552U, // MVE_VQSHRNbhu32
6802
1.14M
    3671552U, // MVE_VQSHRNths16
6803
1.14M
    3671552U, // MVE_VQSHRNths32
6804
1.14M
    3671552U, // MVE_VQSHRNthu16
6805
1.14M
    3671552U, // MVE_VQSHRNthu32
6806
1.14M
    3671552U, // MVE_VQSHRUNs16bh
6807
1.14M
    3671552U, // MVE_VQSHRUNs16th
6808
1.14M
    3671552U, // MVE_VQSHRUNs32bh
6809
1.14M
    3671552U, // MVE_VQSHRUNs32th
6810
1.14M
    0U, // MVE_VQSUB_qr_s16
6811
1.14M
    0U, // MVE_VQSUB_qr_s32
6812
1.14M
    0U, // MVE_VQSUB_qr_s8
6813
1.14M
    0U, // MVE_VQSUB_qr_u16
6814
1.14M
    0U, // MVE_VQSUB_qr_u32
6815
1.14M
    0U, // MVE_VQSUB_qr_u8
6816
1.14M
    0U, // MVE_VQSUBs16
6817
1.14M
    0U, // MVE_VQSUBs32
6818
1.14M
    0U, // MVE_VQSUBs8
6819
1.14M
    0U, // MVE_VQSUBu16
6820
1.14M
    0U, // MVE_VQSUBu32
6821
1.14M
    0U, // MVE_VQSUBu8
6822
1.14M
    16384U, // MVE_VREV16_8
6823
1.14M
    16384U, // MVE_VREV32_16
6824
1.14M
    16384U, // MVE_VREV32_8
6825
1.14M
    16384U, // MVE_VREV64_16
6826
1.14M
    16384U, // MVE_VREV64_32
6827
1.14M
    16384U, // MVE_VREV64_8
6828
1.14M
    0U, // MVE_VRHADDs16
6829
1.14M
    0U, // MVE_VRHADDs32
6830
1.14M
    0U, // MVE_VRHADDs8
6831
1.14M
    0U, // MVE_VRHADDu16
6832
1.14M
    0U, // MVE_VRHADDu32
6833
1.14M
    0U, // MVE_VRHADDu8
6834
1.14M
    16384U, // MVE_VRINTf16A
6835
1.14M
    16384U, // MVE_VRINTf16M
6836
1.14M
    16384U, // MVE_VRINTf16N
6837
1.14M
    16384U, // MVE_VRINTf16P
6838
1.14M
    16384U, // MVE_VRINTf16X
6839
1.14M
    16384U, // MVE_VRINTf16Z
6840
1.14M
    16384U, // MVE_VRINTf32A
6841
1.14M
    16384U, // MVE_VRINTf32M
6842
1.14M
    16384U, // MVE_VRINTf32N
6843
1.14M
    16384U, // MVE_VRINTf32P
6844
1.14M
    16384U, // MVE_VRINTf32X
6845
1.14M
    16384U, // MVE_VRINTf32Z
6846
1.14M
    34078720U,  // MVE_VRMLALDAVHas32
6847
1.14M
    34078720U,  // MVE_VRMLALDAVHau32
6848
1.14M
    34078720U,  // MVE_VRMLALDAVHaxs32
6849
1.14M
    33554432U,  // MVE_VRMLALDAVHs32
6850
1.14M
    33554432U,  // MVE_VRMLALDAVHu32
6851
1.14M
    33554432U,  // MVE_VRMLALDAVHxs32
6852
1.14M
    34078720U,  // MVE_VRMLSLDAVHas32
6853
1.14M
    34078720U,  // MVE_VRMLSLDAVHaxs32
6854
1.14M
    33554432U,  // MVE_VRMLSLDAVHs32
6855
1.14M
    33554432U,  // MVE_VRMLSLDAVHxs32
6856
1.14M
    0U, // MVE_VRMULHs16
6857
1.14M
    0U, // MVE_VRMULHs32
6858
1.14M
    0U, // MVE_VRMULHs8
6859
1.14M
    0U, // MVE_VRMULHu16
6860
1.14M
    0U, // MVE_VRMULHu32
6861
1.14M
    0U, // MVE_VRMULHu8
6862
1.14M
    0U, // MVE_VRSHL_by_vecs16
6863
1.14M
    0U, // MVE_VRSHL_by_vecs32
6864
1.14M
    0U, // MVE_VRSHL_by_vecs8
6865
1.14M
    0U, // MVE_VRSHL_by_vecu16
6866
1.14M
    0U, // MVE_VRSHL_by_vecu32
6867
1.14M
    0U, // MVE_VRSHL_by_vecu8
6868
1.14M
    17920U, // MVE_VRSHL_qrs16
6869
1.14M
    17920U, // MVE_VRSHL_qrs32
6870
1.14M
    17920U, // MVE_VRSHL_qrs8
6871
1.14M
    17920U, // MVE_VRSHL_qru16
6872
1.14M
    17920U, // MVE_VRSHL_qru32
6873
1.14M
    17920U, // MVE_VRSHL_qru8
6874
1.14M
    3671552U, // MVE_VRSHRNi16bh
6875
1.14M
    3671552U, // MVE_VRSHRNi16th
6876
1.14M
    3671552U, // MVE_VRSHRNi32bh
6877
1.14M
    3671552U, // MVE_VRSHRNi32th
6878
1.14M
    0U, // MVE_VRSHR_imms16
6879
1.14M
    0U, // MVE_VRSHR_imms32
6880
1.14M
    0U, // MVE_VRSHR_imms8
6881
1.14M
    0U, // MVE_VRSHR_immu16
6882
1.14M
    0U, // MVE_VRSHR_immu32
6883
1.14M
    0U, // MVE_VRSHR_immu8
6884
1.14M
    3671552U, // MVE_VSBC
6885
1.14M
    3671552U, // MVE_VSBCI
6886
1.14M
    524672U,  // MVE_VSHLC
6887
1.14M
    0U, // MVE_VSHLL_imms16bh
6888
1.14M
    0U, // MVE_VSHLL_imms16th
6889
1.14M
    0U, // MVE_VSHLL_imms8bh
6890
1.14M
    0U, // MVE_VSHLL_imms8th
6891
1.14M
    0U, // MVE_VSHLL_immu16bh
6892
1.14M
    0U, // MVE_VSHLL_immu16th
6893
1.14M
    0U, // MVE_VSHLL_immu8bh
6894
1.14M
    0U, // MVE_VSHLL_immu8th
6895
1.14M
    180224U,  // MVE_VSHLL_lws16bh
6896
1.14M
    180224U,  // MVE_VSHLL_lws16th
6897
1.14M
    196608U,  // MVE_VSHLL_lws8bh
6898
1.14M
    196608U,  // MVE_VSHLL_lws8th
6899
1.14M
    180224U,  // MVE_VSHLL_lwu16bh
6900
1.14M
    180224U,  // MVE_VSHLL_lwu16th
6901
1.14M
    196608U,  // MVE_VSHLL_lwu8bh
6902
1.14M
    196608U,  // MVE_VSHLL_lwu8th
6903
1.14M
    0U, // MVE_VSHL_by_vecs16
6904
1.14M
    0U, // MVE_VSHL_by_vecs32
6905
1.14M
    0U, // MVE_VSHL_by_vecs8
6906
1.14M
    0U, // MVE_VSHL_by_vecu16
6907
1.14M
    0U, // MVE_VSHL_by_vecu32
6908
1.14M
    0U, // MVE_VSHL_by_vecu8
6909
1.14M
    0U, // MVE_VSHL_immi16
6910
1.14M
    0U, // MVE_VSHL_immi32
6911
1.14M
    0U, // MVE_VSHL_immi8
6912
1.14M
    17920U, // MVE_VSHL_qrs16
6913
1.14M
    17920U, // MVE_VSHL_qrs32
6914
1.14M
    17920U, // MVE_VSHL_qrs8
6915
1.14M
    17920U, // MVE_VSHL_qru16
6916
1.14M
    17920U, // MVE_VSHL_qru32
6917
1.14M
    17920U, // MVE_VSHL_qru8
6918
1.14M
    3671552U, // MVE_VSHRNi16bh
6919
1.14M
    3671552U, // MVE_VSHRNi16th
6920
1.14M
    3671552U, // MVE_VSHRNi32bh
6921
1.14M
    3671552U, // MVE_VSHRNi32th
6922
1.14M
    0U, // MVE_VSHR_imms16
6923
1.14M
    0U, // MVE_VSHR_imms32
6924
1.14M
    0U, // MVE_VSHR_imms8
6925
1.14M
    0U, // MVE_VSHR_immu16
6926
1.14M
    0U, // MVE_VSHR_immu32
6927
1.14M
    0U, // MVE_VSHR_immu8
6928
1.14M
    3671552U, // MVE_VSLIimm16
6929
1.14M
    3671552U, // MVE_VSLIimm32
6930
1.14M
    3671552U, // MVE_VSLIimm8
6931
1.14M
    3671552U, // MVE_VSRIimm16
6932
1.14M
    3671552U, // MVE_VSRIimm32
6933
1.14M
    3671552U, // MVE_VSRIimm8
6934
1.14M
    0U, // MVE_VST20_16
6935
1.14M
    0U, // MVE_VST20_16_wb
6936
1.14M
    0U, // MVE_VST20_32
6937
1.14M
    0U, // MVE_VST20_32_wb
6938
1.14M
    0U, // MVE_VST20_8
6939
1.14M
    0U, // MVE_VST20_8_wb
6940
1.14M
    0U, // MVE_VST21_16
6941
1.14M
    0U, // MVE_VST21_16_wb
6942
1.14M
    0U, // MVE_VST21_32
6943
1.14M
    0U, // MVE_VST21_32_wb
6944
1.14M
    0U, // MVE_VST21_8
6945
1.14M
    0U, // MVE_VST21_8_wb
6946
1.14M
    0U, // MVE_VST40_16
6947
1.14M
    0U, // MVE_VST40_16_wb
6948
1.14M
    0U, // MVE_VST40_32
6949
1.14M
    0U, // MVE_VST40_32_wb
6950
1.14M
    0U, // MVE_VST40_8
6951
1.14M
    0U, // MVE_VST40_8_wb
6952
1.14M
    0U, // MVE_VST41_16
6953
1.14M
    0U, // MVE_VST41_16_wb
6954
1.14M
    0U, // MVE_VST41_32
6955
1.14M
    0U, // MVE_VST41_32_wb
6956
1.14M
    0U, // MVE_VST41_8
6957
1.14M
    0U, // MVE_VST41_8_wb
6958
1.14M
    0U, // MVE_VST42_16
6959
1.14M
    0U, // MVE_VST42_16_wb
6960
1.14M
    0U, // MVE_VST42_32
6961
1.14M
    0U, // MVE_VST42_32_wb
6962
1.14M
    0U, // MVE_VST42_8
6963
1.14M
    0U, // MVE_VST42_8_wb
6964
1.14M
    0U, // MVE_VST43_16
6965
1.14M
    0U, // MVE_VST43_16_wb
6966
1.14M
    0U, // MVE_VST43_32
6967
1.14M
    0U, // MVE_VST43_32_wb
6968
1.14M
    0U, // MVE_VST43_8
6969
1.14M
    0U, // MVE_VST43_8_wb
6970
1.14M
    4096U,  // MVE_VSTRB16
6971
1.14M
    133760U,  // MVE_VSTRB16_post
6972
1.14M
    4224U,  // MVE_VSTRB16_pre
6973
1.14M
    4352U,  // MVE_VSTRB16_rq
6974
1.14M
    4096U,  // MVE_VSTRB32
6975
1.14M
    133760U,  // MVE_VSTRB32_post
6976
1.14M
    4224U,  // MVE_VSTRB32_pre
6977
1.14M
    4352U,  // MVE_VSTRB32_rq
6978
1.14M
    4352U,  // MVE_VSTRB8_rq
6979
1.14M
    4096U,  // MVE_VSTRBU8
6980
1.14M
    133760U,  // MVE_VSTRBU8_post
6981
1.14M
    4480U,  // MVE_VSTRBU8_pre
6982
1.14M
    4096U,  // MVE_VSTRD64_qi
6983
1.14M
    4224U,  // MVE_VSTRD64_qi_pre
6984
1.14M
    4608U,  // MVE_VSTRD64_rq
6985
1.14M
    4352U,  // MVE_VSTRD64_rq_u
6986
1.14M
    4736U,  // MVE_VSTRH16_rq
6987
1.14M
    4352U,  // MVE_VSTRH16_rq_u
6988
1.14M
    4096U,  // MVE_VSTRH32
6989
1.14M
    133760U,  // MVE_VSTRH32_post
6990
1.14M
    4224U,  // MVE_VSTRH32_pre
6991
1.14M
    4736U,  // MVE_VSTRH32_rq
6992
1.14M
    4352U,  // MVE_VSTRH32_rq_u
6993
1.14M
    4096U,  // MVE_VSTRHU16
6994
1.14M
    133760U,  // MVE_VSTRHU16_post
6995
1.14M
    4480U,  // MVE_VSTRHU16_pre
6996
1.14M
    4096U,  // MVE_VSTRW32_qi
6997
1.14M
    4224U,  // MVE_VSTRW32_qi_pre
6998
1.14M
    4864U,  // MVE_VSTRW32_rq
6999
1.14M
    4352U,  // MVE_VSTRW32_rq_u
7000
1.14M
    4096U,  // MVE_VSTRWU32
7001
1.14M
    133760U,  // MVE_VSTRWU32_post
7002
1.14M
    4480U,  // MVE_VSTRWU32_pre
7003
1.14M
    0U, // MVE_VSUB_qr_f16
7004
1.14M
    0U, // MVE_VSUB_qr_f32
7005
1.14M
    0U, // MVE_VSUB_qr_i16
7006
1.14M
    0U, // MVE_VSUB_qr_i32
7007
1.14M
    0U, // MVE_VSUB_qr_i8
7008
1.14M
    0U, // MVE_VSUBf16
7009
1.14M
    0U, // MVE_VSUBf32
7010
1.14M
    0U, // MVE_VSUBi16
7011
1.14M
    0U, // MVE_VSUBi32
7012
1.14M
    0U, // MVE_VSUBi8
7013
1.14M
    21504U, // MVE_WLSTP_16
7014
1.14M
    21504U, // MVE_WLSTP_32
7015
1.14M
    21504U, // MVE_WLSTP_64
7016
1.14M
    21504U, // MVE_WLSTP_8
7017
1.14M
    1792U,  // MVNi
7018
1.14M
    16384U, // MVNr
7019
1.14M
    1920U,  // MVNsi
7020
1.14M
    1152U,  // MVNsr
7021
1.14M
    17920U, // NEON_VMAXNMNDf
7022
1.14M
    17920U, // NEON_VMAXNMNDh
7023
1.14M
    17920U, // NEON_VMAXNMNQf
7024
1.14M
    17920U, // NEON_VMAXNMNQh
7025
1.14M
    17920U, // NEON_VMINNMNDf
7026
1.14M
    17920U, // NEON_VMINNMNDh
7027
1.14M
    17920U, // NEON_VMINNMNQf
7028
1.14M
    17920U, // NEON_VMINNMNQh
7029
1.14M
    1048576U, // ORRri
7030
1.14M
    0U, // ORRrr
7031
1.14M
    1572864U, // ORRrsi
7032
1.14M
    0U, // ORRrsr
7033
1.14M
    201326592U, // PKHBT
7034
1.14M
    234881024U, // PKHTB
7035
1.14M
    0U, // PLDWi12
7036
1.14M
    0U, // PLDWrs
7037
1.14M
    0U, // PLDi12
7038
1.14M
    0U, // PLDrs
7039
1.14M
    0U, // PLIi12
7040
1.14M
    0U, // PLIrs
7041
1.14M
    0U, // QADD
7042
1.14M
    0U, // QADD16
7043
1.14M
    0U, // QADD8
7044
1.14M
    0U, // QASX
7045
1.14M
    0U, // QDADD
7046
1.14M
    0U, // QDSUB
7047
1.14M
    0U, // QSAX
7048
1.14M
    0U, // QSUB
7049
1.14M
    0U, // QSUB16
7050
1.14M
    0U, // QSUB8
7051
1.14M
    16384U, // RBIT
7052
1.14M
    16384U, // REV
7053
1.14M
    16384U, // REV16
7054
1.14M
    16384U, // REVSH
7055
1.14M
    0U, // RFEDA
7056
1.14M
    0U, // RFEDA_UPD
7057
1.14M
    0U, // RFEDB
7058
1.14M
    0U, // RFEDB_UPD
7059
1.14M
    0U, // RFEIA
7060
1.14M
    0U, // RFEIA_UPD
7061
1.14M
    0U, // RFEIB
7062
1.14M
    0U, // RFEIB_UPD
7063
1.14M
    1048576U, // RSBri
7064
1.14M
    0U, // RSBrr
7065
1.14M
    1572864U, // RSBrsi
7066
1.14M
    0U, // RSBrsr
7067
1.14M
    1048576U, // RSCri
7068
1.14M
    0U, // RSCrr
7069
1.14M
    1572864U, // RSCrsi
7070
1.14M
    0U, // RSCrsr
7071
1.14M
    0U, // SADD16
7072
1.14M
    0U, // SADD8
7073
1.14M
    0U, // SASX
7074
1.14M
    0U, // SB
7075
1.14M
    1048576U, // SBCri
7076
1.14M
    0U, // SBCrr
7077
1.14M
    1572864U, // SBCrsi
7078
1.14M
    0U, // SBCrsr
7079
1.14M
    33554432U,  // SBFX
7080
1.14M
    0U, // SDIV
7081
1.14M
    0U, // SEL
7082
1.14M
    0U, // SETEND
7083
1.14M
    0U, // SETPAN
7084
1.14M
    16768U, // SHA1C
7085
1.14M
    2U, // SHA1H
7086
1.14M
    16768U, // SHA1M
7087
1.14M
    16768U, // SHA1P
7088
1.14M
    16768U, // SHA1SU0
7089
1.14M
    2U, // SHA1SU1
7090
1.14M
    16768U, // SHA256H
7091
1.14M
    16768U, // SHA256H2
7092
1.14M
    2U, // SHA256SU0
7093
1.14M
    16768U, // SHA256SU1
7094
1.14M
    0U, // SHADD16
7095
1.14M
    0U, // SHADD8
7096
1.14M
    0U, // SHASX
7097
1.14M
    0U, // SHSAX
7098
1.14M
    0U, // SHSUB16
7099
1.14M
    0U, // SHSUB8
7100
1.14M
    2U, // SMC
7101
1.14M
    33554432U,  // SMLABB
7102
1.14M
    33554432U,  // SMLABT
7103
1.14M
    33554432U,  // SMLAD
7104
1.14M
    33554432U,  // SMLADX
7105
1.14M
    0U, // SMLAL
7106
1.14M
    33554432U,  // SMLALBB
7107
1.14M
    33554432U,  // SMLALBT
7108
1.14M
    33554432U,  // SMLALD
7109
1.14M
    33554432U,  // SMLALDX
7110
1.14M
    33554432U,  // SMLALTB
7111
1.14M
    33554432U,  // SMLALTT
7112
1.14M
    33554432U,  // SMLATB
7113
1.14M
    33554432U,  // SMLATT
7114
1.14M
    33554432U,  // SMLAWB
7115
1.14M
    33554432U,  // SMLAWT
7116
1.14M
    33554432U,  // SMLSD
7117
1.14M
    33554432U,  // SMLSDX
7118
1.14M
    33554432U,  // SMLSLD
7119
1.14M
    33554432U,  // SMLSLDX
7120
1.14M
    33554432U,  // SMMLA
7121
1.14M
    33554432U,  // SMMLAR
7122
1.14M
    33554432U,  // SMMLS
7123
1.14M
    33554432U,  // SMMLSR
7124
1.14M
    0U, // SMMUL
7125
1.14M
    0U, // SMMULR
7126
1.14M
    0U, // SMUAD
7127
1.14M
    0U, // SMUADX
7128
1.14M
    0U, // SMULBB
7129
1.14M
    0U, // SMULBT
7130
1.14M
    33554432U,  // SMULL
7131
1.14M
    0U, // SMULTB
7132
1.14M
    0U, // SMULTT
7133
1.14M
    0U, // SMULWB
7134
1.14M
    0U, // SMULWT
7135
1.14M
    0U, // SMUSD
7136
1.14M
    0U, // SMUSDX
7137
1.14M
    0U, // SRSDA
7138
1.14M
    0U, // SRSDA_UPD
7139
1.14M
    0U, // SRSDB
7140
1.14M
    0U, // SRSDB_UPD
7141
1.14M
    0U, // SRSIA
7142
1.14M
    0U, // SRSIA_UPD
7143
1.14M
    0U, // SRSIB
7144
1.14M
    0U, // SRSIB_UPD
7145
1.14M
    218240U,  // SSAT
7146
1.14M
    21632U, // SSAT16
7147
1.14M
    0U, // SSAX
7148
1.14M
    0U, // SSUB16
7149
1.14M
    0U, // SSUB8
7150
1.14M
    0U, // STC2L_OFFSET
7151
1.14M
    2304U,  // STC2L_OPTION
7152
1.14M
    2432U,  // STC2L_POST
7153
1.14M
    0U, // STC2L_PRE
7154
1.14M
    0U, // STC2_OFFSET
7155
1.14M
    2304U,  // STC2_OPTION
7156
1.14M
    2432U,  // STC2_POST
7157
1.14M
    0U, // STC2_PRE
7158
1.14M
    2582U,  // STCL_OFFSET
7159
1.14M
    4721302U, // STCL_OPTION
7160
1.14M
    5245590U, // STCL_POST
7161
1.14M
    2838U,  // STCL_PRE
7162
1.14M
    2582U,  // STC_OFFSET
7163
1.14M
    4721302U, // STC_OPTION
7164
1.14M
    5245590U, // STC_POST
7165
1.14M
    2838U,  // STC_PRE
7166
1.14M
    128U, // STL
7167
1.14M
    128U, // STLB
7168
1.14M
    11010048U,  // STLEX
7169
1.14M
    11010048U,  // STLEXB
7170
1.14M
    5376U,  // STLEXD
7171
1.14M
    11010048U,  // STLEXH
7172
1.14M
    128U, // STLH
7173
1.14M
    18560U, // STMDA
7174
1.14M
    532U, // STMDA_UPD
7175
1.14M
    18560U, // STMDB
7176
1.14M
    532U, // STMDB_UPD
7177
1.14M
    18560U, // STMIA
7178
1.14M
    532U, // STMIA_UPD
7179
1.14M
    18560U, // STMIB
7180
1.14M
    532U, // STMIB_UPD
7181
1.14M
    5769856U, // STRBT_POST_IMM
7182
1.14M
    5769856U, // STRBT_POST_REG
7183
1.14M
    5769856U, // STRB_POST_IMM
7184
1.14M
    5769856U, // STRB_POST_REG
7185
1.14M
    2944U,  // STRB_PRE_IMM
7186
1.14M
    3072U,  // STRB_PRE_REG
7187
1.14M
    3200U,  // STRBi12
7188
1.14M
    3328U,  // STRBrs
7189
1.14M
    6291456U, // STRD
7190
1.14M
    40371712U,  // STRD_POST
7191
1.14M
    7341568U, // STRD_PRE
7192
1.14M
    11010048U,  // STREX
7193
1.14M
    11010048U,  // STREXB
7194
1.14M
    5376U,  // STREXD
7195
1.14M
    11010048U,  // STREXH
7196
1.14M
    3456U,  // STRH
7197
1.14M
    7867008U, // STRHTi
7198
1.14M
    8391296U, // STRHTr
7199
1.14M
    8915584U, // STRH_POST
7200
1.14M
    3584U,  // STRH_PRE
7201
1.14M
    5769856U, // STRT_POST_IMM
7202
1.14M
    5769856U, // STRT_POST_REG
7203
1.14M
    5769856U, // STR_POST_IMM
7204
1.14M
    5769856U, // STR_POST_REG
7205
1.14M
    2944U,  // STR_PRE_IMM
7206
1.14M
    3072U,  // STR_PRE_REG
7207
1.14M
    3200U,  // STRi12
7208
1.14M
    3328U,  // STRrs
7209
1.14M
    1048576U, // SUBri
7210
1.14M
    0U, // SUBrr
7211
1.14M
    1572864U, // SUBrsi
7212
1.14M
    0U, // SUBrsr
7213
1.14M
    2U, // SVC
7214
1.14M
    11010048U,  // SWP
7215
1.14M
    11010048U,  // SWPB
7216
1.14M
    268435456U, // SXTAB
7217
1.14M
    268435456U, // SXTAB16
7218
1.14M
    268435456U, // SXTAH
7219
1.14M
    229376U,  // SXTB
7220
1.14M
    229376U,  // SXTB16
7221
1.14M
    229376U,  // SXTH
7222
1.14M
    1792U,  // TEQri
7223
1.14M
    16384U, // TEQrr
7224
1.14M
    1920U,  // TEQrsi
7225
1.14M
    1152U,  // TEQrsr
7226
1.14M
    0U, // TRAP
7227
1.14M
    0U, // TRAPNaCl
7228
1.14M
    0U, // TSB
7229
1.14M
    1792U,  // TSTri
7230
1.14M
    16384U, // TSTrr
7231
1.14M
    1920U,  // TSTrsi
7232
1.14M
    1152U,  // TSTrsr
7233
1.14M
    0U, // UADD16
7234
1.14M
    0U, // UADD8
7235
1.14M
    0U, // UASX
7236
1.14M
    33554432U,  // UBFX
7237
1.14M
    0U, // UDF
7238
1.14M
    0U, // UDIV
7239
1.14M
    0U, // UHADD16
7240
1.14M
    0U, // UHADD8
7241
1.14M
    0U, // UHASX
7242
1.14M
    0U, // UHSAX
7243
1.14M
    0U, // UHSUB16
7244
1.14M
    0U, // UHSUB8
7245
1.14M
    33554432U,  // UMAAL
7246
1.14M
    0U, // UMLAL
7247
1.14M
    33554432U,  // UMULL
7248
1.14M
    0U, // UQADD16
7249
1.14M
    0U, // UQADD8
7250
1.14M
    0U, // UQASX
7251
1.14M
    0U, // UQSAX
7252
1.14M
    0U, // UQSUB16
7253
1.14M
    0U, // UQSUB8
7254
1.14M
    0U, // USAD8
7255
1.14M
    33554432U,  // USADA8
7256
1.14M
    301989888U, // USAT
7257
1.14M
    0U, // USAT16
7258
1.14M
    0U, // USAX
7259
1.14M
    0U, // USUB16
7260
1.14M
    0U, // USUB8
7261
1.14M
    268435456U, // UXTAB
7262
1.14M
    268435456U, // UXTAB16
7263
1.14M
    268435456U, // UXTAH
7264
1.14M
    229376U,  // UXTB
7265
1.14M
    229376U,  // UXTB16
7266
1.14M
    229376U,  // UXTH
7267
1.14M
    3671552U, // VABALsv2i64
7268
1.14M
    3671552U, // VABALsv4i32
7269
1.14M
    3671552U, // VABALsv8i16
7270
1.14M
    3671552U, // VABALuv2i64
7271
1.14M
    3671552U, // VABALuv4i32
7272
1.14M
    3671552U, // VABALuv8i16
7273
1.14M
    3671552U, // VABAsv16i8
7274
1.14M
    3671552U, // VABAsv2i32
7275
1.14M
    3671552U, // VABAsv4i16
7276
1.14M
    3671552U, // VABAsv4i32
7277
1.14M
    3671552U, // VABAsv8i16
7278
1.14M
    3671552U, // VABAsv8i8
7279
1.14M
    3671552U, // VABAuv16i8
7280
1.14M
    3671552U, // VABAuv2i32
7281
1.14M
    3671552U, // VABAuv4i16
7282
1.14M
    3671552U, // VABAuv4i32
7283
1.14M
    3671552U, // VABAuv8i16
7284
1.14M
    3671552U, // VABAuv8i8
7285
1.14M
    0U, // VABDLsv2i64
7286
1.14M
    0U, // VABDLsv4i32
7287
1.14M
    0U, // VABDLsv8i16
7288
1.14M
    0U, // VABDLuv2i64
7289
1.14M
    0U, // VABDLuv4i32
7290
1.14M
    0U, // VABDLuv8i16
7291
1.14M
    0U, // VABDfd
7292
1.14M
    0U, // VABDfq
7293
1.14M
    0U, // VABDhd
7294
1.14M
    0U, // VABDhq
7295
1.14M
    0U, // VABDsv16i8
7296
1.14M
    0U, // VABDsv2i32
7297
1.14M
    0U, // VABDsv4i16
7298
1.14M
    0U, // VABDsv4i32
7299
1.14M
    0U, // VABDsv8i16
7300
1.14M
    0U, // VABDsv8i8
7301
1.14M
    0U, // VABDuv16i8
7302
1.14M
    0U, // VABDuv2i32
7303
1.14M
    0U, // VABDuv4i16
7304
1.14M
    0U, // VABDuv4i32
7305
1.14M
    0U, // VABDuv8i16
7306
1.14M
    0U, // VABDuv8i8
7307
1.14M
    528U, // VABSD
7308
1.14M
    16384U, // VABSH
7309
1.14M
    16384U, // VABSS
7310
1.14M
    16384U, // VABSfd
7311
1.14M
    16384U, // VABSfq
7312
1.14M
    16384U, // VABShd
7313
1.14M
    16384U, // VABShq
7314
1.14M
    16384U, // VABSv16i8
7315
1.14M
    16384U, // VABSv2i32
7316
1.14M
    16384U, // VABSv4i16
7317
1.14M
    16384U, // VABSv4i32
7318
1.14M
    16384U, // VABSv8i16
7319
1.14M
    16384U, // VABSv8i8
7320
1.14M
    0U, // VACGEfd
7321
1.14M
    0U, // VACGEfq
7322
1.14M
    0U, // VACGEhd
7323
1.14M
    0U, // VACGEhq
7324
1.14M
    0U, // VACGTfd
7325
1.14M
    0U, // VACGTfq
7326
1.14M
    0U, // VACGThd
7327
1.14M
    0U, // VACGThq
7328
1.14M
    2720528U, // VADDD
7329
1.14M
    0U, // VADDH
7330
1.14M
    17920U, // VADDHNv2i32
7331
1.14M
    0U, // VADDHNv4i16
7332
1.14M
    0U, // VADDHNv8i8
7333
1.14M
    0U, // VADDLsv2i64
7334
1.14M
    0U, // VADDLsv4i32
7335
1.14M
    0U, // VADDLsv8i16
7336
1.14M
    0U, // VADDLuv2i64
7337
1.14M
    0U, // VADDLuv4i32
7338
1.14M
    0U, // VADDLuv8i16
7339
1.14M
    0U, // VADDS
7340
1.14M
    0U, // VADDWsv2i64
7341
1.14M
    0U, // VADDWsv4i32
7342
1.14M
    0U, // VADDWsv8i16
7343
1.14M
    0U, // VADDWuv2i64
7344
1.14M
    0U, // VADDWuv4i32
7345
1.14M
    0U, // VADDWuv8i16
7346
1.14M
    0U, // VADDfd
7347
1.14M
    0U, // VADDfq
7348
1.14M
    0U, // VADDhd
7349
1.14M
    0U, // VADDhq
7350
1.14M
    0U, // VADDv16i8
7351
1.14M
    17920U, // VADDv1i64
7352
1.14M
    0U, // VADDv2i32
7353
1.14M
    17920U, // VADDv2i64
7354
1.14M
    0U, // VADDv4i16
7355
1.14M
    0U, // VADDv4i32
7356
1.14M
    0U, // VADDv8i16
7357
1.14M
    0U, // VADDv8i8
7358
1.14M
    0U, // VANDd
7359
1.14M
    0U, // VANDq
7360
1.14M
    2U, // VBF16MALBQ
7361
1.14M
    520U, // VBF16MALBQI
7362
1.14M
    2U, // VBF16MALTQ
7363
1.14M
    520U, // VBF16MALTQI
7364
1.14M
    0U, // VBICd
7365
1.14M
    4992U,  // VBICiv2i32
7366
1.14M
    4992U,  // VBICiv4i16
7367
1.14M
    4992U,  // VBICiv4i32
7368
1.14M
    4992U,  // VBICiv8i16
7369
1.14M
    0U, // VBICq
7370
1.14M
    3671552U, // VBIFd
7371
1.14M
    3671552U, // VBIFq
7372
1.14M
    3671552U, // VBITd
7373
1.14M
    3671552U, // VBITq
7374
1.14M
    3671552U, // VBSLd
7375
1.14M
    3671552U, // VBSLq
7376
1.14M
    0U, // VBSPd
7377
1.14M
    0U, // VBSPq
7378
1.14M
    11535872U,  // VCADDv2f32
7379
1.14M
    11535872U,  // VCADDv4f16
7380
1.14M
    11535872U,  // VCADDv4f32
7381
1.14M
    11535872U,  // VCADDv8f16
7382
1.14M
    0U, // VCEQfd
7383
1.14M
    0U, // VCEQfq
7384
1.14M
    0U, // VCEQhd
7385
1.14M
    0U, // VCEQhq
7386
1.14M
    0U, // VCEQv16i8
7387
1.14M
    0U, // VCEQv2i32
7388
1.14M
    0U, // VCEQv4i16
7389
1.14M
    0U, // VCEQv4i32
7390
1.14M
    0U, // VCEQv8i16
7391
1.14M
    0U, // VCEQv8i8
7392
1.14M
    245760U,  // VCEQzv16i8
7393
1.14M
    245760U,  // VCEQzv2f32
7394
1.14M
    245760U,  // VCEQzv2i32
7395
1.14M
    245760U,  // VCEQzv4f16
7396
1.14M
    245760U,  // VCEQzv4f32
7397
1.14M
    245760U,  // VCEQzv4i16
7398
1.14M
    245760U,  // VCEQzv4i32
7399
1.14M
    245760U,  // VCEQzv8f16
7400
1.14M
    245760U,  // VCEQzv8i16
7401
1.14M
    245760U,  // VCEQzv8i8
7402
1.14M
    0U, // VCGEfd
7403
1.14M
    0U, // VCGEfq
7404
1.14M
    0U, // VCGEhd
7405
1.14M
    0U, // VCGEhq
7406
1.14M
    0U, // VCGEsv16i8
7407
1.14M
    0U, // VCGEsv2i32
7408
1.14M
    0U, // VCGEsv4i16
7409
1.14M
    0U, // VCGEsv4i32
7410
1.14M
    0U, // VCGEsv8i16
7411
1.14M
    0U, // VCGEsv8i8
7412
1.14M
    0U, // VCGEuv16i8
7413
1.14M
    0U, // VCGEuv2i32
7414
1.14M
    0U, // VCGEuv4i16
7415
1.14M
    0U, // VCGEuv4i32
7416
1.14M
    0U, // VCGEuv8i16
7417
1.14M
    0U, // VCGEuv8i8
7418
1.14M
    245760U,  // VCGEzv16i8
7419
1.14M
    245760U,  // VCGEzv2f32
7420
1.14M
    245760U,  // VCGEzv2i32
7421
1.14M
    245760U,  // VCGEzv4f16
7422
1.14M
    245760U,  // VCGEzv4f32
7423
1.14M
    245760U,  // VCGEzv4i16
7424
1.14M
    245760U,  // VCGEzv4i32
7425
1.14M
    245760U,  // VCGEzv8f16
7426
1.14M
    245760U,  // VCGEzv8i16
7427
1.14M
    245760U,  // VCGEzv8i8
7428
1.14M
    0U, // VCGTfd
7429
1.14M
    0U, // VCGTfq
7430
1.14M
    0U, // VCGThd
7431
1.14M
    0U, // VCGThq
7432
1.14M
    0U, // VCGTsv16i8
7433
1.14M
    0U, // VCGTsv2i32
7434
1.14M
    0U, // VCGTsv4i16
7435
1.14M
    0U, // VCGTsv4i32
7436
1.14M
    0U, // VCGTsv8i16
7437
1.14M
    0U, // VCGTsv8i8
7438
1.14M
    0U, // VCGTuv16i8
7439
1.14M
    0U, // VCGTuv2i32
7440
1.14M
    0U, // VCGTuv4i16
7441
1.14M
    0U, // VCGTuv4i32
7442
1.14M
    0U, // VCGTuv8i16
7443
1.14M
    0U, // VCGTuv8i8
7444
1.14M
    245760U,  // VCGTzv16i8
7445
1.14M
    245760U,  // VCGTzv2f32
7446
1.14M
    245760U,  // VCGTzv2i32
7447
1.14M
    245760U,  // VCGTzv4f16
7448
1.14M
    245760U,  // VCGTzv4f32
7449
1.14M
    245760U,  // VCGTzv4i16
7450
1.14M
    245760U,  // VCGTzv4i32
7451
1.14M
    245760U,  // VCGTzv8f16
7452
1.14M
    245760U,  // VCGTzv8i16
7453
1.14M
    245760U,  // VCGTzv8i8
7454
1.14M
    245760U,  // VCLEzv16i8
7455
1.14M
    245760U,  // VCLEzv2f32
7456
1.14M
    245760U,  // VCLEzv2i32
7457
1.14M
    245760U,  // VCLEzv4f16
7458
1.14M
    245760U,  // VCLEzv4f32
7459
1.14M
    245760U,  // VCLEzv4i16
7460
1.14M
    245760U,  // VCLEzv4i32
7461
1.14M
    245760U,  // VCLEzv8f16
7462
1.14M
    245760U,  // VCLEzv8i16
7463
1.14M
    245760U,  // VCLEzv8i8
7464
1.14M
    16384U, // VCLSv16i8
7465
1.14M
    16384U, // VCLSv2i32
7466
1.14M
    16384U, // VCLSv4i16
7467
1.14M
    16384U, // VCLSv4i32
7468
1.14M
    16384U, // VCLSv8i16
7469
1.14M
    16384U, // VCLSv8i8
7470
1.14M
    245760U,  // VCLTzv16i8
7471
1.14M
    245760U,  // VCLTzv2f32
7472
1.14M
    245760U,  // VCLTzv2i32
7473
1.14M
    245760U,  // VCLTzv4f16
7474
1.14M
    245760U,  // VCLTzv4f32
7475
1.14M
    245760U,  // VCLTzv4i16
7476
1.14M
    245760U,  // VCLTzv4i32
7477
1.14M
    245760U,  // VCLTzv8f16
7478
1.14M
    245760U,  // VCLTzv8i16
7479
1.14M
    245760U,  // VCLTzv8i8
7480
1.14M
    16384U, // VCLZv16i8
7481
1.14M
    16384U, // VCLZv2i32
7482
1.14M
    16384U, // VCLZv4i16
7483
1.14M
    16384U, // VCLZv4i32
7484
1.14M
    16384U, // VCLZv8i16
7485
1.14M
    16384U, // VCLZv8i8
7486
1.14M
    12059008U,  // VCMLAv2f32
7487
1.14M
    262528U,  // VCMLAv2f32_indexed
7488
1.14M
    12059008U,  // VCMLAv4f16
7489
1.14M
    262528U,  // VCMLAv4f16_indexed
7490
1.14M
    12059008U,  // VCMLAv4f32
7491
1.14M
    262528U,  // VCMLAv4f32_indexed
7492
1.14M
    12059008U,  // VCMLAv8f16
7493
1.14M
    262528U,  // VCMLAv8f16_indexed
7494
1.14M
    528U, // VCMPD
7495
1.14M
    528U, // VCMPED
7496
1.14M
    16384U, // VCMPEH
7497
1.14M
    16384U, // VCMPES
7498
1.14M
    0U, // VCMPEZD
7499
1.14M
    34U,  // VCMPEZH
7500
1.14M
    34U,  // VCMPEZS
7501
1.14M
    16384U, // VCMPH
7502
1.14M
    16384U, // VCMPS
7503
1.14M
    0U, // VCMPZD
7504
1.14M
    34U,  // VCMPZH
7505
1.14M
    34U,  // VCMPZS
7506
1.14M
    16384U, // VCNTd
7507
1.14M
    16384U, // VCNTq
7508
1.14M
    2U, // VCVTANSDf
7509
1.14M
    2U, // VCVTANSDh
7510
1.14M
    2U, // VCVTANSQf
7511
1.14M
    2U, // VCVTANSQh
7512
1.14M
    2U, // VCVTANUDf
7513
1.14M
    2U, // VCVTANUDh
7514
1.14M
    2U, // VCVTANUQf
7515
1.14M
    2U, // VCVTANUQh
7516
1.14M
    2U, // VCVTASD
7517
1.14M
    2U, // VCVTASH
7518
1.14M
    2U, // VCVTASS
7519
1.14M
    2U, // VCVTAUD
7520
1.14M
    2U, // VCVTAUH
7521
1.14M
    2U, // VCVTAUS
7522
1.14M
    0U, // VCVTBDH
7523
1.14M
    0U, // VCVTBHD
7524
1.14M
    0U, // VCVTBHS
7525
1.14M
    2U, // VCVTBSH
7526
1.14M
    0U, // VCVTDS
7527
1.14M
    2U, // VCVTMNSDf
7528
1.14M
    2U, // VCVTMNSDh
7529
1.14M
    2U, // VCVTMNSQf
7530
1.14M
    2U, // VCVTMNSQh
7531
1.14M
    2U, // VCVTMNUDf
7532
1.14M
    2U, // VCVTMNUDh
7533
1.14M
    2U, // VCVTMNUQf
7534
1.14M
    2U, // VCVTMNUQh
7535
1.14M
    2U, // VCVTMSD
7536
1.14M
    2U, // VCVTMSH
7537
1.14M
    2U, // VCVTMSS
7538
1.14M
    2U, // VCVTMUD
7539
1.14M
    2U, // VCVTMUH
7540
1.14M
    2U, // VCVTMUS
7541
1.14M
    2U, // VCVTNNSDf
7542
1.14M
    2U, // VCVTNNSDh
7543
1.14M
    2U, // VCVTNNSQf
7544
1.14M
    2U, // VCVTNNSQh
7545
1.14M
    2U, // VCVTNNUDf
7546
1.14M
    2U, // VCVTNNUDh
7547
1.14M
    2U, // VCVTNNUQf
7548
1.14M
    2U, // VCVTNNUQh
7549
1.14M
    2U, // VCVTNSD
7550
1.14M
    2U, // VCVTNSH
7551
1.14M
    2U, // VCVTNSS
7552
1.14M
    2U, // VCVTNUD
7553
1.14M
    2U, // VCVTNUH
7554
1.14M
    2U, // VCVTNUS
7555
1.14M
    2U, // VCVTPNSDf
7556
1.14M
    2U, // VCVTPNSDh
7557
1.14M
    2U, // VCVTPNSQf
7558
1.14M
    2U, // VCVTPNSQh
7559
1.14M
    2U, // VCVTPNUDf
7560
1.14M
    2U, // VCVTPNUDh
7561
1.14M
    2U, // VCVTPNUQf
7562
1.14M
    2U, // VCVTPNUQh
7563
1.14M
    2U, // VCVTPSD
7564
1.14M
    2U, // VCVTPSH
7565
1.14M
    2U, // VCVTPSS
7566
1.14M
    2U, // VCVTPUD
7567
1.14M
    2U, // VCVTPUH
7568
1.14M
    2U, // VCVTPUS
7569
1.14M
    0U, // VCVTSD
7570
1.14M
    0U, // VCVTTDH
7571
1.14M
    0U, // VCVTTHD
7572
1.14M
    0U, // VCVTTHS
7573
1.14M
    2U, // VCVTTSH
7574
1.14M
    2U, // VCVTf2h
7575
1.14M
    0U, // VCVTf2sd
7576
1.14M
    0U, // VCVTf2sq
7577
1.14M
    0U, // VCVTf2ud
7578
1.14M
    0U, // VCVTf2uq
7579
1.14M
    536U, // VCVTf2xsd
7580
1.14M
    536U, // VCVTf2xsq
7581
1.14M
    536U, // VCVTf2xud
7582
1.14M
    536U, // VCVTf2xuq
7583
1.14M
    0U, // VCVTh2f
7584
1.14M
    0U, // VCVTh2sd
7585
1.14M
    0U, // VCVTh2sq
7586
1.14M
    0U, // VCVTh2ud
7587
1.14M
    0U, // VCVTh2uq
7588
1.14M
    536U, // VCVTh2xsd
7589
1.14M
    536U, // VCVTh2xsq
7590
1.14M
    536U, // VCVTh2xud
7591
1.14M
    536U, // VCVTh2xuq
7592
1.14M
    0U, // VCVTs2fd
7593
1.14M
    0U, // VCVTs2fq
7594
1.14M
    0U, // VCVTs2hd
7595
1.14M
    0U, // VCVTs2hq
7596
1.14M
    0U, // VCVTu2fd
7597
1.14M
    0U, // VCVTu2fq
7598
1.14M
    0U, // VCVTu2hd
7599
1.14M
    0U, // VCVTu2hq
7600
1.14M
    536U, // VCVTxs2fd
7601
1.14M
    536U, // VCVTxs2fq
7602
1.14M
    536U, // VCVTxs2hd
7603
1.14M
    536U, // VCVTxs2hq
7604
1.14M
    536U, // VCVTxu2fd
7605
1.14M
    536U, // VCVTxu2fq
7606
1.14M
    536U, // VCVTxu2hd
7607
1.14M
    536U, // VCVTxu2hq
7608
1.14M
    2720528U, // VDIVD
7609
1.14M
    0U, // VDIVH
7610
1.14M
    0U, // VDIVS
7611
1.14M
    16384U, // VDUP16d
7612
1.14M
    16384U, // VDUP16q
7613
1.14M
    16384U, // VDUP32d
7614
1.14M
    16384U, // VDUP32q
7615
1.14M
    16384U, // VDUP8d
7616
1.14M
    16384U, // VDUP8q
7617
1.14M
    147456U,  // VDUPLN16d
7618
1.14M
    147456U,  // VDUPLN16q
7619
1.14M
    147456U,  // VDUPLN32d
7620
1.14M
    147456U,  // VDUPLN32q
7621
1.14M
    147456U,  // VDUPLN8d
7622
1.14M
    147456U,  // VDUPLN8q
7623
1.14M
    0U, // VEORd
7624
1.14M
    0U, // VEORq
7625
1.14M
    33554432U,  // VEXTd16
7626
1.14M
    33554432U,  // VEXTd32
7627
1.14M
    33554432U,  // VEXTd8
7628
1.14M
    33554432U,  // VEXTq16
7629
1.14M
    33554432U,  // VEXTq32
7630
1.14M
    33554432U,  // VEXTq64
7631
1.14M
    33554432U,  // VEXTq8
7632
1.14M
    49944U, // VFMAD
7633
1.14M
    3671552U, // VFMAH
7634
1.14M
    17920U, // VFMALD
7635
1.14M
    280064U,  // VFMALDI
7636
1.14M
    17920U, // VFMALQ
7637
1.14M
    280064U,  // VFMALQI
7638
1.14M
    3671552U, // VFMAS
7639
1.14M
    3671552U, // VFMAfd
7640
1.14M
    3671552U, // VFMAfq
7641
1.14M
    3671552U, // VFMAhd
7642
1.14M
    3671552U, // VFMAhq
7643
1.14M
    49944U, // VFMSD
7644
1.14M
    3671552U, // VFMSH
7645
1.14M
    17920U, // VFMSLD
7646
1.14M
    280064U,  // VFMSLDI
7647
1.14M
    17920U, // VFMSLQ
7648
1.14M
    280064U,  // VFMSLQI
7649
1.14M
    3671552U, // VFMSS
7650
1.14M
    3671552U, // VFMSfd
7651
1.14M
    3671552U, // VFMSfq
7652
1.14M
    3671552U, // VFMShd
7653
1.14M
    3671552U, // VFMShq
7654
1.14M
    49944U, // VFNMAD
7655
1.14M
    3671552U, // VFNMAH
7656
1.14M
    3671552U, // VFNMAS
7657
1.14M
    49944U, // VFNMSD
7658
1.14M
    3671552U, // VFNMSH
7659
1.14M
    3671552U, // VFNMSS
7660
1.14M
    17920U, // VFP_VMAXNMD
7661
1.14M
    17920U, // VFP_VMAXNMH
7662
1.14M
    17920U, // VFP_VMAXNMS
7663
1.14M
    17920U, // VFP_VMINNMD
7664
1.14M
    17920U, // VFP_VMINNMH
7665
1.14M
    17920U, // VFP_VMINNMS
7666
1.14M
    147456U,  // VGETLNi32
7667
1.14M
    147456U,  // VGETLNs16
7668
1.14M
    147456U,  // VGETLNs8
7669
1.14M
    147456U,  // VGETLNu16
7670
1.14M
    147456U,  // VGETLNu8
7671
1.14M
    0U, // VHADDsv16i8
7672
1.14M
    0U, // VHADDsv2i32
7673
1.14M
    0U, // VHADDsv4i16
7674
1.14M
    0U, // VHADDsv4i32
7675
1.14M
    0U, // VHADDsv8i16
7676
1.14M
    0U, // VHADDsv8i8
7677
1.14M
    0U, // VHADDuv16i8
7678
1.14M
    0U, // VHADDuv2i32
7679
1.14M
    0U, // VHADDuv4i16
7680
1.14M
    0U, // VHADDuv4i32
7681
1.14M
    0U, // VHADDuv8i16
7682
1.14M
    0U, // VHADDuv8i8
7683
1.14M
    0U, // VHSUBsv16i8
7684
1.14M
    0U, // VHSUBsv2i32
7685
1.14M
    0U, // VHSUBsv4i16
7686
1.14M
    0U, // VHSUBsv4i32
7687
1.14M
    0U, // VHSUBsv8i16
7688
1.14M
    0U, // VHSUBsv8i8
7689
1.14M
    0U, // VHSUBuv16i8
7690
1.14M
    0U, // VHSUBuv2i32
7691
1.14M
    0U, // VHSUBuv4i16
7692
1.14M
    0U, // VHSUBuv4i32
7693
1.14M
    0U, // VHSUBuv8i16
7694
1.14M
    0U, // VHSUBuv8i8
7695
1.14M
    2U, // VINSH
7696
1.14M
    0U, // VJCVT
7697
1.14M
    518U, // VLD1DUPd16
7698
1.14M
    676U, // VLD1DUPd16wb_fixed
7699
1.14M
    2687780U, // VLD1DUPd16wb_register
7700
1.14M
    518U, // VLD1DUPd32
7701
1.14M
    676U, // VLD1DUPd32wb_fixed
7702
1.14M
    2687780U, // VLD1DUPd32wb_register
7703
1.14M
    518U, // VLD1DUPd8
7704
1.14M
    676U, // VLD1DUPd8wb_fixed
7705
1.14M
    2687780U, // VLD1DUPd8wb_register
7706
1.14M
    518U, // VLD1DUPq16
7707
1.14M
    676U, // VLD1DUPq16wb_fixed
7708
1.14M
    2687780U, // VLD1DUPq16wb_register
7709
1.14M
    518U, // VLD1DUPq32
7710
1.14M
    676U, // VLD1DUPq32wb_fixed
7711
1.14M
    2687780U, // VLD1DUPq32wb_register
7712
1.14M
    518U, // VLD1DUPq8
7713
1.14M
    676U, // VLD1DUPq8wb_fixed
7714
1.14M
    2687780U, // VLD1DUPq8wb_register
7715
1.14M
    12883366U,  // VLD1LNd16
7716
1.14M
    13407782U,  // VLD1LNd16_UPD
7717
1.14M
    12883366U,  // VLD1LNd32
7718
1.14M
    13407782U,  // VLD1LNd32_UPD
7719
1.14M
    12883366U,  // VLD1LNd8
7720
1.14M
    13407782U,  // VLD1LNd8_UPD
7721
1.14M
    0U, // VLD1LNq16Pseudo
7722
1.14M
    0U, // VLD1LNq16Pseudo_UPD
7723
1.14M
    0U, // VLD1LNq32Pseudo
7724
1.14M
    0U, // VLD1LNq32Pseudo_UPD
7725
1.14M
    0U, // VLD1LNq8Pseudo
7726
1.14M
    0U, // VLD1LNq8Pseudo_UPD
7727
1.14M
    518U, // VLD1d16
7728
1.14M
    518U, // VLD1d16Q
7729
1.14M
    0U, // VLD1d16QPseudo
7730
1.14M
    0U, // VLD1d16QPseudoWB_fixed
7731
1.14M
    0U, // VLD1d16QPseudoWB_register
7732
1.14M
    676U, // VLD1d16Qwb_fixed
7733
1.14M
    2687780U, // VLD1d16Qwb_register
7734
1.14M
    518U, // VLD1d16T
7735
1.14M
    0U, // VLD1d16TPseudo
7736
1.14M
    0U, // VLD1d16TPseudoWB_fixed
7737
1.14M
    0U, // VLD1d16TPseudoWB_register
7738
1.14M
    676U, // VLD1d16Twb_fixed
7739
1.14M
    2687780U, // VLD1d16Twb_register
7740
1.14M
    676U, // VLD1d16wb_fixed
7741
1.14M
    2687780U, // VLD1d16wb_register
7742
1.14M
    518U, // VLD1d32
7743
1.14M
    518U, // VLD1d32Q
7744
1.14M
    0U, // VLD1d32QPseudo
7745
1.14M
    0U, // VLD1d32QPseudoWB_fixed
7746
1.14M
    0U, // VLD1d32QPseudoWB_register
7747
1.14M
    676U, // VLD1d32Qwb_fixed
7748
1.14M
    2687780U, // VLD1d32Qwb_register
7749
1.14M
    518U, // VLD1d32T
7750
1.14M
    0U, // VLD1d32TPseudo
7751
1.14M
    0U, // VLD1d32TPseudoWB_fixed
7752
1.14M
    0U, // VLD1d32TPseudoWB_register
7753
1.14M
    676U, // VLD1d32Twb_fixed
7754
1.14M
    2687780U, // VLD1d32Twb_register
7755
1.14M
    676U, // VLD1d32wb_fixed
7756
1.14M
    2687780U, // VLD1d32wb_register
7757
1.14M
    518U, // VLD1d64
7758
1.14M
    518U, // VLD1d64Q
7759
1.14M
    0U, // VLD1d64QPseudo
7760
1.14M
    0U, // VLD1d64QPseudoWB_fixed
7761
1.14M
    0U, // VLD1d64QPseudoWB_register
7762
1.14M
    676U, // VLD1d64Qwb_fixed
7763
1.14M
    2687780U, // VLD1d64Qwb_register
7764
1.14M
    518U, // VLD1d64T
7765
1.14M
    0U, // VLD1d64TPseudo
7766
1.14M
    0U, // VLD1d64TPseudoWB_fixed
7767
1.14M
    0U, // VLD1d64TPseudoWB_register
7768
1.14M
    676U, // VLD1d64Twb_fixed
7769
1.14M
    2687780U, // VLD1d64Twb_register
7770
1.14M
    676U, // VLD1d64wb_fixed
7771
1.14M
    2687780U, // VLD1d64wb_register
7772
1.14M
    518U, // VLD1d8
7773
1.14M
    518U, // VLD1d8Q
7774
1.14M
    0U, // VLD1d8QPseudo
7775
1.14M
    0U, // VLD1d8QPseudoWB_fixed
7776
1.14M
    0U, // VLD1d8QPseudoWB_register
7777
1.14M
    676U, // VLD1d8Qwb_fixed
7778
1.14M
    2687780U, // VLD1d8Qwb_register
7779
1.14M
    518U, // VLD1d8T
7780
1.14M
    0U, // VLD1d8TPseudo
7781
1.14M
    0U, // VLD1d8TPseudoWB_fixed
7782
1.14M
    0U, // VLD1d8TPseudoWB_register
7783
1.14M
    676U, // VLD1d8Twb_fixed
7784
1.14M
    2687780U, // VLD1d8Twb_register
7785
1.14M
    676U, // VLD1d8wb_fixed
7786
1.14M
    2687780U, // VLD1d8wb_register
7787
1.14M
    518U, // VLD1q16
7788
1.14M
    0U, // VLD1q16HighQPseudo
7789
1.14M
    0U, // VLD1q16HighQPseudo_UPD
7790
1.14M
    0U, // VLD1q16HighTPseudo
7791
1.14M
    0U, // VLD1q16HighTPseudo_UPD
7792
1.14M
    0U, // VLD1q16LowQPseudo_UPD
7793
1.14M
    0U, // VLD1q16LowTPseudo_UPD
7794
1.14M
    676U, // VLD1q16wb_fixed
7795
1.14M
    2687780U, // VLD1q16wb_register
7796
1.14M
    518U, // VLD1q32
7797
1.14M
    0U, // VLD1q32HighQPseudo
7798
1.14M
    0U, // VLD1q32HighQPseudo_UPD
7799
1.14M
    0U, // VLD1q32HighTPseudo
7800
1.14M
    0U, // VLD1q32HighTPseudo_UPD
7801
1.14M
    0U, // VLD1q32LowQPseudo_UPD
7802
1.14M
    0U, // VLD1q32LowTPseudo_UPD
7803
1.14M
    676U, // VLD1q32wb_fixed
7804
1.14M
    2687780U, // VLD1q32wb_register
7805
1.14M
    518U, // VLD1q64
7806
1.14M
    0U, // VLD1q64HighQPseudo
7807
1.14M
    0U, // VLD1q64HighQPseudo_UPD
7808
1.14M
    0U, // VLD1q64HighTPseudo
7809
1.14M
    0U, // VLD1q64HighTPseudo_UPD
7810
1.14M
    0U, // VLD1q64LowQPseudo_UPD
7811
1.14M
    0U, // VLD1q64LowTPseudo_UPD
7812
1.14M
    676U, // VLD1q64wb_fixed
7813
1.14M
    2687780U, // VLD1q64wb_register
7814
1.14M
    518U, // VLD1q8
7815
1.14M
    0U, // VLD1q8HighQPseudo
7816
1.14M
    0U, // VLD1q8HighQPseudo_UPD
7817
1.14M
    0U, // VLD1q8HighTPseudo
7818
1.14M
    0U, // VLD1q8HighTPseudo_UPD
7819
1.14M
    0U, // VLD1q8LowQPseudo_UPD
7820
1.14M
    0U, // VLD1q8LowTPseudo_UPD
7821
1.14M
    676U, // VLD1q8wb_fixed
7822
1.14M
    2687780U, // VLD1q8wb_register
7823
1.14M
    518U, // VLD2DUPd16
7824
1.14M
    676U, // VLD2DUPd16wb_fixed
7825
1.14M
    2687780U, // VLD2DUPd16wb_register
7826
1.14M
    518U, // VLD2DUPd16x2
7827
1.14M
    676U, // VLD2DUPd16x2wb_fixed
7828
1.14M
    2687780U, // VLD2DUPd16x2wb_register
7829
1.14M
    518U, // VLD2DUPd32
7830
1.14M
    676U, // VLD2DUPd32wb_fixed
7831
1.14M
    2687780U, // VLD2DUPd32wb_register
7832
1.14M
    518U, // VLD2DUPd32x2
7833
1.14M
    676U, // VLD2DUPd32x2wb_fixed
7834
1.14M
    2687780U, // VLD2DUPd32x2wb_register
7835
1.14M
    518U, // VLD2DUPd8
7836
1.14M
    676U, // VLD2DUPd8wb_fixed
7837
1.14M
    2687780U, // VLD2DUPd8wb_register
7838
1.14M
    518U, // VLD2DUPd8x2
7839
1.14M
    676U, // VLD2DUPd8x2wb_fixed
7840
1.14M
    2687780U, // VLD2DUPd8x2wb_register
7841
1.14M
    0U, // VLD2DUPq16EvenPseudo
7842
1.14M
    0U, // VLD2DUPq16OddPseudo
7843
1.14M
    0U, // VLD2DUPq16OddPseudoWB_fixed
7844
1.14M
    0U, // VLD2DUPq16OddPseudoWB_register
7845
1.14M
    0U, // VLD2DUPq32EvenPseudo
7846
1.14M
    0U, // VLD2DUPq32OddPseudo
7847
1.14M
    0U, // VLD2DUPq32OddPseudoWB_fixed
7848
1.14M
    0U, // VLD2DUPq32OddPseudoWB_register
7849
1.14M
    0U, // VLD2DUPq8EvenPseudo
7850
1.14M
    0U, // VLD2DUPq8OddPseudo
7851
1.14M
    0U, // VLD2DUPq8OddPseudoWB_fixed
7852
1.14M
    0U, // VLD2DUPq8OddPseudoWB_register
7853
1.14M
    13948454U,  // VLD2LNd16
7854
1.14M
    0U, // VLD2LNd16Pseudo
7855
1.14M
    0U, // VLD2LNd16Pseudo_UPD
7856
1.14M
    349869734U, // VLD2LNd16_UPD
7857
1.14M
    13948454U,  // VLD2LNd32
7858
1.14M
    0U, // VLD2LNd32Pseudo
7859
1.14M
    0U, // VLD2LNd32Pseudo_UPD
7860
1.14M
    349869734U, // VLD2LNd32_UPD
7861
1.14M
    13948454U,  // VLD2LNd8
7862
1.14M
    0U, // VLD2LNd8Pseudo
7863
1.14M
    0U, // VLD2LNd8Pseudo_UPD
7864
1.14M
    349869734U, // VLD2LNd8_UPD
7865
1.14M
    13948454U,  // VLD2LNq16
7866
1.14M
    0U, // VLD2LNq16Pseudo
7867
1.14M
    0U, // VLD2LNq16Pseudo_UPD
7868
1.14M
    349869734U, // VLD2LNq16_UPD
7869
1.14M
    13948454U,  // VLD2LNq32
7870
1.14M
    0U, // VLD2LNq32Pseudo
7871
1.14M
    0U, // VLD2LNq32Pseudo_UPD
7872
1.14M
    349869734U, // VLD2LNq32_UPD
7873
1.14M
    518U, // VLD2b16
7874
1.14M
    676U, // VLD2b16wb_fixed
7875
1.14M
    2687780U, // VLD2b16wb_register
7876
1.14M
    518U, // VLD2b32
7877
1.14M
    676U, // VLD2b32wb_fixed
7878
1.14M
    2687780U, // VLD2b32wb_register
7879
1.14M
    518U, // VLD2b8
7880
1.14M
    676U, // VLD2b8wb_fixed
7881
1.14M
    2687780U, // VLD2b8wb_register
7882
1.14M
    518U, // VLD2d16
7883
1.14M
    676U, // VLD2d16wb_fixed
7884
1.14M
    2687780U, // VLD2d16wb_register
7885
1.14M
    518U, // VLD2d32
7886
1.14M
    676U, // VLD2d32wb_fixed
7887
1.14M
    2687780U, // VLD2d32wb_register
7888
1.14M
    518U, // VLD2d8
7889
1.14M
    676U, // VLD2d8wb_fixed
7890
1.14M
    2687780U, // VLD2d8wb_register
7891
1.14M
    518U, // VLD2q16
7892
1.14M
    0U, // VLD2q16Pseudo
7893
1.14M
    0U, // VLD2q16PseudoWB_fixed
7894
1.14M
    0U, // VLD2q16PseudoWB_register
7895
1.14M
    676U, // VLD2q16wb_fixed
7896
1.14M
    2687780U, // VLD2q16wb_register
7897
1.14M
    518U, // VLD2q32
7898
1.14M
    0U, // VLD2q32Pseudo
7899
1.14M
    0U, // VLD2q32PseudoWB_fixed
7900
1.14M
    0U, // VLD2q32PseudoWB_register
7901
1.14M
    676U, // VLD2q32wb_fixed
7902
1.14M
    2687780U, // VLD2q32wb_register
7903
1.14M
    518U, // VLD2q8
7904
1.14M
    0U, // VLD2q8Pseudo
7905
1.14M
    0U, // VLD2q8PseudoWB_fixed
7906
1.14M
    0U, // VLD2q8PseudoWB_register
7907
1.14M
    676U, // VLD2q8wb_fixed
7908
1.14M
    2687780U, // VLD2q8wb_register
7909
1.14M
    333608U,  // VLD3DUPd16
7910
1.14M
    0U, // VLD3DUPd16Pseudo
7911
1.14M
    0U, // VLD3DUPd16Pseudo_UPD
7912
1.14M
    15030056U,  // VLD3DUPd16_UPD
7913
1.14M
    333608U,  // VLD3DUPd32
7914
1.14M
    0U, // VLD3DUPd32Pseudo
7915
1.14M
    0U, // VLD3DUPd32Pseudo_UPD
7916
1.14M
    15030056U,  // VLD3DUPd32_UPD
7917
1.14M
    333608U,  // VLD3DUPd8
7918
1.14M
    0U, // VLD3DUPd8Pseudo
7919
1.14M
    0U, // VLD3DUPd8Pseudo_UPD
7920
1.14M
    15030056U,  // VLD3DUPd8_UPD
7921
1.14M
    333608U,  // VLD3DUPq16
7922
1.14M
    0U, // VLD3DUPq16EvenPseudo
7923
1.14M
    0U, // VLD3DUPq16OddPseudo
7924
1.14M
    0U, // VLD3DUPq16OddPseudo_UPD
7925
1.14M
    15030056U,  // VLD3DUPq16_UPD
7926
1.14M
    333608U,  // VLD3DUPq32
7927
1.14M
    0U, // VLD3DUPq32EvenPseudo
7928
1.14M
    0U, // VLD3DUPq32OddPseudo
7929
1.14M
    0U, // VLD3DUPq32OddPseudo_UPD
7930
1.14M
    15030056U,  // VLD3DUPq32_UPD
7931
1.14M
    333608U,  // VLD3DUPq8
7932
1.14M
    0U, // VLD3DUPq8EvenPseudo
7933
1.14M
    0U, // VLD3DUPq8OddPseudo
7934
1.14M
    0U, // VLD3DUPq8OddPseudo_UPD
7935
1.14M
    15030056U,  // VLD3DUPq8_UPD
7936
1.14M
    383424166U, // VLD3LNd16
7937
1.14M
    0U, // VLD3LNd16Pseudo
7938
1.14M
    0U, // VLD3LNd16Pseudo_UPD
7939
1.14M
    15505318U,  // VLD3LNd16_UPD
7940
1.14M
    383424166U, // VLD3LNd32
7941
1.14M
    0U, // VLD3LNd32Pseudo
7942
1.14M
    0U, // VLD3LNd32Pseudo_UPD
7943
1.14M
    15505318U,  // VLD3LNd32_UPD
7944
1.14M
    383424166U, // VLD3LNd8
7945
1.14M
    0U, // VLD3LNd8Pseudo
7946
1.14M
    0U, // VLD3LNd8Pseudo_UPD
7947
1.14M
    15505318U,  // VLD3LNd8_UPD
7948
1.14M
    383424166U, // VLD3LNq16
7949
1.14M
    0U, // VLD3LNq16Pseudo
7950
1.14M
    0U, // VLD3LNq16Pseudo_UPD
7951
1.14M
    15505318U,  // VLD3LNq16_UPD
7952
1.14M
    383424166U, // VLD3LNq32
7953
1.14M
    0U, // VLD3LNq32Pseudo
7954
1.14M
    0U, // VLD3LNq32Pseudo_UPD
7955
1.14M
    15505318U,  // VLD3LNq32_UPD
7956
1.14M
    402653184U, // VLD3d16
7957
1.14M
    0U, // VLD3d16Pseudo
7958
1.14M
    0U, // VLD3d16Pseudo_UPD
7959
1.14M
    402653184U, // VLD3d16_UPD
7960
1.14M
    402653184U, // VLD3d32
7961
1.14M
    0U, // VLD3d32Pseudo
7962
1.14M
    0U, // VLD3d32Pseudo_UPD
7963
1.14M
    402653184U, // VLD3d32_UPD
7964
1.14M
    402653184U, // VLD3d8
7965
1.14M
    0U, // VLD3d8Pseudo
7966
1.14M
    0U, // VLD3d8Pseudo_UPD
7967
1.14M
    402653184U, // VLD3d8_UPD
7968
1.14M
    402653184U, // VLD3q16
7969
1.14M
    0U, // VLD3q16Pseudo_UPD
7970
1.14M
    402653184U, // VLD3q16_UPD
7971
1.14M
    0U, // VLD3q16oddPseudo
7972
1.14M
    0U, // VLD3q16oddPseudo_UPD
7973
1.14M
    402653184U, // VLD3q32
7974
1.14M
    0U, // VLD3q32Pseudo_UPD
7975
1.14M
    402653184U, // VLD3q32_UPD
7976
1.14M
    0U, // VLD3q32oddPseudo
7977
1.14M
    0U, // VLD3q32oddPseudo_UPD
7978
1.14M
    402653184U, // VLD3q8
7979
1.14M
    0U, // VLD3q8Pseudo_UPD
7980
1.14M
    402653184U, // VLD3q8_UPD
7981
1.14M
    0U, // VLD3q8oddPseudo
7982
1.14M
    0U, // VLD3q8oddPseudo_UPD
7983
1.14M
    2971688U, // VLD4DUPd16
7984
1.14M
    0U, // VLD4DUPd16Pseudo
7985
1.14M
    0U, // VLD4DUPd16Pseudo_UPD
7986
1.14M
    366632U,  // VLD4DUPd16_UPD
7987
1.14M
    2971688U, // VLD4DUPd32
7988
1.14M
    0U, // VLD4DUPd32Pseudo
7989
1.14M
    0U, // VLD4DUPd32Pseudo_UPD
7990
1.14M
    366632U,  // VLD4DUPd32_UPD
7991
1.14M
    2971688U, // VLD4DUPd8
7992
1.14M
    0U, // VLD4DUPd8Pseudo
7993
1.14M
    0U, // VLD4DUPd8Pseudo_UPD
7994
1.14M
    366632U,  // VLD4DUPd8_UPD
7995
1.14M
    2971688U, // VLD4DUPq16
7996
1.14M
    0U, // VLD4DUPq16EvenPseudo
7997
1.14M
    0U, // VLD4DUPq16OddPseudo
7998
1.14M
    0U, // VLD4DUPq16OddPseudo_UPD
7999
1.14M
    366632U,  // VLD4DUPq16_UPD
8000
1.14M
    2971688U, // VLD4DUPq32
8001
1.14M
    0U, // VLD4DUPq32EvenPseudo
8002
1.14M
    0U, // VLD4DUPq32OddPseudo
8003
1.14M
    0U, // VLD4DUPq32OddPseudo_UPD
8004
1.14M
    366632U,  // VLD4DUPq32_UPD
8005
1.14M
    2971688U, // VLD4DUPq8
8006
1.14M
    0U, // VLD4DUPq8EvenPseudo
8007
1.14M
    0U, // VLD4DUPq8OddPseudo
8008
1.14M
    0U, // VLD4DUPq8OddPseudo_UPD
8009
1.14M
    366632U,  // VLD4DUPq8_UPD
8010
1.14M
    440194982U, // VLD4LNd16
8011
1.14M
    0U, // VLD4LNd16Pseudo
8012
1.14M
    0U, // VLD4LNd16Pseudo_UPD
8013
1.14M
    6310U,  // VLD4LNd16_UPD
8014
1.14M
    440194982U, // VLD4LNd32
8015
1.14M
    0U, // VLD4LNd32Pseudo
8016
1.14M
    0U, // VLD4LNd32Pseudo_UPD
8017
1.14M
    6310U,  // VLD4LNd32_UPD
8018
1.14M
    440194982U, // VLD4LNd8
8019
1.14M
    0U, // VLD4LNd8Pseudo
8020
1.14M
    0U, // VLD4LNd8Pseudo_UPD
8021
1.14M
    6310U,  // VLD4LNd8_UPD
8022
1.14M
    440194982U, // VLD4LNq16
8023
1.14M
    0U, // VLD4LNq16Pseudo
8024
1.14M
    0U, // VLD4LNq16Pseudo_UPD
8025
1.14M
    6310U,  // VLD4LNq16_UPD
8026
1.14M
    440194982U, // VLD4LNq32
8027
1.14M
    0U, // VLD4LNq32Pseudo
8028
1.14M
    0U, // VLD4LNq32Pseudo_UPD
8029
1.14M
    6310U,  // VLD4LNq32_UPD
8030
1.14M
    33554432U,  // VLD4d16
8031
1.14M
    0U, // VLD4d16Pseudo
8032
1.14M
    0U, // VLD4d16Pseudo_UPD
8033
1.14M
    33554432U,  // VLD4d16_UPD
8034
1.14M
    33554432U,  // VLD4d32
8035
1.14M
    0U, // VLD4d32Pseudo
8036
1.14M
    0U, // VLD4d32Pseudo_UPD
8037
1.14M
    33554432U,  // VLD4d32_UPD
8038
1.14M
    33554432U,  // VLD4d8
8039
1.14M
    0U, // VLD4d8Pseudo
8040
1.14M
    0U, // VLD4d8Pseudo_UPD
8041
1.14M
    33554432U,  // VLD4d8_UPD
8042
1.14M
    33554432U,  // VLD4q16
8043
1.14M
    0U, // VLD4q16Pseudo_UPD
8044
1.14M
    33554432U,  // VLD4q16_UPD
8045
1.14M
    0U, // VLD4q16oddPseudo
8046
1.14M
    0U, // VLD4q16oddPseudo_UPD
8047
1.14M
    33554432U,  // VLD4q32
8048
1.14M
    0U, // VLD4q32Pseudo_UPD
8049
1.14M
    33554432U,  // VLD4q32_UPD
8050
1.14M
    0U, // VLD4q32oddPseudo
8051
1.14M
    0U, // VLD4q32oddPseudo_UPD
8052
1.14M
    33554432U,  // VLD4q8
8053
1.14M
    0U, // VLD4q8Pseudo_UPD
8054
1.14M
    33554432U,  // VLD4q8_UPD
8055
1.14M
    0U, // VLD4q8oddPseudo
8056
1.14M
    0U, // VLD4q8oddPseudo_UPD
8057
1.14M
    532U, // VLDMDDB_UPD
8058
1.14M
    18560U, // VLDMDIA
8059
1.14M
    532U, // VLDMDIA_UPD
8060
1.14M
    0U, // VLDMQIA
8061
1.14M
    532U, // VLDMSDB_UPD
8062
1.14M
    18560U, // VLDMSIA
8063
1.14M
    532U, // VLDMSIA_UPD
8064
1.14M
    6400U,  // VLDRD
8065
1.14M
    6528U,  // VLDRH
8066
1.14M
    6400U,  // VLDRS
8067
1.14M
    0U, // VLDR_FPCXTNS_off
8068
1.14M
    42U,  // VLDR_FPCXTNS_post
8069
1.14M
    0U, // VLDR_FPCXTNS_pre
8070
1.14M
    0U, // VLDR_FPCXTS_off
8071
1.14M
    42U,  // VLDR_FPCXTS_post
8072
1.14M
    0U, // VLDR_FPCXTS_pre
8073
1.14M
    0U, // VLDR_FPSCR_NZCVQC_off
8074
1.14M
    42U,  // VLDR_FPSCR_NZCVQC_post
8075
1.14M
    0U, // VLDR_FPSCR_NZCVQC_pre
8076
1.14M
    0U, // VLDR_FPSCR_off
8077
1.14M
    42U,  // VLDR_FPSCR_post
8078
1.14M
    0U, // VLDR_FPSCR_pre
8079
1.14M
    0U, // VLDR_P0_off
8080
1.14M
    44U,  // VLDR_P0_post
8081
1.14M
    0U, // VLDR_P0_pre
8082
1.14M
    0U, // VLDR_VPR_off
8083
1.14M
    42U,  // VLDR_VPR_post
8084
1.14M
    0U, // VLDR_VPR_pre
8085
1.14M
    2U, // VLLDM
8086
1.14M
    2U, // VLSTM
8087
1.14M
    0U, // VMAXfd
8088
1.14M
    0U, // VMAXfq
8089
1.14M
    0U, // VMAXhd
8090
1.14M
    0U, // VMAXhq
8091
1.14M
    0U, // VMAXsv16i8
8092
1.14M
    0U, // VMAXsv2i32
8093
1.14M
    0U, // VMAXsv4i16
8094
1.14M
    0U, // VMAXsv4i32
8095
1.14M
    0U, // VMAXsv8i16
8096
1.14M
    0U, // VMAXsv8i8
8097
1.14M
    0U, // VMAXuv16i8
8098
1.14M
    0U, // VMAXuv2i32
8099
1.14M
    0U, // VMAXuv4i16
8100
1.14M
    0U, // VMAXuv4i32
8101
1.14M
    0U, // VMAXuv8i16
8102
1.14M
    0U, // VMAXuv8i8
8103
1.14M
    0U, // VMINfd
8104
1.14M
    0U, // VMINfq
8105
1.14M
    0U, // VMINhd
8106
1.14M
    0U, // VMINhq
8107
1.14M
    0U, // VMINsv16i8
8108
1.14M
    0U, // VMINsv2i32
8109
1.14M
    0U, // VMINsv4i16
8110
1.14M
    0U, // VMINsv4i32
8111
1.14M
    0U, // VMINsv8i16
8112
1.14M
    0U, // VMINsv8i8
8113
1.14M
    0U, // VMINuv16i8
8114
1.14M
    0U, // VMINuv2i32
8115
1.14M
    0U, // VMINuv4i16
8116
1.14M
    0U, // VMINuv4i32
8117
1.14M
    0U, // VMINuv8i16
8118
1.14M
    0U, // VMINuv8i8
8119
1.14M
    49944U, // VMLAD
8120
1.14M
    3671552U, // VMLAH
8121
1.14M
    473433600U, // VMLALslsv2i32
8122
1.14M
    473433600U, // VMLALslsv4i16
8123
1.14M
    473433600U, // VMLALsluv2i32
8124
1.14M
    473433600U, // VMLALsluv4i16
8125
1.14M
    3671552U, // VMLALsv2i64
8126
1.14M
    3671552U, // VMLALsv4i32
8127
1.14M
    3671552U, // VMLALsv8i16
8128
1.14M
    3671552U, // VMLALuv2i64
8129
1.14M
    3671552U, // VMLALuv4i32
8130
1.14M
    3671552U, // VMLALuv8i16
8131
1.14M
    3671552U, // VMLAS
8132
1.14M
    3671552U, // VMLAfd
8133
1.14M
    3671552U, // VMLAfq
8134
1.14M
    3671552U, // VMLAhd
8135
1.14M
    3671552U, // VMLAhq
8136
1.14M
    473433600U, // VMLAslfd
8137
1.14M
    473433600U, // VMLAslfq
8138
1.14M
    473433600U, // VMLAslhd
8139
1.14M
    473433600U, // VMLAslhq
8140
1.14M
    473433600U, // VMLAslv2i32
8141
1.14M
    473433600U, // VMLAslv4i16
8142
1.14M
    473433600U, // VMLAslv4i32
8143
1.14M
    473433600U, // VMLAslv8i16
8144
1.14M
    3671552U, // VMLAv16i8
8145
1.14M
    3671552U, // VMLAv2i32
8146
1.14M
    3671552U, // VMLAv4i16
8147
1.14M
    3671552U, // VMLAv4i32
8148
1.14M
    3671552U, // VMLAv8i16
8149
1.14M
    3671552U, // VMLAv8i8
8150
1.14M
    49944U, // VMLSD
8151
1.14M
    3671552U, // VMLSH
8152
1.14M
    473433600U, // VMLSLslsv2i32
8153
1.14M
    473433600U, // VMLSLslsv4i16
8154
1.14M
    473433600U, // VMLSLsluv2i32
8155
1.14M
    473433600U, // VMLSLsluv4i16
8156
1.14M
    3671552U, // VMLSLsv2i64
8157
1.14M
    3671552U, // VMLSLsv4i32
8158
1.14M
    3671552U, // VMLSLsv8i16
8159
1.14M
    3671552U, // VMLSLuv2i64
8160
1.14M
    3671552U, // VMLSLuv4i32
8161
1.14M
    3671552U, // VMLSLuv8i16
8162
1.14M
    3671552U, // VMLSS
8163
1.14M
    3671552U, // VMLSfd
8164
1.14M
    3671552U, // VMLSfq
8165
1.14M
    3671552U, // VMLShd
8166
1.14M
    3671552U, // VMLShq
8167
1.14M
    473433600U, // VMLSslfd
8168
1.14M
    473433600U, // VMLSslfq
8169
1.14M
    473433600U, // VMLSslhd
8170
1.14M
    473433600U, // VMLSslhq
8171
1.14M
    473433600U, // VMLSslv2i32
8172
1.14M
    473433600U, // VMLSslv4i16
8173
1.14M
    473433600U, // VMLSslv4i32
8174
1.14M
    473433600U, // VMLSslv8i16
8175
1.14M
    3671552U, // VMLSv16i8
8176
1.14M
    3671552U, // VMLSv2i32
8177
1.14M
    3671552U, // VMLSv4i16
8178
1.14M
    3671552U, // VMLSv4i32
8179
1.14M
    3671552U, // VMLSv8i16
8180
1.14M
    3671552U, // VMLSv8i8
8181
1.14M
    2U, // VMMLA
8182
1.14M
    528U, // VMOVD
8183
1.14M
    0U, // VMOVDRR
8184
1.14M
    2U, // VMOVH
8185
1.14M
    16384U, // VMOVHR
8186
1.14M
    16384U, // VMOVLsv2i64
8187
1.14M
    16384U, // VMOVLsv4i32
8188
1.14M
    16384U, // VMOVLsv8i16
8189
1.14M
    16384U, // VMOVLuv2i64
8190
1.14M
    16384U, // VMOVLuv4i32
8191
1.14M
    16384U, // VMOVLuv8i16
8192
1.14M
    2U, // VMOVNv2i32
8193
1.14M
    16384U, // VMOVNv4i16
8194
1.14M
    16384U, // VMOVNv8i8
8195
1.14M
    16384U, // VMOVRH
8196
1.14M
    0U, // VMOVRRD
8197
1.14M
    33554432U,  // VMOVRRS
8198
1.14M
    16384U, // VMOVRS
8199
1.14M
    16384U, // VMOVS
8200
1.14M
    16384U, // VMOVSR
8201
1.14M
    33554432U,  // VMOVSRR
8202
1.14M
    4992U,  // VMOVv16i8
8203
1.14M
    0U, // VMOVv1i64
8204
1.14M
    2048U,  // VMOVv2f32
8205
1.14M
    4992U,  // VMOVv2i32
8206
1.14M
    0U, // VMOVv2i64
8207
1.14M
    2048U,  // VMOVv4f32
8208
1.14M
    4992U,  // VMOVv4i16
8209
1.14M
    4992U,  // VMOVv4i32
8210
1.14M
    4992U,  // VMOVv8i16
8211
1.14M
    4992U,  // VMOVv8i8
8212
1.14M
    46U,  // VMRS
8213
1.14M
    48U,  // VMRS_FPCXTNS
8214
1.14M
    50U,  // VMRS_FPCXTS
8215
1.14M
    52U,  // VMRS_FPEXC
8216
1.14M
    54U,  // VMRS_FPINST
8217
1.14M
    56U,  // VMRS_FPINST2
8218
1.14M
    58U,  // VMRS_FPSCR_NZCVQC
8219
1.14M
    60U,  // VMRS_FPSID
8220
1.14M
    62U,  // VMRS_MVFR0
8221
1.14M
    64U,  // VMRS_MVFR1
8222
1.14M
    66U,  // VMRS_MVFR2
8223
1.14M
    68U,  // VMRS_P0
8224
1.14M
    70U,  // VMRS_VPR
8225
1.14M
    2U, // VMSR
8226
1.14M
    2U, // VMSR_FPCXTNS
8227
1.14M
    2U, // VMSR_FPCXTS
8228
1.14M
    0U, // VMSR_FPEXC
8229
1.14M
    0U, // VMSR_FPINST
8230
1.14M
    0U, // VMSR_FPINST2
8231
1.14M
    2U, // VMSR_FPSCR_NZCVQC
8232
1.14M
    0U, // VMSR_FPSID
8233
1.14M
    2U, // VMSR_P0
8234
1.14M
    2U, // VMSR_VPR
8235
1.14M
    2720528U, // VMULD
8236
1.14M
    0U, // VMULH
8237
1.14M
    17920U, // VMULLp64
8238
1.14M
    0U, // VMULLp8
8239
1.14M
    167772160U, // VMULLslsv2i32
8240
1.14M
    167772160U, // VMULLslsv4i16
8241
1.14M
    167772160U, // VMULLsluv2i32
8242
1.14M
    167772160U, // VMULLsluv4i16
8243
1.14M
    0U, // VMULLsv2i64
8244
1.14M
    0U, // VMULLsv4i32
8245
1.14M
    0U, // VMULLsv8i16
8246
1.14M
    0U, // VMULLuv2i64
8247
1.14M
    0U, // VMULLuv4i32
8248
1.14M
    0U, // VMULLuv8i16
8249
1.14M
    0U, // VMULS
8250
1.14M
    0U, // VMULfd
8251
1.14M
    0U, // VMULfq
8252
1.14M
    0U, // VMULhd
8253
1.14M
    0U, // VMULhq
8254
1.14M
    0U, // VMULpd
8255
1.14M
    0U, // VMULpq
8256
1.14M
    167772160U, // VMULslfd
8257
1.14M
    167772160U, // VMULslfq
8258
1.14M
    167772160U, // VMULslhd
8259
1.14M
    167772160U, // VMULslhq
8260
1.14M
    167772160U, // VMULslv2i32
8261
1.14M
    167772160U, // VMULslv4i16
8262
1.14M
    167772160U, // VMULslv4i32
8263
1.14M
    167772160U, // VMULslv8i16
8264
1.14M
    0U, // VMULv16i8
8265
1.14M
    0U, // VMULv2i32
8266
1.14M
    0U, // VMULv4i16
8267
1.14M
    0U, // VMULv4i32
8268
1.14M
    0U, // VMULv8i16
8269
1.14M
    0U, // VMULv8i8
8270
1.14M
    16384U, // VMVNd
8271
1.14M
    16384U, // VMVNq
8272
1.14M
    4992U,  // VMVNv2i32
8273
1.14M
    4992U,  // VMVNv4i16
8274
1.14M
    4992U,  // VMVNv4i32
8275
1.14M
    4992U,  // VMVNv8i16
8276
1.14M
    528U, // VNEGD
8277
1.14M
    16384U, // VNEGH
8278
1.14M
    16384U, // VNEGS
8279
1.14M
    16384U, // VNEGf32q
8280
1.14M
    16384U, // VNEGfd
8281
1.14M
    16384U, // VNEGhd
8282
1.14M
    16384U, // VNEGhq
8283
1.14M
    16384U, // VNEGs16d
8284
1.14M
    16384U, // VNEGs16q
8285
1.14M
    16384U, // VNEGs32d
8286
1.14M
    16384U, // VNEGs32q
8287
1.14M
    16384U, // VNEGs8d
8288
1.14M
    16384U, // VNEGs8q
8289
1.14M
    49944U, // VNMLAD
8290
1.14M
    3671552U, // VNMLAH
8291
1.14M
    3671552U, // VNMLAS
8292
1.14M
    49944U, // VNMLSD
8293
1.14M
    3671552U, // VNMLSH
8294
1.14M
    3671552U, // VNMLSS
8295
1.14M
    2720528U, // VNMULD
8296
1.14M
    0U, // VNMULH
8297
1.14M
    0U, // VNMULS
8298
1.14M
    0U, // VORNd
8299
1.14M
    0U, // VORNq
8300
1.14M
    0U, // VORRd
8301
1.14M
    4992U,  // VORRiv2i32
8302
1.14M
    4992U,  // VORRiv4i16
8303
1.14M
    4992U,  // VORRiv4i32
8304
1.14M
    4992U,  // VORRiv8i16
8305
1.14M
    0U, // VORRq
8306
1.14M
    17920U, // VPADALsv16i8
8307
1.14M
    17920U, // VPADALsv2i32
8308
1.14M
    17920U, // VPADALsv4i16
8309
1.14M
    17920U, // VPADALsv4i32
8310
1.14M
    17920U, // VPADALsv8i16
8311
1.14M
    17920U, // VPADALsv8i8
8312
1.14M
    17920U, // VPADALuv16i8
8313
1.14M
    17920U, // VPADALuv2i32
8314
1.14M
    17920U, // VPADALuv4i16
8315
1.14M
    17920U, // VPADALuv4i32
8316
1.14M
    17920U, // VPADALuv8i16
8317
1.14M
    17920U, // VPADALuv8i8
8318
1.14M
    16384U, // VPADDLsv16i8
8319
1.14M
    16384U, // VPADDLsv2i32
8320
1.14M
    16384U, // VPADDLsv4i16
8321
1.14M
    16384U, // VPADDLsv4i32
8322
1.14M
    16384U, // VPADDLsv8i16
8323
1.14M
    16384U, // VPADDLsv8i8
8324
1.14M
    16384U, // VPADDLuv16i8
8325
1.14M
    16384U, // VPADDLuv2i32
8326
1.14M
    16384U, // VPADDLuv4i16
8327
1.14M
    16384U, // VPADDLuv4i32
8328
1.14M
    16384U, // VPADDLuv8i16
8329
1.14M
    16384U, // VPADDLuv8i8
8330
1.14M
    0U, // VPADDf
8331
1.14M
    0U, // VPADDh
8332
1.14M
    0U, // VPADDi16
8333
1.14M
    0U, // VPADDi32
8334
1.14M
    0U, // VPADDi8
8335
1.14M
    0U, // VPMAXf
8336
1.14M
    0U, // VPMAXh
8337
1.14M
    0U, // VPMAXs16
8338
1.14M
    0U, // VPMAXs32
8339
1.14M
    0U, // VPMAXs8
8340
1.14M
    0U, // VPMAXu16
8341
1.14M
    0U, // VPMAXu32
8342
1.14M
    0U, // VPMAXu8
8343
1.14M
    0U, // VPMINf
8344
1.14M
    0U, // VPMINh
8345
1.14M
    0U, // VPMINs16
8346
1.14M
    0U, // VPMINs32
8347
1.14M
    0U, // VPMINs8
8348
1.14M
    0U, // VPMINu16
8349
1.14M
    0U, // VPMINu32
8350
1.14M
    0U, // VPMINu8
8351
1.14M
    16384U, // VQABSv16i8
8352
1.14M
    16384U, // VQABSv2i32
8353
1.14M
    16384U, // VQABSv4i16
8354
1.14M
    16384U, // VQABSv4i32
8355
1.14M
    16384U, // VQABSv8i16
8356
1.14M
    16384U, // VQABSv8i8
8357
1.14M
    0U, // VQADDsv16i8
8358
1.14M
    17920U, // VQADDsv1i64
8359
1.14M
    0U, // VQADDsv2i32
8360
1.14M
    17920U, // VQADDsv2i64
8361
1.14M
    0U, // VQADDsv4i16
8362
1.14M
    0U, // VQADDsv4i32
8363
1.14M
    0U, // VQADDsv8i16
8364
1.14M
    0U, // VQADDsv8i8
8365
1.14M
    0U, // VQADDuv16i8
8366
1.14M
    0U, // VQADDuv1i64
8367
1.14M
    0U, // VQADDuv2i32
8368
1.14M
    0U, // VQADDuv2i64
8369
1.14M
    0U, // VQADDuv4i16
8370
1.14M
    0U, // VQADDuv4i32
8371
1.14M
    0U, // VQADDuv8i16
8372
1.14M
    0U, // VQADDuv8i8
8373
1.14M
    473433600U, // VQDMLALslv2i32
8374
1.14M
    473433600U, // VQDMLALslv4i16
8375
1.14M
    3671552U, // VQDMLALv2i64
8376
1.14M
    3671552U, // VQDMLALv4i32
8377
1.14M
    473433600U, // VQDMLSLslv2i32
8378
1.14M
    473433600U, // VQDMLSLslv4i16
8379
1.14M
    3671552U, // VQDMLSLv2i64
8380
1.14M
    3671552U, // VQDMLSLv4i32
8381
1.14M
    167772160U, // VQDMULHslv2i32
8382
1.14M
    167772160U, // VQDMULHslv4i16
8383
1.14M
    167772160U, // VQDMULHslv4i32
8384
1.14M
    167772160U, // VQDMULHslv8i16
8385
1.14M
    0U, // VQDMULHv2i32
8386
1.14M
    0U, // VQDMULHv4i16
8387
1.14M
    0U, // VQDMULHv4i32
8388
1.14M
    0U, // VQDMULHv8i16
8389
1.14M
    167772160U, // VQDMULLslv2i32
8390
1.14M
    167772160U, // VQDMULLslv4i16
8391
1.14M
    0U, // VQDMULLv2i64
8392
1.14M
    0U, // VQDMULLv4i32
8393
1.14M
    2U, // VQMOVNsuv2i32
8394
1.14M
    16384U, // VQMOVNsuv4i16
8395
1.14M
    16384U, // VQMOVNsuv8i8
8396
1.14M
    2U, // VQMOVNsv2i32
8397
1.14M
    16384U, // VQMOVNsv4i16
8398
1.14M
    16384U, // VQMOVNsv8i8
8399
1.14M
    16384U, // VQMOVNuv2i32
8400
1.14M
    16384U, // VQMOVNuv4i16
8401
1.14M
    16384U, // VQMOVNuv8i8
8402
1.14M
    16384U, // VQNEGv16i8
8403
1.14M
    16384U, // VQNEGv2i32
8404
1.14M
    16384U, // VQNEGv4i16
8405
1.14M
    16384U, // VQNEGv4i32
8406
1.14M
    16384U, // VQNEGv8i16
8407
1.14M
    16384U, // VQNEGv8i8
8408
1.14M
    473433600U, // VQRDMLAHslv2i32
8409
1.14M
    473433600U, // VQRDMLAHslv4i16
8410
1.14M
    473433600U, // VQRDMLAHslv4i32
8411
1.14M
    473433600U, // VQRDMLAHslv8i16
8412
1.14M
    3671552U, // VQRDMLAHv2i32
8413
1.14M
    3671552U, // VQRDMLAHv4i16
8414
1.14M
    3671552U, // VQRDMLAHv4i32
8415
1.14M
    3671552U, // VQRDMLAHv8i16
8416
1.14M
    473433600U, // VQRDMLSHslv2i32
8417
1.14M
    473433600U, // VQRDMLSHslv4i16
8418
1.14M
    473433600U, // VQRDMLSHslv4i32
8419
1.14M
    473433600U, // VQRDMLSHslv8i16
8420
1.14M
    3671552U, // VQRDMLSHv2i32
8421
1.14M
    3671552U, // VQRDMLSHv4i16
8422
1.14M
    3671552U, // VQRDMLSHv4i32
8423
1.14M
    3671552U, // VQRDMLSHv8i16
8424
1.14M
    167772160U, // VQRDMULHslv2i32
8425
1.14M
    167772160U, // VQRDMULHslv4i16
8426
1.14M
    167772160U, // VQRDMULHslv4i32
8427
1.14M
    167772160U, // VQRDMULHslv8i16
8428
1.14M
    0U, // VQRDMULHv2i32
8429
1.14M
    0U, // VQRDMULHv4i16
8430
1.14M
    0U, // VQRDMULHv4i32
8431
1.14M
    0U, // VQRDMULHv8i16
8432
1.14M
    0U, // VQRSHLsv16i8
8433
1.14M
    17920U, // VQRSHLsv1i64
8434
1.14M
    0U, // VQRSHLsv2i32
8435
1.14M
    17920U, // VQRSHLsv2i64
8436
1.14M
    0U, // VQRSHLsv4i16
8437
1.14M
    0U, // VQRSHLsv4i32
8438
1.14M
    0U, // VQRSHLsv8i16
8439
1.14M
    0U, // VQRSHLsv8i8
8440
1.14M
    0U, // VQRSHLuv16i8
8441
1.14M
    0U, // VQRSHLuv1i64
8442
1.14M
    0U, // VQRSHLuv2i32
8443
1.14M
    0U, // VQRSHLuv2i64
8444
1.14M
    0U, // VQRSHLuv4i16
8445
1.14M
    0U, // VQRSHLuv4i32
8446
1.14M
    0U, // VQRSHLuv8i16
8447
1.14M
    0U, // VQRSHLuv8i8
8448
1.14M
    17920U, // VQRSHRNsv2i32
8449
1.14M
    0U, // VQRSHRNsv4i16
8450
1.14M
    0U, // VQRSHRNsv8i8
8451
1.14M
    0U, // VQRSHRNuv2i32
8452
1.14M
    0U, // VQRSHRNuv4i16
8453
1.14M
    0U, // VQRSHRNuv8i8
8454
1.14M
    17920U, // VQRSHRUNv2i32
8455
1.14M
    0U, // VQRSHRUNv4i16
8456
1.14M
    0U, // VQRSHRUNv8i8
8457
1.14M
    0U, // VQSHLsiv16i8
8458
1.14M
    17920U, // VQSHLsiv1i64
8459
1.14M
    0U, // VQSHLsiv2i32
8460
1.14M
    17920U, // VQSHLsiv2i64
8461
1.14M
    0U, // VQSHLsiv4i16
8462
1.14M
    0U, // VQSHLsiv4i32
8463
1.14M
    0U, // VQSHLsiv8i16
8464
1.14M
    0U, // VQSHLsiv8i8
8465
1.14M
    0U, // VQSHLsuv16i8
8466
1.14M
    17920U, // VQSHLsuv1i64
8467
1.14M
    0U, // VQSHLsuv2i32
8468
1.14M
    17920U, // VQSHLsuv2i64
8469
1.14M
    0U, // VQSHLsuv4i16
8470
1.14M
    0U, // VQSHLsuv4i32
8471
1.14M
    0U, // VQSHLsuv8i16
8472
1.14M
    0U, // VQSHLsuv8i8
8473
1.14M
    0U, // VQSHLsv16i8
8474
1.14M
    17920U, // VQSHLsv1i64
8475
1.14M
    0U, // VQSHLsv2i32
8476
1.14M
    17920U, // VQSHLsv2i64
8477
1.14M
    0U, // VQSHLsv4i16
8478
1.14M
    0U, // VQSHLsv4i32
8479
1.14M
    0U, // VQSHLsv8i16
8480
1.14M
    0U, // VQSHLsv8i8
8481
1.14M
    0U, // VQSHLuiv16i8
8482
1.14M
    0U, // VQSHLuiv1i64
8483
1.14M
    0U, // VQSHLuiv2i32
8484
1.14M
    0U, // VQSHLuiv2i64
8485
1.14M
    0U, // VQSHLuiv4i16
8486
1.14M
    0U, // VQSHLuiv4i32
8487
1.14M
    0U, // VQSHLuiv8i16
8488
1.14M
    0U, // VQSHLuiv8i8
8489
1.14M
    0U, // VQSHLuv16i8
8490
1.14M
    0U, // VQSHLuv1i64
8491
1.14M
    0U, // VQSHLuv2i32
8492
1.14M
    0U, // VQSHLuv2i64
8493
1.14M
    0U, // VQSHLuv4i16
8494
1.14M
    0U, // VQSHLuv4i32
8495
1.14M
    0U, // VQSHLuv8i16
8496
1.14M
    0U, // VQSHLuv8i8
8497
1.14M
    17920U, // VQSHRNsv2i32
8498
1.14M
    0U, // VQSHRNsv4i16
8499
1.14M
    0U, // VQSHRNsv8i8
8500
1.14M
    0U, // VQSHRNuv2i32
8501
1.14M
    0U, // VQSHRNuv4i16
8502
1.14M
    0U, // VQSHRNuv8i8
8503
1.14M
    17920U, // VQSHRUNv2i32
8504
1.14M
    0U, // VQSHRUNv4i16
8505
1.14M
    0U, // VQSHRUNv8i8
8506
1.14M
    0U, // VQSUBsv16i8
8507
1.14M
    17920U, // VQSUBsv1i64
8508
1.14M
    0U, // VQSUBsv2i32
8509
1.14M
    17920U, // VQSUBsv2i64
8510
1.14M
    0U, // VQSUBsv4i16
8511
1.14M
    0U, // VQSUBsv4i32
8512
1.14M
    0U, // VQSUBsv8i16
8513
1.14M
    0U, // VQSUBsv8i8
8514
1.14M
    0U, // VQSUBuv16i8
8515
1.14M
    0U, // VQSUBuv1i64
8516
1.14M
    0U, // VQSUBuv2i32
8517
1.14M
    0U, // VQSUBuv2i64
8518
1.14M
    0U, // VQSUBuv4i16
8519
1.14M
    0U, // VQSUBuv4i32
8520
1.14M
    0U, // VQSUBuv8i16
8521
1.14M
    0U, // VQSUBuv8i8
8522
1.14M
    17920U, // VRADDHNv2i32
8523
1.14M
    0U, // VRADDHNv4i16
8524
1.14M
    0U, // VRADDHNv8i8
8525
1.14M
    16384U, // VRECPEd
8526
1.14M
    16384U, // VRECPEfd
8527
1.14M
    16384U, // VRECPEfq
8528
1.14M
    16384U, // VRECPEhd
8529
1.14M
    16384U, // VRECPEhq
8530
1.14M
    16384U, // VRECPEq
8531
1.14M
    0U, // VRECPSfd
8532
1.14M
    0U, // VRECPSfq
8533
1.14M
    0U, // VRECPShd
8534
1.14M
    0U, // VRECPShq
8535
1.14M
    16384U, // VREV16d8
8536
1.14M
    16384U, // VREV16q8
8537
1.14M
    16384U, // VREV32d16
8538
1.14M
    16384U, // VREV32d8
8539
1.14M
    16384U, // VREV32q16
8540
1.14M
    16384U, // VREV32q8
8541
1.14M
    16384U, // VREV64d16
8542
1.14M
    16384U, // VREV64d32
8543
1.14M
    16384U, // VREV64d8
8544
1.14M
    16384U, // VREV64q16
8545
1.14M
    16384U, // VREV64q32
8546
1.14M
    16384U, // VREV64q8
8547
1.14M
    0U, // VRHADDsv16i8
8548
1.14M
    0U, // VRHADDsv2i32
8549
1.14M
    0U, // VRHADDsv4i16
8550
1.14M
    0U, // VRHADDsv4i32
8551
1.14M
    0U, // VRHADDsv8i16
8552
1.14M
    0U, // VRHADDsv8i8
8553
1.14M
    0U, // VRHADDuv16i8
8554
1.14M
    0U, // VRHADDuv2i32
8555
1.14M
    0U, // VRHADDuv4i16
8556
1.14M
    0U, // VRHADDuv4i32
8557
1.14M
    0U, // VRHADDuv8i16
8558
1.14M
    0U, // VRHADDuv8i8
8559
1.14M
    2U, // VRINTAD
8560
1.14M
    2U, // VRINTAH
8561
1.14M
    2U, // VRINTANDf
8562
1.14M
    2U, // VRINTANDh
8563
1.14M
    2U, // VRINTANQf
8564
1.14M
    2U, // VRINTANQh
8565
1.14M
    2U, // VRINTAS
8566
1.14M
    2U, // VRINTMD
8567
1.14M
    2U, // VRINTMH
8568
1.14M
    2U, // VRINTMNDf
8569
1.14M
    2U, // VRINTMNDh
8570
1.14M
    2U, // VRINTMNQf
8571
1.14M
    2U, // VRINTMNQh
8572
1.14M
    2U, // VRINTMS
8573
1.14M
    2U, // VRINTND
8574
1.14M
    2U, // VRINTNH
8575
1.14M
    2U, // VRINTNNDf
8576
1.14M
    2U, // VRINTNNDh
8577
1.14M
    2U, // VRINTNNQf
8578
1.14M
    2U, // VRINTNNQh
8579
1.14M
    2U, // VRINTNS
8580
1.14M
    2U, // VRINTPD
8581
1.14M
    2U, // VRINTPH
8582
1.14M
    2U, // VRINTPNDf
8583
1.14M
    2U, // VRINTPNDh
8584
1.14M
    2U, // VRINTPNQf
8585
1.14M
    2U, // VRINTPNQh
8586
1.14M
    2U, // VRINTPS
8587
1.14M
    528U, // VRINTRD
8588
1.14M
    16384U, // VRINTRH
8589
1.14M
    16384U, // VRINTRS
8590
1.14M
    528U, // VRINTXD
8591
1.14M
    16384U, // VRINTXH
8592
1.14M
    2U, // VRINTXNDf
8593
1.14M
    2U, // VRINTXNDh
8594
1.14M
    2U, // VRINTXNQf
8595
1.14M
    2U, // VRINTXNQh
8596
1.14M
    16384U, // VRINTXS
8597
1.14M
    528U, // VRINTZD
8598
1.14M
    16384U, // VRINTZH
8599
1.14M
    2U, // VRINTZNDf
8600
1.14M
    2U, // VRINTZNDh
8601
1.14M
    2U, // VRINTZNQf
8602
1.14M
    2U, // VRINTZNQh
8603
1.14M
    16384U, // VRINTZS
8604
1.14M
    0U, // VRSHLsv16i8
8605
1.14M
    17920U, // VRSHLsv1i64
8606
1.14M
    0U, // VRSHLsv2i32
8607
1.14M
    17920U, // VRSHLsv2i64
8608
1.14M
    0U, // VRSHLsv4i16
8609
1.14M
    0U, // VRSHLsv4i32
8610
1.14M
    0U, // VRSHLsv8i16
8611
1.14M
    0U, // VRSHLsv8i8
8612
1.14M
    0U, // VRSHLuv16i8
8613
1.14M
    0U, // VRSHLuv1i64
8614
1.14M
    0U, // VRSHLuv2i32
8615
1.14M
    0U, // VRSHLuv2i64
8616
1.14M
    0U, // VRSHLuv4i16
8617
1.14M
    0U, // VRSHLuv4i32
8618
1.14M
    0U, // VRSHLuv8i16
8619
1.14M
    0U, // VRSHLuv8i8
8620
1.14M
    17920U, // VRSHRNv2i32
8621
1.14M
    0U, // VRSHRNv4i16
8622
1.14M
    0U, // VRSHRNv8i8
8623
1.14M
    0U, // VRSHRsv16i8
8624
1.14M
    17920U, // VRSHRsv1i64
8625
1.14M
    0U, // VRSHRsv2i32
8626
1.14M
    17920U, // VRSHRsv2i64
8627
1.14M
    0U, // VRSHRsv4i16
8628
1.14M
    0U, // VRSHRsv4i32
8629
1.14M
    0U, // VRSHRsv8i16
8630
1.14M
    0U, // VRSHRsv8i8
8631
1.14M
    0U, // VRSHRuv16i8
8632
1.14M
    0U, // VRSHRuv1i64
8633
1.14M
    0U, // VRSHRuv2i32
8634
1.14M
    0U, // VRSHRuv2i64
8635
1.14M
    0U, // VRSHRuv4i16
8636
1.14M
    0U, // VRSHRuv4i32
8637
1.14M
    0U, // VRSHRuv8i16
8638
1.14M
    0U, // VRSHRuv8i8
8639
1.14M
    16384U, // VRSQRTEd
8640
1.14M
    16384U, // VRSQRTEfd
8641
1.14M
    16384U, // VRSQRTEfq
8642
1.14M
    16384U, // VRSQRTEhd
8643
1.14M
    16384U, // VRSQRTEhq
8644
1.14M
    16384U, // VRSQRTEq
8645
1.14M
    0U, // VRSQRTSfd
8646
1.14M
    0U, // VRSQRTSfq
8647
1.14M
    0U, // VRSQRTShd
8648
1.14M
    0U, // VRSQRTShq
8649
1.14M
    3671552U, // VRSRAsv16i8
8650
1.14M
    16768U, // VRSRAsv1i64
8651
1.14M
    3671552U, // VRSRAsv2i32
8652
1.14M
    16768U, // VRSRAsv2i64
8653
1.14M
    3671552U, // VRSRAsv4i16
8654
1.14M
    3671552U, // VRSRAsv4i32
8655
1.14M
    3671552U, // VRSRAsv8i16
8656
1.14M
    3671552U, // VRSRAsv8i8
8657
1.14M
    3671552U, // VRSRAuv16i8
8658
1.14M
    3671552U, // VRSRAuv1i64
8659
1.14M
    3671552U, // VRSRAuv2i32
8660
1.14M
    3671552U, // VRSRAuv2i64
8661
1.14M
    3671552U, // VRSRAuv4i16
8662
1.14M
    3671552U, // VRSRAuv4i32
8663
1.14M
    3671552U, // VRSRAuv8i16
8664
1.14M
    3671552U, // VRSRAuv8i8
8665
1.14M
    17920U, // VRSUBHNv2i32
8666
1.14M
    0U, // VRSUBHNv4i16
8667
1.14M
    0U, // VRSUBHNv8i8
8668
1.14M
    0U, // VSCCLRMD
8669
1.14M
    0U, // VSCCLRMS
8670
1.14M
    2U, // VSDOTD
8671
1.14M
    520U, // VSDOTDI
8672
1.14M
    2U, // VSDOTQ
8673
1.14M
    520U, // VSDOTQI
8674
1.14M
    17920U, // VSELEQD
8675
1.14M
    17920U, // VSELEQH
8676
1.14M
    17920U, // VSELEQS
8677
1.14M
    17920U, // VSELGED
8678
1.14M
    17920U, // VSELGEH
8679
1.14M
    17920U, // VSELGES
8680
1.14M
    17920U, // VSELGTD
8681
1.14M
    17920U, // VSELGTH
8682
1.14M
    17920U, // VSELGTS
8683
1.14M
    17920U, // VSELVSD
8684
1.14M
    17920U, // VSELVSH
8685
1.14M
    17920U, // VSELVSS
8686
1.14M
    32U,  // VSETLNi16
8687
1.14M
    32U,  // VSETLNi32
8688
1.14M
    32U,  // VSETLNi8
8689
1.14M
    0U, // VSHLLi16
8690
1.14M
    0U, // VSHLLi32
8691
1.14M
    0U, // VSHLLi8
8692
1.14M
    0U, // VSHLLsv2i64
8693
1.14M
    0U, // VSHLLsv4i32
8694
1.14M
    0U, // VSHLLsv8i16
8695
1.14M
    0U, // VSHLLuv2i64
8696
1.14M
    0U, // VSHLLuv4i32
8697
1.14M
    0U, // VSHLLuv8i16
8698
1.14M
    0U, // VSHLiv16i8
8699
1.14M
    17920U, // VSHLiv1i64
8700
1.14M
    0U, // VSHLiv2i32
8701
1.14M
    17920U, // VSHLiv2i64
8702
1.14M
    0U, // VSHLiv4i16
8703
1.14M
    0U, // VSHLiv4i32
8704
1.14M
    0U, // VSHLiv8i16
8705
1.14M
    0U, // VSHLiv8i8
8706
1.14M
    0U, // VSHLsv16i8
8707
1.14M
    17920U, // VSHLsv1i64
8708
1.14M
    0U, // VSHLsv2i32
8709
1.14M
    17920U, // VSHLsv2i64
8710
1.14M
    0U, // VSHLsv4i16
8711
1.14M
    0U, // VSHLsv4i32
8712
1.14M
    0U, // VSHLsv8i16
8713
1.14M
    0U, // VSHLsv8i8
8714
1.14M
    0U, // VSHLuv16i8
8715
1.14M
    0U, // VSHLuv1i64
8716
1.14M
    0U, // VSHLuv2i32
8717
1.14M
    0U, // VSHLuv2i64
8718
1.14M
    0U, // VSHLuv4i16
8719
1.14M
    0U, // VSHLuv4i32
8720
1.14M
    0U, // VSHLuv8i16
8721
1.14M
    0U, // VSHLuv8i8
8722
1.14M
    17920U, // VSHRNv2i32
8723
1.14M
    0U, // VSHRNv4i16
8724
1.14M
    0U, // VSHRNv8i8
8725
1.14M
    0U, // VSHRsv16i8
8726
1.14M
    17920U, // VSHRsv1i64
8727
1.14M
    0U, // VSHRsv2i32
8728
1.14M
    17920U, // VSHRsv2i64
8729
1.14M
    0U, // VSHRsv4i16
8730
1.14M
    0U, // VSHRsv4i32
8731
1.14M
    0U, // VSHRsv8i16
8732
1.14M
    0U, // VSHRsv8i8
8733
1.14M
    0U, // VSHRuv16i8
8734
1.14M
    0U, // VSHRuv1i64
8735
1.14M
    0U, // VSHRuv2i32
8736
1.14M
    0U, // VSHRuv2i64
8737
1.14M
    0U, // VSHRuv4i16
8738
1.14M
    0U, // VSHRuv4i32
8739
1.14M
    0U, // VSHRuv8i16
8740
1.14M
    0U, // VSHRuv8i8
8741
1.14M
    0U, // VSHTOD
8742
1.14M
    72U,  // VSHTOH
8743
1.14M
    0U, // VSHTOS
8744
1.14M
    0U, // VSITOD
8745
1.14M
    0U, // VSITOH
8746
1.14M
    0U, // VSITOS
8747
1.14M
    3671552U, // VSLIv16i8
8748
1.14M
    3671552U, // VSLIv1i64
8749
1.14M
    3671552U, // VSLIv2i32
8750
1.14M
    3671552U, // VSLIv2i64
8751
1.14M
    3671552U, // VSLIv4i16
8752
1.14M
    3671552U, // VSLIv4i32
8753
1.14M
    3671552U, // VSLIv8i16
8754
1.14M
    3671552U, // VSLIv8i8
8755
1.14M
    74U,  // VSLTOD
8756
1.14M
    74U,  // VSLTOH
8757
1.14M
    74U,  // VSLTOS
8758
1.14M
    2U, // VSMMLA
8759
1.14M
    528U, // VSQRTD
8760
1.14M
    16384U, // VSQRTH
8761
1.14M
    16384U, // VSQRTS
8762
1.14M
    3671552U, // VSRAsv16i8
8763
1.14M
    16768U, // VSRAsv1i64
8764
1.14M
    3671552U, // VSRAsv2i32
8765
1.14M
    16768U, // VSRAsv2i64
8766
1.14M
    3671552U, // VSRAsv4i16
8767
1.14M
    3671552U, // VSRAsv4i32
8768
1.14M
    3671552U, // VSRAsv8i16
8769
1.14M
    3671552U, // VSRAsv8i8
8770
1.14M
    3671552U, // VSRAuv16i8
8771
1.14M
    3671552U, // VSRAuv1i64
8772
1.14M
    3671552U, // VSRAuv2i32
8773
1.14M
    3671552U, // VSRAuv2i64
8774
1.14M
    3671552U, // VSRAuv4i16
8775
1.14M
    3671552U, // VSRAuv4i32
8776
1.14M
    3671552U, // VSRAuv8i16
8777
1.14M
    3671552U, // VSRAuv8i8
8778
1.14M
    3671552U, // VSRIv16i8
8779
1.14M
    3671552U, // VSRIv1i64
8780
1.14M
    3671552U, // VSRIv2i32
8781
1.14M
    3671552U, // VSRIv2i64
8782
1.14M
    3671552U, // VSRIv4i16
8783
1.14M
    3671552U, // VSRIv4i32
8784
1.14M
    3671552U, // VSRIv8i16
8785
1.14M
    3671552U, // VSRIv8i8
8786
1.14M
    6694U,  // VST1LNd16
8787
1.14M
    516201126U, // VST1LNd16_UPD
8788
1.14M
    6694U,  // VST1LNd32
8789
1.14M
    516201126U, // VST1LNd32_UPD
8790
1.14M
    6694U,  // VST1LNd8
8791
1.14M
    516201126U, // VST1LNd8_UPD
8792
1.14M
    0U, // VST1LNq16Pseudo
8793
1.14M
    0U, // VST1LNq16Pseudo_UPD
8794
1.14M
    0U, // VST1LNq32Pseudo
8795
1.14M
    0U, // VST1LNq32Pseudo_UPD
8796
1.14M
    0U, // VST1LNq8Pseudo
8797
1.14M
    0U, // VST1LNq8Pseudo_UPD
8798
1.14M
    0U, // VST1d16
8799
1.14M
    0U, // VST1d16Q
8800
1.14M
    0U, // VST1d16QPseudo
8801
1.14M
    0U, // VST1d16QPseudoWB_fixed
8802
1.14M
    0U, // VST1d16QPseudoWB_register
8803
1.14M
    0U, // VST1d16Qwb_fixed
8804
1.14M
    0U, // VST1d16Qwb_register
8805
1.14M
    0U, // VST1d16T
8806
1.14M
    0U, // VST1d16TPseudo
8807
1.14M
    0U, // VST1d16TPseudoWB_fixed
8808
1.14M
    0U, // VST1d16TPseudoWB_register
8809
1.14M
    0U, // VST1d16Twb_fixed
8810
1.14M
    0U, // VST1d16Twb_register
8811
1.14M
    0U, // VST1d16wb_fixed
8812
1.14M
    0U, // VST1d16wb_register
8813
1.14M
    0U, // VST1d32
8814
1.14M
    0U, // VST1d32Q
8815
1.14M
    0U, // VST1d32QPseudo
8816
1.14M
    0U, // VST1d32QPseudoWB_fixed
8817
1.14M
    0U, // VST1d32QPseudoWB_register
8818
1.14M
    0U, // VST1d32Qwb_fixed
8819
1.14M
    0U, // VST1d32Qwb_register
8820
1.14M
    0U, // VST1d32T
8821
1.14M
    0U, // VST1d32TPseudo
8822
1.14M
    0U, // VST1d32TPseudoWB_fixed
8823
1.14M
    0U, // VST1d32TPseudoWB_register
8824
1.14M
    0U, // VST1d32Twb_fixed
8825
1.14M
    0U, // VST1d32Twb_register
8826
1.14M
    0U, // VST1d32wb_fixed
8827
1.14M
    0U, // VST1d32wb_register
8828
1.14M
    0U, // VST1d64
8829
1.14M
    0U, // VST1d64Q
8830
1.14M
    0U, // VST1d64QPseudo
8831
1.14M
    0U, // VST1d64QPseudoWB_fixed
8832
1.14M
    0U, // VST1d64QPseudoWB_register
8833
1.14M
    0U, // VST1d64Qwb_fixed
8834
1.14M
    0U, // VST1d64Qwb_register
8835
1.14M
    0U, // VST1d64T
8836
1.14M
    0U, // VST1d64TPseudo
8837
1.14M
    0U, // VST1d64TPseudoWB_fixed
8838
1.14M
    0U, // VST1d64TPseudoWB_register
8839
1.14M
    0U, // VST1d64Twb_fixed
8840
1.14M
    0U, // VST1d64Twb_register
8841
1.14M
    0U, // VST1d64wb_fixed
8842
1.14M
    0U, // VST1d64wb_register
8843
1.14M
    0U, // VST1d8
8844
1.14M
    0U, // VST1d8Q
8845
1.14M
    0U, // VST1d8QPseudo
8846
1.14M
    0U, // VST1d8QPseudoWB_fixed
8847
1.14M
    0U, // VST1d8QPseudoWB_register
8848
1.14M
    0U, // VST1d8Qwb_fixed
8849
1.14M
    0U, // VST1d8Qwb_register
8850
1.14M
    0U, // VST1d8T
8851
1.14M
    0U, // VST1d8TPseudo
8852
1.14M
    0U, // VST1d8TPseudoWB_fixed
8853
1.14M
    0U, // VST1d8TPseudoWB_register
8854
1.14M
    0U, // VST1d8Twb_fixed
8855
1.14M
    0U, // VST1d8Twb_register
8856
1.14M
    0U, // VST1d8wb_fixed
8857
1.14M
    0U, // VST1d8wb_register
8858
1.14M
    0U, // VST1q16
8859
1.14M
    0U, // VST1q16HighQPseudo
8860
1.14M
    0U, // VST1q16HighQPseudo_UPD
8861
1.14M
    0U, // VST1q16HighTPseudo
8862
1.14M
    0U, // VST1q16HighTPseudo_UPD
8863
1.14M
    0U, // VST1q16LowQPseudo_UPD
8864
1.14M
    0U, // VST1q16LowTPseudo_UPD
8865
1.14M
    0U, // VST1q16wb_fixed
8866
1.14M
    0U, // VST1q16wb_register
8867
1.14M
    0U, // VST1q32
8868
1.14M
    0U, // VST1q32HighQPseudo
8869
1.14M
    0U, // VST1q32HighQPseudo_UPD
8870
1.14M
    0U, // VST1q32HighTPseudo
8871
1.14M
    0U, // VST1q32HighTPseudo_UPD
8872
1.14M
    0U, // VST1q32LowQPseudo_UPD
8873
1.14M
    0U, // VST1q32LowTPseudo_UPD
8874
1.14M
    0U, // VST1q32wb_fixed
8875
1.14M
    0U, // VST1q32wb_register
8876
1.14M
    0U, // VST1q64
8877
1.14M
    0U, // VST1q64HighQPseudo
8878
1.14M
    0U, // VST1q64HighQPseudo_UPD
8879
1.14M
    0U, // VST1q64HighTPseudo
8880
1.14M
    0U, // VST1q64HighTPseudo_UPD
8881
1.14M
    0U, // VST1q64LowQPseudo_UPD
8882
1.14M
    0U, // VST1q64LowTPseudo_UPD
8883
1.14M
    0U, // VST1q64wb_fixed
8884
1.14M
    0U, // VST1q64wb_register
8885
1.14M
    0U, // VST1q8
8886
1.14M
    0U, // VST1q8HighQPseudo
8887
1.14M
    0U, // VST1q8HighQPseudo_UPD
8888
1.14M
    0U, // VST1q8HighTPseudo
8889
1.14M
    0U, // VST1q8HighTPseudo_UPD
8890
1.14M
    0U, // VST1q8LowQPseudo_UPD
8891
1.14M
    0U, // VST1q8LowTPseudo_UPD
8892
1.14M
    0U, // VST1q8wb_fixed
8893
1.14M
    0U, // VST1q8wb_register
8894
1.14M
    440194470U, // VST2LNd16
8895
1.14M
    0U, // VST2LNd16Pseudo
8896
1.14M
    0U, // VST2LNd16Pseudo_UPD
8897
1.14M
    440718886U, // VST2LNd16_UPD
8898
1.14M
    440194470U, // VST2LNd32
8899
1.14M
    0U, // VST2LNd32Pseudo
8900
1.14M
    0U, // VST2LNd32Pseudo_UPD
8901
1.14M
    440718886U, // VST2LNd32_UPD
8902
1.14M
    440194470U, // VST2LNd8
8903
1.14M
    0U, // VST2LNd8Pseudo
8904
1.14M
    0U, // VST2LNd8Pseudo_UPD
8905
1.14M
    440718886U, // VST2LNd8_UPD
8906
1.14M
    440194470U, // VST2LNq16
8907
1.14M
    0U, // VST2LNq16Pseudo
8908
1.14M
    0U, // VST2LNq16Pseudo_UPD
8909
1.14M
    440718886U, // VST2LNq16_UPD
8910
1.14M
    440194470U, // VST2LNq32
8911
1.14M
    0U, // VST2LNq32Pseudo
8912
1.14M
    0U, // VST2LNq32Pseudo_UPD
8913
1.14M
    440718886U, // VST2LNq32_UPD
8914
1.14M
    0U, // VST2b16
8915
1.14M
    0U, // VST2b16wb_fixed
8916
1.14M
    0U, // VST2b16wb_register
8917
1.14M
    0U, // VST2b32
8918
1.14M
    0U, // VST2b32wb_fixed
8919
1.14M
    0U, // VST2b32wb_register
8920
1.14M
    0U, // VST2b8
8921
1.14M
    0U, // VST2b8wb_fixed
8922
1.14M
    0U, // VST2b8wb_register
8923
1.14M
    0U, // VST2d16
8924
1.14M
    0U, // VST2d16wb_fixed
8925
1.14M
    0U, // VST2d16wb_register
8926
1.14M
    0U, // VST2d32
8927
1.14M
    0U, // VST2d32wb_fixed
8928
1.14M
    0U, // VST2d32wb_register
8929
1.14M
    0U, // VST2d8
8930
1.14M
    0U, // VST2d8wb_fixed
8931
1.14M
    0U, // VST2d8wb_register
8932
1.14M
    0U, // VST2q16
8933
1.14M
    0U, // VST2q16Pseudo
8934
1.14M
    0U, // VST2q16PseudoWB_fixed
8935
1.14M
    0U, // VST2q16PseudoWB_register
8936
1.14M
    0U, // VST2q16wb_fixed
8937
1.14M
    0U, // VST2q16wb_register
8938
1.14M
    0U, // VST2q32
8939
1.14M
    0U, // VST2q32Pseudo
8940
1.14M
    0U, // VST2q32PseudoWB_fixed
8941
1.14M
    0U, // VST2q32PseudoWB_register
8942
1.14M
    0U, // VST2q32wb_fixed
8943
1.14M
    0U, // VST2q32wb_register
8944
1.14M
    0U, // VST2q8
8945
1.14M
    0U, // VST2q8Pseudo
8946
1.14M
    0U, // VST2q8PseudoWB_fixed
8947
1.14M
    0U, // VST2q8PseudoWB_register
8948
1.14M
    0U, // VST2q8wb_fixed
8949
1.14M
    0U, // VST2q8wb_register
8950
1.14M
    440195750U, // VST3LNd16
8951
1.14M
    0U, // VST3LNd16Pseudo
8952
1.14M
    0U, // VST3LNd16Pseudo_UPD
8953
1.14M
    6950U,  // VST3LNd16_UPD
8954
1.14M
    440195750U, // VST3LNd32
8955
1.14M
    0U, // VST3LNd32Pseudo
8956
1.14M
    0U, // VST3LNd32Pseudo_UPD
8957
1.14M
    6950U,  // VST3LNd32_UPD
8958
1.14M
    440195750U, // VST3LNd8
8959
1.14M
    0U, // VST3LNd8Pseudo
8960
1.14M
    0U, // VST3LNd8Pseudo_UPD
8961
1.14M
    6950U,  // VST3LNd8_UPD
8962
1.14M
    440195750U, // VST3LNq16
8963
1.14M
    0U, // VST3LNq16Pseudo
8964
1.14M
    0U, // VST3LNq16Pseudo_UPD
8965
1.14M
    6950U,  // VST3LNq16_UPD
8966
1.14M
    440195750U, // VST3LNq32
8967
1.14M
    0U, // VST3LNq32Pseudo
8968
1.14M
    0U, // VST3LNq32Pseudo_UPD
8969
1.14M
    6950U,  // VST3LNq32_UPD
8970
1.14M
    403177856U, // VST3d16
8971
1.14M
    0U, // VST3d16Pseudo
8972
1.14M
    0U, // VST3d16Pseudo_UPD
8973
1.14M
    383872U,  // VST3d16_UPD
8974
1.14M
    403177856U, // VST3d32
8975
1.14M
    0U, // VST3d32Pseudo
8976
1.14M
    0U, // VST3d32Pseudo_UPD
8977
1.14M
    383872U,  // VST3d32_UPD
8978
1.14M
    403177856U, // VST3d8
8979
1.14M
    0U, // VST3d8Pseudo
8980
1.14M
    0U, // VST3d8Pseudo_UPD
8981
1.14M
    383872U,  // VST3d8_UPD
8982
1.14M
    403177856U, // VST3q16
8983
1.14M
    0U, // VST3q16Pseudo_UPD
8984
1.14M
    383872U,  // VST3q16_UPD
8985
1.14M
    0U, // VST3q16oddPseudo
8986
1.14M
    0U, // VST3q16oddPseudo_UPD
8987
1.14M
    403177856U, // VST3q32
8988
1.14M
    0U, // VST3q32Pseudo_UPD
8989
1.14M
    383872U,  // VST3q32_UPD
8990
1.14M
    0U, // VST3q32oddPseudo
8991
1.14M
    0U, // VST3q32oddPseudo_UPD
8992
1.14M
    403177856U, // VST3q8
8993
1.14M
    0U, // VST3q8Pseudo_UPD
8994
1.14M
    383872U,  // VST3q8_UPD
8995
1.14M
    0U, // VST3q8oddPseudo
8996
1.14M
    0U, // VST3q8oddPseudo_UPD
8997
1.14M
    440194598U, // VST4LNd16
8998
1.14M
    0U, // VST4LNd16Pseudo
8999
1.14M
    0U, // VST4LNd16Pseudo_UPD
9000
1.14M
    399014U,  // VST4LNd16_UPD
9001
1.14M
    440194598U, // VST4LNd32
9002
1.14M
    0U, // VST4LNd32Pseudo
9003
1.14M
    0U, // VST4LNd32Pseudo_UPD
9004
1.14M
    399014U,  // VST4LNd32_UPD
9005
1.14M
    440194598U, // VST4LNd8
9006
1.14M
    0U, // VST4LNd8Pseudo
9007
1.14M
    0U, // VST4LNd8Pseudo_UPD
9008
1.14M
    399014U,  // VST4LNd8_UPD
9009
1.14M
    440194598U, // VST4LNq16
9010
1.14M
    0U, // VST4LNq16Pseudo
9011
1.14M
    0U, // VST4LNq16Pseudo_UPD
9012
1.14M
    399014U,  // VST4LNq16_UPD
9013
1.14M
    440194598U, // VST4LNq32
9014
1.14M
    0U, // VST4LNq32Pseudo
9015
1.14M
    0U, // VST4LNq32Pseudo_UPD
9016
1.14M
    399014U,  // VST4LNq32_UPD
9017
1.14M
    34079104U,  // VST4d16
9018
1.14M
    0U, // VST4d16Pseudo
9019
1.14M
    0U, // VST4d16Pseudo_UPD
9020
1.14M
    15735680U,  // VST4d16_UPD
9021
1.14M
    34079104U,  // VST4d32
9022
1.14M
    0U, // VST4d32Pseudo
9023
1.14M
    0U, // VST4d32Pseudo_UPD
9024
1.14M
    15735680U,  // VST4d32_UPD
9025
1.14M
    34079104U,  // VST4d8
9026
1.14M
    0U, // VST4d8Pseudo
9027
1.14M
    0U, // VST4d8Pseudo_UPD
9028
1.14M
    15735680U,  // VST4d8_UPD
9029
1.14M
    34079104U,  // VST4q16
9030
1.14M
    0U, // VST4q16Pseudo_UPD
9031
1.14M
    15735680U,  // VST4q16_UPD
9032
1.14M
    0U, // VST4q16oddPseudo
9033
1.14M
    0U, // VST4q16oddPseudo_UPD
9034
1.14M
    34079104U,  // VST4q32
9035
1.14M
    0U, // VST4q32Pseudo_UPD
9036
1.14M
    15735680U,  // VST4q32_UPD
9037
1.14M
    0U, // VST4q32oddPseudo
9038
1.14M
    0U, // VST4q32oddPseudo_UPD
9039
1.14M
    34079104U,  // VST4q8
9040
1.14M
    0U, // VST4q8Pseudo_UPD
9041
1.14M
    15735680U,  // VST4q8_UPD
9042
1.14M
    0U, // VST4q8oddPseudo
9043
1.14M
    0U, // VST4q8oddPseudo_UPD
9044
1.14M
    532U, // VSTMDDB_UPD
9045
1.14M
    18560U, // VSTMDIA
9046
1.14M
    532U, // VSTMDIA_UPD
9047
1.14M
    0U, // VSTMQIA
9048
1.14M
    532U, // VSTMSDB_UPD
9049
1.14M
    18560U, // VSTMSIA
9050
1.14M
    532U, // VSTMSIA_UPD
9051
1.14M
    6400U,  // VSTRD
9052
1.14M
    6528U,  // VSTRH
9053
1.14M
    6400U,  // VSTRS
9054
1.14M
    0U, // VSTR_FPCXTNS_off
9055
1.14M
    42U,  // VSTR_FPCXTNS_post
9056
1.14M
    0U, // VSTR_FPCXTNS_pre
9057
1.14M
    0U, // VSTR_FPCXTS_off
9058
1.14M
    42U,  // VSTR_FPCXTS_post
9059
1.14M
    0U, // VSTR_FPCXTS_pre
9060
1.14M
    0U, // VSTR_FPSCR_NZCVQC_off
9061
1.14M
    42U,  // VSTR_FPSCR_NZCVQC_post
9062
1.14M
    0U, // VSTR_FPSCR_NZCVQC_pre
9063
1.14M
    0U, // VSTR_FPSCR_off
9064
1.14M
    42U,  // VSTR_FPSCR_post
9065
1.14M
    0U, // VSTR_FPSCR_pre
9066
1.14M
    0U, // VSTR_P0_off
9067
1.14M
    44U,  // VSTR_P0_post
9068
1.14M
    0U, // VSTR_P0_pre
9069
1.14M
    0U, // VSTR_VPR_off
9070
1.14M
    42U,  // VSTR_VPR_post
9071
1.14M
    0U, // VSTR_VPR_pre
9072
1.14M
    2720528U, // VSUBD
9073
1.14M
    0U, // VSUBH
9074
1.14M
    17920U, // VSUBHNv2i32
9075
1.14M
    0U, // VSUBHNv4i16
9076
1.14M
    0U, // VSUBHNv8i8
9077
1.14M
    0U, // VSUBLsv2i64
9078
1.14M
    0U, // VSUBLsv4i32
9079
1.14M
    0U, // VSUBLsv8i16
9080
1.14M
    0U, // VSUBLuv2i64
9081
1.14M
    0U, // VSUBLuv4i32
9082
1.14M
    0U, // VSUBLuv8i16
9083
1.14M
    0U, // VSUBS
9084
1.14M
    0U, // VSUBWsv2i64
9085
1.14M
    0U, // VSUBWsv4i32
9086
1.14M
    0U, // VSUBWsv8i16
9087
1.14M
    0U, // VSUBWuv2i64
9088
1.14M
    0U, // VSUBWuv4i32
9089
1.14M
    0U, // VSUBWuv8i16
9090
1.14M
    0U, // VSUBfd
9091
1.14M
    0U, // VSUBfq
9092
1.14M
    0U, // VSUBhd
9093
1.14M
    0U, // VSUBhq
9094
1.14M
    0U, // VSUBv16i8
9095
1.14M
    17920U, // VSUBv1i64
9096
1.14M
    0U, // VSUBv2i32
9097
1.14M
    17920U, // VSUBv2i64
9098
1.14M
    0U, // VSUBv4i16
9099
1.14M
    0U, // VSUBv4i32
9100
1.14M
    0U, // VSUBv8i16
9101
1.14M
    0U, // VSUBv8i8
9102
1.14M
    520U, // VSUDOTDI
9103
1.14M
    520U, // VSUDOTQI
9104
1.14M
    16384U, // VSWPd
9105
1.14M
    16384U, // VSWPq
9106
1.14M
    7168U,  // VTBL1
9107
1.14M
    7296U,  // VTBL2
9108
1.14M
    7424U,  // VTBL3
9109
1.14M
    0U, // VTBL3Pseudo
9110
1.14M
    7552U,  // VTBL4
9111
1.14M
    0U, // VTBL4Pseudo
9112
1.14M
    7680U,  // VTBX1
9113
1.14M
    7808U,  // VTBX2
9114
1.14M
    7936U,  // VTBX3
9115
1.14M
    0U, // VTBX3Pseudo
9116
1.14M
    8064U,  // VTBX4
9117
1.14M
    0U, // VTBX4Pseudo
9118
1.14M
    0U, // VTOSHD
9119
1.14M
    72U,  // VTOSHH
9120
1.14M
    0U, // VTOSHS
9121
1.14M
    0U, // VTOSIRD
9122
1.14M
    0U, // VTOSIRH
9123
1.14M
    0U, // VTOSIRS
9124
1.14M
    0U, // VTOSIZD
9125
1.14M
    0U, // VTOSIZH
9126
1.14M
    0U, // VTOSIZS
9127
1.14M
    74U,  // VTOSLD
9128
1.14M
    74U,  // VTOSLH
9129
1.14M
    74U,  // VTOSLS
9130
1.14M
    0U, // VTOUHD
9131
1.14M
    72U,  // VTOUHH
9132
1.14M
    0U, // VTOUHS
9133
1.14M
    0U, // VTOUIRD
9134
1.14M
    0U, // VTOUIRH
9135
1.14M
    0U, // VTOUIRS
9136
1.14M
    0U, // VTOUIZD
9137
1.14M
    0U, // VTOUIZH
9138
1.14M
    0U, // VTOUIZS
9139
1.14M
    74U,  // VTOULD
9140
1.14M
    74U,  // VTOULH
9141
1.14M
    74U,  // VTOULS
9142
1.14M
    16384U, // VTRNd16
9143
1.14M
    16384U, // VTRNd32
9144
1.14M
    16384U, // VTRNd8
9145
1.14M
    16384U, // VTRNq16
9146
1.14M
    16384U, // VTRNq32
9147
1.14M
    16384U, // VTRNq8
9148
1.14M
    0U, // VTSTv16i8
9149
1.14M
    0U, // VTSTv2i32
9150
1.14M
    0U, // VTSTv4i16
9151
1.14M
    0U, // VTSTv4i32
9152
1.14M
    0U, // VTSTv8i16
9153
1.14M
    0U, // VTSTv8i8
9154
1.14M
    2U, // VUDOTD
9155
1.14M
    520U, // VUDOTDI
9156
1.14M
    2U, // VUDOTQ
9157
1.14M
    520U, // VUDOTQI
9158
1.14M
    0U, // VUHTOD
9159
1.14M
    72U,  // VUHTOH
9160
1.14M
    0U, // VUHTOS
9161
1.14M
    0U, // VUITOD
9162
1.14M
    0U, // VUITOH
9163
1.14M
    0U, // VUITOS
9164
1.14M
    74U,  // VULTOD
9165
1.14M
    74U,  // VULTOH
9166
1.14M
    74U,  // VULTOS
9167
1.14M
    2U, // VUMMLA
9168
1.14M
    2U, // VUSDOTD
9169
1.14M
    520U, // VUSDOTDI
9170
1.14M
    2U, // VUSDOTQ
9171
1.14M
    520U, // VUSDOTQI
9172
1.14M
    2U, // VUSMMLA
9173
1.14M
    16384U, // VUZPd16
9174
1.14M
    16384U, // VUZPd8
9175
1.14M
    16384U, // VUZPq16
9176
1.14M
    16384U, // VUZPq32
9177
1.14M
    16384U, // VUZPq8
9178
1.14M
    16384U, // VZIPd16
9179
1.14M
    16384U, // VZIPd8
9180
1.14M
    16384U, // VZIPq16
9181
1.14M
    16384U, // VZIPq32
9182
1.14M
    16384U, // VZIPq8
9183
1.14M
    411776U,  // sysLDMDA
9184
1.14M
    8212U,  // sysLDMDA_UPD
9185
1.14M
    411776U,  // sysLDMDB
9186
1.14M
    8212U,  // sysLDMDB_UPD
9187
1.14M
    411776U,  // sysLDMIA
9188
1.14M
    8212U,  // sysLDMIA_UPD
9189
1.14M
    411776U,  // sysLDMIB
9190
1.14M
    8212U,  // sysLDMIB_UPD
9191
1.14M
    411776U,  // sysSTMDA
9192
1.14M
    8212U,  // sysSTMDA_UPD
9193
1.14M
    411776U,  // sysSTMDB
9194
1.14M
    8212U,  // sysSTMDB_UPD
9195
1.14M
    411776U,  // sysSTMIA
9196
1.14M
    8212U,  // sysSTMIA_UPD
9197
1.14M
    411776U,  // sysSTMIB
9198
1.14M
    8212U,  // sysSTMIB_UPD
9199
1.14M
    0U, // t2ADCri
9200
1.14M
    0U, // t2ADCrr
9201
1.14M
    16252928U,  // t2ADCrs
9202
1.14M
    0U, // t2ADDri
9203
1.14M
    0U, // t2ADDri12
9204
1.14M
    0U, // t2ADDrr
9205
1.14M
    16252928U,  // t2ADDrs
9206
1.14M
    0U, // t2ADDspImm
9207
1.14M
    0U, // t2ADDspImm12
9208
1.14M
    1280U,  // t2ADR
9209
1.14M
    0U, // t2ANDri
9210
1.14M
    0U, // t2ANDrr
9211
1.14M
    16252928U,  // t2ANDrs
9212
1.14M
    16777216U,  // t2ASRri
9213
1.14M
    0U, // t2ASRrr
9214
1.14M
    0U, // t2AUT
9215
1.14M
    524672U,  // t2AUTG
9216
1.14M
    2U, // t2B
9217
1.14M
    1408U,  // t2BFC
9218
1.14M
    2098688U, // t2BFI
9219
1.14M
    8320U,  // t2BFLi
9220
1.14M
    16384U, // t2BFLr
9221
1.14M
    8320U,  // t2BFi
9222
1.14M
    17306624U,  // t2BFic
9223
1.14M
    16384U, // t2BFr
9224
1.14M
    0U, // t2BICri
9225
1.14M
    0U, // t2BICrr
9226
1.14M
    16252928U,  // t2BICrs
9227
1.14M
    0U, // t2BTI
9228
1.14M
    524672U,  // t2BXAUT
9229
1.14M
    2U, // t2BXJ
9230
1.14M
    2U, // t2Bcc
9231
1.14M
    82704U, // t2CDP
9232
1.14M
    82704U, // t2CDP2
9233
1.14M
    0U, // t2CLREX
9234
1.14M
    0U, // t2CLRM
9235
1.14M
    16384U, // t2CLZ
9236
1.14M
    16384U, // t2CMNri
9237
1.14M
    16384U, // t2CMNzrr
9238
1.14M
    1024U,  // t2CMNzrs
9239
1.14M
    16384U, // t2CMPri
9240
1.14M
    16384U, // t2CMPrr
9241
1.14M
    1024U,  // t2CMPrs
9242
1.14M
    0U, // t2CPS1p
9243
1.14M
    2U, // t2CPS2p
9244
1.14M
    17920U, // t2CPS3p
9245
1.14M
    17920U, // t2CRC32B
9246
1.14M
    17920U, // t2CRC32CB
9247
1.14M
    17920U, // t2CRC32CH
9248
1.14M
    17920U, // t2CRC32CW
9249
1.14M
    17920U, // t2CRC32H
9250
1.14M
    17920U, // t2CRC32W
9251
1.14M
    17303040U,  // t2CSEL
9252
1.14M
    17303040U,  // t2CSINC
9253
1.14M
    17303040U,  // t2CSINV
9254
1.14M
    17303040U,  // t2CSNEG
9255
1.14M
    2U, // t2DBG
9256
1.14M
    0U, // t2DCPS1
9257
1.14M
    0U, // t2DCPS2
9258
1.14M
    0U, // t2DCPS3
9259
1.14M
    2U, // t2DLS
9260
1.14M
    0U, // t2DMB
9261
1.14M
    0U, // t2DSB
9262
1.14M
    0U, // t2EORri
9263
1.14M
    0U, // t2EORrr
9264
1.14M
    16252928U,  // t2EORrs
9265
1.14M
    2U, // t2HINT
9266
1.14M
    0U, // t2HVC
9267
1.14M
    0U, // t2ISB
9268
1.14M
    0U, // t2IT
9269
1.14M
    0U, // t2Int_eh_sjlj_setjmp
9270
1.14M
    0U, // t2Int_eh_sjlj_setjmp_nofp
9271
1.14M
    128U, // t2LDA
9272
1.14M
    128U, // t2LDAB
9273
1.14M
    128U, // t2LDAEX
9274
1.14M
    128U, // t2LDAEXB
9275
1.14M
    11010048U,  // t2LDAEXD
9276
1.14M
    128U, // t2LDAEXH
9277
1.14M
    128U, // t2LDAH
9278
1.14M
    2582U,  // t2LDC2L_OFFSET
9279
1.14M
    4721302U, // t2LDC2L_OPTION
9280
1.14M
    5245590U, // t2LDC2L_POST
9281
1.14M
    2838U,  // t2LDC2L_PRE
9282
1.14M
    2582U,  // t2LDC2_OFFSET
9283
1.14M
    4721302U, // t2LDC2_OPTION
9284
1.14M
    5245590U, // t2LDC2_POST
9285
1.14M
    2838U,  // t2LDC2_PRE
9286
1.14M
    2582U,  // t2LDCL_OFFSET
9287
1.14M
    4721302U, // t2LDCL_OPTION
9288
1.14M
    5245590U, // t2LDCL_POST
9289
1.14M
    2838U,  // t2LDCL_PRE
9290
1.14M
    2582U,  // t2LDC_OFFSET
9291
1.14M
    4721302U, // t2LDC_OPTION
9292
1.14M
    5245590U, // t2LDC_POST
9293
1.14M
    2838U,  // t2LDC_PRE
9294
1.14M
    18560U, // t2LDMDB
9295
1.14M
    532U, // t2LDMDB_UPD
9296
1.14M
    18560U, // t2LDMIA
9297
1.14M
    532U, // t2LDMIA_UPD
9298
1.14M
    4096U,  // t2LDRBT
9299
1.14M
    133760U,  // t2LDRB_POST
9300
1.14M
    4480U,  // t2LDRB_PRE
9301
1.14M
    3200U,  // t2LDRBi12
9302
1.14M
    4096U,  // t2LDRBi8
9303
1.14M
    8448U,  // t2LDRBpci
9304
1.14M
    8576U,  // t2LDRBs
9305
1.14M
    543686656U, // t2LDRD_POST
9306
1.14M
    17825792U,  // t2LDRD_PRE
9307
1.14M
    18350080U,  // t2LDRDi8
9308
1.14M
    8704U,  // t2LDREX
9309
1.14M
    128U, // t2LDREXB
9310
1.14M
    11010048U,  // t2LDREXD
9311
1.14M
    128U, // t2LDREXH
9312
1.14M
    4096U,  // t2LDRHT
9313
1.14M
    133760U,  // t2LDRH_POST
9314
1.14M
    4480U,  // t2LDRH_PRE
9315
1.14M
    3200U,  // t2LDRHi12
9316
1.14M
    4096U,  // t2LDRHi8
9317
1.14M
    8448U,  // t2LDRHpci
9318
1.14M
    8576U,  // t2LDRHs
9319
1.14M
    4096U,  // t2LDRSBT
9320
1.14M
    133760U,  // t2LDRSB_POST
9321
1.14M
    4480U,  // t2LDRSB_PRE
9322
1.14M
    3200U,  // t2LDRSBi12
9323
1.14M
    4096U,  // t2LDRSBi8
9324
1.14M
    8448U,  // t2LDRSBpci
9325
1.14M
    8576U,  // t2LDRSBs
9326
1.14M
    4096U,  // t2LDRSHT
9327
1.14M
    133760U,  // t2LDRSH_POST
9328
1.14M
    4480U,  // t2LDRSH_PRE
9329
1.14M
    3200U,  // t2LDRSHi12
9330
1.14M
    4096U,  // t2LDRSHi8
9331
1.14M
    8448U,  // t2LDRSHpci
9332
1.14M
    8576U,  // t2LDRSHs
9333
1.14M
    4096U,  // t2LDRT
9334
1.14M
    133760U,  // t2LDR_POST
9335
1.14M
    4480U,  // t2LDR_PRE
9336
1.14M
    3200U,  // t2LDRi12
9337
1.14M
    4096U,  // t2LDRi8
9338
1.14M
    8448U,  // t2LDRpci
9339
1.14M
    8576U,  // t2LDRs
9340
1.14M
    0U, // t2LE
9341
1.14M
    0U, // t2LEUpdate
9342
1.14M
    0U, // t2LSLri
9343
1.14M
    0U, // t2LSLrr
9344
1.14M
    16777216U,  // t2LSRri
9345
1.14M
    0U, // t2LSRrr
9346
1.14M
    103908112U, // t2MCR
9347
1.14M
    103908112U, // t2MCR2
9348
1.14M
    137462544U, // t2MCRR
9349
1.14M
    137462544U, // t2MCRR2
9350
1.14M
    33554432U,  // t2MLA
9351
1.14M
    33554432U,  // t2MLS
9352
1.14M
    17920U, // t2MOVTi16
9353
1.14M
    16384U, // t2MOVi
9354
1.14M
    16384U, // t2MOVi16
9355
1.14M
    16384U, // t2MOVr
9356
1.14M
    425984U,  // t2MOVsra_glue
9357
1.14M
    425984U,  // t2MOVsrl_glue
9358
1.14M
    115480U,  // t2MRC
9359
1.14M
    115480U,  // t2MRC2
9360
1.14M
    0U, // t2MRRC
9361
1.14M
    0U, // t2MRRC2
9362
1.14M
    26U,  // t2MRS_AR
9363
1.14M
    8832U,  // t2MRS_M
9364
1.14M
    3840U,  // t2MRSbanked
9365
1.14M
    28U,  // t2MRSsys_AR
9366
1.14M
    528U, // t2MSR_AR
9367
1.14M
    528U, // t2MSR_M
9368
1.14M
    0U, // t2MSRbanked
9369
1.14M
    0U, // t2MUL
9370
1.14M
    16384U, // t2MVNi
9371
1.14M
    16384U, // t2MVNr
9372
1.14M
    1024U,  // t2MVNs
9373
1.14M
    0U, // t2ORNri
9374
1.14M
    0U, // t2ORNrr
9375
1.14M
    16252928U,  // t2ORNrs
9376
1.14M
    0U, // t2ORRri
9377
1.14M
    0U, // t2ORRrr
9378
1.14M
    16252928U,  // t2ORRrs
9379
1.14M
    0U, // t2PAC
9380
1.14M
    0U, // t2PACBTI
9381
1.14M
    524672U,  // t2PACG
9382
1.14M
    201326592U, // t2PKHBT
9383
1.14M
    234881024U, // t2PKHTB
9384
1.14M
    0U, // t2PLDWi12
9385
1.14M
    1U, // t2PLDWi8
9386
1.14M
    1U, // t2PLDWs
9387
1.14M
    0U, // t2PLDi12
9388
1.14M
    1U, // t2PLDi8
9389
1.14M
    1U, // t2PLDpci
9390
1.14M
    1U, // t2PLDs
9391
1.14M
    0U, // t2PLIi12
9392
1.14M
    1U, // t2PLIi8
9393
1.14M
    1U, // t2PLIpci
9394
1.14M
    1U, // t2PLIs
9395
1.14M
    0U, // t2QADD
9396
1.14M
    0U, // t2QADD16
9397
1.14M
    0U, // t2QADD8
9398
1.14M
    0U, // t2QASX
9399
1.14M
    0U, // t2QDADD
9400
1.14M
    0U, // t2QDSUB
9401
1.14M
    0U, // t2QSAX
9402
1.14M
    0U, // t2QSUB
9403
1.14M
    0U, // t2QSUB16
9404
1.14M
    0U, // t2QSUB8
9405
1.14M
    16384U, // t2RBIT
9406
1.14M
    16384U, // t2REV
9407
1.14M
    16384U, // t2REV16
9408
1.14M
    16384U, // t2REVSH
9409
1.14M
    2U, // t2RFEDB
9410
1.14M
    4U, // t2RFEDBW
9411
1.14M
    2U, // t2RFEIA
9412
1.14M
    4U, // t2RFEIAW
9413
1.14M
    0U, // t2RORri
9414
1.14M
    0U, // t2RORrr
9415
1.14M
    16384U, // t2RRX
9416
1.14M
    0U, // t2RSBri
9417
1.14M
    0U, // t2RSBrr
9418
1.14M
    16252928U,  // t2RSBrs
9419
1.14M
    0U, // t2SADD16
9420
1.14M
    0U, // t2SADD8
9421
1.14M
    0U, // t2SASX
9422
1.14M
    0U, // t2SB
9423
1.14M
    0U, // t2SBCri
9424
1.14M
    0U, // t2SBCrr
9425
1.14M
    16252928U,  // t2SBCrs
9426
1.14M
    33554432U,  // t2SBFX
9427
1.14M
    0U, // t2SDIV
9428
1.14M
    0U, // t2SEL
9429
1.14M
    0U, // t2SETPAN
9430
1.14M
    0U, // t2SG
9431
1.14M
    0U, // t2SHADD16
9432
1.14M
    0U, // t2SHADD8
9433
1.14M
    0U, // t2SHASX
9434
1.14M
    0U, // t2SHSAX
9435
1.14M
    0U, // t2SHSUB16
9436
1.14M
    0U, // t2SHSUB8
9437
1.14M
    2U, // t2SMC
9438
1.14M
    33554432U,  // t2SMLABB
9439
1.14M
    33554432U,  // t2SMLABT
9440
1.14M
    33554432U,  // t2SMLAD
9441
1.14M
    33554432U,  // t2SMLADX
9442
1.14M
    33554432U,  // t2SMLAL
9443
1.14M
    33554432U,  // t2SMLALBB
9444
1.14M
    33554432U,  // t2SMLALBT
9445
1.14M
    33554432U,  // t2SMLALD
9446
1.14M
    33554432U,  // t2SMLALDX
9447
1.14M
    33554432U,  // t2SMLALTB
9448
1.14M
    33554432U,  // t2SMLALTT
9449
1.14M
    33554432U,  // t2SMLATB
9450
1.14M
    33554432U,  // t2SMLATT
9451
1.14M
    33554432U,  // t2SMLAWB
9452
1.14M
    33554432U,  // t2SMLAWT
9453
1.14M
    33554432U,  // t2SMLSD
9454
1.14M
    33554432U,  // t2SMLSDX
9455
1.14M
    33554432U,  // t2SMLSLD
9456
1.14M
    33554432U,  // t2SMLSLDX
9457
1.14M
    33554432U,  // t2SMMLA
9458
1.14M
    33554432U,  // t2SMMLAR
9459
1.14M
    33554432U,  // t2SMMLS
9460
1.14M
    33554432U,  // t2SMMLSR
9461
1.14M
    0U, // t2SMMUL
9462
1.14M
    0U, // t2SMMULR
9463
1.14M
    0U, // t2SMUAD
9464
1.14M
    0U, // t2SMUADX
9465
1.14M
    0U, // t2SMULBB
9466
1.14M
    0U, // t2SMULBT
9467
1.14M
    33554432U,  // t2SMULL
9468
1.14M
    0U, // t2SMULTB
9469
1.14M
    0U, // t2SMULTT
9470
1.14M
    0U, // t2SMULWB
9471
1.14M
    0U, // t2SMULWT
9472
1.14M
    0U, // t2SMUSD
9473
1.14M
    0U, // t2SMUSDX
9474
1.14M
    0U, // t2SRSDB
9475
1.14M
    0U, // t2SRSDB_UPD
9476
1.14M
    0U, // t2SRSIA
9477
1.14M
    0U, // t2SRSIA_UPD
9478
1.14M
    218240U,  // t2SSAT
9479
1.14M
    21632U, // t2SSAT16
9480
1.14M
    0U, // t2SSAX
9481
1.14M
    0U, // t2SSUB16
9482
1.14M
    0U, // t2SSUB8
9483
1.14M
    2582U,  // t2STC2L_OFFSET
9484
1.14M
    4721302U, // t2STC2L_OPTION
9485
1.14M
    5245590U, // t2STC2L_POST
9486
1.14M
    2838U,  // t2STC2L_PRE
9487
1.14M
    2582U,  // t2STC2_OFFSET
9488
1.14M
    4721302U, // t2STC2_OPTION
9489
1.14M
    5245590U, // t2STC2_POST
9490
1.14M
    2838U,  // t2STC2_PRE
9491
1.14M
    2582U,  // t2STCL_OFFSET
9492
1.14M
    4721302U, // t2STCL_OPTION
9493
1.14M
    5245590U, // t2STCL_POST
9494
1.14M
    2838U,  // t2STCL_PRE
9495
1.14M
    2582U,  // t2STC_OFFSET
9496
1.14M
    4721302U, // t2STC_OPTION
9497
1.14M
    5245590U, // t2STC_POST
9498
1.14M
    2838U,  // t2STC_PRE
9499
1.14M
    128U, // t2STL
9500
1.14M
    128U, // t2STLB
9501
1.14M
    11010048U,  // t2STLEX
9502
1.14M
    11010048U,  // t2STLEXB
9503
1.14M
    33554432U,  // t2STLEXD
9504
1.14M
    11010048U,  // t2STLEXH
9505
1.14M
    128U, // t2STLH
9506
1.14M
    18560U, // t2STMDB
9507
1.14M
    532U, // t2STMDB_UPD
9508
1.14M
    18560U, // t2STMIA
9509
1.14M
    532U, // t2STMIA_UPD
9510
1.14M
    4096U,  // t2STRBT
9511
1.14M
    133760U,  // t2STRB_POST
9512
1.14M
    4480U,  // t2STRB_PRE
9513
1.14M
    3200U,  // t2STRBi12
9514
1.14M
    4096U,  // t2STRBi8
9515
1.14M
    8576U,  // t2STRBs
9516
1.14M
    543688192U, // t2STRD_POST
9517
1.14M
    17827328U,  // t2STRD_PRE
9518
1.14M
    18350080U,  // t2STRDi8
9519
1.14M
    18874368U,  // t2STREX
9520
1.14M
    11010048U,  // t2STREXB
9521
1.14M
    33554432U,  // t2STREXD
9522
1.14M
    11010048U,  // t2STREXH
9523
1.14M
    4096U,  // t2STRHT
9524
1.14M
    133760U,  // t2STRH_POST
9525
1.14M
    4480U,  // t2STRH_PRE
9526
1.14M
    3200U,  // t2STRHi12
9527
1.14M
    4096U,  // t2STRHi8
9528
1.14M
    8576U,  // t2STRHs
9529
1.14M
    4096U,  // t2STRT
9530
1.14M
    133760U,  // t2STR_POST
9531
1.14M
    4480U,  // t2STR_PRE
9532
1.14M
    3200U,  // t2STRi12
9533
1.14M
    4096U,  // t2STRi8
9534
1.14M
    8576U,  // t2STRs
9535
1.14M
    0U, // t2SUBS_PC_LR
9536
1.14M
    0U, // t2SUBri
9537
1.14M
    0U, // t2SUBri12
9538
1.14M
    0U, // t2SUBrr
9539
1.14M
    16252928U,  // t2SUBrs
9540
1.14M
    0U, // t2SUBspImm
9541
1.14M
    0U, // t2SUBspImm12
9542
1.14M
    268435456U, // t2SXTAB
9543
1.14M
    268435456U, // t2SXTAB16
9544
1.14M
    268435456U, // t2SXTAH
9545
1.14M
    229376U,  // t2SXTB
9546
1.14M
    229376U,  // t2SXTB16
9547
1.14M
    229376U,  // t2SXTH
9548
1.14M
    1U, // t2TBB
9549
1.14M
    1U, // t2TBH
9550
1.14M
    16384U, // t2TEQri
9551
1.14M
    16384U, // t2TEQrr
9552
1.14M
    1024U,  // t2TEQrs
9553
1.14M
    1U, // t2TSB
9554
1.14M
    16384U, // t2TSTri
9555
1.14M
    16384U, // t2TSTrr
9556
1.14M
    1024U,  // t2TSTrs
9557
1.14M
    16384U, // t2TT
9558
1.14M
    16384U, // t2TTA
9559
1.14M
    16384U, // t2TTAT
9560
1.14M
    16384U, // t2TTT
9561
1.14M
    0U, // t2UADD16
9562
1.14M
    0U, // t2UADD8
9563
1.14M
    0U, // t2UASX
9564
1.14M
    33554432U,  // t2UBFX
9565
1.14M
    0U, // t2UDF
9566
1.14M
    0U, // t2UDIV
9567
1.14M
    0U, // t2UHADD16
9568
1.14M
    0U, // t2UHADD8
9569
1.14M
    0U, // t2UHASX
9570
1.14M
    0U, // t2UHSAX
9571
1.14M
    0U, // t2UHSUB16
9572
1.14M
    0U, // t2UHSUB8
9573
1.14M
    33554432U,  // t2UMAAL
9574
1.14M
    33554432U,  // t2UMLAL
9575
1.14M
    33554432U,  // t2UMULL
9576
1.14M
    0U, // t2UQADD16
9577
1.14M
    0U, // t2UQADD8
9578
1.14M
    0U, // t2UQASX
9579
1.14M
    0U, // t2UQSAX
9580
1.14M
    0U, // t2UQSUB16
9581
1.14M
    0U, // t2UQSUB8
9582
1.14M
    0U, // t2USAD8
9583
1.14M
    33554432U,  // t2USADA8
9584
1.14M
    301989888U, // t2USAT
9585
1.14M
    0U, // t2USAT16
9586
1.14M
    0U, // t2USAX
9587
1.14M
    0U, // t2USUB16
9588
1.14M
    0U, // t2USUB8
9589
1.14M
    268435456U, // t2UXTAB
9590
1.14M
    268435456U, // t2UXTAB16
9591
1.14M
    268435456U, // t2UXTAH
9592
1.14M
    229376U,  // t2UXTB
9593
1.14M
    229376U,  // t2UXTB16
9594
1.14M
    229376U,  // t2UXTH
9595
1.14M
    21504U, // t2WLS
9596
1.14M
    2U, // tADC
9597
1.14M
    17920U, // tADDhirr
9598
1.14M
    16768U, // tADDi3
9599
1.14M
    2U, // tADDi8
9600
1.14M
    0U, // tADDrSP
9601
1.14M
    19398656U,  // tADDrSPi
9602
1.14M
    16768U, // tADDrr
9603
1.14M
    8960U,  // tADDspi
9604
1.14M
    17920U, // tADDspr
9605
1.14M
    9088U,  // tADR
9606
1.14M
    2U, // tAND
9607
1.14M
    9216U,  // tASRri
9608
1.14M
    2U, // tASRrr
9609
1.14M
    2U, // tB
9610
1.14M
    2U, // tBIC
9611
1.14M
    0U, // tBKPT
9612
1.14M
    1U, // tBL
9613
1.14M
    2U, // tBLXNSr
9614
1.14M
    1U, // tBLXi
9615
1.14M
    2U, // tBLXr
9616
1.14M
    2U, // tBX
9617
1.14M
    2U, // tBXNS
9618
1.14M
    2U, // tBcc
9619
1.14M
    2U, // tCBNZ
9620
1.14M
    2U, // tCBZ
9621
1.14M
    16384U, // tCMNz
9622
1.14M
    16384U, // tCMPhir
9623
1.14M
    16384U, // tCMPi8
9624
1.14M
    16384U, // tCMPr
9625
1.14M
    2U, // tCPS
9626
1.14M
    2U, // tEOR
9627
1.14M
    2U, // tHINT
9628
1.14M
    0U, // tHLT
9629
1.14M
    0U, // tInt_WIN_eh_sjlj_longjmp
9630
1.14M
    0U, // tInt_eh_sjlj_longjmp
9631
1.14M
    0U, // tInt_eh_sjlj_setjmp
9632
1.14M
    18560U, // tLDMIA
9633
1.14M
    9344U,  // tLDRBi
9634
1.14M
    9472U,  // tLDRBr
9635
1.14M
    9600U,  // tLDRHi
9636
1.14M
    9472U,  // tLDRHr
9637
1.14M
    9472U,  // tLDRSB
9638
1.14M
    9472U,  // tLDRSH
9639
1.14M
    9728U,  // tLDRi
9640
1.14M
    8448U,  // tLDRpci
9641
1.14M
    9472U,  // tLDRr
9642
1.14M
    9856U,  // tLDRspi
9643
1.14M
    16768U, // tLSLri
9644
1.14M
    2U, // tLSLrr
9645
1.14M
    9216U,  // tLSRri
9646
1.14M
    2U, // tLSRrr
9647
1.14M
    2U, // tMOVSr
9648
1.14M
    0U, // tMOVi8
9649
1.14M
    16384U, // tMOVr
9650
1.14M
    16768U, // tMUL
9651
1.14M
    0U, // tMVN
9652
1.14M
    2U, // tORR
9653
1.14M
    0U, // tPICADD
9654
1.14M
    0U, // tPOP
9655
1.14M
    0U, // tPUSH
9656
1.14M
    16384U, // tREV
9657
1.14M
    16384U, // tREV16
9658
1.14M
    16384U, // tREVSH
9659
1.14M
    2U, // tROR
9660
1.14M
    0U, // tRSB
9661
1.14M
    2U, // tSBC
9662
1.14M
    0U, // tSETEND
9663
1.14M
    532U, // tSTMIA_UPD
9664
1.14M
    9344U,  // tSTRBi
9665
1.14M
    9472U,  // tSTRBr
9666
1.14M
    9600U,  // tSTRHi
9667
1.14M
    9472U,  // tSTRHr
9668
1.14M
    9728U,  // tSTRi
9669
1.14M
    9472U,  // tSTRr
9670
1.14M
    9856U,  // tSTRspi
9671
1.14M
    16768U, // tSUBi3
9672
1.14M
    2U, // tSUBi8
9673
1.14M
    16768U, // tSUBrr
9674
1.14M
    8960U,  // tSUBspi
9675
1.14M
    2U, // tSVC
9676
1.14M
    16384U, // tSXTB
9677
1.14M
    16384U, // tSXTH
9678
1.14M
    0U, // tTRAP
9679
1.14M
    16384U, // tTST
9680
1.14M
    0U, // tUDF
9681
1.14M
    16384U, // tUXTB
9682
1.14M
    16384U, // tUXTH
9683
1.14M
    0U, // t__brkdiv0
9684
1.14M
  };
9685
9686
  // Emit the opcode for the instruction.
9687
1.14M
  uint64_t Bits = 0;
9688
1.14M
  Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0;
9689
1.14M
  Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32;
9690
1.14M
  MnemonicBitsInfo MBI = {
9691
1.14M
#ifndef CAPSTONE_DIET
9692
1.14M
    AsmStrs+(Bits & 8191)-1,
9693
#else
9694
    NULL,
9695
#endif // CAPSTONE_DIET
9696
1.14M
    Bits
9697
1.14M
  };
9698
1.14M
  return MBI;
9699
1.14M
}
9700
9701
/// printInstruction - This method is automatically generated by tablegen
9702
/// from the instruction set description.
9703
1.14M
static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
9704
1.14M
  SStream_concat0(O, "");
9705
1.14M
  MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O);
9706
9707
1.14M
  SStream_concat0(O, MnemonicInfo.first);
9708
9709
1.14M
  uint64_t Bits = MnemonicInfo.second;
9710
1.14M
  CS_ASSERT_RET(Bits != 0 && "Cannot print this instruction.");
9711
9712
  // Fragment 0 encoded into 6 bits for 43 unique commands.
9713
1.14M
  switch ((Bits >> 13) & 63) {
9714
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
9715
1.35k
  case 0:
9716
    // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
9717
1.35k
    return;
9718
0
    break;
9719
19.0k
  case 1:
9720
    // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, ADCri, ADCrr, ADDri, A...
9721
19.0k
    printSBitModifierOperand(MI, 5, O);
9722
19.0k
    printPredicateOperand(MI, 3, O);
9723
19.0k
    break;
9724
9.91k
  case 2:
9725
    // ITasm, t2IT
9726
9.91k
    printThumbITMask(MI, 1, O);
9727
9.91k
    break;
9728
142k
  case 3:
9729
    // LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHTii, LDRT_POST, STRB...
9730
142k
    printPredicateOperand(MI, 2, O);
9731
142k
    break;
9732
3.05k
  case 4:
9733
    // RRXi, MOVi, MOVr, MOVr_TC, MVNi, MVNr, t2MOVi, t2MOVr, t2MVNi, t2MVNr,...
9734
3.05k
    printSBitModifierOperand(MI, 4, O);
9735
3.05k
    printPredicateOperand(MI, 2, O);
9736
3.05k
    break;
9737
77.6k
  case 5:
9738
    // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL...
9739
77.6k
    printPredicateOperand(MI, 4, O);
9740
77.6k
    break;
9741
51.0k
  case 6:
9742
    // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist...
9743
51.0k
    printPredicateOperand(MI, 5, O);
9744
51.0k
    break;
9745
260k
  case 7:
9746
    // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16...
9747
260k
    printPredicateOperand(MI, 3, O);
9748
260k
    break;
9749
15.0k
  case 8:
9750
    // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, MLA, MOVsr, MVNsr, ORRrsi, RSB...
9751
15.0k
    printSBitModifierOperand(MI, 6, O);
9752
15.0k
    printPredicateOperand(MI, 4, O);
9753
15.0k
    break;
9754
4.42k
  case 9:
9755
    // ADCrsr, ADDrsr, ANDrsr, BICrsr, EORrsr, ORRrsr, RSBrsr, RSCrsr, SBCrsr...
9756
4.42k
    printSBitModifierOperand(MI, 7, O);
9757
4.42k
    printPredicateOperand(MI, 5, O);
9758
4.42k
    SStream_concat0(O, "\t");
9759
4.42k
    printOperand(MI, 0, O);
9760
4.42k
    SStream_concat0(O, ", ");
9761
4.42k
    printOperand(MI, 1, O);
9762
4.42k
    SStream_concat0(O, ", ");
9763
4.42k
    printSORegRegOperand(MI, 2, O);
9764
4.42k
    return;
9765
0
    break;
9766
88.1k
  case 10:
9767
    // AESD, AESE, AESIMC, AESMC, BKPT, BLX, BX, CPS1p, CRC32B, CRC32CB, CRC3...
9768
88.1k
    printOperand(MI, 0, O);
9769
88.1k
    break;
9770
1.16k
  case 11:
9771
    // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, BF16VDOTS_VDOTQ, MV...
9772
1.16k
    printOperand(MI, 1, O);
9773
1.16k
    SStream_concat0(O, ", ");
9774
1.16k
    break;
9775
2.59k
  case 12:
9776
    // BL, BLXi, t2BFic, t2LE
9777
2.59k
    printOperandAddr(MI, Address, 0, O);
9778
2.59k
    break;
9779
73.0k
  case 13:
9780
    // BLX_pred, BL_pred, BXJ, BX_pred, Bcc, DBG, FLDMXIA, FSTMXIA, HINT, LDM...
9781
73.0k
    printPredicateOperand(MI, 1, O);
9782
73.0k
    break;
9783
14.2k
  case 14:
9784
    // BX_RET, ERET, FMSTAT, MOVPCLR, MVE_LCTP, VSCCLRMD, VSCCLRMS, t2AUTG, t...
9785
14.2k
    printPredicateOperand(MI, 0, O);
9786
14.2k
    break;
9787
386
  case 15:
9788
    // CDE_CX1, CDE_CX1D, CDE_CX2, CDE_CX2D, CDE_CX3, CDE_CX3D, CDE_VCX1A_fpd...
9789
386
    printPImmediate(MI, 1, O);
9790
386
    SStream_concat0(O, ", ");
9791
386
    break;
9792
44.0k
  case 16:
9793
    // CDE_CX3A, CDE_CX3DA, CDP, LDRD_POST, LDRD_PRE, MCR, MRC, MVE_SQRSHRL, ...
9794
44.0k
    printPredicateOperand(MI, 6, O);
9795
44.0k
    break;
9796
16.5k
  case 17:
9797
    // CDE_VCX1A_vec, CDE_VCX2_vec, MVE_VABAVs16, MVE_VABAVs32, MVE_VABAVs8, ...
9798
16.5k
    printVPTPredicateOperand(MI, 4, O);
9799
16.5k
    break;
9800
11.3k
  case 18:
9801
    // CDE_VCX1_vec, MVE_VABDf16, MVE_VABDf32, MVE_VABDs16, MVE_VABDs32, MVE_...
9802
11.3k
    printVPTPredicateOperand(MI, 3, O);
9803
11.3k
    break;
9804
2.38k
  case 19:
9805
    // CDE_VCX2A_vec, CDE_VCX3_vec, MVE_VADC, MVE_VADDLVs32acc, MVE_VADDLVu32...
9806
2.38k
    printVPTPredicateOperand(MI, 5, O);
9807
2.38k
    break;
9808
3.19k
  case 20:
9809
    // CDE_VCX3A_vec, MVE_VMLALDAVas16, MVE_VMLALDAVas32, MVE_VMLALDAVau16, M...
9810
3.19k
    printVPTPredicateOperand(MI, 6, O);
9811
3.19k
    break;
9812
4.96k
  case 21:
9813
    // CDP2, LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, ...
9814
4.96k
    printPImmediate(MI, 0, O);
9815
4.96k
    SStream_concat0(O, ", ");
9816
4.96k
    break;
9817
1.89k
  case 22:
9818
    // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS
9819
1.89k
    printCPSIMod(MI, 0, O);
9820
1.89k
    break;
9821
1.27k
  case 23:
9822
    // DMB, DSB
9823
1.27k
    printMemBOption(MI, 0, O);
9824
1.27k
    return;
9825
0
    break;
9826
997
  case 24:
9827
    // ISB
9828
997
    printInstSyncBOption(MI, 0, O);
9829
997
    return;
9830
0
    break;
9831
426
  case 25:
9832
    // MRRC2
9833
426
    printPImmediate(MI, 2, O);
9834
426
    SStream_concat0(O, ", ");
9835
426
    printOperand(MI, 3, O);
9836
426
    SStream_concat0(O, ", ");
9837
426
    printOperand(MI, 0, O);
9838
426
    SStream_concat0(O, ", ");
9839
426
    printOperand(MI, 1, O);
9840
426
    SStream_concat0(O, ", ");
9841
426
    printCImmediate(MI, 4, O);
9842
426
    return;
9843
0
    break;
9844
3.25k
  case 26:
9845
    // MVE_VABSf16, MVE_VABSf32, MVE_VABSs16, MVE_VABSs32, MVE_VABSs8, MVE_VA...
9846
3.25k
    printVPTPredicateOperand(MI, 2, O);
9847
3.25k
    break;
9848
1.46k
  case 27:
9849
    // MVE_VLD20_16, MVE_VLD20_16_wb, MVE_VLD20_32, MVE_VLD20_32_wb, MVE_VLD2...
9850
1.46k
    printMVEVectorList_2(MI, 0, O);
9851
1.46k
    SStream_concat0(O, ", ");
9852
1.46k
    break;
9853
1.69k
  case 28:
9854
    // MVE_VLD40_16, MVE_VLD40_16_wb, MVE_VLD40_32, MVE_VLD40_32_wb, MVE_VLD4...
9855
1.69k
    printMVEVectorList_4(MI, 0, O);
9856
1.69k
    SStream_concat0(O, ", ");
9857
1.69k
    break;
9858
7.34k
  case 29:
9859
    // MVE_VPST, MVE_VPTv16i8, MVE_VPTv16i8r, MVE_VPTv16s8, MVE_VPTv16s8r, MV...
9860
7.34k
    printVPTMask(MI, 0, O);
9861
7.34k
    break;
9862
91
  case 30:
9863
    // MVE_VST20_16_wb, MVE_VST20_32_wb, MVE_VST20_8_wb, MVE_VST21_16_wb, MVE...
9864
91
    printMVEVectorList_2(MI, 1, O);
9865
91
    SStream_concat0(O, ", ");
9866
91
    printAddrMode7Operand(MI, 2, O);
9867
91
    SStream_concat1(O, '!');
9868
91
    return;
9869
0
    break;
9870
410
  case 31:
9871
    // MVE_VST40_16_wb, MVE_VST40_32_wb, MVE_VST40_8_wb, MVE_VST41_16_wb, MVE...
9872
410
    printMVEVectorList_4(MI, 1, O);
9873
410
    SStream_concat0(O, ", ");
9874
410
    printAddrMode7Operand(MI, 2, O);
9875
410
    SStream_concat1(O, '!');
9876
410
    return;
9877
0
    break;
9878
73
  case 32:
9879
    // PLDWi12, PLDi12, PLIi12
9880
73
    printAddrModeImm12Operand_0(MI, 0, O);
9881
73
    return;
9882
0
    break;
9883
40
  case 33:
9884
    // PLDWrs, PLDrs, PLIrs
9885
40
    printAddrMode2Operand(MI, 0, O);
9886
40
    return;
9887
0
    break;
9888
141
  case 34:
9889
    // SETEND, tSETEND
9890
141
    printSetendOperand(MI, 0, O);
9891
141
    return;
9892
0
    break;
9893
446
  case 35:
9894
    // SMLAL, UMLAL
9895
446
    printSBitModifierOperand(MI, 8, O);
9896
446
    printPredicateOperand(MI, 6, O);
9897
446
    SStream_concat0(O, "\t");
9898
446
    printOperand(MI, 0, O);
9899
446
    SStream_concat0(O, ", ");
9900
446
    printOperand(MI, 1, O);
9901
446
    SStream_concat0(O, ", ");
9902
446
    printOperand(MI, 2, O);
9903
446
    SStream_concat0(O, ", ");
9904
446
    printOperand(MI, 3, O);
9905
446
    return;
9906
0
    break;
9907
0
  case 36:
9908
    // TSB
9909
0
    printTraceSyncBOption(MI, 0, O);
9910
0
    return;
9911
0
    break;
9912
8.63k
  case 37:
9913
    // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2...
9914
8.63k
    printPredicateOperand(MI, 7, O);
9915
8.63k
    break;
9916
3.46k
  case 38:
9917
    // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U...
9918
3.46k
    printPredicateOperand(MI, 9, O);
9919
3.46k
    break;
9920
2.10k
  case 39:
9921
    // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U...
9922
2.10k
    printPredicateOperand(MI, 11, O);
9923
2.10k
    break;
9924
5.08k
  case 40:
9925
    // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP...
9926
5.08k
    printPredicateOperand(MI, 8, O);
9927
5.08k
    break;
9928
1.35k
  case 41:
9929
    // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U...
9930
1.35k
    printPredicateOperand(MI, 13, O);
9931
1.35k
    break;
9932
260k
  case 42:
9933
    // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
9934
260k
    printSBitModifierOperand(MI, 1, O);
9935
260k
    break;
9936
1.14M
  }
9937
9938
9939
  // Fragment 1 encoded into 7 bits for 89 unique commands.
9940
1.13M
  switch ((Bits >> 19) & 127) {
9941
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
9942
164
  case 0:
9943
    // ASRi, ASRr, ITasm, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHT...
9944
164
    SStream_concat1(O, ' ');
9945
164
    break;
9946
14.0k
  case 1:
9947
    // VLD1LNdAsm_16, VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_register_Asm_16, VLD2...
9948
14.0k
    SStream_concat0(O, ".16\t");
9949
14.0k
    ARM_add_vector_size(MI, 16);
9950
14.0k
    break;
9951
14.4k
  case 2:
9952
    // VLD1LNdAsm_32, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_register_Asm_32, VLD2...
9953
14.4k
    SStream_concat0(O, ".32\t");
9954
14.4k
    ARM_add_vector_size(MI, 32);
9955
14.4k
    break;
9956
11.3k
  case 3:
9957
    // VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_8, VLD1LNdWB_register_Asm_8, VLD2LNd...
9958
11.3k
    SStream_concat0(O, ".8\t");
9959
11.3k
    ARM_add_vector_size(MI, 8);
9960
11.3k
    break;
9961
0
  case 4:
9962
    // t2LDRB_OFFSET_imm, t2LDRB_POST_imm, t2LDRB_PRE_imm, t2LDRH_OFFSET_imm,...
9963
0
    SStream_concat0(O, ".w ");
9964
0
    printOperand(MI, 0, O);
9965
0
    SStream_concat0(O, ", ");
9966
0
    break;
9967
593k
  case 5:
9968
    // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,...
9969
593k
    SStream_concat0(O, "\t");
9970
593k
    break;
9971
82.3k
  case 6:
9972
    // AESD, AESE, AESIMC, AESMC, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, ...
9973
82.3k
    SStream_concat0(O, ", ");
9974
82.3k
    break;
9975
1.35k
  case 7:
9976
    // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, BF16VDOTS_VDOTQ, MR...
9977
1.35k
    printOperand(MI, 2, O);
9978
1.35k
    SStream_concat0(O, ", ");
9979
1.35k
    break;
9980
90
  case 8:
9981
    // BF16_VCVT, BF16_VCVTB, BF16_VCVTT
9982
90
    SStream_concat0(O, ".bf16.f32\t");
9983
90
    printOperand(MI, 0, O);
9984
90
    SStream_concat0(O, ", ");
9985
90
    break;
9986
7.51k
  case 9:
9987
    // BKPT, BL, BLX, BLXi, BX, CPS1p, ERET, HLT, HVC, RFEDA, RFEDB, RFEIA, R...
9988
7.51k
    return;
9989
0
    break;
9990
81
  case 10:
9991
    // BX_RET
9992
81
    SStream_concat0(O, "\tlr");
9993
81
    return;
9994
0
    break;
9995
0
  case 11:
9996
    // CDE_CX1, CDE_CX2, CDE_CX3, CDE_VCX1A_fpdp, CDE_VCX1A_fpsp, CDE_VCX1_fp...
9997
0
    printOperand(MI, 0, O);
9998
0
    SStream_concat0(O, ", ");
9999
0
    break;
10000
0
  case 12:
10001
    // CDE_CX1D, CDE_CX2D, CDE_CX3D
10002
0
    printGPRPairOperand(MI, 0, O);
10003
0
    SStream_concat0(O, ", ");
10004
0
    printOperand(MI, 2, O);
10005
0
    break;
10006
1.17k
  case 13:
10007
    // CDP2, MCR2, MCRR2
10008
1.17k
    printOperand(MI, 1, O);
10009
1.17k
    SStream_concat0(O, ", ");
10010
1.17k
    break;
10011
1.70k
  case 14:
10012
    // FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VFMAD, V...
10013
1.70k
    SStream_concat0(O, ".f64\t");
10014
1.70k
    ARM_add_vector_data(MI, ARM_VECTORDATA_F64);
10015
1.70k
    printOperand(MI, 0, O);
10016
1.70k
    break;
10017
5.61k
  case 15:
10018
    // FCONSTH, MVE_VABDf16, MVE_VABSf16, MVE_VADD_qr_f16, MVE_VADDf16, MVE_V...
10019
5.61k
    SStream_concat0(O, ".f16\t");
10020
5.61k
    ARM_add_vector_data(MI, ARM_VECTORDATA_F16);
10021
5.61k
    break;
10022
6.70k
  case 16:
10023
    // FCONSTS, MVE_VABDf32, MVE_VABSf32, MVE_VADD_qr_f32, MVE_VADDf32, MVE_V...
10024
6.70k
    SStream_concat0(O, ".f32\t");
10025
6.70k
    ARM_add_vector_data(MI, ARM_VECTORDATA_F32);
10026
6.70k
    break;
10027
83
  case 17:
10028
    // FMSTAT
10029
83
    SStream_concat0(O, "\tAPSR_nzcv, fpscr");
10030
83
    return;
10031
0
    break;
10032
3.79k
  case 18:
10033
    // LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, LDC2_O...
10034
3.79k
    printCImmediate(MI, 1, O);
10035
3.79k
    SStream_concat0(O, ", ");
10036
3.79k
    break;
10037
39
  case 19:
10038
    // MOVPCLR
10039
39
    SStream_concat0(O, "\tpc, lr");
10040
39
    return;
10041
0
    break;
10042
201
  case 20:
10043
    // MVE_LETP, t2LEUpdate
10044
201
    printOperandAddr(MI, Address, 2, O);
10045
201
    return;
10046
0
    break;
10047
7.12k
  case 21:
10048
    // MVE_VABAVs16, MVE_VABDs16, MVE_VABSs16, MVE_VADDVs16acc, MVE_VADDVs16n...
10049
7.12k
    SStream_concat0(O, ".s16\t");
10050
7.12k
    ARM_add_vector_data(MI, ARM_VECTORDATA_S16);
10051
7.12k
    break;
10052
8.89k
  case 22:
10053
    // MVE_VABAVs32, MVE_VABDs32, MVE_VABSs32, MVE_VADDLVs32acc, MVE_VADDLVs3...
10054
8.89k
    SStream_concat0(O, ".s32\t");
10055
8.89k
    ARM_add_vector_data(MI, ARM_VECTORDATA_S32);
10056
8.89k
    break;
10057
5.61k
  case 23:
10058
    // MVE_VABAVs8, MVE_VABDs8, MVE_VABSs8, MVE_VADDVs8acc, MVE_VADDVs8no_acc...
10059
5.61k
    SStream_concat0(O, ".s8\t");
10060
5.61k
    ARM_add_vector_data(MI, ARM_VECTORDATA_S8);
10061
5.61k
    break;
10062
5.10k
  case 24:
10063
    // MVE_VABAVu16, MVE_VABDu16, MVE_VADDVu16acc, MVE_VADDVu16no_acc, MVE_VC...
10064
5.10k
    SStream_concat0(O, ".u16\t");
10065
5.10k
    ARM_add_vector_data(MI, ARM_VECTORDATA_U16);
10066
5.10k
    break;
10067
8.23k
  case 25:
10068
    // MVE_VABAVu32, MVE_VABDu32, MVE_VADDLVu32acc, MVE_VADDLVu32no_acc, MVE_...
10069
8.23k
    SStream_concat0(O, ".u32\t");
10070
8.23k
    ARM_add_vector_data(MI, ARM_VECTORDATA_U32);
10071
8.23k
    break;
10072
6.82k
  case 26:
10073
    // MVE_VABAVu8, MVE_VABDu8, MVE_VADDVu8acc, MVE_VADDVu8no_acc, MVE_VCMPu8...
10074
6.82k
    SStream_concat0(O, ".u8\t");
10075
6.82k
    ARM_add_vector_data(MI, ARM_VECTORDATA_U8);
10076
6.82k
    break;
10077
5.22k
  case 27:
10078
    // MVE_VADC, MVE_VADCI, MVE_VADD_qr_i32, MVE_VADDi32, MVE_VBICimmi32, MVE...
10079
5.22k
    SStream_concat0(O, ".i32\t");
10080
5.22k
    ARM_add_vector_data(MI, ARM_VECTORDATA_I32);
10081
5.22k
    break;
10082
2.00k
  case 28:
10083
    // MVE_VADD_qr_i16, MVE_VADDi16, MVE_VBICimmi16, MVE_VCADDi16, MVE_VCLZs1...
10084
2.00k
    SStream_concat0(O, ".i16\t");
10085
2.00k
    ARM_add_vector_data(MI, ARM_VECTORDATA_I16);
10086
2.00k
    break;
10087
3.63k
  case 29:
10088
    // MVE_VADD_qr_i8, MVE_VADDi8, MVE_VCADDi8, MVE_VCLZs8, MVE_VCMPi8, MVE_V...
10089
3.63k
    SStream_concat0(O, ".i8\t");
10090
3.63k
    ARM_add_vector_data(MI, ARM_VECTORDATA_I8);
10091
3.63k
    break;
10092
4.34k
  case 30:
10093
    // MVE_VCTP64, MVE_VSTRD64_qi, MVE_VSTRD64_qi_pre, MVE_VSTRD64_rq, MVE_VS...
10094
4.34k
    SStream_concat0(O, ".64\t");
10095
4.34k
    ARM_add_vector_size(MI, 64);
10096
4.34k
    break;
10097
266
  case 31:
10098
    // MVE_VCVTf16f32bh, MVE_VCVTf16f32th, VCVTBSH, VCVTTSH, VCVTf2h
10099
266
    SStream_concat0(O, ".f16.f32\t");
10100
266
    ARM_add_vector_data(MI, ARM_VECTORDATA_F16F32);
10101
266
    printOperand(MI, 0, O);
10102
266
    SStream_concat0(O, ", ");
10103
266
    break;
10104
412
  case 32:
10105
    // MVE_VCVTf16s16_fix, MVE_VCVTf16s16n, VCVTs2hd, VCVTs2hq, VCVTxs2hd, VC...
10106
412
    SStream_concat0(O, ".f16.s16\t");
10107
412
    ARM_add_vector_data(MI, ARM_VECTORDATA_F16S16);
10108
412
    printOperand(MI, 0, O);
10109
412
    SStream_concat0(O, ", ");
10110
412
    printOperand(MI, 1, O);
10111
412
    break;
10112
271
  case 33:
10113
    // MVE_VCVTf16u16_fix, MVE_VCVTf16u16n, VCVTu2hd, VCVTu2hq, VCVTxu2hd, VC...
10114
271
    SStream_concat0(O, ".f16.u16\t");
10115
271
    ARM_add_vector_data(MI, ARM_VECTORDATA_F16U16);
10116
271
    printOperand(MI, 0, O);
10117
271
    SStream_concat0(O, ", ");
10118
271
    printOperand(MI, 1, O);
10119
271
    break;
10120
224
  case 34:
10121
    // MVE_VCVTf32f16bh, MVE_VCVTf32f16th, VCVTBHS, VCVTTHS, VCVTh2f
10122
224
    SStream_concat0(O, ".f32.f16\t");
10123
224
    ARM_add_vector_data(MI, ARM_VECTORDATA_F32F16);
10124
224
    printOperand(MI, 0, O);
10125
224
    SStream_concat0(O, ", ");
10126
224
    printOperand(MI, 1, O);
10127
224
    return;
10128
0
    break;
10129
107
  case 35:
10130
    // MVE_VCVTf32s32_fix, MVE_VCVTf32s32n, VCVTs2fd, VCVTs2fq, VCVTxs2fd, VC...
10131
107
    SStream_concat0(O, ".f32.s32\t");
10132
107
    ARM_add_vector_data(MI, ARM_VECTORDATA_F32S32);
10133
107
    printOperand(MI, 0, O);
10134
107
    SStream_concat0(O, ", ");
10135
107
    printOperand(MI, 1, O);
10136
107
    break;
10137
187
  case 36:
10138
    // MVE_VCVTf32u32_fix, MVE_VCVTf32u32n, VCVTu2fd, VCVTu2fq, VCVTxu2fd, VC...
10139
187
    SStream_concat0(O, ".f32.u32\t");
10140
187
    ARM_add_vector_data(MI, ARM_VECTORDATA_F32U32);
10141
187
    printOperand(MI, 0, O);
10142
187
    SStream_concat0(O, ", ");
10143
187
    printOperand(MI, 1, O);
10144
187
    break;
10145
355
  case 37:
10146
    // MVE_VCVTs16f16_fix, MVE_VCVTs16f16a, MVE_VCVTs16f16m, MVE_VCVTs16f16n,...
10147
355
    SStream_concat0(O, ".s16.f16\t");
10148
355
    ARM_add_vector_data(MI, ARM_VECTORDATA_S16F16);
10149
355
    printOperand(MI, 0, O);
10150
355
    SStream_concat0(O, ", ");
10151
355
    printOperand(MI, 1, O);
10152
355
    break;
10153
1.30k
  case 38:
10154
    // MVE_VCVTs32f32_fix, MVE_VCVTs32f32a, MVE_VCVTs32f32m, MVE_VCVTs32f32n,...
10155
1.30k
    SStream_concat0(O, ".s32.f32\t");
10156
1.30k
    ARM_add_vector_data(MI, ARM_VECTORDATA_S32F32);
10157
1.30k
    printOperand(MI, 0, O);
10158
1.30k
    SStream_concat0(O, ", ");
10159
1.30k
    printOperand(MI, 1, O);
10160
1.30k
    break;
10161
207
  case 39:
10162
    // MVE_VCVTu16f16_fix, MVE_VCVTu16f16a, MVE_VCVTu16f16m, MVE_VCVTu16f16n,...
10163
207
    SStream_concat0(O, ".u16.f16\t");
10164
207
    ARM_add_vector_data(MI, ARM_VECTORDATA_U16F16);
10165
207
    printOperand(MI, 0, O);
10166
207
    SStream_concat0(O, ", ");
10167
207
    printOperand(MI, 1, O);
10168
207
    break;
10169
145
  case 40:
10170
    // MVE_VCVTu32f32_fix, MVE_VCVTu32f32a, MVE_VCVTu32f32m, MVE_VCVTu32f32n,...
10171
145
    SStream_concat0(O, ".u32.f32\t");
10172
145
    ARM_add_vector_data(MI, ARM_VECTORDATA_U32F32);
10173
145
    printOperand(MI, 0, O);
10174
145
    SStream_concat0(O, ", ");
10175
145
    printOperand(MI, 1, O);
10176
145
    break;
10177
1.44k
  case 41:
10178
    // MVE_VLD20_16, MVE_VLD20_32, MVE_VLD20_8, MVE_VLD21_16, MVE_VLD21_32, M...
10179
1.44k
    printAddrMode7Operand(MI, 2, O);
10180
1.44k
    return;
10181
0
    break;
10182
428
  case 42:
10183
    // MVE_VLD20_16_wb, MVE_VLD20_32_wb, MVE_VLD20_8_wb, MVE_VLD21_16_wb, MVE...
10184
428
    printAddrMode7Operand(MI, 3, O);
10185
428
    SStream_concat1(O, '!');
10186
428
    return;
10187
0
    break;
10188
1.18k
  case 43:
10189
    // MVE_VLDRDU64_qi, MVE_VLDRDU64_qi_pre, MVE_VLDRDU64_rq, MVE_VLDRDU64_rq...
10190
1.18k
    SStream_concat0(O, ".u64\t");
10191
1.18k
    ARM_add_vector_data(MI, ARM_VECTORDATA_U64);
10192
1.18k
    break;
10193
521
  case 44:
10194
    // MVE_VMOVimmi64, VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i...
10195
521
    SStream_concat0(O, ".i64\t");
10196
521
    ARM_add_vector_data(MI, ARM_VECTORDATA_I64);
10197
521
    printOperand(MI, 0, O);
10198
521
    SStream_concat0(O, ", ");
10199
521
    break;
10200
101
  case 45:
10201
    // MVE_VMULLBp16, MVE_VMULLTp16
10202
101
    SStream_concat0(O, ".p16\t");
10203
101
    ARM_add_vector_data(MI, ARM_VECTORDATA_P16);
10204
101
    printOperand(MI, 0, O);
10205
101
    SStream_concat0(O, ", ");
10206
101
    printOperand(MI, 1, O);
10207
101
    SStream_concat0(O, ", ");
10208
101
    printOperand(MI, 2, O);
10209
101
    return;
10210
0
    break;
10211
618
  case 46:
10212
    // MVE_VMULLBp8, MVE_VMULLTp8, VMULLp8, VMULpd, VMULpq
10213
618
    SStream_concat0(O, ".p8\t");
10214
618
    ARM_add_vector_data(MI, ARM_VECTORDATA_P8);
10215
618
    printOperand(MI, 0, O);
10216
618
    SStream_concat0(O, ", ");
10217
618
    printOperand(MI, 1, O);
10218
618
    SStream_concat0(O, ", ");
10219
618
    printOperand(MI, 2, O);
10220
618
    return;
10221
0
    break;
10222
1.28k
  case 47:
10223
    // MVE_VST20_16, MVE_VST20_32, MVE_VST20_8, MVE_VST21_16, MVE_VST21_32, M...
10224
1.28k
    printAddrMode7Operand(MI, 1, O);
10225
1.28k
    return;
10226
0
    break;
10227
871
  case 48:
10228
    // RFEDA_UPD, RFEDB_UPD, RFEIA_UPD, RFEIB_UPD
10229
871
    SStream_concat1(O, '!');
10230
871
    return;
10231
0
    break;
10232
73
  case 49:
10233
    // VCVTBDH, VCVTTDH
10234
73
    SStream_concat0(O, ".f16.f64\t");
10235
73
    ARM_add_vector_data(MI, ARM_VECTORDATA_F16F64);
10236
73
    printOperand(MI, 0, O);
10237
73
    SStream_concat0(O, ", ");
10238
73
    printOperand(MI, 2, O);
10239
73
    return;
10240
0
    break;
10241
18
  case 50:
10242
    // VCVTBHD, VCVTTHD
10243
18
    SStream_concat0(O, ".f64.f16\t");
10244
18
    ARM_add_vector_data(MI, ARM_VECTORDATA_F64F16);
10245
18
    printOperand(MI, 0, O);
10246
18
    SStream_concat0(O, ", ");
10247
18
    printOperand(MI, 1, O);
10248
18
    return;
10249
0
    break;
10250
294
  case 51:
10251
    // VCVTDS
10252
294
    SStream_concat0(O, ".f64.f32\t");
10253
294
    ARM_add_vector_data(MI, ARM_VECTORDATA_F64F32);
10254
294
    printOperand(MI, 0, O);
10255
294
    SStream_concat0(O, ", ");
10256
294
    printOperand(MI, 1, O);
10257
294
    return;
10258
0
    break;
10259
71
  case 52:
10260
    // VCVTSD
10261
71
    SStream_concat0(O, ".f32.f64\t");
10262
71
    ARM_add_vector_data(MI, ARM_VECTORDATA_F32F64);
10263
71
    printOperand(MI, 0, O);
10264
71
    SStream_concat0(O, ", ");
10265
71
    printOperand(MI, 1, O);
10266
71
    return;
10267
0
    break;
10268
11
  case 53:
10269
    // VJCVT, VTOSIRD, VTOSIZD, VTOSLD
10270
11
    SStream_concat0(O, ".s32.f64\t");
10271
11
    ARM_add_vector_data(MI, ARM_VECTORDATA_S32F64);
10272
11
    printOperand(MI, 0, O);
10273
11
    SStream_concat0(O, ", ");
10274
11
    printOperand(MI, 1, O);
10275
11
    break;
10276
9.91k
  case 54:
10277
    // VLD1LNd16, VLD1LNd16_UPD, VLD2LNd16, VLD2LNd16_UPD, VLD2LNq16, VLD2LNq...
10278
9.91k
    SStream_concat0(O, ".16\t{");
10279
9.91k
    ARM_add_vector_size(MI, 16);
10280
9.91k
    break;
10281
9.27k
  case 55:
10282
    // VLD1LNd32, VLD1LNd32_UPD, VLD2LNd32, VLD2LNd32_UPD, VLD2LNq32, VLD2LNq...
10283
9.27k
    SStream_concat0(O, ".32\t{");
10284
9.27k
    ARM_add_vector_size(MI, 32);
10285
9.27k
    break;
10286
9.84k
  case 56:
10287
    // VLD1LNd8, VLD1LNd8_UPD, VLD2LNd8, VLD2LNd8_UPD, VLD3DUPd8, VLD3DUPd8_U...
10288
9.84k
    SStream_concat0(O, ".8\t{");
10289
9.84k
    ARM_add_vector_size(MI, 8);
10290
9.84k
    break;
10291
1.01k
  case 57:
10292
    // VLDR_FPCXTNS_off, VLDR_FPCXTNS_post, VLDR_FPCXTNS_pre, VMSR_FPCXTNS, V...
10293
1.01k
    SStream_concat0(O, "\tfpcxtns, ");
10294
1.01k
    break;
10295
1.13k
  case 58:
10296
    // VLDR_FPCXTS_off, VLDR_FPCXTS_post, VLDR_FPCXTS_pre, VMSR_FPCXTS, VSTR_...
10297
1.13k
    SStream_concat0(O, "\tfpcxts, ");
10298
1.13k
    break;
10299
986
  case 59:
10300
    // VLDR_FPSCR_NZCVQC_off, VLDR_FPSCR_NZCVQC_post, VLDR_FPSCR_NZCVQC_pre, ...
10301
986
    SStream_concat0(O, "\tfpscr_nzcvqc, ");
10302
986
    break;
10303
2.02k
  case 60:
10304
    // VLDR_FPSCR_off, VLDR_FPSCR_post, VLDR_FPSCR_pre, VMSR, VSTR_FPSCR_off,...
10305
2.02k
    SStream_concat0(O, "\tfpscr, ");
10306
2.02k
    break;
10307
0
  case 61:
10308
    // VLDR_P0_off, VLDR_P0_post, VLDR_P0_pre, VMSR_P0, VSTR_P0_off, VSTR_P0_...
10309
0
    SStream_concat0(O, "\tp0, ");
10310
0
    break;
10311
0
  case 62:
10312
    // VLDR_VPR_off, VLDR_VPR_post, VLDR_VPR_pre, VMSR_VPR, VSTR_VPR_off, VST...
10313
0
    SStream_concat0(O, "\tvpr, ");
10314
0
    break;
10315
80
  case 63:
10316
    // VMSR_FPEXC
10317
80
    SStream_concat0(O, "\tfpexc, ");
10318
80
    printOperand(MI, 0, O);
10319
80
    return;
10320
0
    break;
10321
33
  case 64:
10322
    // VMSR_FPINST
10323
33
    SStream_concat0(O, "\tfpinst, ");
10324
33
    printOperand(MI, 0, O);
10325
33
    return;
10326
0
    break;
10327
20
  case 65:
10328
    // VMSR_FPINST2
10329
20
    SStream_concat0(O, "\tfpinst2, ");
10330
20
    printOperand(MI, 0, O);
10331
20
    return;
10332
0
    break;
10333
37
  case 66:
10334
    // VMSR_FPSID
10335
37
    SStream_concat0(O, "\tfpsid, ");
10336
37
    printOperand(MI, 0, O);
10337
37
    return;
10338
0
    break;
10339
709
  case 67:
10340
    // VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V...
10341
709
    SStream_concat0(O, ".s64\t");
10342
709
    ARM_add_vector_data(MI, ARM_VECTORDATA_S64);
10343
709
    printOperand(MI, 0, O);
10344
709
    SStream_concat0(O, ", ");
10345
709
    break;
10346
250
  case 68:
10347
    // VSHTOD
10348
250
    SStream_concat0(O, ".f64.s16\t");
10349
250
    ARM_add_vector_data(MI, ARM_VECTORDATA_F64S16);
10350
250
    printOperand(MI, 0, O);
10351
250
    SStream_concat0(O, ", ");
10352
250
    printOperand(MI, 1, O);
10353
250
    SStream_concat0(O, ", ");
10354
250
    printFBits16(MI, 2, O);
10355
250
    return;
10356
0
    break;
10357
207
  case 69:
10358
    // VSHTOS
10359
207
    SStream_concat0(O, ".f32.s16\t");
10360
207
    ARM_add_vector_data(MI, ARM_VECTORDATA_F32S16);
10361
207
    printOperand(MI, 0, O);
10362
207
    SStream_concat0(O, ", ");
10363
207
    printOperand(MI, 1, O);
10364
207
    SStream_concat0(O, ", ");
10365
207
    printFBits16(MI, 2, O);
10366
207
    return;
10367
0
    break;
10368
75
  case 70:
10369
    // VSITOD, VSLTOD
10370
75
    SStream_concat0(O, ".f64.s32\t");
10371
75
    ARM_add_vector_data(MI, ARM_VECTORDATA_F64S32);
10372
75
    printOperand(MI, 0, O);
10373
75
    SStream_concat0(O, ", ");
10374
75
    printOperand(MI, 1, O);
10375
75
    break;
10376
119
  case 71:
10377
    // VSITOH, VSLTOH
10378
119
    SStream_concat0(O, ".f16.s32\t");
10379
119
    ARM_add_vector_data(MI, ARM_VECTORDATA_F16S32);
10380
119
    printOperand(MI, 0, O);
10381
119
    SStream_concat0(O, ", ");
10382
119
    printOperand(MI, 1, O);
10383
119
    break;
10384
74
  case 72:
10385
    // VTOSHD
10386
74
    SStream_concat0(O, ".s16.f64\t");
10387
74
    ARM_add_vector_data(MI, ARM_VECTORDATA_S16F64);
10388
74
    printOperand(MI, 0, O);
10389
74
    SStream_concat0(O, ", ");
10390
74
    printOperand(MI, 1, O);
10391
74
    SStream_concat0(O, ", ");
10392
74
    printFBits16(MI, 2, O);
10393
74
    return;
10394
0
    break;
10395
288
  case 73:
10396
    // VTOSHS
10397
288
    SStream_concat0(O, ".s16.f32\t");
10398
288
    ARM_add_vector_data(MI, ARM_VECTORDATA_S16F32);
10399
288
    printOperand(MI, 0, O);
10400
288
    SStream_concat0(O, ", ");
10401
288
    printOperand(MI, 1, O);
10402
288
    SStream_concat0(O, ", ");
10403
288
    printFBits16(MI, 2, O);
10404
288
    return;
10405
0
    break;
10406
200
  case 74:
10407
    // VTOSIRH, VTOSIZH, VTOSLH
10408
200
    SStream_concat0(O, ".s32.f16\t");
10409
200
    ARM_add_vector_data(MI, ARM_VECTORDATA_S32F16);
10410
200
    printOperand(MI, 0, O);
10411
200
    SStream_concat0(O, ", ");
10412
200
    printOperand(MI, 1, O);
10413
200
    break;
10414
77
  case 75:
10415
    // VTOUHD
10416
77
    SStream_concat0(O, ".u16.f64\t");
10417
77
    ARM_add_vector_data(MI, ARM_VECTORDATA_U16F64);
10418
77
    printOperand(MI, 0, O);
10419
77
    SStream_concat0(O, ", ");
10420
77
    printOperand(MI, 1, O);
10421
77
    SStream_concat0(O, ", ");
10422
77
    printFBits16(MI, 2, O);
10423
77
    return;
10424
0
    break;
10425
76
  case 76:
10426
    // VTOUHS
10427
76
    SStream_concat0(O, ".u16.f32\t");
10428
76
    ARM_add_vector_data(MI, ARM_VECTORDATA_U16F32);
10429
76
    printOperand(MI, 0, O);
10430
76
    SStream_concat0(O, ", ");
10431
76
    printOperand(MI, 1, O);
10432
76
    SStream_concat0(O, ", ");
10433
76
    printFBits16(MI, 2, O);
10434
76
    return;
10435
0
    break;
10436
302
  case 77:
10437
    // VTOUIRD, VTOUIZD, VTOULD
10438
302
    SStream_concat0(O, ".u32.f64\t");
10439
302
    ARM_add_vector_data(MI, ARM_VECTORDATA_U32F64);
10440
302
    printOperand(MI, 0, O);
10441
302
    SStream_concat0(O, ", ");
10442
302
    printOperand(MI, 1, O);
10443
302
    break;
10444
40
  case 78:
10445
    // VTOUIRH, VTOUIZH, VTOULH
10446
40
    SStream_concat0(O, ".u32.f16\t");
10447
40
    ARM_add_vector_data(MI, ARM_VECTORDATA_U32F16);
10448
40
    printOperand(MI, 0, O);
10449
40
    SStream_concat0(O, ", ");
10450
40
    printOperand(MI, 1, O);
10451
40
    break;
10452
80
  case 79:
10453
    // VUHTOD
10454
80
    SStream_concat0(O, ".f64.u16\t");
10455
80
    ARM_add_vector_data(MI, ARM_VECTORDATA_F64U16);
10456
80
    printOperand(MI, 0, O);
10457
80
    SStream_concat0(O, ", ");
10458
80
    printOperand(MI, 1, O);
10459
80
    SStream_concat0(O, ", ");
10460
80
    printFBits16(MI, 2, O);
10461
80
    return;
10462
0
    break;
10463
37
  case 80:
10464
    // VUHTOS
10465
37
    SStream_concat0(O, ".f32.u16\t");
10466
37
    ARM_add_vector_data(MI, ARM_VECTORDATA_F32U16);
10467
37
    printOperand(MI, 0, O);
10468
37
    SStream_concat0(O, ", ");
10469
37
    printOperand(MI, 1, O);
10470
37
    SStream_concat0(O, ", ");
10471
37
    printFBits16(MI, 2, O);
10472
37
    return;
10473
0
    break;
10474
107
  case 81:
10475
    // VUITOD, VULTOD
10476
107
    SStream_concat0(O, ".f64.u32\t");
10477
107
    ARM_add_vector_data(MI, ARM_VECTORDATA_F64U32);
10478
107
    printOperand(MI, 0, O);
10479
107
    SStream_concat0(O, ", ");
10480
107
    printOperand(MI, 1, O);
10481
107
    break;
10482
55
  case 82:
10483
    // VUITOH, VULTOH
10484
55
    SStream_concat0(O, ".f16.u32\t");
10485
55
    ARM_add_vector_data(MI, ARM_VECTORDATA_F16U32);
10486
55
    printOperand(MI, 0, O);
10487
55
    SStream_concat0(O, ", ");
10488
55
    printOperand(MI, 1, O);
10489
55
    break;
10490
27.8k
  case 83:
10491
    // t2ADCrr, t2ADCrs, t2ADDri, t2ADDrr, t2ADDrs, t2ADDspImm, t2ADR, t2ANDr...
10492
27.8k
    SStream_concat0(O, ".w\t");
10493
27.8k
    break;
10494
112
  case 84:
10495
    // t2SRSDB, t2SRSIA
10496
112
    SStream_concat0(O, "\tsp, ");
10497
112
    printOperand(MI, 0, O);
10498
112
    return;
10499
0
    break;
10500
233
  case 85:
10501
    // t2SRSDB_UPD, t2SRSIA_UPD
10502
233
    SStream_concat0(O, "\tsp!, ");
10503
233
    printOperand(MI, 0, O);
10504
233
    return;
10505
0
    break;
10506
69
  case 86:
10507
    // t2SUBS_PC_LR
10508
69
    SStream_concat0(O, "\tpc, lr, ");
10509
69
    printOperand(MI, 0, O);
10510
69
    return;
10511
0
    break;
10512
226k
  case 87:
10513
    // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
10514
226k
    printPredicateOperand(MI, 4, O);
10515
226k
    SStream_concat0(O, "\t");
10516
226k
    printOperand(MI, 0, O);
10517
226k
    SStream_concat0(O, ", ");
10518
226k
    break;
10519
33.8k
  case 88:
10520
    // tMOVi8, tMVN, tRSB
10521
33.8k
    printPredicateOperand(MI, 3, O);
10522
33.8k
    SStream_concat0(O, "\t");
10523
33.8k
    printOperand(MI, 0, O);
10524
33.8k
    SStream_concat0(O, ", ");
10525
33.8k
    printOperand(MI, 2, O);
10526
33.8k
    break;
10527
1.13M
  }
10528
10529
10530
  // Fragment 2 encoded into 7 bits for 71 unique commands.
10531
1.12M
  switch ((Bits >> 26) & 127) {
10532
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
10533
505k
  case 0:
10534
    // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHTii, LDR...
10535
505k
    printOperand(MI, 0, O);
10536
505k
    break;
10537
9.91k
  case 1:
10538
    // ITasm, t2IT
10539
9.91k
    printMandatoryPredicateOperand(MI, 0, O);
10540
9.91k
    return;
10541
0
    break;
10542
0
  case 2:
10543
    // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16...
10544
0
    printVectorListThreeAllLanes(MI, 0, O);
10545
0
    SStream_concat0(O, ", ");
10546
0
    printAddrMode6Operand(MI, 1, O);
10547
0
    break;
10548
0
  case 3:
10549
    // VLD3DUPqAsm_16, VLD3DUPqAsm_32, VLD3DUPqAsm_8, VLD3DUPqWB_fixed_Asm_16...
10550
0
    printVectorListThreeSpacedAllLanes(MI, 0, O);
10551
0
    SStream_concat0(O, ", ");
10552
0
    printAddrMode6Operand(MI, 1, O);
10553
0
    break;
10554
1.04k
  case 4:
10555
    // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD3dWB_fixed_Asm_16, VLD3dWB_fi...
10556
1.04k
    printVectorListThree(MI, 0, O);
10557
1.04k
    SStream_concat0(O, ", ");
10558
1.04k
    break;
10559
0
  case 5:
10560
    // VLD3qAsm_16, VLD3qAsm_32, VLD3qAsm_8, VLD3qWB_fixed_Asm_16, VLD3qWB_fi...
10561
0
    printVectorListThreeSpaced(MI, 0, O);
10562
0
    SStream_concat0(O, ", ");
10563
0
    printAddrMode6Operand(MI, 1, O);
10564
0
    break;
10565
0
  case 6:
10566
    // VLD4DUPdAsm_16, VLD4DUPdAsm_32, VLD4DUPdAsm_8, VLD4DUPdWB_fixed_Asm_16...
10567
0
    printVectorListFourAllLanes(MI, 0, O);
10568
0
    SStream_concat0(O, ", ");
10569
0
    printAddrMode6Operand(MI, 1, O);
10570
0
    break;
10571
0
  case 7:
10572
    // VLD4DUPqAsm_16, VLD4DUPqAsm_32, VLD4DUPqAsm_8, VLD4DUPqWB_fixed_Asm_16...
10573
0
    printVectorListFourSpacedAllLanes(MI, 0, O);
10574
0
    SStream_concat0(O, ", ");
10575
0
    printAddrMode6Operand(MI, 1, O);
10576
0
    break;
10577
2.61k
  case 8:
10578
    // VLD4dAsm_16, VLD4dAsm_32, VLD4dAsm_8, VLD4dWB_fixed_Asm_16, VLD4dWB_fi...
10579
2.61k
    printVectorListFour(MI, 0, O);
10580
2.61k
    SStream_concat0(O, ", ");
10581
2.61k
    break;
10582
0
  case 9:
10583
    // VLD4qAsm_16, VLD4qAsm_32, VLD4qAsm_8, VLD4qWB_fixed_Asm_16, VLD4qWB_fi...
10584
0
    printVectorListFourSpaced(MI, 0, O);
10585
0
    SStream_concat0(O, ", ");
10586
0
    printAddrMode6Operand(MI, 1, O);
10587
0
    break;
10588
0
  case 10:
10589
    // t2LDRB_OFFSET_imm, t2LDRH_OFFSET_imm, t2LDRSB_OFFSET_imm, t2LDRSH_OFFS...
10590
0
    printT2AddrModeImm8Operand_0(MI, 1, O);
10591
0
    return;
10592
0
    break;
10593
1.31k
  case 11:
10594
    // t2LDRB_POST_imm, t2LDRH_POST_imm, t2LDRSB_POST_imm, t2LDRSH_POST_imm, ...
10595
1.31k
    printAddrMode7Operand(MI, 1, O);
10596
1.31k
    break;
10597
0
  case 12:
10598
    // t2LDRB_PRE_imm, t2LDRH_PRE_imm, t2LDRSB_PRE_imm, t2LDRSH_PRE_imm, t2LD...
10599
0
    printT2AddrModeImm8Operand_1(MI, 1, O);
10600
0
    SStream_concat1(O, '!');
10601
0
    return;
10602
0
    break;
10603
169k
  case 13:
10604
    // AESD, AESE, BF16_VCVTB, BF16_VCVTT, CDE_CX1, CDE_CX2, CDE_CX3, CDE_VCX...
10605
169k
    printOperand(MI, 2, O);
10606
169k
    break;
10607
121k
  case 14:
10608
    // AESIMC, AESMC, BF16_VCVT, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, C...
10609
121k
    printOperand(MI, 1, O);
10610
121k
    break;
10611
68.6k
  case 15:
10612
    // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, BF16VDOTS_VDOTQ, CD...
10613
68.6k
    printOperand(MI, 3, O);
10614
68.6k
    break;
10615
44.5k
  case 16:
10616
    // BL_pred, Bcc, t2B, t2BFLi, t2BFLr, t2BFi, t2BFr, t2Bcc, tB, tBcc
10617
44.5k
    printOperandAddr(MI, Address, 0, O);
10618
44.5k
    break;
10619
5.21k
  case 17:
10620
    // CDE_CX1A, CDE_CX1DA, CDE_CX2A, CDE_CX2DA, CDE_CX3A, CDE_CX3DA, CDE_VCX...
10621
5.21k
    printPImmediate(MI, 1, O);
10622
5.21k
    SStream_concat0(O, ", ");
10623
5.21k
    break;
10624
34.6k
  case 18:
10625
    // CDE_CX1D, MVE_LCTP, MVE_VCVTf16s16n, MVE_VCVTf16u16n, MVE_VCVTf32s32n,...
10626
34.6k
    return;
10627
0
    break;
10628
4.56k
  case 19:
10629
    // CDE_CX2D, CDE_CX3D, FCONSTD, MVE_VCVTf16s16_fix, MVE_VCVTf16u16_fix, M...
10630
4.56k
    SStream_concat0(O, ", ");
10631
4.56k
    break;
10632
61.9k
  case 20:
10633
    // CDP, LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OP...
10634
61.9k
    printPImmediate(MI, 0, O);
10635
61.9k
    SStream_concat0(O, ", ");
10636
61.9k
    break;
10637
709
  case 21:
10638
    // CDP2
10639
709
    printCImmediate(MI, 2, O);
10640
709
    SStream_concat0(O, ", ");
10641
709
    printCImmediate(MI, 3, O);
10642
709
    SStream_concat0(O, ", ");
10643
709
    printCImmediate(MI, 4, O);
10644
709
    SStream_concat0(O, ", ");
10645
709
    printOperand(MI, 5, O);
10646
709
    return;
10647
0
    break;
10648
1.89k
  case 22:
10649
    // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS
10650
1.89k
    printCPSIFlag(MI, 1, O);
10651
1.89k
    break;
10652
805
  case 23:
10653
    // LDAEXD, LDREXD
10654
805
    printGPRPairOperand(MI, 0, O);
10655
805
    SStream_concat0(O, ", ");
10656
805
    printAddrMode7Operand(MI, 1, O);
10657
805
    return;
10658
0
    break;
10659
1.07k
  case 24:
10660
    // LDC2L_OFFSET, LDC2_OFFSET, STC2L_OFFSET, STC2_OFFSET
10661
1.07k
    printAddrMode5Operand_0(MI, 2, O);
10662
1.07k
    return;
10663
0
    break;
10664
1.85k
  case 25:
10665
    // LDC2L_OPTION, LDC2L_POST, LDC2_OPTION, LDC2_POST, STC2L_OPTION, STC2L_...
10666
1.85k
    printAddrMode7Operand(MI, 2, O);
10667
1.85k
    break;
10668
865
  case 26:
10669
    // LDC2L_PRE, LDC2_PRE, STC2L_PRE, STC2_PRE
10670
865
    printAddrMode5Operand_1(MI, 2, O);
10671
865
    SStream_concat1(O, '!');
10672
865
    return;
10673
0
    break;
10674
877
  case 27:
10675
    // MRRC, t2MRRC, t2MRRC2
10676
877
    printPImmediate(MI, 2, O);
10677
877
    SStream_concat0(O, ", ");
10678
877
    printOperand(MI, 3, O);
10679
877
    SStream_concat0(O, ", ");
10680
877
    printOperand(MI, 0, O);
10681
877
    SStream_concat0(O, ", ");
10682
877
    printOperand(MI, 1, O);
10683
877
    SStream_concat0(O, ", ");
10684
877
    printCImmediate(MI, 4, O);
10685
877
    return;
10686
0
    break;
10687
9.63k
  case 28:
10688
    // MSR, MSRi, t2MSR_AR, t2MSR_M
10689
9.63k
    printMSRMaskOperand(MI, 0, O);
10690
9.63k
    SStream_concat0(O, ", ");
10691
9.63k
    break;
10692
117
  case 29:
10693
    // MSRbanked, t2MSRbanked
10694
117
    printBankedRegOperand(MI, 0, O);
10695
117
    SStream_concat0(O, ", ");
10696
117
    printOperand(MI, 1, O);
10697
117
    return;
10698
0
    break;
10699
11.1k
  case 30:
10700
    // MVE_VCMPf16, MVE_VCMPf16r, MVE_VCMPf32, MVE_VCMPf32r, MVE_VCMPi16, MVE...
10701
11.1k
    printMandatoryRestrictedPredicateOperand(MI, 3, O);
10702
11.1k
    SStream_concat0(O, ", ");
10703
11.1k
    printOperand(MI, 1, O);
10704
11.1k
    SStream_concat0(O, ", ");
10705
11.1k
    printOperand(MI, 2, O);
10706
11.1k
    return;
10707
0
    break;
10708
431
  case 31:
10709
    // MVE_VMOVimmi64, VMOVv1i64, VMOVv2i64
10710
431
    printVMOVModImmOperand(MI, 1, O);
10711
431
    return;
10712
0
    break;
10713
806
  case 32:
10714
    // VCMPEZD, VCMPZD, tRSB
10715
806
    SStream_concat0(O, ", #0");
10716
806
    return;
10717
0
    break;
10718
624
  case 33:
10719
    // VLD1DUPd16, VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32, VLD...
10720
624
    printVectorListOneAllLanes(MI, 0, O);
10721
624
    SStream_concat0(O, ", ");
10722
624
    break;
10723
2.77k
  case 34:
10724
    // VLD1DUPq16, VLD1DUPq16wb_fixed, VLD1DUPq16wb_register, VLD1DUPq32, VLD...
10725
2.77k
    printVectorListTwoAllLanes(MI, 0, O);
10726
2.77k
    SStream_concat0(O, ", ");
10727
2.77k
    break;
10728
1.49k
  case 35:
10729
    // VLD1d16, VLD1d16wb_fixed, VLD1d16wb_register, VLD1d32, VLD1d32wb_fixed...
10730
1.49k
    printVectorListOne(MI, 0, O);
10731
1.49k
    SStream_concat0(O, ", ");
10732
1.49k
    break;
10733
3.17k
  case 36:
10734
    // VLD1q16, VLD1q16wb_fixed, VLD1q16wb_register, VLD1q32, VLD1q32wb_fixed...
10735
3.17k
    printVectorListTwo(MI, 0, O);
10736
3.17k
    SStream_concat0(O, ", ");
10737
3.17k
    break;
10738
1.76k
  case 37:
10739
    // VLD2DUPd16x2, VLD2DUPd16x2wb_fixed, VLD2DUPd16x2wb_register, VLD2DUPd3...
10740
1.76k
    printVectorListTwoSpacedAllLanes(MI, 0, O);
10741
1.76k
    SStream_concat0(O, ", ");
10742
1.76k
    break;
10743
2.45k
  case 38:
10744
    // VLD2b16, VLD2b16wb_fixed, VLD2b16wb_register, VLD2b32, VLD2b32wb_fixed...
10745
2.45k
    printVectorListTwoSpaced(MI, 0, O);
10746
2.45k
    SStream_concat0(O, ", ");
10747
2.45k
    break;
10748
1.37k
  case 39:
10749
    // VLDR_FPCXTNS_off, VLDR_FPCXTS_off, VLDR_FPSCR_NZCVQC_off, VLDR_FPSCR_o...
10750
1.37k
    printT2AddrModeImm8s4Operand_0(MI, 0, O);
10751
1.37k
    return;
10752
0
    break;
10753
2.23k
  case 40:
10754
    // VLDR_FPCXTNS_pre, VLDR_FPCXTS_pre, VLDR_FPSCR_NZCVQC_pre, VLDR_FPSCR_p...
10755
2.23k
    printT2AddrModeImm8s4Operand_1(MI, 1, O);
10756
2.23k
    SStream_concat1(O, '!');
10757
2.23k
    return;
10758
0
    break;
10759
0
  case 41:
10760
    // VLDR_P0_off, VSTR_P0_off
10761
0
    printT2AddrModeImm8s4Operand_0(MI, 1, O);
10762
0
    return;
10763
0
    break;
10764
0
  case 42:
10765
    // VLDR_P0_pre, VSTR_P0_pre
10766
0
    printT2AddrModeImm8s4Operand_1(MI, 2, O);
10767
0
    SStream_concat1(O, '!');
10768
0
    return;
10769
0
    break;
10770
6.00k
  case 43:
10771
    // VSCCLRMD, VSCCLRMS, t2CLRM, tPOP, tPUSH
10772
6.00k
    printRegisterList(MI, 2, O);
10773
6.00k
    return;
10774
0
    break;
10775
7.69k
  case 44:
10776
    // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST2LNd16_UPD, VST2LNd32_U...
10777
7.69k
    printOperand(MI, 4, O);
10778
7.69k
    break;
10779
72
  case 45:
10780
    // VST1d16, VST1d32, VST1d64, VST1d8
10781
72
    printVectorListOne(MI, 2, O);
10782
72
    SStream_concat0(O, ", ");
10783
72
    printAddrMode6Operand(MI, 0, O);
10784
72
    return;
10785
0
    break;
10786
193
  case 46:
10787
    // VST1d16Q, VST1d32Q, VST1d64Q, VST1d8Q, VST2q16, VST2q32, VST2q8
10788
193
    printVectorListFour(MI, 2, O);
10789
193
    SStream_concat0(O, ", ");
10790
193
    printAddrMode6Operand(MI, 0, O);
10791
193
    return;
10792
0
    break;
10793
738
  case 47:
10794
    // VST1d16Qwb_fixed, VST1d32Qwb_fixed, VST1d64Qwb_fixed, VST1d8Qwb_fixed,...
10795
738
    printVectorListFour(MI, 3, O);
10796
738
    SStream_concat0(O, ", ");
10797
738
    printAddrMode6Operand(MI, 1, O);
10798
738
    SStream_concat1(O, '!');
10799
738
    return;
10800
0
    break;
10801
1.25k
  case 48:
10802
    // VST1d16Qwb_register, VST1d32Qwb_register, VST1d64Qwb_register, VST1d8Q...
10803
1.25k
    printVectorListFour(MI, 4, O);
10804
1.25k
    SStream_concat0(O, ", ");
10805
1.25k
    printAddrMode6Operand(MI, 1, O);
10806
1.25k
    SStream_concat0(O, ", ");
10807
1.25k
    printOperand(MI, 3, O);
10808
1.25k
    return;
10809
0
    break;
10810
112
  case 49:
10811
    // VST1d16T, VST1d32T, VST1d64T, VST1d8T
10812
112
    printVectorListThree(MI, 2, O);
10813
112
    SStream_concat0(O, ", ");
10814
112
    printAddrMode6Operand(MI, 0, O);
10815
112
    return;
10816
0
    break;
10817
578
  case 50:
10818
    // VST1d16Twb_fixed, VST1d32Twb_fixed, VST1d64Twb_fixed, VST1d8Twb_fixed
10819
578
    printVectorListThree(MI, 3, O);
10820
578
    SStream_concat0(O, ", ");
10821
578
    printAddrMode6Operand(MI, 1, O);
10822
578
    SStream_concat1(O, '!');
10823
578
    return;
10824
0
    break;
10825
950
  case 51:
10826
    // VST1d16Twb_register, VST1d32Twb_register, VST1d64Twb_register, VST1d8T...
10827
950
    printVectorListThree(MI, 4, O);
10828
950
    SStream_concat0(O, ", ");
10829
950
    printAddrMode6Operand(MI, 1, O);
10830
950
    SStream_concat0(O, ", ");
10831
950
    printOperand(MI, 3, O);
10832
950
    return;
10833
0
    break;
10834
599
  case 52:
10835
    // VST1d16wb_fixed, VST1d32wb_fixed, VST1d64wb_fixed, VST1d8wb_fixed
10836
599
    printVectorListOne(MI, 3, O);
10837
599
    SStream_concat0(O, ", ");
10838
599
    printAddrMode6Operand(MI, 1, O);
10839
599
    SStream_concat1(O, '!');
10840
599
    return;
10841
0
    break;
10842
907
  case 53:
10843
    // VST1d16wb_register, VST1d32wb_register, VST1d64wb_register, VST1d8wb_r...
10844
907
    printVectorListOne(MI, 4, O);
10845
907
    SStream_concat0(O, ", ");
10846
907
    printAddrMode6Operand(MI, 1, O);
10847
907
    SStream_concat0(O, ", ");
10848
907
    printOperand(MI, 3, O);
10849
907
    return;
10850
0
    break;
10851
1.18k
  case 54:
10852
    // VST1q16, VST1q32, VST1q64, VST1q8, VST2d16, VST2d32, VST2d8
10853
1.18k
    printVectorListTwo(MI, 2, O);
10854
1.18k
    SStream_concat0(O, ", ");
10855
1.18k
    printAddrMode6Operand(MI, 0, O);
10856
1.18k
    return;
10857
0
    break;
10858
865
  case 55:
10859
    // VST1q16wb_fixed, VST1q32wb_fixed, VST1q64wb_fixed, VST1q8wb_fixed, VST...
10860
865
    printVectorListTwo(MI, 3, O);
10861
865
    SStream_concat0(O, ", ");
10862
865
    printAddrMode6Operand(MI, 1, O);
10863
865
    SStream_concat1(O, '!');
10864
865
    return;
10865
0
    break;
10866
1.28k
  case 56:
10867
    // VST1q16wb_register, VST1q32wb_register, VST1q64wb_register, VST1q8wb_r...
10868
1.28k
    printVectorListTwo(MI, 4, O);
10869
1.28k
    SStream_concat0(O, ", ");
10870
1.28k
    printAddrMode6Operand(MI, 1, O);
10871
1.28k
    SStream_concat0(O, ", ");
10872
1.28k
    printOperand(MI, 3, O);
10873
1.28k
    return;
10874
0
    break;
10875
485
  case 57:
10876
    // VST2b16, VST2b32, VST2b8
10877
485
    printVectorListTwoSpaced(MI, 2, O);
10878
485
    SStream_concat0(O, ", ");
10879
485
    printAddrMode6Operand(MI, 0, O);
10880
485
    return;
10881
0
    break;
10882
891
  case 58:
10883
    // VST2b16wb_fixed, VST2b32wb_fixed, VST2b8wb_fixed
10884
891
    printVectorListTwoSpaced(MI, 3, O);
10885
891
    SStream_concat0(O, ", ");
10886
891
    printAddrMode6Operand(MI, 1, O);
10887
891
    SStream_concat1(O, '!');
10888
891
    return;
10889
0
    break;
10890
804
  case 59:
10891
    // VST2b16wb_register, VST2b32wb_register, VST2b8wb_register
10892
804
    printVectorListTwoSpaced(MI, 4, O);
10893
804
    SStream_concat0(O, ", ");
10894
804
    printAddrMode6Operand(MI, 1, O);
10895
804
    SStream_concat0(O, ", ");
10896
804
    printOperand(MI, 3, O);
10897
804
    return;
10898
0
    break;
10899
7.12k
  case 60:
10900
    // t2BFic, tCBNZ, tCBZ
10901
7.12k
    printOperandAddr(MI, Address, 1, O);
10902
7.12k
    break;
10903
1.28k
  case 61:
10904
    // t2DMB, t2DSB
10905
1.28k
    printMemBOption(MI, 0, O);
10906
1.28k
    return;
10907
0
    break;
10908
262
  case 62:
10909
    // t2ISB
10910
262
    printInstSyncBOption(MI, 0, O);
10911
262
    return;
10912
0
    break;
10913
786
  case 63:
10914
    // t2PLDWi12, t2PLDi12, t2PLIi12
10915
786
    printAddrModeImm12Operand_0(MI, 0, O);
10916
786
    return;
10917
0
    break;
10918
942
  case 64:
10919
    // t2PLDWi8, t2PLDi8, t2PLIi8
10920
942
    printT2AddrModeImm8Operand_0(MI, 0, O);
10921
942
    return;
10922
0
    break;
10923
542
  case 65:
10924
    // t2PLDWs, t2PLDs, t2PLIs
10925
542
    printT2AddrModeSoRegOperand(MI, 0, O);
10926
542
    return;
10927
0
    break;
10928
3.59k
  case 66:
10929
    // t2PLDpci, t2PLIpci
10930
3.59k
    printThumbLdrLabelOperand(MI, 0, O);
10931
3.59k
    return;
10932
0
    break;
10933
179
  case 67:
10934
    // t2TBB
10935
179
    printAddrModeTBB(MI, 0, O);
10936
179
    return;
10937
0
    break;
10938
500
  case 68:
10939
    // t2TBH
10940
500
    printAddrModeTBH(MI, 0, O);
10941
500
    return;
10942
0
    break;
10943
0
  case 69:
10944
    // t2TSB
10945
0
    printTraceSyncBOption(MI, 0, O);
10946
0
    return;
10947
0
    break;
10948
5.67k
  case 70:
10949
    // tBL, tBLXi
10950
5.67k
    printOperandAddr(MI, Address, 2, O);
10951
5.67k
    return;
10952
0
    break;
10953
1.12M
  }
10954
10955
10956
  // Fragment 3 encoded into 6 bits for 38 unique commands.
10957
1.02M
  switch ((Bits >> 33) & 63) {
10958
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
10959
680k
  case 0:
10960
    // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHTii, LDR...
10961
680k
    SStream_concat0(O, ", ");
10962
680k
    break;
10963
204k
  case 1:
10964
    // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPqAsm_16, VLD3DUP...
10965
204k
    return;
10966
0
    break;
10967
35
  case 2:
10968
    // VLD3DUPdWB_fixed_Asm_16, VLD3DUPdWB_fixed_Asm_32, VLD3DUPdWB_fixed_Asm...
10969
35
    SStream_concat1(O, '!');
10970
35
    return;
10971
0
    break;
10972
3.78k
  case 3:
10973
    // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD3dWB_fixed_Asm_16, VLD3dWB_fi...
10974
3.78k
    printAddrMode6Operand(MI, 1, O);
10975
3.78k
    break;
10976
748
  case 4:
10977
    // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, MVE_VMOV_q_rr, VBF16MALBQI, VBF16MAL...
10978
748
    printVectorIndex(MI, 4, O);
10979
748
    break;
10980
0
  case 5:
10981
    // CDE_CX1A, CDE_CX2A, CDE_CX3A, CDE_VCX1A_vec, CDE_VCX1_vec, CDE_VCX2A_v...
10982
0
    printOperand(MI, 0, O);
10983
0
    SStream_concat0(O, ", ");
10984
0
    break;
10985
0
  case 6:
10986
    // CDE_CX1DA, CDE_CX2DA, CDE_CX3DA
10987
0
    printGPRPairOperand(MI, 0, O);
10988
0
    SStream_concat0(O, ", ");
10989
0
    printOperand(MI, 3, O);
10990
0
    break;
10991
0
  case 7:
10992
    // CDE_CX2D, CDE_CX3D
10993
0
    printOperand(MI, 3, O);
10994
0
    break;
10995
39.2k
  case 8:
10996
    // CDP, MCR, MCRR, MSR, VABSD, VADDD, VCMPD, VCMPED, VDIVD, VMOVD, VMULD,...
10997
39.2k
    printOperand(MI, 1, O);
10998
39.2k
    break;
10999
98
  case 9:
11000
    // FCONSTD
11001
98
    printFPImmOperand(MI, 1, O);
11002
98
    return;
11003
0
    break;
11004
20.0k
  case 10:
11005
    // FLDMXDB_UPD, FLDMXIA_UPD, FSTMXDB_UPD, FSTMXIA_UPD, LDMDA_UPD, LDMDB_U...
11006
20.0k
    SStream_concat0(O, "!, ");
11007
20.0k
    printRegisterList(MI, 4, O);
11008
20.0k
    break;
11009
32.1k
  case 11:
11010
    // LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OPTION,...
11011
32.1k
    printCImmediate(MI, 1, O);
11012
32.1k
    SStream_concat0(O, ", ");
11013
32.1k
    break;
11014
7.91k
  case 12:
11015
    // MRC, MVE_VCVTf16s16_fix, MVE_VCVTf16u16_fix, MVE_VCVTf32s32_fix, MVE_V...
11016
7.91k
    printOperand(MI, 2, O);
11017
7.91k
    break;
11018
510
  case 13:
11019
    // MRS, t2MRS_AR
11020
510
    SStream_concat0(O, ", apsr");
11021
510
    return;
11022
0
    break;
11023
140
  case 14:
11024
    // MRSsys, t2MRSsys_AR
11025
140
    SStream_concat0(O, ", spsr");
11026
140
    return;
11027
0
    break;
11028
741
  case 15:
11029
    // MSRi
11030
741
    printModImmOperand(MI, 1, O);
11031
741
    return;
11032
0
    break;
11033
793
  case 16:
11034
    // MVE_VMOV_to_lane_16, MVE_VMOV_to_lane_32, MVE_VMOV_to_lane_8, VSETLNi1...
11035
793
    printVectorIndex(MI, 3, O);
11036
793
    SStream_concat0(O, ", ");
11037
793
    printOperand(MI, 2, O);
11038
793
    return;
11039
0
    break;
11040
682
  case 17:
11041
    // VCMPEZH, VCMPEZS, VCMPZH, VCMPZS
11042
682
    SStream_concat0(O, ", #0");
11043
682
    return;
11044
0
    break;
11045
12.1k
  case 18:
11046
    // VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32wb_fixed, VLD1DUP...
11047
12.1k
    printAddrMode6Operand(MI, 2, O);
11048
12.1k
    break;
11049
15.0k
  case 19:
11050
    // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8...
11051
15.0k
    SStream_concat1(O, '[');
11052
15.0k
    break;
11053
2.44k
  case 20:
11054
    // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD...
11055
2.44k
    SStream_concat0(O, "[], ");
11056
2.44k
    printOperand(MI, 1, O);
11057
2.44k
    SStream_concat0(O, "[], ");
11058
2.44k
    printOperand(MI, 2, O);
11059
2.44k
    break;
11060
1.31k
  case 21:
11061
    // VLDR_FPCXTNS_post, VLDR_FPCXTS_post, VLDR_FPSCR_NZCVQC_post, VLDR_FPSC...
11062
1.31k
    printT2AddrModeImm8s4OffsetOperand(MI, 2, O);
11063
1.31k
    return;
11064
0
    break;
11065
0
  case 22:
11066
    // VLDR_P0_post, VSTR_P0_post
11067
0
    printT2AddrModeImm8s4OffsetOperand(MI, 3, O);
11068
0
    return;
11069
0
    break;
11070
124
  case 23:
11071
    // VMRS
11072
124
    SStream_concat0(O, ", fpscr");
11073
124
    return;
11074
0
    break;
11075
49
  case 24:
11076
    // VMRS_FPCXTNS
11077
49
    SStream_concat0(O, ", fpcxtns");
11078
49
    return;
11079
0
    break;
11080
103
  case 25:
11081
    // VMRS_FPCXTS
11082
103
    SStream_concat0(O, ", fpcxts");
11083
103
    return;
11084
0
    break;
11085
482
  case 26:
11086
    // VMRS_FPEXC
11087
482
    SStream_concat0(O, ", fpexc");
11088
482
    return;
11089
0
    break;
11090
886
  case 27:
11091
    // VMRS_FPINST
11092
886
    SStream_concat0(O, ", fpinst");
11093
886
    return;
11094
0
    break;
11095
511
  case 28:
11096
    // VMRS_FPINST2
11097
511
    SStream_concat0(O, ", fpinst2");
11098
511
    return;
11099
0
    break;
11100
106
  case 29:
11101
    // VMRS_FPSCR_NZCVQC
11102
106
    SStream_concat0(O, ", fpscr_nzcvqc");
11103
106
    return;
11104
0
    break;
11105
78
  case 30:
11106
    // VMRS_FPSID
11107
78
    SStream_concat0(O, ", fpsid");
11108
78
    return;
11109
0
    break;
11110
74
  case 31:
11111
    // VMRS_MVFR0
11112
74
    SStream_concat0(O, ", mvfr0");
11113
74
    return;
11114
0
    break;
11115
70
  case 32:
11116
    // VMRS_MVFR1
11117
70
    SStream_concat0(O, ", mvfr1");
11118
70
    return;
11119
0
    break;
11120
20
  case 33:
11121
    // VMRS_MVFR2
11122
20
    SStream_concat0(O, ", mvfr2");
11123
20
    return;
11124
0
    break;
11125
0
  case 34:
11126
    // VMRS_P0
11127
0
    SStream_concat0(O, ", p0");
11128
0
    return;
11129
0
    break;
11130
0
  case 35:
11131
    // VMRS_VPR
11132
0
    SStream_concat0(O, ", vpr");
11133
0
    return;
11134
0
    break;
11135
41
  case 36:
11136
    // VSHTOH, VTOSHH, VTOUHH, VUHTOH
11137
41
    printFBits16(MI, 2, O);
11138
41
    return;
11139
0
    break;
11140
1.25k
  case 37:
11141
    // VSLTOD, VSLTOH, VSLTOS, VTOSLD, VTOSLH, VTOSLS, VTOULD, VTOULH, VTOULS...
11142
1.25k
    printFBits32(MI, 2, O);
11143
1.25k
    return;
11144
0
    break;
11145
1.02M
  }
11146
11147
11148
  // Fragment 4 encoded into 7 bits for 78 unique commands.
11149
814k
  switch ((Bits >> 39) & 127) {
11150
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
11151
168k
  case 0:
11152
    // ASRi, ASRr, LDRConstPool, LSLi, LSLr, LSRi, LSRr, RORi, RORr, RRXi, t2...
11153
168k
    printOperand(MI, 1, O);
11154
168k
    break;
11155
138
  case 1:
11156
    // LDRBT_POST, LDRHTii, LDRSBTii, LDRSHTii, LDRT_POST, STRBT_POST, STRT_P...
11157
138
    printAddrMode7Operand(MI, 1, O);
11158
138
    return;
11159
0
    break;
11160
0
  case 2:
11161
    // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL...
11162
0
    printAddrMode6Operand(MI, 2, O);
11163
0
    break;
11164
112k
  case 3:
11165
    // VLD3DUPdWB_register_Asm_16, VLD3DUPdWB_register_Asm_32, VLD3DUPdWB_reg...
11166
112k
    printOperand(MI, 3, O);
11167
112k
    break;
11168
32.9k
  case 4:
11169
    // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD4dAsm_16, VLD4dAsm_32, VLD4dA...
11170
32.9k
    return;
11171
0
    break;
11172
5.66k
  case 5:
11173
    // VLD3dWB_fixed_Asm_16, VLD3dWB_fixed_Asm_32, VLD3dWB_fixed_Asm_8, VLD4d...
11174
5.66k
    SStream_concat1(O, '!');
11175
5.66k
    return;
11176
0
    break;
11177
42.8k
  case 6:
11178
    // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm...
11179
42.8k
    SStream_concat0(O, ", ");
11180
42.8k
    break;
11181
0
  case 7:
11182
    // t2LDRB_POST_imm, t2LDRH_POST_imm, t2LDRSB_POST_imm, t2LDRSH_POST_imm, ...
11183
0
    printT2AddrModeImm8OffsetOperand(MI, 2, O);
11184
0
    return;
11185
0
    break;
11186
661
  case 8:
11187
    // t2MOVSsi, t2MOVsi, t2CMNzrs, t2CMPrs, t2MVNs, t2TEQrs, t2TSTrs
11188
661
    printT2SOOperand(MI, 1, O);
11189
661
    return;
11190
0
    break;
11191
1.05k
  case 9:
11192
    // t2MOVSsr, t2MOVsr, CMNzrsr, CMPrsr, MOVsr, MVNsr, TEQrsr, TSTrsr
11193
1.05k
    printSORegRegOperand(MI, 1, O);
11194
1.05k
    return;
11195
0
    break;
11196
665
  case 10:
11197
    // ADR, t2ADR
11198
665
    printAdrLabelOperand_0(MI, 1, O);
11199
665
    return;
11200
0
    break;
11201
693
  case 11:
11202
    // BFC, t2BFC
11203
693
    printBitfieldInvMaskImmOperand(MI, 2, O);
11204
693
    return;
11205
0
    break;
11206
25.1k
  case 12:
11207
    // BFI, CDE_VCX1_vec, CDE_VCX2_vec, CDE_VCX3_vec, CPS3p, CRC32B, CRC32CB,...
11208
25.1k
    printOperand(MI, 2, O);
11209
25.1k
    break;
11210
0
  case 13:
11211
    // CDE_VCX2A_fpdp, CDE_VCX2A_fpsp, CDE_VCX3A_fpdp, CDE_VCX3A_fpsp
11212
0
    printOperand(MI, 4, O);
11213
0
    break;
11214
2.07k
  case 14:
11215
    // CMNri, CMPri, MOVi, MVNi, TEQri, TSTri
11216
2.07k
    printModImmOperand(MI, 1, O);
11217
2.07k
    return;
11218
0
    break;
11219
1.92k
  case 15:
11220
    // CMNzrsi, CMPrsi, MOVsi, MVNsi, TEQrsi, TSTrsi
11221
1.92k
    printSORegImmOperand(MI, 1, O);
11222
1.92k
    return;
11223
0
    break;
11224
530
  case 16:
11225
    // FCONSTH, FCONSTS, MVE_VMOVimmf32, VMOVv2f32, VMOVv4f32
11226
530
    printFPImmOperand(MI, 1, O);
11227
530
    return;
11228
0
    break;
11229
5.06k
  case 17:
11230
    // FLDMXIA, FSTMXIA, LDMDA, LDMDB, LDMIA, LDMIB, STMDA, STMDB, STMIA, STM...
11231
5.06k
    printRegisterList(MI, 3, O);
11232
5.06k
    break;
11233
476
  case 18:
11234
    // LDC2L_OPTION, LDC2_OPTION, STC2L_OPTION, STC2_OPTION
11235
476
    printCoprocOptionImm(MI, 3, O);
11236
476
    return;
11237
0
    break;
11238
1.38k
  case 19:
11239
    // LDC2L_POST, LDC2_POST, STC2L_POST, STC2_POST
11240
1.38k
    printPostIdxImm8s4Operand(MI, 3, O);
11241
1.38k
    return;
11242
0
    break;
11243
9.60k
  case 20:
11244
    // LDCL_OFFSET, LDC_OFFSET, STCL_OFFSET, STC_OFFSET, t2LDC2L_OFFSET, t2LD...
11245
9.60k
    printAddrMode5Operand_0(MI, 2, O);
11246
9.60k
    return;
11247
0
    break;
11248
32.3k
  case 21:
11249
    // LDCL_OPTION, LDCL_POST, LDC_OPTION, LDC_POST, LDRBT_POST_IMM, LDRBT_PO...
11250
32.3k
    printAddrMode7Operand(MI, 2, O);
11251
32.3k
    break;
11252
9.62k
  case 22:
11253
    // LDCL_PRE, LDC_PRE, STCL_PRE, STC_PRE, t2LDC2L_PRE, t2LDC2_PRE, t2LDCL_...
11254
9.62k
    printAddrMode5Operand_1(MI, 2, O);
11255
9.62k
    SStream_concat1(O, '!');
11256
9.62k
    return;
11257
0
    break;
11258
3.02k
  case 23:
11259
    // LDRB_PRE_IMM, LDR_PRE_IMM, STRB_PRE_IMM, STR_PRE_IMM
11260
3.02k
    printAddrModeImm12Operand_1(MI, 2, O);
11261
3.02k
    SStream_concat1(O, '!');
11262
3.02k
    return;
11263
0
    break;
11264
4.65k
  case 24:
11265
    // LDRB_PRE_REG, LDR_PRE_REG, STRB_PRE_REG, STR_PRE_REG
11266
4.65k
    printAddrMode2Operand(MI, 2, O);
11267
4.65k
    SStream_concat1(O, '!');
11268
4.65k
    return;
11269
0
    break;
11270
4.06k
  case 25:
11271
    // LDRBi12, LDRcp, LDRi12, STRBi12, STRi12, t2LDRBi12, t2LDRHi12, t2LDRSB...
11272
4.06k
    printAddrModeImm12Operand_0(MI, 1, O);
11273
4.06k
    return;
11274
0
    break;
11275
2.09k
  case 26:
11276
    // LDRBrs, LDRrs, STRBrs, STRrs
11277
2.09k
    printAddrMode2Operand(MI, 1, O);
11278
2.09k
    return;
11279
0
    break;
11280
1.11k
  case 27:
11281
    // LDRH, LDRSB, LDRSH, STRH
11282
1.11k
    printAddrMode3Operand_0(MI, 1, O);
11283
1.11k
    return;
11284
0
    break;
11285
2.12k
  case 28:
11286
    // LDRH_PRE, LDRSB_PRE, LDRSH_PRE, STRH_PRE
11287
2.12k
    printAddrMode3Operand_1(MI, 2, O);
11288
2.12k
    SStream_concat1(O, '!');
11289
2.12k
    return;
11290
0
    break;
11291
474
  case 29:
11292
    // MCR2, MRC2
11293
474
    printCImmediate(MI, 3, O);
11294
474
    SStream_concat0(O, ", ");
11295
474
    printCImmediate(MI, 4, O);
11296
474
    SStream_concat0(O, ", ");
11297
474
    printOperand(MI, 5, O);
11298
474
    return;
11299
0
    break;
11300
322
  case 30:
11301
    // MRSbanked, t2MRSbanked
11302
322
    printBankedRegOperand(MI, 1, O);
11303
322
    return;
11304
0
    break;
11305
569
  case 31:
11306
    // MVE_VBICimmi16, MVE_VBICimmi32, MVE_VORRimmi16, MVE_VORRimmi32
11307
569
    printVMOVModImmOperand(MI, 2, O);
11308
569
    return;
11309
0
    break;
11310
7.45k
  case 32:
11311
    // MVE_VLDRBS16, MVE_VLDRBS32, MVE_VLDRBU16, MVE_VLDRBU32, MVE_VLDRBU8, M...
11312
7.45k
    printT2AddrModeImm8Operand_0(MI, 1, O);
11313
7.45k
    return;
11314
0
    break;
11315
2.37k
  case 33:
11316
    // MVE_VLDRBS16_pre, MVE_VLDRBS32_pre, MVE_VLDRBU16_pre, MVE_VLDRBU32_pre...
11317
2.37k
    printT2AddrModeImm8Operand_0(MI, 2, O);
11318
2.37k
    SStream_concat1(O, '!');
11319
2.37k
    return;
11320
0
    break;
11321
131
  case 34:
11322
    // MVE_VLDRBS16_rq, MVE_VLDRBS32_rq, MVE_VLDRBU16_rq, MVE_VLDRBU32_rq, MV...
11323
131
    printMveAddrModeRQOperand_0(MI, 1, O);
11324
131
    return;
11325
0
    break;
11326
3.79k
  case 35:
11327
    // MVE_VLDRBU8_pre, MVE_VLDRHU16_pre, MVE_VLDRWU32_pre, MVE_VSTRBU8_pre, ...
11328
3.79k
    printT2AddrModeImm8Operand_1(MI, 2, O);
11329
3.79k
    SStream_concat1(O, '!');
11330
3.79k
    return;
11331
0
    break;
11332
69
  case 36:
11333
    // MVE_VLDRDU64_rq, MVE_VSTRD64_rq
11334
69
    printMveAddrModeRQOperand_3(MI, 1, O);
11335
69
    return;
11336
0
    break;
11337
129
  case 37:
11338
    // MVE_VLDRHS32_rq, MVE_VLDRHU16_rq, MVE_VLDRHU32_rq, MVE_VSTRH16_rq, MVE...
11339
129
    printMveAddrModeRQOperand_1(MI, 1, O);
11340
129
    return;
11341
0
    break;
11342
86
  case 38:
11343
    // MVE_VLDRWU32_rq, MVE_VSTRW32_rq
11344
86
    printMveAddrModeRQOperand_2(MI, 1, O);
11345
86
    return;
11346
0
    break;
11347
4.07k
  case 39:
11348
    // MVE_VMOVimmi16, MVE_VMOVimmi32, MVE_VMOVimmi8, MVE_VMVNimmi16, MVE_VMV...
11349
4.07k
    printVMOVModImmOperand(MI, 1, O);
11350
4.07k
    return;
11351
0
    break;
11352
1.97k
  case 40:
11353
    // MVE_WLSTP_16, MVE_WLSTP_32, MVE_WLSTP_64, MVE_WLSTP_8, t2BFic, t2WLS
11354
1.97k
    printOperandAddr(MI, Address, 2, O);
11355
1.97k
    break;
11356
782
  case 41:
11357
    // SSAT, SSAT16, t2SSAT, t2SSAT16
11358
782
    printImmPlusOneOperand(MI, 1, O);
11359
782
    SStream_concat0(O, ", ");
11360
782
    printOperand(MI, 2, O);
11361
782
    break;
11362
958
  case 42:
11363
    // STLEXD, STREXD
11364
958
    printGPRPairOperand(MI, 1, O);
11365
958
    SStream_concat0(O, ", ");
11366
958
    printAddrMode7Operand(MI, 2, O);
11367
958
    return;
11368
0
    break;
11369
1.48k
  case 43:
11370
    // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST2LNd16, VST2LNd32, VST2LNd8, VST2LN...
11371
1.48k
    printNoHashImmediate(MI, 4, O);
11372
1.48k
    break;
11373
4.50k
  case 44:
11374
    // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2...
11375
4.50k
    printNoHashImmediate(MI, 6, O);
11376
4.50k
    break;
11377
3.46k
  case 45:
11378
    // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U...
11379
3.46k
    printNoHashImmediate(MI, 8, O);
11380
3.46k
    SStream_concat0(O, "], ");
11381
3.46k
    break;
11382
734
  case 46:
11383
    // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD...
11384
734
    SStream_concat0(O, "[]}, ");
11385
734
    break;
11386
2.10k
  case 47:
11387
    // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U...
11388
2.10k
    printNoHashImmediate(MI, 10, O);
11389
2.10k
    SStream_concat0(O, "], ");
11390
2.10k
    printOperand(MI, 1, O);
11391
2.10k
    SStream_concat1(O, '[');
11392
2.10k
    printNoHashImmediate(MI, 10, O);
11393
2.10k
    SStream_concat0(O, "], ");
11394
2.10k
    printOperand(MI, 2, O);
11395
2.10k
    SStream_concat1(O, '[');
11396
2.10k
    printNoHashImmediate(MI, 10, O);
11397
2.10k
    break;
11398
1.70k
  case 48:
11399
    // VLD4DUPd16, VLD4DUPd16_UPD, VLD4DUPd32, VLD4DUPd32_UPD, VLD4DUPd8, VLD...
11400
1.70k
    SStream_concat0(O, "[], ");
11401
1.70k
    printOperand(MI, 3, O);
11402
1.70k
    SStream_concat0(O, "[]}, ");
11403
1.70k
    break;
11404
1.35k
  case 49:
11405
    // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U...
11406
1.35k
    printNoHashImmediate(MI, 12, O);
11407
1.35k
    SStream_concat0(O, "], ");
11408
1.35k
    printOperand(MI, 1, O);
11409
1.35k
    SStream_concat1(O, '[');
11410
1.35k
    printNoHashImmediate(MI, 12, O);
11411
1.35k
    SStream_concat0(O, "], ");
11412
1.35k
    printOperand(MI, 2, O);
11413
1.35k
    SStream_concat1(O, '[');
11414
1.35k
    printNoHashImmediate(MI, 12, O);
11415
1.35k
    SStream_concat0(O, "], ");
11416
1.35k
    printOperand(MI, 3, O);
11417
1.35k
    SStream_concat1(O, '[');
11418
1.35k
    printNoHashImmediate(MI, 12, O);
11419
1.35k
    SStream_concat0(O, "]}, ");
11420
1.35k
    printAddrMode6Operand(MI, 5, O);
11421
1.35k
    printAddrMode6OffsetOperand(MI, 7, O);
11422
1.35k
    return;
11423
0
    break;
11424
593
  case 50:
11425
    // VLDRD, VLDRS, VSTRD, VSTRS
11426
593
    printAddrMode5Operand_0(MI, 1, O);
11427
593
    return;
11428
0
    break;
11429
617
  case 51:
11430
    // VLDRH, VSTRH
11431
617
    printAddrMode5FP16Operand_0(MI, 1, O);
11432
617
    return;
11433
0
    break;
11434
250
  case 52:
11435
    // VST1LNd16, VST1LNd32, VST1LNd8
11436
250
    printNoHashImmediate(MI, 3, O);
11437
250
    SStream_concat0(O, "]}, ");
11438
250
    printAddrMode6Operand(MI, 0, O);
11439
250
    return;
11440
0
    break;
11441
1.60k
  case 53:
11442
    // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST3LNd16, VST3LNd32, VST3...
11443
1.60k
    printNoHashImmediate(MI, 5, O);
11444
1.60k
    break;
11445
310
  case 54:
11446
    // VST3LNd16_UPD, VST3LNd32_UPD, VST3LNd8_UPD, VST3LNq16_UPD, VST3LNq32_U...
11447
310
    printNoHashImmediate(MI, 7, O);
11448
310
    SStream_concat0(O, "], ");
11449
310
    printOperand(MI, 5, O);
11450
310
    SStream_concat1(O, '[');
11451
310
    printNoHashImmediate(MI, 7, O);
11452
310
    SStream_concat0(O, "], ");
11453
310
    printOperand(MI, 6, O);
11454
310
    SStream_concat1(O, '[');
11455
310
    printNoHashImmediate(MI, 7, O);
11456
310
    SStream_concat0(O, "]}, ");
11457
310
    printAddrMode6Operand(MI, 1, O);
11458
310
    printAddrMode6OffsetOperand(MI, 3, O);
11459
310
    return;
11460
0
    break;
11461
3.30k
  case 55:
11462
    // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8...
11463
3.30k
    printOperand(MI, 5, O);
11464
3.30k
    SStream_concat0(O, ", ");
11465
3.30k
    printOperand(MI, 6, O);
11466
3.30k
    break;
11467
232
  case 56:
11468
    // VTBL1
11469
232
    printVectorListOne(MI, 1, O);
11470
232
    SStream_concat0(O, ", ");
11471
232
    printOperand(MI, 2, O);
11472
232
    return;
11473
0
    break;
11474
324
  case 57:
11475
    // VTBL2
11476
324
    printVectorListTwo(MI, 1, O);
11477
324
    SStream_concat0(O, ", ");
11478
324
    printOperand(MI, 2, O);
11479
324
    return;
11480
0
    break;
11481
431
  case 58:
11482
    // VTBL3
11483
431
    printVectorListThree(MI, 1, O);
11484
431
    SStream_concat0(O, ", ");
11485
431
    printOperand(MI, 2, O);
11486
431
    return;
11487
0
    break;
11488
193
  case 59:
11489
    // VTBL4
11490
193
    printVectorListFour(MI, 1, O);
11491
193
    SStream_concat0(O, ", ");
11492
193
    printOperand(MI, 2, O);
11493
193
    return;
11494
0
    break;
11495
109
  case 60:
11496
    // VTBX1
11497
109
    printVectorListOne(MI, 2, O);
11498
109
    SStream_concat0(O, ", ");
11499
109
    printOperand(MI, 3, O);
11500
109
    return;
11501
0
    break;
11502
167
  case 61:
11503
    // VTBX2
11504
167
    printVectorListTwo(MI, 2, O);
11505
167
    SStream_concat0(O, ", ");
11506
167
    printOperand(MI, 3, O);
11507
167
    return;
11508
0
    break;
11509
85
  case 62:
11510
    // VTBX3
11511
85
    printVectorListThree(MI, 2, O);
11512
85
    SStream_concat0(O, ", ");
11513
85
    printOperand(MI, 3, O);
11514
85
    return;
11515
0
    break;
11516
225
  case 63:
11517
    // VTBX4
11518
225
    printVectorListFour(MI, 2, O);
11519
225
    SStream_concat0(O, ", ");
11520
225
    printOperand(MI, 3, O);
11521
225
    return;
11522
0
    break;
11523
2.46k
  case 64:
11524
    // sysLDMDA_UPD, sysLDMDB_UPD, sysLDMIA_UPD, sysLDMIB_UPD, sysSTMDA_UPD, ...
11525
2.46k
    SStream_concat0(O, " ^");
11526
2.46k
    return;
11527
0
    break;
11528
1.07k
  case 65:
11529
    // t2BFLi, t2BFi
11530
1.07k
    printOperandAddr(MI, Address, 1, O);
11531
1.07k
    return;
11532
0
    break;
11533
24.1k
  case 66:
11534
    // t2LDRBpci, t2LDRHpci, t2LDRSBpci, t2LDRSHpci, t2LDRpci, tLDRpci
11535
24.1k
    printThumbLdrLabelOperand(MI, 1, O);
11536
24.1k
    return;
11537
0
    break;
11538
1.20k
  case 67:
11539
    // t2LDRBs, t2LDRHs, t2LDRSBs, t2LDRSHs, t2LDRs, t2STRBs, t2STRHs, t2STRs
11540
1.20k
    printT2AddrModeSoRegOperand(MI, 1, O);
11541
1.20k
    return;
11542
0
    break;
11543
82
  case 68:
11544
    // t2LDREX
11545
82
    printT2AddrModeImm0_1020s4Operand(MI, 1, O);
11546
82
    return;
11547
0
    break;
11548
1.77k
  case 69:
11549
    // t2MRS_M
11550
1.77k
    printMSRMaskOperand(MI, 1, O);
11551
1.77k
    return;
11552
0
    break;
11553
1.69k
  case 70:
11554
    // tADDspi, tSUBspi
11555
1.69k
    printThumbS4ImmOperand(MI, 2, O);
11556
1.69k
    return;
11557
0
    break;
11558
19.1k
  case 71:
11559
    // tADR
11560
19.1k
    printAdrLabelOperandAddr_2(MI, Address, 1, O);
11561
19.1k
    return;
11562
0
    break;
11563
52.9k
  case 72:
11564
    // tASRri, tLSRri
11565
52.9k
    printThumbSRImm(MI, 3, O);
11566
52.9k
    return;
11567
0
    break;
11568
38.2k
  case 73:
11569
    // tLDRBi, tSTRBi
11570
38.2k
    printThumbAddrModeImm5S1Operand(MI, 1, O);
11571
38.2k
    return;
11572
0
    break;
11573
24.9k
  case 74:
11574
    // tLDRBr, tLDRHr, tLDRSB, tLDRSH, tLDRr, tSTRBr, tSTRHr, tSTRr
11575
24.9k
    printThumbAddrModeRROperand(MI, 1, O);
11576
24.9k
    return;
11577
0
    break;
11578
47.4k
  case 75:
11579
    // tLDRHi, tSTRHi
11580
47.4k
    printThumbAddrModeImm5S2Operand(MI, 1, O);
11581
47.4k
    return;
11582
0
    break;
11583
52.2k
  case 76:
11584
    // tLDRi, tSTRi
11585
52.2k
    printThumbAddrModeImm5S4Operand(MI, 1, O);
11586
52.2k
    return;
11587
0
    break;
11588
29.0k
  case 77:
11589
    // tLDRspi, tSTRspi
11590
29.0k
    printThumbAddrModeSPOperand(MI, 1, O);
11591
29.0k
    return;
11592
0
    break;
11593
814k
  }
11594
11595
11596
  // Fragment 5 encoded into 5 bits for 27 unique commands.
11597
407k
  switch ((Bits >> 46) & 31) {
11598
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
11599
161k
  case 0:
11600
    // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm...
11601
161k
    SStream_concat0(O, ", ");
11602
161k
    break;
11603
166k
  case 1:
11604
    // LDRConstPool, RRXi, VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD2LN...
11605
166k
    return;
11606
0
    break;
11607
0
  case 2:
11608
    // VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_fixed_Asm_8,...
11609
0
    SStream_concat1(O, '!');
11610
0
    return;
11611
0
    break;
11612
834
  case 3:
11613
    // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm...
11614
834
    printOperand(MI, 3, O);
11615
834
    return;
11616
0
    break;
11617
6.48k
  case 4:
11618
    // CDE_CX2DA, CDE_CX3D, CDE_CX3DA, VLD1DUPd16wb_register, VLD1DUPd32wb_re...
11619
6.48k
    printOperand(MI, 4, O);
11620
6.48k
    break;
11621
24.8k
  case 5:
11622
    // CDP, t2CDP, t2CDP2
11623
24.8k
    printCImmediate(MI, 2, O);
11624
24.8k
    SStream_concat0(O, ", ");
11625
24.8k
    printCImmediate(MI, 3, O);
11626
24.8k
    SStream_concat0(O, ", ");
11627
24.8k
    printCImmediate(MI, 4, O);
11628
24.8k
    SStream_concat0(O, ", ");
11629
24.8k
    printOperand(MI, 5, O);
11630
24.8k
    return;
11631
0
    break;
11632
5.45k
  case 6:
11633
    // MCR, MCRR, VADDD, VDIVD, VMULD, VNMULD, VSUBD, t2MCR, t2MCR2, t2MCRR, ...
11634
5.45k
    printOperand(MI, 2, O);
11635
5.45k
    break;
11636
5.21k
  case 7:
11637
    // MRC, t2MRC, t2MRC2
11638
5.21k
    printOperand(MI, 0, O);
11639
5.21k
    SStream_concat0(O, ", ");
11640
5.21k
    printCImmediate(MI, 3, O);
11641
5.21k
    SStream_concat0(O, ", ");
11642
5.21k
    printCImmediate(MI, 4, O);
11643
5.21k
    SStream_concat0(O, ", ");
11644
5.21k
    printOperand(MI, 5, O);
11645
5.21k
    return;
11646
0
    break;
11647
2.47k
  case 8:
11648
    // MVE_VLDRBS16_post, MVE_VLDRBS32_post, MVE_VLDRBU16_post, MVE_VLDRBU32_...
11649
2.47k
    printT2AddrModeImm8OffsetOperand(MI, 3, O);
11650
2.47k
    return;
11651
0
    break;
11652
1.64k
  case 9:
11653
    // MVE_VMOV_from_lane_32, MVE_VMOV_from_lane_s16, MVE_VMOV_from_lane_s8, ...
11654
1.64k
    printVectorIndex(MI, 2, O);
11655
1.64k
    return;
11656
0
    break;
11657
2.10k
  case 10:
11658
    // MVE_VMOV_q_rr, VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_U...
11659
2.10k
    printOperand(MI, 1, O);
11660
2.10k
    break;
11661
618
  case 11:
11662
    // MVE_VSHLL_lws16bh, MVE_VSHLL_lws16th, MVE_VSHLL_lwu16bh, MVE_VSHLL_lwu...
11663
618
    SStream_concat0(O, ", #16");
11664
618
    return;
11665
0
    break;
11666
1.06k
  case 12:
11667
    // MVE_VSHLL_lws8bh, MVE_VSHLL_lws8th, MVE_VSHLL_lwu8bh, MVE_VSHLL_lwu8th
11668
1.06k
    SStream_concat0(O, ", #8");
11669
1.06k
    return;
11670
0
    break;
11671
769
  case 13:
11672
    // SSAT, t2SSAT
11673
769
    printShiftImmOperand(MI, 3, O);
11674
769
    return;
11675
0
    break;
11676
437
  case 14:
11677
    // SXTB, SXTB16, SXTH, UXTB, UXTB16, UXTH, t2SXTB, t2SXTB16, t2SXTH, t2UX...
11678
437
    printRotImmOperand(MI, 2, O);
11679
437
    return;
11680
0
    break;
11681
9.73k
  case 15:
11682
    // VCEQzv16i8, VCEQzv2f32, VCEQzv2i32, VCEQzv4f16, VCEQzv4f32, VCEQzv4i16...
11683
9.73k
    SStream_concat0(O, ", #0");
11684
9.73k
    return;
11685
0
    break;
11686
632
  case 16:
11687
    // VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed, VCMLAv8f16...
11688
632
    printVectorIndex(MI, 4, O);
11689
632
    SStream_concat0(O, ", ");
11690
632
    printComplexRotationOp_90_0(MI, 5, O);
11691
632
    return;
11692
0
    break;
11693
497
  case 17:
11694
    // VFMALDI, VFMALQI, VFMSLDI, VFMSLQI
11695
497
    printVectorIndex(MI, 3, O);
11696
497
    return;
11697
0
    break;
11698
3.01k
  case 18:
11699
    // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8...
11700
3.01k
    SStream_concat0(O, "]}, ");
11701
3.01k
    break;
11702
6.69k
  case 19:
11703
    // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32, VLD4LNd16, VLD4L...
11704
6.69k
    SStream_concat0(O, "], ");
11705
6.69k
    break;
11706
46
  case 20:
11707
    // VLD3DUPd16, VLD3DUPd32, VLD3DUPd8, VLD3DUPq16, VLD3DUPq32, VLD3DUPq8
11708
46
    printAddrMode6Operand(MI, 3, O);
11709
46
    return;
11710
0
    break;
11711
1.37k
  case 21:
11712
    // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP...
11713
1.37k
    printAddrMode6Operand(MI, 4, O);
11714
1.37k
    break;
11715
1.02k
  case 22:
11716
    // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP...
11717
1.02k
    printAddrMode6Operand(MI, 5, O);
11718
1.02k
    printAddrMode6OffsetOperand(MI, 7, O);
11719
1.02k
    return;
11720
0
    break;
11721
1.60k
  case 23:
11722
    // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8...
11723
1.60k
    SStream_concat0(O, "}, ");
11724
1.60k
    printAddrMode6Operand(MI, 1, O);
11725
1.60k
    printAddrMode6OffsetOperand(MI, 3, O);
11726
1.60k
    return;
11727
0
    break;
11728
1.36k
  case 24:
11729
    // VST4LNd16_UPD, VST4LNd32_UPD, VST4LNd8_UPD, VST4LNq16_UPD, VST4LNq32_U...
11730
1.36k
    printOperand(MI, 5, O);
11731
1.36k
    SStream_concat1(O, '[');
11732
1.36k
    printNoHashImmediate(MI, 8, O);
11733
1.36k
    SStream_concat0(O, "], ");
11734
1.36k
    printOperand(MI, 6, O);
11735
1.36k
    SStream_concat1(O, '[');
11736
1.36k
    printNoHashImmediate(MI, 8, O);
11737
1.36k
    SStream_concat0(O, "], ");
11738
1.36k
    printOperand(MI, 7, O);
11739
1.36k
    SStream_concat1(O, '[');
11740
1.36k
    printNoHashImmediate(MI, 8, O);
11741
1.36k
    SStream_concat0(O, "]}, ");
11742
1.36k
    printAddrMode6Operand(MI, 1, O);
11743
1.36k
    printAddrMode6OffsetOperand(MI, 3, O);
11744
1.36k
    return;
11745
0
    break;
11746
2.05k
  case 25:
11747
    // sysLDMDA, sysLDMDB, sysLDMIA, sysLDMIB, sysSTMDA, sysSTMDB, sysSTMIA, ...
11748
2.05k
    SStream_concat0(O, " ^");
11749
2.05k
    return;
11750
0
    break;
11751
0
  case 26:
11752
    // t2MOVsra_glue, t2MOVsrl_glue
11753
0
    SStream_concat0(O, ", #1");
11754
0
    return;
11755
0
    break;
11756
407k
  }
11757
11758
11759
  // Fragment 6 encoded into 6 bits for 38 unique commands.
11760
186k
  switch ((Bits >> 51) & 63) {
11761
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
11762
61.0k
  case 0:
11763
    // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, ADCrr, ADDrr, ANDrr, B...
11764
61.0k
    printOperand(MI, 2, O);
11765
61.0k
    break;
11766
7.58k
  case 1:
11767
    // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist...
11768
7.58k
    printOperand(MI, 4, O);
11769
7.58k
    break;
11770
5.05k
  case 2:
11771
    // ADCri, ADDri, ANDri, BICri, EORri, ORRri, RSBri, RSCri, SBCri, SUBri
11772
5.05k
    printModImmOperand(MI, 2, O);
11773
5.05k
    return;
11774
0
    break;
11775
10.0k
  case 3:
11776
    // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, ORRrsi, RSBrsi, RSCrsi, SBCrsi...
11777
10.0k
    printSORegImmOperand(MI, 2, O);
11778
10.0k
    return;
11779
0
    break;
11780
262
  case 4:
11781
    // BFI, t2BFI
11782
262
    printBitfieldInvMaskImmOperand(MI, 3, O);
11783
262
    return;
11784
0
    break;
11785
7.56k
  case 5:
11786
    // CDE_CX2DA, CDE_CX3D, VADDD, VDIVD, VLD1DUPd16wb_register, VLD1DUPd32wb...
11787
7.56k
    return;
11788
0
    break;
11789
5.05k
  case 6:
11790
    // CDE_CX3DA, MCR, MCRR, t2MCR, t2MCR2, t2MCRR, t2MCRR2
11791
5.05k
    SStream_concat0(O, ", ");
11792
5.05k
    break;
11793
15.3k
  case 7:
11794
    // CDE_VCX2_vec, CDE_VCX3_vec, MVE_VABAVs16, MVE_VABAVs32, MVE_VABAVs8, M...
11795
15.3k
    printOperand(MI, 3, O);
11796
15.3k
    break;
11797
1.79k
  case 8:
11798
    // CDE_VCX3A_fpdp, CDE_VCX3A_fpsp, VST2LNd16_UPD, VST2LNd32_UPD, VST2LNd8...
11799
1.79k
    printOperand(MI, 5, O);
11800
1.79k
    break;
11801
4.29k
  case 9:
11802
    // LDCL_OPTION, LDC_OPTION, STCL_OPTION, STC_OPTION, t2LDC2L_OPTION, t2LD...
11803
4.29k
    printCoprocOptionImm(MI, 3, O);
11804
4.29k
    return;
11805
0
    break;
11806
8.59k
  case 10:
11807
    // LDCL_POST, LDC_POST, STCL_POST, STC_POST, t2LDC2L_POST, t2LDC2_POST, t...
11808
8.59k
    printPostIdxImm8s4Operand(MI, 3, O);
11809
8.59k
    return;
11810
0
    break;
11811
10.1k
  case 11:
11812
    // LDRBT_POST_IMM, LDRBT_POST_REG, LDRB_POST_IMM, LDRB_POST_REG, LDRT_POS...
11813
10.1k
    printAddrMode2OffsetOperand(MI, 3, O);
11814
10.1k
    return;
11815
0
    break;
11816
1.11k
  case 12:
11817
    // LDRD, STRD
11818
1.11k
    printAddrMode3Operand_0(MI, 2, O);
11819
1.11k
    return;
11820
0
    break;
11821
3.06k
  case 13:
11822
    // LDRD_POST, STRD_POST, t2LDRD_POST, t2STRD_POST
11823
3.06k
    printAddrMode7Operand(MI, 3, O);
11824
3.06k
    break;
11825
759
  case 14:
11826
    // LDRD_PRE, STRD_PRE
11827
759
    printAddrMode3Operand_1(MI, 3, O);
11828
759
    SStream_concat1(O, '!');
11829
759
    return;
11830
0
    break;
11831
968
  case 15:
11832
    // LDRHTi, LDRSBTi, LDRSHTi, STRHTi
11833
968
    printPostIdxImm8Operand(MI, 3, O);
11834
968
    return;
11835
0
    break;
11836
2.65k
  case 16:
11837
    // LDRHTr, LDRSBTr, LDRSHTr, STRHTr
11838
2.65k
    printPostIdxRegOperand(MI, 3, O);
11839
2.65k
    return;
11840
0
    break;
11841
3.24k
  case 17:
11842
    // LDRH_POST, LDRSB_POST, LDRSH_POST, STRH_POST
11843
3.24k
    printAddrMode3OffsetOperand(MI, 3, O);
11844
3.24k
    return;
11845
0
    break;
11846
374
  case 18:
11847
    // MCRR2
11848
374
    printCImmediate(MI, 4, O);
11849
374
    return;
11850
0
    break;
11851
0
  case 19:
11852
    // MVE_SQRSHRL, MVE_UQRSHLL
11853
0
    printMveSaturateOp(MI, 5, O);
11854
0
    SStream_concat0(O, ", ");
11855
0
    printOperand(MI, 4, O);
11856
0
    return;
11857
0
    break;
11858
0
  case 20:
11859
    // MVE_VMOV_q_rr
11860
0
    printVectorIndex(MI, 5, O);
11861
0
    SStream_concat0(O, ", ");
11862
0
    printOperand(MI, 2, O);
11863
0
    SStream_concat0(O, ", ");
11864
0
    printOperand(MI, 3, O);
11865
0
    return;
11866
0
    break;
11867
1.46k
  case 21:
11868
    // STLEX, STLEXB, STLEXH, STREX, STREXB, STREXH, SWP, SWPB, t2LDAEXD, t2L...
11869
1.46k
    printAddrMode7Operand(MI, 2, O);
11870
1.46k
    return;
11871
0
    break;
11872
364
  case 22:
11873
    // VCADDv2f32, VCADDv4f16, VCADDv4f32, VCADDv8f16
11874
364
    printComplexRotationOp_180_90(MI, 3, O);
11875
364
    return;
11876
0
    break;
11877
389
  case 23:
11878
    // VCMLAv2f32, VCMLAv4f16, VCMLAv4f32, VCMLAv8f16
11879
389
    printComplexRotationOp_90_0(MI, 4, O);
11880
389
    return;
11881
0
    break;
11882
1.30k
  case 24:
11883
    // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8...
11884
1.30k
    printAddrMode6Operand(MI, 1, O);
11885
1.30k
    break;
11886
848
  case 25:
11887
    // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD
11888
848
    printAddrMode6Operand(MI, 2, O);
11889
848
    printAddrMode6OffsetOperand(MI, 4, O);
11890
848
    return;
11891
0
    break;
11892
224
  case 26:
11893
    // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32
11894
224
    printOperand(MI, 1, O);
11895
224
    SStream_concat1(O, '[');
11896
224
    printNoHashImmediate(MI, 6, O);
11897
224
    SStream_concat0(O, "]}, ");
11898
224
    printAddrMode6Operand(MI, 2, O);
11899
224
    return;
11900
0
    break;
11901
2.10k
  case 27:
11902
    // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U...
11903
2.10k
    SStream_concat1(O, '[');
11904
2.10k
    printNoHashImmediate(MI, 8, O);
11905
2.10k
    break;
11906
688
  case 28:
11907
    // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP...
11908
688
    printAddrMode6OffsetOperand(MI, 6, O);
11909
688
    return;
11910
0
    break;
11911
864
  case 29:
11912
    // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U...
11913
864
    printAddrMode6Operand(MI, 4, O);
11914
864
    printAddrMode6OffsetOperand(MI, 6, O);
11915
864
    return;
11916
0
    break;
11917
1.69k
  case 30:
11918
    // VST4d16_UPD, VST4d32_UPD, VST4d8_UPD, VST4q16_UPD, VST4q32_UPD, VST4q8...
11919
1.69k
    printOperand(MI, 7, O);
11920
1.69k
    SStream_concat0(O, "}, ");
11921
1.69k
    printAddrMode6Operand(MI, 1, O);
11922
1.69k
    printAddrMode6OffsetOperand(MI, 3, O);
11923
1.69k
    return;
11924
0
    break;
11925
3.24k
  case 31:
11926
    // t2ADCrs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2ORNrs, t2ORRrs, t2RSBrs...
11927
3.24k
    printT2SOOperand(MI, 2, O);
11928
3.24k
    return;
11929
0
    break;
11930
674
  case 32:
11931
    // t2ASRri, t2LSRri
11932
674
    printThumbSRImm(MI, 2, O);
11933
674
    return;
11934
0
    break;
11935
942
  case 33:
11936
    // t2BFic, t2CSEL, t2CSINC, t2CSINV, t2CSNEG
11937
942
    printMandatoryPredicateOperand(MI, 3, O);
11938
942
    return;
11939
0
    break;
11940
7.72k
  case 34:
11941
    // t2LDRD_PRE, t2STRD_PRE
11942
7.72k
    printT2AddrModeImm8s4Operand_1(MI, 3, O);
11943
7.72k
    SStream_concat1(O, '!');
11944
7.72k
    return;
11945
0
    break;
11946
1.25k
  case 35:
11947
    // t2LDRDi8, t2STRDi8
11948
1.25k
    printT2AddrModeImm8s4Operand_0(MI, 2, O);
11949
1.25k
    return;
11950
0
    break;
11951
412
  case 36:
11952
    // t2STREX
11953
412
    printT2AddrModeImm0_1020s4Operand(MI, 2, O);
11954
412
    return;
11955
0
    break;
11956
13.2k
  case 37:
11957
    // tADDrSPi
11958
13.2k
    printThumbS4ImmOperand(MI, 2, O);
11959
13.2k
    return;
11960
0
    break;
11961
186k
  }
11962
11963
11964
  // Fragment 7 encoded into 5 bits for 17 unique commands.
11965
97.3k
  switch ((Bits >> 57) & 31) {
11966
0
  default: CS_ASSERT_RET(0 && "Invalid command number.");
11967
43.4k
  case 0:
11968
    // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm...
11969
43.4k
    return;
11970
0
    break;
11971
29.8k
  case 1:
11972
    // CDE_CX3A, CDE_VCX3A_vec, CDE_VCX3_vec, LDRD_POST, MLA, MLS, MVE_VCADDf...
11973
29.8k
    SStream_concat0(O, ", ");
11974
29.8k
    break;
11975
0
  case 2:
11976
    // CDE_CX3DA
11977
0
    printOperand(MI, 5, O);
11978
0
    return;
11979
0
    break;
11980
4.09k
  case 3:
11981
    // MCR, t2MCR, t2MCR2
11982
4.09k
    printCImmediate(MI, 3, O);
11983
4.09k
    SStream_concat0(O, ", ");
11984
4.09k
    printCImmediate(MI, 4, O);
11985
4.09k
    SStream_concat0(O, ", ");
11986
4.09k
    printOperand(MI, 5, O);
11987
4.09k
    return;
11988
0
    break;
11989
958
  case 4:
11990
    // MCRR, t2MCRR, t2MCRR2
11991
958
    printOperand(MI, 3, O);
11992
958
    SStream_concat0(O, ", ");
11993
958
    printCImmediate(MI, 4, O);
11994
958
    return;
11995
0
    break;
11996
1.24k
  case 5:
11997
    // MVE_VMOV_rr_q, VMULLslsv2i32, VMULLslsv4i16, VMULLsluv2i32, VMULLsluv4...
11998
1.24k
    printVectorIndex(MI, 3, O);
11999
1.24k
    break;
12000
299
  case 6:
12001
    // PKHBT, t2PKHBT
12002
299
    printPKHLSLShiftImm(MI, 3, O);
12003
299
    return;
12004
0
    break;
12005
324
  case 7:
12006
    // PKHTB, t2PKHTB
12007
324
    printPKHASRShiftImm(MI, 3, O);
12008
324
    return;
12009
0
    break;
12010
340
  case 8:
12011
    // SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, UXTAH, t2SXTAB, t2SXTAB16, t2SX...
12012
340
    printRotImmOperand(MI, 3, O);
12013
340
    return;
12014
0
    break;
12015
1.12k
  case 9:
12016
    // USAT, t2USAT
12017
1.12k
    printShiftImmOperand(MI, 3, O);
12018
1.12k
    return;
12019
0
    break;
12020
1.37k
  case 10:
12021
    // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U...
12022
1.37k
    SStream_concat0(O, "]}, ");
12023
1.37k
    printAddrMode6Operand(MI, 3, O);
12024
1.37k
    printAddrMode6OffsetOperand(MI, 5, O);
12025
1.37k
    return;
12026
0
    break;
12027
724
  case 11:
12028
    // VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16, VLD3LNq32
12029
724
    SStream_concat0(O, "], ");
12030
724
    printOperand(MI, 2, O);
12031
724
    SStream_concat1(O, '[');
12032
724
    printNoHashImmediate(MI, 8, O);
12033
724
    SStream_concat0(O, "]}, ");
12034
724
    printAddrMode6Operand(MI, 3, O);
12035
724
    return;
12036
0
    break;
12037
4.29k
  case 12:
12038
    // VLD3d16, VLD3d16_UPD, VLD3d32, VLD3d32_UPD, VLD3d8, VLD3d8_UPD, VLD3q1...
12039
4.29k
    SStream_concat0(O, "}, ");
12040
4.29k
    break;
12041
6.47k
  case 13:
12042
    // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32, VST2LNd16, VST2L...
12043
6.47k
    SStream_concat1(O, '[');
12044
6.47k
    break;
12045
840
  case 14:
12046
    // VMLALslsv2i32, VMLALslsv4i16, VMLALsluv2i32, VMLALsluv4i16, VMLAslfd, ...
12047
840
    printVectorIndex(MI, 4, O);
12048
840
    return;
12049
0
    break;
12050
918
  case 15:
12051
    // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD
12052
918
    printAddrMode6OffsetOperand(MI, 3, O);
12053
918
    return;
12054
0
    break;
12055
1.03k
  case 16:
12056
    // t2LDRD_POST, t2STRD_POST
12057
1.03k
    printT2AddrModeImm8s4OffsetOperand(MI, 4, O);
12058
1.03k
    return;
12059
0
    break;
12060
97.3k
  }
12061
12062
41.8k
  switch (MCInst_getOpcode(MI)) {
12063
0
  default: CS_ASSERT_RET(0 && "Unexpected opcode.");
12064
0
  case ARM_CDE_CX3A:
12065
0
  case ARM_CDE_VCX3A_vec:
12066
0
  case ARM_CDE_VCX3_vec:
12067
697
  case ARM_LDRD_POST:
12068
1.72k
  case ARM_MLA:
12069
1.97k
  case ARM_MLS:
12070
2.04k
  case ARM_MVE_VCADDf16:
12071
2.49k
  case ARM_MVE_VCADDf32:
12072
2.57k
  case ARM_MVE_VCADDi16:
12073
2.83k
  case ARM_MVE_VCADDi32:
12074
2.96k
  case ARM_MVE_VCADDi8:
12075
3.06k
  case ARM_MVE_VCMLAf16:
12076
3.46k
  case ARM_MVE_VCMLAf32:
12077
3.73k
  case ARM_MVE_VCMULf16:
12078
3.98k
  case ARM_MVE_VCMULf32:
12079
4.18k
  case ARM_MVE_VDWDUPu16:
12080
4.64k
  case ARM_MVE_VDWDUPu32:
12081
4.68k
  case ARM_MVE_VDWDUPu8:
12082
4.91k
  case ARM_MVE_VHCADDs16:
12083
5.00k
  case ARM_MVE_VHCADDs32:
12084
5.13k
  case ARM_MVE_VHCADDs8:
12085
5.44k
  case ARM_MVE_VIWDUPu16:
12086
5.52k
  case ARM_MVE_VIWDUPu32:
12087
5.60k
  case ARM_MVE_VIWDUPu8:
12088
5.60k
  case ARM_MVE_VMLALDAVas16:
12089
5.60k
  case ARM_MVE_VMLALDAVas32:
12090
5.60k
  case ARM_MVE_VMLALDAVau16:
12091
5.60k
  case ARM_MVE_VMLALDAVau32:
12092
5.84k
  case ARM_MVE_VMLALDAVaxs16:
12093
6.04k
  case ARM_MVE_VMLALDAVaxs32:
12094
6.04k
  case ARM_MVE_VMLALDAVs16:
12095
6.04k
  case ARM_MVE_VMLALDAVs32:
12096
6.04k
  case ARM_MVE_VMLALDAVu16:
12097
6.04k
  case ARM_MVE_VMLALDAVu32:
12098
6.26k
  case ARM_MVE_VMLALDAVxs16:
12099
6.37k
  case ARM_MVE_VMLALDAVxs32:
12100
7.15k
  case ARM_MVE_VMLSLDAVas16:
12101
8.03k
  case ARM_MVE_VMLSLDAVas32:
12102
8.16k
  case ARM_MVE_VMLSLDAVaxs16:
12103
8.51k
  case ARM_MVE_VMLSLDAVaxs32:
12104
8.65k
  case ARM_MVE_VMLSLDAVs16:
12105
8.93k
  case ARM_MVE_VMLSLDAVs32:
12106
9.32k
  case ARM_MVE_VMLSLDAVxs16:
12107
9.43k
  case ARM_MVE_VMLSLDAVxs32:
12108
9.43k
  case ARM_MVE_VRMLALDAVHas32:
12109
9.43k
  case ARM_MVE_VRMLALDAVHau32:
12110
9.71k
  case ARM_MVE_VRMLALDAVHaxs32:
12111
9.71k
  case ARM_MVE_VRMLALDAVHs32:
12112
9.71k
  case ARM_MVE_VRMLALDAVHu32:
12113
9.79k
  case ARM_MVE_VRMLALDAVHxs32:
12114
10.0k
  case ARM_MVE_VRMLSLDAVHas32:
12115
10.1k
  case ARM_MVE_VRMLSLDAVHaxs32:
12116
10.1k
  case ARM_MVE_VRMLSLDAVHs32:
12117
10.2k
  case ARM_MVE_VRMLSLDAVHxs32:
12118
10.8k
  case ARM_SBFX:
12119
10.9k
  case ARM_SMLABB:
12120
11.2k
  case ARM_SMLABT:
12121
11.4k
  case ARM_SMLAD:
12122
11.4k
  case ARM_SMLADX:
12123
11.5k
  case ARM_SMLALBB:
12124
11.7k
  case ARM_SMLALBT:
12125
11.8k
  case ARM_SMLALD:
12126
11.8k
  case ARM_SMLALDX:
12127
12.0k
  case ARM_SMLALTB:
12128
12.8k
  case ARM_SMLALTT:
12129
13.3k
  case ARM_SMLATB:
12130
13.5k
  case ARM_SMLATT:
12131
13.6k
  case ARM_SMLAWB:
12132
13.8k
  case ARM_SMLAWT:
12133
14.3k
  case ARM_SMLSD:
12134
14.4k
  case ARM_SMLSDX:
12135
14.5k
  case ARM_SMLSLD:
12136
14.9k
  case ARM_SMLSLDX:
12137
15.0k
  case ARM_SMMLA:
12138
15.1k
  case ARM_SMMLAR:
12139
15.2k
  case ARM_SMMLS:
12140
15.3k
  case ARM_SMMLSR:
12141
15.4k
  case ARM_SMULL:
12142
16.7k
  case ARM_STRD_POST:
12143
16.8k
  case ARM_UBFX:
12144
16.9k
  case ARM_UMAAL:
12145
17.3k
  case ARM_UMULL:
12146
17.3k
  case ARM_USADA8:
12147
17.4k
  case ARM_VEXTd16:
12148
17.6k
  case ARM_VEXTd32:
12149
17.8k
  case ARM_VEXTd8:
12150
17.8k
  case ARM_VEXTq16:
12151
17.8k
  case ARM_VEXTq32:
12152
18.0k
  case ARM_VEXTq64:
12153
18.0k
  case ARM_VEXTq8:
12154
18.5k
  case ARM_VLD3d16:
12155
18.6k
  case ARM_VLD3d32:
12156
18.7k
  case ARM_VLD3d8:
12157
18.9k
  case ARM_VLD3q16:
12158
19.0k
  case ARM_VLD3q32:
12159
19.1k
  case ARM_VLD3q8:
12160
19.4k
  case ARM_VMOVRRS:
12161
20.7k
  case ARM_VMOVSRR:
12162
21.2k
  case ARM_VST3d16:
12163
21.2k
  case ARM_VST3d32:
12164
21.4k
  case ARM_VST3d8:
12165
21.7k
  case ARM_VST3q16:
12166
21.9k
  case ARM_VST3q32:
12167
22.1k
  case ARM_VST3q8:
12168
22.3k
  case ARM_t2MLA:
12169
22.5k
  case ARM_t2MLS:
12170
22.8k
  case ARM_t2SBFX:
12171
23.0k
  case ARM_t2SMLABB:
12172
23.7k
  case ARM_t2SMLABT:
12173
24.2k
  case ARM_t2SMLAD:
12174
24.6k
  case ARM_t2SMLADX:
12175
24.7k
  case ARM_t2SMLAL:
12176
24.8k
  case ARM_t2SMLALBB:
12177
24.9k
  case ARM_t2SMLALBT:
12178
24.9k
  case ARM_t2SMLALD:
12179
25.0k
  case ARM_t2SMLALDX:
12180
25.1k
  case ARM_t2SMLALTB:
12181
25.2k
  case ARM_t2SMLALTT:
12182
25.2k
  case ARM_t2SMLATB:
12183
25.3k
  case ARM_t2SMLATT:
12184
25.3k
  case ARM_t2SMLAWB:
12185
25.4k
  case ARM_t2SMLAWT:
12186
25.8k
  case ARM_t2SMLSD:
12187
26.0k
  case ARM_t2SMLSDX:
12188
26.1k
  case ARM_t2SMLSLD:
12189
26.2k
  case ARM_t2SMLSLDX:
12190
26.3k
  case ARM_t2SMMLA:
12191
26.7k
  case ARM_t2SMMLAR:
12192
27.0k
  case ARM_t2SMMLS:
12193
27.1k
  case ARM_t2SMMLSR:
12194
27.3k
  case ARM_t2SMULL:
12195
27.4k
  case ARM_t2STLEXD:
12196
27.5k
  case ARM_t2STREXD:
12197
27.9k
  case ARM_t2UBFX:
12198
28.0k
  case ARM_t2UMAAL:
12199
28.2k
  case ARM_t2UMLAL:
12200
28.3k
  case ARM_t2UMULL:
12201
28.3k
  case ARM_t2USADA8:
12202
28.3k
    switch (MCInst_getOpcode(MI)) {
12203
0
    default: CS_ASSERT_RET(0 && "Unexpected opcode.");
12204
0
    case ARM_CDE_CX3A:
12205
0
    case ARM_CDE_VCX3A_vec:
12206
0
    case ARM_MVE_VMLALDAVas16:
12207
0
    case ARM_MVE_VMLALDAVas32:
12208
0
    case ARM_MVE_VMLALDAVau16:
12209
0
    case ARM_MVE_VMLALDAVau32:
12210
236
    case ARM_MVE_VMLALDAVaxs16:
12211
442
    case ARM_MVE_VMLALDAVaxs32:
12212
1.22k
    case ARM_MVE_VMLSLDAVas16:
12213
2.10k
    case ARM_MVE_VMLSLDAVas32:
12214
2.23k
    case ARM_MVE_VMLSLDAVaxs16:
12215
2.58k
    case ARM_MVE_VMLSLDAVaxs32:
12216
2.58k
    case ARM_MVE_VRMLALDAVHas32:
12217
2.58k
    case ARM_MVE_VRMLALDAVHau32:
12218
2.86k
    case ARM_MVE_VRMLALDAVHaxs32:
12219
3.08k
    case ARM_MVE_VRMLSLDAVHas32:
12220
3.19k
    case ARM_MVE_VRMLSLDAVHaxs32:
12221
3.19k
      printOperand(MI, 5, O);
12222
3.19k
      break;
12223
0
    case ARM_CDE_VCX3_vec:
12224
209
    case ARM_MVE_VDWDUPu16:
12225
661
    case ARM_MVE_VDWDUPu32:
12226
709
    case ARM_MVE_VDWDUPu8:
12227
1.02k
    case ARM_MVE_VIWDUPu16:
12228
1.10k
    case ARM_MVE_VIWDUPu32:
12229
1.18k
    case ARM_MVE_VIWDUPu8:
12230
1.18k
      printOperand(MI, 4, O);
12231
1.18k
      break;
12232
697
    case ARM_LDRD_POST:
12233
2.03k
    case ARM_STRD_POST:
12234
2.03k
      printAddrMode3OffsetOperand(MI, 4, O);
12235
2.03k
      break;
12236
1.03k
    case ARM_MLA:
12237
1.27k
    case ARM_MLS:
12238
1.27k
    case ARM_MVE_VMLALDAVs16:
12239
1.27k
    case ARM_MVE_VMLALDAVs32:
12240
1.27k
    case ARM_MVE_VMLALDAVu16:
12241
1.27k
    case ARM_MVE_VMLALDAVu32:
12242
1.49k
    case ARM_MVE_VMLALDAVxs16:
12243
1.60k
    case ARM_MVE_VMLALDAVxs32:
12244
1.74k
    case ARM_MVE_VMLSLDAVs16:
12245
2.02k
    case ARM_MVE_VMLSLDAVs32:
12246
2.41k
    case ARM_MVE_VMLSLDAVxs16:
12247
2.51k
    case ARM_MVE_VMLSLDAVxs32:
12248
2.51k
    case ARM_MVE_VRMLALDAVHs32:
12249
2.51k
    case ARM_MVE_VRMLALDAVHu32:
12250
2.59k
    case ARM_MVE_VRMLALDAVHxs32:
12251
2.66k
    case ARM_MVE_VRMLSLDAVHs32:
12252
2.75k
    case ARM_MVE_VRMLSLDAVHxs32:
12253
2.88k
    case ARM_SMLABB:
12254
3.19k
    case ARM_SMLABT:
12255
3.32k
    case ARM_SMLAD:
12256
3.39k
    case ARM_SMLADX:
12257
3.47k
    case ARM_SMLALBB:
12258
3.65k
    case ARM_SMLALBT:
12259
3.72k
    case ARM_SMLALD:
12260
3.80k
    case ARM_SMLALDX:
12261
3.99k
    case ARM_SMLALTB:
12262
4.73k
    case ARM_SMLALTT:
12263
5.24k
    case ARM_SMLATB:
12264
5.42k
    case ARM_SMLATT:
12265
5.60k
    case ARM_SMLAWB:
12266
5.72k
    case ARM_SMLAWT:
12267
6.24k
    case ARM_SMLSD:
12268
6.32k
    case ARM_SMLSDX:
12269
6.47k
    case ARM_SMLSLD:
12270
6.89k
    case ARM_SMLSLDX:
12271
6.98k
    case ARM_SMMLA:
12272
7.11k
    case ARM_SMMLAR:
12273
7.15k
    case ARM_SMMLS:
12274
7.23k
    case ARM_SMMLSR:
12275
7.32k
    case ARM_SMULL:
12276
7.42k
    case ARM_UMAAL:
12277
7.88k
    case ARM_UMULL:
12278
7.90k
    case ARM_USADA8:
12279
7.97k
    case ARM_VEXTd16:
12280
8.12k
    case ARM_VEXTd32:
12281
8.30k
    case ARM_VEXTd8:
12282
8.34k
    case ARM_VEXTq16:
12283
8.38k
    case ARM_VEXTq32:
12284
8.51k
    case ARM_VEXTq64:
12285
8.60k
    case ARM_VEXTq8:
12286
8.90k
    case ARM_VMOVRRS:
12287
10.1k
    case ARM_VMOVSRR:
12288
10.3k
    case ARM_t2MLA:
12289
10.5k
    case ARM_t2MLS:
12290
10.7k
    case ARM_t2SMLABB:
12291
11.4k
    case ARM_t2SMLABT:
12292
11.9k
    case ARM_t2SMLAD:
12293
12.3k
    case ARM_t2SMLADX:
12294
12.4k
    case ARM_t2SMLAL:
12295
12.5k
    case ARM_t2SMLALBB:
12296
12.6k
    case ARM_t2SMLALBT:
12297
12.6k
    case ARM_t2SMLALD:
12298
12.7k
    case ARM_t2SMLALDX:
12299
12.8k
    case ARM_t2SMLALTB:
12300
12.9k
    case ARM_t2SMLALTT:
12301
12.9k
    case ARM_t2SMLATB:
12302
13.0k
    case ARM_t2SMLATT:
12303
13.0k
    case ARM_t2SMLAWB:
12304
13.1k
    case ARM_t2SMLAWT:
12305
13.5k
    case ARM_t2SMLSD:
12306
13.7k
    case ARM_t2SMLSDX:
12307
13.8k
    case ARM_t2SMLSLD:
12308
13.9k
    case ARM_t2SMLSLDX:
12309
14.0k
    case ARM_t2SMMLA:
12310
14.4k
    case ARM_t2SMMLAR:
12311
14.7k
    case ARM_t2SMMLS:
12312
14.8k
    case ARM_t2SMMLSR:
12313
15.0k
    case ARM_t2SMULL:
12314
15.1k
    case ARM_t2UMAAL:
12315
15.3k
    case ARM_t2UMLAL:
12316
15.4k
    case ARM_t2UMULL:
12317
15.4k
    case ARM_t2USADA8:
12318
15.4k
      printOperand(MI, 3, O);
12319
15.4k
      break;
12320
68
    case ARM_MVE_VCADDf16:
12321
519
    case ARM_MVE_VCADDf32:
12322
605
    case ARM_MVE_VCADDi16:
12323
863
    case ARM_MVE_VCADDi32:
12324
990
    case ARM_MVE_VCADDi8:
12325
1.21k
    case ARM_MVE_VHCADDs16:
12326
1.30k
    case ARM_MVE_VHCADDs32:
12327
1.43k
    case ARM_MVE_VHCADDs8:
12328
1.43k
      printComplexRotationOp_180_90(MI, 3, O);
12329
1.43k
      break;
12330
106
    case ARM_MVE_VCMLAf16:
12331
501
    case ARM_MVE_VCMLAf32:
12332
501
      printComplexRotationOp_90_0(MI, 4, O);
12333
501
      break;
12334
276
    case ARM_MVE_VCMULf16:
12335
517
    case ARM_MVE_VCMULf32:
12336
517
      printComplexRotationOp_90_0(MI, 3, O);
12337
517
      break;
12338
565
    case ARM_SBFX:
12339
639
    case ARM_UBFX:
12340
978
    case ARM_t2SBFX:
12341
1.39k
    case ARM_t2UBFX:
12342
1.39k
      printImmPlusOneOperand(MI, 3, O);
12343
1.39k
      break;
12344
436
    case ARM_VLD3d16:
12345
532
    case ARM_VLD3d32:
12346
645
    case ARM_VLD3d8:
12347
891
    case ARM_VLD3q16:
12348
997
    case ARM_VLD3q32:
12349
1.04k
    case ARM_VLD3q8:
12350
1.04k
      printAddrMode6Operand(MI, 3, O);
12351
1.04k
      break;
12352
477
    case ARM_VST3d16:
12353
549
    case ARM_VST3d32:
12354
696
    case ARM_VST3d8:
12355
994
    case ARM_VST3q16:
12356
1.20k
    case ARM_VST3q32:
12357
1.41k
    case ARM_VST3q8:
12358
1.41k
      printAddrMode6Operand(MI, 0, O);
12359
1.41k
      break;
12360
121
    case ARM_t2STLEXD:
12361
188
    case ARM_t2STREXD:
12362
188
      printAddrMode7Operand(MI, 3, O);
12363
188
      break;
12364
28.3k
    }
12365
28.3k
    return;
12366
28.3k
    break;
12367
28.3k
  case ARM_MVE_VMOV_rr_q:
12368
0
    SStream_concat0(O, ", ");
12369
0
    printOperand(MI, 2, O);
12370
0
    printVectorIndex(MI, 4, O);
12371
0
    return;
12372
0
    break;
12373
68
  case ARM_VLD3d16_UPD:
12374
687
  case ARM_VLD3d32_UPD:
12375
1.06k
  case ARM_VLD3d8_UPD:
12376
1.21k
  case ARM_VLD3q16_UPD:
12377
1.44k
  case ARM_VLD3q32_UPD:
12378
1.83k
  case ARM_VLD3q8_UPD:
12379
1.83k
    printAddrMode6Operand(MI, 4, O);
12380
1.83k
    printAddrMode6OffsetOperand(MI, 6, O);
12381
1.83k
    return;
12382
0
    break;
12383
112
  case ARM_VLD4LNd16:
12384
441
  case ARM_VLD4LNd32:
12385
577
  case ARM_VLD4LNd8:
12386
860
  case ARM_VLD4LNq16:
12387
1.24k
  case ARM_VLD4LNq32:
12388
1.24k
    printNoHashImmediate(MI, 10, O);
12389
1.24k
    SStream_concat0(O, "]}, ");
12390
1.24k
    printAddrMode6Operand(MI, 4, O);
12391
1.24k
    return;
12392
0
    break;
12393
87
  case ARM_VLD4d16:
12394
185
  case ARM_VLD4d32:
12395
274
  case ARM_VLD4d8:
12396
855
  case ARM_VLD4q16:
12397
897
  case ARM_VLD4q32:
12398
1.22k
  case ARM_VLD4q8:
12399
1.22k
    printOperand(MI, 3, O);
12400
1.22k
    SStream_concat0(O, "}, ");
12401
1.22k
    printAddrMode6Operand(MI, 4, O);
12402
1.22k
    return;
12403
0
    break;
12404
132
  case ARM_VLD4d16_UPD:
12405
585
  case ARM_VLD4d32_UPD:
12406
1.04k
  case ARM_VLD4d8_UPD:
12407
1.68k
  case ARM_VLD4q16_UPD:
12408
1.88k
  case ARM_VLD4q32_UPD:
12409
2.05k
  case ARM_VLD4q8_UPD:
12410
2.05k
    printOperand(MI, 3, O);
12411
2.05k
    SStream_concat0(O, "}, ");
12412
2.05k
    printAddrMode6Operand(MI, 5, O);
12413
2.05k
    printAddrMode6OffsetOperand(MI, 7, O);
12414
2.05k
    return;
12415
0
    break;
12416
211
  case ARM_VMULLslsv2i32:
12417
301
  case ARM_VMULLslsv4i16:
12418
318
  case ARM_VMULLsluv2i32:
12419
318
  case ARM_VMULLsluv4i16:
12420
321
  case ARM_VMULslfd:
12421
334
  case ARM_VMULslfq:
12422
363
  case ARM_VMULslhd:
12423
363
  case ARM_VMULslhq:
12424
678
  case ARM_VMULslv2i32:
12425
690
  case ARM_VMULslv4i16:
12426
691
  case ARM_VMULslv4i32:
12427
692
  case ARM_VMULslv8i16:
12428
706
  case ARM_VQDMULHslv2i32:
12429
958
  case ARM_VQDMULHslv4i16:
12430
961
  case ARM_VQDMULHslv4i32:
12431
967
  case ARM_VQDMULHslv8i16:
12432
978
  case ARM_VQDMULLslv2i32:
12433
981
  case ARM_VQDMULLslv4i16:
12434
995
  case ARM_VQRDMULHslv2i32:
12435
1.00k
  case ARM_VQRDMULHslv4i16:
12436
1.18k
  case ARM_VQRDMULHslv4i32:
12437
1.24k
  case ARM_VQRDMULHslv8i16:
12438
1.24k
    return;
12439
0
    break;
12440
80
  case ARM_VST2LNd16:
12441
281
  case ARM_VST2LNd32:
12442
620
  case ARM_VST2LNd8:
12443
1.02k
  case ARM_VST2LNq16:
12444
1.10k
  case ARM_VST2LNq32:
12445
1.10k
    printNoHashImmediate(MI, 4, O);
12446
1.10k
    SStream_concat0(O, "]}, ");
12447
1.10k
    printAddrMode6Operand(MI, 0, O);
12448
1.10k
    return;
12449
0
    break;
12450
182
  case ARM_VST2LNd16_UPD:
12451
704
  case ARM_VST2LNd32_UPD:
12452
1.26k
  case ARM_VST2LNd8_UPD:
12453
1.53k
  case ARM_VST2LNq16_UPD:
12454
1.79k
  case ARM_VST2LNq32_UPD:
12455
1.79k
    printNoHashImmediate(MI, 6, O);
12456
1.79k
    SStream_concat0(O, "]}, ");
12457
1.79k
    printAddrMode6Operand(MI, 1, O);
12458
1.79k
    printAddrMode6OffsetOperand(MI, 3, O);
12459
1.79k
    return;
12460
0
    break;
12461
335
  case ARM_VST3LNd16:
12462
433
  case ARM_VST3LNd32:
12463
513
  case ARM_VST3LNd8:
12464
623
  case ARM_VST3LNq16:
12465
689
  case ARM_VST3LNq32:
12466
689
    printNoHashImmediate(MI, 5, O);
12467
689
    SStream_concat0(O, "], ");
12468
689
    printOperand(MI, 4, O);
12469
689
    SStream_concat1(O, '[');
12470
689
    printNoHashImmediate(MI, 5, O);
12471
689
    SStream_concat0(O, "]}, ");
12472
689
    printAddrMode6Operand(MI, 0, O);
12473
689
    return;
12474
0
    break;
12475
240
  case ARM_VST4LNd16:
12476
822
  case ARM_VST4LNd32:
12477
1.07k
  case ARM_VST4LNd8:
12478
1.42k
  case ARM_VST4LNq16:
12479
1.64k
  case ARM_VST4LNq32:
12480
1.64k
    printNoHashImmediate(MI, 6, O);
12481
1.64k
    SStream_concat0(O, "], ");
12482
1.64k
    printOperand(MI, 4, O);
12483
1.64k
    SStream_concat1(O, '[');
12484
1.64k
    printNoHashImmediate(MI, 6, O);
12485
1.64k
    SStream_concat0(O, "], ");
12486
1.64k
    printOperand(MI, 5, O);
12487
1.64k
    SStream_concat1(O, '[');
12488
1.64k
    printNoHashImmediate(MI, 6, O);
12489
1.64k
    SStream_concat0(O, "]}, ");
12490
1.64k
    printAddrMode6Operand(MI, 0, O);
12491
1.64k
    return;
12492
0
    break;
12493
139
  case ARM_VST4d16:
12494
217
  case ARM_VST4d32:
12495
327
  case ARM_VST4d8:
12496
432
  case ARM_VST4q16:
12497
520
  case ARM_VST4q32:
12498
619
  case ARM_VST4q8:
12499
619
    printOperand(MI, 5, O);
12500
619
    SStream_concat0(O, "}, ");
12501
619
    printAddrMode6Operand(MI, 0, O);
12502
619
    return;
12503
0
    break;
12504
41.8k
  }
12505
41.8k
}
12506
12507
12508
/// getRegisterName - This method is automatically generated by tblgen
12509
/// from the register set description.  This returns the assembler name
12510
/// for the specified register.
12511
static const char *
12512
3.76M
getRegisterName(unsigned RegNo, unsigned AltIdx) {
12513
3.76M
#ifndef CAPSTONE_DIET
12514
3.76M
  CS_ASSERT_RET_VAL(RegNo && RegNo < 296 && "Invalid register number!", NULL);
12515
12516
3.76M
  static const char AsmStrsNoRegAltName[] = {
12517
3.76M
  /* 0 */ "D4_D6_D8_D10\0"
12518
3.76M
  /* 13 */ "D7_D8_D9_D10\0"
12519
3.76M
  /* 26 */ "Q7_Q8_Q9_Q10\0"
12520
3.76M
  /* 39 */ "d10\0"
12521
3.76M
  /* 43 */ "q10\0"
12522
3.76M
  /* 47 */ "r10\0"
12523
3.76M
  /* 51 */ "s10\0"
12524
3.76M
  /* 55 */ "D14_D16_D18_D20\0"
12525
3.76M
  /* 71 */ "D17_D18_D19_D20\0"
12526
3.76M
  /* 87 */ "d20\0"
12527
3.76M
  /* 91 */ "s20\0"
12528
3.76M
  /* 95 */ "D24_D26_D28_D30\0"
12529
3.76M
  /* 111 */ "D27_D28_D29_D30\0"
12530
3.76M
  /* 127 */ "d30\0"
12531
3.76M
  /* 131 */ "s30\0"
12532
3.76M
  /* 135 */ "d0\0"
12533
3.76M
  /* 138 */ "p0\0"
12534
3.76M
  /* 141 */ "q0\0"
12535
3.76M
  /* 144 */ "mvfr0\0"
12536
3.76M
  /* 150 */ "s0\0"
12537
3.76M
  /* 153 */ "D9_D10_D11\0"
12538
3.76M
  /* 164 */ "D5_D7_D9_D11\0"
12539
3.76M
  /* 177 */ "Q8_Q9_Q10_Q11\0"
12540
3.76M
  /* 191 */ "R10_R11\0"
12541
3.76M
  /* 199 */ "d11\0"
12542
3.76M
  /* 203 */ "q11\0"
12543
3.76M
  /* 207 */ "r11\0"
12544
3.76M
  /* 211 */ "s11\0"
12545
3.76M
  /* 215 */ "D19_D20_D21\0"
12546
3.76M
  /* 227 */ "D15_D17_D19_D21\0"
12547
3.76M
  /* 243 */ "d21\0"
12548
3.76M
  /* 247 */ "s21\0"
12549
3.76M
  /* 251 */ "D29_D30_D31\0"
12550
3.76M
  /* 263 */ "D25_D27_D29_D31\0"
12551
3.76M
  /* 279 */ "d31\0"
12552
3.76M
  /* 283 */ "s31\0"
12553
3.76M
  /* 287 */ "Q0_Q1\0"
12554
3.76M
  /* 293 */ "R0_R1\0"
12555
3.76M
  /* 299 */ "d1\0"
12556
3.76M
  /* 302 */ "q1\0"
12557
3.76M
  /* 305 */ "mvfr1\0"
12558
3.76M
  /* 311 */ "s1\0"
12559
3.76M
  /* 314 */ "D6_D8_D10_D12\0"
12560
3.76M
  /* 328 */ "D9_D10_D11_D12\0"
12561
3.76M
  /* 343 */ "Q9_Q10_Q11_Q12\0"
12562
3.76M
  /* 358 */ "d12\0"
12563
3.76M
  /* 362 */ "q12\0"
12564
3.76M
  /* 366 */ "r12\0"
12565
3.76M
  /* 370 */ "s12\0"
12566
3.76M
  /* 374 */ "D16_D18_D20_D22\0"
12567
3.76M
  /* 390 */ "D19_D20_D21_D22\0"
12568
3.76M
  /* 406 */ "d22\0"
12569
3.76M
  /* 410 */ "s22\0"
12570
3.76M
  /* 414 */ "D0_D2\0"
12571
3.76M
  /* 420 */ "D0_D1_D2\0"
12572
3.76M
  /* 429 */ "Q1_Q2\0"
12573
3.76M
  /* 435 */ "d2\0"
12574
3.76M
  /* 438 */ "q2\0"
12575
3.76M
  /* 441 */ "mvfr2\0"
12576
3.76M
  /* 447 */ "s2\0"
12577
3.76M
  /* 450 */ "fpinst2\0"
12578
3.76M
  /* 458 */ "D7_D9_D11_D13\0"
12579
3.76M
  /* 472 */ "D11_D12_D13\0"
12580
3.76M
  /* 484 */ "Q10_Q11_Q12_Q13\0"
12581
3.76M
  /* 500 */ "d13\0"
12582
3.76M
  /* 504 */ "q13\0"
12583
3.76M
  /* 508 */ "s13\0"
12584
3.76M
  /* 512 */ "D17_D19_D21_D23\0"
12585
3.76M
  /* 528 */ "D21_D22_D23\0"
12586
3.76M
  /* 540 */ "d23\0"
12587
3.76M
  /* 544 */ "s23\0"
12588
3.76M
  /* 548 */ "D1_D3\0"
12589
3.76M
  /* 554 */ "D1_D2_D3\0"
12590
3.76M
  /* 563 */ "Q0_Q1_Q2_Q3\0"
12591
3.76M
  /* 575 */ "R2_R3\0"
12592
3.76M
  /* 581 */ "d3\0"
12593
3.76M
  /* 584 */ "q3\0"
12594
3.76M
  /* 587 */ "r3\0"
12595
3.76M
  /* 590 */ "s3\0"
12596
3.76M
  /* 593 */ "D8_D10_D12_D14\0"
12597
3.76M
  /* 608 */ "D11_D12_D13_D14\0"
12598
3.76M
  /* 624 */ "Q11_Q12_Q13_Q14\0"
12599
3.76M
  /* 640 */ "d14\0"
12600
3.76M
  /* 644 */ "q14\0"
12601
3.76M
  /* 648 */ "s14\0"
12602
3.76M
  /* 652 */ "D18_D20_D22_D24\0"
12603
3.76M
  /* 668 */ "D21_D22_D23_D24\0"
12604
3.76M
  /* 684 */ "d24\0"
12605
3.76M
  /* 688 */ "s24\0"
12606
3.76M
  /* 692 */ "D0_D2_D4\0"
12607
3.76M
  /* 701 */ "D1_D2_D3_D4\0"
12608
3.76M
  /* 713 */ "Q1_Q2_Q3_Q4\0"
12609
3.76M
  /* 725 */ "d4\0"
12610
3.76M
  /* 728 */ "q4\0"
12611
3.76M
  /* 731 */ "r4\0"
12612
3.76M
  /* 734 */ "s4\0"
12613
3.76M
  /* 737 */ "D9_D11_D13_D15\0"
12614
3.76M
  /* 752 */ "D13_D14_D15\0"
12615
3.76M
  /* 764 */ "Q12_Q13_Q14_Q15\0"
12616
3.76M
  /* 780 */ "d15\0"
12617
3.76M
  /* 784 */ "q15\0"
12618
3.76M
  /* 788 */ "s15\0"
12619
3.76M
  /* 792 */ "D19_D21_D23_D25\0"
12620
3.76M
  /* 808 */ "D23_D24_D25\0"
12621
3.76M
  /* 820 */ "d25\0"
12622
3.76M
  /* 824 */ "s25\0"
12623
3.76M
  /* 828 */ "D1_D3_D5\0"
12624
3.76M
  /* 837 */ "D3_D4_D5\0"
12625
3.76M
  /* 846 */ "Q2_Q3_Q4_Q5\0"
12626
3.76M
  /* 858 */ "R4_R5\0"
12627
3.76M
  /* 864 */ "d5\0"
12628
3.76M
  /* 867 */ "q5\0"
12629
3.76M
  /* 870 */ "r5\0"
12630
3.76M
  /* 873 */ "s5\0"
12631
3.76M
  /* 876 */ "D10_D12_D14_D16\0"
12632
3.76M
  /* 892 */ "D13_D14_D15_D16\0"
12633
3.76M
  /* 908 */ "d16\0"
12634
3.76M
  /* 912 */ "s16\0"
12635
3.76M
  /* 916 */ "D20_D22_D24_D26\0"
12636
3.76M
  /* 932 */ "D23_D24_D25_D26\0"
12637
3.76M
  /* 948 */ "d26\0"
12638
3.76M
  /* 952 */ "s26\0"
12639
3.76M
  /* 956 */ "D0_D2_D4_D6\0"
12640
3.76M
  /* 968 */ "D3_D4_D5_D6\0"
12641
3.76M
  /* 980 */ "Q3_Q4_Q5_Q6\0"
12642
3.76M
  /* 992 */ "d6\0"
12643
3.76M
  /* 995 */ "q6\0"
12644
3.76M
  /* 998 */ "r6\0"
12645
3.76M
  /* 1001 */ "s6\0"
12646
3.76M
  /* 1004 */ "D11_D13_D15_D17\0"
12647
3.76M
  /* 1020 */ "D15_D16_D17\0"
12648
3.76M
  /* 1032 */ "d17\0"
12649
3.76M
  /* 1036 */ "s17\0"
12650
3.76M
  /* 1040 */ "D21_D23_D25_D27\0"
12651
3.76M
  /* 1056 */ "D25_D26_D27\0"
12652
3.76M
  /* 1068 */ "d27\0"
12653
3.76M
  /* 1072 */ "s27\0"
12654
3.76M
  /* 1076 */ "D1_D3_D5_D7\0"
12655
3.76M
  /* 1088 */ "D5_D6_D7\0"
12656
3.76M
  /* 1097 */ "Q4_Q5_Q6_Q7\0"
12657
3.76M
  /* 1109 */ "R6_R7\0"
12658
3.76M
  /* 1115 */ "d7\0"
12659
3.76M
  /* 1118 */ "q7\0"
12660
3.76M
  /* 1121 */ "r7\0"
12661
3.76M
  /* 1124 */ "s7\0"
12662
3.76M
  /* 1127 */ "D12_D14_D16_D18\0"
12663
3.76M
  /* 1143 */ "D15_D16_D17_D18\0"
12664
3.76M
  /* 1159 */ "d18\0"
12665
3.76M
  /* 1163 */ "s18\0"
12666
3.76M
  /* 1167 */ "D22_D24_D26_D28\0"
12667
3.76M
  /* 1183 */ "D25_D26_D27_D28\0"
12668
3.76M
  /* 1199 */ "d28\0"
12669
3.76M
  /* 1203 */ "s28\0"
12670
3.76M
  /* 1207 */ "D2_D4_D6_D8\0"
12671
3.76M
  /* 1219 */ "D5_D6_D7_D8\0"
12672
3.76M
  /* 1231 */ "Q5_Q6_Q7_Q8\0"
12673
3.76M
  /* 1243 */ "d8\0"
12674
3.76M
  /* 1246 */ "q8\0"
12675
3.76M
  /* 1249 */ "r8\0"
12676
3.76M
  /* 1252 */ "s8\0"
12677
3.76M
  /* 1255 */ "D13_D15_D17_D19\0"
12678
3.76M
  /* 1271 */ "D17_D18_D19\0"
12679
3.76M
  /* 1283 */ "d19\0"
12680
3.76M
  /* 1287 */ "s19\0"
12681
3.76M
  /* 1291 */ "D23_D25_D27_D29\0"
12682
3.76M
  /* 1307 */ "D27_D28_D29\0"
12683
3.76M
  /* 1319 */ "d29\0"
12684
3.76M
  /* 1323 */ "s29\0"
12685
3.76M
  /* 1327 */ "D3_D5_D7_D9\0"
12686
3.76M
  /* 1339 */ "D7_D8_D9\0"
12687
3.76M
  /* 1348 */ "Q6_Q7_Q8_Q9\0"
12688
3.76M
  /* 1360 */ "R8_R9\0"
12689
3.76M
  /* 1366 */ "d9\0"
12690
3.76M
  /* 1369 */ "q9\0"
12691
3.76M
  /* 1372 */ "r9\0"
12692
3.76M
  /* 1375 */ "s9\0"
12693
3.76M
  /* 1378 */ "R12_SP\0"
12694
3.76M
  /* 1385 */ "pc\0"
12695
3.76M
  /* 1388 */ "fpscr_nzcvqc\0"
12696
3.76M
  /* 1401 */ "fpexc\0"
12697
3.76M
  /* 1407 */ "fpsid\0"
12698
3.76M
  /* 1413 */ "ra_auth_code\0"
12699
3.76M
  /* 1426 */ "itstate\0"
12700
3.76M
  /* 1434 */ "sp\0"
12701
3.76M
  /* 1437 */ "fpscr\0"
12702
3.76M
  /* 1443 */ "lr\0"
12703
3.76M
  /* 1446 */ "vpr\0"
12704
3.76M
  /* 1450 */ "apsr\0"
12705
3.76M
  /* 1455 */ "cpsr\0"
12706
3.76M
  /* 1460 */ "spsr\0"
12707
3.76M
  /* 1465 */ "zr\0"
12708
3.76M
  /* 1468 */ "fpcxtns\0"
12709
3.76M
  /* 1476 */ "fpcxts\0"
12710
3.76M
  /* 1483 */ "fpinst\0"
12711
3.76M
  /* 1490 */ "fpscr_nzcv\0"
12712
3.76M
  /* 1501 */ "apsr_nzcv\0"
12713
3.76M
};
12714
3.76M
  static const uint16_t RegAsmOffsetNoRegAltName[] = {
12715
3.76M
    1450, 1501, 1455, 1468, 1476, 1401, 1483, 1437, 1490, 1388, 1407, 1426, 1443, 1385, 
12716
3.76M
    1413, 1434, 1460, 1446, 1465, 135, 299, 435, 581, 725, 864, 992, 1115, 1243, 
12717
3.76M
    1366, 39, 199, 358, 500, 640, 780, 908, 1032, 1159, 1283, 87, 243, 406, 
12718
3.76M
    540, 684, 820, 948, 1068, 1199, 1319, 127, 279, 450, 144, 305, 441, 138, 
12719
3.76M
    141, 302, 438, 584, 728, 867, 995, 1118, 1246, 1369, 43, 203, 362, 504, 
12720
3.76M
    644, 784, 147, 308, 444, 587, 731, 870, 998, 1121, 1249, 1372, 47, 207, 
12721
3.76M
    366, 150, 311, 447, 590, 734, 873, 1001, 1124, 1252, 1375, 51, 211, 370, 
12722
3.76M
    508, 648, 788, 912, 1036, 1163, 1287, 91, 247, 410, 544, 688, 824, 952, 
12723
3.76M
    1072, 1203, 1323, 131, 283, 414, 548, 695, 831, 962, 1082, 1213, 1333, 6, 
12724
3.76M
    170, 320, 464, 600, 744, 884, 1012, 1135, 1263, 63, 235, 382, 520, 660, 
12725
3.76M
    800, 924, 1048, 1175, 1299, 103, 271, 287, 429, 569, 719, 852, 986, 1103, 
12726
3.76M
    1237, 1354, 32, 183, 350, 492, 632, 772, 563, 713, 846, 980, 1097, 1231, 
12727
3.76M
    1348, 26, 177, 343, 484, 624, 764, 293, 575, 858, 1109, 1360, 191, 1378, 
12728
3.76M
    420, 554, 704, 837, 971, 1088, 1222, 1339, 16, 153, 331, 472, 612, 752, 
12729
3.76M
    896, 1020, 1147, 1271, 75, 215, 394, 528, 672, 808, 936, 1056, 1187, 1307, 
12730
3.76M
    115, 251, 692, 828, 959, 1079, 1210, 1330, 3, 167, 317, 461, 596, 740, 
12731
3.76M
    880, 1008, 1131, 1259, 59, 231, 378, 516, 656, 796, 920, 1044, 1171, 1295, 
12732
3.76M
    99, 267, 956, 1076, 1207, 1327, 0, 164, 314, 458, 593, 737, 876, 1004, 
12733
3.76M
    1127, 1255, 55, 227, 374, 512, 652, 792, 916, 1040, 1167, 1291, 95, 263, 
12734
3.76M
    423, 707, 974, 1225, 19, 335, 616, 900, 1151, 79, 398, 676, 940, 1191, 
12735
3.76M
    119, 701, 968, 1219, 13, 328, 608, 892, 1143, 71, 390, 668, 932, 1183, 
12736
3.76M
    111, 
12737
3.76M
  };
12738
12739
3.76M
  static const char AsmStrsRegNamesRaw[] = {
12740
3.76M
  /* 0 */ "r13\0"
12741
3.76M
  /* 4 */ "r14\0"
12742
3.76M
  /* 8 */ "r15\0"
12743
3.76M
};
12744
3.76M
  static const uint8_t RegAsmOffsetRegNamesRaw[] = {
12745
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 8, 
12746
3.76M
    3, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12747
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12748
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12749
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12750
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12751
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12752
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12753
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12754
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12755
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12756
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12757
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12758
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12759
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12760
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12761
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12762
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12763
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12764
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12765
3.76M
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
12766
3.76M
    3, 
12767
3.76M
  };
12768
12769
3.76M
  switch(AltIdx) {
12770
0
  default: CS_ASSERT_RET_VAL(0 && "Invalid register alt name index!", NULL);
12771
3.01M
  case ARM_NoRegAltName:
12772
3.01M
    CS_ASSERT_RET_VAL(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
12773
3.01M
           "Invalid alt name index for register!", NULL);
12774
3.01M
    return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
12775
744k
  case ARM_RegNamesRaw:
12776
744k
    if (!*(AsmStrsRegNamesRaw+RegAsmOffsetRegNamesRaw[RegNo-1]))
12777
675k
      return getRegisterName(RegNo, ARM_NoRegAltName);
12778
68.9k
    return AsmStrsRegNamesRaw+RegAsmOffsetRegNamesRaw[RegNo-1];
12779
3.76M
  }
12780
#else
12781
  return NULL;
12782
#endif // CAPSTONE_DIET
12783
3.76M
}
12784
#ifdef PRINT_ALIAS_INSTR
12785
#undef PRINT_ALIAS_INSTR
12786
12787
1.15M
static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) {
12788
1.15M
#ifndef CAPSTONE_DIET
12789
1.15M
  static const PatternsForOpcode OpToPatterns[] = {
12790
1.15M
    {ARM_DSB, 0, 3 },
12791
1.15M
    {ARM_HINT, 3, 9 },
12792
1.15M
    {ARM_MVE_VMLADAVas16, 12, 1 },
12793
1.15M
    {ARM_MVE_VMLADAVas32, 13, 1 },
12794
1.15M
    {ARM_MVE_VMLADAVas8, 14, 1 },
12795
1.15M
    {ARM_MVE_VMLADAVau16, 15, 1 },
12796
1.15M
    {ARM_MVE_VMLADAVau32, 16, 1 },
12797
1.15M
    {ARM_MVE_VMLADAVau8, 17, 1 },
12798
1.15M
    {ARM_MVE_VMLADAVs16, 18, 1 },
12799
1.15M
    {ARM_MVE_VMLADAVs32, 19, 1 },
12800
1.15M
    {ARM_MVE_VMLADAVs8, 20, 1 },
12801
1.15M
    {ARM_MVE_VMLADAVu16, 21, 1 },
12802
1.15M
    {ARM_MVE_VMLADAVu32, 22, 1 },
12803
1.15M
    {ARM_MVE_VMLADAVu8, 23, 1 },
12804
1.15M
    {ARM_MVE_VMLALDAVas16, 24, 1 },
12805
1.15M
    {ARM_MVE_VMLALDAVas32, 25, 1 },
12806
1.15M
    {ARM_MVE_VMLALDAVau16, 26, 1 },
12807
1.15M
    {ARM_MVE_VMLALDAVau32, 27, 1 },
12808
1.15M
    {ARM_MVE_VMLALDAVs16, 28, 1 },
12809
1.15M
    {ARM_MVE_VMLALDAVs32, 29, 1 },
12810
1.15M
    {ARM_MVE_VMLALDAVu16, 30, 1 },
12811
1.15M
    {ARM_MVE_VMLALDAVu32, 31, 1 },
12812
1.15M
    {ARM_MVE_VORR, 32, 1 },
12813
1.15M
    {ARM_MVE_VRMLALDAVHas32, 33, 1 },
12814
1.15M
    {ARM_MVE_VRMLALDAVHau32, 34, 1 },
12815
1.15M
    {ARM_MVE_VRMLALDAVHs32, 35, 1 },
12816
1.15M
    {ARM_MVE_VRMLALDAVHu32, 36, 1 },
12817
1.15M
    {ARM_t2CSINC, 37, 2 },
12818
1.15M
    {ARM_t2CSINV, 39, 2 },
12819
1.15M
    {ARM_t2CSNEG, 41, 1 },
12820
1.15M
    {ARM_t2DSB, 42, 3 },
12821
1.15M
    {ARM_t2HINT, 45, 13 },
12822
1.15M
    {ARM_t2SUBS_PC_LR, 58, 1 },
12823
1.15M
    {ARM_tHINT, 59, 6 },
12824
1.15M
  {0},  };
12825
12826
1.15M
  static const AliasPattern Patterns[] = {
12827
    // ARM_DSB - 0
12828
1.15M
    {0, 0, 1, 3 },
12829
1.15M
    {5, 3, 1, 3 },
12830
1.15M
    {11, 6, 1, 3 },
12831
    // ARM_HINT - 3
12832
1.15M
    {15, 9, 3, 3 },
12833
1.15M
    {23, 12, 3, 3 },
12834
1.15M
    {33, 15, 3, 3 },
12835
1.15M
    {41, 18, 3, 3 },
12836
1.15M
    {49, 21, 3, 3 },
12837
1.15M
    {57, 24, 3, 3 },
12838
1.15M
    {66, 27, 3, 3 },
12839
1.15M
    {74, 30, 3, 3 },
12840
1.15M
    {83, 33, 3, 4 },
12841
    // ARM_MVE_VMLADAVas16 - 12
12842
1.15M
    {94, 37, 7, 6 },
12843
    // ARM_MVE_VMLADAVas32 - 13
12844
1.15M
    {120, 43, 7, 6 },
12845
    // ARM_MVE_VMLADAVas8 - 14
12846
1.15M
    {146, 49, 7, 6 },
12847
    // ARM_MVE_VMLADAVau16 - 15
12848
1.15M
    {171, 55, 7, 6 },
12849
    // ARM_MVE_VMLADAVau32 - 16
12850
1.15M
    {197, 61, 7, 6 },
12851
    // ARM_MVE_VMLADAVau8 - 17
12852
1.15M
    {223, 67, 7, 6 },
12853
    // ARM_MVE_VMLADAVs16 - 18
12854
1.15M
    {248, 73, 6, 5 },
12855
    // ARM_MVE_VMLADAVs32 - 19
12856
1.15M
    {273, 78, 6, 5 },
12857
    // ARM_MVE_VMLADAVs8 - 20
12858
1.15M
    {298, 83, 6, 5 },
12859
    // ARM_MVE_VMLADAVu16 - 21
12860
1.15M
    {322, 88, 6, 5 },
12861
    // ARM_MVE_VMLADAVu32 - 22
12862
1.15M
    {347, 93, 6, 5 },
12863
    // ARM_MVE_VMLADAVu8 - 23
12864
1.15M
    {372, 98, 6, 5 },
12865
    // ARM_MVE_VMLALDAVas16 - 24
12866
1.15M
    {396, 103, 9, 8 },
12867
    // ARM_MVE_VMLALDAVas32 - 25
12868
1.15M
    {427, 111, 9, 8 },
12869
    // ARM_MVE_VMLALDAVau16 - 26
12870
1.15M
    {458, 119, 9, 8 },
12871
    // ARM_MVE_VMLALDAVau32 - 27
12872
1.15M
    {489, 127, 9, 8 },
12873
    // ARM_MVE_VMLALDAVs16 - 28
12874
1.15M
    {520, 135, 7, 6 },
12875
    // ARM_MVE_VMLALDAVs32 - 29
12876
1.15M
    {550, 141, 7, 6 },
12877
    // ARM_MVE_VMLALDAVu16 - 30
12878
1.15M
    {580, 147, 7, 6 },
12879
    // ARM_MVE_VMLALDAVu32 - 31
12880
1.15M
    {610, 153, 7, 6 },
12881
    // ARM_MVE_VORR - 32
12882
1.15M
    {640, 159, 7, 5 },
12883
    // ARM_MVE_VRMLALDAVHas32 - 33
12884
1.15M
    {656, 164, 9, 8 },
12885
    // ARM_MVE_VRMLALDAVHau32 - 34
12886
1.15M
    {689, 172, 9, 8 },
12887
    // ARM_MVE_VRMLALDAVHs32 - 35
12888
1.15M
    {722, 180, 7, 6 },
12889
    // ARM_MVE_VRMLALDAVHu32 - 36
12890
1.15M
    {754, 186, 7, 6 },
12891
    // ARM_t2CSINC - 37
12892
1.15M
    {786, 192, 4, 4 },
12893
1.15M
    {800, 196, 4, 4 },
12894
    // ARM_t2CSINV - 39
12895
1.15M
    {818, 200, 4, 4 },
12896
1.15M
    {833, 204, 4, 4 },
12897
    // ARM_t2CSNEG - 41
12898
1.15M
    {851, 208, 4, 4 },
12899
    // ARM_t2DSB - 42
12900
1.15M
    {0, 212, 3, 6 },
12901
1.15M
    {5, 218, 3, 6 },
12902
1.15M
    {869, 224, 3, 2 },
12903
    // ARM_t2HINT - 45
12904
1.15M
    {877, 226, 3, 3 },
12905
1.15M
    {887, 229, 3, 3 },
12906
1.15M
    {899, 232, 3, 3 },
12907
1.15M
    {909, 235, 3, 3 },
12908
1.15M
    {919, 238, 3, 3 },
12909
1.15M
    {929, 241, 3, 4 },
12910
1.15M
    {940, 245, 3, 4 },
12911
1.15M
    {74, 249, 3, 3 },
12912
1.15M
    {950, 252, 3, 3 },
12913
1.15M
    {971, 255, 3, 3 },
12914
1.15M
    {979, 258, 3, 3 },
12915
1.15M
    {997, 261, 3, 3 },
12916
1.15M
    {83, 264, 3, 5 },
12917
    // ARM_t2SUBS_PC_LR - 58
12918
1.15M
    {1015, 269, 3, 4 },
12919
    // ARM_tHINT - 59
12920
1.15M
    {15, 273, 3, 3 },
12921
1.15M
    {23, 276, 3, 3 },
12922
1.15M
    {33, 279, 3, 3 },
12923
1.15M
    {41, 282, 3, 3 },
12924
1.15M
    {49, 285, 3, 3 },
12925
1.15M
    {57, 288, 3, 4 },
12926
1.15M
  {0},  };
12927
12928
1.15M
  static const AliasPatternCond Conds[] = {
12929
    // (DSB 0) - 0
12930
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)0},
12931
1.15M
    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
12932
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureDB},
12933
    // (DSB 4) - 3
12934
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)4},
12935
1.15M
    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
12936
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureDB},
12937
    // (DSB 12) - 6
12938
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)12},
12939
1.15M
    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
12940
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureDFB},
12941
    // (HINT 0, pred:$p) - 9
12942
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)0},
12943
1.15M
    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
12944
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV6KOps},
12945
    // (HINT 1, pred:$p) - 12
12946
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)1},
12947
1.15M
    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
12948
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV6KOps},
12949
    // (HINT 2, pred:$p) - 15
12950
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)2},
12951
1.15M
    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
12952
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV6KOps},
12953
    // (HINT 3, pred:$p) - 18
12954
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)3},
12955
1.15M
    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
12956
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV6KOps},
12957
    // (HINT 4, pred:$p) - 21
12958
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)4},
12959
1.15M
    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
12960
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV6KOps},
12961
    // (HINT 5, pred:$p) - 24
12962
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)5},
12963
1.15M
    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
12964
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV8Ops},
12965
    // (HINT 16, pred:$p) - 27
12966
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)16},
12967
1.15M
    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
12968
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureRAS},
12969
    // (HINT 20, pred:$p) - 30
12970
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)20},
12971
1.15M
    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
12972
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV6KOps},
12973
    // (HINT 22, pred:$p) - 33
12974
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)22},
12975
1.15M
    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
12976
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV8Ops},
12977
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureCLRBHB},
12978
    // (MVE_VMLADAVas16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 37
12979
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
12980
1.15M
    {AliasPatternCond_K_Ignore, 0},
12981
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
12982
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
12983
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
12984
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
12985
    // (MVE_VMLADAVas32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 43
12986
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
12987
1.15M
    {AliasPatternCond_K_Ignore, 0},
12988
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
12989
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
12990
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
12991
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
12992
    // (MVE_VMLADAVas8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 49
12993
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
12994
1.15M
    {AliasPatternCond_K_Ignore, 0},
12995
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
12996
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
12997
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
12998
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
12999
    // (MVE_VMLADAVau16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 55
13000
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13001
1.15M
    {AliasPatternCond_K_Ignore, 0},
13002
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13003
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13004
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13005
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13006
    // (MVE_VMLADAVau32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 61
13007
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13008
1.15M
    {AliasPatternCond_K_Ignore, 0},
13009
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13010
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13011
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13012
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13013
    // (MVE_VMLADAVau8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 67
13014
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13015
1.15M
    {AliasPatternCond_K_Ignore, 0},
13016
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13017
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13018
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13019
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13020
    // (MVE_VMLADAVs16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 73
13021
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13022
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13023
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13024
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13025
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13026
    // (MVE_VMLADAVs32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 78
13027
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13028
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13029
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13030
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13031
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13032
    // (MVE_VMLADAVs8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 83
13033
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13034
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13035
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13036
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13037
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13038
    // (MVE_VMLADAVu16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 88
13039
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13040
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13041
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13042
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13043
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13044
    // (MVE_VMLADAVu32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 93
13045
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13046
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13047
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13048
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13049
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13050
    // (MVE_VMLADAVu8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 98
13051
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13052
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13053
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13054
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13055
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13056
    // (MVE_VMLALDAVas16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 103
13057
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13058
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
13059
1.15M
    {AliasPatternCond_K_Ignore, 0},
13060
1.15M
    {AliasPatternCond_K_Ignore, 0},
13061
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13062
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13063
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13064
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13065
    // (MVE_VMLALDAVas32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 111
13066
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13067
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
13068
1.15M
    {AliasPatternCond_K_Ignore, 0},
13069
1.15M
    {AliasPatternCond_K_Ignore, 0},
13070
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13071
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13072
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13073
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13074
    // (MVE_VMLALDAVau16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 119
13075
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13076
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
13077
1.15M
    {AliasPatternCond_K_Ignore, 0},
13078
1.15M
    {AliasPatternCond_K_Ignore, 0},
13079
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13080
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13081
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13082
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13083
    // (MVE_VMLALDAVau32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 127
13084
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13085
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
13086
1.15M
    {AliasPatternCond_K_Ignore, 0},
13087
1.15M
    {AliasPatternCond_K_Ignore, 0},
13088
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13089
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13090
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13091
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13092
    // (MVE_VMLALDAVs16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 135
13093
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13094
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
13095
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13096
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13097
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13098
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13099
    // (MVE_VMLALDAVs32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 141
13100
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13101
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
13102
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13103
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13104
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13105
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13106
    // (MVE_VMLALDAVu16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 147
13107
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13108
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
13109
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13110
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13111
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13112
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13113
    // (MVE_VMLALDAVu32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 153
13114
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13115
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
13116
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13117
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13118
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13119
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13120
    // (MVE_VORR MQPR:$Qd, MQPR:$Qm, MQPR:$Qm, vpred_r:$vp) - 159
13121
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13122
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13123
1.15M
    {AliasPatternCond_K_TiedReg, 1},
13124
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13125
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13126
    // (MVE_VRMLALDAVHas32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 164
13127
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13128
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
13129
1.15M
    {AliasPatternCond_K_Ignore, 0},
13130
1.15M
    {AliasPatternCond_K_Ignore, 0},
13131
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13132
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13133
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13134
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13135
    // (MVE_VRMLALDAVHau32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 172
13136
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13137
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
13138
1.15M
    {AliasPatternCond_K_Ignore, 0},
13139
1.15M
    {AliasPatternCond_K_Ignore, 0},
13140
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13141
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13142
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13143
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13144
    // (MVE_VRMLALDAVHs32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 180
13145
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13146
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
13147
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13148
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13149
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13150
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13151
    // (MVE_VRMLALDAVHu32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 186
13152
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
13153
1.15M
    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
13154
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13155
1.15M
    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
13156
1.15M
    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
13157
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13158
    // (t2CSINC rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond) - 192
13159
1.15M
    {AliasPatternCond_K_RegClass, ARM_rGPRRegClassID},
13160
1.15M
    {AliasPatternCond_K_Reg, ARM_ZR},
13161
1.15M
    {AliasPatternCond_K_Reg, ARM_ZR},
13162
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps},
13163
    // (t2CSINC rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond) - 196
13164
1.15M
    {AliasPatternCond_K_RegClass, ARM_rGPRRegClassID},
13165
1.15M
    {AliasPatternCond_K_RegClass, ARM_GPRwithZRnospRegClassID},
13166
1.15M
    {AliasPatternCond_K_TiedReg, 1},
13167
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps},
13168
    // (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond) - 200
13169
1.15M
    {AliasPatternCond_K_RegClass, ARM_rGPRRegClassID},
13170
1.15M
    {AliasPatternCond_K_Reg, ARM_ZR},
13171
1.15M
    {AliasPatternCond_K_Reg, ARM_ZR},
13172
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps},
13173
    // (t2CSINV rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond) - 204
13174
1.15M
    {AliasPatternCond_K_RegClass, ARM_rGPRRegClassID},
13175
1.15M
    {AliasPatternCond_K_RegClass, ARM_GPRwithZRnospRegClassID},
13176
1.15M
    {AliasPatternCond_K_TiedReg, 1},
13177
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps},
13178
    // (t2CSNEG rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond) - 208
13179
1.15M
    {AliasPatternCond_K_RegClass, ARM_rGPRRegClassID},
13180
1.15M
    {AliasPatternCond_K_RegClass, ARM_GPRwithZRnospRegClassID},
13181
1.15M
    {AliasPatternCond_K_TiedReg, 1},
13182
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps},
13183
    // (t2DSB 0, 14, 0) - 212
13184
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)0},
13185
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)14},
13186
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)0},
13187
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureDB},
13188
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13189
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13190
    // (t2DSB 4, 14, 0) - 218
13191
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)4},
13192
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)14},
13193
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)0},
13194
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureDB},
13195
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13196
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13197
    // (t2DSB 12, pred:$p) - 224
13198
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)12},
13199
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureDFB},
13200
    // (t2HINT 0, pred:$p) - 226
13201
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)0},
13202
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13203
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13204
    // (t2HINT 1, pred:$p) - 229
13205
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)1},
13206
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13207
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13208
    // (t2HINT 2, pred:$p) - 232
13209
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)2},
13210
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13211
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13212
    // (t2HINT 3, pred:$p) - 235
13213
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)3},
13214
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13215
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13216
    // (t2HINT 4, pred:$p) - 238
13217
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)4},
13218
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13219
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13220
    // (t2HINT 5, pred:$p) - 241
13221
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)5},
13222
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13223
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13224
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV8Ops},
13225
    // (t2HINT 16, pred:$p) - 245
13226
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)16},
13227
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13228
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13229
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureRAS},
13230
    // (t2HINT 20, pred:$p) - 249
13231
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)20},
13232
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13233
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13234
    // (t2HINT 13, pred:$p) - 252
13235
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)13},
13236
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13237
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13238
    // (t2HINT 15, pred:$p) - 255
13239
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)15},
13240
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13241
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13242
    // (t2HINT 29, pred:$p) - 258
13243
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)29},
13244
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13245
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13246
    // (t2HINT 45, pred:$p) - 261
13247
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)45},
13248
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13249
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13250
    // (t2HINT 22, pred:$p) - 264
13251
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)22},
13252
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13253
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13254
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV8Ops},
13255
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureCLRBHB},
13256
    // (t2SUBS_PC_LR 0, pred:$p) - 269
13257
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)0},
13258
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13259
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13260
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureVirtualization},
13261
    // (tHINT 0, pred:$p) - 273
13262
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)0},
13263
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13264
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV6MOps},
13265
    // (tHINT 1, pred:$p) - 276
13266
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)1},
13267
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13268
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV6MOps},
13269
    // (tHINT 2, pred:$p) - 279
13270
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)2},
13271
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13272
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV6MOps},
13273
    // (tHINT 3, pred:$p) - 282
13274
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)3},
13275
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13276
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV6MOps},
13277
    // (tHINT 4, pred:$p) - 285
13278
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)4},
13279
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13280
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV6MOps},
13281
    // (tHINT 5, pred:$p) - 288
13282
1.15M
    {AliasPatternCond_K_Imm, (uint32_t)5},
13283
1.15M
    {AliasPatternCond_K_Feature, ARM_ModeThumb},
13284
1.15M
    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
13285
1.15M
    {AliasPatternCond_K_Feature, ARM_HasV8Ops},
13286
1.15M
  {0},  };
13287
13288
1.15M
  static const char AsmStrings[] =
13289
1.15M
    /* 0 */ "ssbb\0"
13290
1.15M
    /* 5 */ "pssbb\0"
13291
1.15M
    /* 11 */ "dfb\0"
13292
1.15M
    /* 15 */ "nop$\xFF\x02\x01\0"
13293
1.15M
    /* 23 */ "yield$\xFF\x02\x01\0"
13294
1.15M
    /* 33 */ "wfe$\xFF\x02\x01\0"
13295
1.15M
    /* 41 */ "wfi$\xFF\x02\x01\0"
13296
1.15M
    /* 49 */ "sev$\xFF\x02\x01\0"
13297
1.15M
    /* 57 */ "sevl$\xFF\x02\x01\0"
13298
1.15M
    /* 66 */ "esb$\xFF\x02\x01\0"
13299
1.15M
    /* 74 */ "csdb$\xFF\x02\x01\0"
13300
1.15M
    /* 83 */ "clrbhb$\xFF\x02\x01\0"
13301
1.15M
    /* 94 */ "vmlava$\xFF\x05\x02.s16 $\x01, $\x03, $\x04\0"
13302
1.15M
    /* 120 */ "vmlava$\xFF\x05\x02.s32  $\x01, $\x03, $\x04\0"
13303
1.15M
    /* 146 */ "vmlava$\xFF\x05\x02.s8 $\x01, $\x03, $\x04\0"
13304
1.15M
    /* 171 */ "vmlava$\xFF\x05\x02.u16  $\x01, $\x03, $\x04\0"
13305
1.15M
    /* 197 */ "vmlava$\xFF\x05\x02.u32  $\x01, $\x03, $\x04\0"
13306
1.15M
    /* 223 */ "vmlava$\xFF\x05\x02.u8 $\x01, $\x03, $\x04\0"
13307
1.15M
    /* 248 */ "vmlav$\xFF\x04\x02.s16 $\x01, $\x02, $\x03\0"
13308
1.15M
    /* 273 */ "vmlav$\xFF\x04\x02.s32 $\x01, $\x02, $\x03\0"
13309
1.15M
    /* 298 */ "vmlav$\xFF\x04\x02.s8  $\x01, $\x02, $\x03\0"
13310
1.15M
    /* 322 */ "vmlav$\xFF\x04\x02.u16 $\x01, $\x02, $\x03\0"
13311
1.15M
    /* 347 */ "vmlav$\xFF\x04\x02.u32 $\x01, $\x02, $\x03\0"
13312
1.15M
    /* 372 */ "vmlav$\xFF\x04\x02.u8  $\x01, $\x02, $\x03\0"
13313
1.15M
    /* 396 */ "vmlalva$\xFF\x07\x02.s16 $\x01, $\x02, $\x05, $\x06\0"
13314
1.15M
    /* 427 */ "vmlalva$\xFF\x07\x02.s32 $\x01, $\x02, $\x05, $\x06\0"
13315
1.15M
    /* 458 */ "vmlalva$\xFF\x07\x02.u16 $\x01, $\x02, $\x05, $\x06\0"
13316
1.15M
    /* 489 */ "vmlalva$\xFF\x07\x02.u32 $\x01, $\x02, $\x05, $\x06\0"
13317
1.15M
    /* 520 */ "vmlalv$\xFF\x05\x02.s16  $\x01, $\x02, $\x03, $\x04\0"
13318
1.15M
    /* 550 */ "vmlalv$\xFF\x05\x02.s32  $\x01, $\x02, $\x03, $\x04\0"
13319
1.15M
    /* 580 */ "vmlalv$\xFF\x05\x02.u16  $\x01, $\x02, $\x03, $\x04\0"
13320
1.15M
    /* 610 */ "vmlalv$\xFF\x05\x02.u32  $\x01, $\x02, $\x03, $\x04\0"
13321
1.15M
    /* 640 */ "vmov$\xFF\x04\x02  $\x01, $\x02\0"
13322
1.15M
    /* 656 */ "vrmlalvha$\xFF\x07\x02.s32 $\x01, $\x02, $\x05, $\x06\0"
13323
1.15M
    /* 689 */ "vrmlalvha$\xFF\x07\x02.u32 $\x01, $\x02, $\x05, $\x06\0"
13324
1.15M
    /* 722 */ "vrmlalvh$\xFF\x05\x02.s32  $\x01, $\x02, $\x03, $\x04\0"
13325
1.15M
    /* 754 */ "vrmlalvh$\xFF\x05\x02.u32  $\x01, $\x02, $\x03, $\x04\0"
13326
1.15M
    /* 786 */ "cset $\x01, $\xFF\x04\x03\0"
13327
1.15M
    /* 800 */ "cinc $\x01, $\x02, $\xFF\x04\x03\0"
13328
1.15M
    /* 818 */ "csetm  $\x01, $\xFF\x04\x03\0"
13329
1.15M
    /* 833 */ "cinv $\x01, $\x02, $\xFF\x04\x03\0"
13330
1.15M
    /* 851 */ "cneg $\x01, $\x02, $\xFF\x04\x03\0"
13331
1.15M
    /* 869 */ "dfb$\xFF\x02\x01\0"
13332
1.15M
    /* 877 */ "nop$\xFF\x02\x01.w\0"
13333
1.15M
    /* 887 */ "yield$\xFF\x02\x01.w\0"
13334
1.15M
    /* 899 */ "wfe$\xFF\x02\x01.w\0"
13335
1.15M
    /* 909 */ "wfi$\xFF\x02\x01.w\0"
13336
1.15M
    /* 919 */ "sev$\xFF\x02\x01.w\0"
13337
1.15M
    /* 929 */ "sevl$\xFF\x02\x01.w\0"
13338
1.15M
    /* 940 */ "esb$\xFF\x02\x01.w\0"
13339
1.15M
    /* 950 */ "pacbti$\xFF\x02\x01 r12,lr,sp\0"
13340
1.15M
    /* 971 */ "bti$\xFF\x02\x01\0"
13341
1.15M
    /* 979 */ "pac$\xFF\x02\x01 r12,lr,sp\0"
13342
1.15M
    /* 997 */ "aut$\xFF\x02\x01 r12,lr,sp\0"
13343
1.15M
    /* 1015 */ "eret$\xFF\x02\x01\0"
13344
1.15M
  ;
13345
13346
1.15M
#ifndef NDEBUG
13347
  //static struct SortCheck {
13348
  //  SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
13349
  //    assert(std::is_sorted(
13350
  //               OpToPatterns.begin(), OpToPatterns.end(),
13351
  //               [](const PatternsForOpcode &L, const //PatternsForOpcode &R) {
13352
  //                 return L.Opcode < R.Opcode;
13353
  //               }) &&
13354
  //           "tablegen failed to sort opcode patterns");
13355
  //  }
13356
  //} sortCheckVar(OpToPatterns);
13357
1.15M
#endif
13358
13359
1.15M
  AliasMatchingData M = {
13360
1.15M
    OpToPatterns,
13361
1.15M
    Patterns,
13362
1.15M
    Conds,
13363
1.15M
    AsmStrings,
13364
1.15M
    NULL,
13365
1.15M
  };
13366
1.15M
  const char *AsmString = matchAliasPatterns(MI, &M);
13367
1.15M
  if (!AsmString) return false;
13368
13369
3.66k
  unsigned I = 0;
13370
21.4k
  while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
13371
20.1k
         AsmString[I] != '$' && AsmString[I] != '\0')
13372
17.7k
    ++I;
13373
3.66k
  SStream_concat1(OS, '\t');
13374
3.66k
  char *substr = malloc(I+1);
13375
3.66k
  memcpy(substr, AsmString, I);
13376
3.66k
  substr[I] = '\0';
13377
3.66k
  SStream_concat0(OS, substr);
13378
3.66k
  free(substr);
13379
3.66k
  if (AsmString[I] != '\0') {
13380
3.56k
    if (AsmString[I] == ' ' || AsmString[I] == '\t') {
13381
1.21k
      SStream_concat1(OS, '\t');
13382
1.21k
      ++I;
13383
1.21k
    }
13384
26.6k
    do {
13385
26.6k
      if (AsmString[I] == '$') {
13386
10.0k
        ++I;
13387
10.0k
        if (AsmString[I] == (char)0xff) {
13388
3.56k
          ++I;
13389
3.56k
          int OpIdx = AsmString[I++] - 1;
13390
3.56k
          int PrintMethodIdx = AsmString[I++] - 1;
13391
3.56k
          printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS);
13392
3.56k
        } else
13393
6.44k
          printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS);
13394
16.6k
      } else {
13395
16.6k
        SStream_concat1(OS, AsmString[I++]);
13396
16.6k
      }
13397
26.6k
    } while (AsmString[I] != '\0');
13398
3.56k
  }
13399
13400
3.66k
  return true;
13401
#else
13402
  return false;
13403
#endif // CAPSTONE_DIET
13404
1.15M
}
13405
13406
static void printCustomAliasOperand(
13407
         MCInst *MI, uint64_t Address, unsigned OpIdx,
13408
         unsigned PrintMethodIdx,
13409
3.56k
         SStream *OS) {
13410
3.56k
#ifndef CAPSTONE_DIET
13411
3.56k
  switch (PrintMethodIdx) {
13412
0
  default:
13413
0
    CS_ASSERT_RET(0 && "Unknown PrintMethod kind");
13414
0
    break;
13415
994
  case 0:
13416
994
    printPredicateOperand(MI, OpIdx, OS);
13417
994
    break;
13418
1.35k
  case 1:
13419
1.35k
    printVPTPredicateOperand(MI, OpIdx, OS);
13420
1.35k
    break;
13421
1.21k
  case 2:
13422
1.21k
    printMandatoryInvertedPredicateOperand(MI, OpIdx, OS);
13423
1.21k
    break;
13424
3.56k
  }
13425
3.56k
#endif // CAPSTONE_DIET
13426
3.56k
}
13427
13428
#endif // PRINT_ALIAS_INSTR