/src/capstonev5/arch/TMS320C64x/TMS320C64xInstPrinter.c

Source
/* Capstone Disassembly Engine */
/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */

#ifdef CAPSTONE_HAS_TMS320C64X

#ifdef _MSC_VER
// Disable security warnings for strcpy
#ifndef _CRT_SECURE_NO_WARNINGS
#define _CRT_SECURE_NO_WARNINGS
#endif

// Banned API Usage : strcpy is a Banned API as listed in dontuse.h for
// security purposes.
#pragma warning(disable:28719)
#endif

#include <ctype.h>
#include <string.h>

#include "TMS320C64xInstPrinter.h"
#include "../../MCInst.h"
#include "../../utils.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "../../MathExtras.h"
#include "TMS320C64xMapping.h"

#include "capstone/tms320c64x.h"

static const char *getRegisterName(unsigned RegNo);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O);
static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O);

void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
{
  SStream ss;
  char *p, *p2, tmp[8];
  unsigned int unit = 0;
  int i;
  cs_tms320c64x *tms320c64x;

  if (mci->csh->detail) {
    tms320c64x = &mci->flat_insn->detail->tms320c64x;

    for (i = 0; i < insn->detail->groups_count; i++) {
      switch(insn->detail->groups[i]) {
        case TMS320C64X_GRP_FUNIT_D:
          unit = TMS320C64X_FUNIT_D;
          break;
        case TMS320C64X_GRP_FUNIT_L:
          unit = TMS320C64X_FUNIT_L;
          break;
        case TMS320C64X_GRP_FUNIT_M:
          unit = TMS320C64X_FUNIT_M;
          break;
        case TMS320C64X_GRP_FUNIT_S:
          unit = TMS320C64X_FUNIT_S;
          break;
        case TMS320C64X_GRP_FUNIT_NO:
          unit = TMS320C64X_FUNIT_NO;
          break;
      }
      if (unit != 0)
        break;
    }
    tms320c64x->funit.unit = unit;

    SStream_Init(&ss);
    if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
      SStream_concat(&ss, "[%c%s]|", (tms320c64x->condition.zero == 1) ? '!' : '|', cs_reg_name(ud, tms320c64x->condition.reg));

    p = strchr(insn_asm, '\t');
    if (p != NULL)
      *p++ = '\0';

    SStream_concat0(&ss, insn_asm);
    if ((p != NULL) && (((p2 = strchr(p, '[')) != NULL) || ((p2 = strchr(p, '(')) != NULL))) {
      while ((p2 > p) && ((*p2 != 'a') && (*p2 != 'b')))
        p2--;
      if (p2 == p) {
        strcpy(insn_asm, "Invalid!");
        return;
      }
      if (*p2 == 'a')
        strcpy(tmp, "1T");
      else
        strcpy(tmp, "2T");
    } else {
      tmp[0] = '\0';
    }
    switch(tms320c64x->funit.unit) {
      case TMS320C64X_FUNIT_D:
        SStream_concat(&ss, ".D%s%u", tmp, tms320c64x->funit.side);
        break;
      case TMS320C64X_FUNIT_L:
        SStream_concat(&ss, ".L%s%u", tmp, tms320c64x->funit.side);
        break;
      case TMS320C64X_FUNIT_M:
        SStream_concat(&ss, ".M%s%u", tmp, tms320c64x->funit.side);
        break;
      case TMS320C64X_FUNIT_S:
        SStream_concat(&ss, ".S%s%u", tmp, tms320c64x->funit.side);
        break;
    }
    if (tms320c64x->funit.crosspath > 0)
      SStream_concat0(&ss, "X");

    if (p != NULL)
      SStream_concat(&ss, "\t%s", p);

    if (tms320c64x->parallel != 0)
      SStream_concat0(&ss, "\t||");

    /* insn_asm is a buffer from an SStream, so there should be enough space */
    strcpy(insn_asm, ss.buffer);
  }
}

#define PRINT_ALIAS_INSTR
#include "TMS320C64xGenAsmWriter.inc"

#define GET_INSTRINFO_ENUM
#include "TMS320C64xGenInstrInfo.inc"

static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg;

  if (MCOperand_isReg(Op)) {
    reg = MCOperand_getReg(Op);
    if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) && (OpNo == 1)) {
      switch(reg) {
        case TMS320C64X_REG_EFR:
          SStream_concat0(O, "EFR");
          break;
        case TMS320C64X_REG_IFR:
          SStream_concat0(O, "IFR");
          break;
        default:
          SStream_concat0(O, getRegisterName(reg));
          break;
      }
    } else {
      SStream_concat0(O, getRegisterName(reg));
    }

    if (MI->csh->detail) {
      MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_REG;
      MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].reg = reg;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  } else if (MCOperand_isImm(Op)) {
    int64_t Imm = MCOperand_getImm(Op);

    if (Imm >= 0) {
      if (Imm > HEX_THRESHOLD)
        SStream_concat(O, "0x%"PRIx64, Imm);
      else
        SStream_concat(O, "%"PRIu64, Imm);
    } else {
      if (Imm < -HEX_THRESHOLD)
        SStream_concat(O, "-0x%"PRIx64, -Imm);
      else
        SStream_concat(O, "-%"PRIu64, -Imm);
    }

    if (MI->csh->detail) {
      MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_IMM;
      MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].imm = Imm;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  }
}

static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  unsigned scaled, base, offset, mode, unit;
  cs_tms320c64x *tms320c64x;
  char st, nd;

  scaled = (Val >> 19) & 1;
  base = (Val >> 12) & 0x7f;
  offset = (Val >> 5) & 0x7f;
  mode = (Val >> 1) & 0xf;
  unit = Val & 1;

  if (scaled) {
    st = '[';
    nd = ']';
  } else {
    st = '(';
    nd = ')';
  }

  switch(mode) {
    case 0:
      SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st, offset, nd);
      break;
    case 1:
      SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st, offset, nd);
      break;
    case 4:
      SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
      break;
    case 5:
      SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
      break;
    case 8:
      SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st, offset, nd);
      break;
    case 9:
      SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st, offset, nd);
      break;
    case 10:
      SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st, offset, nd);
      break;
    case 11:
      SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st, offset, nd);
      break;
    case 12:
      SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
      break;
    case 13:
      SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
      break;
    case 14:
      SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
      break;
    case 15:
      SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
      break;
  }

  if (MI->csh->detail) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = base;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
    tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
    switch(mode) {
      case 0:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
        break;
      case 1:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
        break;
      case 4:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
        break;
      case 5:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
        break;
      case 8:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
        break;
      case 9:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
        break;
      case 10:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
        break;
      case 11:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
        break;
      case 12:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
        break;
      case 13:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
        break;
      case 14:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
        break;
      case 15:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
        break;
    }
    tms320c64x->op_count++;
  }
}

static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  uint16_t offset;
  unsigned basereg;
  cs_tms320c64x *tms320c64x;

  basereg = Val & 0x7f;
  offset = (Val >> 7) & 0x7fff;
  SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);

  if (MI->csh->detail) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
    tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
    tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
    tms320c64x->op_count++;
  }
}

static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg = MCOperand_getReg(Op);
  cs_tms320c64x *tms320c64x;

  SStream_concat(O, "%s:%s", getRegisterName(reg + 1), getRegisterName(reg));

  if (MI->csh->detail) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_REGPAIR;
    tms320c64x->operands[tms320c64x->op_count].reg = reg;
    tms320c64x->op_count++;
  }
}

static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
{
  unsigned opcode = MCInst_getOpcode(MI);
  MCOperand *op;

  switch(opcode) {
    /* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
    case TMS320C64x_ADD_d2_rir:
    /* ADD.L -i, x, y -> SUB.L x, i, y */
    case TMS320C64x_ADD_l1_irr:
    case TMS320C64x_ADD_l1_ipp:
    /* ADD.S -i, x, y -> SUB.S x, i, y */
    case TMS320C64x_ADD_s1_irr:
      if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
        op = MCInst_getOperand(MI, 2);
        MCOperand_setImm(op, -MCOperand_getImm(op));

        SStream_concat0(O, "SUB\t");
        printOperand(MI, 1, O);
        SStream_concat0(O, ", ");
        printOperand(MI, 2, O);
        SStream_concat0(O, ", ");
        printOperand(MI, 0, O);

        return true;
      }
      break;
  }
  switch(opcode) {
    /* ADD.D 0, x, y -> MV.D x, y */
    case TMS320C64x_ADD_d1_rir:
    /* OR.D x, 0, y -> MV.D x, y */
    case TMS320C64x_OR_d2_rir:
    /* ADD.L 0, x, y -> MV.L x, y */
    case TMS320C64x_ADD_l1_irr:
    case TMS320C64x_ADD_l1_ipp:
    /* OR.L 0, x, y -> MV.L x, y */
    case TMS320C64x_OR_l1_irr:
    /* ADD.S 0, x, y -> MV.S x, y */
    case TMS320C64x_ADD_s1_irr:
    /* OR.S 0, x, y -> MV.S x, y */
    case TMS320C64x_OR_s1_irr:
      if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
        MI->size--;

        SStream_concat0(O, "MV\t");
        printOperand(MI, 1, O);
        SStream_concat0(O, ", ");
        printOperand(MI, 0, O);

        return true;
      }
      break;
  }
  switch(opcode) {
    /* XOR.D -1, x, y -> NOT.D x, y */
    case TMS320C64x_XOR_d2_rir:
    /* XOR.L -1, x, y -> NOT.L x, y */
    case TMS320C64x_XOR_l1_irr:
    /* XOR.S -1, x, y -> NOT.S x, y */
    case TMS320C64x_XOR_s1_irr:
      if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
        MI->size--;

        SStream_concat0(O, "NOT\t");
        printOperand(MI, 1, O);
        SStream_concat0(O, ", ");
        printOperand(MI, 0, O);

        return true;
      }
      break;
  }
  switch(opcode) {
    /* MVK.D 0, x -> ZERO.D x */
    case TMS320C64x_MVK_d1_rr:
    /* MVK.L 0, x -> ZERO.L x */
    case TMS320C64x_MVK_l2_ir:
      if ((MCInst_getNumOperands(MI) == 2) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
        MI->size--;

        SStream_concat0(O, "ZERO\t");
        printOperand(MI, 0, O);

        return true;
      }
      break;
  }
  switch(opcode) {
    /* SUB.L x, x, y -> ZERO.L y */
    case TMS320C64x_SUB_l1_rrp_x1:
    /* SUB.S x, x, y -> ZERO.S y */
    case TMS320C64x_SUB_s1_rrr:
      if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
        MI->size -= 2;

        SStream_concat0(O, "ZERO\t");
        printOperand(MI, 0, O);

        return true;
      }
      break;
  }
  switch(opcode) {
    /* SUB.L 0, x, y -> NEG.L x, y */
    case TMS320C64x_SUB_l1_irr:
    case TMS320C64x_SUB_l1_ipp:
    /* SUB.S 0, x, y -> NEG.S x, y */
    case TMS320C64x_SUB_s1_irr:
      if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
        MI->size--;

        SStream_concat0(O, "NEG\t");
        printOperand(MI, 1, O);
        SStream_concat0(O, ", ");
        printOperand(MI, 0, O);

        return true;
      }
      break;
  }
  switch(opcode) {
    /* PACKLH2.L x, x, y -> SWAP2.L x, y */
    case TMS320C64x_PACKLH2_l1_rrr_x2:
    /* PACKLH2.S x, x, y -> SWAP2.S x, y */
    case TMS320C64x_PACKLH2_s1_rrr:
      if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
        MI->size--;

        SStream_concat0(O, "SWAP2\t");
        printOperand(MI, 1, O);
        SStream_concat0(O, ", ");
        printOperand(MI, 0, O);

        return true;
      }
      break;
  }
  switch(opcode) {
    /* NOP 16 -> IDLE */
    /* NOP 1 -> NOP */
    case TMS320C64x_NOP_n:
      if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
        MI->size--;

        SStream_concat0(O, "IDLE");

        return true;
      }
      if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {

        MI->size--;

        SStream_concat0(O, "NOP");

        return true;
      }
      break;
  }

  return false;
}

void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info)
{
  if (!printAliasInstruction(MI, O, Info))
    printInstruction(MI, O, Info);
}

#endif

Coverage Report

Created: 2026-01-17 06:58

Line	Count	Source
1		/* Capstone Disassembly Engine */
2		/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
3
4		#ifdef CAPSTONE_HAS_TMS320C64X
5
6		#ifdef _MSC_VER
7		// Disable security warnings for strcpy
8		#ifndef _CRT_SECURE_NO_WARNINGS
9		#define _CRT_SECURE_NO_WARNINGS
10		#endif
11
12		// Banned API Usage : strcpy is a Banned API as listed in dontuse.h for
13		// security purposes.
14		#pragma warning(disable:28719)
15		#endif
16
17		#include <ctype.h>
18		#include <string.h>
19
20		#include "TMS320C64xInstPrinter.h"
21		#include "../../MCInst.h"
22		#include "../../utils.h"
23		#include "../../SStream.h"
24		#include "../../MCRegisterInfo.h"
25		#include "../../MathExtras.h"
26		#include "TMS320C64xMapping.h"
27
28		#include "capstone/tms320c64x.h"
29
30		static const char *getRegisterName(unsigned RegNo);
31		static void printOperand(MCInst MI, unsigned OpNo, SStream O);
32		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O);
33		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O);
34		static void printRegPair(MCInst MI, unsigned OpNo, SStream O);
35
36		void TMS320C64x_post_printer(csh ud, cs_insn insn, char insn_asm, MCInst *mci)
37	45.1k	{
38	45.1k	SStream ss;
39	45.1k	char p, p2, tmp[8];
40	45.1k	unsigned int unit = 0;
41	45.1k	int i;
42	45.1k	cs_tms320c64x *tms320c64x;
43
44	45.1k	if (mci->csh->detail) {
45	45.1k	tms320c64x = &mci->flat_insn->detail->tms320c64x;
46
47	45.1k	for (i = 0; i < insn->detail->groups_count; i++) {
48	45.1k	switch(insn->detail->groups[i]) {
49	12.6k	case TMS320C64X_GRP_FUNIT_D:
50	12.6k	unit = TMS320C64X_FUNIT_D;
51	12.6k	break;
52	9.80k	case TMS320C64X_GRP_FUNIT_L:
53	9.80k	unit = TMS320C64X_FUNIT_L;
54	9.80k	break;
55	2.71k	case TMS320C64X_GRP_FUNIT_M:
56	2.71k	unit = TMS320C64X_FUNIT_M;
57	2.71k	break;
58	18.6k	case TMS320C64X_GRP_FUNIT_S:
59	18.6k	unit = TMS320C64X_FUNIT_S;
60	18.6k	break;
61	1.31k	case TMS320C64X_GRP_FUNIT_NO:
62	1.31k	unit = TMS320C64X_FUNIT_NO;
63	1.31k	break;
64	45.1k	}
65	45.1k	if (unit != 0)
66	45.1k	break;
67	45.1k	}
68	45.1k	tms320c64x->funit.unit = unit;
69
70	45.1k	SStream_Init(&ss);
71	45.1k	if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
72	28.5k	SStream_concat(&ss, "[%c%s]\|", (tms320c64x->condition.zero == 1) ? '!' : '\|', cs_reg_name(ud, tms320c64x->condition.reg));
73
74	45.1k	p = strchr(insn_asm, '\t');
75	45.1k	if (p != NULL)
76	44.2k	*p++ = '\0';
77
78	45.1k	SStream_concat0(&ss, insn_asm);
79	45.1k	if ((p != NULL) && (((p2 = strchr(p, '[')) != NULL) \|\| ((p2 = strchr(p, '(')) != NULL))) {
80	39.4k	while ((p2 > p) && ((p2 != 'a') && (p2 != 'b')))
81	29.7k	p2--;
82	9.68k	if (p2 == p) {
83	0	strcpy(insn_asm, "Invalid!");
84	0	return;
85	0	}
86	9.68k	if (*p2 == 'a')
87	4.43k	strcpy(tmp, "1T");
88	5.24k	else
89	5.24k	strcpy(tmp, "2T");
90	35.4k	} else {
91	35.4k	tmp[0] = '\0';
92	35.4k	}
93	45.1k	switch(tms320c64x->funit.unit) {
94	12.6k	case TMS320C64X_FUNIT_D:
95	12.6k	SStream_concat(&ss, ".D%s%u", tmp, tms320c64x->funit.side);
96	12.6k	break;
97	9.80k	case TMS320C64X_FUNIT_L:
98	9.80k	SStream_concat(&ss, ".L%s%u", tmp, tms320c64x->funit.side);
99	9.80k	break;
100	2.71k	case TMS320C64X_FUNIT_M:
101	2.71k	SStream_concat(&ss, ".M%s%u", tmp, tms320c64x->funit.side);
102	2.71k	break;
103	18.6k	case TMS320C64X_FUNIT_S:
104	18.6k	SStream_concat(&ss, ".S%s%u", tmp, tms320c64x->funit.side);
105	18.6k	break;
106	45.1k	}
107	45.1k	if (tms320c64x->funit.crosspath > 0)
108	12.9k	SStream_concat0(&ss, "X");
109
110	45.1k	if (p != NULL)
111	44.2k	SStream_concat(&ss, "\t%s", p);
112
113	45.1k	if (tms320c64x->parallel != 0)
114	21.8k	SStream_concat0(&ss, "\t\|\|");
115
116		/* insn_asm is a buffer from an SStream, so there should be enough space */
117	45.1k	strcpy(insn_asm, ss.buffer);
118	45.1k	}
119	45.1k	}
120
121		#define PRINT_ALIAS_INSTR
122		#include "TMS320C64xGenAsmWriter.inc"
123
124		#define GET_INSTRINFO_ENUM
125		#include "TMS320C64xGenInstrInfo.inc"
126
127		static void printOperand(MCInst MI, unsigned OpNo, SStream O)
128	80.0k	{
129	80.0k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
130	80.0k	unsigned reg;
131
132	80.0k	if (MCOperand_isReg(Op)) {
133	56.7k	reg = MCOperand_getReg(Op);
134	56.7k	if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) && (OpNo == 1)) {
135	1.34k	switch(reg) {
136	197	case TMS320C64X_REG_EFR:
137	197	SStream_concat0(O, "EFR");
138	197	break;
139	498	case TMS320C64X_REG_IFR:
140	498	SStream_concat0(O, "IFR");
141	498	break;
142	646	default:
143	646	SStream_concat0(O, getRegisterName(reg));
144	646	break;
145	1.34k	}
146	55.4k	} else {
147	55.4k	SStream_concat0(O, getRegisterName(reg));
148	55.4k	}
149
150	56.7k	if (MI->csh->detail) {
151	56.7k	MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_REG;
152	56.7k	MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].reg = reg;
153	56.7k	MI->flat_insn->detail->tms320c64x.op_count++;
154	56.7k	}
155	56.7k	} else if (MCOperand_isImm(Op)) {
156	23.2k	int64_t Imm = MCOperand_getImm(Op);
157
158	23.2k	if (Imm >= 0) {
159	18.7k	if (Imm > HEX_THRESHOLD)
160	10.9k	SStream_concat(O, "0x%"PRIx64, Imm);
161	7.82k	else
162	7.82k	SStream_concat(O, "%"PRIu64, Imm);
163	18.7k	} else {
164	4.49k	if (Imm < -HEX_THRESHOLD)
165	3.75k	SStream_concat(O, "-0x%"PRIx64, -Imm);
166	741	else
167	741	SStream_concat(O, "-%"PRIu64, -Imm);
168	4.49k	}
169
170	23.2k	if (MI->csh->detail) {
171	23.2k	MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_IMM;
172	23.2k	MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].imm = Imm;
173	23.2k	MI->flat_insn->detail->tms320c64x.op_count++;
174	23.2k	}
175	23.2k	}
176	80.0k	}
177
178		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O)
179	4.43k	{
180	4.43k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
181	4.43k	int64_t Val = MCOperand_getImm(Op);
182	4.43k	unsigned scaled, base, offset, mode, unit;
183	4.43k	cs_tms320c64x *tms320c64x;
184	4.43k	char st, nd;
185
186	4.43k	scaled = (Val >> 19) & 1;
187	4.43k	base = (Val >> 12) & 0x7f;
188	4.43k	offset = (Val >> 5) & 0x7f;
189	4.43k	mode = (Val >> 1) & 0xf;
190	4.43k	unit = Val & 1;
191
192	4.43k	if (scaled) {
193	3.74k	st = '[';
194	3.74k	nd = ']';
195	3.74k	} else {
196	686	st = '(';
197	686	nd = ')';
198	686	}
199
200	4.43k	switch(mode) {
201	415	case 0:
202	415	SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st, offset, nd);
203	415	break;
204	395	case 1:
205	395	SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st, offset, nd);
206	395	break;
207	348	case 4:
208	348	SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
209	348	break;
210	252	case 5:
211	252	SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
212	252	break;
213	517	case 8:
214	517	SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st, offset, nd);
215	517	break;
216	487	case 9:
217	487	SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st, offset, nd);
218	487	break;
219	329	case 10:
220	329	SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st, offset, nd);
221	329	break;
222	404	case 11:
223	404	SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st, offset, nd);
224	404	break;
225	438	case 12:
226	438	SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
227	438	break;
228	212	case 13:
229	212	SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
230	212	break;
231	271	case 14:
232	271	SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
233	271	break;
234	367	case 15:
235	367	SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
236	367	break;
237	4.43k	}
238
239	4.43k	if (MI->csh->detail) {
240	4.43k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
241
242	4.43k	tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
243	4.43k	tms320c64x->operands[tms320c64x->op_count].mem.base = base;
244	4.43k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
245	4.43k	tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
246	4.43k	tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
247	4.43k	switch(mode) {
248	415	case 0:
249	415	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
250	415	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
251	415	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
252	415	break;
253	395	case 1:
254	395	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
255	395	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
256	395	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
257	395	break;
258	348	case 4:
259	348	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
260	348	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
261	348	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
262	348	break;
263	252	case 5:
264	252	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
265	252	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
266	252	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
267	252	break;
268	517	case 8:
269	517	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
270	517	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
271	517	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
272	517	break;
273	487	case 9:
274	487	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
275	487	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
276	487	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
277	487	break;
278	329	case 10:
279	329	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
280	329	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
281	329	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
282	329	break;
283	404	case 11:
284	404	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
285	404	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
286	404	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
287	404	break;
288	438	case 12:
289	438	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
290	438	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
291	438	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
292	438	break;
293	212	case 13:
294	212	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
295	212	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
296	212	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
297	212	break;
298	271	case 14:
299	271	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
300	271	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
301	271	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
302	271	break;
303	367	case 15:
304	367	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
305	367	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
306	367	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
307	367	break;
308	4.43k	}
309	4.43k	tms320c64x->op_count++;
310	4.43k	}
311	4.43k	}
312
313		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O)
314	5.24k	{
315	5.24k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
316	5.24k	int64_t Val = MCOperand_getImm(Op);
317	5.24k	uint16_t offset;
318	5.24k	unsigned basereg;
319	5.24k	cs_tms320c64x *tms320c64x;
320
321	5.24k	basereg = Val & 0x7f;
322	5.24k	offset = (Val >> 7) & 0x7fff;
323	5.24k	SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);
324
325	5.24k	if (MI->csh->detail) {
326	5.24k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
327
328	5.24k	tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
329	5.24k	tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
330	5.24k	tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
331	5.24k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
332	5.24k	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
333	5.24k	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
334	5.24k	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
335	5.24k	tms320c64x->op_count++;
336	5.24k	}
337	5.24k	}
338
339		static void printRegPair(MCInst MI, unsigned OpNo, SStream O)
340	13.7k	{
341	13.7k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
342	13.7k	unsigned reg = MCOperand_getReg(Op);
343	13.7k	cs_tms320c64x *tms320c64x;
344
345	13.7k	SStream_concat(O, "%s:%s", getRegisterName(reg + 1), getRegisterName(reg));
346
347	13.7k	if (MI->csh->detail) {
348	13.7k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
349
350	13.7k	tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_REGPAIR;
351	13.7k	tms320c64x->operands[tms320c64x->op_count].reg = reg;
352	13.7k	tms320c64x->op_count++;
353	13.7k	}
354	13.7k	}
355
356		static bool printAliasInstruction(MCInst MI, SStream O, MCRegisterInfo *MRI)
357	45.1k	{
358	45.1k	unsigned opcode = MCInst_getOpcode(MI);
359	45.1k	MCOperand *op;
360
361	45.1k	switch(opcode) {
362		/* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
363	295	case TMS320C64x_ADD_d2_rir:
364		/* ADD.L -i, x, y -> SUB.L x, i, y */
365	406	case TMS320C64x_ADD_l1_irr:
366	736	case TMS320C64x_ADD_l1_ipp:
367		/* ADD.S -i, x, y -> SUB.S x, i, y */
368	1.29k	case TMS320C64x_ADD_s1_irr:
369	1.29k	if ((MCInst_getNumOperands(MI) == 3) &&
370	1.29k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
371	1.29k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
372	1.29k	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
373	1.29k	(MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
374
375	225	MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
376	225	op = MCInst_getOperand(MI, 2);
377	225	MCOperand_setImm(op, -MCOperand_getImm(op));
378
379	225	SStream_concat0(O, "SUB\t");
380	225	printOperand(MI, 1, O);
381	225	SStream_concat0(O, ", ");
382	225	printOperand(MI, 2, O);
383	225	SStream_concat0(O, ", ");
384	225	printOperand(MI, 0, O);
385
386	225	return true;
387	225	}
388	1.07k	break;
389	45.1k	}
390	44.9k	switch(opcode) {
391		/* ADD.D 0, x, y -> MV.D x, y */
392	232	case TMS320C64x_ADD_d1_rir:
393		/* OR.D x, 0, y -> MV.D x, y */
394	469	case TMS320C64x_OR_d2_rir:
395		/* ADD.L 0, x, y -> MV.L x, y */
396	576	case TMS320C64x_ADD_l1_irr:
397	834	case TMS320C64x_ADD_l1_ipp:
398		/* OR.L 0, x, y -> MV.L x, y */
399	1.08k	case TMS320C64x_OR_l1_irr:
400		/* ADD.S 0, x, y -> MV.S x, y */
401	1.51k	case TMS320C64x_ADD_s1_irr:
402		/* OR.S 0, x, y -> MV.S x, y */
403	1.86k	case TMS320C64x_OR_s1_irr:
404	1.86k	if ((MCInst_getNumOperands(MI) == 3) &&
405	1.86k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
406	1.86k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
407	1.86k	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
408	1.86k	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
409
410	436	MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
411	436	MI->size--;
412
413	436	SStream_concat0(O, "MV\t");
414	436	printOperand(MI, 1, O);
415	436	SStream_concat0(O, ", ");
416	436	printOperand(MI, 0, O);
417
418	436	return true;
419	436	}
420	1.42k	break;
421	44.9k	}
422	44.4k	switch(opcode) {
423		/* XOR.D -1, x, y -> NOT.D x, y */
424	207	case TMS320C64x_XOR_d2_rir:
425		/* XOR.L -1, x, y -> NOT.L x, y */
426	411	case TMS320C64x_XOR_l1_irr:
427		/* XOR.S -1, x, y -> NOT.S x, y */
428	642	case TMS320C64x_XOR_s1_irr:
429	642	if ((MCInst_getNumOperands(MI) == 3) &&
430	642	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
431	642	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
432	642	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
433	642	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
434
435	372	MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
436	372	MI->size--;
437
438	372	SStream_concat0(O, "NOT\t");
439	372	printOperand(MI, 1, O);
440	372	SStream_concat0(O, ", ");
441	372	printOperand(MI, 0, O);
442
443	372	return true;
444	372	}
445	270	break;
446	44.4k	}
447	44.1k	switch(opcode) {
448		/* MVK.D 0, x -> ZERO.D x */
449	1.03k	case TMS320C64x_MVK_d1_rr:
450		/* MVK.L 0, x -> ZERO.L x */
451	2.45k	case TMS320C64x_MVK_l2_ir:
452	2.45k	if ((MCInst_getNumOperands(MI) == 2) &&
453	2.45k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
454	2.45k	MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
455	2.45k	(MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
456
457	158	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
458	158	MI->size--;
459
460	158	SStream_concat0(O, "ZERO\t");
461	158	printOperand(MI, 0, O);
462
463	158	return true;
464	158	}
465	2.30k	break;
466	44.1k	}
467	43.9k	switch(opcode) {
468		/* SUB.L x, x, y -> ZERO.L y */
469	191	case TMS320C64x_SUB_l1_rrp_x1:
470		/* SUB.S x, x, y -> ZERO.S y */
471	496	case TMS320C64x_SUB_s1_rrr:
472	496	if ((MCInst_getNumOperands(MI) == 3) &&
473	496	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
474	496	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
475	496	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
476	496	(MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
477
478	305	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
479	305	MI->size -= 2;
480
481	305	SStream_concat0(O, "ZERO\t");
482	305	printOperand(MI, 0, O);
483
484	305	return true;
485	305	}
486	191	break;
487	43.9k	}
488	43.6k	switch(opcode) {
489		/* SUB.L 0, x, y -> NEG.L x, y */
490	223	case TMS320C64x_SUB_l1_irr:
491	463	case TMS320C64x_SUB_l1_ipp:
492		/* SUB.S 0, x, y -> NEG.S x, y */
493	545	case TMS320C64x_SUB_s1_irr:
494	545	if ((MCInst_getNumOperands(MI) == 3) &&
495	545	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
496	545	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
497	545	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
498	545	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
499
500	78	MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
501	78	MI->size--;
502
503	78	SStream_concat0(O, "NEG\t");
504	78	printOperand(MI, 1, O);
505	78	SStream_concat0(O, ", ");
506	78	printOperand(MI, 0, O);
507
508	78	return true;
509	78	}
510	467	break;
511	43.6k	}
512	43.5k	switch(opcode) {
513		/* PACKLH2.L x, x, y -> SWAP2.L x, y */
514	232	case TMS320C64x_PACKLH2_l1_rrr_x2:
515		/* PACKLH2.S x, x, y -> SWAP2.S x, y */
516	762	case TMS320C64x_PACKLH2_s1_rrr:
517	762	if ((MCInst_getNumOperands(MI) == 3) &&
518	762	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
519	762	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
520	762	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
521	762	(MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
522
523	327	MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
524	327	MI->size--;
525
526	327	SStream_concat0(O, "SWAP2\t");
527	327	printOperand(MI, 1, O);
528	327	SStream_concat0(O, ", ");
529	327	printOperand(MI, 0, O);
530
531	327	return true;
532	327	}
533	435	break;
534	43.5k	}
535	43.2k	switch(opcode) {
536		/* NOP 16 -> IDLE */
537		/* NOP 1 -> NOP */
538	1.31k	case TMS320C64x_NOP_n:
539	1.31k	if ((MCInst_getNumOperands(MI) == 1) &&
540	1.31k	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
541	1.31k	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
542
543	334	MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
544	334	MI->size--;
545
546	334	SStream_concat0(O, "IDLE");
547
548	334	return true;
549	334	}
550	979	if ((MCInst_getNumOperands(MI) == 1) &&
551	979	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
552	979	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
553
554	586	MI->size--;
555
556	586	SStream_concat0(O, "NOP");
557
558	586	return true;
559	586	}
560	393	break;
561	43.2k	}
562
563	42.3k	return false;
564	43.2k	}
565
566		void TMS320C64x_printInst(MCInst MI, SStream O, void *Info)
567	45.1k	{
568	45.1k	if (!printAliasInstruction(MI, O, Info))
569	42.3k	printInstruction(MI, O, Info);
570	45.1k	}
571
572		#endif