Coverage Report

Created: 2026-02-26 07:11

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/capstonenext/arch/RISCV/RISCVGenCompressedInstructionsInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Compress instruction Source Fragment                                       *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|* From: RISCV.td                                                             *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GEN_COMPRESS_INSTR
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#undef GEN_COMPRESS_INSTR
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static bool RISCVValidateMCOperandForCompress(MCInst *MI,MCOperand *MCOp,
15
                  unsigned PredicateIndex) {
16
  switch (PredicateIndex) {
17
  default:
18
    CS_ASSERT_RET_VAL(0,false);
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   return false;
20
    break;
21
  case 1: {
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  // uimm10_lsb00nonzero
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24
    int64_t Imm;
25
    if (!(Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
26
      return false;
27
    return isShiftedUIntN(8, 2, Imm) && (Imm != 0);
28
29
  }
30
  case 2: {
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  // simm6nonzero
32
33
    int64_t Imm;
34
    if ((Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
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      return (Imm != 0) && isIntN(6, Imm);
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    return MCOperand_isExpr(MCOp);
37
38
  }
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  case 3: {
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  // simm6
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42
    int64_t Imm;
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    if ((Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
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      return isIntN(6, Imm);
45
    return MCOperand_isExpr(MCOp);
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47
  }
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  case 4: {
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  // simm10_lsb0000nonzero
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51
    int64_t Imm;
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    if (!(Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
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      return false;
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    return isShiftedIntN(6, 4, Imm) && (Imm != 0);
55
56
  }
57
  case 5: {
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  // simm9_lsb0
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60
    int64_t Imm;
61
    if ((Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
62
      return isShiftedIntN(8, 1, Imm);
63
    return MCOperand_isExpr(MCOp);
64
65
66
  }
67
  case 6: {
68
  // uimm8_lsb000
69
70
    int64_t Imm;
71
    if (!(Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
72
      return false;
73
    return isShiftedUIntN(5, 3, Imm);
74
75
  }
76
  case 7: {
77
  // uimm9_lsb000
78
79
    int64_t Imm;
80
    if (!(Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
81
      return false;
82
    return isShiftedUIntN(6, 3, Imm);
83
84
  }
85
  case 8: {
86
  // uimm7_lsb00
87
88
    int64_t Imm;
89
    if (!(Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
90
      return false;
91
    return isShiftedUIntN(5, 2, Imm);
92
93
  }
94
  case 9: {
95
  // uimm8_lsb00
96
97
    int64_t Imm;
98
    if (!(Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
99
      return false;
100
    return isShiftedUIntN(6, 2, Imm);
101
102
  }
103
  case 10: {
104
  // simm12_lsb0
105
106
    int64_t Imm;
107
    if ((Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
108
      return isShiftedIntN(11, 1, Imm);
109
    return MCOperand_isExpr(MCOp);
110
111
  }
112
  case 11: {
113
  // uimm2
114
115
    int64_t Imm;
116
    if (!(Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
117
      return false;
118
    return isUIntN(2, Imm);
119
120
  }
121
  case 12: {
122
  // uimm2_lsb0
123
124
    int64_t Imm;
125
    if (!(Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
126
      return false;
127
    return isShiftedUIntN(1, 1, Imm);
128
129
  }
130
  case 13: {
131
  // c_lui_imm
132
133
    int64_t Imm;
134
    if ((Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
135
      return (Imm != 0) && (isUIntN(5, Imm) ||
136
             (Imm >= 0xfffe0 && Imm <= 0xfffff));
137
    return MCOperand_isExpr(MCOp);
138
139
  }
140
  case 14: {
141
  // uimmlog2xlennonzero
142
143
    int64_t Imm;
144
    if (!(Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
145
      return false;
146
    if (RISCV_getFeatureBits(MI->csh->mode,RISCV_Feature64Bit))
147
      return  isUIntN(6, Imm) && (Imm != 0);
148
    return isUIntN(5, Imm) && (Imm != 0);
149
  }
150
  }
151
}
152
153
static bool compressInst(MCInst *OutInst,
154
                         MCInst *MI) {
155
  switch (MCInst_getOpcode(MI)) {
156
    default: return false;
157
    case RISCV_ADD: {
158
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
159
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
160
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) &&
161
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
162
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
163
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
164
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
165
      // c.mv $rs1, $rs2
166
      MCInst_setOpcode(OutInst, RISCV_C_MV);
167
      // Operand: rs1
168
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
169
      // Operand: rs2
170
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
171
172
      return true;
173
    } // if
174
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
175
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
176
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) &&
177
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
178
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
179
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
180
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
181
      // c.mv $rs1, $rs2
182
      MCInst_setOpcode(OutInst, RISCV_C_MV);
183
      // Operand: rs1
184
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
185
      // Operand: rs2
186
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
187
188
      return true;
189
    } // if
190
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
191
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
192
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
193
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
194
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
195
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
196
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
197
      // c.add  $rs1, $rs2
198
      MCInst_setOpcode(OutInst, RISCV_C_ADD);
199
      // Operand: rs1_wb
200
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
201
      // Operand: rs1
202
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
203
      // Operand: rs2
204
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
205
206
      return true;
207
    } // if
208
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
209
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
210
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
211
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
212
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2)))) &&
213
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
214
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
215
      // c.add  $rs1, $rs2
216
      MCInst_setOpcode(OutInst, RISCV_C_ADD);
217
      // Operand: rs1_wb
218
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
219
      // Operand: rs1
220
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
221
      // Operand: rs2
222
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
223
224
      return true;
225
    } // if
226
      break;
227
    } // case ADD
228
    case RISCV_ADDI: {
229
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
230
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
231
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
232
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
233
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
234
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 1)) {
235
      // c.addi4spn $rd, $rs1, $imm
236
      MCInst_setOpcode(OutInst, RISCV_C_ADDI4SPN);
237
      // Operand: rd
238
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
239
      // Operand: rs1
240
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
241
      // Operand: imm
242
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
243
244
      return true;
245
    } // if
246
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
247
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
248
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) &&
249
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
250
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) &&
251
      (MCOperand_isImm(MCInst_getOperand(MI, 2))) &&
252
      (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
253
      // c.nop
254
      MCInst_setOpcode(OutInst, RISCV_C_NOP);
255
256
      return true;
257
    } // if
258
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
259
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
260
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
261
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
262
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
263
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 2)) {
264
      // c.addi $rd, $imm
265
      MCInst_setOpcode(OutInst, RISCV_C_ADDI);
266
      // Operand: rd_wb
267
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
268
      // Operand: rd
269
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
270
      // Operand: imm
271
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
272
273
      return true;
274
    } // if
275
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
276
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
277
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) &&
278
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
279
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
280
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 3)) {
281
      // c.li $rd, $imm
282
      MCInst_setOpcode(OutInst, RISCV_C_LI);
283
      // Operand: rd
284
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
285
      // Operand: imm
286
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
287
288
      return true;
289
    } // if
290
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
291
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
292
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X2) &&
293
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
294
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X2) &&
295
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 4)) {
296
      // c.addi16sp $rd, $imm
297
      MCInst_setOpcode(OutInst, RISCV_C_ADDI16SP);
298
      // Operand: rd_wb
299
      MCOperand_CreateReg0(OutInst, RISCV_X2);
300
      // Operand: rd
301
      MCOperand_CreateReg0(OutInst, RISCV_X2);
302
      // Operand: imm
303
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
304
305
      return true;
306
    } // if
307
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
308
      (MCOperand_isImm(MCInst_getOperand(MI, 2))) &&
309
      (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) &&
310
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
311
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
312
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
313
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
314
      // c.mv $rs1, $rs2
315
      MCInst_setOpcode(OutInst, RISCV_C_MV);
316
      // Operand: rs1
317
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
318
      // Operand: rs2
319
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
320
321
      return true;
322
    } // if
323
      break;
324
    } // case ADDI
325
    case RISCV_ADDIW: {
326
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
327
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
328
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
329
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
330
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
331
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
332
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 3)) {
333
      // c.addiw  $rd, $imm
334
      MCInst_setOpcode(OutInst, RISCV_C_ADDIW);
335
      // Operand: rd_wb
336
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
337
      // Operand: rd
338
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
339
      // Operand: imm
340
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
341
342
      return true;
343
    } // if
344
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
345
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
346
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
347
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) &&
348
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
349
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
350
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 3)) {
351
      // c.li $rd, $imm
352
      MCInst_setOpcode(OutInst, RISCV_C_LI);
353
      // Operand: rd
354
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
355
      // Operand: imm
356
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
357
358
      return true;
359
    } // if
360
      break;
361
    } // case ADDIW
362
    case RISCV_ADDW: {
363
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
364
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
365
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
366
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
367
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
368
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
369
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
370
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
371
      // c.addw $rd, $rs2
372
      MCInst_setOpcode(OutInst, RISCV_C_ADDW);
373
      // Operand: rd_wb
374
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
375
      // Operand: rd
376
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
377
      // Operand: rs2
378
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
379
380
      return true;
381
    } // if
382
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
383
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
384
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
385
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
386
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
387
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2)))) &&
388
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
389
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
390
      // c.addw $rd, $rs2
391
      MCInst_setOpcode(OutInst, RISCV_C_ADDW);
392
      // Operand: rd_wb
393
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
394
      // Operand: rd
395
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
396
      // Operand: rs2
397
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
398
399
      return true;
400
    } // if
401
      break;
402
    } // case ADDW
403
    case RISCV_ADD_UW: {
404
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
405
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZba) &&
406
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
407
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
408
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
409
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
410
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) &&
411
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
412
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
413
      // c.zext.w $rd
414
      MCInst_setOpcode(OutInst, RISCV_C_ZEXT_W);
415
      // Operand: rd_wb
416
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
417
      // Operand: rd
418
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
419
420
      return true;
421
    } // if
422
      break;
423
    } // case ADD_UW
424
    case RISCV_AND: {
425
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
426
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
427
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
428
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
429
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
430
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
431
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
432
      // c.and  $rd, $rs2
433
      MCInst_setOpcode(OutInst, RISCV_C_AND);
434
      // Operand: rd_wb
435
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
436
      // Operand: rd
437
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
438
      // Operand: rs2
439
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
440
441
      return true;
442
    } // if
443
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
444
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
445
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
446
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
447
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2)))) &&
448
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
449
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
450
      // c.and  $rd, $rs2
451
      MCInst_setOpcode(OutInst, RISCV_C_AND);
452
      // Operand: rd_wb
453
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
454
      // Operand: rd
455
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
456
      // Operand: rs2
457
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
458
459
      return true;
460
    } // if
461
      break;
462
    } // case AND
463
    case RISCV_ANDI: {
464
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
465
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
466
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
467
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
468
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
469
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 3)) {
470
      // c.andi $rs1, $imm
471
      MCInst_setOpcode(OutInst, RISCV_C_ANDI);
472
      // Operand: rs1_wb
473
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
474
      // Operand: rs1
475
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
476
      // Operand: imm
477
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
478
479
      return true;
480
    } // if
481
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
482
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
483
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
484
      (MCOperand_isImm(MCInst_getOperand(MI, 2))) &&
485
      (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 255) &&
486
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
487
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
488
      // c.zext.b $rd
489
      MCInst_setOpcode(OutInst, RISCV_C_ZEXT_B);
490
      // Operand: rd_wb
491
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
492
      // Operand: rd
493
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
494
495
      return true;
496
    } // if
497
      break;
498
    } // case ANDI
499
    case RISCV_BEQ: {
500
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
501
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
502
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) &&
503
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
504
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
505
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 5)) {
506
      // c.beqz $rs1, $imm
507
      MCInst_setOpcode(OutInst, RISCV_C_BEQZ);
508
      // Operand: rs1
509
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
510
      // Operand: imm
511
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
512
513
      return true;
514
    } // if
515
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
516
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
517
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) &&
518
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
519
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
520
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 5)) {
521
      // c.beqz $rs1, $imm
522
      MCInst_setOpcode(OutInst, RISCV_C_BEQZ);
523
      // Operand: rs1
524
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
525
      // Operand: imm
526
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
527
528
      return true;
529
    } // if
530
      break;
531
    } // case BEQ
532
    case RISCV_BNE: {
533
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
534
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
535
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) &&
536
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
537
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
538
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 5)) {
539
      // c.bnez $rs1, $imm
540
      MCInst_setOpcode(OutInst, RISCV_C_BNEZ);
541
      // Operand: rs1
542
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
543
      // Operand: imm
544
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
545
546
      return true;
547
    } // if
548
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
549
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
550
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) &&
551
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
552
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
553
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 5)) {
554
      // c.bnez $rs1, $imm
555
      MCInst_setOpcode(OutInst, RISCV_C_BNEZ);
556
      // Operand: rs1
557
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
558
      // Operand: imm
559
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
560
561
      return true;
562
    } // if
563
      break;
564
    } // case BNE
565
    case RISCV_EBREAK: {
566
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca))) {
567
      // c.ebreak
568
      MCInst_setOpcode(OutInst, RISCV_C_EBREAK);
569
570
      return true;
571
    } // if
572
      break;
573
    } // case EBREAK
574
    case RISCV_FLD: {
575
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtD) &&
576
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcd)) &&
577
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
578
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR64CRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
579
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
580
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
581
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 6)) {
582
      // c.fld  $rd, ${imm}(${rs1})
583
      MCInst_setOpcode(OutInst, RISCV_C_FLD);
584
      // Operand: rd
585
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
586
      // Operand: rs1
587
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
588
      // Operand: imm
589
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
590
591
      return true;
592
    } // if
593
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtD) &&
594
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcd)) &&
595
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
596
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR64RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
597
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
598
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
599
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 7)) {
600
      // c.fldsp  $rd, ${imm}(${rs1})
601
      MCInst_setOpcode(OutInst, RISCV_C_FLDSP);
602
      // Operand: rd
603
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
604
      // Operand: rs1
605
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
606
      // Operand: imm
607
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
608
609
      return true;
610
    } // if
611
      break;
612
    } // case FLD
613
    case RISCV_FLW: {
614
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtF) &&
615
      !RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
616
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZce) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcf)) &&
617
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
618
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR32CRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
619
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
620
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
621
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 8)) {
622
      // c.flw  $rd, ${imm}(${rs1})
623
      MCInst_setOpcode(OutInst, RISCV_C_FLW);
624
      // Operand: rd
625
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
626
      // Operand: rs1
627
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
628
      // Operand: imm
629
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
630
631
      return true;
632
    } // if
633
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtF) &&
634
      !RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
635
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZce) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcf)) &&
636
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
637
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR32RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
638
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
639
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
640
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 9)) {
641
      // c.flwsp  $rd, ${imm}(${rs1})
642
      MCInst_setOpcode(OutInst, RISCV_C_FLWSP);
643
      // Operand: rd
644
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
645
      // Operand: rs1
646
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
647
      // Operand: imm
648
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
649
650
      return true;
651
    } // if
652
      break;
653
    } // case FLW
654
    case RISCV_FSD: {
655
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtD) &&
656
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcd)) &&
657
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
658
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR64CRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
659
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
660
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
661
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 6)) {
662
      // c.fsd  $rs2, ${imm}(${rs1})
663
      MCInst_setOpcode(OutInst, RISCV_C_FSD);
664
      // Operand: rs2
665
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
666
      // Operand: rs1
667
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
668
      // Operand: imm
669
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
670
671
      return true;
672
    } // if
673
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtD) &&
674
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcd)) &&
675
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
676
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR64RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
677
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
678
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
679
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 7)) {
680
      // c.fsdsp  $rs2, ${imm}(${rs1})
681
      MCInst_setOpcode(OutInst, RISCV_C_FSDSP);
682
      // Operand: rs2
683
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
684
      // Operand: rs1
685
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
686
      // Operand: imm
687
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
688
689
      return true;
690
    } // if
691
      break;
692
    } // case FSD
693
    case RISCV_FSW: {
694
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtF) &&
695
      !RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
696
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZce) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcf)) &&
697
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
698
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR32CRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
699
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
700
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
701
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 8)) {
702
      // c.fsw  $rs2, ${imm}(${rs1})
703
      MCInst_setOpcode(OutInst, RISCV_C_FSW);
704
      // Operand: rs2
705
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
706
      // Operand: rs1
707
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
708
      // Operand: imm
709
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
710
711
      return true;
712
    } // if
713
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtF) &&
714
      !RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
715
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZce) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcf)) &&
716
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
717
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR32RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
718
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
719
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
720
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 9)) {
721
      // c.fswsp  $rs2, ${imm}(${rs1})
722
      MCInst_setOpcode(OutInst, RISCV_C_FSWSP);
723
      // Operand: rs2
724
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
725
      // Operand: rs1
726
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
727
      // Operand: imm
728
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
729
730
      return true;
731
    } // if
732
      break;
733
    } // case FSW
734
    case RISCV_JAL: {
735
    if (!RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
736
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
737
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
738
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1) &&
739
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 1), 10)) {
740
      // c.jal  $offset
741
      MCInst_setOpcode(OutInst, RISCV_C_JAL);
742
      // Operand: offset
743
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
744
745
      return true;
746
    } // if
747
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
748
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
749
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) &&
750
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 1), 10)) {
751
      // c.j  $offset
752
      MCInst_setOpcode(OutInst, RISCV_C_J);
753
      // Operand: offset
754
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
755
756
      return true;
757
    } // if
758
      break;
759
    } // case JAL
760
    case RISCV_JALR: {
761
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
762
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
763
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) &&
764
      (MCOperand_isImm(MCInst_getOperand(MI, 2))) &&
765
      (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) &&
766
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
767
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
768
      // c.jr $rs1
769
      MCInst_setOpcode(OutInst, RISCV_C_JR);
770
      // Operand: rs1
771
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
772
773
      return true;
774
    } // if
775
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
776
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
777
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1) &&
778
      (MCOperand_isImm(MCInst_getOperand(MI, 2))) &&
779
      (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) &&
780
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
781
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
782
      // c.jalr $rs1
783
      MCInst_setOpcode(OutInst, RISCV_C_JALR);
784
      // Operand: rs1
785
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
786
787
      return true;
788
    } // if
789
      break;
790
    } // case JALR
791
    case RISCV_LBU: {
792
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
793
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
794
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
795
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
796
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
797
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 11)) {
798
      // c.lbu  $rd, ${imm}(${rs1})
799
      MCInst_setOpcode(OutInst, RISCV_C_LBU);
800
      // Operand: rd
801
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
802
      // Operand: rs1
803
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
804
      // Operand: imm
805
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
806
807
      return true;
808
    } // if
809
      break;
810
    } // case LBU
811
    case RISCV_LD: {
812
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
813
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
814
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
815
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
816
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
817
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
818
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 6)) {
819
      // c.ld $rd, ${imm}(${rs1})
820
      MCInst_setOpcode(OutInst, RISCV_C_LD);
821
      // Operand: rd
822
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
823
      // Operand: rs1
824
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
825
      // Operand: imm
826
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
827
828
      return true;
829
    } // if
830
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
831
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
832
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
833
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
834
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
835
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
836
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 7)) {
837
      // c.ldsp $rd, ${imm}(${rs1})
838
      MCInst_setOpcode(OutInst, RISCV_C_LDSP);
839
      // Operand: rd
840
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
841
      // Operand: rs1
842
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
843
      // Operand: imm
844
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
845
846
      return true;
847
    } // if
848
      break;
849
    } // case LD
850
    case RISCV_LH: {
851
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
852
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
853
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
854
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
855
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
856
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 12)) {
857
      // c.lh $rd, ${imm}(${rs1})
858
      MCInst_setOpcode(OutInst, RISCV_C_LH);
859
      // Operand: rd
860
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
861
      // Operand: rs1
862
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
863
      // Operand: imm
864
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
865
866
      return true;
867
    } // if
868
      break;
869
    } // case LH
870
    case RISCV_LHU: {
871
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
872
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
873
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
874
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
875
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
876
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 12)) {
877
      // c.lhu  $rd, ${imm}(${rs1})
878
      MCInst_setOpcode(OutInst, RISCV_C_LHU);
879
      // Operand: rd
880
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
881
      // Operand: rs1
882
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
883
      // Operand: imm
884
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
885
886
      return true;
887
    } // if
888
      break;
889
    } // case LHU
890
    case RISCV_LUI: {
891
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
892
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
893
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0X2RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
894
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 1), 13)) {
895
      // c.lui  $rd, $imm
896
      MCInst_setOpcode(OutInst, RISCV_C_LUI);
897
      // Operand: rd
898
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
899
      // Operand: imm
900
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
901
902
      return true;
903
    } // if
904
      break;
905
    } // case LUI
906
    case RISCV_LW: {
907
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
908
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
909
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
910
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
911
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
912
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 8)) {
913
      // c.lw $rd, ${imm}(${rs1})
914
      MCInst_setOpcode(OutInst, RISCV_C_LW);
915
      // Operand: rd
916
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
917
      // Operand: rs1
918
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
919
      // Operand: imm
920
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
921
922
      return true;
923
    } // if
924
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
925
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
926
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
927
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
928
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
929
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 9)) {
930
      // c.lwsp $rd, ${imm}(${rs1})
931
      MCInst_setOpcode(OutInst, RISCV_C_LWSP);
932
      // Operand: rd
933
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
934
      // Operand: rs1
935
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
936
      // Operand: imm
937
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
938
939
      return true;
940
    } // if
941
      break;
942
    } // case LW
943
    case RISCV_MUL: {
944
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
945
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtM) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZmmul)) &&
946
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
947
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
948
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
949
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
950
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
951
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
952
      // c.mul  $rd, $rs2
953
      MCInst_setOpcode(OutInst, RISCV_C_MUL);
954
      // Operand: rd_wb
955
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
956
      // Operand: rd
957
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
958
      // Operand: rs2
959
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
960
961
      return true;
962
    } // if
963
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
964
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtM) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZmmul)) &&
965
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
966
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
967
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
968
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2)))) &&
969
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
970
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
971
      // c.mul  $rd, $rs2
972
      MCInst_setOpcode(OutInst, RISCV_C_MUL);
973
      // Operand: rd_wb
974
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
975
      // Operand: rd
976
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
977
      // Operand: rs2
978
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
979
980
      return true;
981
    } // if
982
      break;
983
    } // case MUL
984
    case RISCV_OR: {
985
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
986
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
987
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
988
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
989
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
990
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
991
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
992
      // c.or $rd, $rs2
993
      MCInst_setOpcode(OutInst, RISCV_C_OR);
994
      // Operand: rd_wb
995
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
996
      // Operand: rd
997
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
998
      // Operand: rs2
999
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1000
1001
      return true;
1002
    } // if
1003
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1004
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1005
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1006
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
1007
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2)))) &&
1008
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1009
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
1010
      // c.or $rd, $rs2
1011
      MCInst_setOpcode(OutInst, RISCV_C_OR);
1012
      // Operand: rd_wb
1013
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1014
      // Operand: rd
1015
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1016
      // Operand: rs2
1017
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1018
1019
      return true;
1020
    } // if
1021
      break;
1022
    } // case OR
1023
    case RISCV_SB: {
1024
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
1025
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1026
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1027
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1028
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1029
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 11)) {
1030
      // c.sb $rs2, ${imm}(${rs1})
1031
      MCInst_setOpcode(OutInst, RISCV_C_SB);
1032
      // Operand: rs2
1033
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1034
      // Operand: rs1
1035
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1036
      // Operand: imm
1037
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1038
1039
      return true;
1040
    } // if
1041
      break;
1042
    } // case SB
1043
    case RISCV_SD: {
1044
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
1045
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1046
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1047
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1048
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1049
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1050
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 6)) {
1051
      // c.sd $rs2, ${imm}(${rs1})
1052
      MCInst_setOpcode(OutInst, RISCV_C_SD);
1053
      // Operand: rs2
1054
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1055
      // Operand: rs1
1056
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1057
      // Operand: imm
1058
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1059
1060
      return true;
1061
    } // if
1062
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
1063
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1064
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1065
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1066
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1067
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1068
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 7)) {
1069
      // c.sdsp $rs2, ${imm}(${rs1})
1070
      MCInst_setOpcode(OutInst, RISCV_C_SDSP);
1071
      // Operand: rs2
1072
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1073
      // Operand: rs1
1074
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1075
      // Operand: imm
1076
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1077
1078
      return true;
1079
    } // if
1080
      break;
1081
    } // case SD
1082
    case RISCV_SEXT_B: {
1083
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZbb) &&
1084
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
1085
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1086
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1087
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1088
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
1089
      // c.sext.b $rd
1090
      MCInst_setOpcode(OutInst, RISCV_C_SEXT_B);
1091
      // Operand: rd_wb
1092
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1093
      // Operand: rd
1094
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1095
1096
      return true;
1097
    } // if
1098
      break;
1099
    } // case SEXT_B
1100
    case RISCV_SEXT_H: {
1101
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZbb) &&
1102
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
1103
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1104
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1105
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1106
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
1107
      // c.sext.h $rd
1108
      MCInst_setOpcode(OutInst, RISCV_C_SEXT_H);
1109
      // Operand: rd_wb
1110
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1111
      // Operand: rd
1112
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1113
1114
      return true;
1115
    } // if
1116
      break;
1117
    } // case SEXT_H
1118
    case RISCV_SH: {
1119
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
1120
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1121
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1122
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1123
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1124
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 12)) {
1125
      // c.sh $rs2, ${imm}(${rs1})
1126
      MCInst_setOpcode(OutInst, RISCV_C_SH);
1127
      // Operand: rs2
1128
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1129
      // Operand: rs1
1130
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1131
      // Operand: imm
1132
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1133
1134
      return true;
1135
    } // if
1136
      break;
1137
    } // case SH
1138
    case RISCV_SLLI: {
1139
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1140
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1141
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1142
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1143
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1144
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 14)) {
1145
      // c.slli $rd, $imm
1146
      MCInst_setOpcode(OutInst, RISCV_C_SLLI);
1147
      // Operand: rd_wb
1148
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1149
      // Operand: rd
1150
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1151
      // Operand: imm
1152
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1153
1154
      return true;
1155
    } // if
1156
      break;
1157
    } // case SLLI
1158
    case RISCV_SRAI: {
1159
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1160
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1161
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1162
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1163
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1164
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 14)) {
1165
      // c.srai $rs1, $imm
1166
      MCInst_setOpcode(OutInst, RISCV_C_SRAI);
1167
      // Operand: rs1_wb
1168
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1169
      // Operand: rs1
1170
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1171
      // Operand: imm
1172
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1173
1174
      return true;
1175
    } // if
1176
      break;
1177
    } // case SRAI
1178
    case RISCV_SRLI: {
1179
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1180
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1181
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1182
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1183
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1184
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 14)) {
1185
      // c.srli $rs1, $imm
1186
      MCInst_setOpcode(OutInst, RISCV_C_SRLI);
1187
      // Operand: rs1_wb
1188
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1189
      // Operand: rs1
1190
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1191
      // Operand: imm
1192
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1193
1194
      return true;
1195
    } // if
1196
      break;
1197
    } // case SRLI
1198
    case RISCV_SSPOPCHK: {
1199
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcmop) &&
1200
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZicfiss) &&
1201
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1202
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X5)) {
1203
      // c.sspopchk $rs1
1204
      MCInst_setOpcode(OutInst, RISCV_C_SSPOPCHK);
1205
      // Operand: rs1
1206
      MCOperand_CreateReg0(OutInst, RISCV_X5);
1207
1208
      return true;
1209
    } // if
1210
      break;
1211
    } // case SSPOPCHK
1212
    case RISCV_SSPUSH: {
1213
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcmop) &&
1214
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZicfiss) &&
1215
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1216
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1)) {
1217
      // c.sspush $rs1
1218
      MCInst_setOpcode(OutInst, RISCV_C_SSPUSH);
1219
      // Operand: rs1
1220
      MCOperand_CreateReg0(OutInst, RISCV_X1);
1221
1222
      return true;
1223
    } // if
1224
      break;
1225
    } // case SSPUSH
1226
    case RISCV_SUB: {
1227
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1228
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1229
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1230
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1231
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1232
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
1233
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
1234
      // c.sub  $rd, $rs2
1235
      MCInst_setOpcode(OutInst, RISCV_C_SUB);
1236
      // Operand: rd_wb
1237
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1238
      // Operand: rd
1239
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1240
      // Operand: rs2
1241
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1242
1243
      return true;
1244
    } // if
1245
      break;
1246
    } // case SUB
1247
    case RISCV_SUBW: {
1248
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
1249
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1250
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1251
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1252
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1253
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1254
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
1255
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
1256
      // c.subw $rd, $rs2
1257
      MCInst_setOpcode(OutInst, RISCV_C_SUBW);
1258
      // Operand: rd_wb
1259
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1260
      // Operand: rd
1261
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1262
      // Operand: rs2
1263
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1264
1265
      return true;
1266
    } // if
1267
      break;
1268
    } // case SUBW
1269
    case RISCV_SW: {
1270
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1271
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1272
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1273
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1274
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1275
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 8)) {
1276
      // c.sw $rs2, ${imm}(${rs1})
1277
      MCInst_setOpcode(OutInst, RISCV_C_SW);
1278
      // Operand: rs2
1279
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1280
      // Operand: rs1
1281
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1282
      // Operand: imm
1283
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1284
1285
      return true;
1286
    } // if
1287
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1288
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1289
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1290
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1291
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1292
      RISCVValidateMCOperandForCompress(MI,MCInst_getOperand(MI, 2), 9)) {
1293
      // c.swsp $rs2, ${imm}(${rs1})
1294
      MCInst_setOpcode(OutInst, RISCV_C_SWSP);
1295
      // Operand: rs2
1296
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1297
      // Operand: rs1
1298
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1299
      // Operand: imm
1300
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1301
1302
      return true;
1303
    } // if
1304
      break;
1305
    } // case SW
1306
    case RISCV_UNIMP: {
1307
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca))) {
1308
      // c.unimp
1309
      MCInst_setOpcode(OutInst, RISCV_C_UNIMP);
1310
1311
      return true;
1312
    } // if
1313
      break;
1314
    } // case UNIMP
1315
    case RISCV_XOR: {
1316
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1317
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1318
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1319
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1320
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1321
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
1322
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
1323
      // c.xor  $rd, $rs2
1324
      MCInst_setOpcode(OutInst, RISCV_C_XOR);
1325
      // Operand: rd_wb
1326
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1327
      // Operand: rd
1328
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1329
      // Operand: rs2
1330
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1331
1332
      return true;
1333
    } // if
1334
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1335
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1336
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1337
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
1338
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2)))) &&
1339
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1340
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
1341
      // c.xor  $rd, $rs2
1342
      MCInst_setOpcode(OutInst, RISCV_C_XOR);
1343
      // Operand: rd_wb
1344
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1345
      // Operand: rd
1346
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1347
      // Operand: rs2
1348
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1349
1350
      return true;
1351
    } // if
1352
      break;
1353
    } // case XOR
1354
    case RISCV_XORI: {
1355
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
1356
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1357
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1358
      (MCOperand_isImm(MCInst_getOperand(MI, 2))) &&
1359
      (MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1) &&
1360
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1361
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
1362
      // c.not  $rd
1363
      MCInst_setOpcode(OutInst, RISCV_C_NOT);
1364
      // Operand: rd_wb
1365
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1366
      // Operand: rd
1367
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1368
1369
      return true;
1370
    } // if
1371
      break;
1372
    } // case XORI
1373
    case RISCV_ZEXT_H_RV32: {
1374
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZbb) &&
1375
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
1376
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1377
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1378
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1379
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
1380
      // c.zext.h $rd
1381
      MCInst_setOpcode(OutInst, RISCV_C_ZEXT_H);
1382
      // Operand: rd_wb
1383
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1384
      // Operand: rd
1385
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1386
1387
      return true;
1388
    } // if
1389
      break;
1390
    } // case ZEXT_H_RV32
1391
    case RISCV_ZEXT_H_RV64: {
1392
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZbb) &&
1393
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
1394
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1395
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
1396
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1397
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
1398
      // c.zext.h $rd
1399
      MCInst_setOpcode(OutInst, RISCV_C_ZEXT_H);
1400
      // Operand: rd_wb
1401
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1402
      // Operand: rd
1403
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1404
1405
      return true;
1406
    } // if
1407
1408
    } // case ZEXT_H_RV64
1409
  } // switch
1410
  return false;
1411
}
1412
1413
#endif //GEN_COMPRESS_INSTR
1414
1415
#ifdef GEN_UNCOMPRESS_INSTR
1416
#undef GEN_UNCOMPRESS_INSTR
1417
1418
static bool RISCVValidateMCOperandForUncompress(MCInst *MI,MCOperand *MCOp,
1419
72.9k
                  unsigned PredicateIndex) {
1420
72.9k
  switch (PredicateIndex) {
1421
0
  default:
1422
0
    CS_ASSERT_RET_VAL(0,false);
1423
0
   return false;
1424
0
    break;
1425
54.5k
  case 1: {
1426
  // simm12
1427
1428
54.5k
    int64_t Imm;
1429
54.5k
    if ((Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
1430
54.5k
      return isIntN(12, Imm);
1431
0
    return MCOperand_isExpr(MCOp);
1432
1433
54.5k
  }
1434
6.80k
  case 2: {
1435
  // simm13_lsb0
1436
1437
6.80k
    int64_t Imm;
1438
6.80k
    if ((Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
1439
6.80k
      return isShiftedIntN(12, 1, Imm);
1440
0
    return MCOperand_isExpr(MCOp);
1441
1442
6.80k
  }
1443
2.36k
  case 3: {
1444
  // simm21_lsb0_jal
1445
1446
2.36k
    int64_t Imm;
1447
2.36k
    if ((Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
1448
2.36k
      return isShiftedIntN(20, 1, Imm);
1449
0
    return MCOperand_isExpr(MCOp);
1450
1451
2.36k
  }
1452
3.16k
  case 4: {
1453
  // uimm20_lui
1454
1455
3.16k
    int64_t Imm;
1456
3.16k
    if ((Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
1457
3.16k
      return isUIntN(20, Imm);
1458
0
    return MCOperand_isExpr(MCOp);
1459
1460
3.16k
  }
1461
6.14k
  case 5: {
1462
  // uimmlog2xlen
1463
1464
6.14k
    int64_t Imm;
1465
6.14k
    if (!(Imm = MCOperand_getImm(MCOp), MCOperand_isImm(MCOp)))
1466
0
      return false;
1467
6.14k
    if (RISCV_getFeatureBits(MI->csh->mode,RISCV_Feature64Bit))
1468
4.04k
      return isUIntN(6, Imm);
1469
2.10k
    return isUIntN(5, Imm);
1470
1471
6.14k
  }
1472
72.9k
  }
1473
72.9k
}
1474
1475
static bool uncompressInst(MCInst *OutInst,
1476
143k
                           MCInst *MI) {
1477
143k
  switch (MCInst_getOpcode(MI)) {
1478
53.0k
    default: return false;
1479
1.77k
    case RISCV_C_ADD: {
1480
1.77k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1481
1.77k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1482
1.77k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1483
1.77k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1484
1.77k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1485
1.77k
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
1486
1.77k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
1487
      // add  $rd, $rs1, $rs2
1488
1.77k
      MCInst_setOpcode(OutInst, RISCV_ADD);
1489
      // Operand: rd
1490
1.77k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1491
      // Operand: rs1
1492
1.77k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1493
      // Operand: rs2
1494
1.77k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1495
1496
1.77k
      return true;
1497
1.77k
    } // if
1498
0
      break;
1499
1.77k
    } // case C_ADD
1500
5.53k
    case RISCV_C_ADDI: {
1501
5.53k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1502
5.53k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1503
5.53k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1504
5.53k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1505
5.53k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1506
5.53k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1507
      // addi $rd, $rs1, $imm12
1508
5.53k
      MCInst_setOpcode(OutInst, RISCV_ADDI);
1509
      // Operand: rd
1510
5.53k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1511
      // Operand: rs1
1512
5.53k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1513
      // Operand: imm12
1514
5.53k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1515
1516
5.53k
      return true;
1517
5.53k
    } // if
1518
0
      break;
1519
5.53k
    } // case C_ADDI
1520
968
    case RISCV_C_ADDI16SP: {
1521
968
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1522
968
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1523
968
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X2) &&
1524
968
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1525
968
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X2) &&
1526
968
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1527
      // addi $rd, $rs1, $imm12
1528
968
      MCInst_setOpcode(OutInst, RISCV_ADDI);
1529
      // Operand: rd
1530
968
      MCOperand_CreateReg0(OutInst, RISCV_X2);
1531
      // Operand: rs1
1532
968
      MCOperand_CreateReg0(OutInst, RISCV_X2);
1533
      // Operand: imm12
1534
968
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1535
1536
968
      return true;
1537
968
    } // if
1538
0
      break;
1539
968
    } // case C_ADDI16SP
1540
8.86k
    case RISCV_C_ADDI4SPN: {
1541
8.86k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1542
8.86k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1543
8.86k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1544
8.86k
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1545
8.86k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1546
8.86k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1547
      // addi $rd, $rs1, $imm12
1548
8.86k
      MCInst_setOpcode(OutInst, RISCV_ADDI);
1549
      // Operand: rd
1550
8.86k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1551
      // Operand: rs1
1552
8.86k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1553
      // Operand: imm12
1554
8.86k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1555
1556
8.86k
      return true;
1557
8.86k
    } // if
1558
0
      break;
1559
8.86k
    } // case C_ADDI4SPN
1560
1.62k
    case RISCV_C_ADDIW: {
1561
1.62k
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
1562
1.62k
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1563
1.62k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1564
1.62k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1565
1.62k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1566
1.62k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1567
1.62k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1568
      // addiw  $rd, $rs1, $imm12
1569
1.62k
      MCInst_setOpcode(OutInst, RISCV_ADDIW);
1570
      // Operand: rd
1571
1.62k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1572
      // Operand: rs1
1573
1.62k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1574
      // Operand: imm12
1575
1.62k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1576
1577
1.62k
      return true;
1578
1.62k
    } // if
1579
0
      break;
1580
1.62k
    } // case C_ADDIW
1581
218
    case RISCV_C_ADDW: {
1582
218
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
1583
218
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1584
218
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1585
218
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1586
218
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1587
218
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1588
218
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
1589
218
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
1590
      // addw $rd, $rs1, $rs2
1591
218
      MCInst_setOpcode(OutInst, RISCV_ADDW);
1592
      // Operand: rd
1593
218
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1594
      // Operand: rs1
1595
218
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1596
      // Operand: rs2
1597
218
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1598
1599
218
      return true;
1600
218
    } // if
1601
0
      break;
1602
218
    } // case C_ADDW
1603
152
    case RISCV_C_AND: {
1604
152
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1605
152
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1606
152
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1607
152
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1608
152
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1609
152
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
1610
152
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
1611
      // and  $rd, $rs1, $rs2
1612
152
      MCInst_setOpcode(OutInst, RISCV_AND);
1613
      // Operand: rd
1614
152
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1615
      // Operand: rs1
1616
152
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1617
      // Operand: rs2
1618
152
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1619
1620
152
      return true;
1621
152
    } // if
1622
0
      break;
1623
152
    } // case C_AND
1624
1.08k
    case RISCV_C_ANDI: {
1625
1.08k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1626
1.08k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1627
1.08k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1628
1.08k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1629
1.08k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1630
1.08k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1631
      // andi $rd, $rs1, $imm12
1632
1.08k
      MCInst_setOpcode(OutInst, RISCV_ANDI);
1633
      // Operand: rd
1634
1.08k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1635
      // Operand: rs1
1636
1.08k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1637
      // Operand: imm12
1638
1.08k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1639
1640
1.08k
      return true;
1641
1.08k
    } // if
1642
0
      break;
1643
1.08k
    } // case C_ANDI
1644
2.65k
    case RISCV_C_BEQZ: {
1645
2.65k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1646
2.65k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1647
2.65k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1648
2.65k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 1), 2)) {
1649
      // beq  $rs1, $rs2, $imm12
1650
2.65k
      MCInst_setOpcode(OutInst, RISCV_BEQ);
1651
      // Operand: rs1
1652
2.65k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1653
      // Operand: rs2
1654
2.65k
      MCOperand_CreateReg0(OutInst, RISCV_X0);
1655
      // Operand: imm12
1656
2.65k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1657
1658
2.65k
      return true;
1659
2.65k
    } // if
1660
0
      break;
1661
2.65k
    } // case C_BEQZ
1662
4.14k
    case RISCV_C_BNEZ: {
1663
4.14k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1664
4.14k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1665
4.14k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1666
4.14k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 1), 2)) {
1667
      // bne  $rs1, $rs2, $imm12
1668
4.14k
      MCInst_setOpcode(OutInst, RISCV_BNE);
1669
      // Operand: rs1
1670
4.14k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1671
      // Operand: rs2
1672
4.14k
      MCOperand_CreateReg0(OutInst, RISCV_X0);
1673
      // Operand: imm12
1674
4.14k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1675
1676
4.14k
      return true;
1677
4.14k
    } // if
1678
0
      break;
1679
4.14k
    } // case C_BNEZ
1680
204
    case RISCV_C_EBREAK: {
1681
204
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca))) {
1682
      // ebreak
1683
204
      MCInst_setOpcode(OutInst, RISCV_EBREAK);
1684
1685
204
      return true;
1686
204
    } // if
1687
0
      break;
1688
204
    } // case C_EBREAK
1689
0
    case RISCV_C_FLD: {
1690
0
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtD) &&
1691
0
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcd)) &&
1692
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1693
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR64RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1694
0
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1695
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1696
0
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1697
      // fld  $rd, ${imm12}(${rs1})
1698
0
      MCInst_setOpcode(OutInst, RISCV_FLD);
1699
      // Operand: rd
1700
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1701
      // Operand: rs1
1702
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1703
      // Operand: imm12
1704
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1705
1706
0
      return true;
1707
0
    } // if
1708
0
      break;
1709
0
    } // case C_FLD
1710
0
    case RISCV_C_FLDSP: {
1711
0
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtD) &&
1712
0
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcd)) &&
1713
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1714
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR64RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1715
0
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1716
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1717
0
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1718
      // fld  $rd, ${imm12}(${rs1})
1719
0
      MCInst_setOpcode(OutInst, RISCV_FLD);
1720
      // Operand: rd
1721
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1722
      // Operand: rs1
1723
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1724
      // Operand: imm12
1725
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1726
1727
0
      return true;
1728
0
    } // if
1729
0
      break;
1730
0
    } // case C_FLDSP
1731
0
    case RISCV_C_FLW: {
1732
0
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtF) &&
1733
0
      !RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
1734
0
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZce) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcf)) &&
1735
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1736
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR32RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1737
0
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1738
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1739
0
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1740
      // flw  $rd, ${imm12}(${rs1})
1741
0
      MCInst_setOpcode(OutInst, RISCV_FLW);
1742
      // Operand: rd
1743
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1744
      // Operand: rs1
1745
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1746
      // Operand: imm12
1747
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1748
1749
0
      return true;
1750
0
    } // if
1751
0
      break;
1752
0
    } // case C_FLW
1753
0
    case RISCV_C_FLWSP: {
1754
0
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtF) &&
1755
0
      !RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
1756
0
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZce) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcf)) &&
1757
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1758
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR32RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1759
0
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1760
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1761
0
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1762
      // flw  $rd, ${imm12}(${rs1})
1763
0
      MCInst_setOpcode(OutInst, RISCV_FLW);
1764
      // Operand: rd
1765
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1766
      // Operand: rs1
1767
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1768
      // Operand: imm12
1769
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1770
1771
0
      return true;
1772
0
    } // if
1773
0
      break;
1774
0
    } // case C_FLWSP
1775
0
    case RISCV_C_FSD: {
1776
0
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtD) &&
1777
0
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcd)) &&
1778
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1779
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR64RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1780
0
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1781
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1782
0
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1783
      // fsd  $rs2, ${imm12}(${rs1})
1784
0
      MCInst_setOpcode(OutInst, RISCV_FSD);
1785
      // Operand: rs2
1786
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1787
      // Operand: rs1
1788
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1789
      // Operand: imm12
1790
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1791
1792
0
      return true;
1793
0
    } // if
1794
0
      break;
1795
0
    } // case C_FSD
1796
0
    case RISCV_C_FSDSP: {
1797
0
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtD) &&
1798
0
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcd)) &&
1799
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1800
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR64RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1801
0
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1802
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1803
0
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1804
      // fsd  $rs2, ${imm12}(${rs1})
1805
0
      MCInst_setOpcode(OutInst, RISCV_FSD);
1806
      // Operand: rs2
1807
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1808
      // Operand: rs1
1809
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1810
      // Operand: imm12
1811
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1812
1813
0
      return true;
1814
0
    } // if
1815
0
      break;
1816
0
    } // case C_FSDSP
1817
0
    case RISCV_C_FSW: {
1818
0
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtF) &&
1819
0
      !RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
1820
0
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZce) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcf)) &&
1821
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1822
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR32RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1823
0
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1824
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1825
0
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1826
      // fsw  $rs2, ${imm12}(${rs1})
1827
0
      MCInst_setOpcode(OutInst, RISCV_FSW);
1828
      // Operand: rs2
1829
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1830
      // Operand: rs1
1831
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1832
      // Operand: imm12
1833
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1834
1835
0
      return true;
1836
0
    } // if
1837
0
      break;
1838
0
    } // case C_FSW
1839
0
    case RISCV_C_FSWSP: {
1840
0
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtF) &&
1841
0
      !RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
1842
0
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZce) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcf)) &&
1843
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1844
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR32RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1845
0
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1846
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1847
0
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1848
      // fsw  $rs2, ${imm12}(${rs1})
1849
0
      MCInst_setOpcode(OutInst, RISCV_FSW);
1850
      // Operand: rs2
1851
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1852
      // Operand: rs1
1853
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1854
      // Operand: imm12
1855
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1856
1857
0
      return true;
1858
0
    } // if
1859
0
      break;
1860
0
    } // case C_FSWSP
1861
914
    case RISCV_C_J: {
1862
914
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1863
914
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 0), 3)) {
1864
      // jal  $rd, $imm20
1865
914
      MCInst_setOpcode(OutInst, RISCV_JAL);
1866
      // Operand: rd
1867
914
      MCOperand_CreateReg0(OutInst, RISCV_X0);
1868
      // Operand: imm20
1869
914
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1870
1871
914
      return true;
1872
914
    } // if
1873
0
      break;
1874
914
    } // case C_J
1875
1.45k
    case RISCV_C_JAL: {
1876
1.45k
    if (!RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
1877
1.45k
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1878
1.45k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 0), 3)) {
1879
      // jal  $rd, $imm20
1880
1.45k
      MCInst_setOpcode(OutInst, RISCV_JAL);
1881
      // Operand: rd
1882
1.45k
      MCOperand_CreateReg0(OutInst, RISCV_X1);
1883
      // Operand: imm20
1884
1.45k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1885
1886
1.45k
      return true;
1887
1.45k
    } // if
1888
0
      break;
1889
1.45k
    } // case C_JAL
1890
224
    case RISCV_C_JALR: {
1891
224
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1892
224
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1893
224
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1894
224
      RISCVValidateMCOperandForUncompress(MI,MCOperand_CreateImm1(MI, 0), 1)) {
1895
      // jalr $rd, ${imm12}(${rs1})
1896
224
      MCInst_setOpcode(OutInst, RISCV_JALR);
1897
      // Operand: rd
1898
224
      MCOperand_CreateReg0(OutInst, RISCV_X1);
1899
      // Operand: rs1
1900
224
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1901
      // Operand: imm12
1902
224
      MCOperand_CreateImm0(OutInst, 0);
1903
1904
224
      return true;
1905
224
    } // if
1906
0
      break;
1907
224
    } // case C_JALR
1908
1.42k
    case RISCV_C_JR: {
1909
1.42k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1910
1.42k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1911
1.42k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1912
1.42k
      RISCVValidateMCOperandForUncompress(MI,MCOperand_CreateImm1(MI, 0), 1)) {
1913
      // jalr $rd, ${imm12}(${rs1})
1914
1.42k
      MCInst_setOpcode(OutInst, RISCV_JALR);
1915
      // Operand: rd
1916
1.42k
      MCOperand_CreateReg0(OutInst, RISCV_X0);
1917
      // Operand: rs1
1918
1.42k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1919
      // Operand: imm12
1920
1.42k
      MCOperand_CreateImm0(OutInst, 0);
1921
1922
1.42k
      return true;
1923
1.42k
    } // if
1924
0
      break;
1925
1.42k
    } // case C_JR
1926
954
    case RISCV_C_LBU: {
1927
954
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
1928
954
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1929
954
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1930
954
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1931
954
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1932
954
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1933
      // lbu  $rd, ${imm12}(${rs1})
1934
954
      MCInst_setOpcode(OutInst, RISCV_LBU);
1935
      // Operand: rd
1936
954
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1937
      // Operand: rs1
1938
954
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1939
      // Operand: imm12
1940
954
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1941
1942
954
      return true;
1943
954
    } // if
1944
0
      break;
1945
954
    } // case C_LBU
1946
4.66k
    case RISCV_C_LD: {
1947
4.66k
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
1948
4.66k
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1949
4.66k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1950
4.66k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1951
4.66k
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1952
4.66k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1953
4.66k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1954
      // ld $rd, ${imm12}(${rs1})
1955
4.66k
      MCInst_setOpcode(OutInst, RISCV_LD);
1956
      // Operand: rd
1957
4.66k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1958
      // Operand: rs1
1959
4.66k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1960
      // Operand: imm12
1961
4.66k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1962
1963
4.66k
      return true;
1964
4.66k
    } // if
1965
0
      break;
1966
4.66k
    } // case C_LD
1967
3.90k
    case RISCV_C_LDSP: {
1968
3.90k
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
1969
3.90k
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
1970
3.90k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1971
3.90k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1972
3.90k
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1973
3.90k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1974
3.90k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1975
      // ld $rd, ${imm12}(${rs1})
1976
3.90k
      MCInst_setOpcode(OutInst, RISCV_LD);
1977
      // Operand: rd
1978
3.90k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1979
      // Operand: rs1
1980
3.90k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
1981
      // Operand: imm12
1982
3.90k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
1983
1984
3.90k
      return true;
1985
3.90k
    } // if
1986
0
      break;
1987
3.90k
    } // case C_LDSP
1988
372
    case RISCV_C_LH: {
1989
372
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
1990
372
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
1991
372
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
1992
372
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
1993
372
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
1994
372
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
1995
      // lh $rd, ${imm12}(${rs1})
1996
372
      MCInst_setOpcode(OutInst, RISCV_LH);
1997
      // Operand: rd
1998
372
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
1999
      // Operand: rs1
2000
372
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
2001
      // Operand: imm12
2002
372
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2003
2004
372
      return true;
2005
372
    } // if
2006
0
      break;
2007
372
    } // case C_LH
2008
454
    case RISCV_C_LHU: {
2009
454
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
2010
454
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2011
454
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2012
454
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2013
454
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2014
454
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
2015
      // lhu  $rd, ${imm12}(${rs1})
2016
454
      MCInst_setOpcode(OutInst, RISCV_LHU);
2017
      // Operand: rd
2018
454
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2019
      // Operand: rs1
2020
454
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
2021
      // Operand: imm12
2022
454
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2023
2024
454
      return true;
2025
454
    } // if
2026
0
      break;
2027
454
    } // case C_LHU
2028
3.46k
    case RISCV_C_LI: {
2029
3.46k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2030
3.46k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2031
3.46k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2032
3.46k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 1), 1)) {
2033
      // addi $rd, $rs1, $imm12
2034
3.46k
      MCInst_setOpcode(OutInst, RISCV_ADDI);
2035
      // Operand: rd
2036
3.46k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2037
      // Operand: rs1
2038
3.46k
      MCOperand_CreateReg0(OutInst, RISCV_X0);
2039
      // Operand: imm12
2040
3.46k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
2041
2042
3.46k
      return true;
2043
3.46k
    } // if
2044
0
      break;
2045
3.46k
    } // case C_LI
2046
3.16k
    case RISCV_C_LUI: {
2047
3.16k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2048
3.16k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2049
3.16k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2050
3.16k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 1), 4)) {
2051
      // lui  $rd, $imm20
2052
3.16k
      MCInst_setOpcode(OutInst, RISCV_LUI);
2053
      // Operand: rd
2054
3.16k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2055
      // Operand: imm20
2056
3.16k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
2057
2058
3.16k
      return true;
2059
3.16k
    } // if
2060
0
      break;
2061
3.16k
    } // case C_LUI
2062
4.62k
    case RISCV_C_LW: {
2063
4.62k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2064
4.62k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2065
4.62k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2066
4.62k
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2067
4.62k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2068
4.62k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
2069
      // lw $rd, ${imm12}(${rs1})
2070
4.62k
      MCInst_setOpcode(OutInst, RISCV_LW);
2071
      // Operand: rd
2072
4.62k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2073
      // Operand: rs1
2074
4.62k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
2075
      // Operand: imm12
2076
4.62k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2077
2078
4.62k
      return true;
2079
4.62k
    } // if
2080
0
      break;
2081
4.62k
    } // case C_LW
2082
2.90k
    case RISCV_C_LWSP: {
2083
2.90k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2084
2.90k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2085
2.90k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2086
2.90k
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2087
2.90k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2088
2.90k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
2089
      // lw $rd, ${imm12}(${rs1})
2090
2.90k
      MCInst_setOpcode(OutInst, RISCV_LW);
2091
      // Operand: rd
2092
2.90k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2093
      // Operand: rs1
2094
2.90k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
2095
      // Operand: imm12
2096
2.90k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2097
2098
2.90k
      return true;
2099
2.90k
    } // if
2100
0
      break;
2101
2.90k
    } // case C_LWSP
2102
542
    case RISCV_C_MUL: {
2103
542
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
2104
542
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtM) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZmmul)) &&
2105
542
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2106
542
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2107
542
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2108
542
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2109
542
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
2110
542
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
2111
      // mul  $rd, $rs1, $rs2
2112
542
      MCInst_setOpcode(OutInst, RISCV_MUL);
2113
      // Operand: rd
2114
542
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2115
      // Operand: rs1
2116
542
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2117
      // Operand: rs2
2118
542
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2119
2120
542
      return true;
2121
542
    } // if
2122
0
      break;
2123
542
    } // case C_MUL
2124
1.99k
    case RISCV_C_MV: {
2125
1.99k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2126
1.99k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2127
1.99k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2128
1.99k
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2129
1.99k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2130
1.99k
      RISCVValidateMCOperandForUncompress(MI,MCOperand_CreateImm1(MI, 0), 1)) {
2131
      // addi $rd, $rs1, $imm12
2132
1.99k
      MCInst_setOpcode(OutInst, RISCV_ADDI);
2133
      // Operand: rd
2134
1.99k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2135
      // Operand: rs1
2136
1.99k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
2137
      // Operand: imm12
2138
1.99k
      MCOperand_CreateImm0(OutInst, 0);
2139
2140
1.99k
      return true;
2141
1.99k
    } // if
2142
0
      break;
2143
1.99k
    } // case C_MV
2144
676
    case RISCV_C_NOP: {
2145
676
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2146
676
      RISCVValidateMCOperandForUncompress(MI,MCOperand_CreateImm1(MI, 0), 1)) {
2147
      // addi $rd, $rs1, $imm12
2148
676
      MCInst_setOpcode(OutInst, RISCV_ADDI);
2149
      // Operand: rd
2150
676
      MCOperand_CreateReg0(OutInst, RISCV_X0);
2151
      // Operand: rs1
2152
676
      MCOperand_CreateReg0(OutInst, RISCV_X0);
2153
      // Operand: imm12
2154
676
      MCOperand_CreateImm0(OutInst, 0);
2155
2156
676
      return true;
2157
676
    } // if
2158
0
      break;
2159
676
    } // case C_NOP
2160
168
    case RISCV_C_NOT: {
2161
168
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
2162
168
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2163
168
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2164
168
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2165
168
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2166
168
      RISCVValidateMCOperandForUncompress(MI,MCOperand_CreateImm1(MI, -1), 1)) {
2167
      // xori $rd, $rs1, $imm12
2168
168
      MCInst_setOpcode(OutInst, RISCV_XORI);
2169
      // Operand: rd
2170
168
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2171
      // Operand: rs1
2172
168
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2173
      // Operand: imm12
2174
168
      MCOperand_CreateImm0(OutInst, -1);
2175
2176
168
      return true;
2177
168
    } // if
2178
0
      break;
2179
168
    } // case C_NOT
2180
328
    case RISCV_C_OR: {
2181
328
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2182
328
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2183
328
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2184
328
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2185
328
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2186
328
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
2187
328
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
2188
      // or $rd, $rs1, $rs2
2189
328
      MCInst_setOpcode(OutInst, RISCV_OR);
2190
      // Operand: rd
2191
328
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2192
      // Operand: rs1
2193
328
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2194
      // Operand: rs2
2195
328
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2196
2197
328
      return true;
2198
328
    } // if
2199
0
      break;
2200
328
    } // case C_OR
2201
720
    case RISCV_C_SB: {
2202
720
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
2203
720
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2204
720
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2205
720
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2206
720
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2207
720
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
2208
      // sb $rs2, ${imm12}(${rs1})
2209
720
      MCInst_setOpcode(OutInst, RISCV_SB);
2210
      // Operand: rs2
2211
720
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2212
      // Operand: rs1
2213
720
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
2214
      // Operand: imm12
2215
720
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2216
2217
720
      return true;
2218
720
    } // if
2219
0
      break;
2220
720
    } // case C_SB
2221
2.20k
    case RISCV_C_SD: {
2222
2.20k
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
2223
2.20k
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2224
2.20k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2225
2.20k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2226
2.20k
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2227
2.20k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2228
2.20k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
2229
      // sd $rs2, ${imm12}(${rs1})
2230
2.20k
      MCInst_setOpcode(OutInst, RISCV_SD);
2231
      // Operand: rs2
2232
2.20k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2233
      // Operand: rs1
2234
2.20k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
2235
      // Operand: imm12
2236
2.20k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2237
2238
2.20k
      return true;
2239
2.20k
    } // if
2240
0
      break;
2241
2.20k
    } // case C_SD
2242
1.85k
    case RISCV_C_SDSP: {
2243
1.85k
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
2244
1.85k
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2245
1.85k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2246
1.85k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2247
1.85k
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2248
1.85k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2249
1.85k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
2250
      // sd $rs2, ${imm12}(${rs1})
2251
1.85k
      MCInst_setOpcode(OutInst, RISCV_SD);
2252
      // Operand: rs2
2253
1.85k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2254
      // Operand: rs1
2255
1.85k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
2256
      // Operand: imm12
2257
1.85k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2258
2259
1.85k
      return true;
2260
1.85k
    } // if
2261
0
      break;
2262
1.85k
    } // case C_SDSP
2263
0
    case RISCV_C_SEXT_B: {
2264
0
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZbb) &&
2265
0
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
2266
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2267
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2268
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2269
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0))))) {
2270
      // sext.b $rd, $rs1
2271
0
      MCInst_setOpcode(OutInst, RISCV_SEXT_B);
2272
      // Operand: rd
2273
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2274
      // Operand: rs1
2275
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2276
2277
0
      return true;
2278
0
    } // if
2279
0
      break;
2280
0
    } // case C_SEXT_B
2281
0
    case RISCV_C_SEXT_H: {
2282
0
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZbb) &&
2283
0
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
2284
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2285
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2286
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2287
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0))))) {
2288
      // sext.h $rd, $rs1
2289
0
      MCInst_setOpcode(OutInst, RISCV_SEXT_H);
2290
      // Operand: rd
2291
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2292
      // Operand: rs1
2293
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2294
2295
0
      return true;
2296
0
    } // if
2297
0
      break;
2298
0
    } // case C_SEXT_H
2299
890
    case RISCV_C_SH: {
2300
890
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
2301
890
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2302
890
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2303
890
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2304
890
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2305
890
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
2306
      // sh $rs2, ${imm12}(${rs1})
2307
890
      MCInst_setOpcode(OutInst, RISCV_SH);
2308
      // Operand: rs2
2309
890
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2310
      // Operand: rs1
2311
890
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
2312
      // Operand: imm12
2313
890
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2314
2315
890
      return true;
2316
890
    } // if
2317
0
      break;
2318
890
    } // case C_SH
2319
3.89k
    case RISCV_C_SLLI: {
2320
3.89k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2321
3.89k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2322
3.89k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2323
3.89k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2324
3.89k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2325
3.89k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 5)) {
2326
      // slli $rd, $rs1, $shamt
2327
3.89k
      MCInst_setOpcode(OutInst, RISCV_SLLI);
2328
      // Operand: rd
2329
3.89k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2330
      // Operand: rs1
2331
3.89k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2332
      // Operand: shamt
2333
3.89k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2334
2335
3.89k
      return true;
2336
3.89k
    } // if
2337
0
      break;
2338
3.89k
    } // case C_SLLI
2339
846
    case RISCV_C_SRAI: {
2340
846
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2341
846
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2342
846
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2343
846
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2344
846
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2345
846
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 5)) {
2346
      // srai $rd, $rs1, $shamt
2347
846
      MCInst_setOpcode(OutInst, RISCV_SRAI);
2348
      // Operand: rd
2349
846
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2350
      // Operand: rs1
2351
846
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2352
      // Operand: shamt
2353
846
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2354
2355
846
      return true;
2356
846
    } // if
2357
0
      break;
2358
846
    } // case C_SRAI
2359
1.41k
    case RISCV_C_SRLI: {
2360
1.41k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2361
1.41k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2362
1.41k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2363
1.41k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2364
1.41k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2365
1.41k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 5)) {
2366
      // srli $rd, $rs1, $shamt
2367
1.41k
      MCInst_setOpcode(OutInst, RISCV_SRLI);
2368
      // Operand: rd
2369
1.41k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2370
      // Operand: rs1
2371
1.41k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2372
      // Operand: shamt
2373
1.41k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2374
2375
1.41k
      return true;
2376
1.41k
    } // if
2377
0
      break;
2378
1.41k
    } // case C_SRLI
2379
0
    case RISCV_C_SSPOPCHK: {
2380
0
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcmop) &&
2381
0
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZicfiss) &&
2382
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2383
0
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X5)) {
2384
      // sspopchk $rs1
2385
0
      MCInst_setOpcode(OutInst, RISCV_SSPOPCHK);
2386
      // Operand: rs1
2387
0
      MCOperand_CreateReg0(OutInst, RISCV_X5);
2388
2389
0
      return true;
2390
0
    } // if
2391
0
      break;
2392
0
    } // case C_SSPOPCHK
2393
0
    case RISCV_C_SSPUSH: {
2394
0
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcmop) &&
2395
0
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZicfiss) &&
2396
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2397
0
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1)) {
2398
      // sspush $rs2
2399
0
      MCInst_setOpcode(OutInst, RISCV_SSPUSH);
2400
      // Operand: rs2
2401
0
      MCOperand_CreateReg0(OutInst, RISCV_X1);
2402
2403
0
      return true;
2404
0
    } // if
2405
0
      break;
2406
0
    } // case C_SSPUSH
2407
452
    case RISCV_C_SUB: {
2408
452
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2409
452
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2410
452
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2411
452
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2412
452
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2413
452
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
2414
452
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
2415
      // sub  $rd, $rs1, $rs2
2416
452
      MCInst_setOpcode(OutInst, RISCV_SUB);
2417
      // Operand: rd
2418
452
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2419
      // Operand: rs1
2420
452
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2421
      // Operand: rs2
2422
452
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2423
2424
452
      return true;
2425
452
    } // if
2426
0
      break;
2427
452
    } // case C_SUB
2428
890
    case RISCV_C_SUBW: {
2429
890
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
2430
890
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2431
890
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2432
890
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2433
890
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2434
890
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2435
890
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
2436
890
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
2437
      // subw $rd, $rs1, $rs2
2438
890
      MCInst_setOpcode(OutInst, RISCV_SUBW);
2439
      // Operand: rd
2440
890
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2441
      // Operand: rs1
2442
890
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2443
      // Operand: rs2
2444
890
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2445
2446
890
      return true;
2447
890
    } // if
2448
0
      break;
2449
890
    } // case C_SUBW
2450
3.04k
    case RISCV_C_SW: {
2451
3.04k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2452
3.04k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2453
3.04k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2454
3.04k
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2455
3.04k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2456
3.04k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
2457
      // sw $rs2, ${imm12}(${rs1})
2458
3.04k
      MCInst_setOpcode(OutInst, RISCV_SW);
2459
      // Operand: rs2
2460
3.04k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2461
      // Operand: rs1
2462
3.04k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
2463
      // Operand: imm12
2464
3.04k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2465
2466
3.04k
      return true;
2467
3.04k
    } // if
2468
0
      break;
2469
3.04k
    } // case C_SW
2470
1.41k
    case RISCV_C_SWSP: {
2471
1.41k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2472
1.41k
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2473
1.41k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2474
1.41k
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2475
1.41k
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2476
1.41k
      RISCVValidateMCOperandForUncompress(MI,MCInst_getOperand(MI, 2), 1)) {
2477
      // sw $rs2, ${imm12}(${rs1})
2478
1.41k
      MCInst_setOpcode(OutInst, RISCV_SW);
2479
      // Operand: rs2
2480
1.41k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2481
      // Operand: rs1
2482
1.41k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 1));
2483
      // Operand: imm12
2484
1.41k
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2485
2486
1.41k
      return true;
2487
1.41k
    } // if
2488
0
      break;
2489
1.41k
    } // case C_SWSP
2490
13.1k
    case RISCV_C_UNIMP: {
2491
13.1k
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca))) {
2492
      // unimp
2493
13.1k
      MCInst_setOpcode(OutInst, RISCV_UNIMP);
2494
2495
13.1k
      return true;
2496
13.1k
    } // if
2497
0
      break;
2498
13.1k
    } // case C_UNIMP
2499
94
    case RISCV_C_XOR: {
2500
94
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2501
94
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2502
94
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2503
94
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2504
94
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2505
94
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
2506
94
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
2507
      // xor  $rd, $rs1, $rs2
2508
94
      MCInst_setOpcode(OutInst, RISCV_XOR);
2509
      // Operand: rd
2510
94
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2511
      // Operand: rs1
2512
94
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2513
      // Operand: rs2
2514
94
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 2));
2515
2516
94
      return true;
2517
94
    } // if
2518
0
      break;
2519
94
    } // case C_XOR
2520
504
    case RISCV_C_ZEXT_B: {
2521
504
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
2522
504
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2523
504
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2524
504
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2525
504
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2526
504
      RISCVValidateMCOperandForUncompress(MI,MCOperand_CreateImm1(MI, 255), 1)) {
2527
      // andi $rd, $rs1, $imm12
2528
504
      MCInst_setOpcode(OutInst, RISCV_ANDI);
2529
      // Operand: rd
2530
504
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2531
      // Operand: rs1
2532
504
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2533
      // Operand: imm12
2534
504
      MCOperand_CreateImm0(OutInst, 255);
2535
2536
504
      return true;
2537
504
    } // if
2538
0
      break;
2539
504
    } // case C_ZEXT_B
2540
0
    case RISCV_C_ZEXT_H: {
2541
0
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZbb) &&
2542
0
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
2543
0
      !RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
2544
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2545
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2546
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2547
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0))))) {
2548
      // zext.h $rd, $rs1
2549
0
      MCInst_setOpcode(OutInst, RISCV_ZEXT_H_RV32);
2550
      // Operand: rd
2551
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2552
      // Operand: rs1
2553
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2554
2555
0
      return true;
2556
0
    } // if
2557
0
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
2558
0
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZbb) &&
2559
0
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
2560
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2561
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2562
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2563
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0))))) {
2564
      // zext.h $rd, $rs1
2565
0
      MCInst_setOpcode(OutInst, RISCV_ZEXT_H_RV64);
2566
      // Operand: rd
2567
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2568
      // Operand: rs1
2569
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2570
2571
0
      return true;
2572
0
    } // if
2573
0
      break;
2574
0
    } // case C_ZEXT_H
2575
0
    case RISCV_C_ZEXT_W: {
2576
0
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
2577
0
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZba) &&
2578
0
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
2579
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2580
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2581
0
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2582
0
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0))))) {
2583
      // add.uw $rd, $rs1, $rs2
2584
0
      MCInst_setOpcode(OutInst, RISCV_ADD_UW);
2585
      // Operand: rd
2586
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2587
      // Operand: rs1
2588
0
      MCInst_addOperand2(OutInst, MCInst_getOperand(MI, 0));
2589
      // Operand: rs2
2590
0
      MCOperand_CreateReg0(OutInst, RISCV_X0);
2591
2592
0
      return true;
2593
0
    } // if
2594
2595
0
    } // case C_ZEXT_W
2596
143k
  } // switch
2597
0
  return false;
2598
143k
}
2599
2600
#endif //GEN_UNCOMPRESS_INSTR
2601
2602
2603
#ifdef GEN_CHECK_COMPRESS_INSTR
2604
#undef GEN_CHECK_COMPRESS_INSTR
2605
2606
static bool RISCVValidateMachineOperand(MCInst *MI,MCOperand *MO,
2607
                  unsigned PredicateIndex) {
2608
  int64_t Imm = MCOperand_getImm(MO);
2609
  switch (PredicateIndex) {
2610
  default:
2611
    CS_ASSERT_RET_VAL(0,false);
2612
   return false;
2613
    break;
2614
  case 1: {
2615
  // simm6nonzero
2616
  return (Imm != 0) && isIntN(6, Imm);
2617
  }
2618
  case 2: {
2619
  // simm10_lsb0000nonzero
2620
  return (Imm != 0) && isShiftedIntN(6, 4, Imm);
2621
  }
2622
  case 3: {
2623
  // uimm10_lsb00nonzero
2624
  return isShiftedUIntN(8, 2, Imm) && (Imm != 0);
2625
  }
2626
  case 4: {
2627
  // simm6
2628
  return isIntN(6, Imm);
2629
  }
2630
  case 5: {
2631
  // simm9_lsb0
2632
  return isShiftedIntN(8, 1, Imm);
2633
  }
2634
  case 6: {
2635
  // uimm8_lsb000
2636
  return isShiftedUIntN(5, 3, Imm);
2637
  }
2638
  case 7: {
2639
  // uimm9_lsb000
2640
  return isShiftedUIntN(6, 3, Imm);
2641
  }
2642
  case 8: {
2643
  // uimm7_lsb00
2644
  return isShiftedUIntN(5, 2, Imm);
2645
  }
2646
  case 9: {
2647
  // uimm8_lsb00
2648
  return isShiftedUIntN(6, 2, Imm);
2649
  }
2650
  case 10: {
2651
  // simm12_lsb0
2652
  return isShiftedIntN(11, 1, Imm);
2653
  }
2654
  case 11: {
2655
  // uimm2
2656
  return isUIntN(2, Imm);
2657
  }
2658
  case 12: {
2659
  // uimm2_lsb0
2660
  return isShiftedUIntN(1, 1, Imm);
2661
  }
2662
  case 13: {
2663
  // c_lui_imm
2664
  return (Imm != 0) &&
2665
                                 (isUIntN(5, Imm) ||
2666
                                  (Imm >= 0xfffe0 && Imm <= 0xfffff));
2667
  }
2668
  case 14: {
2669
  // uimmlog2xlennonzero
2670
2671
  if (RISCV_getFeatureBits(MI->csh->mode,RISCV_Feature64Bit))
2672
    return isUIntN(6, Imm) && (Imm != 0);
2673
  return isUIntN(5, Imm) && (Imm != 0);
2674
2675
  }
2676
  }
2677
}
2678
2679
static bool isCompressibleInst(MCInst *MI) {
2680
  switch (MCInst_getOpcode(MI)) {
2681
    default: return false;
2682
    case RISCV_ADD: {
2683
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2684
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2685
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2686
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2687
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2688
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
2689
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
2690
      // c.add  $rs1, $rs2
2691
      // Operand: rs1_wb
2692
      // Operand: rs1
2693
      // Operand: rs2
2694
      return true;
2695
    } // if
2696
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2697
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2698
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2699
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
2700
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2)))) &&
2701
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2702
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
2703
      // c.add  $rs1, $rs2
2704
      // Operand: rs1_wb
2705
      // Operand: rs1
2706
      // Operand: rs2
2707
      return true;
2708
    } // if
2709
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2710
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2711
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) &&
2712
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2713
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2714
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
2715
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
2716
      // c.mv $rs1, $rs2
2717
      // Operand: rs1
2718
      // Operand: rs2
2719
      return true;
2720
    } // if
2721
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2722
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
2723
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) &&
2724
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2725
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2726
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2727
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
2728
      // c.mv $rs1, $rs2
2729
      // Operand: rs1
2730
      // Operand: rs2
2731
      return true;
2732
    } // if
2733
      break;
2734
    } // case ADD
2735
    case RISCV_ADDI: {
2736
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2737
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2738
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2739
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2740
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2741
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2742
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 1)) {
2743
      // c.addi $rd, $imm
2744
      // Operand: rd_wb
2745
      // Operand: rd
2746
      // Operand: imm
2747
      return true;
2748
    } // if
2749
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2750
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2751
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X2) &&
2752
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2753
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X2) &&
2754
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2755
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 2)) {
2756
      // c.addi16sp $rd, $imm
2757
      // Operand: rd_wb
2758
      // Operand: rd
2759
      // Operand: imm
2760
      return true;
2761
    } // if
2762
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2763
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2764
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2765
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2766
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2767
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2768
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 3)) {
2769
      // c.addi4spn $rd, $rs1, $imm
2770
      // Operand: rd
2771
      // Operand: rs1
2772
      // Operand: imm
2773
      return true;
2774
    } // if
2775
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2776
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2777
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) &&
2778
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2779
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2780
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2781
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 4)) {
2782
      // c.li $rd, $imm
2783
      // Operand: rd
2784
      // Operand: imm
2785
      return true;
2786
    } // if
2787
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2788
      (MCOperand_isImm(MCInst_getOperand(MI, 2))) &&
2789
      (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) &&
2790
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2791
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2792
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2793
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
2794
      // c.mv $rs1, $rs2
2795
      // Operand: rs1
2796
      // Operand: rs2
2797
      return true;
2798
    } // if
2799
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2800
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2801
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) &&
2802
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2803
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) &&
2804
      (MCOperand_isImm(MCInst_getOperand(MI, 2))) &&
2805
      (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
2806
      // c.nop
2807
      return true;
2808
    } // if
2809
      break;
2810
    } // case ADDI
2811
    case RISCV_ADDIW: {
2812
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
2813
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2814
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2815
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2816
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2817
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2818
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2819
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 4)) {
2820
      // c.addiw  $rd, $imm
2821
      // Operand: rd_wb
2822
      // Operand: rd
2823
      // Operand: imm
2824
      return true;
2825
    } // if
2826
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
2827
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2828
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2829
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) &&
2830
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2831
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2832
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 4)) {
2834
      // c.li $rd, $imm
2835
      // Operand: rd
2836
      // Operand: imm
2837
      return true;
2838
    } // if
2839
      break;
2840
    } // case ADDIW
2841
    case RISCV_ADDW: {
2842
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
2843
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2844
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2845
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2846
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2847
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2848
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
2849
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
2850
      // c.addw $rd, $rs2
2851
      // Operand: rd_wb
2852
      // Operand: rd
2853
      // Operand: rs2
2854
      return true;
2855
    } // if
2856
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
2857
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2858
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2859
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2860
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
2861
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2)))) &&
2862
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2863
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
2864
      // c.addw $rd, $rs2
2865
      // Operand: rd_wb
2866
      // Operand: rd
2867
      // Operand: rs2
2868
      return true;
2869
    } // if
2870
      break;
2871
    } // case ADDW
2872
    case RISCV_ADD_UW: {
2873
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
2874
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZba) &&
2875
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
2876
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2877
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2878
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
2879
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) &&
2880
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2881
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
2882
      // c.zext.w $rd
2883
      // Operand: rd_wb
2884
      // Operand: rd
2885
      return true;
2886
    } // if
2887
      break;
2888
    } // case ADD_UW
2889
    case RISCV_AND: {
2890
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2891
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2892
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2893
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2894
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2895
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
2896
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
2897
      // c.and  $rd, $rs2
2898
      // Operand: rd_wb
2899
      // Operand: rd
2900
      // Operand: rs2
2901
      return true;
2902
    } // if
2903
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2904
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2905
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2906
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
2907
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2)))) &&
2908
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2909
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
2910
      // c.and  $rd, $rs2
2911
      // Operand: rd_wb
2912
      // Operand: rd
2913
      // Operand: rs2
2914
      return true;
2915
    } // if
2916
      break;
2917
    } // case AND
2918
    case RISCV_ANDI: {
2919
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2920
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2921
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2922
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2923
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2924
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2925
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 4)) {
2926
      // c.andi $rs1, $imm
2927
      // Operand: rs1_wb
2928
      // Operand: rs1
2929
      // Operand: imm
2930
      return true;
2931
    } // if
2932
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
2933
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2934
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
2935
      (MCOperand_isImm(MCInst_getOperand(MI, 2))) &&
2936
      (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 255) &&
2937
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2938
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
2939
      // c.zext.b $rd
2940
      // Operand: rd_wb
2941
      // Operand: rd
2942
      return true;
2943
    } // if
2944
      break;
2945
    } // case ANDI
2946
    case RISCV_BEQ: {
2947
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2948
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2949
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) &&
2950
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2951
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2952
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2953
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 5)) {
2954
      // c.beqz $rs1, $imm
2955
      // Operand: rs1
2956
      // Operand: imm
2957
      return true;
2958
    } // if
2959
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2960
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2961
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) &&
2962
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2963
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2964
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2965
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 5)) {
2966
      // c.beqz $rs1, $imm
2967
      // Operand: rs1
2968
      // Operand: imm
2969
      return true;
2970
    } // if
2971
      break;
2972
    } // case BEQ
2973
    case RISCV_BNE: {
2974
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2975
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2976
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) &&
2977
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2978
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
2979
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2980
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 5)) {
2981
      // c.bnez $rs1, $imm
2982
      // Operand: rs1
2983
      // Operand: imm
2984
      return true;
2985
    } // if
2986
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
2987
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
2988
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) &&
2989
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
2990
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
2991
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2992
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 5)) {
2993
      // c.bnez $rs1, $imm
2994
      // Operand: rs1
2995
      // Operand: imm
2996
      return true;
2997
    } // if
2998
      break;
2999
    } // case BNE
3000
    case RISCV_EBREAK: {
3001
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca))) {
3002
      // c.ebreak
3003
      return true;
3004
    } // if
3005
      break;
3006
    } // case EBREAK
3007
    case RISCV_FLD: {
3008
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtD) &&
3009
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcd)) &&
3010
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3011
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR64CRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3012
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3013
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3014
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3015
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 6)) {
3016
      // c.fld  $rd, ${imm}(${rs1})
3017
      // Operand: rd
3018
      // Operand: rs1
3019
      // Operand: imm
3020
      return true;
3021
    } // if
3022
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtD) &&
3023
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcd)) &&
3024
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3025
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR64RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3026
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3027
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3028
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3029
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 7)) {
3030
      // c.fldsp  $rd, ${imm}(${rs1})
3031
      // Operand: rd
3032
      // Operand: rs1
3033
      // Operand: imm
3034
      return true;
3035
    } // if
3036
      break;
3037
    } // case FLD
3038
    case RISCV_FLW: {
3039
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtF) &&
3040
      !RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
3041
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZce) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcf)) &&
3042
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3043
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR32CRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3044
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3045
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3046
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3047
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 8)) {
3048
      // c.flw  $rd, ${imm}(${rs1})
3049
      // Operand: rd
3050
      // Operand: rs1
3051
      // Operand: imm
3052
      return true;
3053
    } // if
3054
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtF) &&
3055
      !RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
3056
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZce) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcf)) &&
3057
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3058
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR32RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3059
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3060
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3061
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3062
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 9)) {
3063
      // c.flwsp  $rd, ${imm}(${rs1})
3064
      // Operand: rd
3065
      // Operand: rs1
3066
      // Operand: imm
3067
      return true;
3068
    } // if
3069
      break;
3070
    } // case FLW
3071
    case RISCV_FSD: {
3072
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtD) &&
3073
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcd)) &&
3074
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3075
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR64CRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3076
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3077
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3078
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3079
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 6)) {
3080
      // c.fsd  $rs2, ${imm}(${rs1})
3081
      // Operand: rs2
3082
      // Operand: rs1
3083
      // Operand: imm
3084
      return true;
3085
    } // if
3086
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtD) &&
3087
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcd)) &&
3088
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3089
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR64RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3090
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3091
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3092
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3093
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 7)) {
3094
      // c.fsdsp  $rs2, ${imm}(${rs1})
3095
      // Operand: rs2
3096
      // Operand: rs1
3097
      // Operand: imm
3098
      return true;
3099
    } // if
3100
      break;
3101
    } // case FSD
3102
    case RISCV_FSW: {
3103
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtF) &&
3104
      !RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
3105
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZce) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcf)) &&
3106
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3107
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR32CRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3108
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3109
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3110
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3111
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 8)) {
3112
      // c.fsw  $rs2, ${imm}(${rs1})
3113
      // Operand: rs2
3114
      // Operand: rs1
3115
      // Operand: imm
3116
      return true;
3117
    } // if
3118
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtF) &&
3119
      !RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
3120
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZce) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcf)) &&
3121
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3122
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_FPR32RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3123
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3124
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3125
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3126
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 9)) {
3127
      // c.fswsp  $rs2, ${imm}(${rs1})
3128
      // Operand: rs2
3129
      // Operand: rs1
3130
      // Operand: imm
3131
      return true;
3132
    } // if
3133
      break;
3134
    } // case FSW
3135
    case RISCV_JAL: {
3136
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3137
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3138
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) &&
3139
      MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
3140
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 1), 10)) {
3141
      // c.j  $offset
3142
      // Operand: offset
3143
      return true;
3144
    } // if
3145
    if (!RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
3146
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3147
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3148
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1) &&
3149
      MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
3150
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 1), 10)) {
3151
      // c.jal  $offset
3152
      // Operand: offset
3153
      return true;
3154
    } // if
3155
      break;
3156
    } // case JAL
3157
    case RISCV_JALR: {
3158
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3159
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3160
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1) &&
3161
      (MCOperand_isImm(MCInst_getOperand(MI, 2))) &&
3162
      (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) &&
3163
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3164
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
3165
      // c.jalr $rs1
3166
      // Operand: rs1
3167
      return true;
3168
    } // if
3169
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3170
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3171
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) &&
3172
      (MCOperand_isImm(MCInst_getOperand(MI, 2))) &&
3173
      (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) &&
3174
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3175
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
3176
      // c.jr $rs1
3177
      // Operand: rs1
3178
      return true;
3179
    } // if
3180
      break;
3181
    } // case JALR
3182
    case RISCV_LBU: {
3183
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
3184
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3185
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3186
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3187
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3188
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 11)) {
3190
      // c.lbu  $rd, ${imm}(${rs1})
3191
      // Operand: rd
3192
      // Operand: rs1
3193
      // Operand: imm
3194
      return true;
3195
    } // if
3196
      break;
3197
    } // case LBU
3198
    case RISCV_LD: {
3199
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
3200
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3201
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3202
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3203
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3204
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3205
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3206
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 6)) {
3207
      // c.ld $rd, ${imm}(${rs1})
3208
      // Operand: rd
3209
      // Operand: rs1
3210
      // Operand: imm
3211
      return true;
3212
    } // if
3213
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
3214
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3215
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3216
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3217
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3218
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3219
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3220
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 7)) {
3221
      // c.ldsp $rd, ${imm}(${rs1})
3222
      // Operand: rd
3223
      // Operand: rs1
3224
      // Operand: imm
3225
      return true;
3226
    } // if
3227
      break;
3228
    } // case LD
3229
    case RISCV_LH: {
3230
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
3231
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3232
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3233
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3234
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3235
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3236
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 12)) {
3237
      // c.lh $rd, ${imm}(${rs1})
3238
      // Operand: rd
3239
      // Operand: rs1
3240
      // Operand: imm
3241
      return true;
3242
    } // if
3243
      break;
3244
    } // case LH
3245
    case RISCV_LHU: {
3246
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
3247
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3248
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3249
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3250
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3251
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3252
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 12)) {
3253
      // c.lhu  $rd, ${imm}(${rs1})
3254
      // Operand: rd
3255
      // Operand: rs1
3256
      // Operand: imm
3257
      return true;
3258
    } // if
3259
      break;
3260
    } // case LHU
3261
    case RISCV_LUI: {
3262
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3263
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3264
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0X2RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3265
      MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
3266
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 1), 13)) {
3267
      // c.lui  $rd, $imm
3268
      // Operand: rd
3269
      // Operand: imm
3270
      return true;
3271
    } // if
3272
      break;
3273
    } // case LUI
3274
    case RISCV_LW: {
3275
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3276
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3277
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3278
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3279
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3280
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3281
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 8)) {
3282
      // c.lw $rd, ${imm}(${rs1})
3283
      // Operand: rd
3284
      // Operand: rs1
3285
      // Operand: imm
3286
      return true;
3287
    } // if
3288
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3289
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3290
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3291
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3292
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3293
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3294
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 9)) {
3295
      // c.lwsp $rd, ${imm}(${rs1})
3296
      // Operand: rd
3297
      // Operand: rs1
3298
      // Operand: imm
3299
      return true;
3300
    } // if
3301
      break;
3302
    } // case LW
3303
    case RISCV_MUL: {
3304
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
3305
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtM) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZmmul)) &&
3306
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3307
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3308
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3309
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3310
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
3311
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
3312
      // c.mul  $rd, $rs2
3313
      // Operand: rd_wb
3314
      // Operand: rd
3315
      // Operand: rs2
3316
      return true;
3317
    } // if
3318
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
3319
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtM) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZmmul)) &&
3320
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3321
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3322
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
3323
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2)))) &&
3324
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3325
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
3326
      // c.mul  $rd, $rs2
3327
      // Operand: rd_wb
3328
      // Operand: rd
3329
      // Operand: rs2
3330
      return true;
3331
    } // if
3332
      break;
3333
    } // case MUL
3334
    case RISCV_OR: {
3335
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3336
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3337
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3338
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3339
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3340
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
3341
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
3342
      // c.or $rd, $rs2
3343
      // Operand: rd_wb
3344
      // Operand: rd
3345
      // Operand: rs2
3346
      return true;
3347
    } // if
3348
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3349
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3350
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3351
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
3352
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2)))) &&
3353
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3354
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
3355
      // c.or $rd, $rs2
3356
      // Operand: rd_wb
3357
      // Operand: rd
3358
      // Operand: rs2
3359
      return true;
3360
    } // if
3361
      break;
3362
    } // case OR
3363
    case RISCV_SB: {
3364
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
3365
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3366
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3367
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3368
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3369
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3370
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 11)) {
3371
      // c.sb $rs2, ${imm}(${rs1})
3372
      // Operand: rs2
3373
      // Operand: rs1
3374
      // Operand: imm
3375
      return true;
3376
    } // if
3377
      break;
3378
    } // case SB
3379
    case RISCV_SD: {
3380
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
3381
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3382
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3383
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3384
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3385
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3386
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3387
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 6)) {
3388
      // c.sd $rs2, ${imm}(${rs1})
3389
      // Operand: rs2
3390
      // Operand: rs1
3391
      // Operand: imm
3392
      return true;
3393
    } // if
3394
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
3395
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3396
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3397
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3398
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3399
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3400
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3401
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 7)) {
3402
      // c.sdsp $rs2, ${imm}(${rs1})
3403
      // Operand: rs2
3404
      // Operand: rs1
3405
      // Operand: imm
3406
      return true;
3407
    } // if
3408
      break;
3409
    } // case SD
3410
    case RISCV_SEXT_B: {
3411
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZbb) &&
3412
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
3413
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3414
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3415
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3416
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
3417
      // c.sext.b $rd
3418
      // Operand: rd_wb
3419
      // Operand: rd
3420
      return true;
3421
    } // if
3422
      break;
3423
    } // case SEXT_B
3424
    case RISCV_SEXT_H: {
3425
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZbb) &&
3426
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
3427
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3428
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3429
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3430
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
3431
      // c.sext.h $rd
3432
      // Operand: rd_wb
3433
      // Operand: rd
3434
      return true;
3435
    } // if
3436
      break;
3437
    } // case SEXT_H
3438
    case RISCV_SH: {
3439
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
3440
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3441
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3442
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3443
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3444
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3445
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 12)) {
3446
      // c.sh $rs2, ${imm}(${rs1})
3447
      // Operand: rs2
3448
      // Operand: rs1
3449
      // Operand: imm
3450
      return true;
3451
    } // if
3452
      break;
3453
    } // case SH
3454
    case RISCV_SLLI: {
3455
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3456
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3457
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3458
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3459
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRNoX0RegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3460
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3461
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 14)) {
3462
      // c.slli $rd, $imm
3463
      // Operand: rd_wb
3464
      // Operand: rd
3465
      // Operand: imm
3466
      return true;
3467
    } // if
3468
      break;
3469
    } // case SLLI
3470
    case RISCV_SRAI: {
3471
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3472
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3473
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3474
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3475
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3476
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3477
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 14)) {
3478
      // c.srai $rs1, $imm
3479
      // Operand: rs1_wb
3480
      // Operand: rs1
3481
      // Operand: imm
3482
      return true;
3483
    } // if
3484
      break;
3485
    } // case SRAI
3486
    case RISCV_SRLI: {
3487
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3488
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3489
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3490
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3491
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3492
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3493
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 14)) {
3494
      // c.srli $rs1, $imm
3495
      // Operand: rs1_wb
3496
      // Operand: rs1
3497
      // Operand: imm
3498
      return true;
3499
    } // if
3500
      break;
3501
    } // case SRLI
3502
    case RISCV_SSPOPCHK: {
3503
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcmop) &&
3504
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZicfiss) &&
3505
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3506
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X5)) {
3507
      // c.sspopchk $rs1
3508
      // Operand: rs1
3509
      return true;
3510
    } // if
3511
      break;
3512
    } // case SSPOPCHK
3513
    case RISCV_SSPUSH: {
3514
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcmop) &&
3515
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZicfiss) &&
3516
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3517
      (MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1)) {
3518
      // c.sspush $rs1
3519
      // Operand: rs1
3520
      return true;
3521
    } // if
3522
      break;
3523
    } // case SSPUSH
3524
    case RISCV_SUB: {
3525
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3526
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3527
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3528
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3529
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3530
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
3531
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
3532
      // c.sub  $rd, $rs2
3533
      // Operand: rd_wb
3534
      // Operand: rd
3535
      // Operand: rs2
3536
      return true;
3537
    } // if
3538
      break;
3539
    } // case SUB
3540
    case RISCV_SUBW: {
3541
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit) &&
3542
      (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3543
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3544
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3545
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3546
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3547
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
3548
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
3549
      // c.subw $rd, $rs2
3550
      // Operand: rd_wb
3551
      // Operand: rd
3552
      // Operand: rs2
3553
      return true;
3554
    } // if
3555
      break;
3556
    } // case SUBW
3557
    case RISCV_SW: {
3558
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3559
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3560
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3561
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3562
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3563
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3564
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 8)) {
3565
      // c.sw $rs2, ${imm}(${rs1})
3566
      // Operand: rs2
3567
      // Operand: rs1
3568
      // Operand: imm
3569
      return true;
3570
    } // if
3571
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3572
      (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3573
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 0)))) &&
3574
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3575
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_SPRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3576
      MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3577
      RISCVValidateMachineOperand(MI,MCInst_getOperand(MI, 2), 9)) {
3578
      // c.swsp $rs2, ${imm}(${rs1})
3579
      // Operand: rs2
3580
      // Operand: rs1
3581
      // Operand: imm
3582
      return true;
3583
    } // if
3584
      break;
3585
    } // case SW
3586
    case RISCV_UNIMP: {
3587
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca))) {
3588
      // c.unimp
3589
      return true;
3590
    } // if
3591
      break;
3592
    } // case UNIMP
3593
    case RISCV_XOR: {
3594
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3595
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3596
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3597
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3598
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1)))) &&
3599
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
3600
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2))))) {
3601
      // c.xor  $rd, $rs2
3602
      // Operand: rd_wb
3603
      // Operand: rd
3604
      // Operand: rs2
3605
      return true;
3606
    } // if
3607
    if ((RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtC) || RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZca)) &&
3608
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3609
      (MCOperand_getReg(MCInst_getOperand(MI, 2)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3610
      (MCOperand_isReg(MCInst_getOperand(MI, 2))) &&
3611
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 2)))) &&
3612
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3613
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
3614
      // c.xor  $rd, $rs2
3615
      // Operand: rd_wb
3616
      // Operand: rd
3617
      // Operand: rs2
3618
      return true;
3619
    } // if
3620
      break;
3621
    } // case XOR
3622
    case RISCV_XORI: {
3623
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
3624
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3625
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3626
      (MCOperand_isImm(MCInst_getOperand(MI, 2))) &&
3627
      (MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1) &&
3628
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3629
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
3630
      // c.not  $rd
3631
      // Operand: rd_wb
3632
      // Operand: rd
3633
      return true;
3634
    } // if
3635
      break;
3636
    } // case XORI
3637
    case RISCV_ZEXT_H_RV32: {
3638
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZbb) &&
3639
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
3640
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3641
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3642
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3643
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
3644
      // c.zext.h $rd
3645
      // Operand: rd_wb
3646
      // Operand: rd
3647
      return true;
3648
    } // if
3649
      break;
3650
    } // case ZEXT_H_RV32
3651
    case RISCV_ZEXT_H_RV64: {
3652
    if (RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZbb) &&
3653
      RISCV_getFeatureBits(MI->csh->mode, RISCV_FeatureStdExtZcb) &&
3654
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) && (MCOperand_isReg(MCInst_getOperand(MI, 0))) &&
3655
      (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==  MCOperand_getReg(MCInst_getOperand(MI, 0))) &&
3656
      (MCOperand_isReg(MCInst_getOperand(MI, 1))) &&
3657
      (MCRegisterClass_contains(MCRegisterInfo_getRegClass(MI->MRI, RISCV_GPRCRegClassID),MCOperand_getReg(MCInst_getOperand(MI, 1))))) {
3658
      // c.zext.h $rd
3659
      // Operand: rd_wb
3660
      // Operand: rd
3661
      return true;
3662
    } // if
3663
3664
    } // case ZEXT_H_RV64
3665
  } // switch
3666
  return false;
3667
}
3668
3669
#endif //GEN_CHECK_COMPRESS_INSTR