/src/capstonenext/arch/TMS320C64x/TMS320C64xInstPrinter.c

Source
/* Capstone Disassembly Engine */
/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */

#ifdef CAPSTONE_HAS_TMS320C64X

#include <ctype.h>
#include <string.h>

#include "TMS320C64xInstPrinter.h"
#include "../../MCInst.h"
#include "../../utils.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "../../MathExtras.h"
#include "TMS320C64xMapping.h"

#include "capstone/tms320c64x.h"

static const char *getRegisterName(unsigned RegNo);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O);
static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O);

void TMS320C64x_post_printer(csh ud, cs_insn *insn, SStream *insn_asm,
           MCInst *mci)
{
  SStream ss;
  const char *op_str_ptr, *p2;
  char tmp[8] = { 0 };
  unsigned int unit = 0;
  int i;
  cs_tms320c64x *tms320c64x;

  if (mci->csh->detail_opt) {
    tms320c64x = &mci->flat_insn->detail->tms320c64x;

    for (i = 0; i < insn->detail->groups_count; i++) {
      switch (insn->detail->groups[i]) {
      case TMS320C64X_GRP_FUNIT_D:
        unit = TMS320C64X_FUNIT_D;
        break;
      case TMS320C64X_GRP_FUNIT_L:
        unit = TMS320C64X_FUNIT_L;
        break;
      case TMS320C64X_GRP_FUNIT_M:
        unit = TMS320C64X_FUNIT_M;
        break;
      case TMS320C64X_GRP_FUNIT_S:
        unit = TMS320C64X_FUNIT_S;
        break;
      case TMS320C64X_GRP_FUNIT_NO:
        unit = TMS320C64X_FUNIT_NO;
        break;
      }
      if (unit != 0)
        break;
    }
    tms320c64x->funit.unit = unit;

    SStream_Init(&ss);
    if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
      SStream_concat(
        &ss, "[%c%s]|",
        (tms320c64x->condition.zero == 1) ? '!' : '|',
        cs_reg_name(ud, tms320c64x->condition.reg));

    // Sorry for all the fixes below. I don't have time to add more helper SStream functions.
    // Before that they messed around with the private buffer of the stream.
    // So it is better now. But still not efficient.
    op_str_ptr = strchr(SStream_rbuf(insn_asm), '\t');

    if ((op_str_ptr != NULL) &&
        (((p2 = strchr(op_str_ptr, '[')) != NULL) ||
         ((p2 = strchr(op_str_ptr, '(')) != NULL))) {
      while ((p2 > op_str_ptr) &&
             ((*p2 != 'a') && (*p2 != 'b')))
        p2--;
      if (p2 == op_str_ptr) {
        SStream_Flush(insn_asm, NULL);
        SStream_concat0(insn_asm, "Invalid!");
        return;
      }
      if (*p2 == 'a')
        strncpy(tmp, "1T", sizeof(tmp));
      else
        strncpy(tmp, "2T", sizeof(tmp));
    } else {
      tmp[0] = '\0';
    }
    SStream mnem_post = { 0 };
    SStream_Init(&mnem_post);
    switch (tms320c64x->funit.unit) {
    case TMS320C64X_FUNIT_D:
      SStream_concat(&mnem_post, ".D%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_L:
      SStream_concat(&mnem_post, ".L%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_M:
      SStream_concat(&mnem_post, ".M%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_S:
      SStream_concat(&mnem_post, ".S%s%u", tmp,
               tms320c64x->funit.side);
      break;
    }
    if (tms320c64x->funit.crosspath > 0)
      SStream_concat0(&mnem_post, "X");

    if (op_str_ptr != NULL) {
      // There is an op_str
      SStream_concat1(&mnem_post, '\t');
      SStream_replc_str(insn_asm, '\t',
            SStream_rbuf(&mnem_post));
    }

    if (tms320c64x->parallel != 0)
      SStream_concat0(insn_asm, "\t||");
    SStream_concat0(&ss, SStream_rbuf(insn_asm));
    SStream_Flush(insn_asm, NULL);
    SStream_concat0(insn_asm, SStream_rbuf(&ss));
  }
}

#define PRINT_ALIAS_INSTR
#include "TMS320C64xGenAsmWriter.inc"

#define GET_INSTRINFO_ENUM
#include "TMS320C64xGenInstrInfo.inc"

static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg;

  if (MCOperand_isReg(Op)) {
    reg = MCOperand_getReg(Op);
    if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) &&
        (OpNo == 1)) {
      switch (reg) {
      case TMS320C64X_REG_EFR:
        SStream_concat0(O, "EFR");
        break;
      case TMS320C64X_REG_IFR:
        SStream_concat0(O, "IFR");
        break;
      default:
        SStream_concat0(O, getRegisterName(reg));
        break;
      }
    } else {
      SStream_concat0(O, getRegisterName(reg));
    }

    if (MI->csh->detail_opt) {
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .type = TMS320C64X_OP_REG;
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .reg = reg;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  } else if (MCOperand_isImm(Op)) {
    int64_t Imm = MCOperand_getImm(Op);

    if (Imm >= 0) {
      if (Imm > HEX_THRESHOLD)
        SStream_concat(O, "0x%" PRIx64, Imm);
      else
        SStream_concat(O, "%" PRIu64, Imm);
    } else {
      if (Imm < -HEX_THRESHOLD)
        SStream_concat(O, "-0x%" PRIx64, -Imm);
      else
        SStream_concat(O, "-%" PRIu64, -Imm);
    }

    if (MI->csh->detail_opt) {
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .type = TMS320C64X_OP_IMM;
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .imm = Imm;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  }
}

static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  unsigned scaled, base, offset, mode, unit;
  cs_tms320c64x *tms320c64x;
  char st, nd;

  scaled = (Val >> 19) & 1;
  base = (Val >> 12) & 0x7f;
  offset = (Val >> 5) & 0x7f;
  mode = (Val >> 1) & 0xf;
  unit = Val & 1;

  if (scaled) {
    st = '[';
    nd = ']';
  } else {
    st = '(';
    nd = ')';
  }

  switch (mode) {
  case 0:
    SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 1:
    SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 4:
    SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 5:
    SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 8:
    SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 9:
    SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 10:
    SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 11:
    SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 12:
    SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 13:
    SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 14:
    SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 15:
    SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  }

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = base;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
    tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
    switch (mode) {
    case 0:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 1:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 4:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 5:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 8:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 9:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 10:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 11:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 12:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 13:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 14:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 15:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    }
    tms320c64x->op_count++;
  }
}

static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  uint16_t offset;
  unsigned basereg;
  cs_tms320c64x *tms320c64x;

  basereg = Val & 0x7f;
  offset = (Val >> 7) & 0x7fff;
  SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.disptype =
      TMS320C64X_MEM_DISP_CONSTANT;
    tms320c64x->operands[tms320c64x->op_count].mem.direction =
      TMS320C64X_MEM_DIR_FW;
    tms320c64x->operands[tms320c64x->op_count].mem.modify =
      TMS320C64X_MEM_MOD_NO;
    tms320c64x->op_count++;
  }
}

static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg = MCOperand_getReg(Op);
  cs_tms320c64x *tms320c64x;

  SStream_concat(O, "%s:%s", getRegisterName(reg + 1),
           getRegisterName(reg));

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_REGPAIR;
    tms320c64x->operands[tms320c64x->op_count].reg = reg;
    tms320c64x->op_count++;
  }
}

static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
{
  unsigned opcode = MCInst_getOpcode(MI);
  MCOperand *op;

  switch (opcode) {
  /* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
  case TMS320C64x_ADD_d2_rir:
  /* ADD.L -i, x, y -> SUB.L x, i, y */
  case TMS320C64x_ADD_l1_irr:
  case TMS320C64x_ADD_l1_ipp:
  /* ADD.S -i, x, y -> SUB.S x, i, y */
  case TMS320C64x_ADD_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
      op = MCInst_getOperand(MI, 2);
      MCOperand_setImm(op, -MCOperand_getImm(op));

      SStream_concat0(O, "SUB\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 2, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* ADD.D 0, x, y -> MV.D x, y */
  case TMS320C64x_ADD_d1_rir:
  /* OR.D x, 0, y -> MV.D x, y */
  case TMS320C64x_OR_d2_rir:
  /* ADD.L 0, x, y -> MV.L x, y */
  case TMS320C64x_ADD_l1_irr:
  case TMS320C64x_ADD_l1_ipp:
  /* OR.L 0, x, y -> MV.L x, y */
  case TMS320C64x_OR_l1_irr:
  /* ADD.S 0, x, y -> MV.S x, y */
  case TMS320C64x_ADD_s1_irr:
  /* OR.S 0, x, y -> MV.S x, y */
  case TMS320C64x_OR_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
      MI->size--;

      SStream_concat0(O, "MV\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* XOR.D -1, x, y -> NOT.D x, y */
  case TMS320C64x_XOR_d2_rir:
  /* XOR.L -1, x, y -> NOT.L x, y */
  case TMS320C64x_XOR_l1_irr:
  /* XOR.S -1, x, y -> NOT.S x, y */
  case TMS320C64x_XOR_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
      MI->size--;

      SStream_concat0(O, "NOT\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* MVK.D 0, x -> ZERO.D x */
  case TMS320C64x_MVK_d1_rr:
  /* MVK.L 0, x -> ZERO.L x */
  case TMS320C64x_MVK_l2_ir:
    if ((MCInst_getNumOperands(MI) == 2) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
      MI->size--;

      SStream_concat0(O, "ZERO\t");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* SUB.L x, x, y -> ZERO.L y */
  case TMS320C64x_SUB_l1_rrp_x1:
  /* SUB.S x, x, y -> ZERO.S y */
  case TMS320C64x_SUB_s1_rrr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
         MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
      MI->size -= 2;

      SStream_concat0(O, "ZERO\t");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* SUB.L 0, x, y -> NEG.L x, y */
  case TMS320C64x_SUB_l1_irr:
  case TMS320C64x_SUB_l1_ipp:
  /* SUB.S 0, x, y -> NEG.S x, y */
  case TMS320C64x_SUB_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
      MI->size--;

      SStream_concat0(O, "NEG\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* PACKLH2.L x, x, y -> SWAP2.L x, y */
  case TMS320C64x_PACKLH2_l1_rrr_x2:
  /* PACKLH2.S x, x, y -> SWAP2.S x, y */
  case TMS320C64x_PACKLH2_s1_rrr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
         MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
      MI->size--;

      SStream_concat0(O, "SWAP2\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* NOP 16 -> IDLE */
  /* NOP 1 -> NOP */
  case TMS320C64x_NOP_n:
    if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
      MI->size--;

      SStream_concat0(O, "IDLE");

      return true;
    }
    if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
      MI->size--;

      SStream_concat0(O, "NOP");

      return true;
    }
    break;
  }

  return false;
}

void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info)
{
  if (!printAliasInstruction(MI, O, Info))
    printInstruction(MI, O, Info);
}

#endif

Coverage Report

Created: 2026-02-26 07:11

Line	Count	Source
1		/* Capstone Disassembly Engine */
2		/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
3
4		#ifdef CAPSTONE_HAS_TMS320C64X
5
6		#include <ctype.h>
7		#include <string.h>
8
9		#include "TMS320C64xInstPrinter.h"
10		#include "../../MCInst.h"
11		#include "../../utils.h"
12		#include "../../SStream.h"
13		#include "../../MCRegisterInfo.h"
14		#include "../../MathExtras.h"
15		#include "TMS320C64xMapping.h"
16
17		#include "capstone/tms320c64x.h"
18
19		static const char *getRegisterName(unsigned RegNo);
20		static void printOperand(MCInst MI, unsigned OpNo, SStream O);
21		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O);
22		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O);
23		static void printRegPair(MCInst MI, unsigned OpNo, SStream O);
24
25		void TMS320C64x_post_printer(csh ud, cs_insn insn, SStream insn_asm,
26		MCInst *mci)
27	44.1k	{
28	44.1k	SStream ss;
29	44.1k	const char op_str_ptr, p2;
30	44.1k	char tmp[8] = { 0 };
31	44.1k	unsigned int unit = 0;
32	44.1k	int i;
33	44.1k	cs_tms320c64x *tms320c64x;
34
35	44.1k	if (mci->csh->detail_opt) {
36	44.1k	tms320c64x = &mci->flat_insn->detail->tms320c64x;
37
38	44.1k	for (i = 0; i < insn->detail->groups_count; i++) {
39	44.1k	switch (insn->detail->groups[i]) {
40	11.8k	case TMS320C64X_GRP_FUNIT_D:
41	11.8k	unit = TMS320C64X_FUNIT_D;
42	11.8k	break;
43	8.78k	case TMS320C64X_GRP_FUNIT_L:
44	8.78k	unit = TMS320C64X_FUNIT_L;
45	8.78k	break;
46	2.72k	case TMS320C64X_GRP_FUNIT_M:
47	2.72k	unit = TMS320C64X_FUNIT_M;
48	2.72k	break;
49	19.3k	case TMS320C64X_GRP_FUNIT_S:
50	19.3k	unit = TMS320C64X_FUNIT_S;
51	19.3k	break;
52	1.38k	case TMS320C64X_GRP_FUNIT_NO:
53	1.38k	unit = TMS320C64X_FUNIT_NO;
54	1.38k	break;
55	44.1k	}
56	44.1k	if (unit != 0)
57	44.1k	break;
58	44.1k	}
59	44.1k	tms320c64x->funit.unit = unit;
60
61	44.1k	SStream_Init(&ss);
62	44.1k	if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
63	28.2k	SStream_concat(
64	28.2k	&ss, "[%c%s]\|",
65	28.2k	(tms320c64x->condition.zero == 1) ? '!' : '\|',
66	28.2k	cs_reg_name(ud, tms320c64x->condition.reg));
67
68		// Sorry for all the fixes below. I don't have time to add more helper SStream functions.
69		// Before that they messed around with the private buffer of the stream.
70		// So it is better now. But still not efficient.
71	44.1k	op_str_ptr = strchr(SStream_rbuf(insn_asm), '\t');
72
73	44.1k	if ((op_str_ptr != NULL) &&
74	42.9k	(((p2 = strchr(op_str_ptr, '[')) != NULL) \|\|
75	34.3k	((p2 = strchr(op_str_ptr, '(')) != NULL))) {
76	38.7k	while ((p2 > op_str_ptr) &&
77	38.7k	((p2 != 'a') && (p2 != 'b')))
78	29.4k	p2--;
79	9.28k	if (p2 == op_str_ptr) {
80	0	SStream_Flush(insn_asm, NULL);
81	0	SStream_concat0(insn_asm, "Invalid!");
82	0	return;
83	0	}
84	9.28k	if (*p2 == 'a')
85	4.25k	strncpy(tmp, "1T", sizeof(tmp));
86	5.03k	else
87	5.03k	strncpy(tmp, "2T", sizeof(tmp));
88	34.8k	} else {
89	34.8k	tmp[0] = '\0';
90	34.8k	}
91	44.1k	SStream mnem_post = { 0 };
92	44.1k	SStream_Init(&mnem_post);
93	44.1k	switch (tms320c64x->funit.unit) {
94	11.8k	case TMS320C64X_FUNIT_D:
95	11.8k	SStream_concat(&mnem_post, ".D%s%u", tmp,
96	11.8k	tms320c64x->funit.side);
97	11.8k	break;
98	8.78k	case TMS320C64X_FUNIT_L:
99	8.78k	SStream_concat(&mnem_post, ".L%s%u", tmp,
100	8.78k	tms320c64x->funit.side);
101	8.78k	break;
102	2.72k	case TMS320C64X_FUNIT_M:
103	2.72k	SStream_concat(&mnem_post, ".M%s%u", tmp,
104	2.72k	tms320c64x->funit.side);
105	2.72k	break;
106	19.3k	case TMS320C64X_FUNIT_S:
107	19.3k	SStream_concat(&mnem_post, ".S%s%u", tmp,
108	19.3k	tms320c64x->funit.side);
109	19.3k	break;
110	44.1k	}
111	44.1k	if (tms320c64x->funit.crosspath > 0)
112	10.8k	SStream_concat0(&mnem_post, "X");
113
114	44.1k	if (op_str_ptr != NULL) {
115		// There is an op_str
116	42.9k	SStream_concat1(&mnem_post, '\t');
117	42.9k	SStream_replc_str(insn_asm, '\t',
118	42.9k	SStream_rbuf(&mnem_post));
119	42.9k	}
120
121	44.1k	if (tms320c64x->parallel != 0)
122	23.0k	SStream_concat0(insn_asm, "\t\|\|");
123	44.1k	SStream_concat0(&ss, SStream_rbuf(insn_asm));
124	44.1k	SStream_Flush(insn_asm, NULL);
125	44.1k	SStream_concat0(insn_asm, SStream_rbuf(&ss));
126	44.1k	}
127	44.1k	}
128
129		#define PRINT_ALIAS_INSTR
130		#include "TMS320C64xGenAsmWriter.inc"
131
132		#define GET_INSTRINFO_ENUM
133		#include "TMS320C64xGenInstrInfo.inc"
134
135		static void printOperand(MCInst MI, unsigned OpNo, SStream O)
136	85.2k	{
137	85.2k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
138	85.2k	unsigned reg;
139
140	85.2k	if (MCOperand_isReg(Op)) {
141	59.9k	reg = MCOperand_getReg(Op);
142	59.9k	if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) &&
143	3.07k	(OpNo == 1)) {
144	1.53k	switch (reg) {
145	989	case TMS320C64X_REG_EFR:
146	989	SStream_concat0(O, "EFR");
147	989	break;
148	350	case TMS320C64X_REG_IFR:
149	350	SStream_concat0(O, "IFR");
150	350	break;
151	199	default:
152	199	SStream_concat0(O, getRegisterName(reg));
153	199	break;
154	1.53k	}
155	58.3k	} else {
156	58.3k	SStream_concat0(O, getRegisterName(reg));
157	58.3k	}
158
159	59.9k	if (MI->csh->detail_opt) {
160	59.9k	MI->flat_insn->detail->tms320c64x
161	59.9k	.operands[MI->flat_insn->detail->tms320c64x
162	59.9k	.op_count]
163	59.9k	.type = TMS320C64X_OP_REG;
164	59.9k	MI->flat_insn->detail->tms320c64x
165	59.9k	.operands[MI->flat_insn->detail->tms320c64x
166	59.9k	.op_count]
167	59.9k	.reg = reg;
168	59.9k	MI->flat_insn->detail->tms320c64x.op_count++;
169	59.9k	}
170	59.9k	} else if (MCOperand_isImm(Op)) {
171	25.3k	int64_t Imm = MCOperand_getImm(Op);
172
173	25.3k	if (Imm >= 0) {
174	21.5k	if (Imm > HEX_THRESHOLD)
175	12.5k	SStream_concat(O, "0x%" PRIx64, Imm);
176	8.97k	else
177	8.97k	SStream_concat(O, "%" PRIu64, Imm);
178	21.5k	} else {
179	3.80k	if (Imm < -HEX_THRESHOLD)
180	3.01k	SStream_concat(O, "-0x%" PRIx64, -Imm);
181	789	else
182	789	SStream_concat(O, "-%" PRIu64, -Imm);
183	3.80k	}
184
185	25.3k	if (MI->csh->detail_opt) {
186	25.3k	MI->flat_insn->detail->tms320c64x
187	25.3k	.operands[MI->flat_insn->detail->tms320c64x
188	25.3k	.op_count]
189	25.3k	.type = TMS320C64X_OP_IMM;
190	25.3k	MI->flat_insn->detail->tms320c64x
191	25.3k	.operands[MI->flat_insn->detail->tms320c64x
192	25.3k	.op_count]
193	25.3k	.imm = Imm;
194	25.3k	MI->flat_insn->detail->tms320c64x.op_count++;
195	25.3k	}
196	25.3k	}
197	85.2k	}
198
199		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O)
200	4.25k	{
201	4.25k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
202	4.25k	int64_t Val = MCOperand_getImm(Op);
203	4.25k	unsigned scaled, base, offset, mode, unit;
204	4.25k	cs_tms320c64x *tms320c64x;
205	4.25k	char st, nd;
206
207	4.25k	scaled = (Val >> 19) & 1;
208	4.25k	base = (Val >> 12) & 0x7f;
209	4.25k	offset = (Val >> 5) & 0x7f;
210	4.25k	mode = (Val >> 1) & 0xf;
211	4.25k	unit = Val & 1;
212
213	4.25k	if (scaled) {
214	3.56k	st = '[';
215	3.56k	nd = ']';
216	3.56k	} else {
217	689	st = '(';
218	689	nd = ')';
219	689	}
220
221	4.25k	switch (mode) {
222	739	case 0:
223	739	SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st,
224	739	offset, nd);
225	739	break;
226	352	case 1:
227	352	SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st,
228	352	offset, nd);
229	352	break;
230	152	case 4:
231	152	SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st,
232	152	getRegisterName(offset), nd);
233	152	break;
234	85	case 5:
235	85	SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st,
236	85	getRegisterName(offset), nd);
237	85	break;
238	582	case 8:
239	582	SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st,
240	582	offset, nd);
241	582	break;
242	178	case 9:
243	178	SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st,
244	178	offset, nd);
245	178	break;
246	437	case 10:
247	437	SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st,
248	437	offset, nd);
249	437	break;
250	609	case 11:
251	609	SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st,
252	609	offset, nd);
253	609	break;
254	258	case 12:
255	258	SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st,
256	258	getRegisterName(offset), nd);
257	258	break;
258	135	case 13:
259	135	SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st,
260	135	getRegisterName(offset), nd);
261	135	break;
262	149	case 14:
263	149	SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st,
264	149	getRegisterName(offset), nd);
265	149	break;
266	582	case 15:
267	582	SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st,
268	582	getRegisterName(offset), nd);
269	582	break;
270	4.25k	}
271
272	4.25k	if (MI->csh->detail_opt) {
273	4.25k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
274
275	4.25k	tms320c64x->operands[tms320c64x->op_count].type =
276	4.25k	TMS320C64X_OP_MEM;
277	4.25k	tms320c64x->operands[tms320c64x->op_count].mem.base = base;
278	4.25k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
279	4.25k	tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
280	4.25k	tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
281	4.25k	switch (mode) {
282	739	case 0:
283	739	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
284	739	TMS320C64X_MEM_DISP_CONSTANT;
285	739	tms320c64x->operands[tms320c64x->op_count]
286	739	.mem.direction = TMS320C64X_MEM_DIR_BW;
287	739	tms320c64x->operands[tms320c64x->op_count].mem.modify =
288	739	TMS320C64X_MEM_MOD_NO;
289	739	break;
290	352	case 1:
291	352	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
292	352	TMS320C64X_MEM_DISP_CONSTANT;
293	352	tms320c64x->operands[tms320c64x->op_count]
294	352	.mem.direction = TMS320C64X_MEM_DIR_FW;
295	352	tms320c64x->operands[tms320c64x->op_count].mem.modify =
296	352	TMS320C64X_MEM_MOD_NO;
297	352	break;
298	152	case 4:
299	152	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
300	152	TMS320C64X_MEM_DISP_REGISTER;
301	152	tms320c64x->operands[tms320c64x->op_count]
302	152	.mem.direction = TMS320C64X_MEM_DIR_BW;
303	152	tms320c64x->operands[tms320c64x->op_count].mem.modify =
304	152	TMS320C64X_MEM_MOD_NO;
305	152	break;
306	85	case 5:
307	85	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
308	85	TMS320C64X_MEM_DISP_REGISTER;
309	85	tms320c64x->operands[tms320c64x->op_count]
310	85	.mem.direction = TMS320C64X_MEM_DIR_FW;
311	85	tms320c64x->operands[tms320c64x->op_count].mem.modify =
312	85	TMS320C64X_MEM_MOD_NO;
313	85	break;
314	582	case 8:
315	582	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
316	582	TMS320C64X_MEM_DISP_CONSTANT;
317	582	tms320c64x->operands[tms320c64x->op_count]
318	582	.mem.direction = TMS320C64X_MEM_DIR_BW;
319	582	tms320c64x->operands[tms320c64x->op_count].mem.modify =
320	582	TMS320C64X_MEM_MOD_PRE;
321	582	break;
322	178	case 9:
323	178	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
324	178	TMS320C64X_MEM_DISP_CONSTANT;
325	178	tms320c64x->operands[tms320c64x->op_count]
326	178	.mem.direction = TMS320C64X_MEM_DIR_FW;
327	178	tms320c64x->operands[tms320c64x->op_count].mem.modify =
328	178	TMS320C64X_MEM_MOD_PRE;
329	178	break;
330	437	case 10:
331	437	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
332	437	TMS320C64X_MEM_DISP_CONSTANT;
333	437	tms320c64x->operands[tms320c64x->op_count]
334	437	.mem.direction = TMS320C64X_MEM_DIR_BW;
335	437	tms320c64x->operands[tms320c64x->op_count].mem.modify =
336	437	TMS320C64X_MEM_MOD_POST;
337	437	break;
338	609	case 11:
339	609	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
340	609	TMS320C64X_MEM_DISP_CONSTANT;
341	609	tms320c64x->operands[tms320c64x->op_count]
342	609	.mem.direction = TMS320C64X_MEM_DIR_FW;
343	609	tms320c64x->operands[tms320c64x->op_count].mem.modify =
344	609	TMS320C64X_MEM_MOD_POST;
345	609	break;
346	258	case 12:
347	258	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
348	258	TMS320C64X_MEM_DISP_REGISTER;
349	258	tms320c64x->operands[tms320c64x->op_count]
350	258	.mem.direction = TMS320C64X_MEM_DIR_BW;
351	258	tms320c64x->operands[tms320c64x->op_count].mem.modify =
352	258	TMS320C64X_MEM_MOD_PRE;
353	258	break;
354	135	case 13:
355	135	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
356	135	TMS320C64X_MEM_DISP_REGISTER;
357	135	tms320c64x->operands[tms320c64x->op_count]
358	135	.mem.direction = TMS320C64X_MEM_DIR_FW;
359	135	tms320c64x->operands[tms320c64x->op_count].mem.modify =
360	135	TMS320C64X_MEM_MOD_PRE;
361	135	break;
362	149	case 14:
363	149	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
364	149	TMS320C64X_MEM_DISP_REGISTER;
365	149	tms320c64x->operands[tms320c64x->op_count]
366	149	.mem.direction = TMS320C64X_MEM_DIR_BW;
367	149	tms320c64x->operands[tms320c64x->op_count].mem.modify =
368	149	TMS320C64X_MEM_MOD_POST;
369	149	break;
370	582	case 15:
371	582	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
372	582	TMS320C64X_MEM_DISP_REGISTER;
373	582	tms320c64x->operands[tms320c64x->op_count]
374	582	.mem.direction = TMS320C64X_MEM_DIR_FW;
375	582	tms320c64x->operands[tms320c64x->op_count].mem.modify =
376	582	TMS320C64X_MEM_MOD_POST;
377	582	break;
378	4.25k	}
379	4.25k	tms320c64x->op_count++;
380	4.25k	}
381	4.25k	}
382
383		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O)
384	5.03k	{
385	5.03k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
386	5.03k	int64_t Val = MCOperand_getImm(Op);
387	5.03k	uint16_t offset;
388	5.03k	unsigned basereg;
389	5.03k	cs_tms320c64x *tms320c64x;
390
391	5.03k	basereg = Val & 0x7f;
392	5.03k	offset = (Val >> 7) & 0x7fff;
393	5.03k	SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);
394
395	5.03k	if (MI->csh->detail_opt) {
396	5.03k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
397
398	5.03k	tms320c64x->operands[tms320c64x->op_count].type =
399	5.03k	TMS320C64X_OP_MEM;
400	5.03k	tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
401	5.03k	tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
402	5.03k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
403	5.03k	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
404	5.03k	TMS320C64X_MEM_DISP_CONSTANT;
405	5.03k	tms320c64x->operands[tms320c64x->op_count].mem.direction =
406	5.03k	TMS320C64X_MEM_DIR_FW;
407	5.03k	tms320c64x->operands[tms320c64x->op_count].mem.modify =
408	5.03k	TMS320C64X_MEM_MOD_NO;
409	5.03k	tms320c64x->op_count++;
410	5.03k	}
411	5.03k	}
412
413		static void printRegPair(MCInst MI, unsigned OpNo, SStream O)
414	10.3k	{
415	10.3k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
416	10.3k	unsigned reg = MCOperand_getReg(Op);
417	10.3k	cs_tms320c64x *tms320c64x;
418
419	10.3k	SStream_concat(O, "%s:%s", getRegisterName(reg + 1),
420	10.3k	getRegisterName(reg));
421
422	10.3k	if (MI->csh->detail_opt) {
423	10.3k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
424
425	10.3k	tms320c64x->operands[tms320c64x->op_count].type =
426	10.3k	TMS320C64X_OP_REGPAIR;
427	10.3k	tms320c64x->operands[tms320c64x->op_count].reg = reg;
428	10.3k	tms320c64x->op_count++;
429	10.3k	}
430	10.3k	}
431
432		static bool printAliasInstruction(MCInst MI, SStream O, MCRegisterInfo *MRI)
433	44.1k	{
434	44.1k	unsigned opcode = MCInst_getOpcode(MI);
435	44.1k	MCOperand *op;
436
437	44.1k	switch (opcode) {
438		/* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
439	276	case TMS320C64x_ADD_d2_rir:
440		/* ADD.L -i, x, y -> SUB.L x, i, y */
441	492	case TMS320C64x_ADD_l1_irr:
442	795	case TMS320C64x_ADD_l1_ipp:
443		/* ADD.S -i, x, y -> SUB.S x, i, y */
444	1.40k	case TMS320C64x_ADD_s1_irr:
445	1.40k	if ((MCInst_getNumOperands(MI) == 3) &&
446	1.40k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
447	1.40k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
448	1.40k	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
449	1.40k	(MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
450	142	MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
451	142	op = MCInst_getOperand(MI, 2);
452	142	MCOperand_setImm(op, -MCOperand_getImm(op));
453
454	142	SStream_concat0(O, "SUB\t");
455	142	printOperand(MI, 1, O);
456	142	SStream_concat0(O, ", ");
457	142	printOperand(MI, 2, O);
458	142	SStream_concat0(O, ", ");
459	142	printOperand(MI, 0, O);
460
461	142	return true;
462	142	}
463	1.26k	break;
464	44.1k	}
465	43.9k	switch (opcode) {
466		/* ADD.D 0, x, y -> MV.D x, y */
467	285	case TMS320C64x_ADD_d1_rir:
468		/* OR.D x, 0, y -> MV.D x, y */
469	669	case TMS320C64x_OR_d2_rir:
470		/* ADD.L 0, x, y -> MV.L x, y */
471	849	case TMS320C64x_ADD_l1_irr:
472	1.14k	case TMS320C64x_ADD_l1_ipp:
473		/* OR.L 0, x, y -> MV.L x, y */
474	1.22k	case TMS320C64x_OR_l1_irr:
475		/* ADD.S 0, x, y -> MV.S x, y */
476	1.80k	case TMS320C64x_ADD_s1_irr:
477		/* OR.S 0, x, y -> MV.S x, y */
478	1.94k	case TMS320C64x_OR_s1_irr:
479	1.94k	if ((MCInst_getNumOperands(MI) == 3) &&
480	1.94k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
481	1.94k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
482	1.94k	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
483	1.94k	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
484	130	MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
485	130	MI->size--;
486
487	130	SStream_concat0(O, "MV\t");
488	130	printOperand(MI, 1, O);
489	130	SStream_concat0(O, ", ");
490	130	printOperand(MI, 0, O);
491
492	130	return true;
493	130	}
494	1.81k	break;
495	43.9k	}
496	43.8k	switch (opcode) {
497		/* XOR.D -1, x, y -> NOT.D x, y */
498	115	case TMS320C64x_XOR_d2_rir:
499		/* XOR.L -1, x, y -> NOT.L x, y */
500	460	case TMS320C64x_XOR_l1_irr:
501		/* XOR.S -1, x, y -> NOT.S x, y */
502	764	case TMS320C64x_XOR_s1_irr:
503	764	if ((MCInst_getNumOperands(MI) == 3) &&
504	764	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
505	764	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
506	764	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
507	764	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
508	216	MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
509	216	MI->size--;
510
511	216	SStream_concat0(O, "NOT\t");
512	216	printOperand(MI, 1, O);
513	216	SStream_concat0(O, ", ");
514	216	printOperand(MI, 0, O);
515
516	216	return true;
517	216	}
518	548	break;
519	43.8k	}
520	43.6k	switch (opcode) {
521		/* MVK.D 0, x -> ZERO.D x */
522	247	case TMS320C64x_MVK_d1_rr:
523		/* MVK.L 0, x -> ZERO.L x */
524	864	case TMS320C64x_MVK_l2_ir:
525	864	if ((MCInst_getNumOperands(MI) == 2) &&
526	864	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
527	864	MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
528	864	(MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
529	202	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
530	202	MI->size--;
531
532	202	SStream_concat0(O, "ZERO\t");
533	202	printOperand(MI, 0, O);
534
535	202	return true;
536	202	}
537	662	break;
538	43.6k	}
539	43.4k	switch (opcode) {
540		/* SUB.L x, x, y -> ZERO.L y */
541	276	case TMS320C64x_SUB_l1_rrp_x1:
542		/* SUB.S x, x, y -> ZERO.S y */
543	367	case TMS320C64x_SUB_s1_rrr:
544	367	if ((MCInst_getNumOperands(MI) == 3) &&
545	367	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
546	367	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
547	367	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
548	367	(MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
549	367	MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
550	83	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
551	83	MI->size -= 2;
552
553	83	SStream_concat0(O, "ZERO\t");
554	83	printOperand(MI, 0, O);
555
556	83	return true;
557	83	}
558	284	break;
559	43.4k	}
560	43.3k	switch (opcode) {
561		/* SUB.L 0, x, y -> NEG.L x, y */
562	227	case TMS320C64x_SUB_l1_irr:
563	380	case TMS320C64x_SUB_l1_ipp:
564		/* SUB.S 0, x, y -> NEG.S x, y */
565	452	case TMS320C64x_SUB_s1_irr:
566	452	if ((MCInst_getNumOperands(MI) == 3) &&
567	452	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
568	452	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
569	452	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
570	452	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
571	167	MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
572	167	MI->size--;
573
574	167	SStream_concat0(O, "NEG\t");
575	167	printOperand(MI, 1, O);
576	167	SStream_concat0(O, ", ");
577	167	printOperand(MI, 0, O);
578
579	167	return true;
580	167	}
581	285	break;
582	43.3k	}
583	43.1k	switch (opcode) {
584		/* PACKLH2.L x, x, y -> SWAP2.L x, y */
585	233	case TMS320C64x_PACKLH2_l1_rrr_x2:
586		/* PACKLH2.S x, x, y -> SWAP2.S x, y */
587	593	case TMS320C64x_PACKLH2_s1_rrr:
588	593	if ((MCInst_getNumOperands(MI) == 3) &&
589	593	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
590	593	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
591	593	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
592	593	(MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
593	593	MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
594	344	MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
595	344	MI->size--;
596
597	344	SStream_concat0(O, "SWAP2\t");
598	344	printOperand(MI, 1, O);
599	344	SStream_concat0(O, ", ");
600	344	printOperand(MI, 0, O);
601
602	344	return true;
603	344	}
604	249	break;
605	43.1k	}
606	42.8k	switch (opcode) {
607		/* NOP 16 -> IDLE */
608		/* NOP 1 -> NOP */
609	1.38k	case TMS320C64x_NOP_n:
610	1.38k	if ((MCInst_getNumOperands(MI) == 1) &&
611	1.38k	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
612	1.38k	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
613	329	MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
614	329	MI->size--;
615
616	329	SStream_concat0(O, "IDLE");
617
618	329	return true;
619	329	}
620	1.05k	if ((MCInst_getNumOperands(MI) == 1) &&
621	1.05k	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
622	1.05k	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
623	862	MI->size--;
624
625	862	SStream_concat0(O, "NOP");
626
627	862	return true;
628	862	}
629	194	break;
630	42.8k	}
631
632	41.6k	return false;
633	42.8k	}
634
635		void TMS320C64x_printInst(MCInst MI, SStream O, void *Info)
636	44.1k	{
637	44.1k	if (!printAliasInstruction(MI, O, Info))
638	41.6k	printInstruction(MI, O, Info);
639	44.1k	}
640
641		#endif