/src/capstonenext/arch/RISCV/RISCVDisassemblerExtension.c

Source
#include "RISCVDisassemblerExtension.h"

#define GET_SUBTARGETINFO_ENUM
#include "RISCVGenSubtargetInfo.inc"

bool RISCV_getFeatureBits(unsigned int mode, unsigned int feature)
{
  if (feature == RISCV_FeatureNoRVCHints) {
    return false;
  }

  switch (feature) {
  case RISCV_Feature32Bit:
    return mode & CS_MODE_RISCV32;

  case RISCV_Feature64Bit:
    return mode & CS_MODE_RISCV64;

  case RISCV_FeatureStdExtF:
  case RISCV_FeatureStdExtD:
    return mode & CS_MODE_RISCV_FD;

  case RISCV_FeatureStdExtV:
    return mode & CS_MODE_RISCV_V;

  case RISCV_FeatureStdExtZfinx:
  case RISCV_FeatureStdExtZdinx:
  case RISCV_FeatureStdExtZhinx:
  case RISCV_FeatureStdExtZhinxmin:
    return mode & CS_MODE_RISCV_ZFINX;

  case RISCV_FeatureStdExtC:
    return mode & CS_MODE_RISCV_C;

  case RISCV_FeatureStdExtZcmp:
  case RISCV_FeatureStdExtZcmt:
  case RISCV_FeatureStdExtZce:
    return mode & CS_MODE_RISCV_ZCMP_ZCMT_ZCE;

  case RISCV_FeatureStdExtZicfiss:
    return mode & CS_MODE_RISCV_ZICFISS;

  case RISCV_FeatureRVE:
    return mode & CS_MODE_RISCV_E;

  case RISCV_FeatureStdExtA:
    return mode & CS_MODE_RISCV_A;

  case RISCV_FeatureVendorXCVelw:
    return mode & CS_MODE_RISCV_COREV;

  case RISCV_FeatureVendorXSfvcp:
  case RISCV_FeatureVendorXSfvfnrclipxfqf:
  case RISCV_FeatureVendorXSfvfwmaccqqq:
  case RISCV_FeatureVendorXSfvqmaccdod:
  case RISCV_FeatureVendorXSfvqmaccqoq:
    return mode & CS_MODE_RISCV_SIFIVE;

  case RISCV_FeatureVendorXTHeadBa:
  case RISCV_FeatureVendorXTHeadBb:
  case RISCV_FeatureVendorXTHeadBs:
  case RISCV_FeatureVendorXTHeadCmo:
  case RISCV_FeatureVendorXTHeadCondMov:
  case RISCV_FeatureVendorXTHeadFMemIdx:
  case RISCV_FeatureVendorXTHeadMac:
  case RISCV_FeatureVendorXTHeadMemIdx:
  case RISCV_FeatureVendorXTHeadMemPair:
  case RISCV_FeatureVendorXTHeadSync:
  case RISCV_FeatureVendorXTHeadVdot:
    return mode & CS_MODE_RISCV_THEAD;

  case RISCV_FeatureStdExtZba:
    return mode & CS_MODE_RISCV_ZBA;
  case RISCV_FeatureStdExtZbb:
    return mode & CS_MODE_RISCV_ZBB;
  case RISCV_FeatureStdExtZbc:
    return mode & CS_MODE_RISCV_ZBC;
  case RISCV_FeatureStdExtZbkb:
    return mode & CS_MODE_RISCV_ZBKB;
  case RISCV_FeatureStdExtZbkc:
    return mode & CS_MODE_RISCV_ZBKC;
  case RISCV_FeatureStdExtZbkx:
    return mode & CS_MODE_RISCV_ZBKX;
  case RISCV_FeatureStdExtZbs:
    return mode & CS_MODE_RISCV_ZBS;
  default:
    // support everything by default
    return true;
  }
}

Line	Count	Source
1		#include "RISCVDisassemblerExtension.h"
2
3		#define GET_SUBTARGETINFO_ENUM
4		#include "RISCVGenSubtargetInfo.inc"
5
6		bool RISCV_getFeatureBits(unsigned int mode, unsigned int feature)
7	276k	{
8	276k	if (feature == RISCV_FeatureNoRVCHints) {
9	3.95k	return false;
10	3.95k	}
11
12	272k	switch (feature) {
13	0	case RISCV_Feature32Bit:
14	0	return mode & CS_MODE_RISCV32;
15
16	34.4k	case RISCV_Feature64Bit:
17	34.4k	return mode & CS_MODE_RISCV64;
18
19	85	case RISCV_FeatureStdExtF:
20	143	case RISCV_FeatureStdExtD:
21	143	return mode & CS_MODE_RISCV_FD;
22
23	0	case RISCV_FeatureStdExtV:
24	0	return mode & CS_MODE_RISCV_V;
25
26	4.28k	case RISCV_FeatureStdExtZfinx:
27	8.60k	case RISCV_FeatureStdExtZdinx:
28	8.60k	case RISCV_FeatureStdExtZhinx:
29	8.60k	case RISCV_FeatureStdExtZhinxmin:
30	8.60k	return mode & CS_MODE_RISCV_ZFINX;
31
32	34.0k	case RISCV_FeatureStdExtC:
33	34.0k	return mode & CS_MODE_RISCV_C;
34
35	9.94k	case RISCV_FeatureStdExtZcmp:
36	19.8k	case RISCV_FeatureStdExtZcmt:
37	19.8k	case RISCV_FeatureStdExtZce:
38	19.8k	return mode & CS_MODE_RISCV_ZCMP_ZCMT_ZCE;
39
40	9.94k	case RISCV_FeatureStdExtZicfiss:
41	9.94k	return mode & CS_MODE_RISCV_ZICFISS;
42
43	10.5k	case RISCV_FeatureRVE:
44	10.5k	return mode & CS_MODE_RISCV_E;
45
46	2	case RISCV_FeatureStdExtA:
47	2	return mode & CS_MODE_RISCV_A;
48
49	4.27k	case RISCV_FeatureVendorXCVelw:
50	4.27k	return mode & CS_MODE_RISCV_COREV;
51
52	4.28k	case RISCV_FeatureVendorXSfvcp:
53	8.57k	case RISCV_FeatureVendorXSfvfnrclipxfqf:
54	12.8k	case RISCV_FeatureVendorXSfvfwmaccqqq:
55	17.1k	case RISCV_FeatureVendorXSfvqmaccdod:
56	21.4k	case RISCV_FeatureVendorXSfvqmaccqoq:
57	21.4k	return mode & CS_MODE_RISCV_SIFIVE;
58
59	4.28k	case RISCV_FeatureVendorXTHeadBa:
60	8.57k	case RISCV_FeatureVendorXTHeadBb:
61	12.8k	case RISCV_FeatureVendorXTHeadBs:
62	17.1k	case RISCV_FeatureVendorXTHeadCmo:
63	21.4k	case RISCV_FeatureVendorXTHeadCondMov:
64	25.7k	case RISCV_FeatureVendorXTHeadFMemIdx:
65	30.0k	case RISCV_FeatureVendorXTHeadMac:
66	34.3k	case RISCV_FeatureVendorXTHeadMemIdx:
67	38.6k	case RISCV_FeatureVendorXTHeadMemPair:
68	42.8k	case RISCV_FeatureVendorXTHeadSync:
69	47.1k	case RISCV_FeatureVendorXTHeadVdot:
70	47.1k	return mode & CS_MODE_RISCV_THEAD;
71
72	2	case RISCV_FeatureStdExtZba:
73	2	return mode & CS_MODE_RISCV_ZBA;
74	3	case RISCV_FeatureStdExtZbb:
75	3	return mode & CS_MODE_RISCV_ZBB;
76	0	case RISCV_FeatureStdExtZbc:
77	0	return mode & CS_MODE_RISCV_ZBC;
78	3	case RISCV_FeatureStdExtZbkb:
79	3	return mode & CS_MODE_RISCV_ZBKB;
80	0	case RISCV_FeatureStdExtZbkc:
81	0	return mode & CS_MODE_RISCV_ZBKC;
82	1	case RISCV_FeatureStdExtZbkx:
83	1	return mode & CS_MODE_RISCV_ZBKX;
84	0	case RISCV_FeatureStdExtZbs:
85	0	return mode & CS_MODE_RISCV_ZBS;
86	81.7k	default:
87		// support everything by default
88		return true;
89	272k	}
90	272k	}

Coverage Report

Created: 2026-03-03 06:14