Coverage Report

Created: 2026-03-03 06:14

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/capstonenext/arch/SystemZ/SystemZMapping.c
Line
Count
Source
1
/* Capstone Disassembly Engine */
2
/* By Rot127 <unisono@quyllur.org> 2022-2023 */
3
4
#ifdef CAPSTONE_HAS_SYSTEMZ
5
6
#include <stdio.h> // debug
7
#include <string.h>
8
9
#include "../../Mapping.h"
10
#include "../../utils.h"
11
#include "../../cs_simple_types.h"
12
#include <capstone/cs_operand.h>
13
14
#include "SystemZMCTargetDesc.h"
15
#include "SystemZMapping.h"
16
#include "SystemZLinkage.h"
17
18
#ifndef CAPSTONE_DIET
19
20
static const char *const insn_name_maps[] = {
21
#include "SystemZGenCSMappingInsnName.inc"
22
};
23
24
static const name_map insn_alias_mnem_map[] = {
25
#include "SystemZGenCSAliasMnemMap.inc"
26
  { SYSTEMZ_INS_ALIAS_END, NULL },
27
};
28
29
static const map_insn_ops insn_operands[] = {
30
#include "SystemZGenCSMappingInsnOp.inc"
31
};
32
33
#endif
34
35
#define GET_REGINFO_MC_DESC
36
#include "SystemZGenRegisterInfo.inc"
37
38
const insn_map systemz_insns[] = {
39
#include "SystemZGenCSMappingInsn.inc"
40
};
41
42
void SystemZ_set_instr_map_data(MCInst *MI, const uint8_t *Bytes,
43
        size_t BytesLen)
44
58.5k
{
45
58.5k
  map_cs_id(MI, systemz_insns, ARR_SIZE(systemz_insns));
46
58.5k
  map_implicit_reads(MI, systemz_insns);
47
58.5k
  map_implicit_writes(MI, systemz_insns);
48
58.5k
  map_groups(MI, systemz_insns);
49
58.5k
  const systemz_suppl_info *suppl_info =
50
58.5k
    map_get_suppl_info(MI, systemz_insns);
51
58.5k
  if (suppl_info) {
52
58.5k
    SystemZ_get_detail(MI)->format = suppl_info->form;
53
58.5k
  }
54
58.5k
}
55
56
void SystemZ_init_mri(MCRegisterInfo *MRI)
57
1.93k
{
58
1.93k
  MCRegisterInfo_InitMCRegisterInfo(
59
1.93k
    MRI, SystemZRegDesc, AARCH64_REG_ENDING, 0, 0,
60
1.93k
    SystemZMCRegisterClasses, ARR_SIZE(SystemZMCRegisterClasses), 0,
61
1.93k
    0, SystemZRegDiffLists, 0, SystemZSubRegIdxLists,
62
1.93k
    ARR_SIZE(SystemZSubRegIdxLists), 0);
63
1.93k
}
64
65
const char *SystemZ_reg_name(csh handle, unsigned int reg)
66
33.5k
{
67
33.5k
  return SystemZ_LLVM_getRegisterName(reg);
68
33.5k
}
69
70
void SystemZ_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
71
57.1k
{
72
57.1k
  MI->MRI = (MCRegisterInfo *)info;
73
57.1k
  MI->fillDetailOps = detail_is_set(MI);
74
57.1k
  SystemZ_LLVM_printInstruction(MI, "", O);
75
57.1k
#ifndef CAPSTONE_DIET
76
57.1k
  map_set_alias_id(MI, O, insn_alias_mnem_map,
77
57.1k
       ARR_SIZE(insn_alias_mnem_map));
78
57.1k
#endif
79
57.1k
}
80
81
void SystemZ_init_cs_detail(MCInst *MI)
82
58.5k
{
83
58.5k
  if (!detail_is_set(MI)) {
84
0
    return;
85
0
  }
86
58.5k
  memset(get_detail(MI), 0, sizeof(cs_detail));
87
58.5k
  if (detail_is_set(MI)) {
88
58.5k
    SystemZ_get_detail(MI)->cc = SYSTEMZ_CC_INVALID;
89
58.5k
  }
90
58.5k
}
91
92
bool SystemZ_getInstruction(csh handle, const uint8_t *bytes, size_t bytes_len,
93
          MCInst *MI, uint16_t *size, uint64_t address,
94
          void *info)
95
58.5k
{
96
58.5k
  SystemZ_init_cs_detail(MI);
97
58.5k
  MI->MRI = (MCRegisterInfo *)info;
98
58.5k
  DecodeStatus Result = SystemZ_LLVM_getInstruction(
99
58.5k
    handle, bytes, bytes_len, MI, size, address, info);
100
58.5k
  SystemZ_set_instr_map_data(MI, bytes, bytes_len);
101
58.5k
  if (Result == MCDisassembler_SoftFail) {
102
0
    MCInst_setSoftFail(MI);
103
0
  }
104
58.5k
  return Result != MCDisassembler_Fail;
105
58.5k
}
106
107
// given internal insn id, return public instruction info
108
void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
109
57.1k
{
110
  // We do this after Instruction disassembly.
111
57.1k
}
112
113
const char *SystemZ_insn_name(csh handle, unsigned int id)
114
57.1k
{
115
57.1k
#ifndef CAPSTONE_DIET
116
57.1k
  if (id < SYSTEMZ_INS_ALIAS_END && id > SYSTEMZ_INS_ALIAS_BEGIN) {
117
0
    if (id - SYSTEMZ_INS_ALIAS_BEGIN >=
118
0
        ARR_SIZE(insn_alias_mnem_map))
119
0
      return NULL;
120
121
0
    return insn_alias_mnem_map[id - SYSTEMZ_INS_ALIAS_BEGIN - 1]
122
0
      .name;
123
0
  }
124
57.1k
  if (id >= SYSTEMZ_INS_ENDING)
125
0
    return NULL;
126
127
57.1k
  if (id < ARR_SIZE(insn_name_maps))
128
57.1k
    return insn_name_maps[id];
129
130
  // not found
131
0
  return NULL;
132
#else
133
  return NULL;
134
#endif
135
57.1k
}
136
137
#ifndef CAPSTONE_DIET
138
static const name_map group_name_maps[] = {
139
  // generic groups
140
  { SYSTEMZ_GRP_INVALID, NULL },
141
  { SYSTEMZ_GRP_JUMP, "jump" },
142
  { SYSTEMZ_GRP_CALL, "call" },
143
  { SYSTEMZ_GRP_RET, "return" },
144
  { SYSTEMZ_GRP_INT, "int" },
145
  { SYSTEMZ_GRP_IRET, "iret" },
146
  { SYSTEMZ_GRP_PRIVILEGE, "privilege" },
147
  { SYSTEMZ_GRP_BRANCH_RELATIVE, "branch_relative" },
148
149
#include "SystemZGenCSFeatureName.inc"
150
};
151
#endif
152
153
const char *SystemZ_group_name(csh handle, unsigned int id)
154
19.6k
{
155
19.6k
#ifndef CAPSTONE_DIET
156
19.6k
  return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
157
#else
158
  return NULL;
159
#endif
160
19.6k
}
161
162
void SystemZ_add_cs_detail_0(MCInst *MI, int /* systemz_op_group */ op_group,
163
           size_t op_num)
164
141k
{
165
141k
#ifndef CAPSTONE_DIET
166
141k
  if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
167
0
    return;
168
169
141k
  switch (op_group) {
170
0
  default:
171
0
    printf("Operand group %d not handled\n", op_group);
172
0
    break;
173
84.7k
  case SystemZ_OP_GROUP_Operand: {
174
84.7k
    cs_op_type secondary_op_type = map_get_op_type(MI, op_num) &
175
84.7k
                 ~(CS_OP_MEM | CS_OP_BOUND);
176
84.7k
    if (secondary_op_type == CS_OP_IMM) {
177
0
      SystemZ_set_detail_op_imm(
178
0
        MI, op_num, MCInst_getOpVal(MI, op_num), 0);
179
84.7k
    } else if (secondary_op_type == CS_OP_REG) {
180
84.7k
      SystemZ_set_detail_op_reg(MI, op_num,
181
84.7k
              MCInst_getOpVal(MI, op_num));
182
84.7k
    } else {
183
0
      CS_ASSERT_RET(0 && "Op type not handled.");
184
0
    }
185
84.7k
    break;
186
84.7k
  }
187
84.7k
  case SystemZ_OP_GROUP_Cond4Operand: {
188
0
    systemz_cc cc = MCInst_getOpVal(MI, op_num);
189
0
    SystemZ_get_detail(MI)->cc = cc;
190
0
    break;
191
84.7k
  }
192
16.1k
  case SystemZ_OP_GROUP_BDAddrOperand:
193
16.1k
    CS_ASSERT_RET(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
194
16.1k
    CS_ASSERT_RET(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
195
16.1k
    CS_ASSERT_RET(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
196
16.1k
    CS_ASSERT_RET(
197
16.1k
      MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
198
16.1k
    SystemZ_set_detail_op_mem(MI, op_num,
199
16.1k
            MCInst_getOpVal(MI, (op_num)),
200
16.1k
            MCInst_getOpVal(MI, (op_num + 1)), 0,
201
16.1k
            0, SYSTEMZ_AM_BD);
202
16.1k
    break;
203
709
  case SystemZ_OP_GROUP_BDVAddrOperand:
204
12.4k
  case SystemZ_OP_GROUP_BDXAddrOperand: {
205
12.4k
    CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
206
12.4k
    CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
207
12.4k
    CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
208
12.4k
    CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
209
12.4k
    CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
210
12.4k
    CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2))));
211
12.4k
    SystemZ_set_detail_op_mem(
212
12.4k
      MI, op_num, MCInst_getOpVal(MI, (op_num)),
213
12.4k
      MCInst_getOpVal(MI, (op_num + 1)), 0,
214
12.4k
      MCInst_getOpVal(MI, (op_num + 2)),
215
12.4k
      (op_group == SystemZ_OP_GROUP_BDXAddrOperand ?
216
11.7k
         SYSTEMZ_AM_BDX :
217
12.4k
         SYSTEMZ_AM_BDV));
218
12.4k
    break;
219
709
  }
220
3.20k
  case SystemZ_OP_GROUP_BDLAddrOperand:
221
3.20k
    CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
222
3.20k
    CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
223
3.20k
    CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
224
3.20k
    CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
225
3.20k
    CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
226
3.20k
    CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 2))));
227
3.20k
    SystemZ_set_detail_op_mem(MI, op_num,
228
3.20k
            MCInst_getOpVal(MI, (op_num)),
229
3.20k
            MCInst_getOpVal(MI, (op_num + 1)),
230
3.20k
            MCInst_getOpVal(MI, (op_num + 2)), 0,
231
3.20k
            SYSTEMZ_AM_BDL);
232
3.20k
    break;
233
314
  case SystemZ_OP_GROUP_BDRAddrOperand:
234
314
    CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
235
314
    CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
236
314
    CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
237
314
    CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
238
314
    CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
239
314
    CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2))));
240
314
    SystemZ_set_detail_op_mem(MI, op_num,
241
314
            MCInst_getOpVal(MI, (op_num)),
242
314
            MCInst_getOpVal(MI, (op_num + 1)),
243
314
            MCInst_getOpVal(MI, (op_num + 2)), 0,
244
314
            SYSTEMZ_AM_BDL);
245
314
    break;
246
2.03k
  case SystemZ_OP_GROUP_PCRelOperand:
247
2.03k
    SystemZ_set_detail_op_imm(MI, op_num,
248
2.03k
            MCInst_getOpVal(MI, op_num), 0);
249
2.03k
    break;
250
641
  case SystemZ_OP_GROUP_U1ImmOperand:
251
641
    SystemZ_set_detail_op_imm(MI, op_num,
252
641
            MCInst_getOpVal(MI, op_num), 1);
253
641
    break;
254
586
  case SystemZ_OP_GROUP_U2ImmOperand:
255
586
    SystemZ_set_detail_op_imm(MI, op_num,
256
586
            MCInst_getOpVal(MI, op_num), 2);
257
586
    break;
258
423
  case SystemZ_OP_GROUP_U3ImmOperand:
259
423
    SystemZ_set_detail_op_imm(MI, op_num,
260
423
            MCInst_getOpVal(MI, op_num), 3);
261
423
    break;
262
13.2k
  case SystemZ_OP_GROUP_U4ImmOperand:
263
13.2k
    SystemZ_set_detail_op_imm(MI, op_num,
264
13.2k
            MCInst_getOpVal(MI, op_num), 4);
265
13.2k
    break;
266
3.28k
  case SystemZ_OP_GROUP_U8ImmOperand:
267
4.24k
  case SystemZ_OP_GROUP_S8ImmOperand:
268
4.24k
    SystemZ_set_detail_op_imm(MI, op_num,
269
4.24k
            MCInst_getOpVal(MI, op_num), 8);
270
4.24k
    break;
271
235
  case SystemZ_OP_GROUP_U12ImmOperand:
272
235
    SystemZ_set_detail_op_imm(MI, op_num,
273
235
            MCInst_getOpVal(MI, op_num), 12);
274
235
    break;
275
916
  case SystemZ_OP_GROUP_U16ImmOperand:
276
1.99k
  case SystemZ_OP_GROUP_S16ImmOperand:
277
1.99k
    SystemZ_set_detail_op_imm(MI, op_num,
278
1.99k
            MCInst_getOpVal(MI, op_num), 16);
279
1.99k
    break;
280
501
  case SystemZ_OP_GROUP_U32ImmOperand:
281
933
  case SystemZ_OP_GROUP_S32ImmOperand:
282
933
    SystemZ_set_detail_op_imm(MI, op_num,
283
933
            MCInst_getOpVal(MI, op_num), 32);
284
933
    break;
285
0
  case SystemZ_OP_GROUP_U48ImmOperand:
286
0
    SystemZ_set_detail_op_imm(MI, op_num,
287
0
            MCInst_getOpVal(MI, op_num), 48);
288
0
    break;
289
141k
  }
290
141k
#endif
291
141k
}
292
293
#ifndef CAPSTONE_DIET
294
295
void SystemZ_set_detail_op_imm(MCInst *MI, unsigned op_num, int64_t Imm,
296
             size_t width)
297
24.3k
{
298
24.3k
  if (!detail_is_set(MI))
299
0
    return;
300
24.3k
  CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_IMM);
301
302
24.3k
  SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_IMM;
303
24.3k
  SystemZ_get_detail_op(MI, 0)->imm = Imm;
304
24.3k
  SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
305
24.3k
  SystemZ_get_detail_op(MI, 0)->imm_width = width;
306
24.3k
  SystemZ_inc_op_count(MI);
307
24.3k
}
308
309
void SystemZ_set_detail_op_reg(MCInst *MI, unsigned op_num, systemz_reg Reg)
310
84.7k
{
311
84.7k
  if (!detail_is_set(MI))
312
0
    return;
313
84.7k
  CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_REG);
314
84.7k
  if (Reg == SYSTEMZ_REG_INVALID) {
315
    // This case is legal. The ISA says:
316
    // "
317
    // When the R1 field is not zero, bits 8-15 of the instruction designated
318
    // by the second-operand address are ORed with bits 56-63 of
319
    // general register R1. [...] When the R1 field is zero, no ORing takes place
320
    // "
321
    // This means we just save the neutral element for ORing, so 0.
322
307
    SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_IMM;
323
307
    SystemZ_get_detail_op(MI, 0)->imm = 0;
324
307
    SystemZ_get_detail_op(MI, 0)->access =
325
307
      map_get_op_access(MI, op_num);
326
307
    SystemZ_get_detail_op(MI, 0)->imm_width = 0;
327
307
    SystemZ_inc_op_count(MI);
328
307
    return;
329
307
  }
330
331
84.4k
  SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_REG;
332
84.4k
  SystemZ_get_detail_op(MI, 0)->reg = Reg;
333
84.4k
  SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
334
84.4k
  SystemZ_inc_op_count(MI);
335
84.4k
}
336
337
void SystemZ_set_detail_op_mem(MCInst *MI, unsigned op_num, systemz_reg base,
338
             int64_t disp, uint64_t length, systemz_reg index,
339
             systemz_addr_mode am)
340
32.1k
{
341
32.1k
  if (!detail_is_set(MI))
342
0
    return;
343
32.1k
  SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_MEM;
344
32.1k
  SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
345
32.1k
  SystemZ_get_detail_op(MI, 0)->mem.am = am;
346
32.1k
  switch (am) {
347
0
  default:
348
0
    CS_ASSERT(0 && "Address mode not handled\n");
349
0
    break;
350
16.1k
  case SYSTEMZ_AM_BD:
351
16.1k
    SystemZ_get_detail_op(MI, 0)->mem.base = base;
352
16.1k
    SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
353
16.1k
    break;
354
11.7k
  case SYSTEMZ_AM_BDX:
355
12.4k
  case SYSTEMZ_AM_BDV:
356
12.4k
    SystemZ_get_detail_op(MI, 0)->mem.base = base;
357
12.4k
    SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
358
12.4k
    SystemZ_get_detail_op(MI, 0)->mem.index = index;
359
12.4k
    break;
360
3.51k
  case SYSTEMZ_AM_BDL:
361
3.51k
    SystemZ_get_detail_op(MI, 0)->mem.base = base;
362
3.51k
    SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
363
3.51k
    SystemZ_get_detail_op(MI, 0)->mem.length = length;
364
3.51k
    break;
365
0
  case SYSTEMZ_AM_BDR:
366
0
    SystemZ_get_detail_op(MI, 0)->mem.base = base;
367
0
    SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
368
0
    SystemZ_get_detail_op(MI, 0)->mem.length = length;
369
0
    break;
370
32.1k
  }
371
32.1k
  SystemZ_inc_op_count(MI);
372
32.1k
}
373
374
#endif
375
376
#endif