/src/capstonenext/arch/MOS65XX/MOS65XXDisassembler.c

Source
/* Capstone Disassembly Engine */
/* MOS65XX Backend by Sebastian Macke <sebastian@macke.de> 2018 */

#include "capstone/mos65xx.h"
#include "MOS65XXDisassembler.h"
#include "MOS65XXDisassemblerInternals.h"

typedef struct OpInfo {
  mos65xx_insn ins;
  mos65xx_address_mode am;
  int operand_bytes;
} OpInfo;

static const struct OpInfo OpInfoTable[] = {

#include "m6502.inc"
#include "m65c02.inc"
#include "mw65c02.inc"
#include "m65816.inc"

};

#ifndef CAPSTONE_DIET
static const char *const RegNames[] = { "invalid", "A",  "X", "Y", "P",
          "SP",    "DP", "B", "K" };

static const char *const GroupNames[] = {
  NULL, "jump", "call", "ret", "int", "iret", "branch_relative"
};

typedef struct InstructionInfo {
  const char *name;
  mos65xx_group_type group_type;
  mos65xx_reg write, read;
  bool modifies_status;
} InstructionInfo;

static const struct InstructionInfo InstructionInfoTable[] = {

#include "instruction_info.inc"

};
#endif

#ifndef CAPSTONE_DIET
static void fillDetails(MCInst *MI, struct OpInfo opinfo, int cpu_type)
{
  int i;
  cs_detail *detail = MI->flat_insn->detail;

  InstructionInfo insinfo = InstructionInfoTable[opinfo.ins];

  detail->mos65xx.am = opinfo.am;
  detail->mos65xx.modifies_flags = insinfo.modifies_status;
  detail->groups_count = 0;
  detail->regs_read_count = 0;
  detail->regs_write_count = 0;
  detail->mos65xx.op_count = 0;

  if (insinfo.group_type != MOS65XX_GRP_INVALID) {
    detail->groups[detail->groups_count] = insinfo.group_type;
    detail->groups_count++;
  }

  if (opinfo.am == MOS65XX_AM_REL || opinfo.am == MOS65XX_AM_ZP_REL) {
    detail->groups[detail->groups_count] =
      MOS65XX_GRP_BRANCH_RELATIVE;
    detail->groups_count++;
  }

  if (insinfo.read != MOS65XX_REG_INVALID) {
    detail->regs_read[detail->regs_read_count++] = insinfo.read;
  } else
    switch (opinfo.am) {
    case MOS65XX_AM_ACC:
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_ACC;
      break;
    case MOS65XX_AM_ZP_Y:
    case MOS65XX_AM_ZP_IND_Y:
    case MOS65XX_AM_ABS_Y:
    case MOS65XX_AM_ZP_IND_LONG_Y:
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_Y;
      break;

    case MOS65XX_AM_ZP_X:
    case MOS65XX_AM_ZP_X_IND:
    case MOS65XX_AM_ABS_X:
    case MOS65XX_AM_ABS_X_IND:
    case MOS65XX_AM_ABS_LONG_X:
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_X;
      break;

    case MOS65XX_AM_SR:
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_SP;
      break;
    case MOS65XX_AM_SR_IND_Y:
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_SP;
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_Y;
      break;

    default:
      break;
    }

  if (insinfo.write != MOS65XX_REG_INVALID) {
    detail->regs_write[detail->regs_write_count++] = insinfo.write;
  } else if (opinfo.am == MOS65XX_AM_ACC) {
    detail->regs_write[detail->regs_write_count++] =
      MOS65XX_REG_ACC;
  }

  switch (opinfo.ins) {
  case MOS65XX_INS_ADC:
  case MOS65XX_INS_SBC:
  case MOS65XX_INS_ROL:
  case MOS65XX_INS_ROR:
    /* these read carry flag (and decimal for ADC/SBC) */
    detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_P;
    break;
  /* stack operations */
  case MOS65XX_INS_JSL:
  case MOS65XX_INS_JSR:
  case MOS65XX_INS_PEA:
  case MOS65XX_INS_PEI:
  case MOS65XX_INS_PER:
  case MOS65XX_INS_PHA:
  case MOS65XX_INS_PHB:
  case MOS65XX_INS_PHD:
  case MOS65XX_INS_PHK:
  case MOS65XX_INS_PHP:
  case MOS65XX_INS_PHX:
  case MOS65XX_INS_PHY:
  case MOS65XX_INS_PLA:
  case MOS65XX_INS_PLB:
  case MOS65XX_INS_PLD:
  case MOS65XX_INS_PLP:
  case MOS65XX_INS_PLX:
  case MOS65XX_INS_PLY:
  case MOS65XX_INS_RTI:
  case MOS65XX_INS_RTL:
  case MOS65XX_INS_RTS:
    detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP;
    detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_SP;
    break;
  default:
    break;
  }

  if (cpu_type == MOS65XX_CPU_TYPE_65816) {
    switch (opinfo.am) {
    case MOS65XX_AM_ZP:
    case MOS65XX_AM_ZP_X:
    case MOS65XX_AM_ZP_Y:
    case MOS65XX_AM_ZP_IND:
    case MOS65XX_AM_ZP_X_IND:
    case MOS65XX_AM_ZP_IND_Y:
    case MOS65XX_AM_ZP_IND_LONG:
    case MOS65XX_AM_ZP_IND_LONG_Y:
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_DP;
      break;
    case MOS65XX_AM_BLOCK:
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_ACC;
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_X;
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_Y;
      detail->regs_write[detail->regs_write_count++] =
        MOS65XX_REG_ACC;
      detail->regs_write[detail->regs_write_count++] =
        MOS65XX_REG_X;
      detail->regs_write[detail->regs_write_count++] =
        MOS65XX_REG_Y;
      detail->regs_write[detail->regs_write_count++] =
        MOS65XX_REG_B;
      break;
    default:
      break;
    }

    switch (opinfo.am) {
    case MOS65XX_AM_ZP_IND:
    case MOS65XX_AM_ZP_X_IND:
    case MOS65XX_AM_ZP_IND_Y:
    case MOS65XX_AM_ABS:
    case MOS65XX_AM_ABS_X:
    case MOS65XX_AM_ABS_Y:
    case MOS65XX_AM_ABS_X_IND:
      /* these depend on the databank to generate a 24-bit address */
      /* exceptions: PEA, PEI, and JMP (abs) */
      if (opinfo.ins == MOS65XX_INS_PEI ||
          opinfo.ins == MOS65XX_INS_PEA)
        break;
      detail->regs_read[detail->regs_read_count++] =
        MOS65XX_REG_B;
      break;
    default:
      break;
    }
  }

  if (insinfo.modifies_status) {
    detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_P;
  }

  switch (opinfo.am) {
  case MOS65XX_AM_IMP:
    break;
  case MOS65XX_AM_IMM:
    detail->mos65xx.operands[detail->mos65xx.op_count].type =
      MOS65XX_OP_IMM;
    detail->mos65xx.operands[detail->mos65xx.op_count].imm =
      MI->Operands[0].ImmVal;
    detail->mos65xx.op_count++;
    break;
  case MOS65XX_AM_ACC:
    detail->mos65xx.operands[detail->mos65xx.op_count].type =
      MOS65XX_OP_REG;
    detail->mos65xx.operands[detail->mos65xx.op_count].reg =
      MOS65XX_REG_ACC;
    detail->mos65xx.op_count++;
    break;
  case MOS65XX_AM_REL: {
    int value = MI->Operands[0].ImmVal;
    if (MI->op1_size == 1)
      value = 2 + (signed char)value;
    else
      value = 3 + (signed short)value;
    detail->mos65xx.operands[detail->mos65xx.op_count].type =
      MOS65XX_OP_MEM;
    detail->mos65xx.operands[detail->mos65xx.op_count].mem =
      (MI->address + value) & 0xffff;
    detail->mos65xx.op_count++;
    break;
  }
  case MOS65XX_AM_ZP_REL: {
    int value = 3 + (signed char)MI->Operands[1].ImmVal;
    /* BBR0, zp, rel  and BBS0, zp, rel */
    detail->mos65xx.operands[detail->mos65xx.op_count].type =
      MOS65XX_OP_MEM;
    detail->mos65xx.operands[detail->mos65xx.op_count].mem =
      MI->Operands[0].ImmVal;
    detail->mos65xx.operands[detail->mos65xx.op_count + 1].type =
      MOS65XX_OP_MEM;
    detail->mos65xx.operands[detail->mos65xx.op_count + 1].mem =
      (MI->address + value) & 0xffff;
    detail->mos65xx.op_count += 2;
    break;
  }
  default:
    for (i = 0; i < MI->size; ++i) {
      detail->mos65xx.operands[detail->mos65xx.op_count].type =
        MOS65XX_OP_MEM;
      detail->mos65xx.operands[detail->mos65xx.op_count].mem =
        MI->Operands[i].ImmVal;
      detail->mos65xx.op_count++;
    }
    break;
  }
}
#endif

void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo)
{
#ifndef CAPSTONE_DIET
  unsigned int value;
  unsigned opcode = MCInst_getOpcode(MI);
  mos65xx_info *info = (mos65xx_info *)PrinterInfo;

  OpInfo opinfo = OpInfoTable[opcode];

  const char *prefix = info->hex_prefix ? info->hex_prefix : "0x";

  SStream_concat0(O, InstructionInfoTable[opinfo.ins].name);
  switch (opinfo.ins) {
  /* special case - bit included as part of the instruction name */
  case MOS65XX_INS_BBR:
  case MOS65XX_INS_BBS:
  case MOS65XX_INS_RMB:
  case MOS65XX_INS_SMB:
    SStream_concat(O, "%" PRId8, (opcode >> 4) & 0x07);
    break;
  default:
    break;
  }

  value = MI->Operands[0].ImmVal;

  switch (opinfo.am) {
  default:
    break;

  case MOS65XX_AM_IMP:
    break;

  case MOS65XX_AM_ACC:
    SStream_concat0(O, " a");
    break;

  case MOS65XX_AM_IMM:
    if (MI->imm_size == 1)
      SStream_concat(O, " #%s%02" PRIx32, prefix, value);
    else
      SStream_concat(O, " #%s%04" PRIx32, prefix, value);
    break;

  case MOS65XX_AM_ZP:
    SStream_concat(O, " %s%02" PRIx32, prefix, value);
    break;

  case MOS65XX_AM_ABS:
    SStream_concat(O, " %s%04" PRIx32, prefix, value);
    break;

  case MOS65XX_AM_ABS_LONG_X:
    SStream_concat(O, " %s%06" PRIx32 ", x", prefix, value);
    break;

  case MOS65XX_AM_INT:
    SStream_concat(O, " %s%02" PRIx32, prefix, value);
    break;

  case MOS65XX_AM_ABS_X:
    SStream_concat(O, " %s%04" PRIx32 ", x", prefix, value);
    break;

  case MOS65XX_AM_ABS_Y:
    SStream_concat(O, " %s%04" PRIx32 ", y", prefix, value);
    break;

  case MOS65XX_AM_ABS_LONG:
    SStream_concat(O, " %s%06" PRIx32, prefix, value);
    break;

  case MOS65XX_AM_ZP_X:
    SStream_concat(O, " %s%02" PRIx32 ", x", prefix, value);
    break;

  case MOS65XX_AM_ZP_Y:
    SStream_concat(O, " %s%02" PRIx32 ", y", prefix, value);
    break;

  case MOS65XX_AM_REL: {
    if (MI->op1_size == 1)
      value = 2 + (int8_t)value;
    else
      value = 3 + (int16_t)value;

    uint32_t addr = MI->address;
    SStream_concat(O, " %s%04" PRIx16, prefix,
             (addr + value) & 0xffff);

    break;
  }
  case MOS65XX_AM_ABS_IND:
    SStream_concat(O, " (%s%04" PRIx32 ")", prefix, value);
    break;

  case MOS65XX_AM_ABS_X_IND:
    SStream_concat(O, " (%s%04" PRIx32 ", x)", prefix, value);
    break;

  case MOS65XX_AM_ABS_IND_LONG:
    SStream_concat(O, " [%s%04" PRIx32 "]", prefix, value);
    break;

  case MOS65XX_AM_ZP_IND:
    SStream_concat(O, " (%s%02" PRIx32 ")", prefix, value);
    break;

  case MOS65XX_AM_ZP_X_IND:
    SStream_concat(O, " (%s%02" PRIx32 ", x)", prefix, value);
    break;

  case MOS65XX_AM_ZP_IND_Y:
    SStream_concat(O, " (%s%02" PRIx32 "), y", prefix, value);
    break;

  case MOS65XX_AM_ZP_IND_LONG:
    SStream_concat(O, " [%s%02" PRIx32 "]", prefix, value);
    break;

  case MOS65XX_AM_ZP_IND_LONG_Y:
    SStream_concat(O, " [%s%02" PRIx32 "], y", prefix, value);
    break;

  case MOS65XX_AM_SR:
    SStream_concat(O, " %s%02" PRIx32 ", s", prefix, value);
    break;

  case MOS65XX_AM_SR_IND_Y:
    SStream_concat(O, " (%s%02" PRIx32 ", s), y", prefix, value);
    break;

  case MOS65XX_AM_BLOCK:
    SStream_concat(O, " %s%02" PRIx32 ", %s%02" PRIx32, prefix,
             (uint32_t)MI->Operands[0].ImmVal, prefix,
             (uint32_t)MI->Operands[1].ImmVal);
    break;

  case MOS65XX_AM_ZP_REL: {
    value = 3 + (int8_t)MI->Operands[1].ImmVal;
    uint32_t addr = MI->address;
    uint32_t target = (addr + value) & 0xffff;
    /* BBR0, zp, rel  and BBS0, zp, rel */
    SStream_concat(O, " %s%02" PRIx32 ", %s%04" PRIx32, prefix,
             (uint32_t)MI->Operands[0].ImmVal, prefix,
             target);
    break;
  }
  }
#endif
}

bool MOS65XX_getInstruction(csh ud, const uint8_t *code, size_t code_len,
          MCInst *MI, uint16_t *size, uint64_t address,
          void *inst_info)
{
  int i;
  unsigned char opcode;
  unsigned char len;
  unsigned cpu_offset = 0;
  int cpu_type = MOS65XX_CPU_TYPE_6502;
  cs_struct *handle = MI->csh;
  mos65xx_info *info = (mos65xx_info *)handle->printer_info;
  OpInfo opinfo;

  if (code_len == 0) {
    *size = 1;
    return false;
  }

  cpu_type = info->cpu_type;
  cpu_offset = cpu_type * 256;

  opcode = code[0];
  opinfo = OpInfoTable[cpu_offset + opcode];
  if (opinfo.ins == MOS65XX_INS_INVALID) {
    *size = 1;
    return false;
  }

  len = opinfo.operand_bytes + 1;

  if (cpu_type == MOS65XX_CPU_TYPE_65816 && opinfo.am == MOS65XX_AM_IMM) {
    switch (opinfo.ins) {
    case MOS65XX_INS_CPX:
    case MOS65XX_INS_CPY:
    case MOS65XX_INS_LDX:
    case MOS65XX_INS_LDY:
      if (info->long_x)
        ++len;
      break;
    case MOS65XX_INS_ADC:
    case MOS65XX_INS_AND:
    case MOS65XX_INS_BIT:
    case MOS65XX_INS_CMP:
    case MOS65XX_INS_EOR:
    case MOS65XX_INS_LDA:
    case MOS65XX_INS_ORA:
    case MOS65XX_INS_SBC:
      if (info->long_m)
        ++len;
      break;
    default:
      break;
    }
  }

  if (code_len < len) {
    *size = 1;
    return false;
  }

  MI->address = address;

  MCInst_setOpcode(MI, cpu_offset + opcode);
  MCInst_setOpcodePub(MI, opinfo.ins);

  *size = len;

  /* needed to differentiate relative vs relative long */
  MI->op1_size = len - 1;
  if (opinfo.ins == MOS65XX_INS_NOP) {
    for (i = 1; i < len; ++i)
      MCOperand_CreateImm0(MI, code[i]);
  }

  switch (opinfo.am) {
  case MOS65XX_AM_ZP_REL:
    MCOperand_CreateImm0(MI, code[1]);
    MCOperand_CreateImm0(MI, code[2]);
    break;
  case MOS65XX_AM_BLOCK:
    MCOperand_CreateImm0(MI, code[2]);
    MCOperand_CreateImm0(MI, code[1]);
    break;
  case MOS65XX_AM_IMP:
  case MOS65XX_AM_ACC:
    break;

  case MOS65XX_AM_IMM:
    MI->has_imm = 1;
    MI->imm_size = len - 1;
    /* 65816 immediate is either 1 or 2 bytes */
    /* drop through */
  default:
    if (len == 2)
      MCOperand_CreateImm0(MI, code[1]);
    else if (len == 3)
      MCOperand_CreateImm0(MI, (code[2] << 8) | code[1]);
    else if (len == 4)
      MCOperand_CreateImm0(
        MI, (code[3] << 16) | (code[2] << 8) | code[1]);
    break;
  }

#ifndef CAPSTONE_DIET
  if (MI->flat_insn->detail) {
    fillDetails(MI, opinfo, cpu_type);
  }
#endif

  return true;
}

const char *MOS65XX_insn_name(csh handle, unsigned int id)
{
#ifdef CAPSTONE_DIET
  return NULL;
#else
  if (id >= ARR_SIZE(InstructionInfoTable)) {
    return NULL;
  }
  return InstructionInfoTable[id].name;
#endif
}

const char *MOS65XX_reg_name(csh handle, unsigned int reg)
{
#ifdef CAPSTONE_DIET
  return NULL;
#else
  if (reg >= ARR_SIZE(RegNames)) {
    return NULL;
  }
  return RegNames[(int)reg];
#endif
}

void MOS65XX_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
  /* id is cpu_offset + opcode */
  if (id < ARR_SIZE(OpInfoTable)) {
    insn->id = OpInfoTable[id].ins;
  }
}

const char *MOS65XX_group_name(csh handle, unsigned int id)
{
#ifdef CAPSTONE_DIET
  return NULL;
#else
  if (id >= ARR_SIZE(GroupNames)) {
    return NULL;
  }
  return GroupNames[(int)id];
#endif
}

Coverage Report

Created: 2026-03-13 06:50

Line	Count	Source
1		/* Capstone Disassembly Engine */
2		/* MOS65XX Backend by Sebastian Macke <sebastian@macke.de> 2018 */
3
4		#include "capstone/mos65xx.h"
5		#include "MOS65XXDisassembler.h"
6		#include "MOS65XXDisassemblerInternals.h"
7
8		typedef struct OpInfo {
9		mos65xx_insn ins;
10		mos65xx_address_mode am;
11		int operand_bytes;
12		} OpInfo;
13
14		static const struct OpInfo OpInfoTable[] = {
15
16		#include "m6502.inc"
17		#include "m65c02.inc"
18		#include "mw65c02.inc"
19		#include "m65816.inc"
20
21		};
22
23		#ifndef CAPSTONE_DIET
24		static const char *const RegNames[] = { "invalid", "A", "X", "Y", "P",
25		"SP", "DP", "B", "K" };
26
27		static const char *const GroupNames[] = {
28		NULL, "jump", "call", "ret", "int", "iret", "branch_relative"
29		};
30
31		typedef struct InstructionInfo {
32		const char *name;
33		mos65xx_group_type group_type;
34		mos65xx_reg write, read;
35		bool modifies_status;
36		} InstructionInfo;
37
38		static const struct InstructionInfo InstructionInfoTable[] = {
39
40		#include "instruction_info.inc"
41
42		};
43		#endif
44
45		#ifndef CAPSTONE_DIET
46		static void fillDetails(MCInst *MI, struct OpInfo opinfo, int cpu_type)
47	7.64k	{
48	7.64k	int i;
49	7.64k	cs_detail *detail = MI->flat_insn->detail;
50
51	7.64k	InstructionInfo insinfo = InstructionInfoTable[opinfo.ins];
52
53	7.64k	detail->mos65xx.am = opinfo.am;
54	7.64k	detail->mos65xx.modifies_flags = insinfo.modifies_status;
55	7.64k	detail->groups_count = 0;
56	7.64k	detail->regs_read_count = 0;
57	7.64k	detail->regs_write_count = 0;
58	7.64k	detail->mos65xx.op_count = 0;
59
60	7.64k	if (insinfo.group_type != MOS65XX_GRP_INVALID) {
61	1.51k	detail->groups[detail->groups_count] = insinfo.group_type;
62	1.51k	detail->groups_count++;
63	1.51k	}
64
65	7.64k	if (opinfo.am == MOS65XX_AM_REL \|\| opinfo.am == MOS65XX_AM_ZP_REL) {
66	196	detail->groups[detail->groups_count] =
67	196	MOS65XX_GRP_BRANCH_RELATIVE;
68	196	detail->groups_count++;
69	196	}
70
71	7.64k	if (insinfo.read != MOS65XX_REG_INVALID) {
72	3.04k	detail->regs_read[detail->regs_read_count++] = insinfo.read;
73	3.04k	} else
74	4.60k	switch (opinfo.am) {
75	361	case MOS65XX_AM_ACC:
76	361	detail->regs_read[detail->regs_read_count++] =
77	361	MOS65XX_REG_ACC;
78	361	break;
79	189	case MOS65XX_AM_ZP_Y:
80	220	case MOS65XX_AM_ZP_IND_Y:
81	471	case MOS65XX_AM_ABS_Y:
82	471	case MOS65XX_AM_ZP_IND_LONG_Y:
83	471	detail->regs_read[detail->regs_read_count++] =
84	471	MOS65XX_REG_Y;
85	471	break;
86
87	612	case MOS65XX_AM_ZP_X:
88	1.13k	case MOS65XX_AM_ZP_X_IND:
89	1.30k	case MOS65XX_AM_ABS_X:
90	1.30k	case MOS65XX_AM_ABS_X_IND:
91	1.30k	case MOS65XX_AM_ABS_LONG_X:
92	1.30k	detail->regs_read[detail->regs_read_count++] =
93	1.30k	MOS65XX_REG_X;
94	1.30k	break;
95
96	0	case MOS65XX_AM_SR:
97	0	detail->regs_read[detail->regs_read_count++] =
98	0	MOS65XX_REG_SP;
99	0	break;
100	0	case MOS65XX_AM_SR_IND_Y:
101	0	detail->regs_read[detail->regs_read_count++] =
102	0	MOS65XX_REG_SP;
103	0	detail->regs_read[detail->regs_read_count++] =
104	0	MOS65XX_REG_Y;
105	0	break;
106
107	2.47k	default:
108	2.47k	break;
109	4.60k	}
110
111	7.64k	if (insinfo.write != MOS65XX_REG_INVALID) {
112	2.11k	detail->regs_write[detail->regs_write_count++] = insinfo.write;
113	5.53k	} else if (opinfo.am == MOS65XX_AM_ACC) {
114	361	detail->regs_write[detail->regs_write_count++] =
115	361	MOS65XX_REG_ACC;
116	361	}
117
118	7.64k	switch (opinfo.ins) {
119	263	case MOS65XX_INS_ADC:
120	507	case MOS65XX_INS_SBC:
121	860	case MOS65XX_INS_ROL:
122	1.04k	case MOS65XX_INS_ROR:
123		/* these read carry flag (and decimal for ADC/SBC) */
124	1.04k	detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_P;
125	1.04k	break;
126		/* stack operations */
127	0	case MOS65XX_INS_JSL:
128	278	case MOS65XX_INS_JSR:
129	278	case MOS65XX_INS_PEA:
130	278	case MOS65XX_INS_PEI:
131	278	case MOS65XX_INS_PER:
132	1.73k	case MOS65XX_INS_PHA:
133	1.73k	case MOS65XX_INS_PHB:
134	1.73k	case MOS65XX_INS_PHD:
135	1.73k	case MOS65XX_INS_PHK:
136	2.03k	case MOS65XX_INS_PHP:
137	2.03k	case MOS65XX_INS_PHX:
138	2.03k	case MOS65XX_INS_PHY:
139	2.09k	case MOS65XX_INS_PLA:
140	2.09k	case MOS65XX_INS_PLB:
141	2.09k	case MOS65XX_INS_PLD:
142	2.39k	case MOS65XX_INS_PLP:
143	2.39k	case MOS65XX_INS_PLX:
144	2.39k	case MOS65XX_INS_PLY:
145	2.46k	case MOS65XX_INS_RTI:
146	2.46k	case MOS65XX_INS_RTL:
147	2.73k	case MOS65XX_INS_RTS:
148	2.73k	detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP;
149	2.73k	detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_SP;
150	2.73k	break;
151	3.86k	default:
152	3.86k	break;
153	7.64k	}
154
155	7.64k	if (cpu_type == MOS65XX_CPU_TYPE_65816) {
156	0	switch (opinfo.am) {
157	0	case MOS65XX_AM_ZP:
158	0	case MOS65XX_AM_ZP_X:
159	0	case MOS65XX_AM_ZP_Y:
160	0	case MOS65XX_AM_ZP_IND:
161	0	case MOS65XX_AM_ZP_X_IND:
162	0	case MOS65XX_AM_ZP_IND_Y:
163	0	case MOS65XX_AM_ZP_IND_LONG:
164	0	case MOS65XX_AM_ZP_IND_LONG_Y:
165	0	detail->regs_read[detail->regs_read_count++] =
166	0	MOS65XX_REG_DP;
167	0	break;
168	0	case MOS65XX_AM_BLOCK:
169	0	detail->regs_read[detail->regs_read_count++] =
170	0	MOS65XX_REG_ACC;
171	0	detail->regs_read[detail->regs_read_count++] =
172	0	MOS65XX_REG_X;
173	0	detail->regs_read[detail->regs_read_count++] =
174	0	MOS65XX_REG_Y;
175	0	detail->regs_write[detail->regs_write_count++] =
176	0	MOS65XX_REG_ACC;
177	0	detail->regs_write[detail->regs_write_count++] =
178	0	MOS65XX_REG_X;
179	0	detail->regs_write[detail->regs_write_count++] =
180	0	MOS65XX_REG_Y;
181	0	detail->regs_write[detail->regs_write_count++] =
182	0	MOS65XX_REG_B;
183	0	break;
184	0	default:
185	0	break;
186	0	}
187
188	0	switch (opinfo.am) {
189	0	case MOS65XX_AM_ZP_IND:
190	0	case MOS65XX_AM_ZP_X_IND:
191	0	case MOS65XX_AM_ZP_IND_Y:
192	0	case MOS65XX_AM_ABS:
193	0	case MOS65XX_AM_ABS_X:
194	0	case MOS65XX_AM_ABS_Y:
195	0	case MOS65XX_AM_ABS_X_IND:
196		/* these depend on the databank to generate a 24-bit address */
197		/* exceptions: PEA, PEI, and JMP (abs) */
198	0	if (opinfo.ins == MOS65XX_INS_PEI \|\|
199	0	opinfo.ins == MOS65XX_INS_PEA)
200	0	break;
201	0	detail->regs_read[detail->regs_read_count++] =
202	0	MOS65XX_REG_B;
203	0	break;
204	0	default:
205	0	break;
206	0	}
207	0	}
208
209	7.64k	if (insinfo.modifies_status) {
210	3.91k	detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_P;
211	3.91k	}
212
213	7.64k	switch (opinfo.am) {
214	3.15k	case MOS65XX_AM_IMP:
215	3.15k	break;
216	203	case MOS65XX_AM_IMM:
217	203	detail->mos65xx.operands[detail->mos65xx.op_count].type =
218	203	MOS65XX_OP_IMM;
219	203	detail->mos65xx.operands[detail->mos65xx.op_count].imm =
220	203	MI->Operands[0].ImmVal;
221	203	detail->mos65xx.op_count++;
222	203	break;
223	361	case MOS65XX_AM_ACC:
224	361	detail->mos65xx.operands[detail->mos65xx.op_count].type =
225	361	MOS65XX_OP_REG;
226	361	detail->mos65xx.operands[detail->mos65xx.op_count].reg =
227	361	MOS65XX_REG_ACC;
228	361	detail->mos65xx.op_count++;
229	361	break;
230	196	case MOS65XX_AM_REL: {
231	196	int value = MI->Operands[0].ImmVal;
232	196	if (MI->op1_size == 1)
233	196	value = 2 + (signed char)value;
234	0	else
235	0	value = 3 + (signed short)value;
236	196	detail->mos65xx.operands[detail->mos65xx.op_count].type =
237	196	MOS65XX_OP_MEM;
238	196	detail->mos65xx.operands[detail->mos65xx.op_count].mem =
239	196	(MI->address + value) & 0xffff;
240	196	detail->mos65xx.op_count++;
241	196	break;
242	0	}
243	0	case MOS65XX_AM_ZP_REL: {
244	0	int value = 3 + (signed char)MI->Operands[1].ImmVal;
245		/* BBR0, zp, rel and BBS0, zp, rel */
246	0	detail->mos65xx.operands[detail->mos65xx.op_count].type =
247	0	MOS65XX_OP_MEM;
248	0	detail->mos65xx.operands[detail->mos65xx.op_count].mem =
249	0	MI->Operands[0].ImmVal;
250	0	detail->mos65xx.operands[detail->mos65xx.op_count + 1].type =
251	0	MOS65XX_OP_MEM;
252	0	detail->mos65xx.operands[detail->mos65xx.op_count + 1].mem =
253	0	(MI->address + value) & 0xffff;
254	0	detail->mos65xx.op_count += 2;
255	0	break;
256	0	}
257	3.73k	default:
258	7.46k	for (i = 0; i < MI->size; ++i) {
259	3.73k	detail->mos65xx.operands[detail->mos65xx.op_count].type =
260	3.73k	MOS65XX_OP_MEM;
261	3.73k	detail->mos65xx.operands[detail->mos65xx.op_count].mem =
262	3.73k	MI->Operands[i].ImmVal;
263	3.73k	detail->mos65xx.op_count++;
264	3.73k	}
265	3.73k	break;
266	7.64k	}
267	7.64k	}
268		#endif
269
270		void MOS65XX_printInst(MCInst MI, struct SStream O, void *PrinterInfo)
271	7.64k	{
272	7.64k	#ifndef CAPSTONE_DIET
273	7.64k	unsigned int value;
274	7.64k	unsigned opcode = MCInst_getOpcode(MI);
275	7.64k	mos65xx_info info = (mos65xx_info )PrinterInfo;
276
277	7.64k	OpInfo opinfo = OpInfoTable[opcode];
278
279	7.64k	const char *prefix = info->hex_prefix ? info->hex_prefix : "0x";
280
281	7.64k	SStream_concat0(O, InstructionInfoTable[opinfo.ins].name);
282	7.64k	switch (opinfo.ins) {
283		/* special case - bit included as part of the instruction name */
284	0	case MOS65XX_INS_BBR:
285	0	case MOS65XX_INS_BBS:
286	0	case MOS65XX_INS_RMB:
287	0	case MOS65XX_INS_SMB:
288	0	SStream_concat(O, "%" PRId8, (opcode >> 4) & 0x07);
289	0	break;
290	7.64k	default:
291	7.64k	break;
292	7.64k	}
293
294	7.64k	value = MI->Operands[0].ImmVal;
295
296	7.64k	switch (opinfo.am) {
297	0	default:
298	0	break;
299
300	3.15k	case MOS65XX_AM_IMP:
301	3.15k	break;
302
303	361	case MOS65XX_AM_ACC:
304	361	SStream_concat0(O, " a");
305	361	break;
306
307	203	case MOS65XX_AM_IMM:
308	203	if (MI->imm_size == 1)
309	203	SStream_concat(O, " #%s%02" PRIx32, prefix, value);
310	0	else
311	0	SStream_concat(O, " #%s%04" PRIx32, prefix, value);
312	203	break;
313
314	236	case MOS65XX_AM_ZP:
315	236	SStream_concat(O, " %s%02" PRIx32, prefix, value);
316	236	break;
317
318	496	case MOS65XX_AM_ABS:
319	496	SStream_concat(O, " %s%04" PRIx32, prefix, value);
320	496	break;
321
322	0	case MOS65XX_AM_ABS_LONG_X:
323	0	SStream_concat(O, " %s%06" PRIx32 ", x", prefix, value);
324	0	break;
325
326	226	case MOS65XX_AM_INT:
327	226	SStream_concat(O, " %s%02" PRIx32, prefix, value);
328	226	break;
329
330	197	case MOS65XX_AM_ABS_X:
331	197	SStream_concat(O, " %s%04" PRIx32 ", x", prefix, value);
332	197	break;
333
334	412	case MOS65XX_AM_ABS_Y:
335	412	SStream_concat(O, " %s%04" PRIx32 ", y", prefix, value);
336	412	break;
337
338	0	case MOS65XX_AM_ABS_LONG:
339	0	SStream_concat(O, " %s%06" PRIx32, prefix, value);
340	0	break;
341
342	619	case MOS65XX_AM_ZP_X:
343	619	SStream_concat(O, " %s%02" PRIx32 ", x", prefix, value);
344	619	break;
345
346	193	case MOS65XX_AM_ZP_Y:
347	193	SStream_concat(O, " %s%02" PRIx32 ", y", prefix, value);
348	193	break;
349
350	196	case MOS65XX_AM_REL: {
351	196	if (MI->op1_size == 1)
352	196	value = 2 + (int8_t)value;
353	0	else
354	0	value = 3 + (int16_t)value;
355
356	196	uint32_t addr = MI->address;
357	196	SStream_concat(O, " %s%04" PRIx16, prefix,
358	196	(addr + value) & 0xffff);
359
360	196	break;
361	0	}
362	471	case MOS65XX_AM_ABS_IND:
363	471	SStream_concat(O, " (%s%04" PRIx32 ")", prefix, value);
364	471	break;
365
366	0	case MOS65XX_AM_ABS_X_IND:
367	0	SStream_concat(O, " (%s%04" PRIx32 ", x)", prefix, value);
368	0	break;
369
370	0	case MOS65XX_AM_ABS_IND_LONG:
371	0	SStream_concat(O, " [%s%04" PRIx32 "]", prefix, value);
372	0	break;
373
374	0	case MOS65XX_AM_ZP_IND:
375	0	SStream_concat(O, " (%s%02" PRIx32 ")", prefix, value);
376	0	break;
377
378	611	case MOS65XX_AM_ZP_X_IND:
379	611	SStream_concat(O, " (%s%02" PRIx32 ", x)", prefix, value);
380	611	break;
381
382	273	case MOS65XX_AM_ZP_IND_Y:
383	273	SStream_concat(O, " (%s%02" PRIx32 "), y", prefix, value);
384	273	break;
385
386	0	case MOS65XX_AM_ZP_IND_LONG:
387	0	SStream_concat(O, " [%s%02" PRIx32 "]", prefix, value);
388	0	break;
389
390	0	case MOS65XX_AM_ZP_IND_LONG_Y:
391	0	SStream_concat(O, " [%s%02" PRIx32 "], y", prefix, value);
392	0	break;
393
394	0	case MOS65XX_AM_SR:
395	0	SStream_concat(O, " %s%02" PRIx32 ", s", prefix, value);
396	0	break;
397
398	0	case MOS65XX_AM_SR_IND_Y:
399	0	SStream_concat(O, " (%s%02" PRIx32 ", s), y", prefix, value);
400	0	break;
401
402	0	case MOS65XX_AM_BLOCK:
403	0	SStream_concat(O, " %s%02" PRIx32 ", %s%02" PRIx32, prefix,
404	0	(uint32_t)MI->Operands[0].ImmVal, prefix,
405	0	(uint32_t)MI->Operands[1].ImmVal);
406	0	break;
407
408	0	case MOS65XX_AM_ZP_REL: {
409	0	value = 3 + (int8_t)MI->Operands[1].ImmVal;
410	0	uint32_t addr = MI->address;
411	0	uint32_t target = (addr + value) & 0xffff;
412		/* BBR0, zp, rel and BBS0, zp, rel */
413	0	SStream_concat(O, " %s%02" PRIx32 ", %s%04" PRIx32, prefix,
414	0	(uint32_t)MI->Operands[0].ImmVal, prefix,
415	0	target);
416	0	break;
417	0	}
418	7.64k	}
419	7.64k	#endif
420	7.64k	}
421
422		bool MOS65XX_getInstruction(csh ud, const uint8_t *code, size_t code_len,
423		MCInst MI, uint16_t size, uint64_t address,
424		void *inst_info)
425	7.71k	{
426	7.71k	int i;
427	7.71k	unsigned char opcode;
428	7.71k	unsigned char len;
429	7.71k	unsigned cpu_offset = 0;
430	7.71k	int cpu_type = MOS65XX_CPU_TYPE_6502;
431	7.71k	cs_struct *handle = MI->csh;
432	7.71k	mos65xx_info info = (mos65xx_info )handle->printer_info;
433	7.71k	OpInfo opinfo;
434
435	7.71k	if (code_len == 0) {
436	0	*size = 1;
437	0	return false;
438	0	}
439
440	7.71k	cpu_type = info->cpu_type;
441	7.71k	cpu_offset = cpu_type * 256;
442
443	7.71k	opcode = code[0];
444	7.71k	opinfo = OpInfoTable[cpu_offset + opcode];
445	7.71k	if (opinfo.ins == MOS65XX_INS_INVALID) {
446	44	*size = 1;
447	44	return false;
448	44	}
449
450	7.67k	len = opinfo.operand_bytes + 1;
451
452	7.67k	if (cpu_type == MOS65XX_CPU_TYPE_65816 && opinfo.am == MOS65XX_AM_IMM) {
453	0	switch (opinfo.ins) {
454	0	case MOS65XX_INS_CPX:
455	0	case MOS65XX_INS_CPY:
456	0	case MOS65XX_INS_LDX:
457	0	case MOS65XX_INS_LDY:
458	0	if (info->long_x)
459	0	++len;
460	0	break;
461	0	case MOS65XX_INS_ADC:
462	0	case MOS65XX_INS_AND:
463	0	case MOS65XX_INS_BIT:
464	0	case MOS65XX_INS_CMP:
465	0	case MOS65XX_INS_EOR:
466	0	case MOS65XX_INS_LDA:
467	0	case MOS65XX_INS_ORA:
468	0	case MOS65XX_INS_SBC:
469	0	if (info->long_m)
470	0	++len;
471	0	break;
472	0	default:
473	0	break;
474	0	}
475	0	}
476
477	7.67k	if (code_len < len) {
478	26	*size = 1;
479	26	return false;
480	26	}
481
482	7.64k	MI->address = address;
483
484	7.64k	MCInst_setOpcode(MI, cpu_offset + opcode);
485	7.64k	MCInst_setOpcodePub(MI, opinfo.ins);
486
487	7.64k	*size = len;
488
489		/* needed to differentiate relative vs relative long */
490	7.64k	MI->op1_size = len - 1;
491	7.64k	if (opinfo.ins == MOS65XX_INS_NOP) {
492	355	for (i = 1; i < len; ++i)
493	0	MCOperand_CreateImm0(MI, code[i]);
494	355	}
495
496	7.64k	switch (opinfo.am) {
497	0	case MOS65XX_AM_ZP_REL:
498	0	MCOperand_CreateImm0(MI, code[1]);
499	0	MCOperand_CreateImm0(MI, code[2]);
500	0	break;
501	0	case MOS65XX_AM_BLOCK:
502	0	MCOperand_CreateImm0(MI, code[2]);
503	0	MCOperand_CreateImm0(MI, code[1]);
504	0	break;
505	3.15k	case MOS65XX_AM_IMP:
506	3.51k	case MOS65XX_AM_ACC:
507	3.51k	break;
508
509	203	case MOS65XX_AM_IMM:
510	203	MI->has_imm = 1;
511	203	MI->imm_size = len - 1;
512		/* 65816 immediate is either 1 or 2 bytes */
513		/* drop through */
514	4.13k	default:
515	4.13k	if (len == 2)
516	2.55k	MCOperand_CreateImm0(MI, code[1]);
517	1.57k	else if (len == 3)
518	1.57k	MCOperand_CreateImm0(MI, (code[2] << 8) \| code[1]);
519	0	else if (len == 4)
520	0	MCOperand_CreateImm0(
521	0	MI, (code[3] << 16) \| (code[2] << 8) \| code[1]);
522	4.13k	break;
523	7.64k	}
524
525	7.64k	#ifndef CAPSTONE_DIET
526	7.64k	if (MI->flat_insn->detail) {
527	7.64k	fillDetails(MI, opinfo, cpu_type);
528	7.64k	}
529	7.64k	#endif
530
531	7.64k	return true;
532	7.64k	}
533
534		const char *MOS65XX_insn_name(csh handle, unsigned int id)
535	7.64k	{
536		#ifdef CAPSTONE_DIET
537		return NULL;
538		#else
539	7.64k	if (id >= ARR_SIZE(InstructionInfoTable)) {
540	0	return NULL;
541	0	}
542	7.64k	return InstructionInfoTable[id].name;
543	7.64k	#endif
544	7.64k	}
545
546		const char *MOS65XX_reg_name(csh handle, unsigned int reg)
547	18.0k	{
548		#ifdef CAPSTONE_DIET
549		return NULL;
550		#else
551	18.0k	if (reg >= ARR_SIZE(RegNames)) {
552	0	return NULL;
553	0	}
554	18.0k	return RegNames[(int)reg];
555	18.0k	#endif
556	18.0k	}
557
558		void MOS65XX_get_insn_id(cs_struct h, cs_insn insn, unsigned int id)
559	7.64k	{
560		/* id is cpu_offset + opcode */
561	7.64k	if (id < ARR_SIZE(OpInfoTable)) {
562	7.64k	insn->id = OpInfoTable[id].ins;
563	7.64k	}
564	7.64k	}
565
566		const char *MOS65XX_group_name(csh handle, unsigned int id)
567	1.70k	{
568		#ifdef CAPSTONE_DIET
569		return NULL;
570		#else
571	1.70k	if (id >= ARR_SIZE(GroupNames)) {
572	0	return NULL;
573	0	}
574	1.70k	return GroupNames[(int)id];
575	1.70k	#endif
576	1.70k	}