/src/capstonenext/arch/TMS320C64x/TMS320C64xInstPrinter.c

Source
/* Capstone Disassembly Engine */
/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */

#ifdef CAPSTONE_HAS_TMS320C64X

#include <ctype.h>
#include <string.h>

#include "TMS320C64xInstPrinter.h"
#include "../../MCInst.h"
#include "../../utils.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "../../MathExtras.h"
#include "TMS320C64xMapping.h"

#include "capstone/tms320c64x.h"

static const char *getRegisterName(unsigned RegNo);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O);
static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O);

void TMS320C64x_post_printer(csh ud, cs_insn *insn, SStream *insn_asm,
           MCInst *mci)
{
  SStream ss;
  const char *op_str_ptr, *p2;
  char tmp[8] = { 0 };
  unsigned int unit = 0;
  int i;
  cs_tms320c64x *tms320c64x;

  if (mci->csh->detail_opt) {
    tms320c64x = &mci->flat_insn->detail->tms320c64x;

    for (i = 0; i < insn->detail->groups_count; i++) {
      switch (insn->detail->groups[i]) {
      case TMS320C64X_GRP_FUNIT_D:
        unit = TMS320C64X_FUNIT_D;
        break;
      case TMS320C64X_GRP_FUNIT_L:
        unit = TMS320C64X_FUNIT_L;
        break;
      case TMS320C64X_GRP_FUNIT_M:
        unit = TMS320C64X_FUNIT_M;
        break;
      case TMS320C64X_GRP_FUNIT_S:
        unit = TMS320C64X_FUNIT_S;
        break;
      case TMS320C64X_GRP_FUNIT_NO:
        unit = TMS320C64X_FUNIT_NO;
        break;
      }
      if (unit != 0)
        break;
    }
    tms320c64x->funit.unit = unit;

    SStream_Init(&ss);
    if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
      SStream_concat(
        &ss, "[%c%s]|",
        (tms320c64x->condition.zero == 1) ? '!' : '|',
        cs_reg_name(ud, tms320c64x->condition.reg));

    // Sorry for all the fixes below. I don't have time to add more helper SStream functions.
    // Before that they messed around with the private buffer of the stream.
    // So it is better now. But still not efficient.
    op_str_ptr = strchr(SStream_rbuf(insn_asm), '\t');

    if ((op_str_ptr != NULL) &&
        (((p2 = strchr(op_str_ptr, '[')) != NULL) ||
         ((p2 = strchr(op_str_ptr, '(')) != NULL))) {
      while ((p2 > op_str_ptr) &&
             ((*p2 != 'a') && (*p2 != 'b')))
        p2--;
      if (p2 == op_str_ptr) {
        SStream_Flush(insn_asm, NULL);
        SStream_concat0(insn_asm, "Invalid!");
        return;
      }
      if (*p2 == 'a')
        strncpy(tmp, "1T", sizeof(tmp));
      else
        strncpy(tmp, "2T", sizeof(tmp));
    } else {
      tmp[0] = '\0';
    }
    SStream mnem_post = { 0 };
    SStream_Init(&mnem_post);
    switch (tms320c64x->funit.unit) {
    case TMS320C64X_FUNIT_D:
      SStream_concat(&mnem_post, ".D%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_L:
      SStream_concat(&mnem_post, ".L%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_M:
      SStream_concat(&mnem_post, ".M%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_S:
      SStream_concat(&mnem_post, ".S%s%u", tmp,
               tms320c64x->funit.side);
      break;
    }
    if (tms320c64x->funit.crosspath > 0)
      SStream_concat0(&mnem_post, "X");

    if (op_str_ptr != NULL) {
      // There is an op_str
      SStream_concat1(&mnem_post, '\t');
      SStream_replc_str(insn_asm, '\t',
            SStream_rbuf(&mnem_post));
    }

    if (tms320c64x->parallel != 0)
      SStream_concat0(insn_asm, "\t||");
    SStream_concat0(&ss, SStream_rbuf(insn_asm));
    SStream_Flush(insn_asm, NULL);
    SStream_concat0(insn_asm, SStream_rbuf(&ss));
  }
}

#define PRINT_ALIAS_INSTR
#include "TMS320C64xGenAsmWriter.inc"

#define GET_INSTRINFO_ENUM
#include "TMS320C64xGenInstrInfo.inc"

static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg;

  if (MCOperand_isReg(Op)) {
    reg = MCOperand_getReg(Op);
    if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) &&
        (OpNo == 1)) {
      switch (reg) {
      case TMS320C64X_REG_EFR:
        SStream_concat0(O, "EFR");
        break;
      case TMS320C64X_REG_IFR:
        SStream_concat0(O, "IFR");
        break;
      default:
        SStream_concat0(O, getRegisterName(reg));
        break;
      }
    } else {
      SStream_concat0(O, getRegisterName(reg));
    }

    if (MI->csh->detail_opt) {
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .type = TMS320C64X_OP_REG;
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .reg = reg;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  } else if (MCOperand_isImm(Op)) {
    int64_t Imm = MCOperand_getImm(Op);

    if (Imm >= 0) {
      if (Imm > HEX_THRESHOLD)
        SStream_concat(O, "0x%" PRIx64, Imm);
      else
        SStream_concat(O, "%" PRIu64, Imm);
    } else {
      if (Imm < -HEX_THRESHOLD)
        SStream_concat(O, "-0x%" PRIx64, -Imm);
      else
        SStream_concat(O, "-%" PRIu64, -Imm);
    }

    if (MI->csh->detail_opt) {
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .type = TMS320C64X_OP_IMM;
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .imm = Imm;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  }
}

static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  unsigned scaled, base, offset, mode, unit;
  cs_tms320c64x *tms320c64x;
  char st, nd;

  scaled = (Val >> 19) & 1;
  base = (Val >> 12) & 0x7f;
  offset = (Val >> 5) & 0x7f;
  mode = (Val >> 1) & 0xf;
  unit = Val & 1;

  if (scaled) {
    st = '[';
    nd = ']';
  } else {
    st = '(';
    nd = ')';
  }

  switch (mode) {
  case 0:
    SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 1:
    SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 4:
    SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 5:
    SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 8:
    SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 9:
    SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 10:
    SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 11:
    SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 12:
    SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 13:
    SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 14:
    SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 15:
    SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  }

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = base;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
    tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
    switch (mode) {
    case 0:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 1:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 4:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 5:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 8:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 9:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 10:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 11:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 12:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 13:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 14:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 15:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    }
    tms320c64x->op_count++;
  }
}

static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  uint16_t offset;
  unsigned basereg;
  cs_tms320c64x *tms320c64x;

  basereg = Val & 0x7f;
  offset = (Val >> 7) & 0x7fff;
  SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.disptype =
      TMS320C64X_MEM_DISP_CONSTANT;
    tms320c64x->operands[tms320c64x->op_count].mem.direction =
      TMS320C64X_MEM_DIR_FW;
    tms320c64x->operands[tms320c64x->op_count].mem.modify =
      TMS320C64X_MEM_MOD_NO;
    tms320c64x->op_count++;
  }
}

static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg = MCOperand_getReg(Op);
  cs_tms320c64x *tms320c64x;

  SStream_concat(O, "%s:%s", getRegisterName(reg + 1),
           getRegisterName(reg));

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_REGPAIR;
    tms320c64x->operands[tms320c64x->op_count].reg = reg;
    tms320c64x->op_count++;
  }
}

static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
{
  unsigned opcode = MCInst_getOpcode(MI);
  MCOperand *op;

  switch (opcode) {
  /* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
  case TMS320C64x_ADD_d2_rir:
  /* ADD.L -i, x, y -> SUB.L x, i, y */
  case TMS320C64x_ADD_l1_irr:
  case TMS320C64x_ADD_l1_ipp:
  /* ADD.S -i, x, y -> SUB.S x, i, y */
  case TMS320C64x_ADD_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
      op = MCInst_getOperand(MI, 2);
      MCOperand_setImm(op, -MCOperand_getImm(op));

      SStream_concat0(O, "SUB\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 2, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* ADD.D 0, x, y -> MV.D x, y */
  case TMS320C64x_ADD_d1_rir:
  /* OR.D x, 0, y -> MV.D x, y */
  case TMS320C64x_OR_d2_rir:
  /* ADD.L 0, x, y -> MV.L x, y */
  case TMS320C64x_ADD_l1_irr:
  case TMS320C64x_ADD_l1_ipp:
  /* OR.L 0, x, y -> MV.L x, y */
  case TMS320C64x_OR_l1_irr:
  /* ADD.S 0, x, y -> MV.S x, y */
  case TMS320C64x_ADD_s1_irr:
  /* OR.S 0, x, y -> MV.S x, y */
  case TMS320C64x_OR_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
      MI->size--;

      SStream_concat0(O, "MV\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* XOR.D -1, x, y -> NOT.D x, y */
  case TMS320C64x_XOR_d2_rir:
  /* XOR.L -1, x, y -> NOT.L x, y */
  case TMS320C64x_XOR_l1_irr:
  /* XOR.S -1, x, y -> NOT.S x, y */
  case TMS320C64x_XOR_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
      MI->size--;

      SStream_concat0(O, "NOT\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* MVK.D 0, x -> ZERO.D x */
  case TMS320C64x_MVK_d1_rr:
  /* MVK.L 0, x -> ZERO.L x */
  case TMS320C64x_MVK_l2_ir:
    if ((MCInst_getNumOperands(MI) == 2) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
      MI->size--;

      SStream_concat0(O, "ZERO\t");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* SUB.L x, x, y -> ZERO.L y */
  case TMS320C64x_SUB_l1_rrp_x1:
  /* SUB.S x, x, y -> ZERO.S y */
  case TMS320C64x_SUB_s1_rrr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
         MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
      MI->size -= 2;

      SStream_concat0(O, "ZERO\t");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* SUB.L 0, x, y -> NEG.L x, y */
  case TMS320C64x_SUB_l1_irr:
  case TMS320C64x_SUB_l1_ipp:
  /* SUB.S 0, x, y -> NEG.S x, y */
  case TMS320C64x_SUB_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
      MI->size--;

      SStream_concat0(O, "NEG\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* PACKLH2.L x, x, y -> SWAP2.L x, y */
  case TMS320C64x_PACKLH2_l1_rrr_x2:
  /* PACKLH2.S x, x, y -> SWAP2.S x, y */
  case TMS320C64x_PACKLH2_s1_rrr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
         MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
      MI->size--;

      SStream_concat0(O, "SWAP2\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* NOP 16 -> IDLE */
  /* NOP 1 -> NOP */
  case TMS320C64x_NOP_n:
    if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
      MI->size--;

      SStream_concat0(O, "IDLE");

      return true;
    }
    if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
      MI->size--;

      SStream_concat0(O, "NOP");

      return true;
    }
    break;
  }

  return false;
}

void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info)
{
  if (!printAliasInstruction(MI, O, Info))
    printInstruction(MI, O, Info);
}

#endif

Coverage Report

Created: 2026-04-12 06:30

Line	Count	Source
1		/* Capstone Disassembly Engine */
2		/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
3
4		#ifdef CAPSTONE_HAS_TMS320C64X
5
6		#include <ctype.h>
7		#include <string.h>
8
9		#include "TMS320C64xInstPrinter.h"
10		#include "../../MCInst.h"
11		#include "../../utils.h"
12		#include "../../SStream.h"
13		#include "../../MCRegisterInfo.h"
14		#include "../../MathExtras.h"
15		#include "TMS320C64xMapping.h"
16
17		#include "capstone/tms320c64x.h"
18
19		static const char *getRegisterName(unsigned RegNo);
20		static void printOperand(MCInst MI, unsigned OpNo, SStream O);
21		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O);
22		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O);
23		static void printRegPair(MCInst MI, unsigned OpNo, SStream O);
24
25		void TMS320C64x_post_printer(csh ud, cs_insn insn, SStream insn_asm,
26		MCInst *mci)
27	24.6k	{
28	24.6k	SStream ss;
29	24.6k	const char op_str_ptr, p2;
30	24.6k	char tmp[8] = { 0 };
31	24.6k	unsigned int unit = 0;
32	24.6k	int i;
33	24.6k	cs_tms320c64x *tms320c64x;
34
35	24.6k	if (mci->csh->detail_opt) {
36	24.6k	tms320c64x = &mci->flat_insn->detail->tms320c64x;
37
38	24.6k	for (i = 0; i < insn->detail->groups_count; i++) {
39	24.6k	switch (insn->detail->groups[i]) {
40	7.46k	case TMS320C64X_GRP_FUNIT_D:
41	7.46k	unit = TMS320C64X_FUNIT_D;
42	7.46k	break;
43	5.02k	case TMS320C64X_GRP_FUNIT_L:
44	5.02k	unit = TMS320C64X_FUNIT_L;
45	5.02k	break;
46	1.36k	case TMS320C64X_GRP_FUNIT_M:
47	1.36k	unit = TMS320C64X_FUNIT_M;
48	1.36k	break;
49	10.2k	case TMS320C64X_GRP_FUNIT_S:
50	10.2k	unit = TMS320C64X_FUNIT_S;
51	10.2k	break;
52	494	case TMS320C64X_GRP_FUNIT_NO:
53	494	unit = TMS320C64X_FUNIT_NO;
54	494	break;
55	24.6k	}
56	24.6k	if (unit != 0)
57	24.6k	break;
58	24.6k	}
59	24.6k	tms320c64x->funit.unit = unit;
60
61	24.6k	SStream_Init(&ss);
62	24.6k	if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
63	15.2k	SStream_concat(
64	15.2k	&ss, "[%c%s]\|",
65	15.2k	(tms320c64x->condition.zero == 1) ? '!' : '\|',
66	15.2k	cs_reg_name(ud, tms320c64x->condition.reg));
67
68		// Sorry for all the fixes below. I don't have time to add more helper SStream functions.
69		// Before that they messed around with the private buffer of the stream.
70		// So it is better now. But still not efficient.
71	24.6k	op_str_ptr = strchr(SStream_rbuf(insn_asm), '\t');
72
73	24.6k	if ((op_str_ptr != NULL) &&
74	24.2k	(((p2 = strchr(op_str_ptr, '[')) != NULL) \|\|
75	18.6k	((p2 = strchr(op_str_ptr, '(')) != NULL))) {
76	26.0k	while ((p2 > op_str_ptr) &&
77	26.0k	((p2 != 'a') && (p2 != 'b')))
78	19.9k	p2--;
79	6.12k	if (p2 == op_str_ptr) {
80	0	SStream_Flush(insn_asm, NULL);
81	0	SStream_concat0(insn_asm, "Invalid!");
82	0	return;
83	0	}
84	6.12k	if (*p2 == 'a')
85	2.88k	strncpy(tmp, "1T", sizeof(tmp));
86	3.23k	else
87	3.23k	strncpy(tmp, "2T", sizeof(tmp));
88	18.4k	} else {
89	18.4k	tmp[0] = '\0';
90	18.4k	}
91	24.6k	SStream mnem_post = { 0 };
92	24.6k	SStream_Init(&mnem_post);
93	24.6k	switch (tms320c64x->funit.unit) {
94	7.46k	case TMS320C64X_FUNIT_D:
95	7.46k	SStream_concat(&mnem_post, ".D%s%u", tmp,
96	7.46k	tms320c64x->funit.side);
97	7.46k	break;
98	5.02k	case TMS320C64X_FUNIT_L:
99	5.02k	SStream_concat(&mnem_post, ".L%s%u", tmp,
100	5.02k	tms320c64x->funit.side);
101	5.02k	break;
102	1.36k	case TMS320C64X_FUNIT_M:
103	1.36k	SStream_concat(&mnem_post, ".M%s%u", tmp,
104	1.36k	tms320c64x->funit.side);
105	1.36k	break;
106	10.2k	case TMS320C64X_FUNIT_S:
107	10.2k	SStream_concat(&mnem_post, ".S%s%u", tmp,
108	10.2k	tms320c64x->funit.side);
109	10.2k	break;
110	24.6k	}
111	24.6k	if (tms320c64x->funit.crosspath > 0)
112	7.14k	SStream_concat0(&mnem_post, "X");
113
114	24.6k	if (op_str_ptr != NULL) {
115		// There is an op_str
116	24.2k	SStream_concat1(&mnem_post, '\t');
117	24.2k	SStream_replc_str(insn_asm, '\t',
118	24.2k	SStream_rbuf(&mnem_post));
119	24.2k	}
120
121	24.6k	if (tms320c64x->parallel != 0)
122	10.9k	SStream_concat0(insn_asm, "\t\|\|");
123	24.6k	SStream_concat0(&ss, SStream_rbuf(insn_asm));
124	24.6k	SStream_Flush(insn_asm, NULL);
125	24.6k	SStream_concat0(insn_asm, SStream_rbuf(&ss));
126	24.6k	}
127	24.6k	}
128
129		#define PRINT_ALIAS_INSTR
130		#include "TMS320C64xGenAsmWriter.inc"
131
132		#define GET_INSTRINFO_ENUM
133		#include "TMS320C64xGenInstrInfo.inc"
134
135		static void printOperand(MCInst MI, unsigned OpNo, SStream O)
136	45.2k	{
137	45.2k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
138	45.2k	unsigned reg;
139
140	45.2k	if (MCOperand_isReg(Op)) {
141	33.6k	reg = MCOperand_getReg(Op);
142	33.6k	if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) &&
143	3.83k	(OpNo == 1)) {
144	1.91k	switch (reg) {
145	1.30k	case TMS320C64X_REG_EFR:
146	1.30k	SStream_concat0(O, "EFR");
147	1.30k	break;
148	437	case TMS320C64X_REG_IFR:
149	437	SStream_concat0(O, "IFR");
150	437	break;
151	179	default:
152	179	SStream_concat0(O, getRegisterName(reg));
153	179	break;
154	1.91k	}
155	31.7k	} else {
156	31.7k	SStream_concat0(O, getRegisterName(reg));
157	31.7k	}
158
159	33.6k	if (MI->csh->detail_opt) {
160	33.6k	MI->flat_insn->detail->tms320c64x
161	33.6k	.operands[MI->flat_insn->detail->tms320c64x
162	33.6k	.op_count]
163	33.6k	.type = TMS320C64X_OP_REG;
164	33.6k	MI->flat_insn->detail->tms320c64x
165	33.6k	.operands[MI->flat_insn->detail->tms320c64x
166	33.6k	.op_count]
167	33.6k	.reg = reg;
168	33.6k	MI->flat_insn->detail->tms320c64x.op_count++;
169	33.6k	}
170	33.6k	} else if (MCOperand_isImm(Op)) {
171	11.6k	int64_t Imm = MCOperand_getImm(Op);
172
173	11.6k	if (Imm >= 0) {
174	9.46k	if (Imm > HEX_THRESHOLD)
175	5.98k	SStream_concat(O, "0x%" PRIx64, Imm);
176	3.48k	else
177	3.48k	SStream_concat(O, "%" PRIu64, Imm);
178	9.46k	} else {
179	2.15k	if (Imm < -HEX_THRESHOLD)
180	1.60k	SStream_concat(O, "-0x%" PRIx64, -Imm);
181	550	else
182	550	SStream_concat(O, "-%" PRIu64, -Imm);
183	2.15k	}
184
185	11.6k	if (MI->csh->detail_opt) {
186	11.6k	MI->flat_insn->detail->tms320c64x
187	11.6k	.operands[MI->flat_insn->detail->tms320c64x
188	11.6k	.op_count]
189	11.6k	.type = TMS320C64X_OP_IMM;
190	11.6k	MI->flat_insn->detail->tms320c64x
191	11.6k	.operands[MI->flat_insn->detail->tms320c64x
192	11.6k	.op_count]
193	11.6k	.imm = Imm;
194	11.6k	MI->flat_insn->detail->tms320c64x.op_count++;
195	11.6k	}
196	11.6k	}
197	45.2k	}
198
199		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O)
200	2.88k	{
201	2.88k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
202	2.88k	int64_t Val = MCOperand_getImm(Op);
203	2.88k	unsigned scaled, base, offset, mode, unit;
204	2.88k	cs_tms320c64x *tms320c64x;
205	2.88k	char st, nd;
206
207	2.88k	scaled = (Val >> 19) & 1;
208	2.88k	base = (Val >> 12) & 0x7f;
209	2.88k	offset = (Val >> 5) & 0x7f;
210	2.88k	mode = (Val >> 1) & 0xf;
211	2.88k	unit = Val & 1;
212
213	2.88k	if (scaled) {
214	2.35k	st = '[';
215	2.35k	nd = ']';
216	2.35k	} else {
217	527	st = '(';
218	527	nd = ')';
219	527	}
220
221	2.88k	switch (mode) {
222	245	case 0:
223	245	SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st,
224	245	offset, nd);
225	245	break;
226	178	case 1:
227	178	SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st,
228	178	offset, nd);
229	178	break;
230	77	case 4:
231	77	SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st,
232	77	getRegisterName(offset), nd);
233	77	break;
234	22	case 5:
235	22	SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st,
236	22	getRegisterName(offset), nd);
237	22	break;
238	524	case 8:
239	524	SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st,
240	524	offset, nd);
241	524	break;
242	191	case 9:
243	191	SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st,
244	191	offset, nd);
245	191	break;
246	483	case 10:
247	483	SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st,
248	483	offset, nd);
249	483	break;
250	301	case 11:
251	301	SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st,
252	301	offset, nd);
253	301	break;
254	146	case 12:
255	146	SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st,
256	146	getRegisterName(offset), nd);
257	146	break;
258	73	case 13:
259	73	SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st,
260	73	getRegisterName(offset), nd);
261	73	break;
262	79	case 14:
263	79	SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st,
264	79	getRegisterName(offset), nd);
265	79	break;
266	567	case 15:
267	567	SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st,
268	567	getRegisterName(offset), nd);
269	567	break;
270	2.88k	}
271
272	2.88k	if (MI->csh->detail_opt) {
273	2.88k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
274
275	2.88k	tms320c64x->operands[tms320c64x->op_count].type =
276	2.88k	TMS320C64X_OP_MEM;
277	2.88k	tms320c64x->operands[tms320c64x->op_count].mem.base = base;
278	2.88k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
279	2.88k	tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
280	2.88k	tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
281	2.88k	switch (mode) {
282	245	case 0:
283	245	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
284	245	TMS320C64X_MEM_DISP_CONSTANT;
285	245	tms320c64x->operands[tms320c64x->op_count]
286	245	.mem.direction = TMS320C64X_MEM_DIR_BW;
287	245	tms320c64x->operands[tms320c64x->op_count].mem.modify =
288	245	TMS320C64X_MEM_MOD_NO;
289	245	break;
290	178	case 1:
291	178	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
292	178	TMS320C64X_MEM_DISP_CONSTANT;
293	178	tms320c64x->operands[tms320c64x->op_count]
294	178	.mem.direction = TMS320C64X_MEM_DIR_FW;
295	178	tms320c64x->operands[tms320c64x->op_count].mem.modify =
296	178	TMS320C64X_MEM_MOD_NO;
297	178	break;
298	77	case 4:
299	77	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
300	77	TMS320C64X_MEM_DISP_REGISTER;
301	77	tms320c64x->operands[tms320c64x->op_count]
302	77	.mem.direction = TMS320C64X_MEM_DIR_BW;
303	77	tms320c64x->operands[tms320c64x->op_count].mem.modify =
304	77	TMS320C64X_MEM_MOD_NO;
305	77	break;
306	22	case 5:
307	22	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
308	22	TMS320C64X_MEM_DISP_REGISTER;
309	22	tms320c64x->operands[tms320c64x->op_count]
310	22	.mem.direction = TMS320C64X_MEM_DIR_FW;
311	22	tms320c64x->operands[tms320c64x->op_count].mem.modify =
312	22	TMS320C64X_MEM_MOD_NO;
313	22	break;
314	524	case 8:
315	524	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
316	524	TMS320C64X_MEM_DISP_CONSTANT;
317	524	tms320c64x->operands[tms320c64x->op_count]
318	524	.mem.direction = TMS320C64X_MEM_DIR_BW;
319	524	tms320c64x->operands[tms320c64x->op_count].mem.modify =
320	524	TMS320C64X_MEM_MOD_PRE;
321	524	break;
322	191	case 9:
323	191	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
324	191	TMS320C64X_MEM_DISP_CONSTANT;
325	191	tms320c64x->operands[tms320c64x->op_count]
326	191	.mem.direction = TMS320C64X_MEM_DIR_FW;
327	191	tms320c64x->operands[tms320c64x->op_count].mem.modify =
328	191	TMS320C64X_MEM_MOD_PRE;
329	191	break;
330	483	case 10:
331	483	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
332	483	TMS320C64X_MEM_DISP_CONSTANT;
333	483	tms320c64x->operands[tms320c64x->op_count]
334	483	.mem.direction = TMS320C64X_MEM_DIR_BW;
335	483	tms320c64x->operands[tms320c64x->op_count].mem.modify =
336	483	TMS320C64X_MEM_MOD_POST;
337	483	break;
338	301	case 11:
339	301	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
340	301	TMS320C64X_MEM_DISP_CONSTANT;
341	301	tms320c64x->operands[tms320c64x->op_count]
342	301	.mem.direction = TMS320C64X_MEM_DIR_FW;
343	301	tms320c64x->operands[tms320c64x->op_count].mem.modify =
344	301	TMS320C64X_MEM_MOD_POST;
345	301	break;
346	146	case 12:
347	146	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
348	146	TMS320C64X_MEM_DISP_REGISTER;
349	146	tms320c64x->operands[tms320c64x->op_count]
350	146	.mem.direction = TMS320C64X_MEM_DIR_BW;
351	146	tms320c64x->operands[tms320c64x->op_count].mem.modify =
352	146	TMS320C64X_MEM_MOD_PRE;
353	146	break;
354	73	case 13:
355	73	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
356	73	TMS320C64X_MEM_DISP_REGISTER;
357	73	tms320c64x->operands[tms320c64x->op_count]
358	73	.mem.direction = TMS320C64X_MEM_DIR_FW;
359	73	tms320c64x->operands[tms320c64x->op_count].mem.modify =
360	73	TMS320C64X_MEM_MOD_PRE;
361	73	break;
362	79	case 14:
363	79	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
364	79	TMS320C64X_MEM_DISP_REGISTER;
365	79	tms320c64x->operands[tms320c64x->op_count]
366	79	.mem.direction = TMS320C64X_MEM_DIR_BW;
367	79	tms320c64x->operands[tms320c64x->op_count].mem.modify =
368	79	TMS320C64X_MEM_MOD_POST;
369	79	break;
370	567	case 15:
371	567	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
372	567	TMS320C64X_MEM_DISP_REGISTER;
373	567	tms320c64x->operands[tms320c64x->op_count]
374	567	.mem.direction = TMS320C64X_MEM_DIR_FW;
375	567	tms320c64x->operands[tms320c64x->op_count].mem.modify =
376	567	TMS320C64X_MEM_MOD_POST;
377	567	break;
378	2.88k	}
379	2.88k	tms320c64x->op_count++;
380	2.88k	}
381	2.88k	}
382
383		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O)
384	3.23k	{
385	3.23k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
386	3.23k	int64_t Val = MCOperand_getImm(Op);
387	3.23k	uint16_t offset;
388	3.23k	unsigned basereg;
389	3.23k	cs_tms320c64x *tms320c64x;
390
391	3.23k	basereg = Val & 0x7f;
392	3.23k	offset = (Val >> 7) & 0x7fff;
393	3.23k	SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);
394
395	3.23k	if (MI->csh->detail_opt) {
396	3.23k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
397
398	3.23k	tms320c64x->operands[tms320c64x->op_count].type =
399	3.23k	TMS320C64X_OP_MEM;
400	3.23k	tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
401	3.23k	tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
402	3.23k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
403	3.23k	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
404	3.23k	TMS320C64X_MEM_DISP_CONSTANT;
405	3.23k	tms320c64x->operands[tms320c64x->op_count].mem.direction =
406	3.23k	TMS320C64X_MEM_DIR_FW;
407	3.23k	tms320c64x->operands[tms320c64x->op_count].mem.modify =
408	3.23k	TMS320C64X_MEM_MOD_NO;
409	3.23k	tms320c64x->op_count++;
410	3.23k	}
411	3.23k	}
412
413		static void printRegPair(MCInst MI, unsigned OpNo, SStream O)
414	6.15k	{
415	6.15k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
416	6.15k	unsigned reg = MCOperand_getReg(Op);
417	6.15k	cs_tms320c64x *tms320c64x;
418
419	6.15k	SStream_concat(O, "%s:%s", getRegisterName(reg + 1),
420	6.15k	getRegisterName(reg));
421
422	6.15k	if (MI->csh->detail_opt) {
423	6.15k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
424
425	6.15k	tms320c64x->operands[tms320c64x->op_count].type =
426	6.15k	TMS320C64X_OP_REGPAIR;
427	6.15k	tms320c64x->operands[tms320c64x->op_count].reg = reg;
428	6.15k	tms320c64x->op_count++;
429	6.15k	}
430	6.15k	}
431
432		static bool printAliasInstruction(MCInst MI, SStream O, MCRegisterInfo *MRI)
433	24.6k	{
434	24.6k	unsigned opcode = MCInst_getOpcode(MI);
435	24.6k	MCOperand *op;
436
437	24.6k	switch (opcode) {
438		/* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
439	48	case TMS320C64x_ADD_d2_rir:
440		/* ADD.L -i, x, y -> SUB.L x, i, y */
441	133	case TMS320C64x_ADD_l1_irr:
442	190	case TMS320C64x_ADD_l1_ipp:
443		/* ADD.S -i, x, y -> SUB.S x, i, y */
444	260	case TMS320C64x_ADD_s1_irr:
445	260	if ((MCInst_getNumOperands(MI) == 3) &&
446	260	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
447	260	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
448	260	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
449	260	(MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
450	87	MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
451	87	op = MCInst_getOperand(MI, 2);
452	87	MCOperand_setImm(op, -MCOperand_getImm(op));
453
454	87	SStream_concat0(O, "SUB\t");
455	87	printOperand(MI, 1, O);
456	87	SStream_concat0(O, ", ");
457	87	printOperand(MI, 2, O);
458	87	SStream_concat0(O, ", ");
459	87	printOperand(MI, 0, O);
460
461	87	return true;
462	87	}
463	173	break;
464	24.6k	}
465	24.5k	switch (opcode) {
466		/* ADD.D 0, x, y -> MV.D x, y */
467	21	case TMS320C64x_ADD_d1_rir:
468		/* OR.D x, 0, y -> MV.D x, y */
469	91	case TMS320C64x_OR_d2_rir:
470		/* ADD.L 0, x, y -> MV.L x, y */
471	107	case TMS320C64x_ADD_l1_irr:
472	151	case TMS320C64x_ADD_l1_ipp:
473		/* OR.L 0, x, y -> MV.L x, y */
474	186	case TMS320C64x_OR_l1_irr:
475		/* ADD.S 0, x, y -> MV.S x, y */
476	256	case TMS320C64x_ADD_s1_irr:
477		/* OR.S 0, x, y -> MV.S x, y */
478	273	case TMS320C64x_OR_s1_irr:
479	273	if ((MCInst_getNumOperands(MI) == 3) &&
480	273	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
481	273	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
482	273	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
483	273	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
484	78	MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
485	78	MI->size--;
486
487	78	SStream_concat0(O, "MV\t");
488	78	printOperand(MI, 1, O);
489	78	SStream_concat0(O, ", ");
490	78	printOperand(MI, 0, O);
491
492	78	return true;
493	78	}
494	195	break;
495	24.5k	}
496	24.4k	switch (opcode) {
497		/* XOR.D -1, x, y -> NOT.D x, y */
498	14	case TMS320C64x_XOR_d2_rir:
499		/* XOR.L -1, x, y -> NOT.L x, y */
500	202	case TMS320C64x_XOR_l1_irr:
501		/* XOR.S -1, x, y -> NOT.S x, y */
502	257	case TMS320C64x_XOR_s1_irr:
503	257	if ((MCInst_getNumOperands(MI) == 3) &&
504	257	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
505	257	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
506	257	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
507	257	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
508	132	MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
509	132	MI->size--;
510
511	132	SStream_concat0(O, "NOT\t");
512	132	printOperand(MI, 1, O);
513	132	SStream_concat0(O, ", ");
514	132	printOperand(MI, 0, O);
515
516	132	return true;
517	132	}
518	125	break;
519	24.4k	}
520	24.3k	switch (opcode) {
521		/* MVK.D 0, x -> ZERO.D x */
522	423	case TMS320C64x_MVK_d1_rr:
523		/* MVK.L 0, x -> ZERO.L x */
524	760	case TMS320C64x_MVK_l2_ir:
525	760	if ((MCInst_getNumOperands(MI) == 2) &&
526	760	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
527	760	MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
528	760	(MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
529	74	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
530	74	MI->size--;
531
532	74	SStream_concat0(O, "ZERO\t");
533	74	printOperand(MI, 0, O);
534
535	74	return true;
536	74	}
537	686	break;
538	24.3k	}
539	24.2k	switch (opcode) {
540		/* SUB.L x, x, y -> ZERO.L y */
541	52	case TMS320C64x_SUB_l1_rrp_x1:
542		/* SUB.S x, x, y -> ZERO.S y */
543	108	case TMS320C64x_SUB_s1_rrr:
544	108	if ((MCInst_getNumOperands(MI) == 3) &&
545	108	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
546	108	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
547	108	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
548	108	(MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
549	108	MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
550	51	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
551	51	MI->size -= 2;
552
553	51	SStream_concat0(O, "ZERO\t");
554	51	printOperand(MI, 0, O);
555
556	51	return true;
557	51	}
558	57	break;
559	24.2k	}
560	24.1k	switch (opcode) {
561		/* SUB.L 0, x, y -> NEG.L x, y */
562	93	case TMS320C64x_SUB_l1_irr:
563	285	case TMS320C64x_SUB_l1_ipp:
564		/* SUB.S 0, x, y -> NEG.S x, y */
565	343	case TMS320C64x_SUB_s1_irr:
566	343	if ((MCInst_getNumOperands(MI) == 3) &&
567	343	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
568	343	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
569	343	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
570	343	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
571	59	MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
572	59	MI->size--;
573
574	59	SStream_concat0(O, "NEG\t");
575	59	printOperand(MI, 1, O);
576	59	SStream_concat0(O, ", ");
577	59	printOperand(MI, 0, O);
578
579	59	return true;
580	59	}
581	284	break;
582	24.1k	}
583	24.1k	switch (opcode) {
584		/* PACKLH2.L x, x, y -> SWAP2.L x, y */
585	92	case TMS320C64x_PACKLH2_l1_rrr_x2:
586		/* PACKLH2.S x, x, y -> SWAP2.S x, y */
587	474	case TMS320C64x_PACKLH2_s1_rrr:
588	474	if ((MCInst_getNumOperands(MI) == 3) &&
589	474	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
590	474	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
591	474	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
592	474	(MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
593	474	MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
594	330	MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
595	330	MI->size--;
596
597	330	SStream_concat0(O, "SWAP2\t");
598	330	printOperand(MI, 1, O);
599	330	SStream_concat0(O, ", ");
600	330	printOperand(MI, 0, O);
601
602	330	return true;
603	330	}
604	144	break;
605	24.1k	}
606	23.7k	switch (opcode) {
607		/* NOP 16 -> IDLE */
608		/* NOP 1 -> NOP */
609	494	case TMS320C64x_NOP_n:
610	494	if ((MCInst_getNumOperands(MI) == 1) &&
611	494	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
612	494	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
613	10	MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
614	10	MI->size--;
615
616	10	SStream_concat0(O, "IDLE");
617
618	10	return true;
619	10	}
620	484	if ((MCInst_getNumOperands(MI) == 1) &&
621	484	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
622	484	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
623	352	MI->size--;
624
625	352	SStream_concat0(O, "NOP");
626
627	352	return true;
628	352	}
629	132	break;
630	23.7k	}
631
632	23.4k	return false;
633	23.7k	}
634
635		void TMS320C64x_printInst(MCInst MI, SStream O, void *Info)
636	24.6k	{
637	24.6k	if (!printAliasInstruction(MI, O, Info))
638	23.4k	printInstruction(MI, O, Info);
639	24.6k	}
640
641		#endif