/src/capstonenext/arch/TMS320C64x/TMS320C64xInstPrinter.c
Line | Count | Source |
1 | | /* Capstone Disassembly Engine */ |
2 | | /* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */ |
3 | | |
4 | | #ifdef CAPSTONE_HAS_TMS320C64X |
5 | | |
6 | | #include <ctype.h> |
7 | | #include <string.h> |
8 | | |
9 | | #include "TMS320C64xInstPrinter.h" |
10 | | #include "../../MCInst.h" |
11 | | #include "../../utils.h" |
12 | | #include "../../SStream.h" |
13 | | #include "../../MCRegisterInfo.h" |
14 | | #include "../../MathExtras.h" |
15 | | #include "TMS320C64xMapping.h" |
16 | | |
17 | | #include "capstone/tms320c64x.h" |
18 | | |
19 | | static const char *getRegisterName(unsigned RegNo); |
20 | | static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); |
21 | | static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O); |
22 | | static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O); |
23 | | static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O); |
24 | | |
25 | | void TMS320C64x_post_printer(csh ud, cs_insn *insn, SStream *insn_asm, |
26 | | MCInst *mci) |
27 | 32.2k | { |
28 | 32.2k | SStream ss; |
29 | 32.2k | const char *op_str_ptr, *p2; |
30 | 32.2k | char tmp[8] = { 0 }; |
31 | 32.2k | unsigned int unit = 0; |
32 | 32.2k | int i; |
33 | 32.2k | cs_tms320c64x *tms320c64x; |
34 | | |
35 | 32.2k | if (mci->csh->detail_opt) { |
36 | 32.2k | tms320c64x = &mci->flat_insn->detail->tms320c64x; |
37 | | |
38 | 32.2k | for (i = 0; i < insn->detail->groups_count; i++) { |
39 | 32.2k | switch (insn->detail->groups[i]) { |
40 | 10.5k | case TMS320C64X_GRP_FUNIT_D: |
41 | 10.5k | unit = TMS320C64X_FUNIT_D; |
42 | 10.5k | break; |
43 | 6.35k | case TMS320C64X_GRP_FUNIT_L: |
44 | 6.35k | unit = TMS320C64X_FUNIT_L; |
45 | 6.35k | break; |
46 | 2.91k | case TMS320C64X_GRP_FUNIT_M: |
47 | 2.91k | unit = TMS320C64X_FUNIT_M; |
48 | 2.91k | break; |
49 | 11.6k | case TMS320C64X_GRP_FUNIT_S: |
50 | 11.6k | unit = TMS320C64X_FUNIT_S; |
51 | 11.6k | break; |
52 | 737 | case TMS320C64X_GRP_FUNIT_NO: |
53 | 737 | unit = TMS320C64X_FUNIT_NO; |
54 | 737 | break; |
55 | 32.2k | } |
56 | 32.2k | if (unit != 0) |
57 | 32.2k | break; |
58 | 32.2k | } |
59 | 32.2k | tms320c64x->funit.unit = unit; |
60 | | |
61 | 32.2k | SStream_Init(&ss); |
62 | 32.2k | if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID) |
63 | 20.6k | SStream_concat( |
64 | 20.6k | &ss, "[%c%s]|", |
65 | 20.6k | (tms320c64x->condition.zero == 1) ? '!' : '|', |
66 | 20.6k | cs_reg_name(ud, tms320c64x->condition.reg)); |
67 | | |
68 | | // Sorry for all the fixes below. I don't have time to add more helper SStream functions. |
69 | | // Before that they messed around with the private buffer of the stream. |
70 | | // So it is better now. But still not efficient. |
71 | 32.2k | op_str_ptr = strchr(SStream_rbuf(insn_asm), '\t'); |
72 | | |
73 | 32.2k | if ((op_str_ptr != NULL) && |
74 | 31.7k | (((p2 = strchr(op_str_ptr, '[')) != NULL) || |
75 | 23.8k | ((p2 = strchr(op_str_ptr, '(')) != NULL))) { |
76 | 32.6k | while ((p2 > op_str_ptr) && |
77 | 32.6k | ((*p2 != 'a') && (*p2 != 'b'))) |
78 | 24.3k | p2--; |
79 | 8.35k | if (p2 == op_str_ptr) { |
80 | 0 | SStream_Flush(insn_asm, NULL); |
81 | 0 | SStream_concat0(insn_asm, "Invalid!"); |
82 | 0 | return; |
83 | 0 | } |
84 | 8.35k | if (*p2 == 'a') |
85 | 3.88k | strncpy(tmp, "1T", sizeof(tmp)); |
86 | 4.47k | else |
87 | 4.47k | strncpy(tmp, "2T", sizeof(tmp)); |
88 | 23.8k | } else { |
89 | 23.8k | tmp[0] = '\0'; |
90 | 23.8k | } |
91 | 32.2k | SStream mnem_post = { 0 }; |
92 | 32.2k | SStream_Init(&mnem_post); |
93 | 32.2k | switch (tms320c64x->funit.unit) { |
94 | 10.5k | case TMS320C64X_FUNIT_D: |
95 | 10.5k | SStream_concat(&mnem_post, ".D%s%u", tmp, |
96 | 10.5k | tms320c64x->funit.side); |
97 | 10.5k | break; |
98 | 6.35k | case TMS320C64X_FUNIT_L: |
99 | 6.35k | SStream_concat(&mnem_post, ".L%s%u", tmp, |
100 | 6.35k | tms320c64x->funit.side); |
101 | 6.35k | break; |
102 | 2.91k | case TMS320C64X_FUNIT_M: |
103 | 2.91k | SStream_concat(&mnem_post, ".M%s%u", tmp, |
104 | 2.91k | tms320c64x->funit.side); |
105 | 2.91k | break; |
106 | 11.6k | case TMS320C64X_FUNIT_S: |
107 | 11.6k | SStream_concat(&mnem_post, ".S%s%u", tmp, |
108 | 11.6k | tms320c64x->funit.side); |
109 | 11.6k | break; |
110 | 32.2k | } |
111 | 32.2k | if (tms320c64x->funit.crosspath > 0) |
112 | 10.0k | SStream_concat0(&mnem_post, "X"); |
113 | | |
114 | 32.2k | if (op_str_ptr != NULL) { |
115 | | // There is an op_str |
116 | 31.7k | SStream_concat1(&mnem_post, '\t'); |
117 | 31.7k | SStream_replc_str(insn_asm, '\t', |
118 | 31.7k | SStream_rbuf(&mnem_post)); |
119 | 31.7k | } |
120 | | |
121 | 32.2k | if (tms320c64x->parallel != 0) |
122 | 14.9k | SStream_concat0(insn_asm, "\t||"); |
123 | 32.2k | SStream_concat0(&ss, SStream_rbuf(insn_asm)); |
124 | 32.2k | SStream_Flush(insn_asm, NULL); |
125 | 32.2k | SStream_concat0(insn_asm, SStream_rbuf(&ss)); |
126 | 32.2k | } |
127 | 32.2k | } |
128 | | |
129 | | #define PRINT_ALIAS_INSTR |
130 | | #include "TMS320C64xGenAsmWriter.inc" |
131 | | |
132 | | #define GET_INSTRINFO_ENUM |
133 | | #include "TMS320C64xGenInstrInfo.inc" |
134 | | |
135 | | static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) |
136 | 60.3k | { |
137 | 60.3k | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
138 | 60.3k | unsigned reg; |
139 | | |
140 | 60.3k | if (MCOperand_isReg(Op)) { |
141 | 45.7k | reg = MCOperand_getReg(Op); |
142 | 45.7k | if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) && |
143 | 3.35k | (OpNo == 1)) { |
144 | 1.67k | switch (reg) { |
145 | 1.13k | case TMS320C64X_REG_EFR: |
146 | 1.13k | SStream_concat0(O, "EFR"); |
147 | 1.13k | break; |
148 | 396 | case TMS320C64X_REG_IFR: |
149 | 396 | SStream_concat0(O, "IFR"); |
150 | 396 | break; |
151 | 151 | default: |
152 | 151 | SStream_concat0(O, getRegisterName(reg)); |
153 | 151 | break; |
154 | 1.67k | } |
155 | 44.1k | } else { |
156 | 44.1k | SStream_concat0(O, getRegisterName(reg)); |
157 | 44.1k | } |
158 | | |
159 | 45.7k | if (MI->csh->detail_opt) { |
160 | 45.7k | MI->flat_insn->detail->tms320c64x |
161 | 45.7k | .operands[MI->flat_insn->detail->tms320c64x |
162 | 45.7k | .op_count] |
163 | 45.7k | .type = TMS320C64X_OP_REG; |
164 | 45.7k | MI->flat_insn->detail->tms320c64x |
165 | 45.7k | .operands[MI->flat_insn->detail->tms320c64x |
166 | 45.7k | .op_count] |
167 | 45.7k | .reg = reg; |
168 | 45.7k | MI->flat_insn->detail->tms320c64x.op_count++; |
169 | 45.7k | } |
170 | 45.7k | } else if (MCOperand_isImm(Op)) { |
171 | 14.5k | int64_t Imm = MCOperand_getImm(Op); |
172 | | |
173 | 14.5k | if (Imm >= 0) { |
174 | 11.9k | if (Imm > HEX_THRESHOLD) |
175 | 5.93k | SStream_concat(O, "0x%" PRIx64, Imm); |
176 | 5.98k | else |
177 | 5.98k | SStream_concat(O, "%" PRIu64, Imm); |
178 | 11.9k | } else { |
179 | 2.66k | if (Imm < -HEX_THRESHOLD) |
180 | 2.28k | SStream_concat(O, "-0x%" PRIx64, -Imm); |
181 | 386 | else |
182 | 386 | SStream_concat(O, "-%" PRIu64, -Imm); |
183 | 2.66k | } |
184 | | |
185 | 14.5k | if (MI->csh->detail_opt) { |
186 | 14.5k | MI->flat_insn->detail->tms320c64x |
187 | 14.5k | .operands[MI->flat_insn->detail->tms320c64x |
188 | 14.5k | .op_count] |
189 | 14.5k | .type = TMS320C64X_OP_IMM; |
190 | 14.5k | MI->flat_insn->detail->tms320c64x |
191 | 14.5k | .operands[MI->flat_insn->detail->tms320c64x |
192 | 14.5k | .op_count] |
193 | 14.5k | .imm = Imm; |
194 | 14.5k | MI->flat_insn->detail->tms320c64x.op_count++; |
195 | 14.5k | } |
196 | 14.5k | } |
197 | 60.3k | } |
198 | | |
199 | | static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O) |
200 | 3.88k | { |
201 | 3.88k | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
202 | 3.88k | int64_t Val = MCOperand_getImm(Op); |
203 | 3.88k | unsigned scaled, base, offset, mode, unit; |
204 | 3.88k | cs_tms320c64x *tms320c64x; |
205 | 3.88k | char st, nd; |
206 | | |
207 | 3.88k | scaled = (Val >> 19) & 1; |
208 | 3.88k | base = (Val >> 12) & 0x7f; |
209 | 3.88k | offset = (Val >> 5) & 0x7f; |
210 | 3.88k | mode = (Val >> 1) & 0xf; |
211 | 3.88k | unit = Val & 1; |
212 | | |
213 | 3.88k | if (scaled) { |
214 | 3.40k | st = '['; |
215 | 3.40k | nd = ']'; |
216 | 3.40k | } else { |
217 | 479 | st = '('; |
218 | 479 | nd = ')'; |
219 | 479 | } |
220 | | |
221 | 3.88k | switch (mode) { |
222 | 515 | case 0: |
223 | 515 | SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st, |
224 | 515 | offset, nd); |
225 | 515 | break; |
226 | 941 | case 1: |
227 | 941 | SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st, |
228 | 941 | offset, nd); |
229 | 941 | break; |
230 | 137 | case 4: |
231 | 137 | SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st, |
232 | 137 | getRegisterName(offset), nd); |
233 | 137 | break; |
234 | 46 | case 5: |
235 | 46 | SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st, |
236 | 46 | getRegisterName(offset), nd); |
237 | 46 | break; |
238 | 813 | case 8: |
239 | 813 | SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st, |
240 | 813 | offset, nd); |
241 | 813 | break; |
242 | 99 | case 9: |
243 | 99 | SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st, |
244 | 99 | offset, nd); |
245 | 99 | break; |
246 | 328 | case 10: |
247 | 328 | SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st, |
248 | 328 | offset, nd); |
249 | 328 | break; |
250 | 293 | case 11: |
251 | 293 | SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st, |
252 | 293 | offset, nd); |
253 | 293 | break; |
254 | 386 | case 12: |
255 | 386 | SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st, |
256 | 386 | getRegisterName(offset), nd); |
257 | 386 | break; |
258 | 110 | case 13: |
259 | 110 | SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st, |
260 | 110 | getRegisterName(offset), nd); |
261 | 110 | break; |
262 | 71 | case 14: |
263 | 71 | SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st, |
264 | 71 | getRegisterName(offset), nd); |
265 | 71 | break; |
266 | 142 | case 15: |
267 | 142 | SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st, |
268 | 142 | getRegisterName(offset), nd); |
269 | 142 | break; |
270 | 3.88k | } |
271 | | |
272 | 3.88k | if (MI->csh->detail_opt) { |
273 | 3.88k | tms320c64x = &MI->flat_insn->detail->tms320c64x; |
274 | | |
275 | 3.88k | tms320c64x->operands[tms320c64x->op_count].type = |
276 | 3.88k | TMS320C64X_OP_MEM; |
277 | 3.88k | tms320c64x->operands[tms320c64x->op_count].mem.base = base; |
278 | 3.88k | tms320c64x->operands[tms320c64x->op_count].mem.disp = offset; |
279 | 3.88k | tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1; |
280 | 3.88k | tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled; |
281 | 3.88k | switch (mode) { |
282 | 515 | case 0: |
283 | 515 | tms320c64x->operands[tms320c64x->op_count].mem.disptype = |
284 | 515 | TMS320C64X_MEM_DISP_CONSTANT; |
285 | 515 | tms320c64x->operands[tms320c64x->op_count] |
286 | 515 | .mem.direction = TMS320C64X_MEM_DIR_BW; |
287 | 515 | tms320c64x->operands[tms320c64x->op_count].mem.modify = |
288 | 515 | TMS320C64X_MEM_MOD_NO; |
289 | 515 | break; |
290 | 941 | case 1: |
291 | 941 | tms320c64x->operands[tms320c64x->op_count].mem.disptype = |
292 | 941 | TMS320C64X_MEM_DISP_CONSTANT; |
293 | 941 | tms320c64x->operands[tms320c64x->op_count] |
294 | 941 | .mem.direction = TMS320C64X_MEM_DIR_FW; |
295 | 941 | tms320c64x->operands[tms320c64x->op_count].mem.modify = |
296 | 941 | TMS320C64X_MEM_MOD_NO; |
297 | 941 | break; |
298 | 137 | case 4: |
299 | 137 | tms320c64x->operands[tms320c64x->op_count].mem.disptype = |
300 | 137 | TMS320C64X_MEM_DISP_REGISTER; |
301 | 137 | tms320c64x->operands[tms320c64x->op_count] |
302 | 137 | .mem.direction = TMS320C64X_MEM_DIR_BW; |
303 | 137 | tms320c64x->operands[tms320c64x->op_count].mem.modify = |
304 | 137 | TMS320C64X_MEM_MOD_NO; |
305 | 137 | break; |
306 | 46 | case 5: |
307 | 46 | tms320c64x->operands[tms320c64x->op_count].mem.disptype = |
308 | 46 | TMS320C64X_MEM_DISP_REGISTER; |
309 | 46 | tms320c64x->operands[tms320c64x->op_count] |
310 | 46 | .mem.direction = TMS320C64X_MEM_DIR_FW; |
311 | 46 | tms320c64x->operands[tms320c64x->op_count].mem.modify = |
312 | 46 | TMS320C64X_MEM_MOD_NO; |
313 | 46 | break; |
314 | 813 | case 8: |
315 | 813 | tms320c64x->operands[tms320c64x->op_count].mem.disptype = |
316 | 813 | TMS320C64X_MEM_DISP_CONSTANT; |
317 | 813 | tms320c64x->operands[tms320c64x->op_count] |
318 | 813 | .mem.direction = TMS320C64X_MEM_DIR_BW; |
319 | 813 | tms320c64x->operands[tms320c64x->op_count].mem.modify = |
320 | 813 | TMS320C64X_MEM_MOD_PRE; |
321 | 813 | break; |
322 | 99 | case 9: |
323 | 99 | tms320c64x->operands[tms320c64x->op_count].mem.disptype = |
324 | 99 | TMS320C64X_MEM_DISP_CONSTANT; |
325 | 99 | tms320c64x->operands[tms320c64x->op_count] |
326 | 99 | .mem.direction = TMS320C64X_MEM_DIR_FW; |
327 | 99 | tms320c64x->operands[tms320c64x->op_count].mem.modify = |
328 | 99 | TMS320C64X_MEM_MOD_PRE; |
329 | 99 | break; |
330 | 328 | case 10: |
331 | 328 | tms320c64x->operands[tms320c64x->op_count].mem.disptype = |
332 | 328 | TMS320C64X_MEM_DISP_CONSTANT; |
333 | 328 | tms320c64x->operands[tms320c64x->op_count] |
334 | 328 | .mem.direction = TMS320C64X_MEM_DIR_BW; |
335 | 328 | tms320c64x->operands[tms320c64x->op_count].mem.modify = |
336 | 328 | TMS320C64X_MEM_MOD_POST; |
337 | 328 | break; |
338 | 293 | case 11: |
339 | 293 | tms320c64x->operands[tms320c64x->op_count].mem.disptype = |
340 | 293 | TMS320C64X_MEM_DISP_CONSTANT; |
341 | 293 | tms320c64x->operands[tms320c64x->op_count] |
342 | 293 | .mem.direction = TMS320C64X_MEM_DIR_FW; |
343 | 293 | tms320c64x->operands[tms320c64x->op_count].mem.modify = |
344 | 293 | TMS320C64X_MEM_MOD_POST; |
345 | 293 | break; |
346 | 386 | case 12: |
347 | 386 | tms320c64x->operands[tms320c64x->op_count].mem.disptype = |
348 | 386 | TMS320C64X_MEM_DISP_REGISTER; |
349 | 386 | tms320c64x->operands[tms320c64x->op_count] |
350 | 386 | .mem.direction = TMS320C64X_MEM_DIR_BW; |
351 | 386 | tms320c64x->operands[tms320c64x->op_count].mem.modify = |
352 | 386 | TMS320C64X_MEM_MOD_PRE; |
353 | 386 | break; |
354 | 110 | case 13: |
355 | 110 | tms320c64x->operands[tms320c64x->op_count].mem.disptype = |
356 | 110 | TMS320C64X_MEM_DISP_REGISTER; |
357 | 110 | tms320c64x->operands[tms320c64x->op_count] |
358 | 110 | .mem.direction = TMS320C64X_MEM_DIR_FW; |
359 | 110 | tms320c64x->operands[tms320c64x->op_count].mem.modify = |
360 | 110 | TMS320C64X_MEM_MOD_PRE; |
361 | 110 | break; |
362 | 71 | case 14: |
363 | 71 | tms320c64x->operands[tms320c64x->op_count].mem.disptype = |
364 | 71 | TMS320C64X_MEM_DISP_REGISTER; |
365 | 71 | tms320c64x->operands[tms320c64x->op_count] |
366 | 71 | .mem.direction = TMS320C64X_MEM_DIR_BW; |
367 | 71 | tms320c64x->operands[tms320c64x->op_count].mem.modify = |
368 | 71 | TMS320C64X_MEM_MOD_POST; |
369 | 71 | break; |
370 | 142 | case 15: |
371 | 142 | tms320c64x->operands[tms320c64x->op_count].mem.disptype = |
372 | 142 | TMS320C64X_MEM_DISP_REGISTER; |
373 | 142 | tms320c64x->operands[tms320c64x->op_count] |
374 | 142 | .mem.direction = TMS320C64X_MEM_DIR_FW; |
375 | 142 | tms320c64x->operands[tms320c64x->op_count].mem.modify = |
376 | 142 | TMS320C64X_MEM_MOD_POST; |
377 | 142 | break; |
378 | 3.88k | } |
379 | 3.88k | tms320c64x->op_count++; |
380 | 3.88k | } |
381 | 3.88k | } |
382 | | |
383 | | static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O) |
384 | 4.47k | { |
385 | 4.47k | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
386 | 4.47k | int64_t Val = MCOperand_getImm(Op); |
387 | 4.47k | uint16_t offset; |
388 | 4.47k | unsigned basereg; |
389 | 4.47k | cs_tms320c64x *tms320c64x; |
390 | | |
391 | 4.47k | basereg = Val & 0x7f; |
392 | 4.47k | offset = (Val >> 7) & 0x7fff; |
393 | 4.47k | SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset); |
394 | | |
395 | 4.47k | if (MI->csh->detail_opt) { |
396 | 4.47k | tms320c64x = &MI->flat_insn->detail->tms320c64x; |
397 | | |
398 | 4.47k | tms320c64x->operands[tms320c64x->op_count].type = |
399 | 4.47k | TMS320C64X_OP_MEM; |
400 | 4.47k | tms320c64x->operands[tms320c64x->op_count].mem.base = basereg; |
401 | 4.47k | tms320c64x->operands[tms320c64x->op_count].mem.unit = 2; |
402 | 4.47k | tms320c64x->operands[tms320c64x->op_count].mem.disp = offset; |
403 | 4.47k | tms320c64x->operands[tms320c64x->op_count].mem.disptype = |
404 | 4.47k | TMS320C64X_MEM_DISP_CONSTANT; |
405 | 4.47k | tms320c64x->operands[tms320c64x->op_count].mem.direction = |
406 | 4.47k | TMS320C64X_MEM_DIR_FW; |
407 | 4.47k | tms320c64x->operands[tms320c64x->op_count].mem.modify = |
408 | 4.47k | TMS320C64X_MEM_MOD_NO; |
409 | 4.47k | tms320c64x->op_count++; |
410 | 4.47k | } |
411 | 4.47k | } |
412 | | |
413 | | static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O) |
414 | 8.85k | { |
415 | 8.85k | MCOperand *Op = MCInst_getOperand(MI, OpNo); |
416 | 8.85k | unsigned reg = MCOperand_getReg(Op); |
417 | 8.85k | cs_tms320c64x *tms320c64x; |
418 | | |
419 | 8.85k | SStream_concat(O, "%s:%s", getRegisterName(reg + 1), |
420 | 8.85k | getRegisterName(reg)); |
421 | | |
422 | 8.85k | if (MI->csh->detail_opt) { |
423 | 8.85k | tms320c64x = &MI->flat_insn->detail->tms320c64x; |
424 | | |
425 | 8.85k | tms320c64x->operands[tms320c64x->op_count].type = |
426 | 8.85k | TMS320C64X_OP_REGPAIR; |
427 | 8.85k | tms320c64x->operands[tms320c64x->op_count].reg = reg; |
428 | 8.85k | tms320c64x->op_count++; |
429 | 8.85k | } |
430 | 8.85k | } |
431 | | |
432 | | static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) |
433 | 32.2k | { |
434 | 32.2k | unsigned opcode = MCInst_getOpcode(MI); |
435 | 32.2k | MCOperand *op; |
436 | | |
437 | 32.2k | switch (opcode) { |
438 | | /* ADD.Dx -i, x, y -> SUB.Dx x, i, y */ |
439 | 379 | case TMS320C64x_ADD_d2_rir: |
440 | | /* ADD.L -i, x, y -> SUB.L x, i, y */ |
441 | 449 | case TMS320C64x_ADD_l1_irr: |
442 | 565 | case TMS320C64x_ADD_l1_ipp: |
443 | | /* ADD.S -i, x, y -> SUB.S x, i, y */ |
444 | 804 | case TMS320C64x_ADD_s1_irr: |
445 | 804 | if ((MCInst_getNumOperands(MI) == 3) && |
446 | 804 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
447 | 804 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
448 | 804 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
449 | 804 | (MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) { |
450 | 345 | MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB); |
451 | 345 | op = MCInst_getOperand(MI, 2); |
452 | 345 | MCOperand_setImm(op, -MCOperand_getImm(op)); |
453 | | |
454 | 345 | SStream_concat0(O, "SUB\t"); |
455 | 345 | printOperand(MI, 1, O); |
456 | 345 | SStream_concat0(O, ", "); |
457 | 345 | printOperand(MI, 2, O); |
458 | 345 | SStream_concat0(O, ", "); |
459 | 345 | printOperand(MI, 0, O); |
460 | | |
461 | 345 | return true; |
462 | 345 | } |
463 | 459 | break; |
464 | 32.2k | } |
465 | 31.8k | switch (opcode) { |
466 | | /* ADD.D 0, x, y -> MV.D x, y */ |
467 | 64 | case TMS320C64x_ADD_d1_rir: |
468 | | /* OR.D x, 0, y -> MV.D x, y */ |
469 | 123 | case TMS320C64x_OR_d2_rir: |
470 | | /* ADD.L 0, x, y -> MV.L x, y */ |
471 | 185 | case TMS320C64x_ADD_l1_irr: |
472 | 287 | case TMS320C64x_ADD_l1_ipp: |
473 | | /* OR.L 0, x, y -> MV.L x, y */ |
474 | 310 | case TMS320C64x_OR_l1_irr: |
475 | | /* ADD.S 0, x, y -> MV.S x, y */ |
476 | 543 | case TMS320C64x_ADD_s1_irr: |
477 | | /* OR.S 0, x, y -> MV.S x, y */ |
478 | 803 | case TMS320C64x_OR_s1_irr: |
479 | 803 | if ((MCInst_getNumOperands(MI) == 3) && |
480 | 803 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
481 | 803 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
482 | 803 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
483 | 803 | (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) { |
484 | 108 | MCInst_setOpcodePub(MI, TMS320C64X_INS_MV); |
485 | 108 | MI->size--; |
486 | | |
487 | 108 | SStream_concat0(O, "MV\t"); |
488 | 108 | printOperand(MI, 1, O); |
489 | 108 | SStream_concat0(O, ", "); |
490 | 108 | printOperand(MI, 0, O); |
491 | | |
492 | 108 | return true; |
493 | 108 | } |
494 | 695 | break; |
495 | 31.8k | } |
496 | 31.7k | switch (opcode) { |
497 | | /* XOR.D -1, x, y -> NOT.D x, y */ |
498 | 130 | case TMS320C64x_XOR_d2_rir: |
499 | | /* XOR.L -1, x, y -> NOT.L x, y */ |
500 | 261 | case TMS320C64x_XOR_l1_irr: |
501 | | /* XOR.S -1, x, y -> NOT.S x, y */ |
502 | 591 | case TMS320C64x_XOR_s1_irr: |
503 | 591 | if ((MCInst_getNumOperands(MI) == 3) && |
504 | 591 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
505 | 591 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
506 | 591 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
507 | 591 | (MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) { |
508 | 110 | MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT); |
509 | 110 | MI->size--; |
510 | | |
511 | 110 | SStream_concat0(O, "NOT\t"); |
512 | 110 | printOperand(MI, 1, O); |
513 | 110 | SStream_concat0(O, ", "); |
514 | 110 | printOperand(MI, 0, O); |
515 | | |
516 | 110 | return true; |
517 | 110 | } |
518 | 481 | break; |
519 | 31.7k | } |
520 | 31.6k | switch (opcode) { |
521 | | /* MVK.D 0, x -> ZERO.D x */ |
522 | 197 | case TMS320C64x_MVK_d1_rr: |
523 | | /* MVK.L 0, x -> ZERO.L x */ |
524 | 535 | case TMS320C64x_MVK_l2_ir: |
525 | 535 | if ((MCInst_getNumOperands(MI) == 2) && |
526 | 535 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
527 | 535 | MCOperand_isImm(MCInst_getOperand(MI, 1)) && |
528 | 535 | (MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) { |
529 | 60 | MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO); |
530 | 60 | MI->size--; |
531 | | |
532 | 60 | SStream_concat0(O, "ZERO\t"); |
533 | 60 | printOperand(MI, 0, O); |
534 | | |
535 | 60 | return true; |
536 | 60 | } |
537 | 475 | break; |
538 | 31.6k | } |
539 | 31.5k | switch (opcode) { |
540 | | /* SUB.L x, x, y -> ZERO.L y */ |
541 | 15 | case TMS320C64x_SUB_l1_rrp_x1: |
542 | | /* SUB.S x, x, y -> ZERO.S y */ |
543 | 119 | case TMS320C64x_SUB_s1_rrr: |
544 | 119 | if ((MCInst_getNumOperands(MI) == 3) && |
545 | 119 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
546 | 119 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
547 | 119 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
548 | 119 | (MCOperand_getReg(MCInst_getOperand(MI, 1)) == |
549 | 119 | MCOperand_getReg(MCInst_getOperand(MI, 2)))) { |
550 | 69 | MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO); |
551 | 69 | MI->size -= 2; |
552 | | |
553 | 69 | SStream_concat0(O, "ZERO\t"); |
554 | 69 | printOperand(MI, 0, O); |
555 | | |
556 | 69 | return true; |
557 | 69 | } |
558 | 50 | break; |
559 | 31.5k | } |
560 | 31.5k | switch (opcode) { |
561 | | /* SUB.L 0, x, y -> NEG.L x, y */ |
562 | 82 | case TMS320C64x_SUB_l1_irr: |
563 | 133 | case TMS320C64x_SUB_l1_ipp: |
564 | | /* SUB.S 0, x, y -> NEG.S x, y */ |
565 | 236 | case TMS320C64x_SUB_s1_irr: |
566 | 236 | if ((MCInst_getNumOperands(MI) == 3) && |
567 | 236 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
568 | 236 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
569 | 236 | MCOperand_isImm(MCInst_getOperand(MI, 2)) && |
570 | 236 | (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) { |
571 | 92 | MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG); |
572 | 92 | MI->size--; |
573 | | |
574 | 92 | SStream_concat0(O, "NEG\t"); |
575 | 92 | printOperand(MI, 1, O); |
576 | 92 | SStream_concat0(O, ", "); |
577 | 92 | printOperand(MI, 0, O); |
578 | | |
579 | 92 | return true; |
580 | 92 | } |
581 | 144 | break; |
582 | 31.5k | } |
583 | 31.4k | switch (opcode) { |
584 | | /* PACKLH2.L x, x, y -> SWAP2.L x, y */ |
585 | 298 | case TMS320C64x_PACKLH2_l1_rrr_x2: |
586 | | /* PACKLH2.S x, x, y -> SWAP2.S x, y */ |
587 | 373 | case TMS320C64x_PACKLH2_s1_rrr: |
588 | 373 | if ((MCInst_getNumOperands(MI) == 3) && |
589 | 373 | MCOperand_isReg(MCInst_getOperand(MI, 0)) && |
590 | 373 | MCOperand_isReg(MCInst_getOperand(MI, 1)) && |
591 | 373 | MCOperand_isReg(MCInst_getOperand(MI, 2)) && |
592 | 373 | (MCOperand_getReg(MCInst_getOperand(MI, 1)) == |
593 | 373 | MCOperand_getReg(MCInst_getOperand(MI, 2)))) { |
594 | 51 | MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2); |
595 | 51 | MI->size--; |
596 | | |
597 | 51 | SStream_concat0(O, "SWAP2\t"); |
598 | 51 | printOperand(MI, 1, O); |
599 | 51 | SStream_concat0(O, ", "); |
600 | 51 | printOperand(MI, 0, O); |
601 | | |
602 | 51 | return true; |
603 | 51 | } |
604 | 322 | break; |
605 | 31.4k | } |
606 | 31.3k | switch (opcode) { |
607 | | /* NOP 16 -> IDLE */ |
608 | | /* NOP 1 -> NOP */ |
609 | 737 | case TMS320C64x_NOP_n: |
610 | 737 | if ((MCInst_getNumOperands(MI) == 1) && |
611 | 737 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
612 | 737 | (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) { |
613 | 26 | MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE); |
614 | 26 | MI->size--; |
615 | | |
616 | 26 | SStream_concat0(O, "IDLE"); |
617 | | |
618 | 26 | return true; |
619 | 26 | } |
620 | 711 | if ((MCInst_getNumOperands(MI) == 1) && |
621 | 711 | MCOperand_isImm(MCInst_getOperand(MI, 0)) && |
622 | 711 | (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) { |
623 | 472 | MI->size--; |
624 | | |
625 | 472 | SStream_concat0(O, "NOP"); |
626 | | |
627 | 472 | return true; |
628 | 472 | } |
629 | 239 | break; |
630 | 31.3k | } |
631 | | |
632 | 30.8k | return false; |
633 | 31.3k | } |
634 | | |
635 | | void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info) |
636 | 32.2k | { |
637 | 32.2k | if (!printAliasInstruction(MI, O, Info)) |
638 | 30.8k | printInstruction(MI, O, Info); |
639 | 32.2k | } |
640 | | |
641 | | #endif |