/src/capstonenext/arch/Sparc/SparcGenAsmWriter.inc
Line | Count | Source |
1 | | /* Capstone Disassembly Engine, https://www.capstone-engine.org */ |
2 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */ |
3 | | /* Rot127 <unisono@quyllur.org> 2022-2024 */ |
4 | | /* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ |
5 | | |
6 | | /* LLVM-commit: <commit> */ |
7 | | /* LLVM-tag: <tag> */ |
8 | | |
9 | | /* Do not edit. */ |
10 | | |
11 | | /* Capstone's LLVM TableGen Backends: */ |
12 | | /* https://github.com/capstone-engine/llvm-capstone */ |
13 | | |
14 | | #include <capstone/platform.h> |
15 | | #include "../../cs_priv.h" |
16 | | |
17 | | /// getMnemonic - This method is automatically generated by tablegen |
18 | | /// from the instruction set description. |
19 | 42.3k | static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { |
20 | 42.3k | #ifndef CAPSTONE_DIET |
21 | 42.3k | static const char AsmStrs[] = { |
22 | 42.3k | /* 0 */ "fcmpd %fcc0, \0" |
23 | 42.3k | /* 14 */ "fcmpq %fcc0, \0" |
24 | 42.3k | /* 28 */ "fcmps %fcc0, \0" |
25 | 42.3k | /* 42 */ "rd %wim, \0" |
26 | 42.3k | /* 52 */ "rdpr %fq, \0" |
27 | 42.3k | /* 63 */ "rd %tbr, \0" |
28 | 42.3k | /* 73 */ "rd %psr, \0" |
29 | 42.3k | /* 83 */ "fsrc1 \0" |
30 | 42.3k | /* 90 */ "fandnot1 \0" |
31 | 42.3k | /* 100 */ "fnot1 \0" |
32 | 42.3k | /* 107 */ "fornot1 \0" |
33 | 42.3k | /* 116 */ "fsra32 \0" |
34 | 42.3k | /* 124 */ "fpsub32 \0" |
35 | 42.3k | /* 133 */ "fpadd32 \0" |
36 | 42.3k | /* 142 */ "edge32 \0" |
37 | 42.3k | /* 150 */ "fcmple32 \0" |
38 | 42.3k | /* 160 */ "fcmpne32 \0" |
39 | 42.3k | /* 170 */ "fpack32 \0" |
40 | 42.3k | /* 179 */ "cmask32 \0" |
41 | 42.3k | /* 188 */ "fsll32 \0" |
42 | 42.3k | /* 196 */ "fsrl32 \0" |
43 | 42.3k | /* 204 */ "fcmpeq32 \0" |
44 | 42.3k | /* 214 */ "fslas32 \0" |
45 | 42.3k | /* 223 */ "fcmpgt32 \0" |
46 | 42.3k | /* 233 */ "array32 \0" |
47 | 42.3k | /* 242 */ "fsrc2 \0" |
48 | 42.3k | /* 249 */ "fandnot2 \0" |
49 | 42.3k | /* 259 */ "fnot2 \0" |
50 | 42.3k | /* 266 */ "fornot2 \0" |
51 | 42.3k | /* 275 */ "fpadd64 \0" |
52 | 42.3k | /* 284 */ "fsra16 \0" |
53 | 42.3k | /* 292 */ "fpsub16 \0" |
54 | 42.3k | /* 301 */ "fpadd16 \0" |
55 | 42.3k | /* 310 */ "edge16 \0" |
56 | 42.3k | /* 318 */ "fcmple16 \0" |
57 | 42.3k | /* 328 */ "fcmpne16 \0" |
58 | 42.3k | /* 338 */ "fpack16 \0" |
59 | 42.3k | /* 347 */ "cmask16 \0" |
60 | 42.3k | /* 356 */ "fsll16 \0" |
61 | 42.3k | /* 364 */ "fsrl16 \0" |
62 | 42.3k | /* 372 */ "fchksm16 \0" |
63 | 42.3k | /* 382 */ "fmean16 \0" |
64 | 42.3k | /* 391 */ "fcmpeq16 \0" |
65 | 42.3k | /* 401 */ "fslas16 \0" |
66 | 42.3k | /* 410 */ "fcmpgt16 \0" |
67 | 42.3k | /* 420 */ "fmul8x16 \0" |
68 | 42.3k | /* 430 */ "fmuld8ulx16 \0" |
69 | 42.3k | /* 443 */ "fmul8ulx16 \0" |
70 | 42.3k | /* 455 */ "fmuld8sux16 \0" |
71 | 42.3k | /* 468 */ "fmul8sux16 \0" |
72 | 42.3k | /* 480 */ "array16 \0" |
73 | 42.3k | /* 489 */ "edge8 \0" |
74 | 42.3k | /* 496 */ "cmask8 \0" |
75 | 42.3k | /* 504 */ "array8 \0" |
76 | 42.3k | /* 512 */ "!ADJCALLSTACKDOWN \0" |
77 | 42.3k | /* 531 */ "!ADJCALLSTACKUP \0" |
78 | 42.3k | /* 548 */ "stba \0" |
79 | 42.3k | /* 554 */ "stda \0" |
80 | 42.3k | /* 560 */ "stha \0" |
81 | 42.3k | /* 566 */ "stqa \0" |
82 | 42.3k | /* 572 */ "sra \0" |
83 | 42.3k | /* 577 */ "faligndata \0" |
84 | 42.3k | /* 589 */ "sta \0" |
85 | 42.3k | /* 594 */ "stxa \0" |
86 | 42.3k | /* 600 */ "stb \0" |
87 | 42.3k | /* 605 */ "sub \0" |
88 | 42.3k | /* 610 */ "smac \0" |
89 | 42.3k | /* 616 */ "umac \0" |
90 | 42.3k | /* 622 */ "tsubcc \0" |
91 | 42.3k | /* 630 */ "addxccc \0" |
92 | 42.3k | /* 639 */ "taddcc \0" |
93 | 42.3k | /* 647 */ "andcc \0" |
94 | 42.3k | /* 654 */ "smulcc \0" |
95 | 42.3k | /* 662 */ "umulcc \0" |
96 | 42.3k | /* 670 */ "andncc \0" |
97 | 42.3k | /* 678 */ "orncc \0" |
98 | 42.3k | /* 685 */ "xnorcc \0" |
99 | 42.3k | /* 693 */ "xorcc \0" |
100 | 42.3k | /* 700 */ "mulscc \0" |
101 | 42.3k | /* 708 */ "sdivcc \0" |
102 | 42.3k | /* 716 */ "udivcc \0" |
103 | 42.3k | /* 724 */ "subxcc \0" |
104 | 42.3k | /* 732 */ "addxcc \0" |
105 | 42.3k | /* 740 */ "popc \0" |
106 | 42.3k | /* 746 */ "addxc \0" |
107 | 42.3k | /* 753 */ "fsubd \0" |
108 | 42.3k | /* 760 */ "fhsubd \0" |
109 | 42.3k | /* 768 */ "add \0" |
110 | 42.3k | /* 773 */ "faddd \0" |
111 | 42.3k | /* 780 */ "fhaddd \0" |
112 | 42.3k | /* 788 */ "fnhaddd \0" |
113 | 42.3k | /* 797 */ "fnaddd \0" |
114 | 42.3k | /* 805 */ "fcmped \0" |
115 | 42.3k | /* 813 */ "fnegd \0" |
116 | 42.3k | /* 820 */ "fmuld \0" |
117 | 42.3k | /* 827 */ "fnmuld \0" |
118 | 42.3k | /* 835 */ "fsmuld \0" |
119 | 42.3k | /* 843 */ "fnsmuld \0" |
120 | 42.3k | /* 852 */ "fand \0" |
121 | 42.3k | /* 858 */ "fnand \0" |
122 | 42.3k | /* 865 */ "fexpand \0" |
123 | 42.3k | /* 874 */ "fitod \0" |
124 | 42.3k | /* 881 */ "fqtod \0" |
125 | 42.3k | /* 888 */ "fstod \0" |
126 | 42.3k | /* 895 */ "fxtod \0" |
127 | 42.3k | /* 902 */ "movxtod \0" |
128 | 42.3k | /* 911 */ "fcmpd \0" |
129 | 42.3k | /* 918 */ "flcmpd \0" |
130 | 42.3k | /* 926 */ "rd \0" |
131 | 42.3k | /* 930 */ "fabsd \0" |
132 | 42.3k | /* 937 */ "fsqrtd \0" |
133 | 42.3k | /* 945 */ "std \0" |
134 | 42.3k | /* 950 */ "fdivd \0" |
135 | 42.3k | /* 957 */ "fmovd \0" |
136 | 42.3k | /* 964 */ "fpmerge \0" |
137 | 42.3k | /* 973 */ "bshuffle \0" |
138 | 42.3k | /* 983 */ "fone \0" |
139 | 42.3k | /* 989 */ "restore \0" |
140 | 42.3k | /* 998 */ "save \0" |
141 | 42.3k | /* 1004 */ "flush \0" |
142 | 42.3k | /* 1011 */ "sth \0" |
143 | 42.3k | /* 1016 */ "sethi \0" |
144 | 42.3k | /* 1023 */ "umulxhi \0" |
145 | 42.3k | /* 1032 */ "xmulxhi \0" |
146 | 42.3k | /* 1041 */ "fdtoi \0" |
147 | 42.3k | /* 1048 */ "fqtoi \0" |
148 | 42.3k | /* 1055 */ "fstoi \0" |
149 | 42.3k | /* 1062 */ "bmask \0" |
150 | 42.3k | /* 1069 */ "edge32l \0" |
151 | 42.3k | /* 1078 */ "edge16l \0" |
152 | 42.3k | /* 1087 */ "edge8l \0" |
153 | 42.3k | /* 1095 */ "fmul8x16al \0" |
154 | 42.3k | /* 1107 */ "call \0" |
155 | 42.3k | /* 1113 */ "sll \0" |
156 | 42.3k | /* 1118 */ "jmpl \0" |
157 | 42.3k | /* 1124 */ "alignaddrl \0" |
158 | 42.3k | /* 1136 */ "srl \0" |
159 | 42.3k | /* 1141 */ "smul \0" |
160 | 42.3k | /* 1147 */ "umul \0" |
161 | 42.3k | /* 1153 */ "edge32n \0" |
162 | 42.3k | /* 1162 */ "edge16n \0" |
163 | 42.3k | /* 1171 */ "edge8n \0" |
164 | 42.3k | /* 1179 */ "andn \0" |
165 | 42.3k | /* 1185 */ "edge32ln \0" |
166 | 42.3k | /* 1195 */ "edge16ln \0" |
167 | 42.3k | /* 1205 */ "edge8ln \0" |
168 | 42.3k | /* 1214 */ "orn \0" |
169 | 42.3k | /* 1219 */ "pdistn \0" |
170 | 42.3k | /* 1227 */ "fzero \0" |
171 | 42.3k | /* 1234 */ "unimp \0" |
172 | 42.3k | /* 1241 */ "jmp \0" |
173 | 42.3k | /* 1246 */ "fsubq \0" |
174 | 42.3k | /* 1253 */ "faddq \0" |
175 | 42.3k | /* 1260 */ "fcmpeq \0" |
176 | 42.3k | /* 1268 */ "fnegq \0" |
177 | 42.3k | /* 1275 */ "fdmulq \0" |
178 | 42.3k | /* 1283 */ "fmulq \0" |
179 | 42.3k | /* 1290 */ "fdtoq \0" |
180 | 42.3k | /* 1297 */ "fitoq \0" |
181 | 42.3k | /* 1304 */ "fstoq \0" |
182 | 42.3k | /* 1311 */ "fxtoq \0" |
183 | 42.3k | /* 1318 */ "fcmpq \0" |
184 | 42.3k | /* 1325 */ "fabsq \0" |
185 | 42.3k | /* 1332 */ "fsqrtq \0" |
186 | 42.3k | /* 1340 */ "stq \0" |
187 | 42.3k | /* 1345 */ "fdivq \0" |
188 | 42.3k | /* 1352 */ "fmovq \0" |
189 | 42.3k | /* 1359 */ "membar \0" |
190 | 42.3k | /* 1367 */ "alignaddr \0" |
191 | 42.3k | /* 1378 */ "sir \0" |
192 | 42.3k | /* 1383 */ "for \0" |
193 | 42.3k | /* 1388 */ "fnor \0" |
194 | 42.3k | /* 1394 */ "fxnor \0" |
195 | 42.3k | /* 1401 */ "fxor \0" |
196 | 42.3k | /* 1407 */ "rdpr \0" |
197 | 42.3k | /* 1413 */ "wrpr \0" |
198 | 42.3k | /* 1419 */ "pwr \0" |
199 | 42.3k | /* 1424 */ "fsrc1s \0" |
200 | 42.3k | /* 1432 */ "fandnot1s \0" |
201 | 42.3k | /* 1443 */ "fnot1s \0" |
202 | 42.3k | /* 1451 */ "fornot1s \0" |
203 | 42.3k | /* 1461 */ "fpsub32s \0" |
204 | 42.3k | /* 1471 */ "fpadd32s \0" |
205 | 42.3k | /* 1481 */ "fsrc2s \0" |
206 | 42.3k | /* 1489 */ "fandnot2s \0" |
207 | 42.3k | /* 1500 */ "fnot2s \0" |
208 | 42.3k | /* 1508 */ "fornot2s \0" |
209 | 42.3k | /* 1518 */ "fpsub16s \0" |
210 | 42.3k | /* 1528 */ "fpadd16s \0" |
211 | 42.3k | /* 1538 */ "fsubs \0" |
212 | 42.3k | /* 1545 */ "fhsubs \0" |
213 | 42.3k | /* 1553 */ "fadds \0" |
214 | 42.3k | /* 1560 */ "fhadds \0" |
215 | 42.3k | /* 1568 */ "fnhadds \0" |
216 | 42.3k | /* 1577 */ "fnadds \0" |
217 | 42.3k | /* 1585 */ "fands \0" |
218 | 42.3k | /* 1592 */ "fnands \0" |
219 | 42.3k | /* 1600 */ "fones \0" |
220 | 42.3k | /* 1607 */ "fcmpes \0" |
221 | 42.3k | /* 1615 */ "fnegs \0" |
222 | 42.3k | /* 1622 */ "fmuls \0" |
223 | 42.3k | /* 1629 */ "fnmuls \0" |
224 | 42.3k | /* 1637 */ "fzeros \0" |
225 | 42.3k | /* 1645 */ "fdtos \0" |
226 | 42.3k | /* 1652 */ "fitos \0" |
227 | 42.3k | /* 1659 */ "fqtos \0" |
228 | 42.3k | /* 1666 */ "movwtos \0" |
229 | 42.3k | /* 1675 */ "fxtos \0" |
230 | 42.3k | /* 1682 */ "fcmps \0" |
231 | 42.3k | /* 1689 */ "flcmps \0" |
232 | 42.3k | /* 1697 */ "fors \0" |
233 | 42.3k | /* 1703 */ "fnors \0" |
234 | 42.3k | /* 1710 */ "fxnors \0" |
235 | 42.3k | /* 1718 */ "fxors \0" |
236 | 42.3k | /* 1725 */ "fabss \0" |
237 | 42.3k | /* 1732 */ "fsqrts \0" |
238 | 42.3k | /* 1740 */ "fdivs \0" |
239 | 42.3k | /* 1747 */ "fmovs \0" |
240 | 42.3k | /* 1754 */ "set \0" |
241 | 42.3k | /* 1759 */ "lzcnt \0" |
242 | 42.3k | /* 1766 */ "pdist \0" |
243 | 42.3k | /* 1773 */ "rett \0" |
244 | 42.3k | /* 1779 */ "fmul8x16au \0" |
245 | 42.3k | /* 1791 */ "sdiv \0" |
246 | 42.3k | /* 1797 */ "udiv \0" |
247 | 42.3k | /* 1803 */ "tsubcctv \0" |
248 | 42.3k | /* 1813 */ "taddcctv \0" |
249 | 42.3k | /* 1823 */ "movstosw \0" |
250 | 42.3k | /* 1833 */ "movstouw \0" |
251 | 42.3k | /* 1843 */ "srax \0" |
252 | 42.3k | /* 1849 */ "subx \0" |
253 | 42.3k | /* 1855 */ "addx \0" |
254 | 42.3k | /* 1861 */ "fpackfix \0" |
255 | 42.3k | /* 1871 */ "sllx \0" |
256 | 42.3k | /* 1877 */ "srlx \0" |
257 | 42.3k | /* 1883 */ "xmulx \0" |
258 | 42.3k | /* 1890 */ "fdtox \0" |
259 | 42.3k | /* 1897 */ "movdtox \0" |
260 | 42.3k | /* 1906 */ "fqtox \0" |
261 | 42.3k | /* 1913 */ "fstox \0" |
262 | 42.3k | /* 1920 */ "setx \0" |
263 | 42.3k | /* 1926 */ "stx \0" |
264 | 42.3k | /* 1931 */ "sdivx \0" |
265 | 42.3k | /* 1938 */ "udivx \0" |
266 | 42.3k | /* 1945 */ "; SELECT_CC_DFP_FCC PSEUDO!\0" |
267 | 42.3k | /* 1973 */ "; SELECT_CC_QFP_FCC PSEUDO!\0" |
268 | 42.3k | /* 2001 */ "; SELECT_CC_FP_FCC PSEUDO!\0" |
269 | 42.3k | /* 2028 */ "; SELECT_CC_Int_FCC PSEUDO!\0" |
270 | 42.3k | /* 2056 */ "; SELECT_CC_DFP_ICC PSEUDO!\0" |
271 | 42.3k | /* 2084 */ "; SELECT_CC_QFP_ICC PSEUDO!\0" |
272 | 42.3k | /* 2112 */ "; SELECT_CC_FP_ICC PSEUDO!\0" |
273 | 42.3k | /* 2139 */ "; SELECT_CC_Int_ICC PSEUDO!\0" |
274 | 42.3k | /* 2167 */ "; SELECT_CC_DFP_XCC PSEUDO!\0" |
275 | 42.3k | /* 2195 */ "; SELECT_CC_QFP_XCC PSEUDO!\0" |
276 | 42.3k | /* 2223 */ "; SELECT_CC_FP_XCC PSEUDO!\0" |
277 | 42.3k | /* 2250 */ "; SELECT_CC_Int_XCC PSEUDO!\0" |
278 | 42.3k | /* 2278 */ "jmp %i7+\0" |
279 | 42.3k | /* 2287 */ "jmp %o7+\0" |
280 | 42.3k | /* 2296 */ "# XRay Function Patchable RET.\0" |
281 | 42.3k | /* 2327 */ "# XRay Typed Event Log.\0" |
282 | 42.3k | /* 2351 */ "# XRay Custom Event Log.\0" |
283 | 42.3k | /* 2376 */ "# XRay Function Enter.\0" |
284 | 42.3k | /* 2399 */ "# XRay Tail Call Exit.\0" |
285 | 42.3k | /* 2422 */ "# XRay Function Exit.\0" |
286 | 42.3k | /* 2444 */ "flush %g0\0" |
287 | 42.3k | /* 2454 */ "ta 1\0" |
288 | 42.3k | /* 2459 */ "ta 3\0" |
289 | 42.3k | /* 2464 */ "ta 5\0" |
290 | 42.3k | /* 2469 */ "LIFETIME_END\0" |
291 | 42.3k | /* 2482 */ "PSEUDO_PROBE\0" |
292 | 42.3k | /* 2495 */ "BUNDLE\0" |
293 | 42.3k | /* 2502 */ "DBG_VALUE\0" |
294 | 42.3k | /* 2512 */ "DBG_INSTR_REF\0" |
295 | 42.3k | /* 2526 */ "DBG_PHI\0" |
296 | 42.3k | /* 2534 */ "DBG_LABEL\0" |
297 | 42.3k | /* 2544 */ "LIFETIME_START\0" |
298 | 42.3k | /* 2559 */ "DBG_VALUE_LIST\0" |
299 | 42.3k | /* 2574 */ "std %cq, [\0" |
300 | 42.3k | /* 2585 */ "std %fq, [\0" |
301 | 42.3k | /* 2596 */ "st %csr, [\0" |
302 | 42.3k | /* 2607 */ "st %fsr, [\0" |
303 | 42.3k | /* 2618 */ "stx %fsr, [\0" |
304 | 42.3k | /* 2630 */ "ldsba [\0" |
305 | 42.3k | /* 2638 */ "lduba [\0" |
306 | 42.3k | /* 2646 */ "ldstuba [\0" |
307 | 42.3k | /* 2656 */ "ldda [\0" |
308 | 42.3k | /* 2663 */ "lda [\0" |
309 | 42.3k | /* 2669 */ "ldsha [\0" |
310 | 42.3k | /* 2677 */ "lduha [\0" |
311 | 42.3k | /* 2685 */ "swapa [\0" |
312 | 42.3k | /* 2693 */ "ldqa [\0" |
313 | 42.3k | /* 2700 */ "casa [\0" |
314 | 42.3k | /* 2707 */ "ldswa [\0" |
315 | 42.3k | /* 2715 */ "ldxa [\0" |
316 | 42.3k | /* 2722 */ "casxa [\0" |
317 | 42.3k | /* 2730 */ "ldsb [\0" |
318 | 42.3k | /* 2737 */ "ldub [\0" |
319 | 42.3k | /* 2744 */ "ldstub [\0" |
320 | 42.3k | /* 2753 */ "ldd [\0" |
321 | 42.3k | /* 2759 */ "ld [\0" |
322 | 42.3k | /* 2764 */ "prefetch [\0" |
323 | 42.3k | /* 2775 */ "ldsh [\0" |
324 | 42.3k | /* 2782 */ "lduh [\0" |
325 | 42.3k | /* 2789 */ "swap [\0" |
326 | 42.3k | /* 2796 */ "ldq [\0" |
327 | 42.3k | /* 2802 */ "ldsw [\0" |
328 | 42.3k | /* 2809 */ "ldx [\0" |
329 | 42.3k | /* 2815 */ "cb\0" |
330 | 42.3k | /* 2818 */ "fb\0" |
331 | 42.3k | /* 2821 */ "restored\0" |
332 | 42.3k | /* 2830 */ "saved\0" |
333 | 42.3k | /* 2836 */ "fmovrd\0" |
334 | 42.3k | /* 2843 */ "fmovd\0" |
335 | 42.3k | /* 2849 */ "done\0" |
336 | 42.3k | /* 2854 */ "# FEntry call\0" |
337 | 42.3k | /* 2868 */ "siam\0" |
338 | 42.3k | /* 2873 */ "shutdown\0" |
339 | 42.3k | /* 2882 */ "nop\0" |
340 | 42.3k | /* 2886 */ "fmovrq\0" |
341 | 42.3k | /* 2893 */ "fmovq\0" |
342 | 42.3k | /* 2899 */ "stbar\0" |
343 | 42.3k | /* 2905 */ "br\0" |
344 | 42.3k | /* 2908 */ "movr\0" |
345 | 42.3k | /* 2913 */ "fmovrs\0" |
346 | 42.3k | /* 2920 */ "fmovs\0" |
347 | 42.3k | /* 2926 */ "t\0" |
348 | 42.3k | /* 2928 */ "mov\0" |
349 | 42.3k | /* 2932 */ "flushw\0" |
350 | 42.3k | /* 2939 */ "retry\0" |
351 | 42.3k | }; |
352 | 42.3k | #endif // CAPSTONE_DIET |
353 | | |
354 | 42.3k | static const uint32_t OpInfo0[] = { |
355 | 42.3k | 0U, // PHI |
356 | 42.3k | 0U, // INLINEASM |
357 | 42.3k | 0U, // INLINEASM_BR |
358 | 42.3k | 0U, // CFI_INSTRUCTION |
359 | 42.3k | 0U, // EH_LABEL |
360 | 42.3k | 0U, // GC_LABEL |
361 | 42.3k | 0U, // ANNOTATION_LABEL |
362 | 42.3k | 0U, // KILL |
363 | 42.3k | 0U, // EXTRACT_SUBREG |
364 | 42.3k | 0U, // INSERT_SUBREG |
365 | 42.3k | 0U, // IMPLICIT_DEF |
366 | 42.3k | 0U, // SUBREG_TO_REG |
367 | 42.3k | 0U, // COPY_TO_REGCLASS |
368 | 42.3k | 2503U, // DBG_VALUE |
369 | 42.3k | 2560U, // DBG_VALUE_LIST |
370 | 42.3k | 2513U, // DBG_INSTR_REF |
371 | 42.3k | 2527U, // DBG_PHI |
372 | 42.3k | 2535U, // DBG_LABEL |
373 | 42.3k | 0U, // REG_SEQUENCE |
374 | 42.3k | 0U, // COPY |
375 | 42.3k | 2496U, // BUNDLE |
376 | 42.3k | 2545U, // LIFETIME_START |
377 | 42.3k | 2470U, // LIFETIME_END |
378 | 42.3k | 2483U, // PSEUDO_PROBE |
379 | 42.3k | 0U, // ARITH_FENCE |
380 | 42.3k | 0U, // STACKMAP |
381 | 42.3k | 2855U, // FENTRY_CALL |
382 | 42.3k | 0U, // PATCHPOINT |
383 | 42.3k | 0U, // LOAD_STACK_GUARD |
384 | 42.3k | 0U, // PREALLOCATED_SETUP |
385 | 42.3k | 0U, // PREALLOCATED_ARG |
386 | 42.3k | 0U, // STATEPOINT |
387 | 42.3k | 0U, // LOCAL_ESCAPE |
388 | 42.3k | 0U, // FAULTING_OP |
389 | 42.3k | 0U, // PATCHABLE_OP |
390 | 42.3k | 2377U, // PATCHABLE_FUNCTION_ENTER |
391 | 42.3k | 2297U, // PATCHABLE_RET |
392 | 42.3k | 2423U, // PATCHABLE_FUNCTION_EXIT |
393 | 42.3k | 2400U, // PATCHABLE_TAIL_CALL |
394 | 42.3k | 2352U, // PATCHABLE_EVENT_CALL |
395 | 42.3k | 2328U, // PATCHABLE_TYPED_EVENT_CALL |
396 | 42.3k | 0U, // ICALL_BRANCH_FUNNEL |
397 | 42.3k | 0U, // MEMBARRIER |
398 | 42.3k | 0U, // JUMP_TABLE_DEBUG_INFO |
399 | 42.3k | 0U, // G_ASSERT_SEXT |
400 | 42.3k | 0U, // G_ASSERT_ZEXT |
401 | 42.3k | 0U, // G_ASSERT_ALIGN |
402 | 42.3k | 0U, // G_ADD |
403 | 42.3k | 0U, // G_SUB |
404 | 42.3k | 0U, // G_MUL |
405 | 42.3k | 0U, // G_SDIV |
406 | 42.3k | 0U, // G_UDIV |
407 | 42.3k | 0U, // G_SREM |
408 | 42.3k | 0U, // G_UREM |
409 | 42.3k | 0U, // G_SDIVREM |
410 | 42.3k | 0U, // G_UDIVREM |
411 | 42.3k | 0U, // G_AND |
412 | 42.3k | 0U, // G_OR |
413 | 42.3k | 0U, // G_XOR |
414 | 42.3k | 0U, // G_IMPLICIT_DEF |
415 | 42.3k | 0U, // G_PHI |
416 | 42.3k | 0U, // G_FRAME_INDEX |
417 | 42.3k | 0U, // G_GLOBAL_VALUE |
418 | 42.3k | 0U, // G_CONSTANT_POOL |
419 | 42.3k | 0U, // G_EXTRACT |
420 | 42.3k | 0U, // G_UNMERGE_VALUES |
421 | 42.3k | 0U, // G_INSERT |
422 | 42.3k | 0U, // G_MERGE_VALUES |
423 | 42.3k | 0U, // G_BUILD_VECTOR |
424 | 42.3k | 0U, // G_BUILD_VECTOR_TRUNC |
425 | 42.3k | 0U, // G_CONCAT_VECTORS |
426 | 42.3k | 0U, // G_PTRTOINT |
427 | 42.3k | 0U, // G_INTTOPTR |
428 | 42.3k | 0U, // G_BITCAST |
429 | 42.3k | 0U, // G_FREEZE |
430 | 42.3k | 0U, // G_CONSTANT_FOLD_BARRIER |
431 | 42.3k | 0U, // G_INTRINSIC_FPTRUNC_ROUND |
432 | 42.3k | 0U, // G_INTRINSIC_TRUNC |
433 | 42.3k | 0U, // G_INTRINSIC_ROUND |
434 | 42.3k | 0U, // G_INTRINSIC_LRINT |
435 | 42.3k | 0U, // G_INTRINSIC_ROUNDEVEN |
436 | 42.3k | 0U, // G_READCYCLECOUNTER |
437 | 42.3k | 0U, // G_LOAD |
438 | 42.3k | 0U, // G_SEXTLOAD |
439 | 42.3k | 0U, // G_ZEXTLOAD |
440 | 42.3k | 0U, // G_INDEXED_LOAD |
441 | 42.3k | 0U, // G_INDEXED_SEXTLOAD |
442 | 42.3k | 0U, // G_INDEXED_ZEXTLOAD |
443 | 42.3k | 0U, // G_STORE |
444 | 42.3k | 0U, // G_INDEXED_STORE |
445 | 42.3k | 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
446 | 42.3k | 0U, // G_ATOMIC_CMPXCHG |
447 | 42.3k | 0U, // G_ATOMICRMW_XCHG |
448 | 42.3k | 0U, // G_ATOMICRMW_ADD |
449 | 42.3k | 0U, // G_ATOMICRMW_SUB |
450 | 42.3k | 0U, // G_ATOMICRMW_AND |
451 | 42.3k | 0U, // G_ATOMICRMW_NAND |
452 | 42.3k | 0U, // G_ATOMICRMW_OR |
453 | 42.3k | 0U, // G_ATOMICRMW_XOR |
454 | 42.3k | 0U, // G_ATOMICRMW_MAX |
455 | 42.3k | 0U, // G_ATOMICRMW_MIN |
456 | 42.3k | 0U, // G_ATOMICRMW_UMAX |
457 | 42.3k | 0U, // G_ATOMICRMW_UMIN |
458 | 42.3k | 0U, // G_ATOMICRMW_FADD |
459 | 42.3k | 0U, // G_ATOMICRMW_FSUB |
460 | 42.3k | 0U, // G_ATOMICRMW_FMAX |
461 | 42.3k | 0U, // G_ATOMICRMW_FMIN |
462 | 42.3k | 0U, // G_ATOMICRMW_UINC_WRAP |
463 | 42.3k | 0U, // G_ATOMICRMW_UDEC_WRAP |
464 | 42.3k | 0U, // G_FENCE |
465 | 42.3k | 0U, // G_PREFETCH |
466 | 42.3k | 0U, // G_BRCOND |
467 | 42.3k | 0U, // G_BRINDIRECT |
468 | 42.3k | 0U, // G_INVOKE_REGION_START |
469 | 42.3k | 0U, // G_INTRINSIC |
470 | 42.3k | 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
471 | 42.3k | 0U, // G_INTRINSIC_CONVERGENT |
472 | 42.3k | 0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
473 | 42.3k | 0U, // G_ANYEXT |
474 | 42.3k | 0U, // G_TRUNC |
475 | 42.3k | 0U, // G_CONSTANT |
476 | 42.3k | 0U, // G_FCONSTANT |
477 | 42.3k | 0U, // G_VASTART |
478 | 42.3k | 0U, // G_VAARG |
479 | 42.3k | 0U, // G_SEXT |
480 | 42.3k | 0U, // G_SEXT_INREG |
481 | 42.3k | 0U, // G_ZEXT |
482 | 42.3k | 0U, // G_SHL |
483 | 42.3k | 0U, // G_LSHR |
484 | 42.3k | 0U, // G_ASHR |
485 | 42.3k | 0U, // G_FSHL |
486 | 42.3k | 0U, // G_FSHR |
487 | 42.3k | 0U, // G_ROTR |
488 | 42.3k | 0U, // G_ROTL |
489 | 42.3k | 0U, // G_ICMP |
490 | 42.3k | 0U, // G_FCMP |
491 | 42.3k | 0U, // G_SELECT |
492 | 42.3k | 0U, // G_UADDO |
493 | 42.3k | 0U, // G_UADDE |
494 | 42.3k | 0U, // G_USUBO |
495 | 42.3k | 0U, // G_USUBE |
496 | 42.3k | 0U, // G_SADDO |
497 | 42.3k | 0U, // G_SADDE |
498 | 42.3k | 0U, // G_SSUBO |
499 | 42.3k | 0U, // G_SSUBE |
500 | 42.3k | 0U, // G_UMULO |
501 | 42.3k | 0U, // G_SMULO |
502 | 42.3k | 0U, // G_UMULH |
503 | 42.3k | 0U, // G_SMULH |
504 | 42.3k | 0U, // G_UADDSAT |
505 | 42.3k | 0U, // G_SADDSAT |
506 | 42.3k | 0U, // G_USUBSAT |
507 | 42.3k | 0U, // G_SSUBSAT |
508 | 42.3k | 0U, // G_USHLSAT |
509 | 42.3k | 0U, // G_SSHLSAT |
510 | 42.3k | 0U, // G_SMULFIX |
511 | 42.3k | 0U, // G_UMULFIX |
512 | 42.3k | 0U, // G_SMULFIXSAT |
513 | 42.3k | 0U, // G_UMULFIXSAT |
514 | 42.3k | 0U, // G_SDIVFIX |
515 | 42.3k | 0U, // G_UDIVFIX |
516 | 42.3k | 0U, // G_SDIVFIXSAT |
517 | 42.3k | 0U, // G_UDIVFIXSAT |
518 | 42.3k | 0U, // G_FADD |
519 | 42.3k | 0U, // G_FSUB |
520 | 42.3k | 0U, // G_FMUL |
521 | 42.3k | 0U, // G_FMA |
522 | 42.3k | 0U, // G_FMAD |
523 | 42.3k | 0U, // G_FDIV |
524 | 42.3k | 0U, // G_FREM |
525 | 42.3k | 0U, // G_FPOW |
526 | 42.3k | 0U, // G_FPOWI |
527 | 42.3k | 0U, // G_FEXP |
528 | 42.3k | 0U, // G_FEXP2 |
529 | 42.3k | 0U, // G_FEXP10 |
530 | 42.3k | 0U, // G_FLOG |
531 | 42.3k | 0U, // G_FLOG2 |
532 | 42.3k | 0U, // G_FLOG10 |
533 | 42.3k | 0U, // G_FLDEXP |
534 | 42.3k | 0U, // G_FFREXP |
535 | 42.3k | 0U, // G_FNEG |
536 | 42.3k | 0U, // G_FPEXT |
537 | 42.3k | 0U, // G_FPTRUNC |
538 | 42.3k | 0U, // G_FPTOSI |
539 | 42.3k | 0U, // G_FPTOUI |
540 | 42.3k | 0U, // G_SITOFP |
541 | 42.3k | 0U, // G_UITOFP |
542 | 42.3k | 0U, // G_FABS |
543 | 42.3k | 0U, // G_FCOPYSIGN |
544 | 42.3k | 0U, // G_IS_FPCLASS |
545 | 42.3k | 0U, // G_FCANONICALIZE |
546 | 42.3k | 0U, // G_FMINNUM |
547 | 42.3k | 0U, // G_FMAXNUM |
548 | 42.3k | 0U, // G_FMINNUM_IEEE |
549 | 42.3k | 0U, // G_FMAXNUM_IEEE |
550 | 42.3k | 0U, // G_FMINIMUM |
551 | 42.3k | 0U, // G_FMAXIMUM |
552 | 42.3k | 0U, // G_GET_FPENV |
553 | 42.3k | 0U, // G_SET_FPENV |
554 | 42.3k | 0U, // G_RESET_FPENV |
555 | 42.3k | 0U, // G_GET_FPMODE |
556 | 42.3k | 0U, // G_SET_FPMODE |
557 | 42.3k | 0U, // G_RESET_FPMODE |
558 | 42.3k | 0U, // G_PTR_ADD |
559 | 42.3k | 0U, // G_PTRMASK |
560 | 42.3k | 0U, // G_SMIN |
561 | 42.3k | 0U, // G_SMAX |
562 | 42.3k | 0U, // G_UMIN |
563 | 42.3k | 0U, // G_UMAX |
564 | 42.3k | 0U, // G_ABS |
565 | 42.3k | 0U, // G_LROUND |
566 | 42.3k | 0U, // G_LLROUND |
567 | 42.3k | 0U, // G_BR |
568 | 42.3k | 0U, // G_BRJT |
569 | 42.3k | 0U, // G_INSERT_VECTOR_ELT |
570 | 42.3k | 0U, // G_EXTRACT_VECTOR_ELT |
571 | 42.3k | 0U, // G_SHUFFLE_VECTOR |
572 | 42.3k | 0U, // G_CTTZ |
573 | 42.3k | 0U, // G_CTTZ_ZERO_UNDEF |
574 | 42.3k | 0U, // G_CTLZ |
575 | 42.3k | 0U, // G_CTLZ_ZERO_UNDEF |
576 | 42.3k | 0U, // G_CTPOP |
577 | 42.3k | 0U, // G_BSWAP |
578 | 42.3k | 0U, // G_BITREVERSE |
579 | 42.3k | 0U, // G_FCEIL |
580 | 42.3k | 0U, // G_FCOS |
581 | 42.3k | 0U, // G_FSIN |
582 | 42.3k | 0U, // G_FSQRT |
583 | 42.3k | 0U, // G_FFLOOR |
584 | 42.3k | 0U, // G_FRINT |
585 | 42.3k | 0U, // G_FNEARBYINT |
586 | 42.3k | 0U, // G_ADDRSPACE_CAST |
587 | 42.3k | 0U, // G_BLOCK_ADDR |
588 | 42.3k | 0U, // G_JUMP_TABLE |
589 | 42.3k | 0U, // G_DYN_STACKALLOC |
590 | 42.3k | 0U, // G_STACKSAVE |
591 | 42.3k | 0U, // G_STACKRESTORE |
592 | 42.3k | 0U, // G_STRICT_FADD |
593 | 42.3k | 0U, // G_STRICT_FSUB |
594 | 42.3k | 0U, // G_STRICT_FMUL |
595 | 42.3k | 0U, // G_STRICT_FDIV |
596 | 42.3k | 0U, // G_STRICT_FREM |
597 | 42.3k | 0U, // G_STRICT_FMA |
598 | 42.3k | 0U, // G_STRICT_FSQRT |
599 | 42.3k | 0U, // G_STRICT_FLDEXP |
600 | 42.3k | 0U, // G_READ_REGISTER |
601 | 42.3k | 0U, // G_WRITE_REGISTER |
602 | 42.3k | 0U, // G_MEMCPY |
603 | 42.3k | 0U, // G_MEMCPY_INLINE |
604 | 42.3k | 0U, // G_MEMMOVE |
605 | 42.3k | 0U, // G_MEMSET |
606 | 42.3k | 0U, // G_BZERO |
607 | 42.3k | 0U, // G_VECREDUCE_SEQ_FADD |
608 | 42.3k | 0U, // G_VECREDUCE_SEQ_FMUL |
609 | 42.3k | 0U, // G_VECREDUCE_FADD |
610 | 42.3k | 0U, // G_VECREDUCE_FMUL |
611 | 42.3k | 0U, // G_VECREDUCE_FMAX |
612 | 42.3k | 0U, // G_VECREDUCE_FMIN |
613 | 42.3k | 0U, // G_VECREDUCE_FMAXIMUM |
614 | 42.3k | 0U, // G_VECREDUCE_FMINIMUM |
615 | 42.3k | 0U, // G_VECREDUCE_ADD |
616 | 42.3k | 0U, // G_VECREDUCE_MUL |
617 | 42.3k | 0U, // G_VECREDUCE_AND |
618 | 42.3k | 0U, // G_VECREDUCE_OR |
619 | 42.3k | 0U, // G_VECREDUCE_XOR |
620 | 42.3k | 0U, // G_VECREDUCE_SMAX |
621 | 42.3k | 0U, // G_VECREDUCE_SMIN |
622 | 42.3k | 0U, // G_VECREDUCE_UMAX |
623 | 42.3k | 0U, // G_VECREDUCE_UMIN |
624 | 42.3k | 0U, // G_SBFX |
625 | 42.3k | 0U, // G_UBFX |
626 | 42.3k | 4609U, // ADJCALLSTACKDOWN |
627 | 42.3k | 70164U, // ADJCALLSTACKUP |
628 | 42.3k | 8206U, // GETPCX |
629 | 42.3k | 1946U, // SELECT_CC_DFP_FCC |
630 | 42.3k | 2057U, // SELECT_CC_DFP_ICC |
631 | 42.3k | 2168U, // SELECT_CC_DFP_XCC |
632 | 42.3k | 2002U, // SELECT_CC_FP_FCC |
633 | 42.3k | 2113U, // SELECT_CC_FP_ICC |
634 | 42.3k | 2224U, // SELECT_CC_FP_XCC |
635 | 42.3k | 2029U, // SELECT_CC_Int_FCC |
636 | 42.3k | 2140U, // SELECT_CC_Int_ICC |
637 | 42.3k | 2251U, // SELECT_CC_Int_XCC |
638 | 42.3k | 1974U, // SELECT_CC_QFP_FCC |
639 | 42.3k | 2085U, // SELECT_CC_QFP_ICC |
640 | 42.3k | 2196U, // SELECT_CC_QFP_XCC |
641 | 42.3k | 2111195U, // SET |
642 | 42.3k | 20985729U, // SETX |
643 | 42.3k | 20984449U, // ADDCCri |
644 | 42.3k | 20984449U, // ADDCCrr |
645 | 42.3k | 20985664U, // ADDCri |
646 | 42.3k | 20985664U, // ADDCrr |
647 | 42.3k | 20984541U, // ADDEri |
648 | 42.3k | 20984541U, // ADDErr |
649 | 42.3k | 20984555U, // ADDXC |
650 | 42.3k | 20984439U, // ADDXCCC |
651 | 42.3k | 20984577U, // ADDri |
652 | 42.3k | 20984577U, // ADDrr |
653 | 42.3k | 20985176U, // ALIGNADDR |
654 | 42.3k | 20984933U, // ALIGNADDRL |
655 | 42.3k | 20984456U, // ANDCCri |
656 | 42.3k | 20984456U, // ANDCCrr |
657 | 42.3k | 20984479U, // ANDNCCri |
658 | 42.3k | 20984479U, // ANDNCCrr |
659 | 42.3k | 20984988U, // ANDNri |
660 | 42.3k | 20984988U, // ANDNrr |
661 | 42.3k | 20984662U, // ANDri |
662 | 42.3k | 20984662U, // ANDrr |
663 | 42.3k | 20984289U, // ARRAY16 |
664 | 42.3k | 20984042U, // ARRAY32 |
665 | 42.3k | 20984313U, // ARRAY8 |
666 | 42.3k | 2247425U, // BCOND |
667 | 42.3k | 2312961U, // BCONDA |
668 | 42.3k | 87258U, // BINDri |
669 | 42.3k | 87258U, // BINDrr |
670 | 42.3k | 20984871U, // BMASK |
671 | 42.3k | 21121795U, // BPFCC |
672 | 42.3k | 21187331U, // BPFCCA |
673 | 42.3k | 281347U, // BPFCCANT |
674 | 42.3k | 346883U, // BPFCCNT |
675 | 42.3k | 2509569U, // BPICC |
676 | 42.3k | 477953U, // BPICCA |
677 | 42.3k | 543489U, // BPICCANT |
678 | 42.3k | 609025U, // BPICCNT |
679 | 42.3k | 21121882U, // BPR |
680 | 42.3k | 21187418U, // BPRA |
681 | 42.3k | 281434U, // BPRANT |
682 | 42.3k | 346970U, // BPRNT |
683 | 42.3k | 2771713U, // BPXCC |
684 | 42.3k | 740097U, // BPXCCA |
685 | 42.3k | 805633U, // BPXCCANT |
686 | 42.3k | 871169U, // BPXCCNT |
687 | 42.3k | 20984782U, // BSHUFFLE |
688 | 42.3k | 70740U, // CALL |
689 | 42.3k | 87124U, // CALLri |
690 | 42.3k | 87124U, // CALLrr |
691 | 42.3k | 21904013U, // CASAri |
692 | 42.3k | 7289485U, // CASArr |
693 | 42.3k | 21904035U, // CASXAri |
694 | 42.3k | 7289507U, // CASXArr |
695 | 42.3k | 2247424U, // CBCOND |
696 | 42.3k | 2312960U, // CBCONDA |
697 | 42.3k | 69980U, // CMASK16 |
698 | 42.3k | 69812U, // CMASK32 |
699 | 42.3k | 70129U, // CMASK8 |
700 | 42.3k | 2850U, // DONE |
701 | 42.3k | 20984119U, // EDGE16 |
702 | 42.3k | 20984887U, // EDGE16L |
703 | 42.3k | 20985004U, // EDGE16LN |
704 | 42.3k | 20984971U, // EDGE16N |
705 | 42.3k | 20983951U, // EDGE32 |
706 | 42.3k | 20984878U, // EDGE32L |
707 | 42.3k | 20984994U, // EDGE32LN |
708 | 42.3k | 20984962U, // EDGE32N |
709 | 42.3k | 20984298U, // EDGE8 |
710 | 42.3k | 20984896U, // EDGE8L |
711 | 42.3k | 20985014U, // EDGE8LN |
712 | 42.3k | 20984980U, // EDGE8N |
713 | 42.3k | 2110371U, // FABSD |
714 | 42.3k | 2110766U, // FABSQ |
715 | 42.3k | 2111166U, // FABSS |
716 | 42.3k | 20984582U, // FADDD |
717 | 42.3k | 20985062U, // FADDQ |
718 | 42.3k | 20985362U, // FADDS |
719 | 42.3k | 20984386U, // FALIGNADATA |
720 | 42.3k | 20984661U, // FAND |
721 | 42.3k | 20983899U, // FANDNOT1 |
722 | 42.3k | 20985241U, // FANDNOT1S |
723 | 42.3k | 20984058U, // FANDNOT2 |
724 | 42.3k | 20985298U, // FANDNOT2S |
725 | 42.3k | 20985394U, // FANDS |
726 | 42.3k | 2247427U, // FBCOND |
727 | 42.3k | 2312963U, // FBCONDA |
728 | 42.3k | 1067779U, // FBCONDA_V9 |
729 | 42.3k | 3230467U, // FBCOND_V9 |
730 | 42.3k | 20984181U, // FCHKSM16 |
731 | 42.3k | 5008U, // FCMPD |
732 | 42.3k | 4097U, // FCMPD_V9 |
733 | 42.3k | 20984200U, // FCMPEQ16 |
734 | 42.3k | 20984013U, // FCMPEQ32 |
735 | 42.3k | 20984219U, // FCMPGT16 |
736 | 42.3k | 20984032U, // FCMPGT32 |
737 | 42.3k | 20984127U, // FCMPLE16 |
738 | 42.3k | 20983959U, // FCMPLE32 |
739 | 42.3k | 20984137U, // FCMPNE16 |
740 | 42.3k | 20983969U, // FCMPNE32 |
741 | 42.3k | 5415U, // FCMPQ |
742 | 42.3k | 4111U, // FCMPQ_V9 |
743 | 42.3k | 5779U, // FCMPS |
744 | 42.3k | 4125U, // FCMPS_V9 |
745 | 42.3k | 20984759U, // FDIVD |
746 | 42.3k | 20985154U, // FDIVQ |
747 | 42.3k | 20985549U, // FDIVS |
748 | 42.3k | 20985084U, // FDMULQ |
749 | 42.3k | 2110482U, // FDTOI |
750 | 42.3k | 2110731U, // FDTOQ |
751 | 42.3k | 2111086U, // FDTOS |
752 | 42.3k | 2111331U, // FDTOX |
753 | 42.3k | 2110306U, // FEXPAND |
754 | 42.3k | 20984589U, // FHADDD |
755 | 42.3k | 20985369U, // FHADDS |
756 | 42.3k | 20984569U, // FHSUBD |
757 | 42.3k | 20985354U, // FHSUBS |
758 | 42.3k | 2110315U, // FITOD |
759 | 42.3k | 2110738U, // FITOQ |
760 | 42.3k | 2111093U, // FITOS |
761 | 42.3k | 150999959U, // FLCMPD |
762 | 42.3k | 151000730U, // FLCMPS |
763 | 42.3k | 2445U, // FLUSH |
764 | 42.3k | 2933U, // FLUSHW |
765 | 42.3k | 87021U, // FLUSHri |
766 | 42.3k | 87021U, // FLUSHrr |
767 | 42.3k | 20984191U, // FMEAN16 |
768 | 42.3k | 2110398U, // FMOVD |
769 | 42.3k | 17918748U, // FMOVD_FCC |
770 | 42.3k | 17197852U, // FMOVD_ICC |
771 | 42.3k | 17459996U, // FMOVD_XCC |
772 | 42.3k | 2110793U, // FMOVQ |
773 | 42.3k | 17918798U, // FMOVQ_FCC |
774 | 42.3k | 17197902U, // FMOVQ_ICC |
775 | 42.3k | 17460046U, // FMOVQ_XCC |
776 | 42.3k | 31509U, // FMOVRD |
777 | 42.3k | 31559U, // FMOVRQ |
778 | 42.3k | 31586U, // FMOVRS |
779 | 42.3k | 2111188U, // FMOVS |
780 | 42.3k | 17918825U, // FMOVS_FCC |
781 | 42.3k | 17197929U, // FMOVS_ICC |
782 | 42.3k | 17460073U, // FMOVS_XCC |
783 | 42.3k | 20984277U, // FMUL8SUX16 |
784 | 42.3k | 20984252U, // FMUL8ULX16 |
785 | 42.3k | 20984229U, // FMUL8X16 |
786 | 42.3k | 20984904U, // FMUL8X16AL |
787 | 42.3k | 20985588U, // FMUL8X16AU |
788 | 42.3k | 20984629U, // FMULD |
789 | 42.3k | 20984264U, // FMULD8SUX16 |
790 | 42.3k | 20984239U, // FMULD8ULX16 |
791 | 42.3k | 20985092U, // FMULQ |
792 | 42.3k | 20985431U, // FMULS |
793 | 42.3k | 20984606U, // FNADDD |
794 | 42.3k | 20985386U, // FNADDS |
795 | 42.3k | 20984667U, // FNAND |
796 | 42.3k | 20985401U, // FNANDS |
797 | 42.3k | 2110254U, // FNEGD |
798 | 42.3k | 2110709U, // FNEGQ |
799 | 42.3k | 2111056U, // FNEGS |
800 | 42.3k | 20984597U, // FNHADDD |
801 | 42.3k | 20985377U, // FNHADDS |
802 | 42.3k | 20984636U, // FNMULD |
803 | 42.3k | 20985438U, // FNMULS |
804 | 42.3k | 20985197U, // FNOR |
805 | 42.3k | 20985512U, // FNORS |
806 | 42.3k | 2109541U, // FNOT1 |
807 | 42.3k | 2110884U, // FNOT1S |
808 | 42.3k | 2109700U, // FNOT2 |
809 | 42.3k | 2110941U, // FNOT2S |
810 | 42.3k | 20984652U, // FNSMULD |
811 | 42.3k | 70616U, // FONE |
812 | 42.3k | 71233U, // FONES |
813 | 42.3k | 20985192U, // FOR |
814 | 42.3k | 20983916U, // FORNOT1 |
815 | 42.3k | 20985260U, // FORNOT1S |
816 | 42.3k | 20984075U, // FORNOT2 |
817 | 42.3k | 20985317U, // FORNOT2S |
818 | 42.3k | 20985506U, // FORS |
819 | 42.3k | 2109779U, // FPACK16 |
820 | 42.3k | 20983979U, // FPACK32 |
821 | 42.3k | 2111302U, // FPACKFIX |
822 | 42.3k | 20984110U, // FPADD16 |
823 | 42.3k | 20985337U, // FPADD16S |
824 | 42.3k | 20983942U, // FPADD32 |
825 | 42.3k | 20985280U, // FPADD32S |
826 | 42.3k | 20984084U, // FPADD64 |
827 | 42.3k | 20984773U, // FPMERGE |
828 | 42.3k | 20984101U, // FPSUB16 |
829 | 42.3k | 20985327U, // FPSUB16S |
830 | 42.3k | 20983933U, // FPSUB32 |
831 | 42.3k | 20985270U, // FPSUB32S |
832 | 42.3k | 2110322U, // FQTOD |
833 | 42.3k | 2110489U, // FQTOI |
834 | 42.3k | 2111100U, // FQTOS |
835 | 42.3k | 2111347U, // FQTOX |
836 | 42.3k | 20984210U, // FSLAS16 |
837 | 42.3k | 20984023U, // FSLAS32 |
838 | 42.3k | 20984165U, // FSLL16 |
839 | 42.3k | 20983997U, // FSLL32 |
840 | 42.3k | 20984644U, // FSMULD |
841 | 42.3k | 2110378U, // FSQRTD |
842 | 42.3k | 2110773U, // FSQRTQ |
843 | 42.3k | 2111173U, // FSQRTS |
844 | 42.3k | 20984093U, // FSRA16 |
845 | 42.3k | 20983925U, // FSRA32 |
846 | 42.3k | 2109524U, // FSRC1 |
847 | 42.3k | 2110865U, // FSRC1S |
848 | 42.3k | 2109683U, // FSRC2 |
849 | 42.3k | 2110922U, // FSRC2S |
850 | 42.3k | 20984173U, // FSRL16 |
851 | 42.3k | 20984005U, // FSRL32 |
852 | 42.3k | 2110329U, // FSTOD |
853 | 42.3k | 2110496U, // FSTOI |
854 | 42.3k | 2110745U, // FSTOQ |
855 | 42.3k | 2111354U, // FSTOX |
856 | 42.3k | 20984562U, // FSUBD |
857 | 42.3k | 20985055U, // FSUBQ |
858 | 42.3k | 20985347U, // FSUBS |
859 | 42.3k | 20985203U, // FXNOR |
860 | 42.3k | 20985519U, // FXNORS |
861 | 42.3k | 20985210U, // FXOR |
862 | 42.3k | 20985527U, // FXORS |
863 | 42.3k | 2110336U, // FXTOD |
864 | 42.3k | 2110752U, // FXTOQ |
865 | 42.3k | 2111116U, // FXTOS |
866 | 42.3k | 70860U, // FZERO |
867 | 42.3k | 71270U, // FZEROS |
868 | 42.3k | 288525050U, // GDOP_LDXrr |
869 | 42.3k | 288525000U, // GDOP_LDrr |
870 | 42.3k | 2131039U, // JMPLri |
871 | 42.3k | 2131039U, // JMPLrr |
872 | 42.3k | 3050088U, // LDAri |
873 | 42.3k | 26184296U, // LDArr |
874 | 42.3k | 1268424U, // LDCSRri |
875 | 42.3k | 1268424U, // LDCSRrr |
876 | 42.3k | 3312328U, // LDCri |
877 | 42.3k | 3312328U, // LDCrr |
878 | 42.3k | 3050081U, // LDDAri |
879 | 42.3k | 26184289U, // LDDArr |
880 | 42.3k | 3312322U, // LDDCri |
881 | 42.3k | 3312322U, // LDDCrr |
882 | 42.3k | 3050081U, // LDDFAri |
883 | 42.3k | 26184289U, // LDDFArr |
884 | 42.3k | 3312322U, // LDDFri |
885 | 42.3k | 3312322U, // LDDFrr |
886 | 42.3k | 3312322U, // LDDri |
887 | 42.3k | 3312322U, // LDDrr |
888 | 42.3k | 3050088U, // LDFAri |
889 | 42.3k | 26184296U, // LDFArr |
890 | 42.3k | 1333960U, // LDFSRri |
891 | 42.3k | 1333960U, // LDFSRrr |
892 | 42.3k | 3312328U, // LDFri |
893 | 42.3k | 3312328U, // LDFrr |
894 | 42.3k | 3050118U, // LDQFAri |
895 | 42.3k | 26184326U, // LDQFArr |
896 | 42.3k | 3312365U, // LDQFri |
897 | 42.3k | 3312365U, // LDQFrr |
898 | 42.3k | 3050055U, // LDSBAri |
899 | 42.3k | 26184263U, // LDSBArr |
900 | 42.3k | 3312299U, // LDSBri |
901 | 42.3k | 3312299U, // LDSBrr |
902 | 42.3k | 3050094U, // LDSHAri |
903 | 42.3k | 26184302U, // LDSHArr |
904 | 42.3k | 3312344U, // LDSHri |
905 | 42.3k | 3312344U, // LDSHrr |
906 | 42.3k | 3050071U, // LDSTUBAri |
907 | 42.3k | 26184279U, // LDSTUBArr |
908 | 42.3k | 3312313U, // LDSTUBri |
909 | 42.3k | 3312313U, // LDSTUBrr |
910 | 42.3k | 3050132U, // LDSWAri |
911 | 42.3k | 26184340U, // LDSWArr |
912 | 42.3k | 3312371U, // LDSWri |
913 | 42.3k | 3312371U, // LDSWrr |
914 | 42.3k | 3050063U, // LDUBAri |
915 | 42.3k | 26184271U, // LDUBArr |
916 | 42.3k | 3312306U, // LDUBri |
917 | 42.3k | 3312306U, // LDUBrr |
918 | 42.3k | 3050102U, // LDUHAri |
919 | 42.3k | 26184310U, // LDUHArr |
920 | 42.3k | 3312351U, // LDUHri |
921 | 42.3k | 3312351U, // LDUHrr |
922 | 42.3k | 3050140U, // LDXAri |
923 | 42.3k | 26184348U, // LDXArr |
924 | 42.3k | 1334010U, // LDXFSRri |
925 | 42.3k | 1334010U, // LDXFSRrr |
926 | 42.3k | 3312378U, // LDXri |
927 | 42.3k | 3312378U, // LDXrr |
928 | 42.3k | 3312328U, // LDri |
929 | 42.3k | 3312328U, // LDrr |
930 | 42.3k | 2111200U, // LZCNT |
931 | 42.3k | 38224U, // MEMBARi |
932 | 42.3k | 2111338U, // MOVDTOX |
933 | 42.3k | 17918833U, // MOVFCCri |
934 | 42.3k | 17918833U, // MOVFCCrr |
935 | 42.3k | 17197937U, // MOVICCri |
936 | 42.3k | 17197937U, // MOVICCrr |
937 | 42.3k | 31581U, // MOVRri |
938 | 42.3k | 31581U, // MOVRrr |
939 | 42.3k | 2111264U, // MOVSTOSW |
940 | 42.3k | 2111274U, // MOVSTOUW |
941 | 42.3k | 2111107U, // MOVWTOS |
942 | 42.3k | 17460081U, // MOVXCCri |
943 | 42.3k | 17460081U, // MOVXCCrr |
944 | 42.3k | 2110343U, // MOVXTOD |
945 | 42.3k | 20984509U, // MULSCCri |
946 | 42.3k | 20984509U, // MULSCCrr |
947 | 42.3k | 20985693U, // MULXri |
948 | 42.3k | 20985693U, // MULXrr |
949 | 42.3k | 2883U, // NOP |
950 | 42.3k | 20984496U, // ORCCri |
951 | 42.3k | 20984496U, // ORCCrr |
952 | 42.3k | 20984487U, // ORNCCri |
953 | 42.3k | 20984487U, // ORNCCrr |
954 | 42.3k | 20985023U, // ORNri |
955 | 42.3k | 20985023U, // ORNrr |
956 | 42.3k | 20985193U, // ORri |
957 | 42.3k | 20985193U, // ORrr |
958 | 42.3k | 20985575U, // PDIST |
959 | 42.3k | 20985028U, // PDISTN |
960 | 42.3k | 2110181U, // POPCrr |
961 | 42.3k | 5397197U, // PREFETCHi |
962 | 42.3k | 5397197U, // PREFETCHr |
963 | 42.3k | 33559948U, // PWRPSRri |
964 | 42.3k | 33559948U, // PWRPSRrr |
965 | 42.3k | 2110367U, // RDASR |
966 | 42.3k | 69685U, // RDFQ |
967 | 42.3k | 2110848U, // RDPR |
968 | 42.3k | 69706U, // RDPSR |
969 | 42.3k | 69696U, // RDTBR |
970 | 42.3k | 69675U, // RDWIM |
971 | 42.3k | 2822U, // RESTORED |
972 | 42.3k | 20984798U, // RESTOREri |
973 | 42.3k | 20984798U, // RESTORErr |
974 | 42.3k | 71911U, // RET |
975 | 42.3k | 71920U, // RETL |
976 | 42.3k | 2940U, // RETRY |
977 | 42.3k | 87790U, // RETTri |
978 | 42.3k | 87790U, // RETTrr |
979 | 42.3k | 2831U, // SAVED |
980 | 42.3k | 20984807U, // SAVEri |
981 | 42.3k | 20984807U, // SAVErr |
982 | 42.3k | 20984517U, // SDIVCCri |
983 | 42.3k | 20984517U, // SDIVCCrr |
984 | 42.3k | 20985740U, // SDIVXri |
985 | 42.3k | 20985740U, // SDIVXrr |
986 | 42.3k | 20985600U, // SDIVri |
987 | 42.3k | 20985600U, // SDIVrr |
988 | 42.3k | 2110457U, // SETHIi |
989 | 42.3k | 2874U, // SHUTDOWN |
990 | 42.3k | 2869U, // SIAM |
991 | 42.3k | 71011U, // SIR |
992 | 42.3k | 20985680U, // SLLXri |
993 | 42.3k | 20985680U, // SLLXrr |
994 | 42.3k | 20984922U, // SLLri |
995 | 42.3k | 20984922U, // SLLrr |
996 | 42.3k | 20984419U, // SMACri |
997 | 42.3k | 20984419U, // SMACrr |
998 | 42.3k | 20984463U, // SMULCCri |
999 | 42.3k | 20984463U, // SMULCCrr |
1000 | 42.3k | 20984950U, // SMULri |
1001 | 42.3k | 20984950U, // SMULrr |
1002 | 42.3k | 20985652U, // SRAXri |
1003 | 42.3k | 20985652U, // SRAXrr |
1004 | 42.3k | 20984381U, // SRAri |
1005 | 42.3k | 20984381U, // SRArr |
1006 | 42.3k | 20985686U, // SRLXri |
1007 | 42.3k | 20985686U, // SRLXrr |
1008 | 42.3k | 20984945U, // SRLri |
1009 | 42.3k | 20984945U, // SRLrr |
1010 | 42.3k | 1417806U, // STAri |
1011 | 42.3k | 9413198U, // STArr |
1012 | 42.3k | 2900U, // STBAR |
1013 | 42.3k | 1417765U, // STBAri |
1014 | 42.3k | 9413157U, // STBArr |
1015 | 42.3k | 1483353U, // STBri |
1016 | 42.3k | 1483353U, // STBrr |
1017 | 42.3k | 1464869U, // STCSRri |
1018 | 42.3k | 1464869U, // STCSRrr |
1019 | 42.3k | 1484522U, // STCri |
1020 | 42.3k | 1484522U, // STCrr |
1021 | 42.3k | 1417771U, // STDAri |
1022 | 42.3k | 9413163U, // STDArr |
1023 | 42.3k | 1464847U, // STDCQri |
1024 | 42.3k | 1464847U, // STDCQrr |
1025 | 42.3k | 1483698U, // STDCri |
1026 | 42.3k | 1483698U, // STDCrr |
1027 | 42.3k | 1417771U, // STDFAri |
1028 | 42.3k | 9413163U, // STDFArr |
1029 | 42.3k | 1464858U, // STDFQri |
1030 | 42.3k | 1464858U, // STDFQrr |
1031 | 42.3k | 1483698U, // STDFri |
1032 | 42.3k | 1483698U, // STDFrr |
1033 | 42.3k | 1483698U, // STDri |
1034 | 42.3k | 1483698U, // STDrr |
1035 | 42.3k | 1417806U, // STFAri |
1036 | 42.3k | 9413198U, // STFArr |
1037 | 42.3k | 1464880U, // STFSRri |
1038 | 42.3k | 1464880U, // STFSRrr |
1039 | 42.3k | 1484522U, // STFri |
1040 | 42.3k | 1484522U, // STFrr |
1041 | 42.3k | 1417777U, // STHAri |
1042 | 42.3k | 9413169U, // STHArr |
1043 | 42.3k | 1483764U, // STHri |
1044 | 42.3k | 1483764U, // STHrr |
1045 | 42.3k | 1417783U, // STQFAri |
1046 | 42.3k | 9413175U, // STQFArr |
1047 | 42.3k | 1484093U, // STQFri |
1048 | 42.3k | 1484093U, // STQFrr |
1049 | 42.3k | 1417811U, // STXAri |
1050 | 42.3k | 9413203U, // STXArr |
1051 | 42.3k | 1464891U, // STXFSRri |
1052 | 42.3k | 1464891U, // STXFSRrr |
1053 | 42.3k | 1484679U, // STXri |
1054 | 42.3k | 1484679U, // STXrr |
1055 | 42.3k | 1484522U, // STri |
1056 | 42.3k | 1484522U, // STrr |
1057 | 42.3k | 20984432U, // SUBCCri |
1058 | 42.3k | 20984432U, // SUBCCrr |
1059 | 42.3k | 20985658U, // SUBCri |
1060 | 42.3k | 20985658U, // SUBCrr |
1061 | 42.3k | 20984533U, // SUBEri |
1062 | 42.3k | 20984533U, // SUBErr |
1063 | 42.3k | 20984414U, // SUBri |
1064 | 42.3k | 20984414U, // SUBrr |
1065 | 42.3k | 3050110U, // SWAPAri |
1066 | 42.3k | 26184318U, // SWAPArr |
1067 | 42.3k | 3312358U, // SWAPri |
1068 | 42.3k | 3312358U, // SWAPrr |
1069 | 42.3k | 2455U, // TA1 |
1070 | 42.3k | 2460U, // TA3 |
1071 | 42.3k | 2465U, // TA5 |
1072 | 42.3k | 20985622U, // TADDCCTVri |
1073 | 42.3k | 20985622U, // TADDCCTVrr |
1074 | 42.3k | 20984448U, // TADDCCri |
1075 | 42.3k | 20984448U, // TADDCCrr |
1076 | 42.3k | 70740U, // TAIL_CALL |
1077 | 42.3k | 87258U, // TAIL_CALLri |
1078 | 42.3k | 52869999U, // TICCri |
1079 | 42.3k | 52869999U, // TICCrr |
1080 | 42.3k | 557855489U, // TLS_ADDrr |
1081 | 42.3k | 5204U, // TLS_CALL |
1082 | 42.3k | 288525050U, // TLS_LDXrr |
1083 | 42.3k | 288525000U, // TLS_LDrr |
1084 | 42.3k | 52607855U, // TRAPri |
1085 | 42.3k | 52607855U, // TRAPrr |
1086 | 42.3k | 20985612U, // TSUBCCTVri |
1087 | 42.3k | 20985612U, // TSUBCCTVrr |
1088 | 42.3k | 20984431U, // TSUBCCri |
1089 | 42.3k | 20984431U, // TSUBCCrr |
1090 | 42.3k | 53132143U, // TXCCri |
1091 | 42.3k | 53132143U, // TXCCrr |
1092 | 42.3k | 20984525U, // UDIVCCri |
1093 | 42.3k | 20984525U, // UDIVCCrr |
1094 | 42.3k | 20985747U, // UDIVXri |
1095 | 42.3k | 20985747U, // UDIVXrr |
1096 | 42.3k | 20985606U, // UDIVri |
1097 | 42.3k | 20985606U, // UDIVrr |
1098 | 42.3k | 20984425U, // UMACri |
1099 | 42.3k | 20984425U, // UMACrr |
1100 | 42.3k | 20984471U, // UMULCCri |
1101 | 42.3k | 20984471U, // UMULCCrr |
1102 | 42.3k | 20984832U, // UMULXHI |
1103 | 42.3k | 20984956U, // UMULri |
1104 | 42.3k | 20984956U, // UMULrr |
1105 | 42.3k | 70867U, // UNIMP |
1106 | 42.3k | 150999952U, // V9FCMPD |
1107 | 42.3k | 150999846U, // V9FCMPED |
1108 | 42.3k | 151000301U, // V9FCMPEQ |
1109 | 42.3k | 151000648U, // V9FCMPES |
1110 | 42.3k | 151000359U, // V9FCMPQ |
1111 | 42.3k | 151000723U, // V9FCMPS |
1112 | 42.3k | 31516U, // V9FMOVD_FCC |
1113 | 42.3k | 31566U, // V9FMOVQ_FCC |
1114 | 42.3k | 31593U, // V9FMOVS_FCC |
1115 | 42.3k | 31601U, // V9MOVFCCri |
1116 | 42.3k | 31601U, // V9MOVFCCrr |
1117 | 42.3k | 20985229U, // WRASRri |
1118 | 42.3k | 20985229U, // WRASRrr |
1119 | 42.3k | 20985222U, // WRPRri |
1120 | 42.3k | 20985222U, // WRPRrr |
1121 | 42.3k | 33559949U, // WRPSRri |
1122 | 42.3k | 33559949U, // WRPSRrr |
1123 | 42.3k | 67114381U, // WRTBRri |
1124 | 42.3k | 67114381U, // WRTBRrr |
1125 | 42.3k | 83891597U, // WRWIMri |
1126 | 42.3k | 83891597U, // WRWIMrr |
1127 | 42.3k | 20985692U, // XMULX |
1128 | 42.3k | 20984841U, // XMULXHI |
1129 | 42.3k | 20984494U, // XNORCCri |
1130 | 42.3k | 20984494U, // XNORCCrr |
1131 | 42.3k | 20985204U, // XNORri |
1132 | 42.3k | 20985204U, // XNORrr |
1133 | 42.3k | 20984502U, // XORCCri |
1134 | 42.3k | 20984502U, // XORCCrr |
1135 | 42.3k | 20985211U, // XORri |
1136 | 42.3k | 20985211U, // XORrr |
1137 | 42.3k | }; |
1138 | | |
1139 | | // Emit the opcode for the instruction. |
1140 | 42.3k | uint32_t Bits = 0; |
1141 | 42.3k | Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0; |
1142 | 42.3k | MnemonicBitsInfo MBI = { |
1143 | 42.3k | #ifndef CAPSTONE_DIET |
1144 | 42.3k | AsmStrs+(Bits & 4095)-1, |
1145 | | #else |
1146 | | NULL, |
1147 | | #endif // CAPSTONE_DIET |
1148 | 42.3k | Bits |
1149 | 42.3k | }; |
1150 | 42.3k | return MBI; |
1151 | 42.3k | } |
1152 | | |
1153 | | /// printInstruction - This method is automatically generated by tablegen |
1154 | | /// from the instruction set description. |
1155 | 42.3k | static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) { |
1156 | 42.3k | SStream_concat0(O, ""); |
1157 | 42.3k | MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O); |
1158 | | |
1159 | 42.3k | SStream_concat0(O, MnemonicInfo.first); |
1160 | | |
1161 | 42.3k | uint32_t Bits = MnemonicInfo.second; |
1162 | 42.3k | CS_ASSERT_RET(Bits != 0 && "Cannot print this instruction."); |
1163 | | |
1164 | | // Fragment 0 encoded into 4 bits for 12 unique commands. |
1165 | 42.3k | switch ((Bits >> 12) & 15) { |
1166 | 0 | default: CS_ASSERT_RET(0 && "Invalid command number."); |
1167 | 235 | case 0: |
1168 | | // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... |
1169 | 235 | return; |
1170 | 0 | break; |
1171 | 13.4k | case 1: |
1172 | | // ADJCALLSTACKDOWN, ADJCALLSTACKUP, CALL, CMASK16, CMASK32, CMASK8, FCMP... |
1173 | 13.4k | printOperand(MI, 0, O); |
1174 | 13.4k | break; |
1175 | 0 | case 2: |
1176 | | // GETPCX |
1177 | 0 | printGetPCX(MI, 0, O); |
1178 | 0 | return; |
1179 | 0 | break; |
1180 | 8.29k | case 3: |
1181 | | // SET, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, AD... |
1182 | 8.29k | printOperand(MI, 1, O); |
1183 | 8.29k | break; |
1184 | 6.19k | case 4: |
1185 | | // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA... |
1186 | 6.19k | printCCOperand(MI, 1, O); |
1187 | 6.19k | break; |
1188 | 1.61k | case 5: |
1189 | | // BINDri, BINDrr, CALLri, CALLrr, FLUSHri, FLUSHrr, LDCSRri, LDCSRrr, LD... |
1190 | 1.61k | printMemOperand(MI, 0, O); |
1191 | 1.61k | break; |
1192 | 621 | case 6: |
1193 | | // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV... |
1194 | 621 | printCCOperand(MI, 3, O); |
1195 | 621 | break; |
1196 | 386 | case 7: |
1197 | | // FMOVRD, FMOVRQ, FMOVRS, MOVRri, MOVRrr, V9FMOVD_FCC, V9FMOVQ_FCC, V9FM... |
1198 | 386 | printCCOperand(MI, 4, O); |
1199 | 386 | SStream_concat1(O, ' '); |
1200 | 386 | printOperand(MI, 1, O); |
1201 | 386 | SStream_concat0(O, ", "); |
1202 | 386 | printOperand(MI, 2, O); |
1203 | 386 | SStream_concat0(O, ", "); |
1204 | 386 | printOperand(MI, 0, O); |
1205 | 386 | return; |
1206 | 0 | break; |
1207 | 5.69k | case 8: |
1208 | | // GDOP_LDXrr, GDOP_LDrr, JMPLri, JMPLrr, LDAri, LDArr, LDCri, LDCrr, LDD... |
1209 | 5.69k | printMemOperand(MI, 1, O); |
1210 | 5.69k | break; |
1211 | 2.05k | case 9: |
1212 | | // MEMBARi |
1213 | 2.05k | printMembarTag(MI, 0, O); |
1214 | 2.05k | return; |
1215 | 0 | break; |
1216 | 3.85k | case 10: |
1217 | | // STAri, STArr, STBAri, STBArr, STBri, STBrr, STCri, STCrr, STDAri, STDA... |
1218 | 3.85k | printOperand(MI, 2, O); |
1219 | 3.85k | SStream_concat0(O, ", ["); |
1220 | 3.85k | printMemOperand(MI, 0, O); |
1221 | 3.85k | break; |
1222 | 0 | case 11: |
1223 | | // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr |
1224 | 0 | printCCOperand(MI, 2, O); |
1225 | 0 | break; |
1226 | 42.3k | } |
1227 | | |
1228 | | |
1229 | | // Fragment 1 encoded into 5 bits for 23 unique commands. |
1230 | 39.6k | switch ((Bits >> 16) & 31) { |
1231 | 0 | default: CS_ASSERT_RET(0 && "Invalid command number."); |
1232 | 10.5k | case 0: |
1233 | | // ADJCALLSTACKDOWN, SET, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri,... |
1234 | 10.5k | SStream_concat0(O, ", "); |
1235 | 10.5k | break; |
1236 | 10.8k | case 1: |
1237 | | // ADJCALLSTACKUP, BINDri, BINDrr, CALL, CALLri, CALLrr, CMASK16, CMASK32... |
1238 | 10.8k | return; |
1239 | 0 | break; |
1240 | 1.92k | case 2: |
1241 | | // BCOND, BPFCC, BPR, CBCOND, FBCOND, TRAPri, TRAPrr |
1242 | 1.92k | SStream_concat1(O, ' '); |
1243 | 1.92k | break; |
1244 | 1.34k | case 3: |
1245 | | // BCONDA, BPFCCA, BPRA, CBCONDA, FBCONDA |
1246 | 1.34k | SStream_concat0(O, ",a "); |
1247 | 1.34k | break; |
1248 | 92 | case 4: |
1249 | | // BPFCCANT, BPRANT |
1250 | 92 | SStream_concat0(O, ",a,pn "); |
1251 | 92 | printOperand(MI, 2, O); |
1252 | 92 | SStream_concat0(O, ", "); |
1253 | 92 | printOperand(MI, 0, O); |
1254 | 92 | return; |
1255 | 0 | break; |
1256 | 476 | case 5: |
1257 | | // BPFCCNT, BPRNT |
1258 | 476 | SStream_concat0(O, ",pn "); |
1259 | 476 | printOperand(MI, 2, O); |
1260 | 476 | SStream_concat0(O, ", "); |
1261 | 476 | printOperand(MI, 0, O); |
1262 | 476 | return; |
1263 | 0 | break; |
1264 | 746 | case 6: |
1265 | | // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI... |
1266 | 746 | SStream_concat0(O, " %icc, "); |
1267 | 746 | break; |
1268 | 135 | case 7: |
1269 | | // BPICCA |
1270 | 135 | SStream_concat0(O, ",a %icc, "); |
1271 | 135 | printOperand(MI, 0, O); |
1272 | 135 | return; |
1273 | 0 | break; |
1274 | 0 | case 8: |
1275 | | // BPICCANT |
1276 | 0 | SStream_concat0(O, ",a,pn %icc, "); |
1277 | 0 | printOperand(MI, 0, O); |
1278 | 0 | return; |
1279 | 0 | break; |
1280 | 0 | case 9: |
1281 | | // BPICCNT |
1282 | 0 | SStream_concat0(O, ",pn %icc, "); |
1283 | 0 | printOperand(MI, 0, O); |
1284 | 0 | return; |
1285 | 0 | break; |
1286 | 141 | case 10: |
1287 | | // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX... |
1288 | 141 | SStream_concat0(O, " %xcc, "); |
1289 | 141 | break; |
1290 | 548 | case 11: |
1291 | | // BPXCCA |
1292 | 548 | SStream_concat0(O, ",a %xcc, "); |
1293 | 548 | printOperand(MI, 0, O); |
1294 | 548 | return; |
1295 | 0 | break; |
1296 | 0 | case 12: |
1297 | | // BPXCCANT |
1298 | 0 | SStream_concat0(O, ",a,pn %xcc, "); |
1299 | 0 | printOperand(MI, 0, O); |
1300 | 0 | return; |
1301 | 0 | break; |
1302 | 0 | case 13: |
1303 | | // BPXCCNT |
1304 | 0 | SStream_concat0(O, ",pn %xcc, "); |
1305 | 0 | printOperand(MI, 0, O); |
1306 | 0 | return; |
1307 | 0 | break; |
1308 | 1.64k | case 14: |
1309 | | // CASAri, CASXAri, LDAri, LDDAri, LDDFAri, LDFAri, LDQFAri, LDSBAri, LDS... |
1310 | 1.64k | SStream_concat0(O, "] %asi, "); |
1311 | 1.64k | break; |
1312 | 3.51k | case 15: |
1313 | | // CASArr, CASXArr, LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDS... |
1314 | 3.51k | SStream_concat0(O, "] "); |
1315 | 3.51k | break; |
1316 | 351 | case 16: |
1317 | | // FBCONDA_V9 |
1318 | 351 | SStream_concat0(O, ",a %fcc0, "); |
1319 | 351 | printOperand(MI, 0, O); |
1320 | 351 | return; |
1321 | 0 | break; |
1322 | 1.05k | case 17: |
1323 | | // FBCOND_V9, FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr |
1324 | 1.05k | SStream_concat0(O, " %fcc0, "); |
1325 | 1.05k | break; |
1326 | 2.76k | case 18: |
1327 | | // GDOP_LDXrr, GDOP_LDrr, LDCri, LDCrr, LDDCri, LDDCrr, LDDFri, LDDFrr, L... |
1328 | 2.76k | SStream_concat0(O, "], "); |
1329 | 2.76k | break; |
1330 | 282 | case 19: |
1331 | | // LDCSRri, LDCSRrr |
1332 | 282 | SStream_concat0(O, "], %csr"); |
1333 | 282 | return; |
1334 | 0 | break; |
1335 | 182 | case 20: |
1336 | | // LDFSRri, LDFSRrr, LDXFSRri, LDXFSRrr |
1337 | 182 | SStream_concat0(O, "], %fsr"); |
1338 | 182 | return; |
1339 | 0 | break; |
1340 | 1.06k | case 21: |
1341 | | // STAri, STBAri, STDAri, STDFAri, STFAri, STHAri, STQFAri, STXAri |
1342 | 1.06k | SStream_concat0(O, "] %asi"); |
1343 | 1.06k | return; |
1344 | 0 | break; |
1345 | 2.02k | case 22: |
1346 | | // STBri, STBrr, STCSRri, STCSRrr, STCri, STCrr, STDCQri, STDCQrr, STDCri... |
1347 | 2.02k | SStream_concat1(O, ']'); |
1348 | 2.02k | return; |
1349 | 0 | break; |
1350 | 39.6k | } |
1351 | | |
1352 | | |
1353 | | // Fragment 2 encoded into 3 bits for 5 unique commands. |
1354 | 23.7k | switch ((Bits >> 21) & 7) { |
1355 | 0 | default: CS_ASSERT_RET(0 && "Invalid command number."); |
1356 | 3.23k | case 0: |
1357 | | // ADJCALLSTACKDOWN, FCMPD, FCMPD_V9, FCMPQ, FCMPQ_V9, FCMPS, FCMPS_V9, F... |
1358 | 3.23k | printOperand(MI, 1, O); |
1359 | 3.23k | break; |
1360 | 10.6k | case 1: |
1361 | | // SET, BCOND, BCONDA, BPICC, BPXCC, CBCOND, CBCONDA, FABSD, FABSQ, FABSS... |
1362 | 10.6k | printOperand(MI, 0, O); |
1363 | 10.6k | break; |
1364 | 6.28k | case 2: |
1365 | | // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC... |
1366 | 6.28k | printOperand(MI, 2, O); |
1367 | 6.28k | break; |
1368 | 355 | case 3: |
1369 | | // CASArr, CASXArr |
1370 | 355 | printASITag(MI, 4, O); |
1371 | 355 | SStream_concat0(O, ", "); |
1372 | 355 | printOperand(MI, 2, O); |
1373 | 355 | SStream_concat0(O, ", "); |
1374 | 355 | printOperand(MI, 0, O); |
1375 | 355 | return; |
1376 | 0 | break; |
1377 | 3.15k | case 4: |
1378 | | // LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDSHArr, LDSTUBArr, ... |
1379 | 3.15k | printASITag(MI, 3, O); |
1380 | 3.15k | break; |
1381 | 23.7k | } |
1382 | | |
1383 | | |
1384 | | // Fragment 3 encoded into 3 bits for 6 unique commands. |
1385 | 23.3k | switch ((Bits >> 24) & 7) { |
1386 | 0 | default: CS_ASSERT_RET(0 && "Invalid command number."); |
1387 | 12.5k | case 0: |
1388 | | // ADJCALLSTACKDOWN, SET, BCOND, BCONDA, BPICC, BPXCC, CBCOND, CBCONDA, F... |
1389 | 12.5k | return; |
1390 | 0 | break; |
1391 | 9.74k | case 1: |
1392 | | // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC... |
1393 | 9.74k | SStream_concat0(O, ", "); |
1394 | 9.74k | break; |
1395 | 491 | case 2: |
1396 | | // PWRPSRri, PWRPSRrr, WRPSRri, WRPSRrr |
1397 | 491 | SStream_concat0(O, ", %psr"); |
1398 | 491 | return; |
1399 | 0 | break; |
1400 | 0 | case 3: |
1401 | | // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr |
1402 | 0 | SStream_concat0(O, " + "); |
1403 | 0 | printOperand(MI, 1, O); |
1404 | 0 | return; |
1405 | 0 | break; |
1406 | 420 | case 4: |
1407 | | // WRTBRri, WRTBRrr |
1408 | 420 | SStream_concat0(O, ", %tbr"); |
1409 | 420 | return; |
1410 | 0 | break; |
1411 | 144 | case 5: |
1412 | | // WRWIMri, WRWIMrr |
1413 | 144 | SStream_concat0(O, ", %wim"); |
1414 | 144 | return; |
1415 | 0 | break; |
1416 | 23.3k | } |
1417 | | |
1418 | | |
1419 | | // Fragment 4 encoded into 2 bits for 3 unique commands. |
1420 | 9.74k | switch ((Bits >> 27) & 3) { |
1421 | 0 | default: CS_ASSERT_RET(0 && "Invalid command number."); |
1422 | 8.18k | case 0: |
1423 | | // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC... |
1424 | 8.18k | printOperand(MI, 0, O); |
1425 | 8.18k | break; |
1426 | 1.56k | case 1: |
1427 | | // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP... |
1428 | 1.56k | printOperand(MI, 2, O); |
1429 | 1.56k | return; |
1430 | 0 | break; |
1431 | 0 | case 2: |
1432 | | // GDOP_LDXrr, GDOP_LDrr, TLS_LDXrr, TLS_LDrr |
1433 | 0 | printOperand(MI, 3, O); |
1434 | 0 | return; |
1435 | 0 | break; |
1436 | 9.74k | } |
1437 | | |
1438 | | |
1439 | | // Fragment 5 encoded into 1 bits for 2 unique commands. |
1440 | 8.18k | if ((Bits >> 29) & 1) { |
1441 | | // TLS_ADDrr |
1442 | 0 | SStream_concat0(O, ", "); |
1443 | 0 | printOperand(MI, 3, O); |
1444 | 0 | return; |
1445 | 8.18k | } else { |
1446 | | // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC... |
1447 | 8.18k | return; |
1448 | 8.18k | } |
1449 | | |
1450 | 8.18k | } |
1451 | | |
1452 | | |
1453 | | /// getRegisterName - This method is automatically generated by tblgen |
1454 | | /// from the register set description. This returns the assembler name |
1455 | | /// for the specified register. |
1456 | | static const char * |
1457 | 135k | getRegisterName(unsigned RegNo, unsigned AltIdx) { |
1458 | 135k | #ifndef CAPSTONE_DIET |
1459 | 135k | CS_ASSERT_RET_VAL(RegNo && RegNo < 238 && "Invalid register number!", NULL); |
1460 | | |
1461 | 135k | static const char AsmStrsNoRegAltName[] = { |
1462 | 135k | /* 0 */ "c10\0" |
1463 | 135k | /* 4 */ "f10\0" |
1464 | 135k | /* 8 */ "asr10\0" |
1465 | 135k | /* 14 */ "c20\0" |
1466 | 135k | /* 18 */ "f20\0" |
1467 | 135k | /* 22 */ "asr20\0" |
1468 | 135k | /* 28 */ "c30\0" |
1469 | 135k | /* 32 */ "f30\0" |
1470 | 135k | /* 36 */ "asr30\0" |
1471 | 135k | /* 42 */ "f40\0" |
1472 | 135k | /* 46 */ "f50\0" |
1473 | 135k | /* 50 */ "f60\0" |
1474 | 135k | /* 54 */ "fcc0\0" |
1475 | 135k | /* 59 */ "f0\0" |
1476 | 135k | /* 62 */ "g0\0" |
1477 | 135k | /* 65 */ "i0\0" |
1478 | 135k | /* 68 */ "l0\0" |
1479 | 135k | /* 71 */ "o0\0" |
1480 | 135k | /* 74 */ "c11\0" |
1481 | 135k | /* 78 */ "f11\0" |
1482 | 135k | /* 82 */ "asr11\0" |
1483 | 135k | /* 88 */ "c21\0" |
1484 | 135k | /* 92 */ "f21\0" |
1485 | 135k | /* 96 */ "asr21\0" |
1486 | 135k | /* 102 */ "c31\0" |
1487 | 135k | /* 106 */ "f31\0" |
1488 | 135k | /* 110 */ "asr31\0" |
1489 | 135k | /* 116 */ "fcc1\0" |
1490 | 135k | /* 121 */ "f1\0" |
1491 | 135k | /* 124 */ "g1\0" |
1492 | 135k | /* 127 */ "i1\0" |
1493 | 135k | /* 130 */ "l1\0" |
1494 | 135k | /* 133 */ "o1\0" |
1495 | 135k | /* 136 */ "asr1\0" |
1496 | 135k | /* 141 */ "c12\0" |
1497 | 135k | /* 145 */ "f12\0" |
1498 | 135k | /* 149 */ "asr12\0" |
1499 | 135k | /* 155 */ "c22\0" |
1500 | 135k | /* 159 */ "f22\0" |
1501 | 135k | /* 163 */ "asr22\0" |
1502 | 135k | /* 169 */ "f32\0" |
1503 | 135k | /* 173 */ "f42\0" |
1504 | 135k | /* 177 */ "f52\0" |
1505 | 135k | /* 181 */ "f62\0" |
1506 | 135k | /* 185 */ "fcc2\0" |
1507 | 135k | /* 190 */ "f2\0" |
1508 | 135k | /* 193 */ "g2\0" |
1509 | 135k | /* 196 */ "i2\0" |
1510 | 135k | /* 199 */ "l2\0" |
1511 | 135k | /* 202 */ "o2\0" |
1512 | 135k | /* 205 */ "asr2\0" |
1513 | 135k | /* 210 */ "c13\0" |
1514 | 135k | /* 214 */ "f13\0" |
1515 | 135k | /* 218 */ "asr13\0" |
1516 | 135k | /* 224 */ "c23\0" |
1517 | 135k | /* 228 */ "f23\0" |
1518 | 135k | /* 232 */ "asr23\0" |
1519 | 135k | /* 238 */ "fcc3\0" |
1520 | 135k | /* 243 */ "f3\0" |
1521 | 135k | /* 246 */ "g3\0" |
1522 | 135k | /* 249 */ "i3\0" |
1523 | 135k | /* 252 */ "l3\0" |
1524 | 135k | /* 255 */ "o3\0" |
1525 | 135k | /* 258 */ "asr3\0" |
1526 | 135k | /* 263 */ "c14\0" |
1527 | 135k | /* 267 */ "f14\0" |
1528 | 135k | /* 271 */ "asr14\0" |
1529 | 135k | /* 277 */ "c24\0" |
1530 | 135k | /* 281 */ "f24\0" |
1531 | 135k | /* 285 */ "asr24\0" |
1532 | 135k | /* 291 */ "f34\0" |
1533 | 135k | /* 295 */ "f44\0" |
1534 | 135k | /* 299 */ "f54\0" |
1535 | 135k | /* 303 */ "c4\0" |
1536 | 135k | /* 306 */ "f4\0" |
1537 | 135k | /* 309 */ "g4\0" |
1538 | 135k | /* 312 */ "i4\0" |
1539 | 135k | /* 315 */ "l4\0" |
1540 | 135k | /* 318 */ "o4\0" |
1541 | 135k | /* 321 */ "asr4\0" |
1542 | 135k | /* 326 */ "c15\0" |
1543 | 135k | /* 330 */ "f15\0" |
1544 | 135k | /* 334 */ "asr15\0" |
1545 | 135k | /* 340 */ "c25\0" |
1546 | 135k | /* 344 */ "f25\0" |
1547 | 135k | /* 348 */ "asr25\0" |
1548 | 135k | /* 354 */ "c5\0" |
1549 | 135k | /* 357 */ "f5\0" |
1550 | 135k | /* 360 */ "g5\0" |
1551 | 135k | /* 363 */ "i5\0" |
1552 | 135k | /* 366 */ "l5\0" |
1553 | 135k | /* 369 */ "o5\0" |
1554 | 135k | /* 372 */ "asr5\0" |
1555 | 135k | /* 377 */ "c16\0" |
1556 | 135k | /* 381 */ "f16\0" |
1557 | 135k | /* 385 */ "asr16\0" |
1558 | 135k | /* 391 */ "c26\0" |
1559 | 135k | /* 395 */ "f26\0" |
1560 | 135k | /* 399 */ "asr26\0" |
1561 | 135k | /* 405 */ "f36\0" |
1562 | 135k | /* 409 */ "f46\0" |
1563 | 135k | /* 413 */ "f56\0" |
1564 | 135k | /* 417 */ "c6\0" |
1565 | 135k | /* 420 */ "f6\0" |
1566 | 135k | /* 423 */ "g6\0" |
1567 | 135k | /* 426 */ "i6\0" |
1568 | 135k | /* 429 */ "l6\0" |
1569 | 135k | /* 432 */ "o6\0" |
1570 | 135k | /* 435 */ "asr6\0" |
1571 | 135k | /* 440 */ "c17\0" |
1572 | 135k | /* 444 */ "f17\0" |
1573 | 135k | /* 448 */ "asr17\0" |
1574 | 135k | /* 454 */ "c27\0" |
1575 | 135k | /* 458 */ "f27\0" |
1576 | 135k | /* 462 */ "asr27\0" |
1577 | 135k | /* 468 */ "c7\0" |
1578 | 135k | /* 471 */ "f7\0" |
1579 | 135k | /* 474 */ "g7\0" |
1580 | 135k | /* 477 */ "i7\0" |
1581 | 135k | /* 480 */ "l7\0" |
1582 | 135k | /* 483 */ "o7\0" |
1583 | 135k | /* 486 */ "asr7\0" |
1584 | 135k | /* 491 */ "c18\0" |
1585 | 135k | /* 495 */ "f18\0" |
1586 | 135k | /* 499 */ "asr18\0" |
1587 | 135k | /* 505 */ "c28\0" |
1588 | 135k | /* 509 */ "f28\0" |
1589 | 135k | /* 513 */ "asr28\0" |
1590 | 135k | /* 519 */ "f38\0" |
1591 | 135k | /* 523 */ "f48\0" |
1592 | 135k | /* 527 */ "f58\0" |
1593 | 135k | /* 531 */ "c8\0" |
1594 | 135k | /* 534 */ "f8\0" |
1595 | 135k | /* 537 */ "asr8\0" |
1596 | 135k | /* 542 */ "c19\0" |
1597 | 135k | /* 546 */ "f19\0" |
1598 | 135k | /* 550 */ "asr19\0" |
1599 | 135k | /* 556 */ "c29\0" |
1600 | 135k | /* 560 */ "f29\0" |
1601 | 135k | /* 564 */ "asr29\0" |
1602 | 135k | /* 570 */ "c9\0" |
1603 | 135k | /* 573 */ "f9\0" |
1604 | 135k | /* 576 */ "asr9\0" |
1605 | 135k | /* 581 */ "tba\0" |
1606 | 135k | /* 585 */ "icc\0" |
1607 | 135k | /* 589 */ "tnpc\0" |
1608 | 135k | /* 594 */ "tpc\0" |
1609 | 135k | /* 598 */ "canrestore\0" |
1610 | 135k | /* 609 */ "pstate\0" |
1611 | 135k | /* 616 */ "tstate\0" |
1612 | 135k | /* 623 */ "wstate\0" |
1613 | 135k | /* 630 */ "cansave\0" |
1614 | 135k | /* 638 */ "tick\0" |
1615 | 135k | /* 643 */ "gl\0" |
1616 | 135k | /* 646 */ "pil\0" |
1617 | 135k | /* 650 */ "tl\0" |
1618 | 135k | /* 653 */ "wim\0" |
1619 | 135k | /* 657 */ "cleanwin\0" |
1620 | 135k | /* 666 */ "otherwin\0" |
1621 | 135k | /* 675 */ "fp\0" |
1622 | 135k | /* 678 */ "sp\0" |
1623 | 135k | /* 681 */ "cwp\0" |
1624 | 135k | /* 685 */ "cq\0" |
1625 | 135k | /* 688 */ "fq\0" |
1626 | 135k | /* 691 */ "tbr\0" |
1627 | 135k | /* 695 */ "ver\0" |
1628 | 135k | /* 699 */ "csr\0" |
1629 | 135k | /* 703 */ "fsr\0" |
1630 | 135k | /* 707 */ "psr\0" |
1631 | 135k | /* 711 */ "tt\0" |
1632 | 135k | /* 714 */ "y\0" |
1633 | 135k | }; |
1634 | 135k | static const uint16_t RegAsmOffsetNoRegAltName[] = { |
1635 | 135k | 598, 630, 657, 685, 699, 681, 688, 703, 643, 585, 666, 646, 707, 609, |
1636 | 135k | 581, 691, 638, 650, 589, 594, 616, 711, 695, 653, 623, 714, 136, 205, |
1637 | 135k | 258, 321, 372, 435, 486, 537, 576, 8, 82, 149, 218, 271, 334, 385, |
1638 | 135k | 448, 499, 550, 22, 96, 163, 232, 285, 348, 399, 462, 513, 564, 36, |
1639 | 135k | 110, 56, 118, 187, 240, 303, 354, 417, 468, 531, 570, 0, 74, 141, |
1640 | 135k | 210, 263, 326, 377, 440, 491, 542, 14, 88, 155, 224, 277, 340, 391, |
1641 | 135k | 454, 505, 556, 28, 102, 59, 190, 306, 420, 534, 4, 145, 267, 381, |
1642 | 135k | 495, 18, 159, 281, 395, 509, 32, 169, 291, 405, 519, 42, 173, 295, |
1643 | 135k | 409, 523, 46, 177, 299, 413, 527, 50, 181, 59, 121, 190, 243, 306, |
1644 | 135k | 357, 420, 471, 534, 573, 4, 78, 145, 214, 267, 330, 381, 444, 495, |
1645 | 135k | 546, 18, 92, 159, 228, 281, 344, 395, 458, 509, 560, 32, 106, 54, |
1646 | 135k | 116, 185, 238, 62, 124, 193, 246, 309, 360, 423, 474, 65, 127, 196, |
1647 | 135k | 249, 312, 363, 675, 477, 68, 130, 199, 252, 315, 366, 429, 480, 71, |
1648 | 135k | 133, 202, 255, 318, 369, 678, 483, 59, 306, 534, 145, 381, 18, 281, |
1649 | 135k | 509, 169, 405, 42, 295, 523, 177, 413, 50, 56, 187, 303, 417, 531, |
1650 | 135k | 0, 141, 263, 377, 491, 14, 155, 277, 391, 505, 28, 62, 193, 309, |
1651 | 135k | 423, 65, 196, 312, 426, 68, 199, 315, 429, 71, 202, 318, 432, |
1652 | 135k | }; |
1653 | | |
1654 | 135k | static const char AsmStrsRegNamesStateReg[] = { |
1655 | 135k | /* 0 */ "pc\0" |
1656 | 135k | /* 3 */ "asi\0" |
1657 | 135k | /* 7 */ "tick\0" |
1658 | 135k | /* 12 */ "ccr\0" |
1659 | 135k | /* 16 */ "fprs\0" |
1660 | 135k | }; |
1661 | 135k | static const uint8_t RegAsmOffsetRegNamesStateReg[] = { |
1662 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1663 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 12, |
1664 | 135k | 3, 7, 0, 16, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1665 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1666 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1667 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1668 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1669 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1670 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1671 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1672 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1673 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1674 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1675 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1676 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1677 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1678 | 135k | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, |
1679 | 135k | }; |
1680 | | |
1681 | 135k | switch(AltIdx) { |
1682 | 0 | default: CS_ASSERT_RET_VAL(0 && "Invalid register alt name index!", NULL); |
1683 | 70.6k | case Sparc_NoRegAltName: |
1684 | 70.6k | CS_ASSERT_RET_VAL(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && |
1685 | 70.6k | "Invalid alt name index for register!", NULL); |
1686 | 70.6k | return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; |
1687 | 65.3k | case Sparc_RegNamesStateReg: |
1688 | 65.3k | if (!*(AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1])) |
1689 | 62.4k | return getRegisterName(RegNo, Sparc_NoRegAltName); |
1690 | 2.89k | return AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1]; |
1691 | 135k | } |
1692 | | #else |
1693 | | return NULL; |
1694 | | #endif // CAPSTONE_DIET |
1695 | 135k | } |
1696 | | #ifdef PRINT_ALIAS_INSTR |
1697 | | #undef PRINT_ALIAS_INSTR |
1698 | | |
1699 | 47.5k | static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) { |
1700 | 47.5k | #ifndef CAPSTONE_DIET |
1701 | 47.5k | static const PatternsForOpcode OpToPatterns[] = { |
1702 | 47.5k | {Sparc_BCOND, 0, 16 }, |
1703 | 47.5k | {Sparc_BCONDA, 16, 16 }, |
1704 | 47.5k | {Sparc_BPFCCANT, 32, 16 }, |
1705 | 47.5k | {Sparc_BPFCCNT, 48, 16 }, |
1706 | 47.5k | {Sparc_BPICCANT, 64, 16 }, |
1707 | 47.5k | {Sparc_BPICCNT, 80, 16 }, |
1708 | 47.5k | {Sparc_BPRANT, 96, 6 }, |
1709 | 47.5k | {Sparc_BPRNT, 102, 6 }, |
1710 | 47.5k | {Sparc_BPXCCANT, 108, 16 }, |
1711 | 47.5k | {Sparc_BPXCCNT, 124, 16 }, |
1712 | 47.5k | {Sparc_CASArr, 140, 2 }, |
1713 | 47.5k | {Sparc_CASXArr, 142, 2 }, |
1714 | 47.5k | {Sparc_FMOVD_ICC, 144, 16 }, |
1715 | 47.5k | {Sparc_FMOVD_XCC, 160, 16 }, |
1716 | 47.5k | {Sparc_FMOVQ_ICC, 176, 16 }, |
1717 | 47.5k | {Sparc_FMOVQ_XCC, 192, 16 }, |
1718 | 47.5k | {Sparc_FMOVRD, 208, 6 }, |
1719 | 47.5k | {Sparc_FMOVRQ, 214, 6 }, |
1720 | 47.5k | {Sparc_FMOVRS, 220, 6 }, |
1721 | 47.5k | {Sparc_FMOVS_ICC, 226, 16 }, |
1722 | 47.5k | {Sparc_FMOVS_XCC, 242, 16 }, |
1723 | 47.5k | {Sparc_MOVICCri, 258, 16 }, |
1724 | 47.5k | {Sparc_MOVICCrr, 274, 16 }, |
1725 | 47.5k | {Sparc_MOVRri, 290, 6 }, |
1726 | 47.5k | {Sparc_MOVRrr, 296, 6 }, |
1727 | 47.5k | {Sparc_MOVXCCri, 302, 16 }, |
1728 | 47.5k | {Sparc_MOVXCCrr, 318, 16 }, |
1729 | 47.5k | {Sparc_ORCCrr, 334, 1 }, |
1730 | 47.5k | {Sparc_ORri, 335, 1 }, |
1731 | 47.5k | {Sparc_ORrr, 336, 1 }, |
1732 | 47.5k | {Sparc_RESTORErr, 337, 1 }, |
1733 | 47.5k | {Sparc_RET, 338, 1 }, |
1734 | 47.5k | {Sparc_RETL, 339, 1 }, |
1735 | 47.5k | {Sparc_SAVErr, 340, 1 }, |
1736 | 47.5k | {Sparc_SUBCCri, 341, 1 }, |
1737 | 47.5k | {Sparc_SUBCCrr, 342, 1 }, |
1738 | 47.5k | {Sparc_TICCri, 343, 32 }, |
1739 | 47.5k | {Sparc_TICCrr, 375, 32 }, |
1740 | 47.5k | {Sparc_TRAPri, 407, 32 }, |
1741 | 47.5k | {Sparc_TRAPrr, 439, 32 }, |
1742 | 47.5k | {Sparc_TXCCri, 471, 32 }, |
1743 | 47.5k | {Sparc_TXCCrr, 503, 32 }, |
1744 | 47.5k | {Sparc_V9FCMPD, 535, 1 }, |
1745 | 47.5k | {Sparc_V9FCMPED, 536, 1 }, |
1746 | 47.5k | {Sparc_V9FCMPEQ, 537, 1 }, |
1747 | 47.5k | {Sparc_V9FCMPES, 538, 1 }, |
1748 | 47.5k | {Sparc_V9FCMPQ, 539, 1 }, |
1749 | 47.5k | {Sparc_V9FCMPS, 540, 1 }, |
1750 | 47.5k | {Sparc_V9FMOVD_FCC, 541, 16 }, |
1751 | 47.5k | {Sparc_V9FMOVQ_FCC, 557, 16 }, |
1752 | 47.5k | {Sparc_V9FMOVS_FCC, 573, 16 }, |
1753 | 47.5k | {Sparc_V9MOVFCCri, 589, 16 }, |
1754 | 47.5k | {Sparc_V9MOVFCCrr, 605, 16 }, |
1755 | 47.5k | {0}, }; |
1756 | | |
1757 | 47.5k | static const AliasPattern Patterns[] = { |
1758 | | // Sparc_BCOND - 0 |
1759 | 47.5k | {0, 0, 2, 2 }, |
1760 | 47.5k | {6, 2, 2, 2 }, |
1761 | 47.5k | {12, 4, 2, 2 }, |
1762 | 47.5k | {19, 6, 2, 2 }, |
1763 | 47.5k | {25, 8, 2, 2 }, |
1764 | 47.5k | {31, 10, 2, 2 }, |
1765 | 47.5k | {38, 12, 2, 2 }, |
1766 | 47.5k | {45, 14, 2, 2 }, |
1767 | 47.5k | {51, 16, 2, 2 }, |
1768 | 47.5k | {58, 18, 2, 2 }, |
1769 | 47.5k | {66, 20, 2, 2 }, |
1770 | 47.5k | {73, 22, 2, 2 }, |
1771 | 47.5k | {80, 24, 2, 2 }, |
1772 | 47.5k | {88, 26, 2, 2 }, |
1773 | 47.5k | {96, 28, 2, 2 }, |
1774 | 47.5k | {103, 30, 2, 2 }, |
1775 | | // Sparc_BCONDA - 16 |
1776 | 47.5k | {110, 32, 2, 2 }, |
1777 | 47.5k | {118, 34, 2, 2 }, |
1778 | 47.5k | {126, 36, 2, 2 }, |
1779 | 47.5k | {135, 38, 2, 2 }, |
1780 | 47.5k | {143, 40, 2, 2 }, |
1781 | 47.5k | {151, 42, 2, 2 }, |
1782 | 47.5k | {160, 44, 2, 2 }, |
1783 | 47.5k | {169, 46, 2, 2 }, |
1784 | 47.5k | {177, 48, 2, 2 }, |
1785 | 47.5k | {186, 50, 2, 2 }, |
1786 | 47.5k | {196, 52, 2, 2 }, |
1787 | 47.5k | {205, 54, 2, 2 }, |
1788 | 47.5k | {214, 56, 2, 2 }, |
1789 | 47.5k | {224, 58, 2, 2 }, |
1790 | 47.5k | {234, 60, 2, 2 }, |
1791 | 47.5k | {243, 62, 2, 2 }, |
1792 | | // Sparc_BPFCCANT - 32 |
1793 | 47.5k | {252, 64, 3, 4 }, |
1794 | 47.5k | {268, 68, 3, 4 }, |
1795 | 47.5k | {284, 72, 3, 4 }, |
1796 | 47.5k | {300, 76, 3, 4 }, |
1797 | 47.5k | {316, 80, 3, 4 }, |
1798 | 47.5k | {333, 84, 3, 4 }, |
1799 | 47.5k | {349, 88, 3, 4 }, |
1800 | 47.5k | {366, 92, 3, 4 }, |
1801 | 47.5k | {383, 96, 3, 4 }, |
1802 | 47.5k | {400, 100, 3, 4 }, |
1803 | 47.5k | {416, 104, 3, 4 }, |
1804 | 47.5k | {433, 108, 3, 4 }, |
1805 | 47.5k | {450, 112, 3, 4 }, |
1806 | 47.5k | {468, 116, 3, 4 }, |
1807 | 47.5k | {485, 120, 3, 4 }, |
1808 | 47.5k | {503, 124, 3, 4 }, |
1809 | | // Sparc_BPFCCNT - 48 |
1810 | 47.5k | {519, 128, 3, 4 }, |
1811 | 47.5k | {533, 132, 3, 4 }, |
1812 | 47.5k | {547, 136, 3, 4 }, |
1813 | 47.5k | {561, 140, 3, 4 }, |
1814 | 47.5k | {575, 144, 3, 4 }, |
1815 | 47.5k | {590, 148, 3, 4 }, |
1816 | 47.5k | {604, 152, 3, 4 }, |
1817 | 47.5k | {619, 156, 3, 4 }, |
1818 | 47.5k | {634, 160, 3, 4 }, |
1819 | 47.5k | {649, 164, 3, 4 }, |
1820 | 47.5k | {663, 168, 3, 4 }, |
1821 | 47.5k | {678, 172, 3, 4 }, |
1822 | 47.5k | {693, 176, 3, 4 }, |
1823 | 47.5k | {709, 180, 3, 4 }, |
1824 | 47.5k | {724, 184, 3, 4 }, |
1825 | 47.5k | {740, 188, 3, 4 }, |
1826 | | // Sparc_BPICCANT - 64 |
1827 | 47.5k | {754, 192, 2, 3 }, |
1828 | 47.5k | {771, 195, 2, 3 }, |
1829 | 47.5k | {788, 198, 2, 3 }, |
1830 | 47.5k | {806, 201, 2, 3 }, |
1831 | 47.5k | {823, 204, 2, 3 }, |
1832 | 47.5k | {840, 207, 2, 3 }, |
1833 | 47.5k | {858, 210, 2, 3 }, |
1834 | 47.5k | {876, 213, 2, 3 }, |
1835 | 47.5k | {893, 216, 2, 3 }, |
1836 | 47.5k | {911, 219, 2, 3 }, |
1837 | 47.5k | {930, 222, 2, 3 }, |
1838 | 47.5k | {948, 225, 2, 3 }, |
1839 | 47.5k | {966, 228, 2, 3 }, |
1840 | 47.5k | {985, 231, 2, 3 }, |
1841 | 47.5k | {1004, 234, 2, 3 }, |
1842 | 47.5k | {1022, 237, 2, 3 }, |
1843 | | // Sparc_BPICCNT - 80 |
1844 | 47.5k | {1040, 240, 2, 3 }, |
1845 | 47.5k | {1055, 243, 2, 3 }, |
1846 | 47.5k | {1070, 246, 2, 3 }, |
1847 | 47.5k | {1086, 249, 2, 3 }, |
1848 | 47.5k | {1101, 252, 2, 3 }, |
1849 | 47.5k | {1116, 255, 2, 3 }, |
1850 | 47.5k | {1132, 258, 2, 3 }, |
1851 | 47.5k | {1148, 261, 2, 3 }, |
1852 | 47.5k | {1163, 264, 2, 3 }, |
1853 | 47.5k | {1179, 267, 2, 3 }, |
1854 | 47.5k | {1196, 270, 2, 3 }, |
1855 | 47.5k | {1212, 273, 2, 3 }, |
1856 | 47.5k | {1228, 276, 2, 3 }, |
1857 | 47.5k | {1245, 279, 2, 3 }, |
1858 | 47.5k | {1262, 282, 2, 3 }, |
1859 | 47.5k | {1278, 285, 2, 3 }, |
1860 | | // Sparc_BPRANT - 96 |
1861 | 47.5k | {1294, 288, 3, 4 }, |
1862 | 47.5k | {1310, 292, 3, 4 }, |
1863 | 47.5k | {1328, 296, 3, 4 }, |
1864 | 47.5k | {1345, 300, 3, 4 }, |
1865 | 47.5k | {1362, 304, 3, 4 }, |
1866 | 47.5k | {1379, 308, 3, 4 }, |
1867 | | // Sparc_BPRNT - 102 |
1868 | 47.5k | {1397, 312, 3, 4 }, |
1869 | 47.5k | {1411, 316, 3, 4 }, |
1870 | 47.5k | {1427, 320, 3, 4 }, |
1871 | 47.5k | {1442, 324, 3, 4 }, |
1872 | 47.5k | {1457, 328, 3, 4 }, |
1873 | 47.5k | {1472, 332, 3, 4 }, |
1874 | | // Sparc_BPXCCANT - 108 |
1875 | 47.5k | {1488, 336, 2, 3 }, |
1876 | 47.5k | {1505, 339, 2, 3 }, |
1877 | 47.5k | {1522, 342, 2, 3 }, |
1878 | 47.5k | {1540, 345, 2, 3 }, |
1879 | 47.5k | {1557, 348, 2, 3 }, |
1880 | 47.5k | {1574, 351, 2, 3 }, |
1881 | 47.5k | {1592, 354, 2, 3 }, |
1882 | 47.5k | {1610, 357, 2, 3 }, |
1883 | 47.5k | {1627, 360, 2, 3 }, |
1884 | 47.5k | {1645, 363, 2, 3 }, |
1885 | 47.5k | {1664, 366, 2, 3 }, |
1886 | 47.5k | {1682, 369, 2, 3 }, |
1887 | 47.5k | {1700, 372, 2, 3 }, |
1888 | 47.5k | {1719, 375, 2, 3 }, |
1889 | 47.5k | {1738, 378, 2, 3 }, |
1890 | 47.5k | {1756, 381, 2, 3 }, |
1891 | | // Sparc_BPXCCNT - 124 |
1892 | 47.5k | {1774, 384, 2, 3 }, |
1893 | 47.5k | {1789, 387, 2, 3 }, |
1894 | 47.5k | {1804, 390, 2, 3 }, |
1895 | 47.5k | {1820, 393, 2, 3 }, |
1896 | 47.5k | {1835, 396, 2, 3 }, |
1897 | 47.5k | {1850, 399, 2, 3 }, |
1898 | 47.5k | {1866, 402, 2, 3 }, |
1899 | 47.5k | {1882, 405, 2, 3 }, |
1900 | 47.5k | {1897, 408, 2, 3 }, |
1901 | 47.5k | {1913, 411, 2, 3 }, |
1902 | 47.5k | {1930, 414, 2, 3 }, |
1903 | 47.5k | {1946, 417, 2, 3 }, |
1904 | 47.5k | {1962, 420, 2, 3 }, |
1905 | 47.5k | {1979, 423, 2, 3 }, |
1906 | 47.5k | {1996, 426, 2, 3 }, |
1907 | 47.5k | {2012, 429, 2, 3 }, |
1908 | | // Sparc_CASArr - 140 |
1909 | 47.5k | {2028, 432, 5, 6 }, |
1910 | 47.5k | {2045, 438, 5, 6 }, |
1911 | | // Sparc_CASXArr - 142 |
1912 | 47.5k | {2063, 444, 5, 6 }, |
1913 | 47.5k | {2081, 450, 5, 6 }, |
1914 | | // Sparc_FMOVD_ICC - 144 |
1915 | 47.5k | {2100, 456, 4, 5 }, |
1916 | 47.5k | {2120, 461, 4, 5 }, |
1917 | 47.5k | {2140, 466, 4, 5 }, |
1918 | 47.5k | {2161, 471, 4, 5 }, |
1919 | 47.5k | {2181, 476, 4, 5 }, |
1920 | 47.5k | {2201, 481, 4, 5 }, |
1921 | 47.5k | {2222, 486, 4, 5 }, |
1922 | 47.5k | {2243, 491, 4, 5 }, |
1923 | 47.5k | {2263, 496, 4, 5 }, |
1924 | 47.5k | {2284, 501, 4, 5 }, |
1925 | 47.5k | {2306, 506, 4, 5 }, |
1926 | 47.5k | {2327, 511, 4, 5 }, |
1927 | 47.5k | {2348, 516, 4, 5 }, |
1928 | 47.5k | {2370, 521, 4, 5 }, |
1929 | 47.5k | {2392, 526, 4, 5 }, |
1930 | 47.5k | {2413, 531, 4, 5 }, |
1931 | | // Sparc_FMOVD_XCC - 160 |
1932 | 47.5k | {2434, 536, 4, 5 }, |
1933 | 47.5k | {2454, 541, 4, 5 }, |
1934 | 47.5k | {2474, 546, 4, 5 }, |
1935 | 47.5k | {2495, 551, 4, 5 }, |
1936 | 47.5k | {2515, 556, 4, 5 }, |
1937 | 47.5k | {2535, 561, 4, 5 }, |
1938 | 47.5k | {2556, 566, 4, 5 }, |
1939 | 47.5k | {2577, 571, 4, 5 }, |
1940 | 47.5k | {2597, 576, 4, 5 }, |
1941 | 47.5k | {2618, 581, 4, 5 }, |
1942 | 47.5k | {2640, 586, 4, 5 }, |
1943 | 47.5k | {2661, 591, 4, 5 }, |
1944 | 47.5k | {2682, 596, 4, 5 }, |
1945 | 47.5k | {2704, 601, 4, 5 }, |
1946 | 47.5k | {2726, 606, 4, 5 }, |
1947 | 47.5k | {2747, 611, 4, 5 }, |
1948 | | // Sparc_FMOVQ_ICC - 176 |
1949 | 47.5k | {2768, 616, 4, 5 }, |
1950 | 47.5k | {2788, 621, 4, 5 }, |
1951 | 47.5k | {2808, 626, 4, 5 }, |
1952 | 47.5k | {2829, 631, 4, 5 }, |
1953 | 47.5k | {2849, 636, 4, 5 }, |
1954 | 47.5k | {2869, 641, 4, 5 }, |
1955 | 47.5k | {2890, 646, 4, 5 }, |
1956 | 47.5k | {2911, 651, 4, 5 }, |
1957 | 47.5k | {2931, 656, 4, 5 }, |
1958 | 47.5k | {2952, 661, 4, 5 }, |
1959 | 47.5k | {2974, 666, 4, 5 }, |
1960 | 47.5k | {2995, 671, 4, 5 }, |
1961 | 47.5k | {3016, 676, 4, 5 }, |
1962 | 47.5k | {3038, 681, 4, 5 }, |
1963 | 47.5k | {3060, 686, 4, 5 }, |
1964 | 47.5k | {3081, 691, 4, 5 }, |
1965 | | // Sparc_FMOVQ_XCC - 192 |
1966 | 47.5k | {3102, 696, 4, 5 }, |
1967 | 47.5k | {3122, 701, 4, 5 }, |
1968 | 47.5k | {3142, 706, 4, 5 }, |
1969 | 47.5k | {3163, 711, 4, 5 }, |
1970 | 47.5k | {3183, 716, 4, 5 }, |
1971 | 47.5k | {3203, 721, 4, 5 }, |
1972 | 47.5k | {3224, 726, 4, 5 }, |
1973 | 47.5k | {3245, 731, 4, 5 }, |
1974 | 47.5k | {3265, 736, 4, 5 }, |
1975 | 47.5k | {3286, 741, 4, 5 }, |
1976 | 47.5k | {3308, 746, 4, 5 }, |
1977 | 47.5k | {3329, 751, 4, 5 }, |
1978 | 47.5k | {3350, 756, 4, 5 }, |
1979 | 47.5k | {3372, 761, 4, 5 }, |
1980 | 47.5k | {3394, 766, 4, 5 }, |
1981 | 47.5k | {3415, 771, 4, 5 }, |
1982 | | // Sparc_FMOVRD - 208 |
1983 | 47.5k | {3436, 776, 5, 6 }, |
1984 | 47.5k | {3455, 782, 5, 6 }, |
1985 | 47.5k | {3476, 788, 5, 6 }, |
1986 | 47.5k | {3496, 794, 5, 6 }, |
1987 | 47.5k | {3516, 800, 5, 6 }, |
1988 | 47.5k | {3536, 806, 5, 6 }, |
1989 | | // Sparc_FMOVRQ - 214 |
1990 | 47.5k | {3557, 812, 5, 6 }, |
1991 | 47.5k | {3576, 818, 5, 6 }, |
1992 | 47.5k | {3597, 824, 5, 6 }, |
1993 | 47.5k | {3617, 830, 5, 6 }, |
1994 | 47.5k | {3637, 836, 5, 6 }, |
1995 | 47.5k | {3657, 842, 5, 6 }, |
1996 | | // Sparc_FMOVRS - 220 |
1997 | 47.5k | {3678, 848, 5, 6 }, |
1998 | 47.5k | {3697, 854, 5, 6 }, |
1999 | 47.5k | {3718, 860, 5, 6 }, |
2000 | 47.5k | {3738, 866, 5, 6 }, |
2001 | 47.5k | {3758, 872, 5, 6 }, |
2002 | 47.5k | {3778, 878, 5, 6 }, |
2003 | | // Sparc_FMOVS_ICC - 226 |
2004 | 47.5k | {3799, 884, 4, 5 }, |
2005 | 47.5k | {3819, 889, 4, 5 }, |
2006 | 47.5k | {3839, 894, 4, 5 }, |
2007 | 47.5k | {3860, 899, 4, 5 }, |
2008 | 47.5k | {3880, 904, 4, 5 }, |
2009 | 47.5k | {3900, 909, 4, 5 }, |
2010 | 47.5k | {3921, 914, 4, 5 }, |
2011 | 47.5k | {3942, 919, 4, 5 }, |
2012 | 47.5k | {3962, 924, 4, 5 }, |
2013 | 47.5k | {3983, 929, 4, 5 }, |
2014 | 47.5k | {4005, 934, 4, 5 }, |
2015 | 47.5k | {4026, 939, 4, 5 }, |
2016 | 47.5k | {4047, 944, 4, 5 }, |
2017 | 47.5k | {4069, 949, 4, 5 }, |
2018 | 47.5k | {4091, 954, 4, 5 }, |
2019 | 47.5k | {4112, 959, 4, 5 }, |
2020 | | // Sparc_FMOVS_XCC - 242 |
2021 | 47.5k | {4133, 964, 4, 5 }, |
2022 | 47.5k | {4153, 969, 4, 5 }, |
2023 | 47.5k | {4173, 974, 4, 5 }, |
2024 | 47.5k | {4194, 979, 4, 5 }, |
2025 | 47.5k | {4214, 984, 4, 5 }, |
2026 | 47.5k | {4234, 989, 4, 5 }, |
2027 | 47.5k | {4255, 994, 4, 5 }, |
2028 | 47.5k | {4276, 999, 4, 5 }, |
2029 | 47.5k | {4296, 1004, 4, 5 }, |
2030 | 47.5k | {4317, 1009, 4, 5 }, |
2031 | 47.5k | {4339, 1014, 4, 5 }, |
2032 | 47.5k | {4360, 1019, 4, 5 }, |
2033 | 47.5k | {4381, 1024, 4, 5 }, |
2034 | 47.5k | {4403, 1029, 4, 5 }, |
2035 | 47.5k | {4425, 1034, 4, 5 }, |
2036 | 47.5k | {4446, 1039, 4, 5 }, |
2037 | | // Sparc_MOVICCri - 258 |
2038 | 47.5k | {4467, 1044, 4, 5 }, |
2039 | 47.5k | {4485, 1049, 4, 5 }, |
2040 | 47.5k | {4503, 1054, 4, 5 }, |
2041 | 47.5k | {4522, 1059, 4, 5 }, |
2042 | 47.5k | {4540, 1064, 4, 5 }, |
2043 | 47.5k | {4558, 1069, 4, 5 }, |
2044 | 47.5k | {4577, 1074, 4, 5 }, |
2045 | 47.5k | {4596, 1079, 4, 5 }, |
2046 | 47.5k | {4614, 1084, 4, 5 }, |
2047 | 47.5k | {4633, 1089, 4, 5 }, |
2048 | 47.5k | {4653, 1094, 4, 5 }, |
2049 | 47.5k | {4672, 1099, 4, 5 }, |
2050 | 47.5k | {4691, 1104, 4, 5 }, |
2051 | 47.5k | {4711, 1109, 4, 5 }, |
2052 | 47.5k | {4731, 1114, 4, 5 }, |
2053 | 47.5k | {4750, 1119, 4, 5 }, |
2054 | | // Sparc_MOVICCrr - 274 |
2055 | 47.5k | {4467, 1124, 4, 5 }, |
2056 | 47.5k | {4485, 1129, 4, 5 }, |
2057 | 47.5k | {4503, 1134, 4, 5 }, |
2058 | 47.5k | {4522, 1139, 4, 5 }, |
2059 | 47.5k | {4540, 1144, 4, 5 }, |
2060 | 47.5k | {4558, 1149, 4, 5 }, |
2061 | 47.5k | {4577, 1154, 4, 5 }, |
2062 | 47.5k | {4596, 1159, 4, 5 }, |
2063 | 47.5k | {4614, 1164, 4, 5 }, |
2064 | 47.5k | {4633, 1169, 4, 5 }, |
2065 | 47.5k | {4653, 1174, 4, 5 }, |
2066 | 47.5k | {4672, 1179, 4, 5 }, |
2067 | 47.5k | {4691, 1184, 4, 5 }, |
2068 | 47.5k | {4711, 1189, 4, 5 }, |
2069 | 47.5k | {4731, 1194, 4, 5 }, |
2070 | 47.5k | {4750, 1199, 4, 5 }, |
2071 | | // Sparc_MOVRri - 290 |
2072 | 47.5k | {4769, 1204, 5, 6 }, |
2073 | 47.5k | {4786, 1210, 5, 6 }, |
2074 | 47.5k | {4805, 1216, 5, 6 }, |
2075 | 47.5k | {4823, 1222, 5, 6 }, |
2076 | 47.5k | {4841, 1228, 5, 6 }, |
2077 | 47.5k | {4859, 1234, 5, 6 }, |
2078 | | // Sparc_MOVRrr - 296 |
2079 | 47.5k | {4769, 1240, 5, 6 }, |
2080 | 47.5k | {4786, 1246, 5, 6 }, |
2081 | 47.5k | {4805, 1252, 5, 6 }, |
2082 | 47.5k | {4823, 1258, 5, 6 }, |
2083 | 47.5k | {4841, 1264, 5, 6 }, |
2084 | 47.5k | {4859, 1270, 5, 6 }, |
2085 | | // Sparc_MOVXCCri - 302 |
2086 | 47.5k | {4878, 1276, 4, 5 }, |
2087 | 47.5k | {4896, 1281, 4, 5 }, |
2088 | 47.5k | {4914, 1286, 4, 5 }, |
2089 | 47.5k | {4933, 1291, 4, 5 }, |
2090 | 47.5k | {4951, 1296, 4, 5 }, |
2091 | 47.5k | {4969, 1301, 4, 5 }, |
2092 | 47.5k | {4988, 1306, 4, 5 }, |
2093 | 47.5k | {5007, 1311, 4, 5 }, |
2094 | 47.5k | {5025, 1316, 4, 5 }, |
2095 | 47.5k | {5044, 1321, 4, 5 }, |
2096 | 47.5k | {5064, 1326, 4, 5 }, |
2097 | 47.5k | {5083, 1331, 4, 5 }, |
2098 | 47.5k | {5102, 1336, 4, 5 }, |
2099 | 47.5k | {5122, 1341, 4, 5 }, |
2100 | 47.5k | {5142, 1346, 4, 5 }, |
2101 | 47.5k | {5161, 1351, 4, 5 }, |
2102 | | // Sparc_MOVXCCrr - 318 |
2103 | 47.5k | {4878, 1356, 4, 5 }, |
2104 | 47.5k | {4896, 1361, 4, 5 }, |
2105 | 47.5k | {4914, 1366, 4, 5 }, |
2106 | 47.5k | {4933, 1371, 4, 5 }, |
2107 | 47.5k | {4951, 1376, 4, 5 }, |
2108 | 47.5k | {4969, 1381, 4, 5 }, |
2109 | 47.5k | {4988, 1386, 4, 5 }, |
2110 | 47.5k | {5007, 1391, 4, 5 }, |
2111 | 47.5k | {5025, 1396, 4, 5 }, |
2112 | 47.5k | {5044, 1401, 4, 5 }, |
2113 | 47.5k | {5064, 1406, 4, 5 }, |
2114 | 47.5k | {5083, 1411, 4, 5 }, |
2115 | 47.5k | {5102, 1416, 4, 5 }, |
2116 | 47.5k | {5122, 1421, 4, 5 }, |
2117 | 47.5k | {5142, 1426, 4, 5 }, |
2118 | 47.5k | {5161, 1431, 4, 5 }, |
2119 | | // Sparc_ORCCrr - 334 |
2120 | 47.5k | {5180, 1436, 3, 3 }, |
2121 | | // Sparc_ORri - 335 |
2122 | 47.5k | {5187, 1439, 3, 2 }, |
2123 | | // Sparc_ORrr - 336 |
2124 | 47.5k | {5187, 1441, 3, 3 }, |
2125 | | // Sparc_RESTORErr - 337 |
2126 | 47.5k | {5198, 1444, 3, 3 }, |
2127 | | // Sparc_RET - 338 |
2128 | 47.5k | {5206, 1447, 1, 1 }, |
2129 | | // Sparc_RETL - 339 |
2130 | 47.5k | {5210, 1448, 1, 1 }, |
2131 | | // Sparc_SAVErr - 340 |
2132 | 47.5k | {5215, 1449, 3, 3 }, |
2133 | | // Sparc_SUBCCri - 341 |
2134 | 47.5k | {5220, 1452, 3, 2 }, |
2135 | | // Sparc_SUBCCrr - 342 |
2136 | 47.5k | {5220, 1454, 3, 3 }, |
2137 | | // Sparc_TICCri - 343 |
2138 | 47.5k | {5231, 1457, 3, 4 }, |
2139 | 47.5k | {5243, 1461, 3, 4 }, |
2140 | 47.5k | {5260, 1465, 3, 4 }, |
2141 | 47.5k | {5272, 1469, 3, 4 }, |
2142 | 47.5k | {5289, 1473, 3, 4 }, |
2143 | 47.5k | {5302, 1477, 3, 4 }, |
2144 | 47.5k | {5320, 1481, 3, 4 }, |
2145 | 47.5k | {5332, 1485, 3, 4 }, |
2146 | 47.5k | {5349, 1489, 3, 4 }, |
2147 | 47.5k | {5361, 1493, 3, 4 }, |
2148 | 47.5k | {5378, 1497, 3, 4 }, |
2149 | 47.5k | {5391, 1501, 3, 4 }, |
2150 | 47.5k | {5409, 1505, 3, 4 }, |
2151 | 47.5k | {5422, 1509, 3, 4 }, |
2152 | 47.5k | {5440, 1513, 3, 4 }, |
2153 | 47.5k | {5452, 1517, 3, 4 }, |
2154 | 47.5k | {5469, 1521, 3, 4 }, |
2155 | 47.5k | {5482, 1525, 3, 4 }, |
2156 | 47.5k | {5500, 1529, 3, 4 }, |
2157 | 47.5k | {5514, 1533, 3, 4 }, |
2158 | 47.5k | {5533, 1537, 3, 4 }, |
2159 | 47.5k | {5546, 1541, 3, 4 }, |
2160 | 47.5k | {5564, 1545, 3, 4 }, |
2161 | 47.5k | {5577, 1549, 3, 4 }, |
2162 | 47.5k | {5595, 1553, 3, 4 }, |
2163 | 47.5k | {5609, 1557, 3, 4 }, |
2164 | 47.5k | {5628, 1561, 3, 4 }, |
2165 | 47.5k | {5642, 1565, 3, 4 }, |
2166 | 47.5k | {5661, 1569, 3, 4 }, |
2167 | 47.5k | {5674, 1573, 3, 4 }, |
2168 | 47.5k | {5692, 1577, 3, 4 }, |
2169 | 47.5k | {5705, 1581, 3, 4 }, |
2170 | | // Sparc_TICCrr - 375 |
2171 | 47.5k | {5231, 1585, 3, 4 }, |
2172 | 47.5k | {5243, 1589, 3, 4 }, |
2173 | 47.5k | {5260, 1593, 3, 4 }, |
2174 | 47.5k | {5272, 1597, 3, 4 }, |
2175 | 47.5k | {5289, 1601, 3, 4 }, |
2176 | 47.5k | {5302, 1605, 3, 4 }, |
2177 | 47.5k | {5320, 1609, 3, 4 }, |
2178 | 47.5k | {5332, 1613, 3, 4 }, |
2179 | 47.5k | {5349, 1617, 3, 4 }, |
2180 | 47.5k | {5361, 1621, 3, 4 }, |
2181 | 47.5k | {5378, 1625, 3, 4 }, |
2182 | 47.5k | {5391, 1629, 3, 4 }, |
2183 | 47.5k | {5409, 1633, 3, 4 }, |
2184 | 47.5k | {5422, 1637, 3, 4 }, |
2185 | 47.5k | {5440, 1641, 3, 4 }, |
2186 | 47.5k | {5452, 1645, 3, 4 }, |
2187 | 47.5k | {5469, 1649, 3, 4 }, |
2188 | 47.5k | {5482, 1653, 3, 4 }, |
2189 | 47.5k | {5500, 1657, 3, 4 }, |
2190 | 47.5k | {5514, 1661, 3, 4 }, |
2191 | 47.5k | {5533, 1665, 3, 4 }, |
2192 | 47.5k | {5546, 1669, 3, 4 }, |
2193 | 47.5k | {5564, 1673, 3, 4 }, |
2194 | 47.5k | {5577, 1677, 3, 4 }, |
2195 | 47.5k | {5595, 1681, 3, 4 }, |
2196 | 47.5k | {5609, 1685, 3, 4 }, |
2197 | 47.5k | {5628, 1689, 3, 4 }, |
2198 | 47.5k | {5642, 1693, 3, 4 }, |
2199 | 47.5k | {5661, 1697, 3, 4 }, |
2200 | 47.5k | {5674, 1701, 3, 4 }, |
2201 | 47.5k | {5692, 1705, 3, 4 }, |
2202 | 47.5k | {5705, 1709, 3, 4 }, |
2203 | | // Sparc_TRAPri - 407 |
2204 | 47.5k | {5723, 1713, 3, 3 }, |
2205 | 47.5k | {5729, 1716, 3, 3 }, |
2206 | 47.5k | {5740, 1719, 3, 3 }, |
2207 | 47.5k | {5746, 1722, 3, 3 }, |
2208 | 47.5k | {5757, 1725, 3, 3 }, |
2209 | 47.5k | {5764, 1728, 3, 3 }, |
2210 | 47.5k | {5776, 1731, 3, 3 }, |
2211 | 47.5k | {5782, 1734, 3, 3 }, |
2212 | 47.5k | {5793, 1737, 3, 3 }, |
2213 | 47.5k | {5799, 1740, 3, 3 }, |
2214 | 47.5k | {5810, 1743, 3, 3 }, |
2215 | 47.5k | {5817, 1746, 3, 3 }, |
2216 | 47.5k | {5829, 1749, 3, 3 }, |
2217 | 47.5k | {5836, 1752, 3, 3 }, |
2218 | 47.5k | {5848, 1755, 3, 3 }, |
2219 | 47.5k | {5854, 1758, 3, 3 }, |
2220 | 47.5k | {5865, 1761, 3, 3 }, |
2221 | 47.5k | {5872, 1764, 3, 3 }, |
2222 | 47.5k | {5884, 1767, 3, 3 }, |
2223 | 47.5k | {5892, 1770, 3, 3 }, |
2224 | 47.5k | {5905, 1773, 3, 3 }, |
2225 | 47.5k | {5912, 1776, 3, 3 }, |
2226 | 47.5k | {5924, 1779, 3, 3 }, |
2227 | 47.5k | {5931, 1782, 3, 3 }, |
2228 | 47.5k | {5943, 1785, 3, 3 }, |
2229 | 47.5k | {5951, 1788, 3, 3 }, |
2230 | 47.5k | {5964, 1791, 3, 3 }, |
2231 | 47.5k | {5972, 1794, 3, 3 }, |
2232 | 47.5k | {5985, 1797, 3, 3 }, |
2233 | 47.5k | {5992, 1800, 3, 3 }, |
2234 | 47.5k | {6004, 1803, 3, 3 }, |
2235 | 47.5k | {6011, 1806, 3, 3 }, |
2236 | | // Sparc_TRAPrr - 439 |
2237 | 47.5k | {5723, 1809, 3, 3 }, |
2238 | 47.5k | {5729, 1812, 3, 3 }, |
2239 | 47.5k | {5740, 1815, 3, 3 }, |
2240 | 47.5k | {5746, 1818, 3, 3 }, |
2241 | 47.5k | {5757, 1821, 3, 3 }, |
2242 | 47.5k | {5764, 1824, 3, 3 }, |
2243 | 47.5k | {5776, 1827, 3, 3 }, |
2244 | 47.5k | {5782, 1830, 3, 3 }, |
2245 | 47.5k | {5793, 1833, 3, 3 }, |
2246 | 47.5k | {5799, 1836, 3, 3 }, |
2247 | 47.5k | {5810, 1839, 3, 3 }, |
2248 | 47.5k | {5817, 1842, 3, 3 }, |
2249 | 47.5k | {5829, 1845, 3, 3 }, |
2250 | 47.5k | {5836, 1848, 3, 3 }, |
2251 | 47.5k | {5848, 1851, 3, 3 }, |
2252 | 47.5k | {5854, 1854, 3, 3 }, |
2253 | 47.5k | {5865, 1857, 3, 3 }, |
2254 | 47.5k | {5872, 1860, 3, 3 }, |
2255 | 47.5k | {5884, 1863, 3, 3 }, |
2256 | 47.5k | {5892, 1866, 3, 3 }, |
2257 | 47.5k | {5905, 1869, 3, 3 }, |
2258 | 47.5k | {5912, 1872, 3, 3 }, |
2259 | 47.5k | {5924, 1875, 3, 3 }, |
2260 | 47.5k | {5931, 1878, 3, 3 }, |
2261 | 47.5k | {5943, 1881, 3, 3 }, |
2262 | 47.5k | {5951, 1884, 3, 3 }, |
2263 | 47.5k | {5964, 1887, 3, 3 }, |
2264 | 47.5k | {5972, 1890, 3, 3 }, |
2265 | 47.5k | {5985, 1893, 3, 3 }, |
2266 | 47.5k | {5992, 1896, 3, 3 }, |
2267 | 47.5k | {6004, 1899, 3, 3 }, |
2268 | 47.5k | {6011, 1902, 3, 3 }, |
2269 | | // Sparc_TXCCri - 471 |
2270 | 47.5k | {6023, 1905, 3, 4 }, |
2271 | 47.5k | {6035, 1909, 3, 4 }, |
2272 | 47.5k | {6052, 1913, 3, 4 }, |
2273 | 47.5k | {6064, 1917, 3, 4 }, |
2274 | 47.5k | {6081, 1921, 3, 4 }, |
2275 | 47.5k | {6094, 1925, 3, 4 }, |
2276 | 47.5k | {6112, 1929, 3, 4 }, |
2277 | 47.5k | {6124, 1933, 3, 4 }, |
2278 | 47.5k | {6141, 1937, 3, 4 }, |
2279 | 47.5k | {6153, 1941, 3, 4 }, |
2280 | 47.5k | {6170, 1945, 3, 4 }, |
2281 | 47.5k | {6183, 1949, 3, 4 }, |
2282 | 47.5k | {6201, 1953, 3, 4 }, |
2283 | 47.5k | {6214, 1957, 3, 4 }, |
2284 | 47.5k | {6232, 1961, 3, 4 }, |
2285 | 47.5k | {6244, 1965, 3, 4 }, |
2286 | 47.5k | {6261, 1969, 3, 4 }, |
2287 | 47.5k | {6274, 1973, 3, 4 }, |
2288 | 47.5k | {6292, 1977, 3, 4 }, |
2289 | 47.5k | {6306, 1981, 3, 4 }, |
2290 | 47.5k | {6325, 1985, 3, 4 }, |
2291 | 47.5k | {6338, 1989, 3, 4 }, |
2292 | 47.5k | {6356, 1993, 3, 4 }, |
2293 | 47.5k | {6369, 1997, 3, 4 }, |
2294 | 47.5k | {6387, 2001, 3, 4 }, |
2295 | 47.5k | {6401, 2005, 3, 4 }, |
2296 | 47.5k | {6420, 2009, 3, 4 }, |
2297 | 47.5k | {6434, 2013, 3, 4 }, |
2298 | 47.5k | {6453, 2017, 3, 4 }, |
2299 | 47.5k | {6466, 2021, 3, 4 }, |
2300 | 47.5k | {6484, 2025, 3, 4 }, |
2301 | 47.5k | {6497, 2029, 3, 4 }, |
2302 | | // Sparc_TXCCrr - 503 |
2303 | 47.5k | {6023, 2033, 3, 4 }, |
2304 | 47.5k | {6035, 2037, 3, 4 }, |
2305 | 47.5k | {6052, 2041, 3, 4 }, |
2306 | 47.5k | {6064, 2045, 3, 4 }, |
2307 | 47.5k | {6081, 2049, 3, 4 }, |
2308 | 47.5k | {6094, 2053, 3, 4 }, |
2309 | 47.5k | {6112, 2057, 3, 4 }, |
2310 | 47.5k | {6124, 2061, 3, 4 }, |
2311 | 47.5k | {6141, 2065, 3, 4 }, |
2312 | 47.5k | {6153, 2069, 3, 4 }, |
2313 | 47.5k | {6170, 2073, 3, 4 }, |
2314 | 47.5k | {6183, 2077, 3, 4 }, |
2315 | 47.5k | {6201, 2081, 3, 4 }, |
2316 | 47.5k | {6214, 2085, 3, 4 }, |
2317 | 47.5k | {6232, 2089, 3, 4 }, |
2318 | 47.5k | {6244, 2093, 3, 4 }, |
2319 | 47.5k | {6261, 2097, 3, 4 }, |
2320 | 47.5k | {6274, 2101, 3, 4 }, |
2321 | 47.5k | {6292, 2105, 3, 4 }, |
2322 | 47.5k | {6306, 2109, 3, 4 }, |
2323 | 47.5k | {6325, 2113, 3, 4 }, |
2324 | 47.5k | {6338, 2117, 3, 4 }, |
2325 | 47.5k | {6356, 2121, 3, 4 }, |
2326 | 47.5k | {6369, 2125, 3, 4 }, |
2327 | 47.5k | {6387, 2129, 3, 4 }, |
2328 | 47.5k | {6401, 2133, 3, 4 }, |
2329 | 47.5k | {6420, 2137, 3, 4 }, |
2330 | 47.5k | {6434, 2141, 3, 4 }, |
2331 | 47.5k | {6453, 2145, 3, 4 }, |
2332 | 47.5k | {6466, 2149, 3, 4 }, |
2333 | 47.5k | {6484, 2153, 3, 4 }, |
2334 | 47.5k | {6497, 2157, 3, 4 }, |
2335 | | // Sparc_V9FCMPD - 535 |
2336 | 47.5k | {6515, 2161, 3, 3 }, |
2337 | | // Sparc_V9FCMPED - 536 |
2338 | 47.5k | {6528, 2164, 3, 3 }, |
2339 | | // Sparc_V9FCMPEQ - 537 |
2340 | 47.5k | {6542, 2167, 3, 3 }, |
2341 | | // Sparc_V9FCMPES - 538 |
2342 | 47.5k | {6556, 2170, 3, 3 }, |
2343 | | // Sparc_V9FCMPQ - 539 |
2344 | 47.5k | {6570, 2173, 3, 3 }, |
2345 | | // Sparc_V9FCMPS - 540 |
2346 | 47.5k | {6583, 2176, 3, 3 }, |
2347 | | // Sparc_V9FMOVD_FCC - 541 |
2348 | 47.5k | {6596, 2179, 5, 6 }, |
2349 | 47.5k | {6614, 2185, 5, 6 }, |
2350 | 47.5k | {6632, 2191, 5, 6 }, |
2351 | 47.5k | {6650, 2197, 5, 6 }, |
2352 | 47.5k | {6668, 2203, 5, 6 }, |
2353 | 47.5k | {6687, 2209, 5, 6 }, |
2354 | 47.5k | {6705, 2215, 5, 6 }, |
2355 | 47.5k | {6724, 2221, 5, 6 }, |
2356 | 47.5k | {6743, 2227, 5, 6 }, |
2357 | 47.5k | {6762, 2233, 5, 6 }, |
2358 | 47.5k | {6780, 2239, 5, 6 }, |
2359 | 47.5k | {6799, 2245, 5, 6 }, |
2360 | 47.5k | {6818, 2251, 5, 6 }, |
2361 | 47.5k | {6838, 2257, 5, 6 }, |
2362 | 47.5k | {6857, 2263, 5, 6 }, |
2363 | 47.5k | {6877, 2269, 5, 6 }, |
2364 | | // Sparc_V9FMOVQ_FCC - 557 |
2365 | 47.5k | {6895, 2275, 5, 6 }, |
2366 | 47.5k | {6913, 2281, 5, 6 }, |
2367 | 47.5k | {6931, 2287, 5, 6 }, |
2368 | 47.5k | {6949, 2293, 5, 6 }, |
2369 | 47.5k | {6967, 2299, 5, 6 }, |
2370 | 47.5k | {6986, 2305, 5, 6 }, |
2371 | 47.5k | {7004, 2311, 5, 6 }, |
2372 | 47.5k | {7023, 2317, 5, 6 }, |
2373 | 47.5k | {7042, 2323, 5, 6 }, |
2374 | 47.5k | {7061, 2329, 5, 6 }, |
2375 | 47.5k | {7079, 2335, 5, 6 }, |
2376 | 47.5k | {7098, 2341, 5, 6 }, |
2377 | 47.5k | {7117, 2347, 5, 6 }, |
2378 | 47.5k | {7137, 2353, 5, 6 }, |
2379 | 47.5k | {7156, 2359, 5, 6 }, |
2380 | 47.5k | {7176, 2365, 5, 6 }, |
2381 | | // Sparc_V9FMOVS_FCC - 573 |
2382 | 47.5k | {7194, 2371, 5, 6 }, |
2383 | 47.5k | {7212, 2377, 5, 6 }, |
2384 | 47.5k | {7230, 2383, 5, 6 }, |
2385 | 47.5k | {7248, 2389, 5, 6 }, |
2386 | 47.5k | {7266, 2395, 5, 6 }, |
2387 | 47.5k | {7285, 2401, 5, 6 }, |
2388 | 47.5k | {7303, 2407, 5, 6 }, |
2389 | 47.5k | {7322, 2413, 5, 6 }, |
2390 | 47.5k | {7341, 2419, 5, 6 }, |
2391 | 47.5k | {7360, 2425, 5, 6 }, |
2392 | 47.5k | {7378, 2431, 5, 6 }, |
2393 | 47.5k | {7397, 2437, 5, 6 }, |
2394 | 47.5k | {7416, 2443, 5, 6 }, |
2395 | 47.5k | {7436, 2449, 5, 6 }, |
2396 | 47.5k | {7455, 2455, 5, 6 }, |
2397 | 47.5k | {7475, 2461, 5, 6 }, |
2398 | | // Sparc_V9MOVFCCri - 589 |
2399 | 47.5k | {7493, 2467, 5, 6 }, |
2400 | 47.5k | {7509, 2473, 5, 6 }, |
2401 | 47.5k | {7525, 2479, 5, 6 }, |
2402 | 47.5k | {7541, 2485, 5, 6 }, |
2403 | 47.5k | {7557, 2491, 5, 6 }, |
2404 | 47.5k | {7574, 2497, 5, 6 }, |
2405 | 47.5k | {7590, 2503, 5, 6 }, |
2406 | 47.5k | {7607, 2509, 5, 6 }, |
2407 | 47.5k | {7624, 2515, 5, 6 }, |
2408 | 47.5k | {7641, 2521, 5, 6 }, |
2409 | 47.5k | {7657, 2527, 5, 6 }, |
2410 | 47.5k | {7674, 2533, 5, 6 }, |
2411 | 47.5k | {7691, 2539, 5, 6 }, |
2412 | 47.5k | {7709, 2545, 5, 6 }, |
2413 | 47.5k | {7726, 2551, 5, 6 }, |
2414 | 47.5k | {7744, 2557, 5, 6 }, |
2415 | | // Sparc_V9MOVFCCrr - 605 |
2416 | 47.5k | {7493, 2563, 5, 6 }, |
2417 | 47.5k | {7509, 2569, 5, 6 }, |
2418 | 47.5k | {7525, 2575, 5, 6 }, |
2419 | 47.5k | {7541, 2581, 5, 6 }, |
2420 | 47.5k | {7557, 2587, 5, 6 }, |
2421 | 47.5k | {7574, 2593, 5, 6 }, |
2422 | 47.5k | {7590, 2599, 5, 6 }, |
2423 | 47.5k | {7607, 2605, 5, 6 }, |
2424 | 47.5k | {7624, 2611, 5, 6 }, |
2425 | 47.5k | {7641, 2617, 5, 6 }, |
2426 | 47.5k | {7657, 2623, 5, 6 }, |
2427 | 47.5k | {7674, 2629, 5, 6 }, |
2428 | 47.5k | {7691, 2635, 5, 6 }, |
2429 | 47.5k | {7709, 2641, 5, 6 }, |
2430 | 47.5k | {7726, 2647, 5, 6 }, |
2431 | 47.5k | {7744, 2653, 5, 6 }, |
2432 | 47.5k | {0}, }; |
2433 | | |
2434 | 47.5k | static const AliasPatternCond Conds[] = { |
2435 | | // (BCOND brtarget:$imm, 8) - 0 |
2436 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2437 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
2438 | | // (BCOND brtarget:$imm, 0) - 2 |
2439 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2440 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
2441 | | // (BCOND brtarget:$imm, 9) - 4 |
2442 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2443 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
2444 | | // (BCOND brtarget:$imm, 1) - 6 |
2445 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2446 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
2447 | | // (BCOND brtarget:$imm, 10) - 8 |
2448 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2449 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
2450 | | // (BCOND brtarget:$imm, 2) - 10 |
2451 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2452 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
2453 | | // (BCOND brtarget:$imm, 11) - 12 |
2454 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2455 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
2456 | | // (BCOND brtarget:$imm, 3) - 14 |
2457 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2458 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
2459 | | // (BCOND brtarget:$imm, 12) - 16 |
2460 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2461 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
2462 | | // (BCOND brtarget:$imm, 4) - 18 |
2463 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2464 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
2465 | | // (BCOND brtarget:$imm, 13) - 20 |
2466 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2467 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
2468 | | // (BCOND brtarget:$imm, 5) - 22 |
2469 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2470 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
2471 | | // (BCOND brtarget:$imm, 14) - 24 |
2472 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2473 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
2474 | | // (BCOND brtarget:$imm, 6) - 26 |
2475 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2476 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
2477 | | // (BCOND brtarget:$imm, 15) - 28 |
2478 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2479 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
2480 | | // (BCOND brtarget:$imm, 7) - 30 |
2481 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2482 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
2483 | | // (BCONDA brtarget:$imm, 8) - 32 |
2484 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2485 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
2486 | | // (BCONDA brtarget:$imm, 0) - 34 |
2487 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2488 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
2489 | | // (BCONDA brtarget:$imm, 9) - 36 |
2490 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2491 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
2492 | | // (BCONDA brtarget:$imm, 1) - 38 |
2493 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2494 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
2495 | | // (BCONDA brtarget:$imm, 10) - 40 |
2496 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2497 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
2498 | | // (BCONDA brtarget:$imm, 2) - 42 |
2499 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2500 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
2501 | | // (BCONDA brtarget:$imm, 11) - 44 |
2502 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2503 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
2504 | | // (BCONDA brtarget:$imm, 3) - 46 |
2505 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2506 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
2507 | | // (BCONDA brtarget:$imm, 12) - 48 |
2508 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2509 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
2510 | | // (BCONDA brtarget:$imm, 4) - 50 |
2511 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2512 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
2513 | | // (BCONDA brtarget:$imm, 13) - 52 |
2514 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2515 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
2516 | | // (BCONDA brtarget:$imm, 5) - 54 |
2517 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2518 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
2519 | | // (BCONDA brtarget:$imm, 14) - 56 |
2520 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2521 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
2522 | | // (BCONDA brtarget:$imm, 6) - 58 |
2523 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2524 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
2525 | | // (BCONDA brtarget:$imm, 15) - 60 |
2526 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2527 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
2528 | | // (BCONDA brtarget:$imm, 7) - 62 |
2529 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2530 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
2531 | | // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) - 64 |
2532 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2533 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
2534 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2535 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2536 | | // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) - 68 |
2537 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2538 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
2539 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2540 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2541 | | // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) - 72 |
2542 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2543 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
2544 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2545 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2546 | | // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) - 76 |
2547 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2548 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
2549 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2550 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2551 | | // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) - 80 |
2552 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2553 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
2554 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2555 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2556 | | // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) - 84 |
2557 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2558 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
2559 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2560 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2561 | | // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) - 88 |
2562 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2563 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
2564 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2565 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2566 | | // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) - 92 |
2567 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2568 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
2569 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2570 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2571 | | // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) - 96 |
2572 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2573 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
2574 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2575 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2576 | | // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) - 100 |
2577 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2578 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
2579 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2580 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2581 | | // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) - 104 |
2582 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2583 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
2584 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2585 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2586 | | // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) - 108 |
2587 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2588 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
2589 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2590 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2591 | | // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) - 112 |
2592 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2593 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
2594 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2595 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2596 | | // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) - 116 |
2597 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2598 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
2599 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2600 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2601 | | // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) - 120 |
2602 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2603 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
2604 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2605 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2606 | | // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) - 124 |
2607 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2608 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
2609 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2610 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2611 | | // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) - 128 |
2612 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2613 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
2614 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2615 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2616 | | // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) - 132 |
2617 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2618 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
2619 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2620 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2621 | | // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) - 136 |
2622 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2623 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
2624 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2625 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2626 | | // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) - 140 |
2627 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2628 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
2629 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2630 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2631 | | // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) - 144 |
2632 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2633 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
2634 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2635 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2636 | | // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) - 148 |
2637 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2638 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
2639 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2640 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2641 | | // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) - 152 |
2642 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2643 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
2644 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2645 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2646 | | // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) - 156 |
2647 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2648 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
2649 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2650 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2651 | | // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) - 160 |
2652 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2653 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
2654 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2655 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2656 | | // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) - 164 |
2657 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2658 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
2659 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2660 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2661 | | // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) - 168 |
2662 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2663 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
2664 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2665 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2666 | | // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) - 172 |
2667 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2668 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
2669 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2670 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2671 | | // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) - 176 |
2672 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2673 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
2674 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2675 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2676 | | // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) - 180 |
2677 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2678 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
2679 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2680 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2681 | | // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) - 184 |
2682 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2683 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
2684 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2685 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2686 | | // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) - 188 |
2687 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2688 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
2689 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
2690 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2691 | | // (BPICCANT brtarget:$imm, 8) - 192 |
2692 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2693 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
2694 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2695 | | // (BPICCANT brtarget:$imm, 0) - 195 |
2696 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2697 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
2698 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2699 | | // (BPICCANT brtarget:$imm, 9) - 198 |
2700 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2701 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
2702 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2703 | | // (BPICCANT brtarget:$imm, 1) - 201 |
2704 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2705 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
2706 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2707 | | // (BPICCANT brtarget:$imm, 10) - 204 |
2708 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2709 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
2710 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2711 | | // (BPICCANT brtarget:$imm, 2) - 207 |
2712 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2713 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
2714 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2715 | | // (BPICCANT brtarget:$imm, 11) - 210 |
2716 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2717 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
2718 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2719 | | // (BPICCANT brtarget:$imm, 3) - 213 |
2720 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2721 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
2722 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2723 | | // (BPICCANT brtarget:$imm, 12) - 216 |
2724 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2725 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
2726 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2727 | | // (BPICCANT brtarget:$imm, 4) - 219 |
2728 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2729 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
2730 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2731 | | // (BPICCANT brtarget:$imm, 13) - 222 |
2732 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2733 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
2734 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2735 | | // (BPICCANT brtarget:$imm, 5) - 225 |
2736 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2737 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
2738 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2739 | | // (BPICCANT brtarget:$imm, 14) - 228 |
2740 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2741 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
2742 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2743 | | // (BPICCANT brtarget:$imm, 6) - 231 |
2744 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2745 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
2746 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2747 | | // (BPICCANT brtarget:$imm, 15) - 234 |
2748 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2749 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
2750 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2751 | | // (BPICCANT brtarget:$imm, 7) - 237 |
2752 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2753 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
2754 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2755 | | // (BPICCNT brtarget:$imm, 8) - 240 |
2756 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2757 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
2758 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2759 | | // (BPICCNT brtarget:$imm, 0) - 243 |
2760 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2761 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
2762 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2763 | | // (BPICCNT brtarget:$imm, 9) - 246 |
2764 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2765 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
2766 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2767 | | // (BPICCNT brtarget:$imm, 1) - 249 |
2768 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2769 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
2770 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2771 | | // (BPICCNT brtarget:$imm, 10) - 252 |
2772 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2773 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
2774 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2775 | | // (BPICCNT brtarget:$imm, 2) - 255 |
2776 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2777 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
2778 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2779 | | // (BPICCNT brtarget:$imm, 11) - 258 |
2780 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2781 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
2782 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2783 | | // (BPICCNT brtarget:$imm, 3) - 261 |
2784 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2785 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
2786 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2787 | | // (BPICCNT brtarget:$imm, 12) - 264 |
2788 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2789 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
2790 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2791 | | // (BPICCNT brtarget:$imm, 4) - 267 |
2792 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2793 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
2794 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2795 | | // (BPICCNT brtarget:$imm, 13) - 270 |
2796 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2797 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
2798 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2799 | | // (BPICCNT brtarget:$imm, 5) - 273 |
2800 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2801 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
2802 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2803 | | // (BPICCNT brtarget:$imm, 14) - 276 |
2804 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2805 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
2806 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2807 | | // (BPICCNT brtarget:$imm, 6) - 279 |
2808 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2809 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
2810 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2811 | | // (BPICCNT brtarget:$imm, 15) - 282 |
2812 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2813 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
2814 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2815 | | // (BPICCNT brtarget:$imm, 7) - 285 |
2816 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2817 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
2818 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2819 | | // (BPRANT bprtarget16:$imm, 1, I64Regs:$rs1) - 288 |
2820 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2821 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
2822 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
2823 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2824 | | // (BPRANT bprtarget16:$imm, 2, I64Regs:$rs1) - 292 |
2825 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2826 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
2827 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
2828 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2829 | | // (BPRANT bprtarget16:$imm, 3, I64Regs:$rs1) - 296 |
2830 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2831 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
2832 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
2833 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2834 | | // (BPRANT bprtarget16:$imm, 5, I64Regs:$rs1) - 300 |
2835 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2836 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
2837 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
2838 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2839 | | // (BPRANT bprtarget16:$imm, 6, I64Regs:$rs1) - 304 |
2840 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2841 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
2842 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
2843 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2844 | | // (BPRANT bprtarget16:$imm, 7, I64Regs:$rs1) - 308 |
2845 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2846 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
2847 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
2848 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2849 | | // (BPRNT bprtarget16:$imm, 1, I64Regs:$rs1) - 312 |
2850 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2851 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
2852 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
2853 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2854 | | // (BPRNT bprtarget16:$imm, 2, I64Regs:$rs1) - 316 |
2855 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2856 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
2857 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
2858 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2859 | | // (BPRNT bprtarget16:$imm, 3, I64Regs:$rs1) - 320 |
2860 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2861 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
2862 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
2863 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2864 | | // (BPRNT bprtarget16:$imm, 5, I64Regs:$rs1) - 324 |
2865 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2866 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
2867 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
2868 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2869 | | // (BPRNT bprtarget16:$imm, 6, I64Regs:$rs1) - 328 |
2870 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2871 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
2872 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
2873 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2874 | | // (BPRNT bprtarget16:$imm, 7, I64Regs:$rs1) - 332 |
2875 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2876 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
2877 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
2878 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2879 | | // (BPXCCANT brtarget:$imm, 8) - 336 |
2880 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2881 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
2882 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2883 | | // (BPXCCANT brtarget:$imm, 0) - 339 |
2884 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2885 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
2886 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2887 | | // (BPXCCANT brtarget:$imm, 9) - 342 |
2888 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2889 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
2890 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2891 | | // (BPXCCANT brtarget:$imm, 1) - 345 |
2892 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2893 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
2894 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2895 | | // (BPXCCANT brtarget:$imm, 10) - 348 |
2896 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2897 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
2898 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2899 | | // (BPXCCANT brtarget:$imm, 2) - 351 |
2900 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2901 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
2902 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2903 | | // (BPXCCANT brtarget:$imm, 11) - 354 |
2904 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2905 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
2906 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2907 | | // (BPXCCANT brtarget:$imm, 3) - 357 |
2908 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2909 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
2910 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2911 | | // (BPXCCANT brtarget:$imm, 12) - 360 |
2912 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2913 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
2914 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2915 | | // (BPXCCANT brtarget:$imm, 4) - 363 |
2916 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2917 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
2918 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2919 | | // (BPXCCANT brtarget:$imm, 13) - 366 |
2920 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2921 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
2922 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2923 | | // (BPXCCANT brtarget:$imm, 5) - 369 |
2924 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2925 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
2926 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2927 | | // (BPXCCANT brtarget:$imm, 14) - 372 |
2928 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2929 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
2930 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2931 | | // (BPXCCANT brtarget:$imm, 6) - 375 |
2932 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2933 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
2934 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2935 | | // (BPXCCANT brtarget:$imm, 15) - 378 |
2936 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2937 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
2938 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2939 | | // (BPXCCANT brtarget:$imm, 7) - 381 |
2940 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2941 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
2942 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2943 | | // (BPXCCNT brtarget:$imm, 8) - 384 |
2944 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2945 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
2946 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2947 | | // (BPXCCNT brtarget:$imm, 0) - 387 |
2948 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2949 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
2950 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2951 | | // (BPXCCNT brtarget:$imm, 9) - 390 |
2952 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2953 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
2954 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2955 | | // (BPXCCNT brtarget:$imm, 1) - 393 |
2956 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2957 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
2958 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2959 | | // (BPXCCNT brtarget:$imm, 10) - 396 |
2960 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2961 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
2962 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2963 | | // (BPXCCNT brtarget:$imm, 2) - 399 |
2964 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2965 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
2966 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2967 | | // (BPXCCNT brtarget:$imm, 11) - 402 |
2968 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2969 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
2970 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2971 | | // (BPXCCNT brtarget:$imm, 3) - 405 |
2972 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2973 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
2974 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2975 | | // (BPXCCNT brtarget:$imm, 12) - 408 |
2976 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2977 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
2978 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2979 | | // (BPXCCNT brtarget:$imm, 4) - 411 |
2980 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2981 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
2982 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2983 | | // (BPXCCNT brtarget:$imm, 13) - 414 |
2984 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2985 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
2986 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2987 | | // (BPXCCNT brtarget:$imm, 5) - 417 |
2988 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2989 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
2990 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2991 | | // (BPXCCNT brtarget:$imm, 14) - 420 |
2992 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2993 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
2994 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2995 | | // (BPXCCNT brtarget:$imm, 6) - 423 |
2996 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
2997 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
2998 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
2999 | | // (BPXCCNT brtarget:$imm, 15) - 426 |
3000 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3001 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
3002 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3003 | | // (BPXCCNT brtarget:$imm, 7) - 429 |
3004 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3005 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
3006 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3007 | | // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 128) - 432 |
3008 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3009 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3010 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3011 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3012 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)128}, |
3013 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3014 | | // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 136) - 438 |
3015 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3016 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3017 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3018 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3019 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)136}, |
3020 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3021 | | // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 128) - 444 |
3022 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3023 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3024 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3025 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3026 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)128}, |
3027 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3028 | | // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 136) - 450 |
3029 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3030 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3031 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3032 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3033 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)136}, |
3034 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3035 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 456 |
3036 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3037 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3038 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3039 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
3040 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3041 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 461 |
3042 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3043 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3044 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3045 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
3046 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3047 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 466 |
3048 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3049 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3050 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3051 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
3052 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3053 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 471 |
3054 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3055 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3056 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3057 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
3058 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3059 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 476 |
3060 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3061 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3062 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3063 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
3064 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3065 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 481 |
3066 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3067 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3068 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3069 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
3070 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3071 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 486 |
3072 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3073 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3074 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3075 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
3076 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3077 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 491 |
3078 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3079 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3080 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3081 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
3082 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3083 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 496 |
3084 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3085 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3086 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3087 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
3088 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3089 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 501 |
3090 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3091 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3092 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3093 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
3094 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3095 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 506 |
3096 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3097 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3098 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3099 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
3100 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3101 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 511 |
3102 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3103 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3104 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3105 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
3106 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3107 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 516 |
3108 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3109 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3110 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3111 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
3112 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3113 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 521 |
3114 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3115 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3116 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3117 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
3118 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3119 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 526 |
3120 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3121 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3122 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3123 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
3124 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3125 | | // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 531 |
3126 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3127 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3128 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3129 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
3130 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3131 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8) - 536 |
3132 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3133 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3134 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3135 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
3136 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3137 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0) - 541 |
3138 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3139 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3140 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3141 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
3142 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3143 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9) - 546 |
3144 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3145 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3146 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3147 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
3148 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3149 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1) - 551 |
3150 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3151 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3152 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3153 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
3154 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3155 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10) - 556 |
3156 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3157 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3158 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3159 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
3160 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3161 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2) - 561 |
3162 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3163 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3164 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3165 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
3166 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3167 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11) - 566 |
3168 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3169 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3170 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3171 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
3172 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3173 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3) - 571 |
3174 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3175 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3176 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3177 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
3178 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3179 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12) - 576 |
3180 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3181 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3182 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3183 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
3184 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3185 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4) - 581 |
3186 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3187 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3188 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3189 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
3190 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3191 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13) - 586 |
3192 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3193 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3194 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3195 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
3196 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3197 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5) - 591 |
3198 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3199 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3200 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3201 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
3202 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3203 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14) - 596 |
3204 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3205 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3206 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3207 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
3208 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3209 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6) - 601 |
3210 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3211 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3212 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3213 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
3214 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3215 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15) - 606 |
3216 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3217 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3218 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3219 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
3220 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3221 | | // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7) - 611 |
3222 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3223 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3224 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3225 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
3226 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3227 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 616 |
3228 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3229 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3230 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3231 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
3232 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3233 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 621 |
3234 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3235 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3236 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3237 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
3238 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3239 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 626 |
3240 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3241 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3242 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3243 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
3244 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3245 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 631 |
3246 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3247 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3248 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3249 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
3250 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3251 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 636 |
3252 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3253 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3254 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3255 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
3256 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3257 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 641 |
3258 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3259 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3260 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3261 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
3262 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3263 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 646 |
3264 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3265 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3266 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3267 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
3268 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3269 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 651 |
3270 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3271 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3272 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3273 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
3274 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3275 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 656 |
3276 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3277 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3278 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3279 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
3280 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3281 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 661 |
3282 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3283 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3284 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3285 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
3286 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3287 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 666 |
3288 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3289 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3290 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3291 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
3292 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3293 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 671 |
3294 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3295 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3296 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3297 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
3298 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3299 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 676 |
3300 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3301 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3302 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3303 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
3304 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3305 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 681 |
3306 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3307 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3308 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3309 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
3310 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3311 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 686 |
3312 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3313 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3314 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3315 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
3316 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3317 | | // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 691 |
3318 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3319 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3320 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3321 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
3322 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3323 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8) - 696 |
3324 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3325 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3326 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3327 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
3328 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3329 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0) - 701 |
3330 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3331 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3332 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3333 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
3334 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3335 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9) - 706 |
3336 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3337 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3338 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3339 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
3340 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3341 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1) - 711 |
3342 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3343 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3344 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3345 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
3346 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3347 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10) - 716 |
3348 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3349 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3350 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3351 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
3352 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3353 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2) - 721 |
3354 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3355 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3356 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3357 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
3358 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3359 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11) - 726 |
3360 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3361 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3362 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3363 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
3364 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3365 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3) - 731 |
3366 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3367 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3368 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3369 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
3370 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3371 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12) - 736 |
3372 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3373 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3374 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3375 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
3376 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3377 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4) - 741 |
3378 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3379 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3380 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3381 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
3382 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3383 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13) - 746 |
3384 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3385 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3386 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3387 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
3388 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3389 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5) - 751 |
3390 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3391 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3392 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3393 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
3394 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3395 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14) - 756 |
3396 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3397 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3398 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3399 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
3400 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3401 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6) - 761 |
3402 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3403 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3404 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3405 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
3406 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3407 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15) - 766 |
3408 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3409 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3410 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3411 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
3412 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3413 | | // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7) - 771 |
3414 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3415 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3416 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3417 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
3418 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3419 | | // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 1) - 776 |
3420 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3421 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3422 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3423 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3424 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
3425 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3426 | | // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 2) - 782 |
3427 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3428 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3429 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3430 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3431 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
3432 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3433 | | // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 3) - 788 |
3434 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3435 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3436 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3437 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3438 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
3439 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3440 | | // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 5) - 794 |
3441 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3442 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3443 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3444 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3445 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
3446 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3447 | | // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 6) - 800 |
3448 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3449 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3450 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3451 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3452 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
3453 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3454 | | // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 7) - 806 |
3455 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3456 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3457 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
3458 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3459 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
3460 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3461 | | // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 1) - 812 |
3462 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3463 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3464 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3465 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3466 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
3467 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3468 | | // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 2) - 818 |
3469 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3470 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3471 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3472 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3473 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
3474 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3475 | | // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 3) - 824 |
3476 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3477 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3478 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3479 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3480 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
3481 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3482 | | // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 5) - 830 |
3483 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3484 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3485 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3486 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3487 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
3488 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3489 | | // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 6) - 836 |
3490 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3491 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3492 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3493 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3494 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
3495 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3496 | | // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 7) - 842 |
3497 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3498 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3499 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
3500 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3501 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
3502 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3503 | | // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 1) - 848 |
3504 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3505 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3506 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3507 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3508 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
3509 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3510 | | // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 2) - 854 |
3511 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3512 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3513 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3514 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3515 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
3516 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3517 | | // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 3) - 860 |
3518 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3519 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3520 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3521 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3522 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
3523 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3524 | | // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 5) - 866 |
3525 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3526 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3527 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3528 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3529 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
3530 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3531 | | // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 6) - 872 |
3532 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3533 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3534 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3535 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3536 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
3537 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3538 | | // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 7) - 878 |
3539 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3540 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3541 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3542 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3543 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
3544 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3545 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 884 |
3546 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3547 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3548 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3549 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
3550 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3551 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 889 |
3552 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3553 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3554 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3555 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
3556 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3557 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 894 |
3558 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3559 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3560 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3561 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
3562 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3563 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 899 |
3564 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3565 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3566 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3567 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
3568 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3569 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 904 |
3570 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3571 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3572 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3573 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
3574 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3575 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 909 |
3576 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3577 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3578 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3579 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
3580 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3581 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 914 |
3582 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3583 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3584 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3585 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
3586 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3587 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 919 |
3588 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3589 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3590 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3591 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
3592 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3593 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 924 |
3594 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3595 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3596 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3597 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
3598 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3599 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 929 |
3600 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3601 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3602 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3603 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
3604 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3605 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 934 |
3606 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3607 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3608 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3609 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
3610 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3611 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 939 |
3612 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3613 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3614 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3615 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
3616 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3617 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 944 |
3618 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3619 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3620 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3621 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
3622 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3623 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 949 |
3624 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3625 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3626 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3627 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
3628 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3629 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 954 |
3630 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3631 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3632 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3633 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
3634 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3635 | | // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 959 |
3636 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3637 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3638 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3639 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
3640 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3641 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8) - 964 |
3642 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3643 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3644 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3645 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
3646 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3647 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0) - 969 |
3648 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3649 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3650 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3651 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
3652 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3653 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9) - 974 |
3654 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3655 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3656 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3657 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
3658 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3659 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1) - 979 |
3660 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3661 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3662 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3663 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
3664 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3665 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10) - 984 |
3666 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3667 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3668 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3669 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
3670 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3671 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2) - 989 |
3672 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3673 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3674 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3675 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
3676 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3677 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11) - 994 |
3678 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3679 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3680 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3681 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
3682 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3683 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3) - 999 |
3684 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3685 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3686 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3687 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
3688 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3689 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12) - 1004 |
3690 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3691 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3692 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3693 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
3694 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3695 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4) - 1009 |
3696 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3697 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3698 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3699 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
3700 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3701 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13) - 1014 |
3702 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3703 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3704 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3705 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
3706 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3707 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5) - 1019 |
3708 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3709 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3710 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3711 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
3712 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3713 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14) - 1024 |
3714 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3715 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3716 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3717 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
3718 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3719 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6) - 1029 |
3720 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3721 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3722 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3723 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
3724 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3725 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15) - 1034 |
3726 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3727 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3728 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3729 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
3730 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3731 | | // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7) - 1039 |
3732 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3733 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
3734 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3735 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
3736 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3737 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 1044 |
3738 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3739 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3740 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3741 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
3742 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3743 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 1049 |
3744 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3745 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3746 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3747 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
3748 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3749 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 1054 |
3750 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3751 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3752 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3753 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
3754 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3755 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 1059 |
3756 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3757 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3758 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3759 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
3760 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3761 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 1064 |
3762 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3763 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3764 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3765 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
3766 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3767 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 1069 |
3768 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3769 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3770 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3771 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
3772 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3773 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 1074 |
3774 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3775 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3776 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3777 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
3778 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3779 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 1079 |
3780 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3781 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3782 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3783 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
3784 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3785 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 1084 |
3786 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3787 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3788 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3789 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
3790 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3791 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 1089 |
3792 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3793 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3794 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3795 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
3796 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3797 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 1094 |
3798 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3799 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3800 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3801 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
3802 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3803 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 1099 |
3804 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3805 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3806 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3807 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
3808 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3809 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 1104 |
3810 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3811 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3812 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3813 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
3814 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3815 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 1109 |
3816 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3817 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3818 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3819 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
3820 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3821 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1114 |
3822 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3823 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3824 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3825 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
3826 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3827 | | // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1119 |
3828 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3829 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3830 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3831 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
3832 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3833 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1124 |
3834 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3835 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3836 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3837 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
3838 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3839 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1129 |
3840 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3841 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3842 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3843 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
3844 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3845 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1134 |
3846 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3847 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3848 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3849 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
3850 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3851 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1139 |
3852 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3853 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3854 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3855 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
3856 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3857 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1144 |
3858 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3859 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3860 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3861 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
3862 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3863 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1149 |
3864 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3865 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3866 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3867 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
3868 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3869 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1154 |
3870 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3871 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3872 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3873 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
3874 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3875 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1159 |
3876 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3877 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3878 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3879 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
3880 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3881 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1164 |
3882 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3883 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3884 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3885 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
3886 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3887 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1169 |
3888 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3889 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3890 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3891 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
3892 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3893 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1174 |
3894 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3895 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3896 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3897 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
3898 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3899 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1179 |
3900 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3901 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3902 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3903 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
3904 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3905 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1184 |
3906 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3907 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3908 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3909 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
3910 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3911 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1189 |
3912 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3913 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3914 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3915 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
3916 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3917 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1194 |
3918 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3919 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3920 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3921 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
3922 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3923 | | // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1199 |
3924 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3925 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3926 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3927 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
3928 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3929 | | // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 1) - 1204 |
3930 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3931 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3932 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3933 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3934 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
3935 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3936 | | // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 2) - 1210 |
3937 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3938 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3939 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3940 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3941 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
3942 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3943 | | // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 3) - 1216 |
3944 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3945 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3946 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3947 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3948 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
3949 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3950 | | // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 5) - 1222 |
3951 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3952 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3953 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3954 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3955 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
3956 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3957 | | // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 6) - 1228 |
3958 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3959 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3960 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3961 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3962 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
3963 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3964 | | // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 7) - 1234 |
3965 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3966 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3967 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3968 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3969 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
3970 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3971 | | // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 1) - 1240 |
3972 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3973 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3974 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3975 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3976 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
3977 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3978 | | // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 2) - 1246 |
3979 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3980 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3981 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3982 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3983 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
3984 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3985 | | // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 3) - 1252 |
3986 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3987 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3988 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3989 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3990 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
3991 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3992 | | // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 5) - 1258 |
3993 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3994 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
3995 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
3996 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
3997 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
3998 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
3999 | | // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 6) - 1264 |
4000 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4001 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
4002 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4003 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4004 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
4005 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4006 | | // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 7) - 1270 |
4007 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4008 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_I64RegsRegClassID}, |
4009 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4010 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4011 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
4012 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4013 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8) - 1276 |
4014 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4015 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4016 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4017 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4018 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4019 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0) - 1281 |
4020 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4021 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4022 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4023 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
4024 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4025 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9) - 1286 |
4026 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4027 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4028 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4029 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
4030 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4031 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1) - 1291 |
4032 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4033 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4034 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4035 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
4036 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4037 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10) - 1296 |
4038 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4039 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4040 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4041 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
4042 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4043 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2) - 1301 |
4044 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4045 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4046 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4047 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
4048 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4049 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11) - 1306 |
4050 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4051 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4052 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4053 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
4054 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4055 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3) - 1311 |
4056 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4057 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4058 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4059 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
4060 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4061 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12) - 1316 |
4062 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4063 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4064 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4065 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
4066 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4067 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4) - 1321 |
4068 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4069 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4070 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4071 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
4072 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4073 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13) - 1326 |
4074 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4075 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4076 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4077 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
4078 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4079 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5) - 1331 |
4080 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4081 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4082 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4083 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
4084 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4085 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14) - 1336 |
4086 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4087 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4088 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4089 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
4090 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4091 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6) - 1341 |
4092 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4093 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4094 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4095 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
4096 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4097 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15) - 1346 |
4098 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4099 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4100 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4101 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
4102 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4103 | | // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7) - 1351 |
4104 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4105 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4106 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4107 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
4108 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4109 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1356 |
4110 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4111 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4112 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4113 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4114 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4115 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1361 |
4116 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4117 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4118 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4119 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
4120 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4121 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1366 |
4122 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4123 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4124 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4125 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
4126 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4127 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1371 |
4128 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4129 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4130 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4131 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
4132 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4133 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1376 |
4134 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4135 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4136 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4137 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
4138 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4139 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1381 |
4140 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4141 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4142 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4143 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
4144 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4145 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1386 |
4146 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4147 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4148 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4149 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
4150 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4151 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1391 |
4152 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4153 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4154 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4155 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
4156 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4157 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1396 |
4158 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4159 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4160 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4161 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
4162 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4163 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1401 |
4164 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4165 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4166 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4167 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
4168 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4169 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1406 |
4170 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4171 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4172 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4173 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
4174 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4175 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1411 |
4176 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4177 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4178 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4179 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
4180 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4181 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1416 |
4182 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4183 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4184 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4185 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
4186 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4187 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1421 |
4188 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4189 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4190 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4191 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
4192 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4193 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1426 |
4194 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4195 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4196 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4197 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
4198 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4199 | | // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1431 |
4200 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4201 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4202 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4203 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
4204 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4205 | | // (ORCCrr G0, IntRegs:$rs2, G0) - 1436 |
4206 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4207 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4208 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4209 | | // (ORri IntRegs:$rd, G0, simm13Op:$simm13) - 1439 |
4210 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4211 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4212 | | // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) - 1441 |
4213 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4214 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4215 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4216 | | // (RESTORErr G0, G0, G0) - 1444 |
4217 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4218 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4219 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4220 | | // (RET 8) - 1447 |
4221 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4222 | | // (RETL 8) - 1448 |
4223 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4224 | | // (SAVErr G0, G0, G0) - 1449 |
4225 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4226 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4227 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4228 | | // (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm) - 1452 |
4229 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4230 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4231 | | // (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2) - 1454 |
4232 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4233 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4234 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4235 | | // (TICCri G0, i32imm:$imm, 8) - 1457 |
4236 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4237 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4238 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4239 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4240 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1461 |
4241 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4242 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4243 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4244 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4245 | | // (TICCri G0, i32imm:$imm, 0) - 1465 |
4246 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4247 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4248 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
4249 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4250 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1469 |
4251 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4252 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4253 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
4254 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4255 | | // (TICCri G0, i32imm:$imm, 9) - 1473 |
4256 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4257 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4258 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
4259 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4260 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1477 |
4261 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4262 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4263 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
4264 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4265 | | // (TICCri G0, i32imm:$imm, 1) - 1481 |
4266 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4267 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4268 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
4269 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4270 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1485 |
4271 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4272 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4273 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
4274 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4275 | | // (TICCri G0, i32imm:$imm, 10) - 1489 |
4276 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4277 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4278 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
4279 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4280 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1493 |
4281 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4282 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4283 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
4284 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4285 | | // (TICCri G0, i32imm:$imm, 2) - 1497 |
4286 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4287 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4288 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
4289 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4290 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1501 |
4291 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4292 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4293 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
4294 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4295 | | // (TICCri G0, i32imm:$imm, 11) - 1505 |
4296 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4297 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4298 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
4299 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4300 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1509 |
4301 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4302 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4303 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
4304 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4305 | | // (TICCri G0, i32imm:$imm, 3) - 1513 |
4306 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4307 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4308 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
4309 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4310 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1517 |
4311 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4312 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4313 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
4314 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4315 | | // (TICCri G0, i32imm:$imm, 12) - 1521 |
4316 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4317 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4318 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
4319 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4320 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1525 |
4321 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4322 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4323 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
4324 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4325 | | // (TICCri G0, i32imm:$imm, 4) - 1529 |
4326 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4327 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4328 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
4329 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4330 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1533 |
4331 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4332 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4333 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
4334 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4335 | | // (TICCri G0, i32imm:$imm, 13) - 1537 |
4336 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4337 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4338 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
4339 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4340 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1541 |
4341 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4342 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4343 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
4344 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4345 | | // (TICCri G0, i32imm:$imm, 5) - 1545 |
4346 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4347 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4348 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
4349 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4350 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1549 |
4351 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4352 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4353 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
4354 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4355 | | // (TICCri G0, i32imm:$imm, 14) - 1553 |
4356 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4357 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4358 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
4359 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4360 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1557 |
4361 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4362 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4363 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
4364 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4365 | | // (TICCri G0, i32imm:$imm, 6) - 1561 |
4366 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4367 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4368 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
4369 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4370 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1565 |
4371 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4372 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4373 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
4374 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4375 | | // (TICCri G0, i32imm:$imm, 15) - 1569 |
4376 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4377 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4378 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
4379 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4380 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 1573 |
4381 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4382 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4383 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
4384 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4385 | | // (TICCri G0, i32imm:$imm, 7) - 1577 |
4386 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4387 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4388 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
4389 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4390 | | // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 1581 |
4391 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4392 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4393 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
4394 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4395 | | // (TICCrr G0, IntRegs:$rs2, 8) - 1585 |
4396 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4397 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4398 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4399 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4400 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1589 |
4401 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4402 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4403 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4404 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4405 | | // (TICCrr G0, IntRegs:$rs2, 0) - 1593 |
4406 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4407 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4408 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
4409 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4410 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1597 |
4411 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4412 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4413 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
4414 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4415 | | // (TICCrr G0, IntRegs:$rs2, 9) - 1601 |
4416 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4417 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4418 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
4419 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4420 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1605 |
4421 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4422 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4423 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
4424 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4425 | | // (TICCrr G0, IntRegs:$rs2, 1) - 1609 |
4426 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4427 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4428 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
4429 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4430 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1613 |
4431 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4432 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4433 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
4434 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4435 | | // (TICCrr G0, IntRegs:$rs2, 10) - 1617 |
4436 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4437 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4438 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
4439 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4440 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1621 |
4441 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4442 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4443 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
4444 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4445 | | // (TICCrr G0, IntRegs:$rs2, 2) - 1625 |
4446 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4447 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4448 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
4449 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4450 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1629 |
4451 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4452 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4453 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
4454 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4455 | | // (TICCrr G0, IntRegs:$rs2, 11) - 1633 |
4456 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4457 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4458 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
4459 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4460 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1637 |
4461 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4462 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4463 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
4464 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4465 | | // (TICCrr G0, IntRegs:$rs2, 3) - 1641 |
4466 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4467 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4468 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
4469 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4470 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1645 |
4471 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4472 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4473 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
4474 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4475 | | // (TICCrr G0, IntRegs:$rs2, 12) - 1649 |
4476 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4477 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4478 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
4479 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4480 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1653 |
4481 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4482 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4483 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
4484 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4485 | | // (TICCrr G0, IntRegs:$rs2, 4) - 1657 |
4486 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4487 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4488 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
4489 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4490 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1661 |
4491 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4492 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4493 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
4494 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4495 | | // (TICCrr G0, IntRegs:$rs2, 13) - 1665 |
4496 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4497 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4498 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
4499 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4500 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1669 |
4501 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4502 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4503 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
4504 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4505 | | // (TICCrr G0, IntRegs:$rs2, 5) - 1673 |
4506 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4507 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4508 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
4509 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4510 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1677 |
4511 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4512 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4513 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
4514 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4515 | | // (TICCrr G0, IntRegs:$rs2, 14) - 1681 |
4516 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4517 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4518 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
4519 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4520 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1685 |
4521 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4522 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4523 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
4524 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4525 | | // (TICCrr G0, IntRegs:$rs2, 6) - 1689 |
4526 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4527 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4528 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
4529 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4530 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1693 |
4531 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4532 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4533 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
4534 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4535 | | // (TICCrr G0, IntRegs:$rs2, 15) - 1697 |
4536 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4537 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4538 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
4539 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4540 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1701 |
4541 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4542 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4543 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
4544 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4545 | | // (TICCrr G0, IntRegs:$rs2, 7) - 1705 |
4546 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4547 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4548 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
4549 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4550 | | // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1709 |
4551 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4552 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4553 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
4554 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4555 | | // (TRAPri G0, i32imm:$imm, 8) - 1713 |
4556 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4557 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4558 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4559 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 8) - 1716 |
4560 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4561 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4562 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4563 | | // (TRAPri G0, i32imm:$imm, 0) - 1719 |
4564 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4565 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4566 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
4567 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 0) - 1722 |
4568 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4569 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4570 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
4571 | | // (TRAPri G0, i32imm:$imm, 9) - 1725 |
4572 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4573 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4574 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
4575 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 9) - 1728 |
4576 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4577 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4578 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
4579 | | // (TRAPri G0, i32imm:$imm, 1) - 1731 |
4580 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4581 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4582 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
4583 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 1) - 1734 |
4584 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4585 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4586 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
4587 | | // (TRAPri G0, i32imm:$imm, 10) - 1737 |
4588 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4589 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4590 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
4591 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 10) - 1740 |
4592 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4593 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4594 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
4595 | | // (TRAPri G0, i32imm:$imm, 2) - 1743 |
4596 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4597 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4598 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
4599 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 2) - 1746 |
4600 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4601 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4602 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
4603 | | // (TRAPri G0, i32imm:$imm, 11) - 1749 |
4604 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4605 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4606 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
4607 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 11) - 1752 |
4608 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4609 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4610 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
4611 | | // (TRAPri G0, i32imm:$imm, 3) - 1755 |
4612 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4613 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4614 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
4615 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 3) - 1758 |
4616 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4617 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4618 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
4619 | | // (TRAPri G0, i32imm:$imm, 12) - 1761 |
4620 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4621 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4622 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
4623 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 12) - 1764 |
4624 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4625 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4626 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
4627 | | // (TRAPri G0, i32imm:$imm, 4) - 1767 |
4628 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4629 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4630 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
4631 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 4) - 1770 |
4632 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4633 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4634 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
4635 | | // (TRAPri G0, i32imm:$imm, 13) - 1773 |
4636 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4637 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4638 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
4639 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 13) - 1776 |
4640 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4641 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4642 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
4643 | | // (TRAPri G0, i32imm:$imm, 5) - 1779 |
4644 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4645 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4646 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
4647 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 5) - 1782 |
4648 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4649 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4650 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
4651 | | // (TRAPri G0, i32imm:$imm, 14) - 1785 |
4652 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4653 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4654 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
4655 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 14) - 1788 |
4656 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4657 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4658 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
4659 | | // (TRAPri G0, i32imm:$imm, 6) - 1791 |
4660 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4661 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4662 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
4663 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 6) - 1794 |
4664 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4665 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4666 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
4667 | | // (TRAPri G0, i32imm:$imm, 15) - 1797 |
4668 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4669 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4670 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
4671 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 15) - 1800 |
4672 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4673 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4674 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
4675 | | // (TRAPri G0, i32imm:$imm, 7) - 1803 |
4676 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4677 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4678 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
4679 | | // (TRAPri IntRegs:$rs1, i32imm:$imm, 7) - 1806 |
4680 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4681 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4682 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
4683 | | // (TRAPrr G0, IntRegs:$rs1, 8) - 1809 |
4684 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4685 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4686 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4687 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1812 |
4688 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4689 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4690 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4691 | | // (TRAPrr G0, IntRegs:$rs1, 0) - 1815 |
4692 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4693 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4694 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
4695 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1818 |
4696 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4697 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4698 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
4699 | | // (TRAPrr G0, IntRegs:$rs1, 9) - 1821 |
4700 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4701 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4702 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
4703 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1824 |
4704 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4705 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4706 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
4707 | | // (TRAPrr G0, IntRegs:$rs1, 1) - 1827 |
4708 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4709 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4710 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
4711 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1830 |
4712 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4713 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4714 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
4715 | | // (TRAPrr G0, IntRegs:$rs1, 10) - 1833 |
4716 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4717 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4718 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
4719 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1836 |
4720 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4721 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4722 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
4723 | | // (TRAPrr G0, IntRegs:$rs1, 2) - 1839 |
4724 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4725 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4726 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
4727 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1842 |
4728 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4729 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4730 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
4731 | | // (TRAPrr G0, IntRegs:$rs1, 11) - 1845 |
4732 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4733 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4734 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
4735 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1848 |
4736 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4737 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4738 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
4739 | | // (TRAPrr G0, IntRegs:$rs1, 3) - 1851 |
4740 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4741 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4742 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
4743 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1854 |
4744 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4745 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4746 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
4747 | | // (TRAPrr G0, IntRegs:$rs1, 12) - 1857 |
4748 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4749 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4750 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
4751 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1860 |
4752 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4753 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4754 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
4755 | | // (TRAPrr G0, IntRegs:$rs1, 4) - 1863 |
4756 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4757 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4758 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
4759 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1866 |
4760 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4761 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4762 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
4763 | | // (TRAPrr G0, IntRegs:$rs1, 13) - 1869 |
4764 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4765 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4766 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
4767 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1872 |
4768 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4769 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4770 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
4771 | | // (TRAPrr G0, IntRegs:$rs1, 5) - 1875 |
4772 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4773 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4774 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
4775 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1878 |
4776 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4777 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4778 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
4779 | | // (TRAPrr G0, IntRegs:$rs1, 14) - 1881 |
4780 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4781 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4782 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
4783 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1884 |
4784 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4785 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4786 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
4787 | | // (TRAPrr G0, IntRegs:$rs1, 6) - 1887 |
4788 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4789 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4790 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
4791 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1890 |
4792 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4793 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4794 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
4795 | | // (TRAPrr G0, IntRegs:$rs1, 15) - 1893 |
4796 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4797 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4798 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
4799 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1896 |
4800 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4801 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4802 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
4803 | | // (TRAPrr G0, IntRegs:$rs1, 7) - 1899 |
4804 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4805 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4806 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
4807 | | // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1902 |
4808 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4809 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4810 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
4811 | | // (TXCCri G0, i32imm:$imm, 8) - 1905 |
4812 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4813 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4814 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4815 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4816 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 1909 |
4817 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4818 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4819 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4820 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4821 | | // (TXCCri G0, i32imm:$imm, 0) - 1913 |
4822 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4823 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4824 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
4825 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4826 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 1917 |
4827 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4828 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4829 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
4830 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4831 | | // (TXCCri G0, i32imm:$imm, 9) - 1921 |
4832 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4833 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4834 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
4835 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4836 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 1925 |
4837 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4838 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4839 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
4840 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4841 | | // (TXCCri G0, i32imm:$imm, 1) - 1929 |
4842 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4843 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4844 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
4845 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4846 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 1933 |
4847 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4848 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4849 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
4850 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4851 | | // (TXCCri G0, i32imm:$imm, 10) - 1937 |
4852 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4853 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4854 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
4855 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4856 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 1941 |
4857 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4858 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4859 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
4860 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4861 | | // (TXCCri G0, i32imm:$imm, 2) - 1945 |
4862 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4863 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4864 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
4865 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4866 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 1949 |
4867 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4868 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4869 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
4870 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4871 | | // (TXCCri G0, i32imm:$imm, 11) - 1953 |
4872 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4873 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4874 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
4875 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4876 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 1957 |
4877 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4878 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4879 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
4880 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4881 | | // (TXCCri G0, i32imm:$imm, 3) - 1961 |
4882 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4883 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4884 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
4885 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4886 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 1965 |
4887 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4888 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4889 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
4890 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4891 | | // (TXCCri G0, i32imm:$imm, 12) - 1969 |
4892 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4893 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4894 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
4895 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4896 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 1973 |
4897 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4898 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4899 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
4900 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4901 | | // (TXCCri G0, i32imm:$imm, 4) - 1977 |
4902 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4903 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4904 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
4905 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4906 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 1981 |
4907 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4908 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4909 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
4910 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4911 | | // (TXCCri G0, i32imm:$imm, 13) - 1985 |
4912 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4913 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4914 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
4915 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4916 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 1989 |
4917 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4918 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4919 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
4920 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4921 | | // (TXCCri G0, i32imm:$imm, 5) - 1993 |
4922 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4923 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4924 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
4925 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4926 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 1997 |
4927 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4928 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4929 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
4930 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4931 | | // (TXCCri G0, i32imm:$imm, 14) - 2001 |
4932 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4933 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4934 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
4935 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4936 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 2005 |
4937 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4938 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4939 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
4940 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4941 | | // (TXCCri G0, i32imm:$imm, 6) - 2009 |
4942 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4943 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4944 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
4945 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4946 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 2013 |
4947 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4948 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4949 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
4950 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4951 | | // (TXCCri G0, i32imm:$imm, 15) - 2017 |
4952 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4953 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4954 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
4955 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4956 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 2021 |
4957 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4958 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4959 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
4960 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4961 | | // (TXCCri G0, i32imm:$imm, 7) - 2025 |
4962 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4963 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4964 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
4965 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4966 | | // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 2029 |
4967 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4968 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
4969 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
4970 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4971 | | // (TXCCrr G0, IntRegs:$rs2, 8) - 2033 |
4972 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4973 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4974 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4975 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4976 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 2037 |
4977 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4978 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4979 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
4980 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4981 | | // (TXCCrr G0, IntRegs:$rs2, 0) - 2041 |
4982 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4983 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4984 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
4985 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4986 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 2045 |
4987 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4988 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4989 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
4990 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4991 | | // (TXCCrr G0, IntRegs:$rs2, 9) - 2049 |
4992 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
4993 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4994 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
4995 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
4996 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 2053 |
4997 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4998 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
4999 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
5000 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5001 | | // (TXCCrr G0, IntRegs:$rs2, 1) - 2057 |
5002 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
5003 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5004 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
5005 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5006 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 2061 |
5007 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5008 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5009 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
5010 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5011 | | // (TXCCrr G0, IntRegs:$rs2, 10) - 2065 |
5012 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
5013 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5014 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
5015 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5016 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 2069 |
5017 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5018 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5019 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
5020 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5021 | | // (TXCCrr G0, IntRegs:$rs2, 2) - 2073 |
5022 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
5023 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5024 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
5025 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5026 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 2077 |
5027 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5028 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5029 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
5030 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5031 | | // (TXCCrr G0, IntRegs:$rs2, 11) - 2081 |
5032 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
5033 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5034 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
5035 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5036 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 2085 |
5037 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5038 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5039 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
5040 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5041 | | // (TXCCrr G0, IntRegs:$rs2, 3) - 2089 |
5042 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
5043 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5044 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
5045 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5046 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 2093 |
5047 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5048 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5049 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
5050 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5051 | | // (TXCCrr G0, IntRegs:$rs2, 12) - 2097 |
5052 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
5053 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5054 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
5055 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5056 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 2101 |
5057 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5058 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5059 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
5060 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5061 | | // (TXCCrr G0, IntRegs:$rs2, 4) - 2105 |
5062 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
5063 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5064 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
5065 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5066 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 2109 |
5067 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5068 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5069 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
5070 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5071 | | // (TXCCrr G0, IntRegs:$rs2, 13) - 2113 |
5072 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
5073 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5074 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
5075 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5076 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 2117 |
5077 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5078 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5079 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
5080 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5081 | | // (TXCCrr G0, IntRegs:$rs2, 5) - 2121 |
5082 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
5083 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5084 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
5085 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5086 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 2125 |
5087 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5088 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5089 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
5090 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5091 | | // (TXCCrr G0, IntRegs:$rs2, 14) - 2129 |
5092 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
5093 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5094 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
5095 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5096 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 2133 |
5097 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5098 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5099 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
5100 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5101 | | // (TXCCrr G0, IntRegs:$rs2, 6) - 2137 |
5102 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
5103 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5104 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
5105 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5106 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 2141 |
5107 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5108 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5109 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
5110 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5111 | | // (TXCCrr G0, IntRegs:$rs2, 15) - 2145 |
5112 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
5113 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5114 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
5115 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5116 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 2149 |
5117 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5118 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5119 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
5120 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5121 | | // (TXCCrr G0, IntRegs:$rs2, 7) - 2153 |
5122 | 47.5k | {AliasPatternCond_K_Reg, Sparc_G0}, |
5123 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5124 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
5125 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5126 | | // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2157 |
5127 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5128 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5129 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
5130 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5131 | | // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 2161 |
5132 | 47.5k | {AliasPatternCond_K_Reg, Sparc_FCC0}, |
5133 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5134 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5135 | | // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 2164 |
5136 | 47.5k | {AliasPatternCond_K_Reg, Sparc_FCC0}, |
5137 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5138 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5139 | | // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 2167 |
5140 | 47.5k | {AliasPatternCond_K_Reg, Sparc_FCC0}, |
5141 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5142 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5143 | | // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) - 2170 |
5144 | 47.5k | {AliasPatternCond_K_Reg, Sparc_FCC0}, |
5145 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5146 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5147 | | // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 2173 |
5148 | 47.5k | {AliasPatternCond_K_Reg, Sparc_FCC0}, |
5149 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5150 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5151 | | // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) - 2176 |
5152 | 47.5k | {AliasPatternCond_K_Reg, Sparc_FCC0}, |
5153 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5154 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5155 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) - 2179 |
5156 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5157 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5158 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5159 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5160 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
5161 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5162 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) - 2185 |
5163 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5164 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5165 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5166 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5167 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
5168 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5169 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) - 2191 |
5170 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5171 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5172 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5173 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5174 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
5175 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5176 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) - 2197 |
5177 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5178 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5179 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5180 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5181 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
5182 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5183 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) - 2203 |
5184 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5185 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5186 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5187 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5188 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
5189 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5190 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) - 2209 |
5191 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5192 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5193 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5194 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5195 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
5196 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5197 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) - 2215 |
5198 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5199 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5200 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5201 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5202 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
5203 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5204 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) - 2221 |
5205 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5206 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5207 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5208 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5209 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
5210 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5211 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) - 2227 |
5212 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5213 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5214 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5215 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5216 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
5217 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5218 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) - 2233 |
5219 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5220 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5221 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5222 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5223 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
5224 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5225 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) - 2239 |
5226 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5227 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5228 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5229 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5230 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
5231 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5232 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) - 2245 |
5233 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5234 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5235 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5236 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5237 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
5238 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5239 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) - 2251 |
5240 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5241 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5242 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5243 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5244 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
5245 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5246 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) - 2257 |
5247 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5248 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5249 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5250 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5251 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
5252 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5253 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) - 2263 |
5254 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5255 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5256 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5257 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5258 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
5259 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5260 | | // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) - 2269 |
5261 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5262 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5263 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_DFPRegsRegClassID}, |
5264 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5265 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
5266 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5267 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) - 2275 |
5268 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5269 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5270 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5271 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5272 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
5273 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5274 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) - 2281 |
5275 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5276 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5277 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5278 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5279 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
5280 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5281 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) - 2287 |
5282 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5283 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5284 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5285 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5286 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
5287 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5288 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) - 2293 |
5289 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5290 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5291 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5292 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5293 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
5294 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5295 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) - 2299 |
5296 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5297 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5298 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5299 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5300 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
5301 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5302 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) - 2305 |
5303 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5304 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5305 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5306 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5307 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
5308 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5309 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) - 2311 |
5310 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5311 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5312 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5313 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5314 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
5315 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5316 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) - 2317 |
5317 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5318 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5319 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5320 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5321 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
5322 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5323 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) - 2323 |
5324 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5325 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5326 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5327 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5328 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
5329 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5330 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) - 2329 |
5331 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5332 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5333 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5334 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5335 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
5336 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5337 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) - 2335 |
5338 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5339 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5340 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5341 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5342 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
5343 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5344 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) - 2341 |
5345 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5346 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5347 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5348 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5349 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
5350 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5351 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) - 2347 |
5352 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5353 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5354 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5355 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5356 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
5357 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5358 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) - 2353 |
5359 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5360 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5361 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5362 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5363 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
5364 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5365 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) - 2359 |
5366 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5367 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5368 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5369 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5370 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
5371 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5372 | | // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) - 2365 |
5373 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5374 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5375 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_QFPRegsRegClassID}, |
5376 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5377 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
5378 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5379 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) - 2371 |
5380 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5381 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5382 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5383 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5384 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
5385 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5386 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) - 2377 |
5387 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5388 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5389 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5390 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5391 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
5392 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5393 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) - 2383 |
5394 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5395 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5396 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5397 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5398 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
5399 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5400 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) - 2389 |
5401 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5402 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5403 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5404 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5405 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
5406 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5407 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) - 2395 |
5408 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5409 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5410 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5411 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5412 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
5413 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5414 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) - 2401 |
5415 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5416 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5417 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5418 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5419 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
5420 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5421 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) - 2407 |
5422 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5423 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5424 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5425 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5426 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
5427 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5428 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) - 2413 |
5429 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5430 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5431 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5432 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5433 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
5434 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5435 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) - 2419 |
5436 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5437 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5438 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5439 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5440 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
5441 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5442 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) - 2425 |
5443 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5444 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5445 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5446 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5447 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
5448 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5449 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) - 2431 |
5450 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5451 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5452 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5453 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5454 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
5455 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5456 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) - 2437 |
5457 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5458 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5459 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5460 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5461 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
5462 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5463 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) - 2443 |
5464 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5465 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5466 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5467 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5468 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
5469 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5470 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) - 2449 |
5471 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5472 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5473 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5474 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5475 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
5476 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5477 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) - 2455 |
5478 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5479 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5480 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5481 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5482 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
5483 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5484 | | // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) - 2461 |
5485 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5486 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5487 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FPRegsRegClassID}, |
5488 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5489 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
5490 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5491 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) - 2467 |
5492 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5493 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5494 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5495 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5496 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
5497 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5498 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) - 2473 |
5499 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5500 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5501 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5502 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5503 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
5504 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5505 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) - 2479 |
5506 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5507 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5508 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5509 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5510 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
5511 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5512 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) - 2485 |
5513 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5514 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5515 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5516 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5517 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
5518 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5519 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) - 2491 |
5520 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5521 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5522 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5523 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5524 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
5525 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5526 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) - 2497 |
5527 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5528 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5529 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5530 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5531 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
5532 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5533 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) - 2503 |
5534 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5535 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5536 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5537 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5538 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
5539 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5540 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) - 2509 |
5541 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5542 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5543 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5544 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5545 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
5546 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5547 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) - 2515 |
5548 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5549 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5550 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5551 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5552 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
5553 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5554 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) - 2521 |
5555 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5556 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5557 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5558 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5559 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
5560 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5561 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) - 2527 |
5562 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5563 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5564 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5565 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5566 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
5567 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5568 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) - 2533 |
5569 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5570 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5571 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5572 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5573 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
5574 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5575 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) - 2539 |
5576 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5577 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5578 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5579 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5580 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
5581 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5582 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) - 2545 |
5583 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5584 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5585 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5586 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5587 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
5588 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5589 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) - 2551 |
5590 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5591 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5592 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5593 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5594 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
5595 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5596 | | // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) - 2557 |
5597 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5598 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5599 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5600 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5601 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
5602 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5603 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) - 2563 |
5604 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5605 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5606 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5607 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5608 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)8}, |
5609 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5610 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) - 2569 |
5611 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5612 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5613 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5614 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5615 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)0}, |
5616 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5617 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) - 2575 |
5618 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5619 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5620 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5621 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5622 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)7}, |
5623 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5624 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) - 2581 |
5625 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5626 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5627 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5628 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5629 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)6}, |
5630 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5631 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) - 2587 |
5632 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5633 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5634 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5635 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5636 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)5}, |
5637 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5638 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) - 2593 |
5639 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5640 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5641 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5642 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5643 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)4}, |
5644 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5645 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) - 2599 |
5646 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5647 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5648 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5649 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5650 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)3}, |
5651 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5652 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) - 2605 |
5653 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5654 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5655 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5656 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5657 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)2}, |
5658 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5659 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) - 2611 |
5660 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5661 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5662 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5663 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5664 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)1}, |
5665 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5666 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) - 2617 |
5667 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5668 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5669 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5670 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5671 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)9}, |
5672 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5673 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) - 2623 |
5674 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5675 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5676 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5677 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5678 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)10}, |
5679 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5680 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) - 2629 |
5681 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5682 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5683 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5684 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5685 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)11}, |
5686 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5687 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) - 2635 |
5688 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5689 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5690 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5691 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5692 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)12}, |
5693 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5694 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) - 2641 |
5695 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5696 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5697 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5698 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5699 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)13}, |
5700 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5701 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) - 2647 |
5702 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5703 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5704 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5705 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5706 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)14}, |
5707 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5708 | | // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) - 2653 |
5709 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5710 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_FCCRegsRegClassID}, |
5711 | 47.5k | {AliasPatternCond_K_RegClass, Sparc_IntRegsRegClassID}, |
5712 | 47.5k | {AliasPatternCond_K_Ignore, 0}, |
5713 | 47.5k | {AliasPatternCond_K_Imm, (uint32_t)15}, |
5714 | 47.5k | {AliasPatternCond_K_Feature, Sparc_FeatureV9}, |
5715 | 47.5k | {0}, }; |
5716 | | |
5717 | 47.5k | static const char AsmStrings[] = |
5718 | 47.5k | /* 0 */ "ba $\x01\0" |
5719 | 47.5k | /* 6 */ "bn $\x01\0" |
5720 | 47.5k | /* 12 */ "bne $\x01\0" |
5721 | 47.5k | /* 19 */ "be $\x01\0" |
5722 | 47.5k | /* 25 */ "bg $\x01\0" |
5723 | 47.5k | /* 31 */ "ble $\x01\0" |
5724 | 47.5k | /* 38 */ "bge $\x01\0" |
5725 | 47.5k | /* 45 */ "bl $\x01\0" |
5726 | 47.5k | /* 51 */ "bgu $\x01\0" |
5727 | 47.5k | /* 58 */ "bleu $\x01\0" |
5728 | 47.5k | /* 66 */ "bcc $\x01\0" |
5729 | 47.5k | /* 73 */ "bcs $\x01\0" |
5730 | 47.5k | /* 80 */ "bpos $\x01\0" |
5731 | 47.5k | /* 88 */ "bneg $\x01\0" |
5732 | 47.5k | /* 96 */ "bvc $\x01\0" |
5733 | 47.5k | /* 103 */ "bvs $\x01\0" |
5734 | 47.5k | /* 110 */ "ba,a $\x01\0" |
5735 | 47.5k | /* 118 */ "bn,a $\x01\0" |
5736 | 47.5k | /* 126 */ "bne,a $\x01\0" |
5737 | 47.5k | /* 135 */ "be,a $\x01\0" |
5738 | 47.5k | /* 143 */ "bg,a $\x01\0" |
5739 | 47.5k | /* 151 */ "ble,a $\x01\0" |
5740 | 47.5k | /* 160 */ "bge,a $\x01\0" |
5741 | 47.5k | /* 169 */ "bl,a $\x01\0" |
5742 | 47.5k | /* 177 */ "bgu,a $\x01\0" |
5743 | 47.5k | /* 186 */ "bleu,a $\x01\0" |
5744 | 47.5k | /* 196 */ "bcc,a $\x01\0" |
5745 | 47.5k | /* 205 */ "bcs,a $\x01\0" |
5746 | 47.5k | /* 214 */ "bpos,a $\x01\0" |
5747 | 47.5k | /* 224 */ "bneg,a $\x01\0" |
5748 | 47.5k | /* 234 */ "bvc,a $\x01\0" |
5749 | 47.5k | /* 243 */ "bvs,a $\x01\0" |
5750 | 47.5k | /* 252 */ "fba,a,pn $\x03, $\x01\0" |
5751 | 47.5k | /* 268 */ "fbn,a,pn $\x03, $\x01\0" |
5752 | 47.5k | /* 284 */ "fbu,a,pn $\x03, $\x01\0" |
5753 | 47.5k | /* 300 */ "fbg,a,pn $\x03, $\x01\0" |
5754 | 47.5k | /* 316 */ "fbug,a,pn $\x03, $\x01\0" |
5755 | 47.5k | /* 333 */ "fbl,a,pn $\x03, $\x01\0" |
5756 | 47.5k | /* 349 */ "fbul,a,pn $\x03, $\x01\0" |
5757 | 47.5k | /* 366 */ "fblg,a,pn $\x03, $\x01\0" |
5758 | 47.5k | /* 383 */ "fbne,a,pn $\x03, $\x01\0" |
5759 | 47.5k | /* 400 */ "fbe,a,pn $\x03, $\x01\0" |
5760 | 47.5k | /* 416 */ "fbue,a,pn $\x03, $\x01\0" |
5761 | 47.5k | /* 433 */ "fbge,a,pn $\x03, $\x01\0" |
5762 | 47.5k | /* 450 */ "fbuge,a,pn $\x03, $\x01\0" |
5763 | 47.5k | /* 468 */ "fble,a,pn $\x03, $\x01\0" |
5764 | 47.5k | /* 485 */ "fbule,a,pn $\x03, $\x01\0" |
5765 | 47.5k | /* 503 */ "fbo,a,pn $\x03, $\x01\0" |
5766 | 47.5k | /* 519 */ "fba,pn $\x03, $\x01\0" |
5767 | 47.5k | /* 533 */ "fbn,pn $\x03, $\x01\0" |
5768 | 47.5k | /* 547 */ "fbu,pn $\x03, $\x01\0" |
5769 | 47.5k | /* 561 */ "fbg,pn $\x03, $\x01\0" |
5770 | 47.5k | /* 575 */ "fbug,pn $\x03, $\x01\0" |
5771 | 47.5k | /* 590 */ "fbl,pn $\x03, $\x01\0" |
5772 | 47.5k | /* 604 */ "fbul,pn $\x03, $\x01\0" |
5773 | 47.5k | /* 619 */ "fblg,pn $\x03, $\x01\0" |
5774 | 47.5k | /* 634 */ "fbne,pn $\x03, $\x01\0" |
5775 | 47.5k | /* 649 */ "fbe,pn $\x03, $\x01\0" |
5776 | 47.5k | /* 663 */ "fbue,pn $\x03, $\x01\0" |
5777 | 47.5k | /* 678 */ "fbge,pn $\x03, $\x01\0" |
5778 | 47.5k | /* 693 */ "fbuge,pn $\x03, $\x01\0" |
5779 | 47.5k | /* 709 */ "fble,pn $\x03, $\x01\0" |
5780 | 47.5k | /* 724 */ "fbule,pn $\x03, $\x01\0" |
5781 | 47.5k | /* 740 */ "fbo,pn $\x03, $\x01\0" |
5782 | 47.5k | /* 754 */ "ba,a,pn %icc, $\x01\0" |
5783 | 47.5k | /* 771 */ "bn,a,pn %icc, $\x01\0" |
5784 | 47.5k | /* 788 */ "bne,a,pn %icc, $\x01\0" |
5785 | 47.5k | /* 806 */ "be,a,pn %icc, $\x01\0" |
5786 | 47.5k | /* 823 */ "bg,a,pn %icc, $\x01\0" |
5787 | 47.5k | /* 840 */ "ble,a,pn %icc, $\x01\0" |
5788 | 47.5k | /* 858 */ "bge,a,pn %icc, $\x01\0" |
5789 | 47.5k | /* 876 */ "bl,a,pn %icc, $\x01\0" |
5790 | 47.5k | /* 893 */ "bgu,a,pn %icc, $\x01\0" |
5791 | 47.5k | /* 911 */ "bleu,a,pn %icc, $\x01\0" |
5792 | 47.5k | /* 930 */ "bcc,a,pn %icc, $\x01\0" |
5793 | 47.5k | /* 948 */ "bcs,a,pn %icc, $\x01\0" |
5794 | 47.5k | /* 966 */ "bpos,a,pn %icc, $\x01\0" |
5795 | 47.5k | /* 985 */ "bneg,a,pn %icc, $\x01\0" |
5796 | 47.5k | /* 1004 */ "bvc,a,pn %icc, $\x01\0" |
5797 | 47.5k | /* 1022 */ "bvs,a,pn %icc, $\x01\0" |
5798 | 47.5k | /* 1040 */ "ba,pn %icc, $\x01\0" |
5799 | 47.5k | /* 1055 */ "bn,pn %icc, $\x01\0" |
5800 | 47.5k | /* 1070 */ "bne,pn %icc, $\x01\0" |
5801 | 47.5k | /* 1086 */ "be,pn %icc, $\x01\0" |
5802 | 47.5k | /* 1101 */ "bg,pn %icc, $\x01\0" |
5803 | 47.5k | /* 1116 */ "ble,pn %icc, $\x01\0" |
5804 | 47.5k | /* 1132 */ "bge,pn %icc, $\x01\0" |
5805 | 47.5k | /* 1148 */ "bl,pn %icc, $\x01\0" |
5806 | 47.5k | /* 1163 */ "bgu,pn %icc, $\x01\0" |
5807 | 47.5k | /* 1179 */ "bleu,pn %icc, $\x01\0" |
5808 | 47.5k | /* 1196 */ "bcc,pn %icc, $\x01\0" |
5809 | 47.5k | /* 1212 */ "bcs,pn %icc, $\x01\0" |
5810 | 47.5k | /* 1228 */ "bpos,pn %icc, $\x01\0" |
5811 | 47.5k | /* 1245 */ "bneg,pn %icc, $\x01\0" |
5812 | 47.5k | /* 1262 */ "bvc,pn %icc, $\x01\0" |
5813 | 47.5k | /* 1278 */ "bvs,pn %icc, $\x01\0" |
5814 | 47.5k | /* 1294 */ "brz,a,pn $\x03, $\x01\0" |
5815 | 47.5k | /* 1310 */ "brlez,a,pn $\x03, $\x01\0" |
5816 | 47.5k | /* 1328 */ "brlz,a,pn $\x03, $\x01\0" |
5817 | 47.5k | /* 1345 */ "brnz,a,pn $\x03, $\x01\0" |
5818 | 47.5k | /* 1362 */ "brgz,a,pn $\x03, $\x01\0" |
5819 | 47.5k | /* 1379 */ "brgez,a,pn $\x03, $\x01\0" |
5820 | 47.5k | /* 1397 */ "brz,pn $\x03, $\x01\0" |
5821 | 47.5k | /* 1411 */ "brlez,pn $\x03, $\x01\0" |
5822 | 47.5k | /* 1427 */ "brlz,pn $\x03, $\x01\0" |
5823 | 47.5k | /* 1442 */ "brnz,pn $\x03, $\x01\0" |
5824 | 47.5k | /* 1457 */ "brgz,pn $\x03, $\x01\0" |
5825 | 47.5k | /* 1472 */ "brgez,pn $\x03, $\x01\0" |
5826 | 47.5k | /* 1488 */ "ba,a,pn %xcc, $\x01\0" |
5827 | 47.5k | /* 1505 */ "bn,a,pn %xcc, $\x01\0" |
5828 | 47.5k | /* 1522 */ "bne,a,pn %xcc, $\x01\0" |
5829 | 47.5k | /* 1540 */ "be,a,pn %xcc, $\x01\0" |
5830 | 47.5k | /* 1557 */ "bg,a,pn %xcc, $\x01\0" |
5831 | 47.5k | /* 1574 */ "ble,a,pn %xcc, $\x01\0" |
5832 | 47.5k | /* 1592 */ "bge,a,pn %xcc, $\x01\0" |
5833 | 47.5k | /* 1610 */ "bl,a,pn %xcc, $\x01\0" |
5834 | 47.5k | /* 1627 */ "bgu,a,pn %xcc, $\x01\0" |
5835 | 47.5k | /* 1645 */ "bleu,a,pn %xcc, $\x01\0" |
5836 | 47.5k | /* 1664 */ "bcc,a,pn %xcc, $\x01\0" |
5837 | 47.5k | /* 1682 */ "bcs,a,pn %xcc, $\x01\0" |
5838 | 47.5k | /* 1700 */ "bpos,a,pn %xcc, $\x01\0" |
5839 | 47.5k | /* 1719 */ "bneg,a,pn %xcc, $\x01\0" |
5840 | 47.5k | /* 1738 */ "bvc,a,pn %xcc, $\x01\0" |
5841 | 47.5k | /* 1756 */ "bvs,a,pn %xcc, $\x01\0" |
5842 | 47.5k | /* 1774 */ "ba,pn %xcc, $\x01\0" |
5843 | 47.5k | /* 1789 */ "bn,pn %xcc, $\x01\0" |
5844 | 47.5k | /* 1804 */ "bne,pn %xcc, $\x01\0" |
5845 | 47.5k | /* 1820 */ "be,pn %xcc, $\x01\0" |
5846 | 47.5k | /* 1835 */ "bg,pn %xcc, $\x01\0" |
5847 | 47.5k | /* 1850 */ "ble,pn %xcc, $\x01\0" |
5848 | 47.5k | /* 1866 */ "bge,pn %xcc, $\x01\0" |
5849 | 47.5k | /* 1882 */ "bl,pn %xcc, $\x01\0" |
5850 | 47.5k | /* 1897 */ "bgu,pn %xcc, $\x01\0" |
5851 | 47.5k | /* 1913 */ "bleu,pn %xcc, $\x01\0" |
5852 | 47.5k | /* 1930 */ "bcc,pn %xcc, $\x01\0" |
5853 | 47.5k | /* 1946 */ "bcs,pn %xcc, $\x01\0" |
5854 | 47.5k | /* 1962 */ "bpos,pn %xcc, $\x01\0" |
5855 | 47.5k | /* 1979 */ "bneg,pn %xcc, $\x01\0" |
5856 | 47.5k | /* 1996 */ "bvc,pn %xcc, $\x01\0" |
5857 | 47.5k | /* 2012 */ "bvs,pn %xcc, $\x01\0" |
5858 | 47.5k | /* 2028 */ "cas [$\x02], $\x03, $\x01\0" |
5859 | 47.5k | /* 2045 */ "casl [$\x02], $\x03, $\x01\0" |
5860 | 47.5k | /* 2063 */ "casx [$\x02], $\x03, $\x01\0" |
5861 | 47.5k | /* 2081 */ "casxl [$\x02], $\x03, $\x01\0" |
5862 | 47.5k | /* 2100 */ "fmovda %icc, $\x02, $\x01\0" |
5863 | 47.5k | /* 2120 */ "fmovdn %icc, $\x02, $\x01\0" |
5864 | 47.5k | /* 2140 */ "fmovdne %icc, $\x02, $\x01\0" |
5865 | 47.5k | /* 2161 */ "fmovde %icc, $\x02, $\x01\0" |
5866 | 47.5k | /* 2181 */ "fmovdg %icc, $\x02, $\x01\0" |
5867 | 47.5k | /* 2201 */ "fmovdle %icc, $\x02, $\x01\0" |
5868 | 47.5k | /* 2222 */ "fmovdge %icc, $\x02, $\x01\0" |
5869 | 47.5k | /* 2243 */ "fmovdl %icc, $\x02, $\x01\0" |
5870 | 47.5k | /* 2263 */ "fmovdgu %icc, $\x02, $\x01\0" |
5871 | 47.5k | /* 2284 */ "fmovdleu %icc, $\x02, $\x01\0" |
5872 | 47.5k | /* 2306 */ "fmovdcc %icc, $\x02, $\x01\0" |
5873 | 47.5k | /* 2327 */ "fmovdcs %icc, $\x02, $\x01\0" |
5874 | 47.5k | /* 2348 */ "fmovdpos %icc, $\x02, $\x01\0" |
5875 | 47.5k | /* 2370 */ "fmovdneg %icc, $\x02, $\x01\0" |
5876 | 47.5k | /* 2392 */ "fmovdvc %icc, $\x02, $\x01\0" |
5877 | 47.5k | /* 2413 */ "fmovdvs %icc, $\x02, $\x01\0" |
5878 | 47.5k | /* 2434 */ "fmovda %xcc, $\x02, $\x01\0" |
5879 | 47.5k | /* 2454 */ "fmovdn %xcc, $\x02, $\x01\0" |
5880 | 47.5k | /* 2474 */ "fmovdne %xcc, $\x02, $\x01\0" |
5881 | 47.5k | /* 2495 */ "fmovde %xcc, $\x02, $\x01\0" |
5882 | 47.5k | /* 2515 */ "fmovdg %xcc, $\x02, $\x01\0" |
5883 | 47.5k | /* 2535 */ "fmovdle %xcc, $\x02, $\x01\0" |
5884 | 47.5k | /* 2556 */ "fmovdge %xcc, $\x02, $\x01\0" |
5885 | 47.5k | /* 2577 */ "fmovdl %xcc, $\x02, $\x01\0" |
5886 | 47.5k | /* 2597 */ "fmovdgu %xcc, $\x02, $\x01\0" |
5887 | 47.5k | /* 2618 */ "fmovdleu %xcc, $\x02, $\x01\0" |
5888 | 47.5k | /* 2640 */ "fmovdcc %xcc, $\x02, $\x01\0" |
5889 | 47.5k | /* 2661 */ "fmovdcs %xcc, $\x02, $\x01\0" |
5890 | 47.5k | /* 2682 */ "fmovdpos %xcc, $\x02, $\x01\0" |
5891 | 47.5k | /* 2704 */ "fmovdneg %xcc, $\x02, $\x01\0" |
5892 | 47.5k | /* 2726 */ "fmovdvc %xcc, $\x02, $\x01\0" |
5893 | 47.5k | /* 2747 */ "fmovdvs %xcc, $\x02, $\x01\0" |
5894 | 47.5k | /* 2768 */ "fmovqa %icc, $\x02, $\x01\0" |
5895 | 47.5k | /* 2788 */ "fmovqn %icc, $\x02, $\x01\0" |
5896 | 47.5k | /* 2808 */ "fmovqne %icc, $\x02, $\x01\0" |
5897 | 47.5k | /* 2829 */ "fmovqe %icc, $\x02, $\x01\0" |
5898 | 47.5k | /* 2849 */ "fmovqg %icc, $\x02, $\x01\0" |
5899 | 47.5k | /* 2869 */ "fmovqle %icc, $\x02, $\x01\0" |
5900 | 47.5k | /* 2890 */ "fmovqge %icc, $\x02, $\x01\0" |
5901 | 47.5k | /* 2911 */ "fmovql %icc, $\x02, $\x01\0" |
5902 | 47.5k | /* 2931 */ "fmovqgu %icc, $\x02, $\x01\0" |
5903 | 47.5k | /* 2952 */ "fmovqleu %icc, $\x02, $\x01\0" |
5904 | 47.5k | /* 2974 */ "fmovqcc %icc, $\x02, $\x01\0" |
5905 | 47.5k | /* 2995 */ "fmovqcs %icc, $\x02, $\x01\0" |
5906 | 47.5k | /* 3016 */ "fmovqpos %icc, $\x02, $\x01\0" |
5907 | 47.5k | /* 3038 */ "fmovqneg %icc, $\x02, $\x01\0" |
5908 | 47.5k | /* 3060 */ "fmovqvc %icc, $\x02, $\x01\0" |
5909 | 47.5k | /* 3081 */ "fmovqvs %icc, $\x02, $\x01\0" |
5910 | 47.5k | /* 3102 */ "fmovqa %xcc, $\x02, $\x01\0" |
5911 | 47.5k | /* 3122 */ "fmovqn %xcc, $\x02, $\x01\0" |
5912 | 47.5k | /* 3142 */ "fmovqne %xcc, $\x02, $\x01\0" |
5913 | 47.5k | /* 3163 */ "fmovqe %xcc, $\x02, $\x01\0" |
5914 | 47.5k | /* 3183 */ "fmovqg %xcc, $\x02, $\x01\0" |
5915 | 47.5k | /* 3203 */ "fmovqle %xcc, $\x02, $\x01\0" |
5916 | 47.5k | /* 3224 */ "fmovqge %xcc, $\x02, $\x01\0" |
5917 | 47.5k | /* 3245 */ "fmovql %xcc, $\x02, $\x01\0" |
5918 | 47.5k | /* 3265 */ "fmovqgu %xcc, $\x02, $\x01\0" |
5919 | 47.5k | /* 3286 */ "fmovqleu %xcc, $\x02, $\x01\0" |
5920 | 47.5k | /* 3308 */ "fmovqcc %xcc, $\x02, $\x01\0" |
5921 | 47.5k | /* 3329 */ "fmovqcs %xcc, $\x02, $\x01\0" |
5922 | 47.5k | /* 3350 */ "fmovqpos %xcc, $\x02, $\x01\0" |
5923 | 47.5k | /* 3372 */ "fmovqneg %xcc, $\x02, $\x01\0" |
5924 | 47.5k | /* 3394 */ "fmovqvc %xcc, $\x02, $\x01\0" |
5925 | 47.5k | /* 3415 */ "fmovqvs %xcc, $\x02, $\x01\0" |
5926 | 47.5k | /* 3436 */ "fmovrdz $\x02, $\x03, $\x01\0" |
5927 | 47.5k | /* 3455 */ "fmovrdlez $\x02, $\x03, $\x01\0" |
5928 | 47.5k | /* 3476 */ "fmovrdlz $\x02, $\x03, $\x01\0" |
5929 | 47.5k | /* 3496 */ "fmovrdnz $\x02, $\x03, $\x01\0" |
5930 | 47.5k | /* 3516 */ "fmovrdgz $\x02, $\x03, $\x01\0" |
5931 | 47.5k | /* 3536 */ "fmovrdgez $\x02, $\x03, $\x01\0" |
5932 | 47.5k | /* 3557 */ "fmovrqz $\x02, $\x03, $\x01\0" |
5933 | 47.5k | /* 3576 */ "fmovrqlez $\x02, $\x03, $\x01\0" |
5934 | 47.5k | /* 3597 */ "fmovrqlz $\x02, $\x03, $\x01\0" |
5935 | 47.5k | /* 3617 */ "fmovrqnz $\x02, $\x03, $\x01\0" |
5936 | 47.5k | /* 3637 */ "fmovrqgz $\x02, $\x03, $\x01\0" |
5937 | 47.5k | /* 3657 */ "fmovrqgez $\x02, $\x03, $\x01\0" |
5938 | 47.5k | /* 3678 */ "fmovrsz $\x02, $\x03, $\x01\0" |
5939 | 47.5k | /* 3697 */ "fmovrslez $\x02, $\x03, $\x01\0" |
5940 | 47.5k | /* 3718 */ "fmovrslz $\x02, $\x03, $\x01\0" |
5941 | 47.5k | /* 3738 */ "fmovrsnz $\x02, $\x03, $\x01\0" |
5942 | 47.5k | /* 3758 */ "fmovrsgz $\x02, $\x03, $\x01\0" |
5943 | 47.5k | /* 3778 */ "fmovrsgez $\x02, $\x03, $\x01\0" |
5944 | 47.5k | /* 3799 */ "fmovsa %icc, $\x02, $\x01\0" |
5945 | 47.5k | /* 3819 */ "fmovsn %icc, $\x02, $\x01\0" |
5946 | 47.5k | /* 3839 */ "fmovsne %icc, $\x02, $\x01\0" |
5947 | 47.5k | /* 3860 */ "fmovse %icc, $\x02, $\x01\0" |
5948 | 47.5k | /* 3880 */ "fmovsg %icc, $\x02, $\x01\0" |
5949 | 47.5k | /* 3900 */ "fmovsle %icc, $\x02, $\x01\0" |
5950 | 47.5k | /* 3921 */ "fmovsge %icc, $\x02, $\x01\0" |
5951 | 47.5k | /* 3942 */ "fmovsl %icc, $\x02, $\x01\0" |
5952 | 47.5k | /* 3962 */ "fmovsgu %icc, $\x02, $\x01\0" |
5953 | 47.5k | /* 3983 */ "fmovsleu %icc, $\x02, $\x01\0" |
5954 | 47.5k | /* 4005 */ "fmovscc %icc, $\x02, $\x01\0" |
5955 | 47.5k | /* 4026 */ "fmovscs %icc, $\x02, $\x01\0" |
5956 | 47.5k | /* 4047 */ "fmovspos %icc, $\x02, $\x01\0" |
5957 | 47.5k | /* 4069 */ "fmovsneg %icc, $\x02, $\x01\0" |
5958 | 47.5k | /* 4091 */ "fmovsvc %icc, $\x02, $\x01\0" |
5959 | 47.5k | /* 4112 */ "fmovsvs %icc, $\x02, $\x01\0" |
5960 | 47.5k | /* 4133 */ "fmovsa %xcc, $\x02, $\x01\0" |
5961 | 47.5k | /* 4153 */ "fmovsn %xcc, $\x02, $\x01\0" |
5962 | 47.5k | /* 4173 */ "fmovsne %xcc, $\x02, $\x01\0" |
5963 | 47.5k | /* 4194 */ "fmovse %xcc, $\x02, $\x01\0" |
5964 | 47.5k | /* 4214 */ "fmovsg %xcc, $\x02, $\x01\0" |
5965 | 47.5k | /* 4234 */ "fmovsle %xcc, $\x02, $\x01\0" |
5966 | 47.5k | /* 4255 */ "fmovsge %xcc, $\x02, $\x01\0" |
5967 | 47.5k | /* 4276 */ "fmovsl %xcc, $\x02, $\x01\0" |
5968 | 47.5k | /* 4296 */ "fmovsgu %xcc, $\x02, $\x01\0" |
5969 | 47.5k | /* 4317 */ "fmovsleu %xcc, $\x02, $\x01\0" |
5970 | 47.5k | /* 4339 */ "fmovscc %xcc, $\x02, $\x01\0" |
5971 | 47.5k | /* 4360 */ "fmovscs %xcc, $\x02, $\x01\0" |
5972 | 47.5k | /* 4381 */ "fmovspos %xcc, $\x02, $\x01\0" |
5973 | 47.5k | /* 4403 */ "fmovsneg %xcc, $\x02, $\x01\0" |
5974 | 47.5k | /* 4425 */ "fmovsvc %xcc, $\x02, $\x01\0" |
5975 | 47.5k | /* 4446 */ "fmovsvs %xcc, $\x02, $\x01\0" |
5976 | 47.5k | /* 4467 */ "mova %icc, $\x02, $\x01\0" |
5977 | 47.5k | /* 4485 */ "movn %icc, $\x02, $\x01\0" |
5978 | 47.5k | /* 4503 */ "movne %icc, $\x02, $\x01\0" |
5979 | 47.5k | /* 4522 */ "move %icc, $\x02, $\x01\0" |
5980 | 47.5k | /* 4540 */ "movg %icc, $\x02, $\x01\0" |
5981 | 47.5k | /* 4558 */ "movle %icc, $\x02, $\x01\0" |
5982 | 47.5k | /* 4577 */ "movge %icc, $\x02, $\x01\0" |
5983 | 47.5k | /* 4596 */ "movl %icc, $\x02, $\x01\0" |
5984 | 47.5k | /* 4614 */ "movgu %icc, $\x02, $\x01\0" |
5985 | 47.5k | /* 4633 */ "movleu %icc, $\x02, $\x01\0" |
5986 | 47.5k | /* 4653 */ "movcc %icc, $\x02, $\x01\0" |
5987 | 47.5k | /* 4672 */ "movcs %icc, $\x02, $\x01\0" |
5988 | 47.5k | /* 4691 */ "movpos %icc, $\x02, $\x01\0" |
5989 | 47.5k | /* 4711 */ "movneg %icc, $\x02, $\x01\0" |
5990 | 47.5k | /* 4731 */ "movvc %icc, $\x02, $\x01\0" |
5991 | 47.5k | /* 4750 */ "movvs %icc, $\x02, $\x01\0" |
5992 | 47.5k | /* 4769 */ "movrz $\x02, $\x03, $\x01\0" |
5993 | 47.5k | /* 4786 */ "movrlez $\x02, $\x03, $\x01\0" |
5994 | 47.5k | /* 4805 */ "movrlz $\x02, $\x03, $\x01\0" |
5995 | 47.5k | /* 4823 */ "movrnz $\x02, $\x03, $\x01\0" |
5996 | 47.5k | /* 4841 */ "movrgz $\x02, $\x03, $\x01\0" |
5997 | 47.5k | /* 4859 */ "movrgez $\x02, $\x03, $\x01\0" |
5998 | 47.5k | /* 4878 */ "mova %xcc, $\x02, $\x01\0" |
5999 | 47.5k | /* 4896 */ "movn %xcc, $\x02, $\x01\0" |
6000 | 47.5k | /* 4914 */ "movne %xcc, $\x02, $\x01\0" |
6001 | 47.5k | /* 4933 */ "move %xcc, $\x02, $\x01\0" |
6002 | 47.5k | /* 4951 */ "movg %xcc, $\x02, $\x01\0" |
6003 | 47.5k | /* 4969 */ "movle %xcc, $\x02, $\x01\0" |
6004 | 47.5k | /* 4988 */ "movge %xcc, $\x02, $\x01\0" |
6005 | 47.5k | /* 5007 */ "movl %xcc, $\x02, $\x01\0" |
6006 | 47.5k | /* 5025 */ "movgu %xcc, $\x02, $\x01\0" |
6007 | 47.5k | /* 5044 */ "movleu %xcc, $\x02, $\x01\0" |
6008 | 47.5k | /* 5064 */ "movcc %xcc, $\x02, $\x01\0" |
6009 | 47.5k | /* 5083 */ "movcs %xcc, $\x02, $\x01\0" |
6010 | 47.5k | /* 5102 */ "movpos %xcc, $\x02, $\x01\0" |
6011 | 47.5k | /* 5122 */ "movneg %xcc, $\x02, $\x01\0" |
6012 | 47.5k | /* 5142 */ "movvc %xcc, $\x02, $\x01\0" |
6013 | 47.5k | /* 5161 */ "movvs %xcc, $\x02, $\x01\0" |
6014 | 47.5k | /* 5180 */ "tst $\x02\0" |
6015 | 47.5k | /* 5187 */ "mov $\x03, $\x01\0" |
6016 | 47.5k | /* 5198 */ "restore\0" |
6017 | 47.5k | /* 5206 */ "ret\0" |
6018 | 47.5k | /* 5210 */ "retl\0" |
6019 | 47.5k | /* 5215 */ "save\0" |
6020 | 47.5k | /* 5220 */ "cmp $\x02, $\x03\0" |
6021 | 47.5k | /* 5231 */ "ta %icc, $\x02\0" |
6022 | 47.5k | /* 5243 */ "ta %icc, $\x01 + $\x02\0" |
6023 | 47.5k | /* 5260 */ "tn %icc, $\x02\0" |
6024 | 47.5k | /* 5272 */ "tn %icc, $\x01 + $\x02\0" |
6025 | 47.5k | /* 5289 */ "tne %icc, $\x02\0" |
6026 | 47.5k | /* 5302 */ "tne %icc, $\x01 + $\x02\0" |
6027 | 47.5k | /* 5320 */ "te %icc, $\x02\0" |
6028 | 47.5k | /* 5332 */ "te %icc, $\x01 + $\x02\0" |
6029 | 47.5k | /* 5349 */ "tg %icc, $\x02\0" |
6030 | 47.5k | /* 5361 */ "tg %icc, $\x01 + $\x02\0" |
6031 | 47.5k | /* 5378 */ "tle %icc, $\x02\0" |
6032 | 47.5k | /* 5391 */ "tle %icc, $\x01 + $\x02\0" |
6033 | 47.5k | /* 5409 */ "tge %icc, $\x02\0" |
6034 | 47.5k | /* 5422 */ "tge %icc, $\x01 + $\x02\0" |
6035 | 47.5k | /* 5440 */ "tl %icc, $\x02\0" |
6036 | 47.5k | /* 5452 */ "tl %icc, $\x01 + $\x02\0" |
6037 | 47.5k | /* 5469 */ "tgu %icc, $\x02\0" |
6038 | 47.5k | /* 5482 */ "tgu %icc, $\x01 + $\x02\0" |
6039 | 47.5k | /* 5500 */ "tleu %icc, $\x02\0" |
6040 | 47.5k | /* 5514 */ "tleu %icc, $\x01 + $\x02\0" |
6041 | 47.5k | /* 5533 */ "tcc %icc, $\x02\0" |
6042 | 47.5k | /* 5546 */ "tcc %icc, $\x01 + $\x02\0" |
6043 | 47.5k | /* 5564 */ "tcs %icc, $\x02\0" |
6044 | 47.5k | /* 5577 */ "tcs %icc, $\x01 + $\x02\0" |
6045 | 47.5k | /* 5595 */ "tpos %icc, $\x02\0" |
6046 | 47.5k | /* 5609 */ "tpos %icc, $\x01 + $\x02\0" |
6047 | 47.5k | /* 5628 */ "tneg %icc, $\x02\0" |
6048 | 47.5k | /* 5642 */ "tneg %icc, $\x01 + $\x02\0" |
6049 | 47.5k | /* 5661 */ "tvc %icc, $\x02\0" |
6050 | 47.5k | /* 5674 */ "tvc %icc, $\x01 + $\x02\0" |
6051 | 47.5k | /* 5692 */ "tvs %icc, $\x02\0" |
6052 | 47.5k | /* 5705 */ "tvs %icc, $\x01 + $\x02\0" |
6053 | 47.5k | /* 5723 */ "ta $\x02\0" |
6054 | 47.5k | /* 5729 */ "ta $\x01 + $\x02\0" |
6055 | 47.5k | /* 5740 */ "tn $\x02\0" |
6056 | 47.5k | /* 5746 */ "tn $\x01 + $\x02\0" |
6057 | 47.5k | /* 5757 */ "tne $\x02\0" |
6058 | 47.5k | /* 5764 */ "tne $\x01 + $\x02\0" |
6059 | 47.5k | /* 5776 */ "te $\x02\0" |
6060 | 47.5k | /* 5782 */ "te $\x01 + $\x02\0" |
6061 | 47.5k | /* 5793 */ "tg $\x02\0" |
6062 | 47.5k | /* 5799 */ "tg $\x01 + $\x02\0" |
6063 | 47.5k | /* 5810 */ "tle $\x02\0" |
6064 | 47.5k | /* 5817 */ "tle $\x01 + $\x02\0" |
6065 | 47.5k | /* 5829 */ "tge $\x02\0" |
6066 | 47.5k | /* 5836 */ "tge $\x01 + $\x02\0" |
6067 | 47.5k | /* 5848 */ "tl $\x02\0" |
6068 | 47.5k | /* 5854 */ "tl $\x01 + $\x02\0" |
6069 | 47.5k | /* 5865 */ "tgu $\x02\0" |
6070 | 47.5k | /* 5872 */ "tgu $\x01 + $\x02\0" |
6071 | 47.5k | /* 5884 */ "tleu $\x02\0" |
6072 | 47.5k | /* 5892 */ "tleu $\x01 + $\x02\0" |
6073 | 47.5k | /* 5905 */ "tcc $\x02\0" |
6074 | 47.5k | /* 5912 */ "tcc $\x01 + $\x02\0" |
6075 | 47.5k | /* 5924 */ "tcs $\x02\0" |
6076 | 47.5k | /* 5931 */ "tcs $\x01 + $\x02\0" |
6077 | 47.5k | /* 5943 */ "tpos $\x02\0" |
6078 | 47.5k | /* 5951 */ "tpos $\x01 + $\x02\0" |
6079 | 47.5k | /* 5964 */ "tneg $\x02\0" |
6080 | 47.5k | /* 5972 */ "tneg $\x01 + $\x02\0" |
6081 | 47.5k | /* 5985 */ "tvc $\x02\0" |
6082 | 47.5k | /* 5992 */ "tvc $\x01 + $\x02\0" |
6083 | 47.5k | /* 6004 */ "tvs $\x02\0" |
6084 | 47.5k | /* 6011 */ "tvs $\x01 + $\x02\0" |
6085 | 47.5k | /* 6023 */ "ta %xcc, $\x02\0" |
6086 | 47.5k | /* 6035 */ "ta %xcc, $\x01 + $\x02\0" |
6087 | 47.5k | /* 6052 */ "tn %xcc, $\x02\0" |
6088 | 47.5k | /* 6064 */ "tn %xcc, $\x01 + $\x02\0" |
6089 | 47.5k | /* 6081 */ "tne %xcc, $\x02\0" |
6090 | 47.5k | /* 6094 */ "tne %xcc, $\x01 + $\x02\0" |
6091 | 47.5k | /* 6112 */ "te %xcc, $\x02\0" |
6092 | 47.5k | /* 6124 */ "te %xcc, $\x01 + $\x02\0" |
6093 | 47.5k | /* 6141 */ "tg %xcc, $\x02\0" |
6094 | 47.5k | /* 6153 */ "tg %xcc, $\x01 + $\x02\0" |
6095 | 47.5k | /* 6170 */ "tle %xcc, $\x02\0" |
6096 | 47.5k | /* 6183 */ "tle %xcc, $\x01 + $\x02\0" |
6097 | 47.5k | /* 6201 */ "tge %xcc, $\x02\0" |
6098 | 47.5k | /* 6214 */ "tge %xcc, $\x01 + $\x02\0" |
6099 | 47.5k | /* 6232 */ "tl %xcc, $\x02\0" |
6100 | 47.5k | /* 6244 */ "tl %xcc, $\x01 + $\x02\0" |
6101 | 47.5k | /* 6261 */ "tgu %xcc, $\x02\0" |
6102 | 47.5k | /* 6274 */ "tgu %xcc, $\x01 + $\x02\0" |
6103 | 47.5k | /* 6292 */ "tleu %xcc, $\x02\0" |
6104 | 47.5k | /* 6306 */ "tleu %xcc, $\x01 + $\x02\0" |
6105 | 47.5k | /* 6325 */ "tcc %xcc, $\x02\0" |
6106 | 47.5k | /* 6338 */ "tcc %xcc, $\x01 + $\x02\0" |
6107 | 47.5k | /* 6356 */ "tcs %xcc, $\x02\0" |
6108 | 47.5k | /* 6369 */ "tcs %xcc, $\x01 + $\x02\0" |
6109 | 47.5k | /* 6387 */ "tpos %xcc, $\x02\0" |
6110 | 47.5k | /* 6401 */ "tpos %xcc, $\x01 + $\x02\0" |
6111 | 47.5k | /* 6420 */ "tneg %xcc, $\x02\0" |
6112 | 47.5k | /* 6434 */ "tneg %xcc, $\x01 + $\x02\0" |
6113 | 47.5k | /* 6453 */ "tvc %xcc, $\x02\0" |
6114 | 47.5k | /* 6466 */ "tvc %xcc, $\x01 + $\x02\0" |
6115 | 47.5k | /* 6484 */ "tvs %xcc, $\x02\0" |
6116 | 47.5k | /* 6497 */ "tvs %xcc, $\x01 + $\x02\0" |
6117 | 47.5k | /* 6515 */ "fcmpd $\x02, $\x03\0" |
6118 | 47.5k | /* 6528 */ "fcmped $\x02, $\x03\0" |
6119 | 47.5k | /* 6542 */ "fcmpeq $\x02, $\x03\0" |
6120 | 47.5k | /* 6556 */ "fcmpes $\x02, $\x03\0" |
6121 | 47.5k | /* 6570 */ "fcmpq $\x02, $\x03\0" |
6122 | 47.5k | /* 6583 */ "fcmps $\x02, $\x03\0" |
6123 | 47.5k | /* 6596 */ "fmovda $\x02, $\x03, $\x01\0" |
6124 | 47.5k | /* 6614 */ "fmovdn $\x02, $\x03, $\x01\0" |
6125 | 47.5k | /* 6632 */ "fmovdu $\x02, $\x03, $\x01\0" |
6126 | 47.5k | /* 6650 */ "fmovdg $\x02, $\x03, $\x01\0" |
6127 | 47.5k | /* 6668 */ "fmovdug $\x02, $\x03, $\x01\0" |
6128 | 47.5k | /* 6687 */ "fmovdl $\x02, $\x03, $\x01\0" |
6129 | 47.5k | /* 6705 */ "fmovdul $\x02, $\x03, $\x01\0" |
6130 | 47.5k | /* 6724 */ "fmovdlg $\x02, $\x03, $\x01\0" |
6131 | 47.5k | /* 6743 */ "fmovdne $\x02, $\x03, $\x01\0" |
6132 | 47.5k | /* 6762 */ "fmovde $\x02, $\x03, $\x01\0" |
6133 | 47.5k | /* 6780 */ "fmovdue $\x02, $\x03, $\x01\0" |
6134 | 47.5k | /* 6799 */ "fmovdge $\x02, $\x03, $\x01\0" |
6135 | 47.5k | /* 6818 */ "fmovduge $\x02, $\x03, $\x01\0" |
6136 | 47.5k | /* 6838 */ "fmovdle $\x02, $\x03, $\x01\0" |
6137 | 47.5k | /* 6857 */ "fmovdule $\x02, $\x03, $\x01\0" |
6138 | 47.5k | /* 6877 */ "fmovdo $\x02, $\x03, $\x01\0" |
6139 | 47.5k | /* 6895 */ "fmovqa $\x02, $\x03, $\x01\0" |
6140 | 47.5k | /* 6913 */ "fmovqn $\x02, $\x03, $\x01\0" |
6141 | 47.5k | /* 6931 */ "fmovqu $\x02, $\x03, $\x01\0" |
6142 | 47.5k | /* 6949 */ "fmovqg $\x02, $\x03, $\x01\0" |
6143 | 47.5k | /* 6967 */ "fmovqug $\x02, $\x03, $\x01\0" |
6144 | 47.5k | /* 6986 */ "fmovql $\x02, $\x03, $\x01\0" |
6145 | 47.5k | /* 7004 */ "fmovqul $\x02, $\x03, $\x01\0" |
6146 | 47.5k | /* 7023 */ "fmovqlg $\x02, $\x03, $\x01\0" |
6147 | 47.5k | /* 7042 */ "fmovqne $\x02, $\x03, $\x01\0" |
6148 | 47.5k | /* 7061 */ "fmovqe $\x02, $\x03, $\x01\0" |
6149 | 47.5k | /* 7079 */ "fmovque $\x02, $\x03, $\x01\0" |
6150 | 47.5k | /* 7098 */ "fmovqge $\x02, $\x03, $\x01\0" |
6151 | 47.5k | /* 7117 */ "fmovquge $\x02, $\x03, $\x01\0" |
6152 | 47.5k | /* 7137 */ "fmovqle $\x02, $\x03, $\x01\0" |
6153 | 47.5k | /* 7156 */ "fmovqule $\x02, $\x03, $\x01\0" |
6154 | 47.5k | /* 7176 */ "fmovqo $\x02, $\x03, $\x01\0" |
6155 | 47.5k | /* 7194 */ "fmovsa $\x02, $\x03, $\x01\0" |
6156 | 47.5k | /* 7212 */ "fmovsn $\x02, $\x03, $\x01\0" |
6157 | 47.5k | /* 7230 */ "fmovsu $\x02, $\x03, $\x01\0" |
6158 | 47.5k | /* 7248 */ "fmovsg $\x02, $\x03, $\x01\0" |
6159 | 47.5k | /* 7266 */ "fmovsug $\x02, $\x03, $\x01\0" |
6160 | 47.5k | /* 7285 */ "fmovsl $\x02, $\x03, $\x01\0" |
6161 | 47.5k | /* 7303 */ "fmovsul $\x02, $\x03, $\x01\0" |
6162 | 47.5k | /* 7322 */ "fmovslg $\x02, $\x03, $\x01\0" |
6163 | 47.5k | /* 7341 */ "fmovsne $\x02, $\x03, $\x01\0" |
6164 | 47.5k | /* 7360 */ "fmovse $\x02, $\x03, $\x01\0" |
6165 | 47.5k | /* 7378 */ "fmovsue $\x02, $\x03, $\x01\0" |
6166 | 47.5k | /* 7397 */ "fmovsge $\x02, $\x03, $\x01\0" |
6167 | 47.5k | /* 7416 */ "fmovsuge $\x02, $\x03, $\x01\0" |
6168 | 47.5k | /* 7436 */ "fmovsle $\x02, $\x03, $\x01\0" |
6169 | 47.5k | /* 7455 */ "fmovsule $\x02, $\x03, $\x01\0" |
6170 | 47.5k | /* 7475 */ "fmovso $\x02, $\x03, $\x01\0" |
6171 | 47.5k | /* 7493 */ "mova $\x02, $\x03, $\x01\0" |
6172 | 47.5k | /* 7509 */ "movn $\x02, $\x03, $\x01\0" |
6173 | 47.5k | /* 7525 */ "movu $\x02, $\x03, $\x01\0" |
6174 | 47.5k | /* 7541 */ "movg $\x02, $\x03, $\x01\0" |
6175 | 47.5k | /* 7557 */ "movug $\x02, $\x03, $\x01\0" |
6176 | 47.5k | /* 7574 */ "movl $\x02, $\x03, $\x01\0" |
6177 | 47.5k | /* 7590 */ "movul $\x02, $\x03, $\x01\0" |
6178 | 47.5k | /* 7607 */ "movlg $\x02, $\x03, $\x01\0" |
6179 | 47.5k | /* 7624 */ "movne $\x02, $\x03, $\x01\0" |
6180 | 47.5k | /* 7641 */ "move $\x02, $\x03, $\x01\0" |
6181 | 47.5k | /* 7657 */ "movue $\x02, $\x03, $\x01\0" |
6182 | 47.5k | /* 7674 */ "movge $\x02, $\x03, $\x01\0" |
6183 | 47.5k | /* 7691 */ "movuge $\x02, $\x03, $\x01\0" |
6184 | 47.5k | /* 7709 */ "movle $\x02, $\x03, $\x01\0" |
6185 | 47.5k | /* 7726 */ "movule $\x02, $\x03, $\x01\0" |
6186 | 47.5k | /* 7744 */ "movo $\x02, $\x03, $\x01\0" |
6187 | 47.5k | ; |
6188 | | |
6189 | 47.5k | #ifndef NDEBUG |
6190 | | //static struct SortCheck { |
6191 | | // SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) { |
6192 | | // assert(std::is_sorted( |
6193 | | // OpToPatterns.begin(), OpToPatterns.end(), |
6194 | | // [](const PatternsForOpcode &L, const //PatternsForOpcode &R) { |
6195 | | // return L.Opcode < R.Opcode; |
6196 | | // }) && |
6197 | | // "tablegen failed to sort opcode patterns"); |
6198 | | // } |
6199 | | //} sortCheckVar(OpToPatterns); |
6200 | 47.5k | #endif |
6201 | | |
6202 | 47.5k | AliasMatchingData M = { |
6203 | 47.5k | OpToPatterns, |
6204 | 47.5k | Patterns, |
6205 | 47.5k | Conds, |
6206 | 47.5k | AsmStrings, |
6207 | 47.5k | NULL, |
6208 | 47.5k | }; |
6209 | 47.5k | const char *AsmString = matchAliasPatterns(MI, &M); |
6210 | 47.5k | if (!AsmString) return false; |
6211 | | |
6212 | 3.33k | unsigned I = 0; |
6213 | 20.9k | while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
6214 | 17.6k | AsmString[I] != '$' && AsmString[I] != '\0') |
6215 | 17.6k | ++I; |
6216 | 3.33k | SStream_concat1(OS, '\t'); |
6217 | 3.33k | char *substr = malloc(I+1); |
6218 | 3.33k | memcpy(substr, AsmString, I); |
6219 | 3.33k | substr[I] = '\0'; |
6220 | 3.33k | SStream_concat0(OS, substr); |
6221 | 3.33k | free(substr); |
6222 | 3.33k | if (AsmString[I] != '\0') { |
6223 | 3.29k | if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
6224 | 3.29k | SStream_concat1(OS, '\t'); |
6225 | 3.29k | ++I; |
6226 | 3.29k | } |
6227 | 15.7k | do { |
6228 | 15.7k | if (AsmString[I] == '$') { |
6229 | 5.72k | ++I; |
6230 | 5.72k | if (AsmString[I] == (char)0xff) { |
6231 | 0 | ++I; |
6232 | 0 | int OpIdx = AsmString[I++] - 1; |
6233 | 0 | int PrintMethodIdx = AsmString[I++] - 1; |
6234 | 0 | printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS); |
6235 | 0 | } else |
6236 | 5.72k | printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS); |
6237 | 10.0k | } else { |
6238 | 10.0k | SStream_concat1(OS, AsmString[I++]); |
6239 | 10.0k | } |
6240 | 15.7k | } while (AsmString[I] != '\0'); |
6241 | 3.29k | } |
6242 | | |
6243 | 3.33k | return true; |
6244 | | #else |
6245 | | return false; |
6246 | | #endif // CAPSTONE_DIET |
6247 | 47.5k | } |
6248 | | |
6249 | | static void printCustomAliasOperand( |
6250 | | MCInst *MI, uint64_t Address, unsigned OpIdx, |
6251 | | unsigned PrintMethodIdx, |
6252 | 0 | SStream *OS) { |
6253 | 0 | #ifndef CAPSTONE_DIET |
6254 | 0 | CS_ASSERT_RET(0 && "Unknown PrintMethod kind"); |
6255 | 0 | #endif // CAPSTONE_DIET |
6256 | 0 | } |
6257 | | |
6258 | | #endif // PRINT_ALIAS_INSTR |