Coverage Report

Created: 2026-09-03 07:09

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/capstonev5/arch/Sparc/SparcGenAsmWriter.inc
Line
Count
Source
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|*Assembly Writer Source Fragment                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
/* Capstone Disassembly Engine */
10
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
12
#include <stdio.h>  // debug
13
#include <capstone/platform.h>
14
15
16
/// printInstruction - This method is automatically generated by tablegen
17
/// from the instruction set description.
18
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19
36.2k
{
20
36.2k
  static const uint32_t OpInfo[] = {
21
36.2k
    0U, // PHI
22
36.2k
    0U, // INLINEASM
23
36.2k
    0U, // CFI_INSTRUCTION
24
36.2k
    0U, // EH_LABEL
25
36.2k
    0U, // GC_LABEL
26
36.2k
    0U, // KILL
27
36.2k
    0U, // EXTRACT_SUBREG
28
36.2k
    0U, // INSERT_SUBREG
29
36.2k
    0U, // IMPLICIT_DEF
30
36.2k
    0U, // SUBREG_TO_REG
31
36.2k
    0U, // COPY_TO_REGCLASS
32
36.2k
    2452U,  // DBG_VALUE
33
36.2k
    0U, // REG_SEQUENCE
34
36.2k
    0U, // COPY
35
36.2k
    2445U,  // BUNDLE
36
36.2k
    2462U,  // LIFETIME_START
37
36.2k
    2432U,  // LIFETIME_END
38
36.2k
    0U, // STACKMAP
39
36.2k
    0U, // PATCHPOINT
40
36.2k
    0U, // LOAD_STACK_GUARD
41
36.2k
    0U, // STATEPOINT
42
36.2k
    0U, // FRAME_ALLOC
43
36.2k
    4688U,  // ADDCCri
44
36.2k
    4688U,  // ADDCCrr
45
36.2k
    5925U,  // ADDCri
46
36.2k
    5925U,  // ADDCrr
47
36.2k
    4772U,  // ADDEri
48
36.2k
    4772U,  // ADDErr
49
36.2k
    4786U,  // ADDXC
50
36.2k
    4678U,  // ADDXCCC
51
36.2k
    4808U,  // ADDXri
52
36.2k
    4808U,  // ADDXrr
53
36.2k
    4808U,  // ADDri
54
36.2k
    4808U,  // ADDrr
55
36.2k
    74166U, // ADJCALLSTACKDOWN
56
36.2k
    74185U, // ADJCALLSTACKUP
57
36.2k
    5497U,  // ALIGNADDR
58
36.2k
    5127U,  // ALIGNADDRL
59
36.2k
    4695U,  // ANDCCri
60
36.2k
    4695U,  // ANDCCrr
61
36.2k
    4718U,  // ANDNCCri
62
36.2k
    4718U,  // ANDNCCrr
63
36.2k
    5182U,  // ANDNri
64
36.2k
    5182U,  // ANDNrr
65
36.2k
    5182U,  // ANDXNrr
66
36.2k
    4876U,  // ANDXri
67
36.2k
    4876U,  // ANDXrr
68
36.2k
    4876U,  // ANDri
69
36.2k
    4876U,  // ANDrr
70
36.2k
    4502U,  // ARRAY16
71
36.2k
    4255U,  // ARRAY32
72
36.2k
    4526U,  // ARRAY8
73
36.2k
    0U, // ATOMIC_LOAD_ADD_32
74
36.2k
    0U, // ATOMIC_LOAD_ADD_64
75
36.2k
    0U, // ATOMIC_LOAD_AND_32
76
36.2k
    0U, // ATOMIC_LOAD_AND_64
77
36.2k
    0U, // ATOMIC_LOAD_MAX_32
78
36.2k
    0U, // ATOMIC_LOAD_MAX_64
79
36.2k
    0U, // ATOMIC_LOAD_MIN_32
80
36.2k
    0U, // ATOMIC_LOAD_MIN_64
81
36.2k
    0U, // ATOMIC_LOAD_NAND_32
82
36.2k
    0U, // ATOMIC_LOAD_NAND_64
83
36.2k
    0U, // ATOMIC_LOAD_OR_32
84
36.2k
    0U, // ATOMIC_LOAD_OR_64
85
36.2k
    0U, // ATOMIC_LOAD_SUB_32
86
36.2k
    0U, // ATOMIC_LOAD_SUB_64
87
36.2k
    0U, // ATOMIC_LOAD_UMAX_32
88
36.2k
    0U, // ATOMIC_LOAD_UMAX_64
89
36.2k
    0U, // ATOMIC_LOAD_UMIN_32
90
36.2k
    0U, // ATOMIC_LOAD_UMIN_64
91
36.2k
    0U, // ATOMIC_LOAD_XOR_32
92
36.2k
    0U, // ATOMIC_LOAD_XOR_64
93
36.2k
    0U, // ATOMIC_SWAP_64
94
36.2k
    74271U, // BA
95
36.2k
    1194492U, // BCOND
96
36.2k
    1260028U, // BCONDA
97
36.2k
    17659U, // BINDri
98
36.2k
    17659U, // BINDrr
99
36.2k
    5065U,  // BMASK
100
36.2k
    145915U,  // BPFCC
101
36.2k
    211451U,  // BPFCCA
102
36.2k
    276987U,  // BPFCCANT
103
36.2k
    342523U,  // BPFCCNT
104
36.2k
    2106465U, // BPGEZapn
105
36.2k
    2105838U, // BPGEZapt
106
36.2k
    2106532U, // BPGEZnapn
107
36.2k
    2107288U, // BPGEZnapt
108
36.2k
    2106489U, // BPGZapn
109
36.2k
    2105856U, // BPGZapt
110
36.2k
    2106552U, // BPGZnapn
111
36.2k
    2107384U, // BPGZnapt
112
36.2k
    1456636U, // BPICC
113
36.2k
    473596U,  // BPICCA
114
36.2k
    539132U,  // BPICCANT
115
36.2k
    604668U,  // BPICCNT
116
36.2k
    2106477U, // BPLEZapn
117
36.2k
    2105847U, // BPLEZapt
118
36.2k
    2106542U, // BPLEZnapn
119
36.2k
    2107337U, // BPLEZnapt
120
36.2k
    2106500U, // BPLZapn
121
36.2k
    2105864U, // BPLZapt
122
36.2k
    2106561U, // BPLZnapn
123
36.2k
    2107428U, // BPLZnapt
124
36.2k
    2106511U, // BPNZapn
125
36.2k
    2105872U, // BPNZapt
126
36.2k
    2106570U, // BPNZnapn
127
36.2k
    2107472U, // BPNZnapt
128
36.2k
    1718780U, // BPXCC
129
36.2k
    735740U,  // BPXCCA
130
36.2k
    801276U,  // BPXCCANT
131
36.2k
    866812U,  // BPXCCNT
132
36.2k
    2106522U, // BPZapn
133
36.2k
    2105880U, // BPZapt
134
36.2k
    2106579U, // BPZnapn
135
36.2k
    2107505U, // BPZnapt
136
36.2k
    4983U,  // BSHUFFLE
137
36.2k
    74742U, // CALL
138
36.2k
    17398U, // CALLri
139
36.2k
    17398U, // CALLrr
140
36.2k
    924148U,  // CASXrr
141
36.2k
    924129U,  // CASrr
142
36.2k
    74001U, // CMASK16
143
36.2k
    73833U, // CMASK32
144
36.2k
    74150U, // CMASK8
145
36.2k
    2106607U, // CMPri
146
36.2k
    2106607U, // CMPrr
147
36.2k
    4332U,  // EDGE16
148
36.2k
    5081U,  // EDGE16L
149
36.2k
    5198U,  // EDGE16LN
150
36.2k
    5165U,  // EDGE16N
151
36.2k
    4164U,  // EDGE32
152
36.2k
    5072U,  // EDGE32L
153
36.2k
    5188U,  // EDGE32LN
154
36.2k
    5156U,  // EDGE32N
155
36.2k
    4511U,  // EDGE8
156
36.2k
    5090U,  // EDGE8L
157
36.2k
    5208U,  // EDGE8LN
158
36.2k
    5174U,  // EDGE8N
159
36.2k
    1053516U, // FABSD
160
36.2k
    1054031U, // FABSQ
161
36.2k
    1054376U, // FABSS
162
36.2k
    4813U,  // FADDD
163
36.2k
    5383U,  // FADDQ
164
36.2k
    5645U,  // FADDS
165
36.2k
    4648U,  // FALIGNADATA
166
36.2k
    4875U,  // FAND
167
36.2k
    4112U,  // FANDNOT1
168
36.2k
    5544U,  // FANDNOT1S
169
36.2k
    4271U,  // FANDNOT2
170
36.2k
    5591U,  // FANDNOT2S
171
36.2k
    5677U,  // FANDS
172
36.2k
    1194491U, // FBCOND
173
36.2k
    1260027U, // FBCONDA
174
36.2k
    4394U,  // FCHKSM16
175
36.2k
    2106173U, // FCMPD
176
36.2k
    4413U,  // FCMPEQ16
177
36.2k
    4226U,  // FCMPEQ32
178
36.2k
    4432U,  // FCMPGT16
179
36.2k
    4245U,  // FCMPGT32
180
36.2k
    4340U,  // FCMPLE16
181
36.2k
    4172U,  // FCMPLE32
182
36.2k
    4350U,  // FCMPNE16
183
36.2k
    4182U,  // FCMPNE32
184
36.2k
    2106696U, // FCMPQ
185
36.2k
    2107005U, // FCMPS
186
36.2k
    4960U,  // FDIVD
187
36.2k
    5475U,  // FDIVQ
188
36.2k
    5815U,  // FDIVS
189
36.2k
    5405U,  // FDMULQ
190
36.2k
    1053620U, // FDTOI
191
36.2k
    1053996U, // FDTOQ
192
36.2k
    1054305U, // FDTOS
193
36.2k
    1054536U, // FDTOX
194
36.2k
    1053464U, // FEXPAND
195
36.2k
    4820U,  // FHADDD
196
36.2k
    5652U,  // FHADDS
197
36.2k
    4800U,  // FHSUBD
198
36.2k
    5637U,  // FHSUBS
199
36.2k
    1053473U, // FITOD
200
36.2k
    1054003U, // FITOQ
201
36.2k
    1054312U, // FITOS
202
36.2k
    6300484U, // FLCMPD
203
36.2k
    6301316U, // FLCMPS
204
36.2k
    2606U,  // FLUSHW
205
36.2k
    4404U,  // FMEAN16
206
36.2k
    1053543U, // FMOVD
207
36.2k
    1006078U, // FMOVD_FCC
208
36.2k
    23484926U,  // FMOVD_ICC
209
36.2k
    23747070U,  // FMOVD_XCC
210
36.2k
    1054058U, // FMOVQ
211
36.2k
    1006102U, // FMOVQ_FCC
212
36.2k
    23484950U,  // FMOVQ_ICC
213
36.2k
    23747094U,  // FMOVQ_XCC
214
36.2k
    6018U,  // FMOVRGEZD
215
36.2k
    6029U,  // FMOVRGEZQ
216
36.2k
    6056U,  // FMOVRGEZS
217
36.2k
    6116U,  // FMOVRGZD
218
36.2k
    6126U,  // FMOVRGZQ
219
36.2k
    6150U,  // FMOVRGZS
220
36.2k
    6067U,  // FMOVRLEZD
221
36.2k
    6078U,  // FMOVRLEZQ
222
36.2k
    6105U,  // FMOVRLEZS
223
36.2k
    6160U,  // FMOVRLZD
224
36.2k
    6170U,  // FMOVRLZQ
225
36.2k
    6194U,  // FMOVRLZS
226
36.2k
    6204U,  // FMOVRNZD
227
36.2k
    6214U,  // FMOVRNZQ
228
36.2k
    6238U,  // FMOVRNZS
229
36.2k
    6009U,  // FMOVRZD
230
36.2k
    6248U,  // FMOVRZQ
231
36.2k
    6269U,  // FMOVRZS
232
36.2k
    1054398U, // FMOVS
233
36.2k
    1006114U, // FMOVS_FCC
234
36.2k
    23484962U,  // FMOVS_ICC
235
36.2k
    23747106U,  // FMOVS_XCC
236
36.2k
    4490U,  // FMUL8SUX16
237
36.2k
    4465U,  // FMUL8ULX16
238
36.2k
    4442U,  // FMUL8X16
239
36.2k
    5098U,  // FMUL8X16AL
240
36.2k
    5849U,  // FMUL8X16AU
241
36.2k
    4860U,  // FMULD
242
36.2k
    4477U,  // FMULD8SUX16
243
36.2k
    4452U,  // FMULD8ULX16
244
36.2k
    5413U,  // FMULQ
245
36.2k
    5714U,  // FMULS
246
36.2k
    4837U,  // FNADDD
247
36.2k
    5669U,  // FNADDS
248
36.2k
    4881U,  // FNAND
249
36.2k
    5684U,  // FNANDS
250
36.2k
    1053429U, // FNEGD
251
36.2k
    1053974U, // FNEGQ
252
36.2k
    1054283U, // FNEGS
253
36.2k
    4828U,  // FNHADDD
254
36.2k
    5660U,  // FNHADDS
255
36.2k
    4828U,  // FNMULD
256
36.2k
    5660U,  // FNMULS
257
36.2k
    5513U,  // FNOR
258
36.2k
    5778U,  // FNORS
259
36.2k
    1052698U, // FNOT1
260
36.2k
    1054131U, // FNOT1S
261
36.2k
    1052857U, // FNOT2
262
36.2k
    1054178U, // FNOT2S
263
36.2k
    5660U,  // FNSMULD
264
36.2k
    74625U, // FONE
265
36.2k
    75324U, // FONES
266
36.2k
    5508U,  // FOR
267
36.2k
    4129U,  // FORNOT1
268
36.2k
    5563U,  // FORNOT1S
269
36.2k
    4288U,  // FORNOT2
270
36.2k
    5610U,  // FORNOT2S
271
36.2k
    5772U,  // FORS
272
36.2k
    1052936U, // FPACK16
273
36.2k
    4192U,  // FPACK32
274
36.2k
    1054507U, // FPACKFIX
275
36.2k
    4323U,  // FPADD16
276
36.2k
    5620U,  // FPADD16S
277
36.2k
    4155U,  // FPADD32
278
36.2k
    5573U,  // FPADD32S
279
36.2k
    4297U,  // FPADD64
280
36.2k
    4974U,  // FPMERGE
281
36.2k
    4314U,  // FPSUB16
282
36.2k
    4580U,  // FPSUB16S
283
36.2k
    4146U,  // FPSUB32
284
36.2k
    4570U,  // FPSUB32S
285
36.2k
    1053480U, // FQTOD
286
36.2k
    1053627U, // FQTOI
287
36.2k
    1054319U, // FQTOS
288
36.2k
    1054552U, // FQTOX
289
36.2k
    4423U,  // FSLAS16
290
36.2k
    4236U,  // FSLAS32
291
36.2k
    4378U,  // FSLL16
292
36.2k
    4210U,  // FSLL32
293
36.2k
    4867U,  // FSMULD
294
36.2k
    1053523U, // FSQRTD
295
36.2k
    1054038U, // FSQRTQ
296
36.2k
    1054383U, // FSQRTS
297
36.2k
    4306U,  // FSRA16
298
36.2k
    4138U,  // FSRA32
299
36.2k
    1052681U, // FSRC1
300
36.2k
    1054112U, // FSRC1S
301
36.2k
    1052840U, // FSRC2
302
36.2k
    1054159U, // FSRC2S
303
36.2k
    4386U,  // FSRL16
304
36.2k
    4218U,  // FSRL32
305
36.2k
    1053487U, // FSTOD
306
36.2k
    1053634U, // FSTOI
307
36.2k
    1054010U, // FSTOQ
308
36.2k
    1054559U, // FSTOX
309
36.2k
    4793U,  // FSUBD
310
36.2k
    5376U,  // FSUBQ
311
36.2k
    5630U,  // FSUBS
312
36.2k
    5519U,  // FXNOR
313
36.2k
    5785U,  // FXNORS
314
36.2k
    5526U,  // FXOR
315
36.2k
    5793U,  // FXORS
316
36.2k
    1053494U, // FXTOD
317
36.2k
    1054017U, // FXTOQ
318
36.2k
    1054326U, // FXTOS
319
36.2k
    74984U, // FZERO
320
36.2k
    75353U, // FZEROS
321
36.2k
    24584U, // GETPCX
322
36.2k
    1078273U, // JMPLri
323
36.2k
    1078273U, // JMPLrr
324
36.2k
    1997243U, // LDDFri
325
36.2k
    1997243U, // LDDFrr
326
36.2k
    1997249U, // LDFri
327
36.2k
    1997249U, // LDFrr
328
36.2k
    1997275U, // LDQFri
329
36.2k
    1997275U, // LDQFrr
330
36.2k
    1997229U, // LDSBri
331
36.2k
    1997229U, // LDSBrr
332
36.2k
    1997254U, // LDSHri
333
36.2k
    1997254U, // LDSHrr
334
36.2k
    1997287U, // LDSWri
335
36.2k
    1997287U, // LDSWrr
336
36.2k
    1997236U, // LDUBri
337
36.2k
    1997236U, // LDUBrr
338
36.2k
    1997261U, // LDUHri
339
36.2k
    1997261U, // LDUHrr
340
36.2k
    1997294U, // LDXri
341
36.2k
    1997294U, // LDXrr
342
36.2k
    1997249U, // LDri
343
36.2k
    1997249U, // LDrr
344
36.2k
    33480U, // LEAX_ADDri
345
36.2k
    33480U, // LEA_ADDri
346
36.2k
    1054405U, // LZCNT
347
36.2k
    75121U, // MEMBARi
348
36.2k
    1054543U, // MOVDTOX
349
36.2k
    1006122U, // MOVFCCri
350
36.2k
    1006122U, // MOVFCCrr
351
36.2k
    23484970U,  // MOVICCri
352
36.2k
    23484970U,  // MOVICCrr
353
36.2k
    6047U,  // MOVRGEZri
354
36.2k
    6047U,  // MOVRGEZrr
355
36.2k
    6142U,  // MOVRGZri
356
36.2k
    6142U,  // MOVRGZrr
357
36.2k
    6096U,  // MOVRLEZri
358
36.2k
    6096U,  // MOVRLEZrr
359
36.2k
    6186U,  // MOVRLZri
360
36.2k
    6186U,  // MOVRLZrr
361
36.2k
    6230U,  // MOVRNZri
362
36.2k
    6230U,  // MOVRNZrr
363
36.2k
    6262U,  // MOVRRZri
364
36.2k
    6262U,  // MOVRRZrr
365
36.2k
    1054469U, // MOVSTOSW
366
36.2k
    1054479U, // MOVSTOUW
367
36.2k
    1054543U, // MOVWTOS
368
36.2k
    23747114U,  // MOVXCCri
369
36.2k
    23747114U,  // MOVXCCrr
370
36.2k
    1054543U, // MOVXTOD
371
36.2k
    5954U,  // MULXri
372
36.2k
    5954U,  // MULXrr
373
36.2k
    2578U,  // NOP
374
36.2k
    4735U,  // ORCCri
375
36.2k
    4735U,  // ORCCrr
376
36.2k
    4726U,  // ORNCCri
377
36.2k
    4726U,  // ORNCCrr
378
36.2k
    5339U,  // ORNri
379
36.2k
    5339U,  // ORNrr
380
36.2k
    5339U,  // ORXNrr
381
36.2k
    5509U,  // ORXri
382
36.2k
    5509U,  // ORXrr
383
36.2k
    5509U,  // ORri
384
36.2k
    5509U,  // ORrr
385
36.2k
    5836U,  // PDIST
386
36.2k
    5344U,  // PDISTN
387
36.2k
    1053356U, // POPCrr
388
36.2k
    73729U, // RDY
389
36.2k
    4999U,  // RESTOREri
390
36.2k
    4999U,  // RESTORErr
391
36.2k
    76132U, // RET
392
36.2k
    76141U, // RETL
393
36.2k
    18131U, // RETTri
394
36.2k
    18131U, // RETTrr
395
36.2k
    5008U,  // SAVEri
396
36.2k
    5008U,  // SAVErr
397
36.2k
    4748U,  // SDIVCCri
398
36.2k
    4748U,  // SDIVCCrr
399
36.2k
    5995U,  // SDIVXri
400
36.2k
    5995U,  // SDIVXrr
401
36.2k
    5861U,  // SDIVri
402
36.2k
    5861U,  // SDIVrr
403
36.2k
    2182U,  // SELECT_CC_DFP_FCC
404
36.2k
    2293U,  // SELECT_CC_DFP_ICC
405
36.2k
    2238U,  // SELECT_CC_FP_FCC
406
36.2k
    2349U,  // SELECT_CC_FP_ICC
407
36.2k
    2265U,  // SELECT_CC_Int_FCC
408
36.2k
    2376U,  // SELECT_CC_Int_ICC
409
36.2k
    2210U,  // SELECT_CC_QFP_FCC
410
36.2k
    2321U,  // SELECT_CC_QFP_ICC
411
36.2k
    1053595U, // SETHIXi
412
36.2k
    1053595U, // SETHIi
413
36.2k
    2569U,  // SHUTDOWN
414
36.2k
    2564U,  // SIAM
415
36.2k
    5941U,  // SLLXri
416
36.2k
    5941U,  // SLLXrr
417
36.2k
    5116U,  // SLLri
418
36.2k
    5116U,  // SLLrr
419
36.2k
    4702U,  // SMULCCri
420
36.2k
    4702U,  // SMULCCrr
421
36.2k
    5144U,  // SMULri
422
36.2k
    5144U,  // SMULrr
423
36.2k
    5913U,  // SRAXri
424
36.2k
    5913U,  // SRAXrr
425
36.2k
    4643U,  // SRAri
426
36.2k
    4643U,  // SRArr
427
36.2k
    5947U,  // SRLXri
428
36.2k
    5947U,  // SRLXrr
429
36.2k
    5139U,  // SRLri
430
36.2k
    5139U,  // SRLrr
431
36.2k
    2588U,  // STBAR
432
36.2k
    37428U, // STBri
433
36.2k
    37428U, // STBrr
434
36.2k
    37723U, // STDFri
435
36.2k
    37723U, // STDFrr
436
36.2k
    38607U, // STFri
437
36.2k
    38607U, // STFrr
438
36.2k
    37782U, // STHri
439
36.2k
    37782U, // STHrr
440
36.2k
    38238U, // STQFri
441
36.2k
    38238U, // STQFrr
442
36.2k
    38758U, // STXri
443
36.2k
    38758U, // STXrr
444
36.2k
    38607U, // STri
445
36.2k
    38607U, // STrr
446
36.2k
    4671U,  // SUBCCri
447
36.2k
    4671U,  // SUBCCrr
448
36.2k
    5919U,  // SUBCri
449
36.2k
    5919U,  // SUBCrr
450
36.2k
    4764U,  // SUBEri
451
36.2k
    4764U,  // SUBErr
452
36.2k
    4665U,  // SUBXri
453
36.2k
    4665U,  // SUBXrr
454
36.2k
    4665U,  // SUBri
455
36.2k
    4665U,  // SUBrr
456
36.2k
    1997268U, // SWAPri
457
36.2k
    1997268U, // SWAPrr
458
36.2k
    2422U,  // TA3
459
36.2k
    2427U,  // TA5
460
36.2k
    5883U,  // TADDCCTVri
461
36.2k
    5883U,  // TADDCCTVrr
462
36.2k
    4687U,  // TADDCCri
463
36.2k
    4687U,  // TADDCCrr
464
36.2k
    9873960U, // TICCri
465
36.2k
    9873960U, // TICCrr
466
36.2k
    37753544U,  // TLS_ADDXrr
467
36.2k
    37753544U,  // TLS_ADDrr
468
36.2k
    2106358U, // TLS_CALL
469
36.2k
    39746030U,  // TLS_LDXrr
470
36.2k
    39745985U,  // TLS_LDrr
471
36.2k
    5873U,  // TSUBCCTVri
472
36.2k
    5873U,  // TSUBCCTVrr
473
36.2k
    4670U,  // TSUBCCri
474
36.2k
    4670U,  // TSUBCCrr
475
36.2k
    10136104U,  // TXCCri
476
36.2k
    10136104U,  // TXCCrr
477
36.2k
    4756U,  // UDIVCCri
478
36.2k
    4756U,  // UDIVCCrr
479
36.2k
    6002U,  // UDIVXri
480
36.2k
    6002U,  // UDIVXrr
481
36.2k
    5867U,  // UDIVri
482
36.2k
    5867U,  // UDIVrr
483
36.2k
    4710U,  // UMULCCri
484
36.2k
    4710U,  // UMULCCrr
485
36.2k
    5026U,  // UMULXHI
486
36.2k
    5150U,  // UMULri
487
36.2k
    5150U,  // UMULrr
488
36.2k
    74996U, // UNIMP
489
36.2k
    6300477U, // V9FCMPD
490
36.2k
    6300397U, // V9FCMPED
491
36.2k
    6300942U, // V9FCMPEQ
492
36.2k
    6301251U, // V9FCMPES
493
36.2k
    6301000U, // V9FCMPQ
494
36.2k
    6301309U, // V9FCMPS
495
36.2k
    47614U, // V9FMOVD_FCC
496
36.2k
    47638U, // V9FMOVQ_FCC
497
36.2k
    47650U, // V9FMOVS_FCC
498
36.2k
    47658U, // V9MOVFCCri
499
36.2k
    47658U, // V9MOVFCCrr
500
36.2k
    14689692U,  // WRYri
501
36.2k
    14689692U,  // WRYrr
502
36.2k
    5953U,  // XMULX
503
36.2k
    5035U,  // XMULXHI
504
36.2k
    4733U,  // XNORCCri
505
36.2k
    4733U,  // XNORCCrr
506
36.2k
    5520U,  // XNORXrr
507
36.2k
    5520U,  // XNORri
508
36.2k
    5520U,  // XNORrr
509
36.2k
    4741U,  // XORCCri
510
36.2k
    4741U,  // XORCCrr
511
36.2k
    5527U,  // XORXri
512
36.2k
    5527U,  // XORXrr
513
36.2k
    5527U,  // XORri
514
36.2k
    5527U,  // XORrr
515
36.2k
    0U
516
36.2k
  };
517
518
36.2k
#ifndef CAPSTONE_DIET
519
36.2k
  static const char AsmStrs[] = {
520
36.2k
  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521
36.2k
  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522
36.2k
  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523
36.2k
  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524
36.2k
  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525
36.2k
  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526
36.2k
  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527
36.2k
  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528
36.2k
  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529
36.2k
  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530
36.2k
  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531
36.2k
  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532
36.2k
  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533
36.2k
  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534
36.2k
  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535
36.2k
  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536
36.2k
  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537
36.2k
  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538
36.2k
  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539
36.2k
  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540
36.2k
  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541
36.2k
  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542
36.2k
  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543
36.2k
  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544
36.2k
  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545
36.2k
  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546
36.2k
  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547
36.2k
  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548
36.2k
  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549
36.2k
  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550
36.2k
  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551
36.2k
  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552
36.2k
  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553
36.2k
  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554
36.2k
  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555
36.2k
  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556
36.2k
  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557
36.2k
  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558
36.2k
  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559
36.2k
  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560
36.2k
  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561
36.2k
  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562
36.2k
  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563
36.2k
  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564
36.2k
  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565
36.2k
  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566
36.2k
  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567
36.2k
  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568
36.2k
  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569
36.2k
  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570
36.2k
  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571
36.2k
  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572
36.2k
  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573
36.2k
  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574
36.2k
  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575
36.2k
  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576
36.2k
  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577
36.2k
  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578
36.2k
  /* 542 */ 'b', 'a', 32, 0,
579
36.2k
  /* 546 */ 's', 'r', 'a', 32, 0,
580
36.2k
  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581
36.2k
  /* 563 */ 's', 't', 'b', 32, 0,
582
36.2k
  /* 568 */ 's', 'u', 'b', 32, 0,
583
36.2k
  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584
36.2k
  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585
36.2k
  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586
36.2k
  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587
36.2k
  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588
36.2k
  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589
36.2k
  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590
36.2k
  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591
36.2k
  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592
36.2k
  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593
36.2k
  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594
36.2k
  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595
36.2k
  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596
36.2k
  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597
36.2k
  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598
36.2k
  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599
36.2k
  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600
36.2k
  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601
36.2k
  /* 711 */ 'a', 'd', 'd', 32, 0,
602
36.2k
  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603
36.2k
  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604
36.2k
  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605
36.2k
  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606
36.2k
  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607
36.2k
  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608
36.2k
  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609
36.2k
  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610
36.2k
  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611
36.2k
  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612
36.2k
  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613
36.2k
  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614
36.2k
  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615
36.2k
  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616
36.2k
  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617
36.2k
  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618
36.2k
  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619
36.2k
  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620
36.2k
  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621
36.2k
  /* 858 */ 's', 't', 'd', 32, 0,
622
36.2k
  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623
36.2k
  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624
36.2k
  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625
36.2k
  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626
36.2k
  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627
36.2k
  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628
36.2k
  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629
36.2k
  /* 917 */ 's', 't', 'h', 32, 0,
630
36.2k
  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631
36.2k
  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632
36.2k
  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633
36.2k
  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634
36.2k
  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635
36.2k
  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636
36.2k
  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637
36.2k
  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638
36.2k
  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639
36.2k
  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640
36.2k
  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641
36.2k
  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642
36.2k
  /* 1019 */ 's', 'l', 'l', 32, 0,
643
36.2k
  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644
36.2k
  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645
36.2k
  /* 1042 */ 's', 'r', 'l', 32, 0,
646
36.2k
  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647
36.2k
  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648
36.2k
  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649
36.2k
  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650
36.2k
  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651
36.2k
  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652
36.2k
  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653
36.2k
  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654
36.2k
  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655
36.2k
  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656
36.2k
  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657
36.2k
  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658
36.2k
  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659
36.2k
  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660
36.2k
  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661
36.2k
  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662
36.2k
  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663
36.2k
  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664
36.2k
  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665
36.2k
  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666
36.2k
  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667
36.2k
  /* 1242 */ 'o', 'r', 'n', 32, 0,
668
36.2k
  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669
36.2k
  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670
36.2k
  /* 1262 */ 'c', 'm', 'p', 32, 0,
671
36.2k
  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672
36.2k
  /* 1274 */ 'j', 'm', 'p', 32, 0,
673
36.2k
  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674
36.2k
  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675
36.2k
  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676
36.2k
  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677
36.2k
  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678
36.2k
  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679
36.2k
  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680
36.2k
  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681
36.2k
  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682
36.2k
  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683
36.2k
  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684
36.2k
  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685
36.2k
  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686
36.2k
  /* 1373 */ 's', 't', 'q', 32, 0,
687
36.2k
  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688
36.2k
  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689
36.2k
  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690
36.2k
  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691
36.2k
  /* 1411 */ 'f', 'o', 'r', 32, 0,
692
36.2k
  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693
36.2k
  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694
36.2k
  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695
36.2k
  /* 1435 */ 'w', 'r', 32, 0,
696
36.2k
  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697
36.2k
  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698
36.2k
  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699
36.2k
  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700
36.2k
  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701
36.2k
  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702
36.2k
  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703
36.2k
  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704
36.2k
  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705
36.2k
  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706
36.2k
  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707
36.2k
  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708
36.2k
  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709
36.2k
  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710
36.2k
  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711
36.2k
  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712
36.2k
  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713
36.2k
  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714
36.2k
  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715
36.2k
  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716
36.2k
  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717
36.2k
  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718
36.2k
  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719
36.2k
  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720
36.2k
  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721
36.2k
  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722
36.2k
  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723
36.2k
  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724
36.2k
  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725
36.2k
  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726
36.2k
  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727
36.2k
  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728
36.2k
  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729
36.2k
  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730
36.2k
  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731
36.2k
  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732
36.2k
  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733
36.2k
  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734
36.2k
  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735
36.2k
  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736
36.2k
  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737
36.2k
  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738
36.2k
  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739
36.2k
  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740
36.2k
  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741
36.2k
  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742
36.2k
  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743
36.2k
  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744
36.2k
  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745
36.2k
  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746
36.2k
  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747
36.2k
  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748
36.2k
  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749
36.2k
  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750
36.2k
  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751
36.2k
  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752
36.2k
  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753
36.2k
  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754
36.2k
  /* 1893 */ 's', 't', 'x', 32, 0,
755
36.2k
  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756
36.2k
  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757
36.2k
  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758
36.2k
  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759
36.2k
  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760
36.2k
  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761
36.2k
  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762
36.2k
  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763
36.2k
  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764
36.2k
  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765
36.2k
  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766
36.2k
  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767
36.2k
  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768
36.2k
  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769
36.2k
  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770
36.2k
  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771
36.2k
  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772
36.2k
  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773
36.2k
  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774
36.2k
  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775
36.2k
  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776
36.2k
  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777
36.2k
  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778
36.2k
  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779
36.2k
  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780
36.2k
  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781
36.2k
  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782
36.2k
  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783
36.2k
  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784
36.2k
  /* 2160 */ 'b', 'r', 'z', 32, 0,
785
36.2k
  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786
36.2k
  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787
36.2k
  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788
36.2k
  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789
36.2k
  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790
36.2k
  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791
36.2k
  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792
36.2k
  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793
36.2k
  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794
36.2k
  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795
36.2k
  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796
36.2k
  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797
36.2k
  /* 2421 */ 't', 'a', 32, '3', 0,
798
36.2k
  /* 2426 */ 't', 'a', 32, '5', 0,
799
36.2k
  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800
36.2k
  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801
36.2k
  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802
36.2k
  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803
36.2k
  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804
36.2k
  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805
36.2k
  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806
36.2k
  /* 2496 */ 'l', 'd', 32, '[', 0,
807
36.2k
  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808
36.2k
  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809
36.2k
  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810
36.2k
  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811
36.2k
  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812
36.2k
  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813
36.2k
  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814
36.2k
  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815
36.2k
  /* 2554 */ 'f', 'b', 0,
816
36.2k
  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817
36.2k
  /* 2563 */ 's', 'i', 'a', 'm', 0,
818
36.2k
  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819
36.2k
  /* 2577 */ 'n', 'o', 'p', 0,
820
36.2k
  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821
36.2k
  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822
36.2k
  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823
36.2k
  /* 2599 */ 't', 0,
824
36.2k
  /* 2601 */ 'm', 'o', 'v', 0,
825
36.2k
  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826
36.2k
  };
827
36.2k
#endif
828
829
  // Emit the opcode for the instruction.
830
36.2k
  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831
36.2k
#ifndef CAPSTONE_DIET
832
  // assert(Bits != 0 && "Cannot print this instruction.");
833
36.2k
  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834
36.2k
#endif
835
836
837
  // Fragment 0 encoded into 4 bits for 12 unique commands.
838
  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839
36.2k
  switch ((Bits >> 12) & 15) {
840
0
  default:   // unreachable.
841
130
  case 0:
842
    // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843
130
    return;
844
0
    break;
845
7.66k
  case 1:
846
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847
7.66k
    printOperand(MI, 1, O); 
848
7.66k
    break;
849
19.4k
  case 2:
850
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851
19.4k
    printOperand(MI, 0, O); 
852
19.4k
    break;
853
2.81k
  case 3:
854
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855
2.81k
    printCCOperand(MI, 1, O); 
856
2.81k
    break;
857
99
  case 4:
858
    // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859
99
    printMemOperand(MI, 0, O, NULL); 
860
99
    return;
861
0
    break;
862
1.64k
  case 5:
863
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864
1.64k
    printCCOperand(MI, 3, O); 
865
1.64k
    break;
866
0
  case 6:
867
    // GETPCX
868
0
    printGetPCX(MI, 0, O); 
869
0
    return;
870
0
    break;
871
2.40k
  case 7:
872
    // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873
2.40k
    printMemOperand(MI, 1, O, NULL); 
874
2.40k
    break;
875
0
  case 8:
876
    // LEAX_ADDri, LEA_ADDri
877
0
    printMemOperand(MI, 1, O, "arith"); 
878
0
    SStream_concat0(O, ", "); 
879
0
    printOperand(MI, 0, O); 
880
0
    return;
881
0
    break;
882
1.05k
  case 9:
883
    // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884
1.05k
    printOperand(MI, 2, O); 
885
1.05k
    SStream_concat0(O, ", ["); 
886
1.05k
    printMemOperand(MI, 0, O, NULL); 
887
1.05k
    SStream_concat0(O, "]"); 
888
1.05k
    return;
889
0
    break;
890
426
  case 10:
891
    // TICCri, TICCrr, TXCCri, TXCCrr
892
426
    printCCOperand(MI, 2, O); 
893
426
    break;
894
585
  case 11:
895
    // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896
585
    printCCOperand(MI, 4, O); 
897
585
    SStream_concat0(O, " "); 
898
585
    printOperand(MI, 1, O); 
899
585
    SStream_concat0(O, ", "); 
900
585
    printOperand(MI, 2, O); 
901
585
    SStream_concat0(O, ", "); 
902
585
    printOperand(MI, 0, O); 
903
585
    return;
904
0
    break;
905
36.2k
  }
906
907
908
  // Fragment 1 encoded into 4 bits for 16 unique commands.
909
  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910
34.3k
  switch ((Bits >> 16) & 15) {
911
0
  default:   // unreachable.
912
12.1k
  case 0:
913
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914
12.1k
    SStream_concat0(O, ", "); 
915
12.1k
    break;
916
14.9k
  case 1:
917
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918
14.9k
    return;
919
0
    break;
920
939
  case 2:
921
    // BCOND, BPFCC, FBCOND
922
939
    SStream_concat0(O, " "); 
923
939
    break;
924
908
  case 3:
925
    // BCONDA, BPFCCA, FBCONDA
926
908
    SStream_concat0(O, ",a ");
927
908
  Sparc_add_hint(MI, SPARC_HINT_A);
928
908
    break;
929
0
  case 4:
930
    // BPFCCANT
931
0
    SStream_concat0(O, ",a,pn ");
932
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933
0
    printOperand(MI, 2, O); 
934
0
    SStream_concat0(O, ", "); 
935
0
    printOperand(MI, 0, O); 
936
0
    return;
937
0
    break;
938
0
  case 5:
939
    // BPFCCNT
940
0
    SStream_concat0(O, ",pn ");
941
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
942
0
    printOperand(MI, 2, O); 
943
0
    SStream_concat0(O, ", "); 
944
0
    printOperand(MI, 0, O); 
945
0
    return;
946
0
    break;
947
1.39k
  case 6:
948
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949
1.39k
    SStream_concat0(O, " %icc, ");
950
1.39k
  Sparc_add_reg(MI, SPARC_REG_ICC);
951
1.39k
    break;
952
43
  case 7:
953
    // BPICCA
954
43
    SStream_concat0(O, ",a %icc, ");
955
43
  Sparc_add_hint(MI, SPARC_HINT_A);
956
43
  Sparc_add_reg(MI, SPARC_REG_ICC);
957
43
    printOperand(MI, 0, O); 
958
43
    return;
959
0
    break;
960
0
  case 8:
961
    // BPICCANT
962
0
    SStream_concat0(O, ",a,pn %icc, ");
963
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
965
0
    printOperand(MI, 0, O); 
966
0
    return;
967
0
    break;
968
0
  case 9:
969
    // BPICCNT
970
0
    SStream_concat0(O, ",pn %icc, ");
971
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
972
0
  Sparc_add_reg(MI, SPARC_REG_ICC);
973
0
    printOperand(MI, 0, O); 
974
0
    return;
975
0
    break;
976
988
  case 10:
977
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978
988
    SStream_concat0(O, " %xcc, ");
979
988
  Sparc_add_reg(MI, SPARC_REG_XCC);
980
988
    break;
981
124
  case 11:
982
    // BPXCCA
983
124
    SStream_concat0(O, ",a %xcc, ");
984
124
  Sparc_add_hint(MI, SPARC_HINT_A);
985
124
  Sparc_add_reg(MI, SPARC_REG_XCC);
986
124
    printOperand(MI, 0, O); 
987
124
    return;
988
0
    break;
989
0
  case 12:
990
    // BPXCCANT
991
0
    SStream_concat0(O, ",a,pn %xcc, ");
992
0
  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
994
0
    printOperand(MI, 0, O); 
995
0
    return;
996
0
    break;
997
0
  case 13:
998
    // BPXCCNT
999
0
    SStream_concat0(O, ",pn %xcc, ");
1000
0
  Sparc_add_hint(MI, SPARC_HINT_PN);
1001
0
  Sparc_add_reg(MI, SPARC_REG_XCC);
1002
0
    printOperand(MI, 0, O); 
1003
0
    return;
1004
0
    break;
1005
2.33k
  case 14:
1006
    // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007
2.33k
    SStream_concat0(O, "], "); 
1008
2.33k
    break;
1009
480
  case 15:
1010
    // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011
480
    SStream_concat0(O, " %fcc0, ");
1012
480
  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013
480
    printOperand(MI, 1, O); 
1014
480
    SStream_concat0(O, ", "); 
1015
480
    printOperand(MI, 0, O); 
1016
480
    return;
1017
0
    break;
1018
34.3k
  }
1019
1020
1021
  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022
  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023
18.7k
  switch ((Bits >> 20) & 3) {
1024
0
  default:   // unreachable.
1025
4.31k
  case 0:
1026
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027
4.31k
    printOperand(MI, 2, O); 
1028
4.31k
    SStream_concat0(O, ", "); 
1029
4.31k
    printOperand(MI, 0, O); 
1030
4.31k
    break;
1031
8.82k
  case 1:
1032
    // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033
8.82k
    printOperand(MI, 0, O); 
1034
8.82k
    break;
1035
5.63k
  case 2:
1036
    // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037
5.63k
    printOperand(MI, 1, O); 
1038
5.63k
    break;
1039
18.7k
  }
1040
1041
1042
  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043
  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044
18.7k
  switch ((Bits >> 22) & 3) {
1045
0
  default:   // unreachable.
1046
15.9k
  case 0:
1047
    // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048
15.9k
    return;
1049
0
    break;
1050
2.25k
  case 1:
1051
    // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052
2.25k
    SStream_concat0(O, ", "); 
1053
2.25k
    break;
1054
426
  case 2:
1055
    // TICCri, TICCrr, TXCCri, TXCCrr
1056
426
    SStream_concat0(O, " + ");  // qq
1057
426
    printOperand(MI, 1, O); 
1058
426
    return;
1059
0
    break;
1060
93
  case 3:
1061
    // WRYri, WRYrr
1062
93
    SStream_concat0(O, ", %y");
1063
93
  Sparc_add_reg(MI, SPARC_REG_Y);
1064
93
    return;
1065
0
    break;
1066
18.7k
  }
1067
1068
1069
  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070
  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071
2.25k
  switch ((Bits >> 24) & 3) {
1072
0
  default:   // unreachable.
1073
1.09k
  case 0:
1074
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075
1.09k
    printOperand(MI, 2, O); 
1076
1.09k
    return;
1077
0
    break;
1078
1.16k
  case 1:
1079
    // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080
1.16k
    printOperand(MI, 0, O); 
1081
1.16k
    return;
1082
0
    break;
1083
0
  case 2:
1084
    // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085
0
    printOperand(MI, 3, O); 
1086
0
    return;
1087
0
    break;
1088
2.25k
  }
1089
2.25k
}
1090
1091
1092
/// getRegisterName - This method is automatically generated by tblgen
1093
/// from the register set description.  This returns the assembler name
1094
/// for the specified register.
1095
static const char *getRegisterName(unsigned RegNo)
1096
50.3k
{
1097
  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098
1099
50.3k
#ifndef CAPSTONE_DIET
1100
50.3k
  static const char AsmStrs[] = {
1101
50.3k
  /* 0 */ 'f', '1', '0', 0,
1102
50.3k
  /* 4 */ 'f', '2', '0', 0,
1103
50.3k
  /* 8 */ 'f', '3', '0', 0,
1104
50.3k
  /* 12 */ 'f', '4', '0', 0,
1105
50.3k
  /* 16 */ 'f', '5', '0', 0,
1106
50.3k
  /* 20 */ 'f', '6', '0', 0,
1107
50.3k
  /* 24 */ 'f', 'c', 'c', '0', 0,
1108
50.3k
  /* 29 */ 'f', '0', 0,
1109
50.3k
  /* 32 */ 'g', '0', 0,
1110
50.3k
  /* 35 */ 'i', '0', 0,
1111
50.3k
  /* 38 */ 'l', '0', 0,
1112
50.3k
  /* 41 */ 'o', '0', 0,
1113
50.3k
  /* 44 */ 'f', '1', '1', 0,
1114
50.3k
  /* 48 */ 'f', '2', '1', 0,
1115
50.3k
  /* 52 */ 'f', '3', '1', 0,
1116
50.3k
  /* 56 */ 'f', 'c', 'c', '1', 0,
1117
50.3k
  /* 61 */ 'f', '1', 0,
1118
50.3k
  /* 64 */ 'g', '1', 0,
1119
50.3k
  /* 67 */ 'i', '1', 0,
1120
50.3k
  /* 70 */ 'l', '1', 0,
1121
50.3k
  /* 73 */ 'o', '1', 0,
1122
50.3k
  /* 76 */ 'f', '1', '2', 0,
1123
50.3k
  /* 80 */ 'f', '2', '2', 0,
1124
50.3k
  /* 84 */ 'f', '3', '2', 0,
1125
50.3k
  /* 88 */ 'f', '4', '2', 0,
1126
50.3k
  /* 92 */ 'f', '5', '2', 0,
1127
50.3k
  /* 96 */ 'f', '6', '2', 0,
1128
50.3k
  /* 100 */ 'f', 'c', 'c', '2', 0,
1129
50.3k
  /* 105 */ 'f', '2', 0,
1130
50.3k
  /* 108 */ 'g', '2', 0,
1131
50.3k
  /* 111 */ 'i', '2', 0,
1132
50.3k
  /* 114 */ 'l', '2', 0,
1133
50.3k
  /* 117 */ 'o', '2', 0,
1134
50.3k
  /* 120 */ 'f', '1', '3', 0,
1135
50.3k
  /* 124 */ 'f', '2', '3', 0,
1136
50.3k
  /* 128 */ 'f', 'c', 'c', '3', 0,
1137
50.3k
  /* 133 */ 'f', '3', 0,
1138
50.3k
  /* 136 */ 'g', '3', 0,
1139
50.3k
  /* 139 */ 'i', '3', 0,
1140
50.3k
  /* 142 */ 'l', '3', 0,
1141
50.3k
  /* 145 */ 'o', '3', 0,
1142
50.3k
  /* 148 */ 'f', '1', '4', 0,
1143
50.3k
  /* 152 */ 'f', '2', '4', 0,
1144
50.3k
  /* 156 */ 'f', '3', '4', 0,
1145
50.3k
  /* 160 */ 'f', '4', '4', 0,
1146
50.3k
  /* 164 */ 'f', '5', '4', 0,
1147
50.3k
  /* 168 */ 'f', '4', 0,
1148
50.3k
  /* 171 */ 'g', '4', 0,
1149
50.3k
  /* 174 */ 'i', '4', 0,
1150
50.3k
  /* 177 */ 'l', '4', 0,
1151
50.3k
  /* 180 */ 'o', '4', 0,
1152
50.3k
  /* 183 */ 'f', '1', '5', 0,
1153
50.3k
  /* 187 */ 'f', '2', '5', 0,
1154
50.3k
  /* 191 */ 'f', '5', 0,
1155
50.3k
  /* 194 */ 'g', '5', 0,
1156
50.3k
  /* 197 */ 'i', '5', 0,
1157
50.3k
  /* 200 */ 'l', '5', 0,
1158
50.3k
  /* 203 */ 'o', '5', 0,
1159
50.3k
  /* 206 */ 'f', '1', '6', 0,
1160
50.3k
  /* 210 */ 'f', '2', '6', 0,
1161
50.3k
  /* 214 */ 'f', '3', '6', 0,
1162
50.3k
  /* 218 */ 'f', '4', '6', 0,
1163
50.3k
  /* 222 */ 'f', '5', '6', 0,
1164
50.3k
  /* 226 */ 'f', '6', 0,
1165
50.3k
  /* 229 */ 'g', '6', 0,
1166
50.3k
  /* 232 */ 'l', '6', 0,
1167
50.3k
  /* 235 */ 'f', '1', '7', 0,
1168
50.3k
  /* 239 */ 'f', '2', '7', 0,
1169
50.3k
  /* 243 */ 'f', '7', 0,
1170
50.3k
  /* 246 */ 'g', '7', 0,
1171
50.3k
  /* 249 */ 'i', '7', 0,
1172
50.3k
  /* 252 */ 'l', '7', 0,
1173
50.3k
  /* 255 */ 'o', '7', 0,
1174
50.3k
  /* 258 */ 'f', '1', '8', 0,
1175
50.3k
  /* 262 */ 'f', '2', '8', 0,
1176
50.3k
  /* 266 */ 'f', '3', '8', 0,
1177
50.3k
  /* 270 */ 'f', '4', '8', 0,
1178
50.3k
  /* 274 */ 'f', '5', '8', 0,
1179
50.3k
  /* 278 */ 'f', '8', 0,
1180
50.3k
  /* 281 */ 'f', '1', '9', 0,
1181
50.3k
  /* 285 */ 'f', '2', '9', 0,
1182
50.3k
  /* 289 */ 'f', '9', 0,
1183
50.3k
  /* 292 */ 'i', 'c', 'c', 0,
1184
50.3k
  /* 296 */ 'f', 'p', 0,
1185
50.3k
  /* 299 */ 's', 'p', 0,
1186
50.3k
  /* 302 */ 'y', 0,
1187
50.3k
  };
1188
1189
50.3k
  static const uint16_t RegAsmOffset[] = {
1190
50.3k
    292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 
1191
50.3k
    152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 
1192
50.3k
    92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 
1193
50.3k
    278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 
1194
50.3k
    80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 
1195
50.3k
    32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 
1196
50.3k
    296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 
1197
50.3k
    180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 
1198
50.3k
    12, 160, 270, 92, 222, 20, 
1199
50.3k
  };
1200
1201
  //int i;
1202
  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203
  //     printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204
  //printf("*************************\n");
1205
50.3k
  return AsmStrs+RegAsmOffset[RegNo-1];
1206
#else
1207
  return NULL;
1208
#endif
1209
50.3k
}
1210
1211
#ifdef PRINT_ALIAS_INSTR
1212
#undef PRINT_ALIAS_INSTR
1213
1214
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1215
  unsigned PrintMethodIdx, SStream *OS)
1216
0
{
1217
0
}
1218
1219
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1220
63.7k
{
1221
248k
  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1222
63.7k
  const char *AsmString;
1223
63.7k
  char *tmp, *AsmMnem, *AsmOps, *c;
1224
63.7k
  int OpIdx, PrintMethodIdx;
1225
63.7k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1226
63.7k
  switch (MCInst_getOpcode(MI)) {
1227
34.0k
  default: return NULL;
1228
2.07k
  case SP_BCOND:
1229
2.07k
    if (MCInst_getNumOperands(MI) == 2 &&
1230
2.07k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1231
2.07k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1232
      // (BCOND brtarget:$imm, 8)
1233
0
      AsmString = "ba $\x01";
1234
0
      break;
1235
0
    }
1236
2.07k
    if (MCInst_getNumOperands(MI) == 2 &&
1237
2.07k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1238
2.07k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1239
      // (BCOND brtarget:$imm, 0)
1240
217
      AsmString = "bn $\x01";
1241
217
      break;
1242
217
    }
1243
1.85k
    if (MCInst_getNumOperands(MI) == 2 &&
1244
1.85k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1245
1.85k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1246
      // (BCOND brtarget:$imm, 9)
1247
57
      AsmString = "bne $\x01";
1248
57
      break;
1249
57
    }
1250
1.80k
    if (MCInst_getNumOperands(MI) == 2 &&
1251
1.80k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1252
1.80k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1253
      // (BCOND brtarget:$imm, 1)
1254
126
      AsmString = "be $\x01";
1255
126
      break;
1256
126
    }
1257
1.67k
    if (MCInst_getNumOperands(MI) == 2 &&
1258
1.67k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1259
1.67k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1260
      // (BCOND brtarget:$imm, 10)
1261
123
      AsmString = "bg $\x01";
1262
123
      break;
1263
123
    }
1264
1.55k
    if (MCInst_getNumOperands(MI) == 2 &&
1265
1.55k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1266
1.55k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1267
      // (BCOND brtarget:$imm, 2)
1268
266
      AsmString = "ble $\x01";
1269
266
      break;
1270
266
    }
1271
1.28k
    if (MCInst_getNumOperands(MI) == 2 &&
1272
1.28k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1273
1.28k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1274
      // (BCOND brtarget:$imm, 11)
1275
329
      AsmString = "bge $\x01";
1276
329
      break;
1277
329
    }
1278
956
    if (MCInst_getNumOperands(MI) == 2 &&
1279
956
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1280
956
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1281
      // (BCOND brtarget:$imm, 3)
1282
68
      AsmString = "bl $\x01";
1283
68
      break;
1284
68
    }
1285
888
    if (MCInst_getNumOperands(MI) == 2 &&
1286
888
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1287
888
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1288
      // (BCOND brtarget:$imm, 12)
1289
81
      AsmString = "bgu $\x01";
1290
81
      break;
1291
81
    }
1292
807
    if (MCInst_getNumOperands(MI) == 2 &&
1293
807
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1294
807
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1295
      // (BCOND brtarget:$imm, 4)
1296
111
      AsmString = "bleu $\x01";
1297
111
      break;
1298
111
    }
1299
696
    if (MCInst_getNumOperands(MI) == 2 &&
1300
696
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1301
696
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1302
      // (BCOND brtarget:$imm, 13)
1303
67
      AsmString = "bcc $\x01";
1304
67
      break;
1305
67
    }
1306
629
    if (MCInst_getNumOperands(MI) == 2 &&
1307
629
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1308
629
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1309
      // (BCOND brtarget:$imm, 5)
1310
247
      AsmString = "bcs $\x01";
1311
247
      break;
1312
247
    }
1313
382
    if (MCInst_getNumOperands(MI) == 2 &&
1314
382
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1315
382
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1316
      // (BCOND brtarget:$imm, 14)
1317
128
      AsmString = "bpos $\x01";
1318
128
      break;
1319
128
    }
1320
254
    if (MCInst_getNumOperands(MI) == 2 &&
1321
254
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1322
254
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1323
      // (BCOND brtarget:$imm, 6)
1324
124
      AsmString = "bneg $\x01";
1325
124
      break;
1326
124
    }
1327
130
    if (MCInst_getNumOperands(MI) == 2 &&
1328
130
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1329
130
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1330
      // (BCOND brtarget:$imm, 15)
1331
20
      AsmString = "bvc $\x01";
1332
20
      break;
1333
20
    }
1334
110
    if (MCInst_getNumOperands(MI) == 2 &&
1335
110
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1336
110
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1337
      // (BCOND brtarget:$imm, 7)
1338
110
      AsmString = "bvs $\x01";
1339
110
      break;
1340
110
    }
1341
0
    return NULL;
1342
2.18k
  case SP_BCONDA:
1343
2.18k
    if (MCInst_getNumOperands(MI) == 2 &&
1344
2.18k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1345
2.18k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1346
      // (BCONDA brtarget:$imm, 8)
1347
125
      AsmString = "ba,a $\x01";
1348
125
      break;
1349
125
    }
1350
2.05k
    if (MCInst_getNumOperands(MI) == 2 &&
1351
2.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1352
2.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1353
      // (BCONDA brtarget:$imm, 0)
1354
135
      AsmString = "bn,a $\x01";
1355
135
      break;
1356
135
    }
1357
1.92k
    if (MCInst_getNumOperands(MI) == 2 &&
1358
1.92k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1359
1.92k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1360
      // (BCONDA brtarget:$imm, 9)
1361
65
      AsmString = "bne,a $\x01";
1362
65
      break;
1363
65
    }
1364
1.85k
    if (MCInst_getNumOperands(MI) == 2 &&
1365
1.85k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1366
1.85k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1367
      // (BCONDA brtarget:$imm, 1)
1368
42
      AsmString = "be,a $\x01";
1369
42
      break;
1370
42
    }
1371
1.81k
    if (MCInst_getNumOperands(MI) == 2 &&
1372
1.81k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1373
1.81k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1374
      // (BCONDA brtarget:$imm, 10)
1375
97
      AsmString = "bg,a $\x01";
1376
97
      break;
1377
97
    }
1378
1.71k
    if (MCInst_getNumOperands(MI) == 2 &&
1379
1.71k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1380
1.71k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1381
      // (BCONDA brtarget:$imm, 2)
1382
223
      AsmString = "ble,a $\x01";
1383
223
      break;
1384
223
    }
1385
1.49k
    if (MCInst_getNumOperands(MI) == 2 &&
1386
1.49k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1387
1.49k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1388
      // (BCONDA brtarget:$imm, 11)
1389
81
      AsmString = "bge,a $\x01";
1390
81
      break;
1391
81
    }
1392
1.41k
    if (MCInst_getNumOperands(MI) == 2 &&
1393
1.41k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1394
1.41k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1395
      // (BCONDA brtarget:$imm, 3)
1396
44
      AsmString = "bl,a $\x01";
1397
44
      break;
1398
44
    }
1399
1.36k
    if (MCInst_getNumOperands(MI) == 2 &&
1400
1.36k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1401
1.36k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1402
      // (BCONDA brtarget:$imm, 12)
1403
306
      AsmString = "bgu,a $\x01";
1404
306
      break;
1405
306
    }
1406
1.06k
    if (MCInst_getNumOperands(MI) == 2 &&
1407
1.06k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1408
1.06k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1409
      // (BCONDA brtarget:$imm, 4)
1410
220
      AsmString = "bleu,a $\x01";
1411
220
      break;
1412
220
    }
1413
843
    if (MCInst_getNumOperands(MI) == 2 &&
1414
843
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1415
843
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1416
      // (BCONDA brtarget:$imm, 13)
1417
86
      AsmString = "bcc,a $\x01";
1418
86
      break;
1419
86
    }
1420
757
    if (MCInst_getNumOperands(MI) == 2 &&
1421
757
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1422
757
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1423
      // (BCONDA brtarget:$imm, 5)
1424
297
      AsmString = "bcs,a $\x01";
1425
297
      break;
1426
297
    }
1427
460
    if (MCInst_getNumOperands(MI) == 2 &&
1428
460
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1429
460
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1430
      // (BCONDA brtarget:$imm, 14)
1431
239
      AsmString = "bpos,a $\x01";
1432
239
      break;
1433
239
    }
1434
221
    if (MCInst_getNumOperands(MI) == 2 &&
1435
221
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1436
221
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1437
      // (BCONDA brtarget:$imm, 6)
1438
93
      AsmString = "bneg,a $\x01";
1439
93
      break;
1440
93
    }
1441
128
    if (MCInst_getNumOperands(MI) == 2 &&
1442
128
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1443
128
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1444
      // (BCONDA brtarget:$imm, 15)
1445
57
      AsmString = "bvc,a $\x01";
1446
57
      break;
1447
57
    }
1448
71
    if (MCInst_getNumOperands(MI) == 2 &&
1449
71
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1450
71
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1451
      // (BCONDA brtarget:$imm, 7)
1452
71
      AsmString = "bvs,a $\x01";
1453
71
      break;
1454
71
    }
1455
0
    return NULL;
1456
2.13k
  case SP_BPFCCANT:
1457
2.13k
    if (MCInst_getNumOperands(MI) == 3 &&
1458
2.13k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1459
2.13k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1460
112
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1461
112
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1462
      // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1463
112
      AsmString = "fba,a,pn $\x03, $\x01";
1464
112
      break;
1465
112
    }
1466
2.01k
    if (MCInst_getNumOperands(MI) == 3 &&
1467
2.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1468
2.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1469
300
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1470
300
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1471
      // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1472
300
      AsmString = "fbn,a,pn $\x03, $\x01";
1473
300
      break;
1474
300
    }
1475
1.71k
    if (MCInst_getNumOperands(MI) == 3 &&
1476
1.71k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1477
1.71k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1478
82
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1479
82
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1480
      // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1481
82
      AsmString = "fbu,a,pn $\x03, $\x01";
1482
82
      break;
1483
82
    }
1484
1.63k
    if (MCInst_getNumOperands(MI) == 3 &&
1485
1.63k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1486
1.63k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1487
483
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1488
483
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1489
      // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1490
483
      AsmString = "fbg,a,pn $\x03, $\x01";
1491
483
      break;
1492
483
    }
1493
1.15k
    if (MCInst_getNumOperands(MI) == 3 &&
1494
1.15k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1495
1.15k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1496
166
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1497
166
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1498
      // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1499
166
      AsmString = "fbug,a,pn $\x03, $\x01";
1500
166
      break;
1501
166
    }
1502
987
    if (MCInst_getNumOperands(MI) == 3 &&
1503
987
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1504
987
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1505
44
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1506
44
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1507
      // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1508
44
      AsmString = "fbl,a,pn $\x03, $\x01";
1509
44
      break;
1510
44
    }
1511
943
    if (MCInst_getNumOperands(MI) == 3 &&
1512
943
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1513
943
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1514
152
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1515
152
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1516
      // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1517
152
      AsmString = "fbul,a,pn $\x03, $\x01";
1518
152
      break;
1519
152
    }
1520
791
    if (MCInst_getNumOperands(MI) == 3 &&
1521
791
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1522
791
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1523
77
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1524
77
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1525
      // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1526
77
      AsmString = "fblg,a,pn $\x03, $\x01";
1527
77
      break;
1528
77
    }
1529
714
    if (MCInst_getNumOperands(MI) == 3 &&
1530
714
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1531
714
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1532
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1533
36
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1534
      // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1535
36
      AsmString = "fbne,a,pn $\x03, $\x01";
1536
36
      break;
1537
36
    }
1538
678
    if (MCInst_getNumOperands(MI) == 3 &&
1539
678
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1540
678
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1541
43
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1542
43
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1543
      // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1544
43
      AsmString = "fbe,a,pn $\x03, $\x01";
1545
43
      break;
1546
43
    }
1547
635
    if (MCInst_getNumOperands(MI) == 3 &&
1548
635
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1549
635
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1550
95
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1551
95
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1552
      // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1553
95
      AsmString = "fbue,a,pn $\x03, $\x01";
1554
95
      break;
1555
95
    }
1556
540
    if (MCInst_getNumOperands(MI) == 3 &&
1557
540
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1558
540
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1559
52
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1560
52
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1561
      // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1562
52
      AsmString = "fbge,a,pn $\x03, $\x01";
1563
52
      break;
1564
52
    }
1565
488
    if (MCInst_getNumOperands(MI) == 3 &&
1566
488
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1567
488
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1568
154
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1569
154
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1570
      // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1571
154
      AsmString = "fbuge,a,pn $\x03, $\x01";
1572
154
      break;
1573
154
    }
1574
334
    if (MCInst_getNumOperands(MI) == 3 &&
1575
334
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1576
334
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1577
235
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1578
235
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1579
      // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1580
235
      AsmString = "fble,a,pn $\x03, $\x01";
1581
235
      break;
1582
235
    }
1583
99
    if (MCInst_getNumOperands(MI) == 3 &&
1584
99
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1585
99
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1586
46
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1587
46
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1588
      // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1589
46
      AsmString = "fbule,a,pn $\x03, $\x01";
1590
46
      break;
1591
46
    }
1592
53
    if (MCInst_getNumOperands(MI) == 3 &&
1593
53
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1594
53
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1595
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1596
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1597
      // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1598
53
      AsmString = "fbo,a,pn $\x03, $\x01";
1599
53
      break;
1600
53
    }
1601
0
    return NULL;
1602
2.43k
  case SP_BPFCCNT:
1603
2.43k
    if (MCInst_getNumOperands(MI) == 3 &&
1604
2.43k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1605
2.43k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1606
122
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1607
122
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1608
      // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1609
122
      AsmString = "fba,pn $\x03, $\x01";
1610
122
      break;
1611
122
    }
1612
2.31k
    if (MCInst_getNumOperands(MI) == 3 &&
1613
2.31k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1614
2.31k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1615
117
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1616
117
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1617
      // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1618
117
      AsmString = "fbn,pn $\x03, $\x01";
1619
117
      break;
1620
117
    }
1621
2.19k
    if (MCInst_getNumOperands(MI) == 3 &&
1622
2.19k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1623
2.19k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1624
74
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1625
74
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1626
      // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1627
74
      AsmString = "fbu,pn $\x03, $\x01";
1628
74
      break;
1629
74
    }
1630
2.12k
    if (MCInst_getNumOperands(MI) == 3 &&
1631
2.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1632
2.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1633
197
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1634
197
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1635
      // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1636
197
      AsmString = "fbg,pn $\x03, $\x01";
1637
197
      break;
1638
197
    }
1639
1.92k
    if (MCInst_getNumOperands(MI) == 3 &&
1640
1.92k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1641
1.92k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1642
142
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1643
142
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1644
      // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1645
142
      AsmString = "fbug,pn $\x03, $\x01";
1646
142
      break;
1647
142
    }
1648
1.78k
    if (MCInst_getNumOperands(MI) == 3 &&
1649
1.78k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1650
1.78k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1651
40
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1652
40
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1653
      // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1654
40
      AsmString = "fbl,pn $\x03, $\x01";
1655
40
      break;
1656
40
    }
1657
1.74k
    if (MCInst_getNumOperands(MI) == 3 &&
1658
1.74k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1659
1.74k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1660
53
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1661
53
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1662
      // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1663
53
      AsmString = "fbul,pn $\x03, $\x01";
1664
53
      break;
1665
53
    }
1666
1.69k
    if (MCInst_getNumOperands(MI) == 3 &&
1667
1.69k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1668
1.69k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1669
188
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1670
188
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1671
      // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1672
188
      AsmString = "fblg,pn $\x03, $\x01";
1673
188
      break;
1674
188
    }
1675
1.50k
    if (MCInst_getNumOperands(MI) == 3 &&
1676
1.50k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1677
1.50k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1678
297
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1679
297
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1680
      // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1681
297
      AsmString = "fbne,pn $\x03, $\x01";
1682
297
      break;
1683
297
    }
1684
1.20k
    if (MCInst_getNumOperands(MI) == 3 &&
1685
1.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1686
1.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1687
179
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1688
179
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1689
      // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1690
179
      AsmString = "fbe,pn $\x03, $\x01";
1691
179
      break;
1692
179
    }
1693
1.02k
    if (MCInst_getNumOperands(MI) == 3 &&
1694
1.02k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1695
1.02k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1696
15
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1697
15
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1698
      // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1699
15
      AsmString = "fbue,pn $\x03, $\x01";
1700
15
      break;
1701
15
    }
1702
1.01k
    if (MCInst_getNumOperands(MI) == 3 &&
1703
1.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1704
1.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1705
206
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1706
206
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1707
      // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1708
206
      AsmString = "fbge,pn $\x03, $\x01";
1709
206
      break;
1710
206
    }
1711
806
    if (MCInst_getNumOperands(MI) == 3 &&
1712
806
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1713
806
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1714
317
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1715
317
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1716
      // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1717
317
      AsmString = "fbuge,pn $\x03, $\x01";
1718
317
      break;
1719
317
    }
1720
489
    if (MCInst_getNumOperands(MI) == 3 &&
1721
489
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1722
489
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1723
64
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1724
64
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1725
      // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1726
64
      AsmString = "fble,pn $\x03, $\x01";
1727
64
      break;
1728
64
    }
1729
425
    if (MCInst_getNumOperands(MI) == 3 &&
1730
425
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1731
425
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1732
159
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1733
159
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1734
      // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1735
159
      AsmString = "fbule,pn $\x03, $\x01";
1736
159
      break;
1737
159
    }
1738
266
    if (MCInst_getNumOperands(MI) == 3 &&
1739
266
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1740
266
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1741
266
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1742
266
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1743
      // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1744
266
      AsmString = "fbo,pn $\x03, $\x01";
1745
266
      break;
1746
266
    }
1747
0
    return NULL;
1748
2.59k
  case SP_BPICCANT:
1749
2.59k
    if (MCInst_getNumOperands(MI) == 2 &&
1750
2.59k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1751
2.59k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1752
      // (BPICCANT brtarget:$imm, 8)
1753
168
      AsmString = "ba,a,pn %icc, $\x01";
1754
168
      break;
1755
168
    }
1756
2.42k
    if (MCInst_getNumOperands(MI) == 2 &&
1757
2.42k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1758
2.42k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1759
      // (BPICCANT brtarget:$imm, 0)
1760
193
      AsmString = "bn,a,pn %icc, $\x01";
1761
193
      break;
1762
193
    }
1763
2.23k
    if (MCInst_getNumOperands(MI) == 2 &&
1764
2.23k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1765
2.23k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1766
      // (BPICCANT brtarget:$imm, 9)
1767
152
      AsmString = "bne,a,pn %icc, $\x01";
1768
152
      break;
1769
152
    }
1770
2.08k
    if (MCInst_getNumOperands(MI) == 2 &&
1771
2.08k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1772
2.08k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1773
      // (BPICCANT brtarget:$imm, 1)
1774
241
      AsmString = "be,a,pn %icc, $\x01";
1775
241
      break;
1776
241
    }
1777
1.83k
    if (MCInst_getNumOperands(MI) == 2 &&
1778
1.83k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1779
1.83k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1780
      // (BPICCANT brtarget:$imm, 10)
1781
385
      AsmString = "bg,a,pn %icc, $\x01";
1782
385
      break;
1783
385
    }
1784
1.45k
    if (MCInst_getNumOperands(MI) == 2 &&
1785
1.45k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1786
1.45k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1787
      // (BPICCANT brtarget:$imm, 2)
1788
134
      AsmString = "ble,a,pn %icc, $\x01";
1789
134
      break;
1790
134
    }
1791
1.32k
    if (MCInst_getNumOperands(MI) == 2 &&
1792
1.32k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1793
1.32k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1794
      // (BPICCANT brtarget:$imm, 11)
1795
199
      AsmString = "bge,a,pn %icc, $\x01";
1796
199
      break;
1797
199
    }
1798
1.12k
    if (MCInst_getNumOperands(MI) == 2 &&
1799
1.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1800
1.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1801
      // (BPICCANT brtarget:$imm, 3)
1802
24
      AsmString = "bl,a,pn %icc, $\x01";
1803
24
      break;
1804
24
    }
1805
1.09k
    if (MCInst_getNumOperands(MI) == 2 &&
1806
1.09k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1807
1.09k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1808
      // (BPICCANT brtarget:$imm, 12)
1809
252
      AsmString = "bgu,a,pn %icc, $\x01";
1810
252
      break;
1811
252
    }
1812
845
    if (MCInst_getNumOperands(MI) == 2 &&
1813
845
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1814
845
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1815
      // (BPICCANT brtarget:$imm, 4)
1816
233
      AsmString = "bleu,a,pn %icc, $\x01";
1817
233
      break;
1818
233
    }
1819
612
    if (MCInst_getNumOperands(MI) == 2 &&
1820
612
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1821
612
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1822
      // (BPICCANT brtarget:$imm, 13)
1823
71
      AsmString = "bcc,a,pn %icc, $\x01";
1824
71
      break;
1825
71
    }
1826
541
    if (MCInst_getNumOperands(MI) == 2 &&
1827
541
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1828
541
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1829
      // (BPICCANT brtarget:$imm, 5)
1830
133
      AsmString = "bcs,a,pn %icc, $\x01";
1831
133
      break;
1832
133
    }
1833
408
    if (MCInst_getNumOperands(MI) == 2 &&
1834
408
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1835
408
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1836
      // (BPICCANT brtarget:$imm, 14)
1837
199
      AsmString = "bpos,a,pn %icc, $\x01";
1838
199
      break;
1839
199
    }
1840
209
    if (MCInst_getNumOperands(MI) == 2 &&
1841
209
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1842
209
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1843
      // (BPICCANT brtarget:$imm, 6)
1844
55
      AsmString = "bneg,a,pn %icc, $\x01";
1845
55
      break;
1846
55
    }
1847
154
    if (MCInst_getNumOperands(MI) == 2 &&
1848
154
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1849
154
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1850
      // (BPICCANT brtarget:$imm, 15)
1851
34
      AsmString = "bvc,a,pn %icc, $\x01";
1852
34
      break;
1853
34
    }
1854
120
    if (MCInst_getNumOperands(MI) == 2 &&
1855
120
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1856
120
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1857
      // (BPICCANT brtarget:$imm, 7)
1858
120
      AsmString = "bvs,a,pn %icc, $\x01";
1859
120
      break;
1860
120
    }
1861
0
    return NULL;
1862
2.33k
  case SP_BPICCNT:
1863
2.33k
    if (MCInst_getNumOperands(MI) == 2 &&
1864
2.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1865
2.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1866
      // (BPICCNT brtarget:$imm, 8)
1867
112
      AsmString = "ba,pn %icc, $\x01";
1868
112
      break;
1869
112
    }
1870
2.22k
    if (MCInst_getNumOperands(MI) == 2 &&
1871
2.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1872
2.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1873
      // (BPICCNT brtarget:$imm, 0)
1874
32
      AsmString = "bn,pn %icc, $\x01";
1875
32
      break;
1876
32
    }
1877
2.18k
    if (MCInst_getNumOperands(MI) == 2 &&
1878
2.18k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1879
2.18k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1880
      // (BPICCNT brtarget:$imm, 9)
1881
69
      AsmString = "bne,pn %icc, $\x01";
1882
69
      break;
1883
69
    }
1884
2.12k
    if (MCInst_getNumOperands(MI) == 2 &&
1885
2.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1886
2.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1887
      // (BPICCNT brtarget:$imm, 1)
1888
15
      AsmString = "be,pn %icc, $\x01";
1889
15
      break;
1890
15
    }
1891
2.10k
    if (MCInst_getNumOperands(MI) == 2 &&
1892
2.10k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1893
2.10k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1894
      // (BPICCNT brtarget:$imm, 10)
1895
319
      AsmString = "bg,pn %icc, $\x01";
1896
319
      break;
1897
319
    }
1898
1.78k
    if (MCInst_getNumOperands(MI) == 2 &&
1899
1.78k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1900
1.78k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1901
      // (BPICCNT brtarget:$imm, 2)
1902
85
      AsmString = "ble,pn %icc, $\x01";
1903
85
      break;
1904
85
    }
1905
1.70k
    if (MCInst_getNumOperands(MI) == 2 &&
1906
1.70k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1907
1.70k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1908
      // (BPICCNT brtarget:$imm, 11)
1909
409
      AsmString = "bge,pn %icc, $\x01";
1910
409
      break;
1911
409
    }
1912
1.29k
    if (MCInst_getNumOperands(MI) == 2 &&
1913
1.29k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1914
1.29k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1915
      // (BPICCNT brtarget:$imm, 3)
1916
176
      AsmString = "bl,pn %icc, $\x01";
1917
176
      break;
1918
176
    }
1919
1.11k
    if (MCInst_getNumOperands(MI) == 2 &&
1920
1.11k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1921
1.11k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1922
      // (BPICCNT brtarget:$imm, 12)
1923
74
      AsmString = "bgu,pn %icc, $\x01";
1924
74
      break;
1925
74
    }
1926
1.04k
    if (MCInst_getNumOperands(MI) == 2 &&
1927
1.04k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1928
1.04k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1929
      // (BPICCNT brtarget:$imm, 4)
1930
71
      AsmString = "bleu,pn %icc, $\x01";
1931
71
      break;
1932
71
    }
1933
971
    if (MCInst_getNumOperands(MI) == 2 &&
1934
971
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1935
971
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1936
      // (BPICCNT brtarget:$imm, 13)
1937
346
      AsmString = "bcc,pn %icc, $\x01";
1938
346
      break;
1939
346
    }
1940
625
    if (MCInst_getNumOperands(MI) == 2 &&
1941
625
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1942
625
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1943
      // (BPICCNT brtarget:$imm, 5)
1944
95
      AsmString = "bcs,pn %icc, $\x01";
1945
95
      break;
1946
95
    }
1947
530
    if (MCInst_getNumOperands(MI) == 2 &&
1948
530
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1949
530
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1950
      // (BPICCNT brtarget:$imm, 14)
1951
201
      AsmString = "bpos,pn %icc, $\x01";
1952
201
      break;
1953
201
    }
1954
329
    if (MCInst_getNumOperands(MI) == 2 &&
1955
329
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1956
329
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1957
      // (BPICCNT brtarget:$imm, 6)
1958
77
      AsmString = "bneg,pn %icc, $\x01";
1959
77
      break;
1960
77
    }
1961
252
    if (MCInst_getNumOperands(MI) == 2 &&
1962
252
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1963
252
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1964
      // (BPICCNT brtarget:$imm, 15)
1965
210
      AsmString = "bvc,pn %icc, $\x01";
1966
210
      break;
1967
210
    }
1968
42
    if (MCInst_getNumOperands(MI) == 2 &&
1969
42
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1970
42
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1971
      // (BPICCNT brtarget:$imm, 7)
1972
42
      AsmString = "bvs,pn %icc, $\x01";
1973
42
      break;
1974
42
    }
1975
0
    return NULL;
1976
2.22k
  case SP_BPXCCANT:
1977
2.22k
    if (MCInst_getNumOperands(MI) == 2 &&
1978
2.22k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1979
2.22k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1980
      // (BPXCCANT brtarget:$imm, 8)
1981
104
      AsmString = "ba,a,pn %xcc, $\x01";
1982
104
      break;
1983
104
    }
1984
2.12k
    if (MCInst_getNumOperands(MI) == 2 &&
1985
2.12k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1986
2.12k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1987
      // (BPXCCANT brtarget:$imm, 0)
1988
164
      AsmString = "bn,a,pn %xcc, $\x01";
1989
164
      break;
1990
164
    }
1991
1.96k
    if (MCInst_getNumOperands(MI) == 2 &&
1992
1.96k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1993
1.96k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1994
      // (BPXCCANT brtarget:$imm, 9)
1995
57
      AsmString = "bne,a,pn %xcc, $\x01";
1996
57
      break;
1997
57
    }
1998
1.90k
    if (MCInst_getNumOperands(MI) == 2 &&
1999
1.90k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2000
1.90k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2001
      // (BPXCCANT brtarget:$imm, 1)
2002
43
      AsmString = "be,a,pn %xcc, $\x01";
2003
43
      break;
2004
43
    }
2005
1.86k
    if (MCInst_getNumOperands(MI) == 2 &&
2006
1.86k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2007
1.86k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2008
      // (BPXCCANT brtarget:$imm, 10)
2009
107
      AsmString = "bg,a,pn %xcc, $\x01";
2010
107
      break;
2011
107
    }
2012
1.75k
    if (MCInst_getNumOperands(MI) == 2 &&
2013
1.75k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2014
1.75k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2015
      // (BPXCCANT brtarget:$imm, 2)
2016
155
      AsmString = "ble,a,pn %xcc, $\x01";
2017
155
      break;
2018
155
    }
2019
1.59k
    if (MCInst_getNumOperands(MI) == 2 &&
2020
1.59k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2021
1.59k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2022
      // (BPXCCANT brtarget:$imm, 11)
2023
267
      AsmString = "bge,a,pn %xcc, $\x01";
2024
267
      break;
2025
267
    }
2026
1.33k
    if (MCInst_getNumOperands(MI) == 2 &&
2027
1.33k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2028
1.33k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2029
      // (BPXCCANT brtarget:$imm, 3)
2030
246
      AsmString = "bl,a,pn %xcc, $\x01";
2031
246
      break;
2032
246
    }
2033
1.08k
    if (MCInst_getNumOperands(MI) == 2 &&
2034
1.08k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2035
1.08k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2036
      // (BPXCCANT brtarget:$imm, 12)
2037
350
      AsmString = "bgu,a,pn %xcc, $\x01";
2038
350
      break;
2039
350
    }
2040
736
    if (MCInst_getNumOperands(MI) == 2 &&
2041
736
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2042
736
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2043
      // (BPXCCANT brtarget:$imm, 4)
2044
279
      AsmString = "bleu,a,pn %xcc, $\x01";
2045
279
      break;
2046
279
    }
2047
457
    if (MCInst_getNumOperands(MI) == 2 &&
2048
457
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2049
457
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2050
      // (BPXCCANT brtarget:$imm, 13)
2051
24
      AsmString = "bcc,a,pn %xcc, $\x01";
2052
24
      break;
2053
24
    }
2054
433
    if (MCInst_getNumOperands(MI) == 2 &&
2055
433
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2056
433
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2057
      // (BPXCCANT brtarget:$imm, 5)
2058
64
      AsmString = "bcs,a,pn %xcc, $\x01";
2059
64
      break;
2060
64
    }
2061
369
    if (MCInst_getNumOperands(MI) == 2 &&
2062
369
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2063
369
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2064
      // (BPXCCANT brtarget:$imm, 14)
2065
11
      AsmString = "bpos,a,pn %xcc, $\x01";
2066
11
      break;
2067
11
    }
2068
358
    if (MCInst_getNumOperands(MI) == 2 &&
2069
358
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2070
358
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2071
      // (BPXCCANT brtarget:$imm, 6)
2072
108
      AsmString = "bneg,a,pn %xcc, $\x01";
2073
108
      break;
2074
108
    }
2075
250
    if (MCInst_getNumOperands(MI) == 2 &&
2076
250
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2077
250
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2078
      // (BPXCCANT brtarget:$imm, 15)
2079
95
      AsmString = "bvc,a,pn %xcc, $\x01";
2080
95
      break;
2081
95
    }
2082
155
    if (MCInst_getNumOperands(MI) == 2 &&
2083
155
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2084
155
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2085
      // (BPXCCANT brtarget:$imm, 7)
2086
155
      AsmString = "bvs,a,pn %xcc, $\x01";
2087
155
      break;
2088
155
    }
2089
0
    return NULL;
2090
3.05k
  case SP_BPXCCNT:
2091
3.05k
    if (MCInst_getNumOperands(MI) == 2 &&
2092
3.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2093
3.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2094
      // (BPXCCNT brtarget:$imm, 8)
2095
47
      AsmString = "ba,pn %xcc, $\x01";
2096
47
      break;
2097
47
    }
2098
3.01k
    if (MCInst_getNumOperands(MI) == 2 &&
2099
3.01k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2100
3.01k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2101
      // (BPXCCNT brtarget:$imm, 0)
2102
132
      AsmString = "bn,pn %xcc, $\x01";
2103
132
      break;
2104
132
    }
2105
2.88k
    if (MCInst_getNumOperands(MI) == 2 &&
2106
2.88k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2107
2.88k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2108
      // (BPXCCNT brtarget:$imm, 9)
2109
61
      AsmString = "bne,pn %xcc, $\x01";
2110
61
      break;
2111
61
    }
2112
2.81k
    if (MCInst_getNumOperands(MI) == 2 &&
2113
2.81k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2114
2.81k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2115
      // (BPXCCNT brtarget:$imm, 1)
2116
48
      AsmString = "be,pn %xcc, $\x01";
2117
48
      break;
2118
48
    }
2119
2.77k
    if (MCInst_getNumOperands(MI) == 2 &&
2120
2.77k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2121
2.77k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2122
      // (BPXCCNT brtarget:$imm, 10)
2123
201
      AsmString = "bg,pn %xcc, $\x01";
2124
201
      break;
2125
201
    }
2126
2.57k
    if (MCInst_getNumOperands(MI) == 2 &&
2127
2.57k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2128
2.57k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2129
      // (BPXCCNT brtarget:$imm, 2)
2130
370
      AsmString = "ble,pn %xcc, $\x01";
2131
370
      break;
2132
370
    }
2133
2.20k
    if (MCInst_getNumOperands(MI) == 2 &&
2134
2.20k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2135
2.20k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2136
      // (BPXCCNT brtarget:$imm, 11)
2137
83
      AsmString = "bge,pn %xcc, $\x01";
2138
83
      break;
2139
83
    }
2140
2.11k
    if (MCInst_getNumOperands(MI) == 2 &&
2141
2.11k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2142
2.11k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2143
      // (BPXCCNT brtarget:$imm, 3)
2144
29
      AsmString = "bl,pn %xcc, $\x01";
2145
29
      break;
2146
29
    }
2147
2.08k
    if (MCInst_getNumOperands(MI) == 2 &&
2148
2.08k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2149
2.08k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2150
      // (BPXCCNT brtarget:$imm, 12)
2151
153
      AsmString = "bgu,pn %xcc, $\x01";
2152
153
      break;
2153
153
    }
2154
1.93k
    if (MCInst_getNumOperands(MI) == 2 &&
2155
1.93k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2156
1.93k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2157
      // (BPXCCNT brtarget:$imm, 4)
2158
181
      AsmString = "bleu,pn %xcc, $\x01";
2159
181
      break;
2160
181
    }
2161
1.75k
    if (MCInst_getNumOperands(MI) == 2 &&
2162
1.75k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2163
1.75k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2164
      // (BPXCCNT brtarget:$imm, 13)
2165
179
      AsmString = "bcc,pn %xcc, $\x01";
2166
179
      break;
2167
179
    }
2168
1.57k
    if (MCInst_getNumOperands(MI) == 2 &&
2169
1.57k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2170
1.57k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2171
      // (BPXCCNT brtarget:$imm, 5)
2172
522
      AsmString = "bcs,pn %xcc, $\x01";
2173
522
      break;
2174
522
    }
2175
1.05k
    if (MCInst_getNumOperands(MI) == 2 &&
2176
1.05k
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2177
1.05k
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2178
      // (BPXCCNT brtarget:$imm, 14)
2179
773
      AsmString = "bpos,pn %xcc, $\x01";
2180
773
      break;
2181
773
    }
2182
280
    if (MCInst_getNumOperands(MI) == 2 &&
2183
280
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2184
280
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2185
      // (BPXCCNT brtarget:$imm, 6)
2186
58
      AsmString = "bneg,pn %xcc, $\x01";
2187
58
      break;
2188
58
    }
2189
222
    if (MCInst_getNumOperands(MI) == 2 &&
2190
222
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2191
222
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2192
      // (BPXCCNT brtarget:$imm, 15)
2193
139
      AsmString = "bvc,pn %xcc, $\x01";
2194
139
      break;
2195
139
    }
2196
83
    if (MCInst_getNumOperands(MI) == 2 &&
2197
83
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2198
83
        MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2199
      // (BPXCCNT brtarget:$imm, 7)
2200
83
      AsmString = "bvs,pn %xcc, $\x01";
2201
83
      break;
2202
83
    }
2203
0
    return NULL;
2204
101
  case SP_FMOVD_ICC:
2205
101
    if (MCInst_getNumOperands(MI) == 3 &&
2206
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2207
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2208
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2209
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2210
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2211
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2212
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2213
0
      AsmString = "fmovda %icc, $\x02, $\x01";
2214
0
      break;
2215
0
    }
2216
101
    if (MCInst_getNumOperands(MI) == 3 &&
2217
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2218
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2219
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2220
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2221
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2222
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2223
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2224
0
      AsmString = "fmovdn %icc, $\x02, $\x01";
2225
0
      break;
2226
0
    }
2227
101
    if (MCInst_getNumOperands(MI) == 3 &&
2228
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2229
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2230
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2231
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2232
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2233
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2234
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2235
0
      AsmString = "fmovdne %icc, $\x02, $\x01";
2236
0
      break;
2237
0
    }
2238
101
    if (MCInst_getNumOperands(MI) == 3 &&
2239
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2240
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2241
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2242
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2243
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2244
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2245
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2246
0
      AsmString = "fmovde %icc, $\x02, $\x01";
2247
0
      break;
2248
0
    }
2249
101
    if (MCInst_getNumOperands(MI) == 3 &&
2250
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2251
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2252
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2253
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2254
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2255
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2256
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2257
0
      AsmString = "fmovdg %icc, $\x02, $\x01";
2258
0
      break;
2259
0
    }
2260
101
    if (MCInst_getNumOperands(MI) == 3 &&
2261
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2262
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2263
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2264
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2265
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2266
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2267
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2268
0
      AsmString = "fmovdle %icc, $\x02, $\x01";
2269
0
      break;
2270
0
    }
2271
101
    if (MCInst_getNumOperands(MI) == 3 &&
2272
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2273
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2274
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2275
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2276
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2277
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2278
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2279
0
      AsmString = "fmovdge %icc, $\x02, $\x01";
2280
0
      break;
2281
0
    }
2282
101
    if (MCInst_getNumOperands(MI) == 3 &&
2283
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2284
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2285
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2286
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2287
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2288
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2289
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2290
0
      AsmString = "fmovdl %icc, $\x02, $\x01";
2291
0
      break;
2292
0
    }
2293
101
    if (MCInst_getNumOperands(MI) == 3 &&
2294
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2295
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2296
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2297
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2298
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2299
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2300
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2301
0
      AsmString = "fmovdgu %icc, $\x02, $\x01";
2302
0
      break;
2303
0
    }
2304
101
    if (MCInst_getNumOperands(MI) == 3 &&
2305
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2306
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2307
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2308
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2309
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2310
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2311
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2312
0
      AsmString = "fmovdleu %icc, $\x02, $\x01";
2313
0
      break;
2314
0
    }
2315
101
    if (MCInst_getNumOperands(MI) == 3 &&
2316
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2317
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2318
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2319
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2320
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2321
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2322
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2323
0
      AsmString = "fmovdcc %icc, $\x02, $\x01";
2324
0
      break;
2325
0
    }
2326
101
    if (MCInst_getNumOperands(MI) == 3 &&
2327
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2328
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2329
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2330
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2331
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2332
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2333
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2334
0
      AsmString = "fmovdcs %icc, $\x02, $\x01";
2335
0
      break;
2336
0
    }
2337
101
    if (MCInst_getNumOperands(MI) == 3 &&
2338
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2339
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2340
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2341
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2342
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2343
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2344
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2345
0
      AsmString = "fmovdpos %icc, $\x02, $\x01";
2346
0
      break;
2347
0
    }
2348
101
    if (MCInst_getNumOperands(MI) == 3 &&
2349
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2350
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2351
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2352
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2353
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2354
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2355
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2356
0
      AsmString = "fmovdneg %icc, $\x02, $\x01";
2357
0
      break;
2358
0
    }
2359
101
    if (MCInst_getNumOperands(MI) == 3 &&
2360
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2361
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2362
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2363
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2364
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2365
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2366
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2367
0
      AsmString = "fmovdvc %icc, $\x02, $\x01";
2368
0
      break;
2369
0
    }
2370
101
    if (MCInst_getNumOperands(MI) == 3 &&
2371
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2372
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2373
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2374
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2375
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2376
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2377
      // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2378
0
      AsmString = "fmovdvs %icc, $\x02, $\x01";
2379
0
      break;
2380
0
    }
2381
101
    return NULL;
2382
11
  case SP_FMOVD_XCC:
2383
11
    if (MCInst_getNumOperands(MI) == 3 &&
2384
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2385
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2386
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2387
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2388
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2389
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2390
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2391
0
      AsmString = "fmovda %xcc, $\x02, $\x01";
2392
0
      break;
2393
0
    }
2394
11
    if (MCInst_getNumOperands(MI) == 3 &&
2395
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2396
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2397
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2398
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2399
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2400
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2401
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2402
0
      AsmString = "fmovdn %xcc, $\x02, $\x01";
2403
0
      break;
2404
0
    }
2405
11
    if (MCInst_getNumOperands(MI) == 3 &&
2406
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2407
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2408
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2409
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2410
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2411
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2412
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2413
0
      AsmString = "fmovdne %xcc, $\x02, $\x01";
2414
0
      break;
2415
0
    }
2416
11
    if (MCInst_getNumOperands(MI) == 3 &&
2417
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2418
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2419
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2420
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2421
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2422
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2423
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2424
0
      AsmString = "fmovde %xcc, $\x02, $\x01";
2425
0
      break;
2426
0
    }
2427
11
    if (MCInst_getNumOperands(MI) == 3 &&
2428
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2429
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2430
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2431
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2432
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2433
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2434
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2435
0
      AsmString = "fmovdg %xcc, $\x02, $\x01";
2436
0
      break;
2437
0
    }
2438
11
    if (MCInst_getNumOperands(MI) == 3 &&
2439
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2440
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2441
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2442
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2443
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2444
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2445
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2446
0
      AsmString = "fmovdle %xcc, $\x02, $\x01";
2447
0
      break;
2448
0
    }
2449
11
    if (MCInst_getNumOperands(MI) == 3 &&
2450
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2451
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2452
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2453
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2454
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2455
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2456
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2457
0
      AsmString = "fmovdge %xcc, $\x02, $\x01";
2458
0
      break;
2459
0
    }
2460
11
    if (MCInst_getNumOperands(MI) == 3 &&
2461
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2462
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2463
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2464
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2465
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2466
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2467
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2468
0
      AsmString = "fmovdl %xcc, $\x02, $\x01";
2469
0
      break;
2470
0
    }
2471
11
    if (MCInst_getNumOperands(MI) == 3 &&
2472
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2473
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2474
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2475
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2476
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2477
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2478
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2479
0
      AsmString = "fmovdgu %xcc, $\x02, $\x01";
2480
0
      break;
2481
0
    }
2482
11
    if (MCInst_getNumOperands(MI) == 3 &&
2483
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2484
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2485
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2486
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2487
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2488
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2489
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2490
0
      AsmString = "fmovdleu %xcc, $\x02, $\x01";
2491
0
      break;
2492
0
    }
2493
11
    if (MCInst_getNumOperands(MI) == 3 &&
2494
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2495
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2496
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2497
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2498
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2499
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2500
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2501
0
      AsmString = "fmovdcc %xcc, $\x02, $\x01";
2502
0
      break;
2503
0
    }
2504
11
    if (MCInst_getNumOperands(MI) == 3 &&
2505
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2506
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2507
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2508
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2509
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2510
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2511
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2512
0
      AsmString = "fmovdcs %xcc, $\x02, $\x01";
2513
0
      break;
2514
0
    }
2515
11
    if (MCInst_getNumOperands(MI) == 3 &&
2516
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2517
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2518
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2519
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2520
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2521
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2522
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2523
0
      AsmString = "fmovdpos %xcc, $\x02, $\x01";
2524
0
      break;
2525
0
    }
2526
11
    if (MCInst_getNumOperands(MI) == 3 &&
2527
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2528
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2529
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2530
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2531
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2532
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2533
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2534
0
      AsmString = "fmovdneg %xcc, $\x02, $\x01";
2535
0
      break;
2536
0
    }
2537
11
    if (MCInst_getNumOperands(MI) == 3 &&
2538
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2539
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2540
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2541
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2542
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2543
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2544
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2545
0
      AsmString = "fmovdvc %xcc, $\x02, $\x01";
2546
0
      break;
2547
0
    }
2548
11
    if (MCInst_getNumOperands(MI) == 3 &&
2549
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2550
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2551
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2552
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2553
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2554
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2555
      // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2556
0
      AsmString = "fmovdvs %xcc, $\x02, $\x01";
2557
0
      break;
2558
0
    }
2559
11
    return NULL;
2560
315
  case SP_FMOVQ_ICC:
2561
315
    if (MCInst_getNumOperands(MI) == 3 &&
2562
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2563
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2564
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2565
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2566
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2567
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2568
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2569
0
      AsmString = "fmovqa %icc, $\x02, $\x01";
2570
0
      break;
2571
0
    }
2572
315
    if (MCInst_getNumOperands(MI) == 3 &&
2573
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2574
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2575
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2576
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2577
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2578
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2579
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2580
0
      AsmString = "fmovqn %icc, $\x02, $\x01";
2581
0
      break;
2582
0
    }
2583
315
    if (MCInst_getNumOperands(MI) == 3 &&
2584
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2585
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2586
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2587
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2588
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2589
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2590
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2591
0
      AsmString = "fmovqne %icc, $\x02, $\x01";
2592
0
      break;
2593
0
    }
2594
315
    if (MCInst_getNumOperands(MI) == 3 &&
2595
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2596
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2597
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2598
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2599
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2600
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2601
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2602
0
      AsmString = "fmovqe %icc, $\x02, $\x01";
2603
0
      break;
2604
0
    }
2605
315
    if (MCInst_getNumOperands(MI) == 3 &&
2606
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2607
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2608
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2609
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2610
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2611
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2612
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2613
0
      AsmString = "fmovqg %icc, $\x02, $\x01";
2614
0
      break;
2615
0
    }
2616
315
    if (MCInst_getNumOperands(MI) == 3 &&
2617
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2618
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2619
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2620
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2621
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2622
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2623
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2624
0
      AsmString = "fmovqle %icc, $\x02, $\x01";
2625
0
      break;
2626
0
    }
2627
315
    if (MCInst_getNumOperands(MI) == 3 &&
2628
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2629
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2630
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2631
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2632
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2633
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2634
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2635
0
      AsmString = "fmovqge %icc, $\x02, $\x01";
2636
0
      break;
2637
0
    }
2638
315
    if (MCInst_getNumOperands(MI) == 3 &&
2639
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2640
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2641
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2642
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2643
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2644
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2645
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2646
0
      AsmString = "fmovql %icc, $\x02, $\x01";
2647
0
      break;
2648
0
    }
2649
315
    if (MCInst_getNumOperands(MI) == 3 &&
2650
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2651
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2652
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2653
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2654
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2655
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2656
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2657
0
      AsmString = "fmovqgu %icc, $\x02, $\x01";
2658
0
      break;
2659
0
    }
2660
315
    if (MCInst_getNumOperands(MI) == 3 &&
2661
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2662
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2663
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2664
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2665
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2666
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2667
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2668
0
      AsmString = "fmovqleu %icc, $\x02, $\x01";
2669
0
      break;
2670
0
    }
2671
315
    if (MCInst_getNumOperands(MI) == 3 &&
2672
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2673
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2674
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2675
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2676
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2677
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2678
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2679
0
      AsmString = "fmovqcc %icc, $\x02, $\x01";
2680
0
      break;
2681
0
    }
2682
315
    if (MCInst_getNumOperands(MI) == 3 &&
2683
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2684
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2685
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2686
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2687
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2688
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2689
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2690
0
      AsmString = "fmovqcs %icc, $\x02, $\x01";
2691
0
      break;
2692
0
    }
2693
315
    if (MCInst_getNumOperands(MI) == 3 &&
2694
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2695
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2696
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2697
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2698
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2699
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2700
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2701
0
      AsmString = "fmovqpos %icc, $\x02, $\x01";
2702
0
      break;
2703
0
    }
2704
315
    if (MCInst_getNumOperands(MI) == 3 &&
2705
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2706
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2707
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2708
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2709
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2710
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2711
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2712
0
      AsmString = "fmovqneg %icc, $\x02, $\x01";
2713
0
      break;
2714
0
    }
2715
315
    if (MCInst_getNumOperands(MI) == 3 &&
2716
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2717
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2718
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2719
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2720
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2721
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2722
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2723
0
      AsmString = "fmovqvc %icc, $\x02, $\x01";
2724
0
      break;
2725
0
    }
2726
315
    if (MCInst_getNumOperands(MI) == 3 &&
2727
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2728
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2729
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2730
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2731
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2732
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2733
      // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2734
0
      AsmString = "fmovqvs %icc, $\x02, $\x01";
2735
0
      break;
2736
0
    }
2737
315
    return NULL;
2738
126
  case SP_FMOVQ_XCC:
2739
126
    if (MCInst_getNumOperands(MI) == 3 &&
2740
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2741
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2742
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2743
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2744
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2745
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2746
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2747
0
      AsmString = "fmovqa %xcc, $\x02, $\x01";
2748
0
      break;
2749
0
    }
2750
126
    if (MCInst_getNumOperands(MI) == 3 &&
2751
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2752
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2753
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2754
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2755
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2756
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2757
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2758
0
      AsmString = "fmovqn %xcc, $\x02, $\x01";
2759
0
      break;
2760
0
    }
2761
126
    if (MCInst_getNumOperands(MI) == 3 &&
2762
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2763
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2764
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2765
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2766
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2767
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2768
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2769
0
      AsmString = "fmovqne %xcc, $\x02, $\x01";
2770
0
      break;
2771
0
    }
2772
126
    if (MCInst_getNumOperands(MI) == 3 &&
2773
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2774
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2775
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2776
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2777
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2778
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2779
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2780
0
      AsmString = "fmovqe %xcc, $\x02, $\x01";
2781
0
      break;
2782
0
    }
2783
126
    if (MCInst_getNumOperands(MI) == 3 &&
2784
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2785
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2786
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2787
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2788
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2789
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2790
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2791
0
      AsmString = "fmovqg %xcc, $\x02, $\x01";
2792
0
      break;
2793
0
    }
2794
126
    if (MCInst_getNumOperands(MI) == 3 &&
2795
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2796
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2797
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2798
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2799
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2800
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2801
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2802
0
      AsmString = "fmovqle %xcc, $\x02, $\x01";
2803
0
      break;
2804
0
    }
2805
126
    if (MCInst_getNumOperands(MI) == 3 &&
2806
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2807
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2808
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2809
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2810
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2811
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2812
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2813
0
      AsmString = "fmovqge %xcc, $\x02, $\x01";
2814
0
      break;
2815
0
    }
2816
126
    if (MCInst_getNumOperands(MI) == 3 &&
2817
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2818
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2819
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2820
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2821
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2822
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2823
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2824
0
      AsmString = "fmovql %xcc, $\x02, $\x01";
2825
0
      break;
2826
0
    }
2827
126
    if (MCInst_getNumOperands(MI) == 3 &&
2828
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2829
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2830
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2831
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2832
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2833
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2834
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2835
0
      AsmString = "fmovqgu %xcc, $\x02, $\x01";
2836
0
      break;
2837
0
    }
2838
126
    if (MCInst_getNumOperands(MI) == 3 &&
2839
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2840
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2841
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2842
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2843
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2844
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2845
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2846
0
      AsmString = "fmovqleu %xcc, $\x02, $\x01";
2847
0
      break;
2848
0
    }
2849
126
    if (MCInst_getNumOperands(MI) == 3 &&
2850
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2851
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2852
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2853
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2854
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2855
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2856
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2857
0
      AsmString = "fmovqcc %xcc, $\x02, $\x01";
2858
0
      break;
2859
0
    }
2860
126
    if (MCInst_getNumOperands(MI) == 3 &&
2861
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2862
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2863
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2864
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2865
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2866
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2867
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2868
0
      AsmString = "fmovqcs %xcc, $\x02, $\x01";
2869
0
      break;
2870
0
    }
2871
126
    if (MCInst_getNumOperands(MI) == 3 &&
2872
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2873
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2874
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2875
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2876
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2877
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2878
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2879
0
      AsmString = "fmovqpos %xcc, $\x02, $\x01";
2880
0
      break;
2881
0
    }
2882
126
    if (MCInst_getNumOperands(MI) == 3 &&
2883
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2884
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2885
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2886
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2887
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2888
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2889
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2890
0
      AsmString = "fmovqneg %xcc, $\x02, $\x01";
2891
0
      break;
2892
0
    }
2893
126
    if (MCInst_getNumOperands(MI) == 3 &&
2894
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2895
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2896
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2897
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2898
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2899
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2900
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2901
0
      AsmString = "fmovqvc %xcc, $\x02, $\x01";
2902
0
      break;
2903
0
    }
2904
126
    if (MCInst_getNumOperands(MI) == 3 &&
2905
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2906
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2907
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2908
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2909
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2910
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2911
      // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2912
0
      AsmString = "fmovqvs %xcc, $\x02, $\x01";
2913
0
      break;
2914
0
    }
2915
126
    return NULL;
2916
53
  case SP_FMOVS_ICC:
2917
53
    if (MCInst_getNumOperands(MI) == 3 &&
2918
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2919
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2920
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2921
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2922
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2923
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2924
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2925
0
      AsmString = "fmovsa %icc, $\x02, $\x01";
2926
0
      break;
2927
0
    }
2928
53
    if (MCInst_getNumOperands(MI) == 3 &&
2929
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2930
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2931
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2932
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2933
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2934
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2935
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2936
0
      AsmString = "fmovsn %icc, $\x02, $\x01";
2937
0
      break;
2938
0
    }
2939
53
    if (MCInst_getNumOperands(MI) == 3 &&
2940
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2941
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2942
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2943
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2944
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2945
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2946
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2947
0
      AsmString = "fmovsne %icc, $\x02, $\x01";
2948
0
      break;
2949
0
    }
2950
53
    if (MCInst_getNumOperands(MI) == 3 &&
2951
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2952
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2953
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2954
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2955
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2956
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2957
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2958
0
      AsmString = "fmovse %icc, $\x02, $\x01";
2959
0
      break;
2960
0
    }
2961
53
    if (MCInst_getNumOperands(MI) == 3 &&
2962
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2963
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2964
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2965
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2966
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2967
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2968
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2969
0
      AsmString = "fmovsg %icc, $\x02, $\x01";
2970
0
      break;
2971
0
    }
2972
53
    if (MCInst_getNumOperands(MI) == 3 &&
2973
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2974
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2975
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2976
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2977
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2978
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2979
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2980
0
      AsmString = "fmovsle %icc, $\x02, $\x01";
2981
0
      break;
2982
0
    }
2983
53
    if (MCInst_getNumOperands(MI) == 3 &&
2984
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2985
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2986
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2987
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2988
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2989
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2990
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2991
0
      AsmString = "fmovsge %icc, $\x02, $\x01";
2992
0
      break;
2993
0
    }
2994
53
    if (MCInst_getNumOperands(MI) == 3 &&
2995
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2996
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2997
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2998
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2999
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3000
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3001
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3002
0
      AsmString = "fmovsl %icc, $\x02, $\x01";
3003
0
      break;
3004
0
    }
3005
53
    if (MCInst_getNumOperands(MI) == 3 &&
3006
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3007
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3008
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3009
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3010
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3011
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3012
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3013
0
      AsmString = "fmovsgu %icc, $\x02, $\x01";
3014
0
      break;
3015
0
    }
3016
53
    if (MCInst_getNumOperands(MI) == 3 &&
3017
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3018
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3019
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3020
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3021
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3022
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3023
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3024
0
      AsmString = "fmovsleu %icc, $\x02, $\x01";
3025
0
      break;
3026
0
    }
3027
53
    if (MCInst_getNumOperands(MI) == 3 &&
3028
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3029
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3030
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3031
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3032
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3033
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3034
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3035
0
      AsmString = "fmovscc %icc, $\x02, $\x01";
3036
0
      break;
3037
0
    }
3038
53
    if (MCInst_getNumOperands(MI) == 3 &&
3039
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3040
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3041
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3042
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3043
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3044
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3045
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3046
0
      AsmString = "fmovscs %icc, $\x02, $\x01";
3047
0
      break;
3048
0
    }
3049
53
    if (MCInst_getNumOperands(MI) == 3 &&
3050
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3051
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3052
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3053
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3054
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3055
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3056
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3057
0
      AsmString = "fmovspos %icc, $\x02, $\x01";
3058
0
      break;
3059
0
    }
3060
53
    if (MCInst_getNumOperands(MI) == 3 &&
3061
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3062
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3063
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3064
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3065
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3066
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3067
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3068
0
      AsmString = "fmovsneg %icc, $\x02, $\x01";
3069
0
      break;
3070
0
    }
3071
53
    if (MCInst_getNumOperands(MI) == 3 &&
3072
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3073
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3074
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3075
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3076
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3077
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3078
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3079
0
      AsmString = "fmovsvc %icc, $\x02, $\x01";
3080
0
      break;
3081
0
    }
3082
53
    if (MCInst_getNumOperands(MI) == 3 &&
3083
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3084
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3085
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3086
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3087
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3088
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3089
      // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3090
0
      AsmString = "fmovsvs %icc, $\x02, $\x01";
3091
0
      break;
3092
0
    }
3093
53
    return NULL;
3094
33
  case SP_FMOVS_XCC:
3095
33
    if (MCInst_getNumOperands(MI) == 3 &&
3096
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3097
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3098
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3099
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3100
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3101
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3102
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3103
0
      AsmString = "fmovsa %xcc, $\x02, $\x01";
3104
0
      break;
3105
0
    }
3106
33
    if (MCInst_getNumOperands(MI) == 3 &&
3107
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3108
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3109
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3110
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3111
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3112
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3113
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3114
0
      AsmString = "fmovsn %xcc, $\x02, $\x01";
3115
0
      break;
3116
0
    }
3117
33
    if (MCInst_getNumOperands(MI) == 3 &&
3118
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3119
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3120
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3121
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3122
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3123
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3124
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3125
0
      AsmString = "fmovsne %xcc, $\x02, $\x01";
3126
0
      break;
3127
0
    }
3128
33
    if (MCInst_getNumOperands(MI) == 3 &&
3129
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3130
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3131
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3132
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3133
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3134
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3135
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3136
0
      AsmString = "fmovse %xcc, $\x02, $\x01";
3137
0
      break;
3138
0
    }
3139
33
    if (MCInst_getNumOperands(MI) == 3 &&
3140
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3141
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3142
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3143
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3144
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3145
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3146
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3147
0
      AsmString = "fmovsg %xcc, $\x02, $\x01";
3148
0
      break;
3149
0
    }
3150
33
    if (MCInst_getNumOperands(MI) == 3 &&
3151
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3152
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3153
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3154
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3155
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3156
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3157
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3158
0
      AsmString = "fmovsle %xcc, $\x02, $\x01";
3159
0
      break;
3160
0
    }
3161
33
    if (MCInst_getNumOperands(MI) == 3 &&
3162
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3163
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3164
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3165
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3166
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3167
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3168
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3169
0
      AsmString = "fmovsge %xcc, $\x02, $\x01";
3170
0
      break;
3171
0
    }
3172
33
    if (MCInst_getNumOperands(MI) == 3 &&
3173
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3174
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3175
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3176
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3177
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3178
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3179
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3180
0
      AsmString = "fmovsl %xcc, $\x02, $\x01";
3181
0
      break;
3182
0
    }
3183
33
    if (MCInst_getNumOperands(MI) == 3 &&
3184
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3185
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3186
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3187
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3188
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3189
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3190
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3191
0
      AsmString = "fmovsgu %xcc, $\x02, $\x01";
3192
0
      break;
3193
0
    }
3194
33
    if (MCInst_getNumOperands(MI) == 3 &&
3195
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3196
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3197
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3198
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3199
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3200
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3201
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3202
0
      AsmString = "fmovsleu %xcc, $\x02, $\x01";
3203
0
      break;
3204
0
    }
3205
33
    if (MCInst_getNumOperands(MI) == 3 &&
3206
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3207
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3208
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3209
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3210
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3211
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3212
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3213
0
      AsmString = "fmovscc %xcc, $\x02, $\x01";
3214
0
      break;
3215
0
    }
3216
33
    if (MCInst_getNumOperands(MI) == 3 &&
3217
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3218
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3219
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3220
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3221
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3222
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3223
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3224
0
      AsmString = "fmovscs %xcc, $\x02, $\x01";
3225
0
      break;
3226
0
    }
3227
33
    if (MCInst_getNumOperands(MI) == 3 &&
3228
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3229
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3230
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3231
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3232
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3233
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3234
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3235
0
      AsmString = "fmovspos %xcc, $\x02, $\x01";
3236
0
      break;
3237
0
    }
3238
33
    if (MCInst_getNumOperands(MI) == 3 &&
3239
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3240
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3241
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3242
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3243
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3244
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3245
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3246
0
      AsmString = "fmovsneg %xcc, $\x02, $\x01";
3247
0
      break;
3248
0
    }
3249
33
    if (MCInst_getNumOperands(MI) == 3 &&
3250
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3251
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3252
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3253
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3254
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3255
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3256
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3257
0
      AsmString = "fmovsvc %xcc, $\x02, $\x01";
3258
0
      break;
3259
0
    }
3260
33
    if (MCInst_getNumOperands(MI) == 3 &&
3261
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3262
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3263
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3264
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3265
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3266
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3267
      // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3268
0
      AsmString = "fmovsvs %xcc, $\x02, $\x01";
3269
0
      break;
3270
0
    }
3271
33
    return NULL;
3272
108
  case SP_MOVICCri:
3273
108
    if (MCInst_getNumOperands(MI) == 3 &&
3274
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3275
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3276
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3277
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3278
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3279
0
      AsmString = "mova %icc, $\x02, $\x01";
3280
0
      break;
3281
0
    }
3282
108
    if (MCInst_getNumOperands(MI) == 3 &&
3283
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3284
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3285
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3286
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3287
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3288
0
      AsmString = "movn %icc, $\x02, $\x01";
3289
0
      break;
3290
0
    }
3291
108
    if (MCInst_getNumOperands(MI) == 3 &&
3292
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3293
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3294
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3295
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3296
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3297
0
      AsmString = "movne %icc, $\x02, $\x01";
3298
0
      break;
3299
0
    }
3300
108
    if (MCInst_getNumOperands(MI) == 3 &&
3301
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3302
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3303
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3304
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3305
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3306
0
      AsmString = "move %icc, $\x02, $\x01";
3307
0
      break;
3308
0
    }
3309
108
    if (MCInst_getNumOperands(MI) == 3 &&
3310
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3311
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3312
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3313
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3314
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3315
0
      AsmString = "movg %icc, $\x02, $\x01";
3316
0
      break;
3317
0
    }
3318
108
    if (MCInst_getNumOperands(MI) == 3 &&
3319
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3320
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3321
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3322
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3323
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3324
0
      AsmString = "movle %icc, $\x02, $\x01";
3325
0
      break;
3326
0
    }
3327
108
    if (MCInst_getNumOperands(MI) == 3 &&
3328
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3329
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3330
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3331
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3332
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3333
0
      AsmString = "movge %icc, $\x02, $\x01";
3334
0
      break;
3335
0
    }
3336
108
    if (MCInst_getNumOperands(MI) == 3 &&
3337
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3338
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3339
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3340
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3341
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3342
0
      AsmString = "movl %icc, $\x02, $\x01";
3343
0
      break;
3344
0
    }
3345
108
    if (MCInst_getNumOperands(MI) == 3 &&
3346
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3347
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3348
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3349
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3350
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3351
0
      AsmString = "movgu %icc, $\x02, $\x01";
3352
0
      break;
3353
0
    }
3354
108
    if (MCInst_getNumOperands(MI) == 3 &&
3355
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3356
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3357
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3358
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3359
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3360
0
      AsmString = "movleu %icc, $\x02, $\x01";
3361
0
      break;
3362
0
    }
3363
108
    if (MCInst_getNumOperands(MI) == 3 &&
3364
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3365
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3366
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3367
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3368
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3369
0
      AsmString = "movcc %icc, $\x02, $\x01";
3370
0
      break;
3371
0
    }
3372
108
    if (MCInst_getNumOperands(MI) == 3 &&
3373
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3374
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3375
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3376
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3377
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3378
0
      AsmString = "movcs %icc, $\x02, $\x01";
3379
0
      break;
3380
0
    }
3381
108
    if (MCInst_getNumOperands(MI) == 3 &&
3382
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3383
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3384
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3385
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3386
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3387
0
      AsmString = "movpos %icc, $\x02, $\x01";
3388
0
      break;
3389
0
    }
3390
108
    if (MCInst_getNumOperands(MI) == 3 &&
3391
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3392
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3393
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3394
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3395
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3396
0
      AsmString = "movneg %icc, $\x02, $\x01";
3397
0
      break;
3398
0
    }
3399
108
    if (MCInst_getNumOperands(MI) == 3 &&
3400
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3401
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3402
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3403
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3404
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3405
0
      AsmString = "movvc %icc, $\x02, $\x01";
3406
0
      break;
3407
0
    }
3408
108
    if (MCInst_getNumOperands(MI) == 3 &&
3409
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3410
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3411
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3412
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3413
      // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3414
0
      AsmString = "movvs %icc, $\x02, $\x01";
3415
0
      break;
3416
0
    }
3417
108
    return NULL;
3418
87
  case SP_MOVICCrr:
3419
87
    if (MCInst_getNumOperands(MI) == 3 &&
3420
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3421
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3422
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3423
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3424
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3425
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3426
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3427
0
      AsmString = "mova %icc, $\x02, $\x01";
3428
0
      break;
3429
0
    }
3430
87
    if (MCInst_getNumOperands(MI) == 3 &&
3431
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3432
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3433
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3434
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3435
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3436
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3437
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3438
0
      AsmString = "movn %icc, $\x02, $\x01";
3439
0
      break;
3440
0
    }
3441
87
    if (MCInst_getNumOperands(MI) == 3 &&
3442
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3443
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3444
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3445
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3446
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3447
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3448
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3449
0
      AsmString = "movne %icc, $\x02, $\x01";
3450
0
      break;
3451
0
    }
3452
87
    if (MCInst_getNumOperands(MI) == 3 &&
3453
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3454
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3455
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3456
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3457
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3458
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3459
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3460
0
      AsmString = "move %icc, $\x02, $\x01";
3461
0
      break;
3462
0
    }
3463
87
    if (MCInst_getNumOperands(MI) == 3 &&
3464
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3465
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3466
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3467
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3468
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3469
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3470
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3471
0
      AsmString = "movg %icc, $\x02, $\x01";
3472
0
      break;
3473
0
    }
3474
87
    if (MCInst_getNumOperands(MI) == 3 &&
3475
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3476
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3477
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3478
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3479
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3480
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3481
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3482
0
      AsmString = "movle %icc, $\x02, $\x01";
3483
0
      break;
3484
0
    }
3485
87
    if (MCInst_getNumOperands(MI) == 3 &&
3486
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3487
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3488
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3489
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3490
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3491
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3492
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3493
0
      AsmString = "movge %icc, $\x02, $\x01";
3494
0
      break;
3495
0
    }
3496
87
    if (MCInst_getNumOperands(MI) == 3 &&
3497
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3498
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3499
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3500
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3501
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3502
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3503
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3504
0
      AsmString = "movl %icc, $\x02, $\x01";
3505
0
      break;
3506
0
    }
3507
87
    if (MCInst_getNumOperands(MI) == 3 &&
3508
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3509
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3510
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3511
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3512
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3513
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3514
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3515
0
      AsmString = "movgu %icc, $\x02, $\x01";
3516
0
      break;
3517
0
    }
3518
87
    if (MCInst_getNumOperands(MI) == 3 &&
3519
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3520
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3521
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3522
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3523
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3524
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3525
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3526
0
      AsmString = "movleu %icc, $\x02, $\x01";
3527
0
      break;
3528
0
    }
3529
87
    if (MCInst_getNumOperands(MI) == 3 &&
3530
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3531
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3532
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3533
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3534
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3535
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3536
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3537
0
      AsmString = "movcc %icc, $\x02, $\x01";
3538
0
      break;
3539
0
    }
3540
87
    if (MCInst_getNumOperands(MI) == 3 &&
3541
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3542
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3543
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3544
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3545
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3546
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3547
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3548
0
      AsmString = "movcs %icc, $\x02, $\x01";
3549
0
      break;
3550
0
    }
3551
87
    if (MCInst_getNumOperands(MI) == 3 &&
3552
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3553
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3554
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3555
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3556
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3557
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3558
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3559
0
      AsmString = "movpos %icc, $\x02, $\x01";
3560
0
      break;
3561
0
    }
3562
87
    if (MCInst_getNumOperands(MI) == 3 &&
3563
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3564
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3565
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3566
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3567
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3568
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3569
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3570
0
      AsmString = "movneg %icc, $\x02, $\x01";
3571
0
      break;
3572
0
    }
3573
87
    if (MCInst_getNumOperands(MI) == 3 &&
3574
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3575
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3576
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3577
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3578
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3579
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3580
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3581
0
      AsmString = "movvc %icc, $\x02, $\x01";
3582
0
      break;
3583
0
    }
3584
87
    if (MCInst_getNumOperands(MI) == 3 &&
3585
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3586
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3587
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3588
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3589
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3590
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3591
      // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3592
0
      AsmString = "movvs %icc, $\x02, $\x01";
3593
0
      break;
3594
0
    }
3595
87
    return NULL;
3596
126
  case SP_MOVXCCri:
3597
126
    if (MCInst_getNumOperands(MI) == 3 &&
3598
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3599
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3600
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3601
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3602
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3603
0
      AsmString = "mova %xcc, $\x02, $\x01";
3604
0
      break;
3605
0
    }
3606
126
    if (MCInst_getNumOperands(MI) == 3 &&
3607
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3608
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3609
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3610
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3611
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3612
0
      AsmString = "movn %xcc, $\x02, $\x01";
3613
0
      break;
3614
0
    }
3615
126
    if (MCInst_getNumOperands(MI) == 3 &&
3616
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3617
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3618
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3619
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3620
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3621
0
      AsmString = "movne %xcc, $\x02, $\x01";
3622
0
      break;
3623
0
    }
3624
126
    if (MCInst_getNumOperands(MI) == 3 &&
3625
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3626
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3627
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3628
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3629
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3630
0
      AsmString = "move %xcc, $\x02, $\x01";
3631
0
      break;
3632
0
    }
3633
126
    if (MCInst_getNumOperands(MI) == 3 &&
3634
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3635
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3636
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3637
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3638
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3639
0
      AsmString = "movg %xcc, $\x02, $\x01";
3640
0
      break;
3641
0
    }
3642
126
    if (MCInst_getNumOperands(MI) == 3 &&
3643
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3644
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3645
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3646
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3647
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3648
0
      AsmString = "movle %xcc, $\x02, $\x01";
3649
0
      break;
3650
0
    }
3651
126
    if (MCInst_getNumOperands(MI) == 3 &&
3652
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3653
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3654
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3655
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3656
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3657
0
      AsmString = "movge %xcc, $\x02, $\x01";
3658
0
      break;
3659
0
    }
3660
126
    if (MCInst_getNumOperands(MI) == 3 &&
3661
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3662
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3663
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3664
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3665
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3666
0
      AsmString = "movl %xcc, $\x02, $\x01";
3667
0
      break;
3668
0
    }
3669
126
    if (MCInst_getNumOperands(MI) == 3 &&
3670
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3671
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3672
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3673
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3674
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3675
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3676
0
      break;
3677
0
    }
3678
126
    if (MCInst_getNumOperands(MI) == 3 &&
3679
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3680
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3681
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3682
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3683
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3684
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3685
0
      break;
3686
0
    }
3687
126
    if (MCInst_getNumOperands(MI) == 3 &&
3688
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3689
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3690
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3691
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3692
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3693
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3694
0
      break;
3695
0
    }
3696
126
    if (MCInst_getNumOperands(MI) == 3 &&
3697
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3698
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3699
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3700
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3701
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3702
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3703
0
      break;
3704
0
    }
3705
126
    if (MCInst_getNumOperands(MI) == 3 &&
3706
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3707
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3708
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3709
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3710
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3711
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3712
0
      break;
3713
0
    }
3714
126
    if (MCInst_getNumOperands(MI) == 3 &&
3715
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3716
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3717
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3718
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3719
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3720
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3721
0
      break;
3722
0
    }
3723
126
    if (MCInst_getNumOperands(MI) == 3 &&
3724
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3725
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3726
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3727
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3728
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3729
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3730
0
      break;
3731
0
    }
3732
126
    if (MCInst_getNumOperands(MI) == 3 &&
3733
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3734
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3735
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3736
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3737
      // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3738
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3739
0
      break;
3740
0
    }
3741
126
    return NULL;
3742
204
  case SP_MOVXCCrr:
3743
204
    if (MCInst_getNumOperands(MI) == 3 &&
3744
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3745
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3746
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3747
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3748
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3749
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3750
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3751
0
      AsmString = "mova %xcc, $\x02, $\x01";
3752
0
      break;
3753
0
    }
3754
204
    if (MCInst_getNumOperands(MI) == 3 &&
3755
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3756
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3757
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3758
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3759
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3760
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3761
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3762
0
      AsmString = "movn %xcc, $\x02, $\x01";
3763
0
      break;
3764
0
    }
3765
204
    if (MCInst_getNumOperands(MI) == 3 &&
3766
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3767
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3768
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3769
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3770
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3771
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3772
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3773
0
      AsmString = "movne %xcc, $\x02, $\x01";
3774
0
      break;
3775
0
    }
3776
204
    if (MCInst_getNumOperands(MI) == 3 &&
3777
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3778
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3779
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3780
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3781
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3782
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3783
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3784
0
      AsmString = "move %xcc, $\x02, $\x01";
3785
0
      break;
3786
0
    }
3787
204
    if (MCInst_getNumOperands(MI) == 3 &&
3788
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3789
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3790
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3791
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3792
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3793
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3794
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3795
0
      AsmString = "movg %xcc, $\x02, $\x01";
3796
0
      break;
3797
0
    }
3798
204
    if (MCInst_getNumOperands(MI) == 3 &&
3799
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3800
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3801
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3802
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3803
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3804
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3805
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3806
0
      AsmString = "movle %xcc, $\x02, $\x01";
3807
0
      break;
3808
0
    }
3809
204
    if (MCInst_getNumOperands(MI) == 3 &&
3810
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3811
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3812
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3813
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3814
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3815
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3816
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3817
0
      AsmString = "movge %xcc, $\x02, $\x01";
3818
0
      break;
3819
0
    }
3820
204
    if (MCInst_getNumOperands(MI) == 3 &&
3821
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3822
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3823
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3824
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3825
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3826
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3827
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3828
0
      AsmString = "movl %xcc, $\x02, $\x01";
3829
0
      break;
3830
0
    }
3831
204
    if (MCInst_getNumOperands(MI) == 3 &&
3832
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3833
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3834
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3835
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3836
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3837
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3838
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3839
0
      AsmString = "movgu %xcc, $\x02, $\x01";
3840
0
      break;
3841
0
    }
3842
204
    if (MCInst_getNumOperands(MI) == 3 &&
3843
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3844
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3845
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3846
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3847
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3848
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3849
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3850
0
      AsmString = "movleu %xcc, $\x02, $\x01";
3851
0
      break;
3852
0
    }
3853
204
    if (MCInst_getNumOperands(MI) == 3 &&
3854
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3855
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3856
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3857
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3858
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3859
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3860
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3861
0
      AsmString = "movcc %xcc, $\x02, $\x01";
3862
0
      break;
3863
0
    }
3864
204
    if (MCInst_getNumOperands(MI) == 3 &&
3865
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3866
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3867
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3868
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3869
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3870
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3871
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3872
0
      AsmString = "movcs %xcc, $\x02, $\x01";
3873
0
      break;
3874
0
    }
3875
204
    if (MCInst_getNumOperands(MI) == 3 &&
3876
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3877
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3878
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3879
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3880
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3881
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3882
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3883
0
      AsmString = "movpos %xcc, $\x02, $\x01";
3884
0
      break;
3885
0
    }
3886
204
    if (MCInst_getNumOperands(MI) == 3 &&
3887
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3888
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3889
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3890
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3891
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3892
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3893
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3894
0
      AsmString = "movneg %xcc, $\x02, $\x01";
3895
0
      break;
3896
0
    }
3897
204
    if (MCInst_getNumOperands(MI) == 3 &&
3898
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3899
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3900
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3901
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3902
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3903
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3904
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3905
0
      AsmString = "movvc %xcc, $\x02, $\x01";
3906
0
      break;
3907
0
    }
3908
204
    if (MCInst_getNumOperands(MI) == 3 &&
3909
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3910
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3911
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3912
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3913
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3914
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3915
      // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3916
0
      AsmString = "movvs %xcc, $\x02, $\x01";
3917
0
      break;
3918
0
    }
3919
204
    return NULL;
3920
239
  case SP_ORri:
3921
239
    if (MCInst_getNumOperands(MI) == 3 &&
3922
239
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3923
239
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3924
239
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3925
      // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3926
74
      AsmString = "mov $\x03, $\x01";
3927
74
      break;
3928
74
    }
3929
165
    return NULL;
3930
85
  case SP_ORrr:
3931
85
    if (MCInst_getNumOperands(MI) == 3 &&
3932
85
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3933
85
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3934
85
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3935
55
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3936
55
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3937
      // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3938
55
      AsmString = "mov $\x03, $\x01";
3939
55
      break;
3940
55
    }
3941
30
    return NULL;
3942
224
  case SP_RESTORErr:
3943
224
    if (MCInst_getNumOperands(MI) == 3 &&
3944
224
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3945
209
        MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3946
79
        MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3947
      // (RESTORErr G0, G0, G0)
3948
60
      AsmString = "restore";
3949
60
      break;
3950
60
    }
3951
164
    return NULL;
3952
0
  case SP_RET:
3953
0
    if (MCInst_getNumOperands(MI) == 1 &&
3954
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3955
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3956
      // (RET 8)
3957
0
      AsmString = "ret";
3958
0
      break;
3959
0
    }
3960
0
    return NULL;
3961
0
  case SP_RETL:
3962
0
    if (MCInst_getNumOperands(MI) == 1 &&
3963
0
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3964
0
        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3965
      // (RETL 8)
3966
0
      AsmString = "retl";
3967
0
      break;
3968
0
    }
3969
0
    return NULL;
3970
4.59k
  case SP_TXCCri:
3971
4.59k
    if (MCInst_getNumOperands(MI) == 3 &&
3972
4.59k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3973
4.59k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3974
4.59k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3975
4.59k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3976
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3977
504
      AsmString = "ta %xcc, $\x01 + $\x02";
3978
504
      break;
3979
504
    }
3980
4.09k
    if (MCInst_getNumOperands(MI) == 3 &&
3981
4.09k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3982
577
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3983
577
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3984
      // (TXCCri G0, i32imm:$imm, 8)
3985
0
      AsmString = "ta %xcc, $\x02";
3986
0
      break;
3987
0
    }
3988
4.09k
    if (MCInst_getNumOperands(MI) == 3 &&
3989
4.09k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3990
4.09k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3991
4.09k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3992
4.09k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3993
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3994
235
      AsmString = "tn %xcc, $\x01 + $\x02";
3995
235
      break;
3996
235
    }
3997
3.86k
    if (MCInst_getNumOperands(MI) == 3 &&
3998
3.86k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3999
570
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4000
570
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4001
      // (TXCCri G0, i32imm:$imm, 0)
4002
0
      AsmString = "tn %xcc, $\x02";
4003
0
      break;
4004
0
    }
4005
3.86k
    if (MCInst_getNumOperands(MI) == 3 &&
4006
3.86k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4007
3.86k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4008
3.86k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4009
3.86k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4010
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4011
270
      AsmString = "tne %xcc, $\x01 + $\x02";
4012
270
      break;
4013
270
    }
4014
3.59k
    if (MCInst_getNumOperands(MI) == 3 &&
4015
3.59k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4016
570
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4017
570
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4018
      // (TXCCri G0, i32imm:$imm, 9)
4019
0
      AsmString = "tne %xcc, $\x02";
4020
0
      break;
4021
0
    }
4022
3.59k
    if (MCInst_getNumOperands(MI) == 3 &&
4023
3.59k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4024
3.59k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4025
3.59k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4026
3.59k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4027
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4028
78
      AsmString = "te %xcc, $\x01 + $\x02";
4029
78
      break;
4030
78
    }
4031
3.51k
    if (MCInst_getNumOperands(MI) == 3 &&
4032
3.51k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4033
569
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4034
569
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4035
      // (TXCCri G0, i32imm:$imm, 1)
4036
0
      AsmString = "te %xcc, $\x02";
4037
0
      break;
4038
0
    }
4039
3.51k
    if (MCInst_getNumOperands(MI) == 3 &&
4040
3.51k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4041
3.51k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4042
3.51k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4043
3.51k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4044
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4045
289
      AsmString = "tg %xcc, $\x01 + $\x02";
4046
289
      break;
4047
289
    }
4048
3.22k
    if (MCInst_getNumOperands(MI) == 3 &&
4049
3.22k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4050
285
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4051
285
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4052
      // (TXCCri G0, i32imm:$imm, 10)
4053
0
      AsmString = "tg %xcc, $\x02";
4054
0
      break;
4055
0
    }
4056
3.22k
    if (MCInst_getNumOperands(MI) == 3 &&
4057
3.22k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4058
3.22k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4059
3.22k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4060
3.22k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4061
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4062
196
      AsmString = "tle %xcc, $\x01 + $\x02";
4063
196
      break;
4064
196
    }
4065
3.02k
    if (MCInst_getNumOperands(MI) == 3 &&
4066
3.02k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4067
280
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4068
280
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4069
      // (TXCCri G0, i32imm:$imm, 2)
4070
0
      AsmString = "tle %xcc, $\x02";
4071
0
      break;
4072
0
    }
4073
3.02k
    if (MCInst_getNumOperands(MI) == 3 &&
4074
3.02k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4075
3.02k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4076
3.02k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4077
3.02k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4078
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4079
77
      AsmString = "tge %xcc, $\x01 + $\x02";
4080
77
      break;
4081
77
    }
4082
2.95k
    if (MCInst_getNumOperands(MI) == 3 &&
4083
2.95k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4084
266
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4085
266
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4086
      // (TXCCri G0, i32imm:$imm, 11)
4087
0
      AsmString = "tge %xcc, $\x02";
4088
0
      break;
4089
0
    }
4090
2.95k
    if (MCInst_getNumOperands(MI) == 3 &&
4091
2.95k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4092
2.95k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4093
2.95k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4094
2.95k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4095
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4096
131
      AsmString = "tl %xcc, $\x01 + $\x02";
4097
131
      break;
4098
131
    }
4099
2.81k
    if (MCInst_getNumOperands(MI) == 3 &&
4100
2.81k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4101
265
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4102
265
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4103
      // (TXCCri G0, i32imm:$imm, 3)
4104
0
      AsmString = "tl %xcc, $\x02";
4105
0
      break;
4106
0
    }
4107
2.81k
    if (MCInst_getNumOperands(MI) == 3 &&
4108
2.81k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4109
2.81k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4110
2.81k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4111
2.81k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4112
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4113
700
      AsmString = "tgu %xcc, $\x01 + $\x02";
4114
700
      break;
4115
700
    }
4116
2.11k
    if (MCInst_getNumOperands(MI) == 3 &&
4117
2.11k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4118
265
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4119
265
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4120
      // (TXCCri G0, i32imm:$imm, 12)
4121
0
      AsmString = "tgu %xcc, $\x02";
4122
0
      break;
4123
0
    }
4124
2.11k
    if (MCInst_getNumOperands(MI) == 3 &&
4125
2.11k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4126
2.11k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4127
2.11k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4128
2.11k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4129
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4130
36
      AsmString = "tleu %xcc, $\x01 + $\x02";
4131
36
      break;
4132
36
    }
4133
2.08k
    if (MCInst_getNumOperands(MI) == 3 &&
4134
2.08k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4135
262
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4136
262
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4137
      // (TXCCri G0, i32imm:$imm, 4)
4138
0
      AsmString = "tleu %xcc, $\x02";
4139
0
      break;
4140
0
    }
4141
2.08k
    if (MCInst_getNumOperands(MI) == 3 &&
4142
2.08k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4143
2.08k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4144
2.08k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4145
2.08k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4146
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4147
415
      AsmString = "tcc %xcc, $\x01 + $\x02";
4148
415
      break;
4149
415
    }
4150
1.66k
    if (MCInst_getNumOperands(MI) == 3 &&
4151
1.66k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4152
262
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4153
262
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4154
      // (TXCCri G0, i32imm:$imm, 13)
4155
0
      AsmString = "tcc %xcc, $\x02";
4156
0
      break;
4157
0
    }
4158
1.66k
    if (MCInst_getNumOperands(MI) == 3 &&
4159
1.66k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4160
1.66k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4161
1.66k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4162
1.66k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4163
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4164
608
      AsmString = "tcs %xcc, $\x01 + $\x02";
4165
608
      break;
4166
608
    }
4167
1.06k
    if (MCInst_getNumOperands(MI) == 3 &&
4168
1.06k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4169
262
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4170
262
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4171
      // (TXCCri G0, i32imm:$imm, 5)
4172
0
      AsmString = "tcs %xcc, $\x02";
4173
0
      break;
4174
0
    }
4175
1.06k
    if (MCInst_getNumOperands(MI) == 3 &&
4176
1.06k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4177
1.06k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4178
1.06k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4179
1.06k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4180
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4181
92
      AsmString = "tpos %xcc, $\x01 + $\x02";
4182
92
      break;
4183
92
    }
4184
968
    if (MCInst_getNumOperands(MI) == 3 &&
4185
968
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4186
262
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4187
262
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4188
      // (TXCCri G0, i32imm:$imm, 14)
4189
0
      AsmString = "tpos %xcc, $\x02";
4190
0
      break;
4191
0
    }
4192
968
    if (MCInst_getNumOperands(MI) == 3 &&
4193
968
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4194
968
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4195
968
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4196
968
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4197
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4198
83
      AsmString = "tneg %xcc, $\x01 + $\x02";
4199
83
      break;
4200
83
    }
4201
885
    if (MCInst_getNumOperands(MI) == 3 &&
4202
885
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4203
229
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4204
229
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4205
      // (TXCCri G0, i32imm:$imm, 6)
4206
0
      AsmString = "tneg %xcc, $\x02";
4207
0
      break;
4208
0
    }
4209
885
    if (MCInst_getNumOperands(MI) == 3 &&
4210
885
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4211
885
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4212
885
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4213
885
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4214
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4215
225
      AsmString = "tvc %xcc, $\x01 + $\x02";
4216
225
      break;
4217
225
    }
4218
660
    if (MCInst_getNumOperands(MI) == 3 &&
4219
660
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4220
228
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4221
228
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4222
      // (TXCCri G0, i32imm:$imm, 15)
4223
0
      AsmString = "tvc %xcc, $\x02";
4224
0
      break;
4225
0
    }
4226
660
    if (MCInst_getNumOperands(MI) == 3 &&
4227
660
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4228
660
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4229
660
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4230
660
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4231
      // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4232
660
      AsmString = "tvs %xcc, $\x01 + $\x02";
4233
660
      break;
4234
660
    }
4235
0
    if (MCInst_getNumOperands(MI) == 3 &&
4236
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4237
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4238
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4239
      // (TXCCri G0, i32imm:$imm, 7)
4240
0
      AsmString = "tvs %xcc, $\x02";
4241
0
      break;
4242
0
    }
4243
0
    return NULL;
4244
1.87k
  case SP_TXCCrr:
4245
1.87k
    if (MCInst_getNumOperands(MI) == 3 &&
4246
1.87k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4247
1.87k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4248
1.87k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4249
1.87k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4250
1.87k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4251
1.87k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4252
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4253
61
      AsmString = "ta %xcc, $\x01 + $\x02";
4254
61
      break;
4255
61
    }
4256
1.81k
    if (MCInst_getNumOperands(MI) == 3 &&
4257
1.81k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4258
892
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4259
892
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4260
892
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4261
892
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4262
      // (TXCCrr G0, IntRegs:$rs2, 8)
4263
0
      AsmString = "ta %xcc, $\x02";
4264
0
      break;
4265
0
    }
4266
1.81k
    if (MCInst_getNumOperands(MI) == 3 &&
4267
1.81k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4268
1.81k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4269
1.81k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4270
1.81k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4271
1.81k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4272
1.81k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4273
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4274
134
      AsmString = "tn %xcc, $\x01 + $\x02";
4275
134
      break;
4276
134
    }
4277
1.68k
    if (MCInst_getNumOperands(MI) == 3 &&
4278
1.68k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4279
762
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4280
762
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4281
762
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4282
762
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4283
      // (TXCCrr G0, IntRegs:$rs2, 0)
4284
0
      AsmString = "tn %xcc, $\x02";
4285
0
      break;
4286
0
    }
4287
1.68k
    if (MCInst_getNumOperands(MI) == 3 &&
4288
1.68k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4289
1.68k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4290
1.68k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4291
1.68k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4292
1.68k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4293
1.68k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4294
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4295
62
      AsmString = "tne %xcc, $\x01 + $\x02";
4296
62
      break;
4297
62
    }
4298
1.62k
    if (MCInst_getNumOperands(MI) == 3 &&
4299
1.62k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4300
762
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4301
762
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4302
762
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4303
762
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4304
      // (TXCCrr G0, IntRegs:$rs2, 9)
4305
0
      AsmString = "tne %xcc, $\x02";
4306
0
      break;
4307
0
    }
4308
1.62k
    if (MCInst_getNumOperands(MI) == 3 &&
4309
1.62k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4310
1.62k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4311
1.62k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4312
1.62k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4313
1.62k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4314
1.62k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4315
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4316
68
      AsmString = "te %xcc, $\x01 + $\x02";
4317
68
      break;
4318
68
    }
4319
1.55k
    if (MCInst_getNumOperands(MI) == 3 &&
4320
1.55k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4321
762
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4322
762
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4323
762
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4324
762
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4325
      // (TXCCrr G0, IntRegs:$rs2, 1)
4326
0
      AsmString = "te %xcc, $\x02";
4327
0
      break;
4328
0
    }
4329
1.55k
    if (MCInst_getNumOperands(MI) == 3 &&
4330
1.55k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4331
1.55k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4332
1.55k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4333
1.55k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4334
1.55k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4335
1.55k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4336
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4337
190
      AsmString = "tg %xcc, $\x01 + $\x02";
4338
190
      break;
4339
190
    }
4340
1.36k
    if (MCInst_getNumOperands(MI) == 3 &&
4341
1.36k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4342
761
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4343
761
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4344
761
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4345
761
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4346
      // (TXCCrr G0, IntRegs:$rs2, 10)
4347
0
      AsmString = "tg %xcc, $\x02";
4348
0
      break;
4349
0
    }
4350
1.36k
    if (MCInst_getNumOperands(MI) == 3 &&
4351
1.36k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4352
1.36k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4353
1.36k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4354
1.36k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4355
1.36k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4356
1.36k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4357
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4358
54
      AsmString = "tle %xcc, $\x01 + $\x02";
4359
54
      break;
4360
54
    }
4361
1.31k
    if (MCInst_getNumOperands(MI) == 3 &&
4362
1.31k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4363
760
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4364
760
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4365
760
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4366
760
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4367
      // (TXCCrr G0, IntRegs:$rs2, 2)
4368
0
      AsmString = "tle %xcc, $\x02";
4369
0
      break;
4370
0
    }
4371
1.31k
    if (MCInst_getNumOperands(MI) == 3 &&
4372
1.31k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4373
1.31k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4374
1.31k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4375
1.31k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4376
1.31k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4377
1.31k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4378
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4379
18
      AsmString = "tge %xcc, $\x01 + $\x02";
4380
18
      break;
4381
18
    }
4382
1.29k
    if (MCInst_getNumOperands(MI) == 3 &&
4383
1.29k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4384
757
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4385
757
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4386
757
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4387
757
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4388
      // (TXCCrr G0, IntRegs:$rs2, 11)
4389
0
      AsmString = "tge %xcc, $\x02";
4390
0
      break;
4391
0
    }
4392
1.29k
    if (MCInst_getNumOperands(MI) == 3 &&
4393
1.29k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4394
1.29k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4395
1.29k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4396
1.29k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4397
1.29k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4398
1.29k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4399
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4400
238
      AsmString = "tl %xcc, $\x01 + $\x02";
4401
238
      break;
4402
238
    }
4403
1.05k
    if (MCInst_getNumOperands(MI) == 3 &&
4404
1.05k
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4405
526
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4406
526
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4407
526
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4408
526
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4409
      // (TXCCrr G0, IntRegs:$rs2, 3)
4410
0
      AsmString = "tl %xcc, $\x02";
4411
0
      break;
4412
0
    }
4413
1.05k
    if (MCInst_getNumOperands(MI) == 3 &&
4414
1.05k
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4415
1.05k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4416
1.05k
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4417
1.05k
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4418
1.05k
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4419
1.05k
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4420
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4421
235
      AsmString = "tgu %xcc, $\x01 + $\x02";
4422
235
      break;
4423
235
    }
4424
819
    if (MCInst_getNumOperands(MI) == 3 &&
4425
819
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4426
526
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4427
526
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4428
526
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4429
526
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4430
      // (TXCCrr G0, IntRegs:$rs2, 12)
4431
0
      AsmString = "tgu %xcc, $\x02";
4432
0
      break;
4433
0
    }
4434
819
    if (MCInst_getNumOperands(MI) == 3 &&
4435
819
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4436
819
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4437
819
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4438
819
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4439
819
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4440
819
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4441
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4442
6
      AsmString = "tleu %xcc, $\x01 + $\x02";
4443
6
      break;
4444
6
    }
4445
813
    if (MCInst_getNumOperands(MI) == 3 &&
4446
813
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4447
526
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4448
526
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4449
526
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4450
526
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4451
      // (TXCCrr G0, IntRegs:$rs2, 4)
4452
0
      AsmString = "tleu %xcc, $\x02";
4453
0
      break;
4454
0
    }
4455
813
    if (MCInst_getNumOperands(MI) == 3 &&
4456
813
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4457
813
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4458
813
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4459
813
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4460
813
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4461
813
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4462
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4463
85
      AsmString = "tcc %xcc, $\x01 + $\x02";
4464
85
      break;
4465
85
    }
4466
728
    if (MCInst_getNumOperands(MI) == 3 &&
4467
728
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4468
526
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4469
526
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4470
526
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4471
526
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4472
      // (TXCCrr G0, IntRegs:$rs2, 13)
4473
0
      AsmString = "tcc %xcc, $\x02";
4474
0
      break;
4475
0
    }
4476
728
    if (MCInst_getNumOperands(MI) == 3 &&
4477
728
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4478
728
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4479
728
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4480
728
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4481
728
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4482
728
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4483
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4484
103
      AsmString = "tcs %xcc, $\x01 + $\x02";
4485
103
      break;
4486
103
    }
4487
625
    if (MCInst_getNumOperands(MI) == 3 &&
4488
625
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4489
526
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4490
526
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4491
526
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4492
526
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4493
      // (TXCCrr G0, IntRegs:$rs2, 5)
4494
0
      AsmString = "tcs %xcc, $\x02";
4495
0
      break;
4496
0
    }
4497
625
    if (MCInst_getNumOperands(MI) == 3 &&
4498
625
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4499
625
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4500
625
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4501
625
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4502
625
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4503
625
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4504
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4505
7
      AsmString = "tpos %xcc, $\x01 + $\x02";
4506
7
      break;
4507
7
    }
4508
618
    if (MCInst_getNumOperands(MI) == 3 &&
4509
618
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4510
522
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4511
522
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4512
522
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4513
522
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4514
      // (TXCCrr G0, IntRegs:$rs2, 14)
4515
0
      AsmString = "tpos %xcc, $\x02";
4516
0
      break;
4517
0
    }
4518
618
    if (MCInst_getNumOperands(MI) == 3 &&
4519
618
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4520
618
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4521
618
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4522
618
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4523
618
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4524
618
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4525
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4526
56
      AsmString = "tneg %xcc, $\x01 + $\x02";
4527
56
      break;
4528
56
    }
4529
562
    if (MCInst_getNumOperands(MI) == 3 &&
4530
562
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4531
470
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4532
470
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4533
470
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4534
470
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4535
      // (TXCCrr G0, IntRegs:$rs2, 6)
4536
0
      AsmString = "tneg %xcc, $\x02";
4537
0
      break;
4538
0
    }
4539
562
    if (MCInst_getNumOperands(MI) == 3 &&
4540
562
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4541
562
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4542
562
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4543
562
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4544
562
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4545
562
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4546
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4547
155
      AsmString = "tvc %xcc, $\x01 + $\x02";
4548
155
      break;
4549
155
    }
4550
407
    if (MCInst_getNumOperands(MI) == 3 &&
4551
407
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4552
323
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4553
323
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4554
323
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4555
323
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4556
      // (TXCCrr G0, IntRegs:$rs2, 15)
4557
0
      AsmString = "tvc %xcc, $\x02";
4558
0
      break;
4559
0
    }
4560
407
    if (MCInst_getNumOperands(MI) == 3 &&
4561
407
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4562
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4563
407
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4564
407
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4565
407
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4566
407
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4567
      // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4568
407
      AsmString = "tvs %xcc, $\x01 + $\x02";
4569
407
      break;
4570
407
    }
4571
0
    if (MCInst_getNumOperands(MI) == 3 &&
4572
0
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4573
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4574
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4575
0
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4576
0
        MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4577
      // (TXCCrr G0, IntRegs:$rs2, 7)
4578
0
      AsmString = "tvs %xcc, $\x02";
4579
0
      break;
4580
0
    }
4581
0
    return NULL;
4582
102
  case SP_V9FCMPD:
4583
102
    if (MCInst_getNumOperands(MI) == 3 &&
4584
102
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4585
87
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4586
87
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4587
87
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4588
87
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4589
      // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4590
87
      AsmString = "fcmpd $\x02, $\x03";
4591
87
      break;
4592
87
    }
4593
15
    return NULL;
4594
266
  case SP_V9FCMPED:
4595
266
    if (MCInst_getNumOperands(MI) == 3 &&
4596
266
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4597
61
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4598
61
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4599
61
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4600
61
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4601
      // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4602
61
      AsmString = "fcmped $\x02, $\x03";
4603
61
      break;
4604
61
    }
4605
205
    return NULL;
4606
150
  case SP_V9FCMPEQ:
4607
150
    if (MCInst_getNumOperands(MI) == 3 &&
4608
150
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4609
36
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4610
36
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4611
36
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4612
36
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4613
      // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4614
36
      AsmString = "fcmpeq $\x02, $\x03";
4615
36
      break;
4616
36
    }
4617
114
    return NULL;
4618
188
  case SP_V9FCMPES:
4619
188
    if (MCInst_getNumOperands(MI) == 3 &&
4620
188
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4621
51
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4622
51
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4623
51
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4624
51
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4625
      // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4626
51
      AsmString = "fcmpes $\x02, $\x03";
4627
51
      break;
4628
51
    }
4629
137
    return NULL;
4630
749
  case SP_V9FCMPQ:
4631
749
    if (MCInst_getNumOperands(MI) == 3 &&
4632
749
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4633
226
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4634
226
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4635
226
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4636
226
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4637
      // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4638
226
      AsmString = "fcmpq $\x02, $\x03";
4639
226
      break;
4640
226
    }
4641
523
    return NULL;
4642
449
  case SP_V9FCMPS:
4643
449
    if (MCInst_getNumOperands(MI) == 3 &&
4644
449
        MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4645
351
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4646
351
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4647
351
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4648
351
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4649
      // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4650
351
      AsmString = "fcmps $\x02, $\x03";
4651
351
      break;
4652
351
    }
4653
98
    return NULL;
4654
84
  case SP_V9FMOVD_FCC:
4655
84
    if (MCInst_getNumOperands(MI) == 4 &&
4656
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4657
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4658
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4659
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4660
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4661
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4662
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4663
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4664
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4665
0
      AsmString = "fmovda $\x02, $\x03, $\x01";
4666
0
      break;
4667
0
    }
4668
84
    if (MCInst_getNumOperands(MI) == 4 &&
4669
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4670
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4671
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4672
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4673
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4674
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4675
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4676
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4677
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4678
0
      AsmString = "fmovdn $\x02, $\x03, $\x01";
4679
0
      break;
4680
0
    }
4681
84
    if (MCInst_getNumOperands(MI) == 4 &&
4682
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4683
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4684
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4685
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4686
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4687
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4688
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4689
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4690
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4691
0
      AsmString = "fmovdu $\x02, $\x03, $\x01";
4692
0
      break;
4693
0
    }
4694
84
    if (MCInst_getNumOperands(MI) == 4 &&
4695
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4696
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4697
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4698
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4699
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4700
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4701
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4702
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4703
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4704
0
      AsmString = "fmovdg $\x02, $\x03, $\x01";
4705
0
      break;
4706
0
    }
4707
84
    if (MCInst_getNumOperands(MI) == 4 &&
4708
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4709
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4710
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4711
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4712
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4713
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4714
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4715
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4716
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4717
0
      AsmString = "fmovdug $\x02, $\x03, $\x01";
4718
0
      break;
4719
0
    }
4720
84
    if (MCInst_getNumOperands(MI) == 4 &&
4721
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4722
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4723
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4724
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4725
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4726
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4727
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4728
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4729
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4730
0
      AsmString = "fmovdl $\x02, $\x03, $\x01";
4731
0
      break;
4732
0
    }
4733
84
    if (MCInst_getNumOperands(MI) == 4 &&
4734
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4735
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4736
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4737
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4738
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4739
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4740
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4741
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4742
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4743
0
      AsmString = "fmovdul $\x02, $\x03, $\x01";
4744
0
      break;
4745
0
    }
4746
84
    if (MCInst_getNumOperands(MI) == 4 &&
4747
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4748
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4749
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4750
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4751
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4752
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4753
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4754
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4755
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4756
0
      AsmString = "fmovdlg $\x02, $\x03, $\x01";
4757
0
      break;
4758
0
    }
4759
84
    if (MCInst_getNumOperands(MI) == 4 &&
4760
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4761
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4762
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4763
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4764
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4765
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4766
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4767
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4768
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4769
0
      AsmString = "fmovdne $\x02, $\x03, $\x01";
4770
0
      break;
4771
0
    }
4772
84
    if (MCInst_getNumOperands(MI) == 4 &&
4773
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4774
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4775
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4776
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4777
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4778
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4779
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4780
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4781
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4782
0
      AsmString = "fmovde $\x02, $\x03, $\x01";
4783
0
      break;
4784
0
    }
4785
84
    if (MCInst_getNumOperands(MI) == 4 &&
4786
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4787
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4788
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4789
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4790
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4791
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4792
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4793
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4794
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4795
0
      AsmString = "fmovdue $\x02, $\x03, $\x01";
4796
0
      break;
4797
0
    }
4798
84
    if (MCInst_getNumOperands(MI) == 4 &&
4799
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4800
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4801
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4802
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4803
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4804
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4805
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4806
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4807
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4808
0
      AsmString = "fmovdge $\x02, $\x03, $\x01";
4809
0
      break;
4810
0
    }
4811
84
    if (MCInst_getNumOperands(MI) == 4 &&
4812
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4813
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4814
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4815
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4816
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4817
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4818
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4819
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4820
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4821
0
      AsmString = "fmovduge $\x02, $\x03, $\x01";
4822
0
      break;
4823
0
    }
4824
84
    if (MCInst_getNumOperands(MI) == 4 &&
4825
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4826
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4827
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4828
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4829
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4830
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4831
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4832
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4833
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4834
0
      AsmString = "fmovdle $\x02, $\x03, $\x01";
4835
0
      break;
4836
0
    }
4837
84
    if (MCInst_getNumOperands(MI) == 4 &&
4838
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4839
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4840
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4841
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4842
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4843
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4844
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4845
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4846
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4847
0
      AsmString = "fmovdule $\x02, $\x03, $\x01";
4848
0
      break;
4849
0
    }
4850
84
    if (MCInst_getNumOperands(MI) == 4 &&
4851
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4852
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4853
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4854
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4855
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4856
0
        GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4857
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4858
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4859
      // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4860
0
      AsmString = "fmovdo $\x02, $\x03, $\x01";
4861
0
      break;
4862
0
    }
4863
84
    return NULL;
4864
101
  case SP_V9FMOVQ_FCC:
4865
101
    if (MCInst_getNumOperands(MI) == 4 &&
4866
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4867
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4868
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4869
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4870
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4871
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4872
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4873
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4874
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4875
0
      AsmString = "fmovqa $\x02, $\x03, $\x01";
4876
0
      break;
4877
0
    }
4878
101
    if (MCInst_getNumOperands(MI) == 4 &&
4879
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4880
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4881
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4882
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4883
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4884
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4885
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4886
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4887
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4888
0
      AsmString = "fmovqn $\x02, $\x03, $\x01";
4889
0
      break;
4890
0
    }
4891
101
    if (MCInst_getNumOperands(MI) == 4 &&
4892
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4893
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4894
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4895
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4896
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4897
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4898
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4899
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4900
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4901
0
      AsmString = "fmovqu $\x02, $\x03, $\x01";
4902
0
      break;
4903
0
    }
4904
101
    if (MCInst_getNumOperands(MI) == 4 &&
4905
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4906
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4907
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4908
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4909
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4910
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4911
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4912
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4913
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4914
0
      AsmString = "fmovqg $\x02, $\x03, $\x01";
4915
0
      break;
4916
0
    }
4917
101
    if (MCInst_getNumOperands(MI) == 4 &&
4918
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4919
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4920
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4921
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4922
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4923
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4924
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4925
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4926
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4927
0
      AsmString = "fmovqug $\x02, $\x03, $\x01";
4928
0
      break;
4929
0
    }
4930
101
    if (MCInst_getNumOperands(MI) == 4 &&
4931
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4932
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4933
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4934
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4935
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4936
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4937
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4938
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4939
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4940
0
      AsmString = "fmovql $\x02, $\x03, $\x01";
4941
0
      break;
4942
0
    }
4943
101
    if (MCInst_getNumOperands(MI) == 4 &&
4944
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4945
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4946
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4947
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4948
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4949
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4950
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4951
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4952
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4953
0
      AsmString = "fmovqul $\x02, $\x03, $\x01";
4954
0
      break;
4955
0
    }
4956
101
    if (MCInst_getNumOperands(MI) == 4 &&
4957
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4958
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4959
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4960
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4961
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4962
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4963
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4964
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4965
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4966
0
      AsmString = "fmovqlg $\x02, $\x03, $\x01";
4967
0
      break;
4968
0
    }
4969
101
    if (MCInst_getNumOperands(MI) == 4 &&
4970
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4971
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4972
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4973
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4974
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4975
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4976
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4977
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4978
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4979
0
      AsmString = "fmovqne $\x02, $\x03, $\x01";
4980
0
      break;
4981
0
    }
4982
101
    if (MCInst_getNumOperands(MI) == 4 &&
4983
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4984
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4985
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4986
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4987
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4988
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4989
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4990
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4991
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4992
0
      AsmString = "fmovqe $\x02, $\x03, $\x01";
4993
0
      break;
4994
0
    }
4995
101
    if (MCInst_getNumOperands(MI) == 4 &&
4996
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4997
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4998
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4999
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5000
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5001
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5002
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5003
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5004
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5005
0
      AsmString = "fmovque $\x02, $\x03, $\x01";
5006
0
      break;
5007
0
    }
5008
101
    if (MCInst_getNumOperands(MI) == 4 &&
5009
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5010
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5011
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5012
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5013
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5014
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5015
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5016
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5017
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5018
0
      AsmString = "fmovqge $\x02, $\x03, $\x01";
5019
0
      break;
5020
0
    }
5021
101
    if (MCInst_getNumOperands(MI) == 4 &&
5022
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5023
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5024
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5025
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5026
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5027
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5028
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5029
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5030
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5031
0
      AsmString = "fmovquge $\x02, $\x03, $\x01";
5032
0
      break;
5033
0
    }
5034
101
    if (MCInst_getNumOperands(MI) == 4 &&
5035
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5036
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5037
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5038
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5039
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5040
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5041
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5042
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5043
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5044
0
      AsmString = "fmovqle $\x02, $\x03, $\x01";
5045
0
      break;
5046
0
    }
5047
101
    if (MCInst_getNumOperands(MI) == 4 &&
5048
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5049
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5050
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5051
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5052
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5053
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5054
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5055
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5056
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5057
0
      AsmString = "fmovqule $\x02, $\x03, $\x01";
5058
0
      break;
5059
0
    }
5060
101
    if (MCInst_getNumOperands(MI) == 4 &&
5061
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5062
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5063
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5064
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5065
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5066
0
        GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5067
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5068
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5069
      // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5070
0
      AsmString = "fmovqo $\x02, $\x03, $\x01";
5071
0
      break;
5072
0
    }
5073
101
    return NULL;
5074
50
  case SP_V9FMOVS_FCC:
5075
50
    if (MCInst_getNumOperands(MI) == 4 &&
5076
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5077
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5078
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5079
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5080
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5081
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5082
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5083
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5084
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5085
0
      AsmString = "fmovsa $\x02, $\x03, $\x01";
5086
0
      break;
5087
0
    }
5088
50
    if (MCInst_getNumOperands(MI) == 4 &&
5089
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5090
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5091
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5092
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5093
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5094
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5095
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5096
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5097
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5098
0
      AsmString = "fmovsn $\x02, $\x03, $\x01";
5099
0
      break;
5100
0
    }
5101
50
    if (MCInst_getNumOperands(MI) == 4 &&
5102
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5103
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5104
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5105
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5106
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5107
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5108
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5109
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5110
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5111
0
      AsmString = "fmovsu $\x02, $\x03, $\x01";
5112
0
      break;
5113
0
    }
5114
50
    if (MCInst_getNumOperands(MI) == 4 &&
5115
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5116
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5117
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5118
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5119
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5120
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5121
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5122
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5123
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5124
0
      AsmString = "fmovsg $\x02, $\x03, $\x01";
5125
0
      break;
5126
0
    }
5127
50
    if (MCInst_getNumOperands(MI) == 4 &&
5128
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5129
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5130
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5131
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5132
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5133
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5134
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5135
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5136
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5137
0
      AsmString = "fmovsug $\x02, $\x03, $\x01";
5138
0
      break;
5139
0
    }
5140
50
    if (MCInst_getNumOperands(MI) == 4 &&
5141
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5142
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5143
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5144
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5145
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5146
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5147
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5148
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5149
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5150
0
      AsmString = "fmovsl $\x02, $\x03, $\x01";
5151
0
      break;
5152
0
    }
5153
50
    if (MCInst_getNumOperands(MI) == 4 &&
5154
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5155
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5156
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5157
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5158
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5159
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5160
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5161
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5162
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5163
0
      AsmString = "fmovsul $\x02, $\x03, $\x01";
5164
0
      break;
5165
0
    }
5166
50
    if (MCInst_getNumOperands(MI) == 4 &&
5167
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5168
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5169
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5170
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5171
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5172
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5173
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5174
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5175
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5176
0
      AsmString = "fmovslg $\x02, $\x03, $\x01";
5177
0
      break;
5178
0
    }
5179
50
    if (MCInst_getNumOperands(MI) == 4 &&
5180
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5181
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5182
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5183
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5184
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5185
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5186
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5187
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5188
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5189
0
      AsmString = "fmovsne $\x02, $\x03, $\x01";
5190
0
      break;
5191
0
    }
5192
50
    if (MCInst_getNumOperands(MI) == 4 &&
5193
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5194
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5195
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5196
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5197
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5198
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5199
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5200
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5201
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5202
0
      AsmString = "fmovse $\x02, $\x03, $\x01";
5203
0
      break;
5204
0
    }
5205
50
    if (MCInst_getNumOperands(MI) == 4 &&
5206
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5207
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5208
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5209
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5210
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5211
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5212
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5213
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5214
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5215
0
      AsmString = "fmovsue $\x02, $\x03, $\x01";
5216
0
      break;
5217
0
    }
5218
50
    if (MCInst_getNumOperands(MI) == 4 &&
5219
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5220
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5221
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5222
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5223
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5224
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5225
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5226
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5227
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5228
0
      AsmString = "fmovsge $\x02, $\x03, $\x01";
5229
0
      break;
5230
0
    }
5231
50
    if (MCInst_getNumOperands(MI) == 4 &&
5232
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5233
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5234
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5235
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5236
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5237
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5238
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5239
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5240
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5241
0
      AsmString = "fmovsuge $\x02, $\x03, $\x01";
5242
0
      break;
5243
0
    }
5244
50
    if (MCInst_getNumOperands(MI) == 4 &&
5245
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5246
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5247
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5248
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5249
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5250
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5251
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5252
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5253
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5254
0
      AsmString = "fmovsle $\x02, $\x03, $\x01";
5255
0
      break;
5256
0
    }
5257
50
    if (MCInst_getNumOperands(MI) == 4 &&
5258
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5259
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5260
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5261
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5262
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5263
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5264
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5265
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5266
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5267
0
      AsmString = "fmovsule $\x02, $\x03, $\x01";
5268
0
      break;
5269
0
    }
5270
50
    if (MCInst_getNumOperands(MI) == 4 &&
5271
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5272
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5273
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5274
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5275
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5276
0
        GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5277
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5278
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5279
      // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5280
0
      AsmString = "fmovso $\x02, $\x03, $\x01";
5281
0
      break;
5282
0
    }
5283
50
    return NULL;
5284
129
  case SP_V9MOVFCCri:
5285
129
    if (MCInst_getNumOperands(MI) == 4 &&
5286
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5287
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5288
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5289
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5290
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5291
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5292
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5293
0
      AsmString = "mova $\x02, $\x03, $\x01";
5294
0
      break;
5295
0
    }
5296
129
    if (MCInst_getNumOperands(MI) == 4 &&
5297
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5298
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5299
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5300
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5301
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5302
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5303
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5304
0
      AsmString = "movn $\x02, $\x03, $\x01";
5305
0
      break;
5306
0
    }
5307
129
    if (MCInst_getNumOperands(MI) == 4 &&
5308
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5309
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5310
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5311
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5312
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5313
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5314
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5315
0
      AsmString = "movu $\x02, $\x03, $\x01";
5316
0
      break;
5317
0
    }
5318
129
    if (MCInst_getNumOperands(MI) == 4 &&
5319
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5320
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5321
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5322
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5323
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5324
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5325
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5326
0
      AsmString = "movg $\x02, $\x03, $\x01";
5327
0
      break;
5328
0
    }
5329
129
    if (MCInst_getNumOperands(MI) == 4 &&
5330
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5331
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5332
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5333
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5334
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5335
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5336
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5337
0
      AsmString = "movug $\x02, $\x03, $\x01";
5338
0
      break;
5339
0
    }
5340
129
    if (MCInst_getNumOperands(MI) == 4 &&
5341
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5342
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5343
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5344
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5345
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5346
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5347
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5348
0
      AsmString = "movl $\x02, $\x03, $\x01";
5349
0
      break;
5350
0
    }
5351
129
    if (MCInst_getNumOperands(MI) == 4 &&
5352
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5353
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5354
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5355
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5356
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5357
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5358
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5359
0
      AsmString = "movul $\x02, $\x03, $\x01";
5360
0
      break;
5361
0
    }
5362
129
    if (MCInst_getNumOperands(MI) == 4 &&
5363
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5364
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5365
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5366
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5367
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5368
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5369
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5370
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5371
0
      break;
5372
0
    }
5373
129
    if (MCInst_getNumOperands(MI) == 4 &&
5374
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5375
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5376
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5377
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5378
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5379
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5380
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5381
0
      AsmString = "movne $\x02, $\x03, $\x01";
5382
0
      break;
5383
0
    }
5384
129
    if (MCInst_getNumOperands(MI) == 4 &&
5385
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5386
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5387
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5388
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5389
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5390
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5391
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5392
0
      AsmString = "move $\x02, $\x03, $\x01";
5393
0
      break;
5394
0
    }
5395
129
    if (MCInst_getNumOperands(MI) == 4 &&
5396
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5397
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5398
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5399
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5400
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5401
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5402
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5403
0
      AsmString = "movue $\x02, $\x03, $\x01";
5404
0
      break;
5405
0
    }
5406
129
    if (MCInst_getNumOperands(MI) == 4 &&
5407
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5408
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5409
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5410
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5411
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5412
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5413
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5414
0
      AsmString = "movge $\x02, $\x03, $\x01";
5415
0
      break;
5416
0
    }
5417
129
    if (MCInst_getNumOperands(MI) == 4 &&
5418
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5419
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5420
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5421
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5422
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5423
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5424
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5425
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5426
0
      break;
5427
0
    }
5428
129
    if (MCInst_getNumOperands(MI) == 4 &&
5429
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5430
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5431
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5432
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5433
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5434
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5435
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5436
0
      AsmString = "movle $\x02, $\x03, $\x01";
5437
0
      break;
5438
0
    }
5439
129
    if (MCInst_getNumOperands(MI) == 4 &&
5440
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5441
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5442
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5443
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5444
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5445
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5446
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5447
0
      AsmString = "movule $\x02, $\x03, $\x01";
5448
0
      break;
5449
0
    }
5450
129
    if (MCInst_getNumOperands(MI) == 4 &&
5451
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5452
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5453
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5454
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5455
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5456
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5457
      // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5458
0
      AsmString = "movo $\x02, $\x03, $\x01";
5459
0
      break;
5460
0
    }
5461
129
    return NULL;
5462
221
  case SP_V9MOVFCCrr:
5463
221
    if (MCInst_getNumOperands(MI) == 4 &&
5464
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5465
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5466
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5467
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5468
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5469
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5470
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5471
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5472
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5473
0
      AsmString = "mova $\x02, $\x03, $\x01";
5474
0
      break;
5475
0
    }
5476
221
    if (MCInst_getNumOperands(MI) == 4 &&
5477
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5478
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5479
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5480
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5481
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5482
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5483
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5484
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5485
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5486
0
      AsmString = "movn $\x02, $\x03, $\x01";
5487
0
      break;
5488
0
    }
5489
221
    if (MCInst_getNumOperands(MI) == 4 &&
5490
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5491
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5492
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5493
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5494
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5495
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5496
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5497
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5498
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5499
0
      AsmString = "movu $\x02, $\x03, $\x01";
5500
0
      break;
5501
0
    }
5502
221
    if (MCInst_getNumOperands(MI) == 4 &&
5503
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5504
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5505
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5506
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5507
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5508
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5509
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5510
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5511
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5512
0
      AsmString = "movg $\x02, $\x03, $\x01";
5513
0
      break;
5514
0
    }
5515
221
    if (MCInst_getNumOperands(MI) == 4 &&
5516
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5517
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5518
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5519
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5520
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5521
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5522
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5523
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5524
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5525
0
      AsmString = "movug $\x02, $\x03, $\x01";
5526
0
      break;
5527
0
    }
5528
221
    if (MCInst_getNumOperands(MI) == 4 &&
5529
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5530
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5531
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5532
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5533
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5534
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5535
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5536
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5537
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5538
0
      AsmString = "movl $\x02, $\x03, $\x01";
5539
0
      break;
5540
0
    }
5541
221
    if (MCInst_getNumOperands(MI) == 4 &&
5542
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5543
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5544
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5545
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5546
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5547
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5548
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5549
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5550
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5551
0
      AsmString = "movul $\x02, $\x03, $\x01";
5552
0
      break;
5553
0
    }
5554
221
    if (MCInst_getNumOperands(MI) == 4 &&
5555
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5556
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5557
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5558
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5559
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5560
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5561
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5562
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5563
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5564
0
      AsmString = "movlg $\x02, $\x03, $\x01";
5565
0
      break;
5566
0
    }
5567
221
    if (MCInst_getNumOperands(MI) == 4 &&
5568
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5569
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5570
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5571
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5572
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5573
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5574
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5575
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5576
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5577
0
      AsmString = "movne $\x02, $\x03, $\x01";
5578
0
      break;
5579
0
    }
5580
221
    if (MCInst_getNumOperands(MI) == 4 &&
5581
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5582
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5583
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5584
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5585
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5586
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5587
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5588
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5589
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5590
0
      AsmString = "move $\x02, $\x03, $\x01";
5591
0
      break;
5592
0
    }
5593
221
    if (MCInst_getNumOperands(MI) == 4 &&
5594
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5595
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5596
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5597
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5598
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5599
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5600
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5601
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5602
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5603
0
      AsmString = "movue $\x02, $\x03, $\x01";
5604
0
      break;
5605
0
    }
5606
221
    if (MCInst_getNumOperands(MI) == 4 &&
5607
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5608
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5609
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5610
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5611
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5612
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5613
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5614
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5615
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5616
0
      AsmString = "movge $\x02, $\x03, $\x01";
5617
0
      break;
5618
0
    }
5619
221
    if (MCInst_getNumOperands(MI) == 4 &&
5620
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5621
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5622
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5623
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5624
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5625
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5626
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5627
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5628
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5629
0
      AsmString = "movuge $\x02, $\x03, $\x01";
5630
0
      break;
5631
0
    }
5632
221
    if (MCInst_getNumOperands(MI) == 4 &&
5633
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5634
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5635
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5636
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5637
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5638
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5639
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5640
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5641
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5642
0
      AsmString = "movle $\x02, $\x03, $\x01";
5643
0
      break;
5644
0
    }
5645
221
    if (MCInst_getNumOperands(MI) == 4 &&
5646
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5647
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5648
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5649
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5650
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5651
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5652
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5653
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5654
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5655
0
      AsmString = "movule $\x02, $\x03, $\x01";
5656
0
      break;
5657
0
    }
5658
221
    if (MCInst_getNumOperands(MI) == 4 &&
5659
0
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5660
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5661
0
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5662
0
        GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5663
0
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5664
0
        GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5665
0
        MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5666
0
        MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5667
      // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5668
0
      AsmString = "movo $\x02, $\x03, $\x01";
5669
0
      break;
5670
0
    }
5671
221
    return NULL;
5672
63.7k
  }
5673
5674
26.5k
  tmp = cs_strdup(AsmString);
5675
26.5k
  AsmMnem = tmp;
5676
171k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5677
171k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
5678
26.4k
      *AsmOps = '\0';
5679
26.4k
      AsmOps++;
5680
26.4k
      break;
5681
26.4k
    }
5682
171k
  }
5683
26.5k
  SStream_concat0(OS, AsmMnem);
5684
26.5k
  if (*AsmOps) {
5685
26.4k
    SStream_concat0(OS, "\t");
5686
26.4k
    if (strstr(AsmOps, "icc"))
5687
4.92k
      Sparc_addReg(MI, SPARC_REG_ICC);
5688
26.4k
    if (strstr(AsmOps, "xcc"))
5689
11.7k
      Sparc_addReg(MI, SPARC_REG_XCC);
5690
195k
    for (c = AsmOps; *c; c++) {
5691
169k
      if (*c == '$') {
5692
38.4k
        c += 1;
5693
38.4k
        if (*c == (char)0xff) {
5694
0
          c += 1;
5695
0
          OpIdx = *c - 1;
5696
0
          c += 1;
5697
0
          PrintMethodIdx = *c - 1;
5698
0
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5699
0
        } else
5700
38.4k
          printOperand(MI, *c - 1, OS);
5701
130k
      } else {
5702
130k
        SStream_concat(OS, "%c", *c);
5703
130k
      }
5704
169k
    }
5705
26.4k
  }
5706
26.5k
  return tmp;
5707
63.7k
}
5708
5709
#endif // PRINT_ALIAS_INSTR