/src/capstonenext/arch/TMS320C64x/TMS320C64xInstPrinter.c

Source
/* Capstone Disassembly Engine */
/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */

#ifdef CAPSTONE_HAS_TMS320C64X

#include <ctype.h>
#include <string.h>

#include "TMS320C64xInstPrinter.h"
#include "../../MCInst.h"
#include "../../utils.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "../../MathExtras.h"
#include "TMS320C64xMapping.h"

#include "capstone/tms320c64x.h"

static const char *getRegisterName(unsigned RegNo);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O);
static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O);

void TMS320C64x_post_printer(csh ud, cs_insn *insn, SStream *insn_asm,
           MCInst *mci)
{
  SStream ss;
  const char *op_str_ptr, *p2;
  char tmp[8] = { 0 };
  unsigned int unit = 0;
  int i;
  cs_tms320c64x *tms320c64x;

  if (mci->csh->detail_opt) {
    tms320c64x = &mci->flat_insn->detail->tms320c64x;

    for (i = 0; i < insn->detail->groups_count; i++) {
      switch (insn->detail->groups[i]) {
      case TMS320C64X_GRP_FUNIT_D:
        unit = TMS320C64X_FUNIT_D;
        break;
      case TMS320C64X_GRP_FUNIT_L:
        unit = TMS320C64X_FUNIT_L;
        break;
      case TMS320C64X_GRP_FUNIT_M:
        unit = TMS320C64X_FUNIT_M;
        break;
      case TMS320C64X_GRP_FUNIT_S:
        unit = TMS320C64X_FUNIT_S;
        break;
      case TMS320C64X_GRP_FUNIT_NO:
        unit = TMS320C64X_FUNIT_NO;
        break;
      }
      if (unit != 0)
        break;
    }
    tms320c64x->funit.unit = unit;

    SStream_Init(&ss);
    if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
      SStream_concat(
        &ss, "[%c%s]|",
        (tms320c64x->condition.zero == 1) ? '!' : '|',
        cs_reg_name(ud, tms320c64x->condition.reg));

    // Sorry for all the fixes below. I don't have time to add more helper SStream functions.
    // Before that they messed around with the private buffer of the stream.
    // So it is better now. But still not efficient.
    op_str_ptr = strchr(SStream_rbuf(insn_asm), '\t');

    if ((op_str_ptr != NULL) &&
        (((p2 = strchr(op_str_ptr, '[')) != NULL) ||
         ((p2 = strchr(op_str_ptr, '(')) != NULL))) {
      while ((p2 > op_str_ptr) &&
             ((*p2 != 'a') && (*p2 != 'b')))
        p2--;
      if (p2 == op_str_ptr) {
        SStream_Flush(insn_asm, NULL);
        SStream_concat0(insn_asm, "Invalid!");
        return;
      }
      if (*p2 == 'a')
        strncpy(tmp, "1T", sizeof(tmp));
      else
        strncpy(tmp, "2T", sizeof(tmp));
    } else {
      tmp[0] = '\0';
    }
    SStream mnem_post = { 0 };
    SStream_Init(&mnem_post);
    switch (tms320c64x->funit.unit) {
    case TMS320C64X_FUNIT_D:
      SStream_concat(&mnem_post, ".D%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_L:
      SStream_concat(&mnem_post, ".L%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_M:
      SStream_concat(&mnem_post, ".M%s%u", tmp,
               tms320c64x->funit.side);
      break;
    case TMS320C64X_FUNIT_S:
      SStream_concat(&mnem_post, ".S%s%u", tmp,
               tms320c64x->funit.side);
      break;
    }
    if (tms320c64x->funit.crosspath > 0)
      SStream_concat0(&mnem_post, "X");

    if (op_str_ptr != NULL) {
      // There is an op_str
      SStream_concat1(&mnem_post, '\t');
      SStream_replc_str(insn_asm, '\t',
            SStream_rbuf(&mnem_post));
    }

    if (tms320c64x->parallel != 0)
      SStream_concat0(insn_asm, "\t||");
    SStream_concat0(&ss, SStream_rbuf(insn_asm));
    SStream_Flush(insn_asm, NULL);
    SStream_concat0(insn_asm, SStream_rbuf(&ss));
  }
}

#define PRINT_ALIAS_INSTR
#include "TMS320C64xGenAsmWriter.inc"

#define GET_INSTRINFO_ENUM
#include "TMS320C64xGenInstrInfo.inc"

static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg;

  if (MCOperand_isReg(Op)) {
    reg = MCOperand_getReg(Op);
    if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) &&
        (OpNo == 1)) {
      switch (reg) {
      case TMS320C64X_REG_EFR:
        SStream_concat0(O, "EFR");
        break;
      case TMS320C64X_REG_IFR:
        SStream_concat0(O, "IFR");
        break;
      default:
        SStream_concat0(O, getRegisterName(reg));
        break;
      }
    } else {
      SStream_concat0(O, getRegisterName(reg));
    }

    if (MI->csh->detail_opt) {
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .type = TMS320C64X_OP_REG;
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .reg = reg;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  } else if (MCOperand_isImm(Op)) {
    int64_t Imm = MCOperand_getImm(Op);

    if (Imm >= 0) {
      if (Imm > HEX_THRESHOLD)
        SStream_concat(O, "0x%" PRIx64, Imm);
      else
        SStream_concat(O, "%" PRIu64, Imm);
    } else {
      if (Imm < -HEX_THRESHOLD)
        SStream_concat(O, "-0x%" PRIx64, -Imm);
      else
        SStream_concat(O, "-%" PRIu64, -Imm);
    }

    if (MI->csh->detail_opt) {
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .type = TMS320C64X_OP_IMM;
      MI->flat_insn->detail->tms320c64x
        .operands[MI->flat_insn->detail->tms320c64x
              .op_count]
        .imm = Imm;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  }
}

static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  unsigned scaled, base, offset, mode, unit;
  cs_tms320c64x *tms320c64x;
  char st, nd;

  scaled = (Val >> 19) & 1;
  base = (Val >> 12) & 0x7f;
  offset = (Val >> 5) & 0x7f;
  mode = (Val >> 1) & 0xf;
  unit = Val & 1;

  if (scaled) {
    st = '[';
    nd = ']';
  } else {
    st = '(';
    nd = ')';
  }

  switch (mode) {
  case 0:
    SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 1:
    SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 4:
    SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 5:
    SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 8:
    SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 9:
    SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 10:
    SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 11:
    SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st,
             offset, nd);
    break;
  case 12:
    SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 13:
    SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 14:
    SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  case 15:
    SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st,
             getRegisterName(offset), nd);
    break;
  }

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = base;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
    tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
    switch (mode) {
    case 0:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 1:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 4:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 5:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_NO;
      break;
    case 8:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 9:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 10:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 11:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_CONSTANT;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 12:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 13:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_PRE;
      break;
    case 14:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_BW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    case 15:
      tms320c64x->operands[tms320c64x->op_count].mem.disptype =
        TMS320C64X_MEM_DISP_REGISTER;
      tms320c64x->operands[tms320c64x->op_count]
        .mem.direction = TMS320C64X_MEM_DIR_FW;
      tms320c64x->operands[tms320c64x->op_count].mem.modify =
        TMS320C64X_MEM_MOD_POST;
      break;
    }
    tms320c64x->op_count++;
  }
}

static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  uint16_t offset;
  unsigned basereg;
  cs_tms320c64x *tms320c64x;

  basereg = Val & 0x7f;
  offset = (Val >> 7) & 0x7fff;
  SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.disptype =
      TMS320C64X_MEM_DISP_CONSTANT;
    tms320c64x->operands[tms320c64x->op_count].mem.direction =
      TMS320C64X_MEM_DIR_FW;
    tms320c64x->operands[tms320c64x->op_count].mem.modify =
      TMS320C64X_MEM_MOD_NO;
    tms320c64x->op_count++;
  }
}

static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg = MCOperand_getReg(Op);
  cs_tms320c64x *tms320c64x;

  SStream_concat(O, "%s:%s", getRegisterName(reg + 1),
           getRegisterName(reg));

  if (MI->csh->detail_opt) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type =
      TMS320C64X_OP_REGPAIR;
    tms320c64x->operands[tms320c64x->op_count].reg = reg;
    tms320c64x->op_count++;
  }
}

static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
{
  unsigned opcode = MCInst_getOpcode(MI);
  MCOperand *op;

  switch (opcode) {
  /* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
  case TMS320C64x_ADD_d2_rir:
  /* ADD.L -i, x, y -> SUB.L x, i, y */
  case TMS320C64x_ADD_l1_irr:
  case TMS320C64x_ADD_l1_ipp:
  /* ADD.S -i, x, y -> SUB.S x, i, y */
  case TMS320C64x_ADD_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
      op = MCInst_getOperand(MI, 2);
      MCOperand_setImm(op, -MCOperand_getImm(op));

      SStream_concat0(O, "SUB\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 2, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* ADD.D 0, x, y -> MV.D x, y */
  case TMS320C64x_ADD_d1_rir:
  /* OR.D x, 0, y -> MV.D x, y */
  case TMS320C64x_OR_d2_rir:
  /* ADD.L 0, x, y -> MV.L x, y */
  case TMS320C64x_ADD_l1_irr:
  case TMS320C64x_ADD_l1_ipp:
  /* OR.L 0, x, y -> MV.L x, y */
  case TMS320C64x_OR_l1_irr:
  /* ADD.S 0, x, y -> MV.S x, y */
  case TMS320C64x_ADD_s1_irr:
  /* OR.S 0, x, y -> MV.S x, y */
  case TMS320C64x_OR_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
      MI->size--;

      SStream_concat0(O, "MV\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* XOR.D -1, x, y -> NOT.D x, y */
  case TMS320C64x_XOR_d2_rir:
  /* XOR.L -1, x, y -> NOT.L x, y */
  case TMS320C64x_XOR_l1_irr:
  /* XOR.S -1, x, y -> NOT.S x, y */
  case TMS320C64x_XOR_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
      MI->size--;

      SStream_concat0(O, "NOT\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* MVK.D 0, x -> ZERO.D x */
  case TMS320C64x_MVK_d1_rr:
  /* MVK.L 0, x -> ZERO.L x */
  case TMS320C64x_MVK_l2_ir:
    if ((MCInst_getNumOperands(MI) == 2) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
      MI->size--;

      SStream_concat0(O, "ZERO\t");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* SUB.L x, x, y -> ZERO.L y */
  case TMS320C64x_SUB_l1_rrp_x1:
  /* SUB.S x, x, y -> ZERO.S y */
  case TMS320C64x_SUB_s1_rrr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
         MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
      MI->size -= 2;

      SStream_concat0(O, "ZERO\t");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* SUB.L 0, x, y -> NEG.L x, y */
  case TMS320C64x_SUB_l1_irr:
  case TMS320C64x_SUB_l1_ipp:
  /* SUB.S 0, x, y -> NEG.S x, y */
  case TMS320C64x_SUB_s1_irr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
      MI->size--;

      SStream_concat0(O, "NEG\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* PACKLH2.L x, x, y -> SWAP2.L x, y */
  case TMS320C64x_PACKLH2_l1_rrr_x2:
  /* PACKLH2.S x, x, y -> SWAP2.S x, y */
  case TMS320C64x_PACKLH2_s1_rrr:
    if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
         MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
      MI->size--;

      SStream_concat0(O, "SWAP2\t");
      printOperand(MI, 1, O);
      SStream_concat0(O, ", ");
      printOperand(MI, 0, O);

      return true;
    }
    break;
  }
  switch (opcode) {
  /* NOP 16 -> IDLE */
  /* NOP 1 -> NOP */
  case TMS320C64x_NOP_n:
    if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
      MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
      MI->size--;

      SStream_concat0(O, "IDLE");

      return true;
    }
    if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
      MI->size--;

      SStream_concat0(O, "NOP");

      return true;
    }
    break;
  }

  return false;
}

void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info)
{
  if (!printAliasInstruction(MI, O, Info))
    printInstruction(MI, O, Info);
}

#endif

Coverage Report

Created: 2026-11-12 06:22

Line	Count	Source
1		/* Capstone Disassembly Engine */
2		/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
3
4		#ifdef CAPSTONE_HAS_TMS320C64X
5
6		#include <ctype.h>
7		#include <string.h>
8
9		#include "TMS320C64xInstPrinter.h"
10		#include "../../MCInst.h"
11		#include "../../utils.h"
12		#include "../../SStream.h"
13		#include "../../MCRegisterInfo.h"
14		#include "../../MathExtras.h"
15		#include "TMS320C64xMapping.h"
16
17		#include "capstone/tms320c64x.h"
18
19		static const char *getRegisterName(unsigned RegNo);
20		static void printOperand(MCInst MI, unsigned OpNo, SStream O);
21		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O);
22		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O);
23		static void printRegPair(MCInst MI, unsigned OpNo, SStream O);
24
25		void TMS320C64x_post_printer(csh ud, cs_insn insn, SStream insn_asm,
26		MCInst *mci)
27	45.6k	{
28	45.6k	SStream ss;
29	45.6k	const char op_str_ptr, p2;
30	45.6k	char tmp[8] = { 0 };
31	45.6k	unsigned int unit = 0;
32	45.6k	int i;
33	45.6k	cs_tms320c64x *tms320c64x;
34
35	45.6k	if (mci->csh->detail_opt) {
36	45.6k	tms320c64x = &mci->flat_insn->detail->tms320c64x;
37
38	45.6k	for (i = 0; i < insn->detail->groups_count; i++) {
39	45.6k	switch (insn->detail->groups[i]) {
40	11.1k	case TMS320C64X_GRP_FUNIT_D:
41	11.1k	unit = TMS320C64X_FUNIT_D;
42	11.1k	break;
43	11.3k	case TMS320C64X_GRP_FUNIT_L:
44	11.3k	unit = TMS320C64X_FUNIT_L;
45	11.3k	break;
46	2.25k	case TMS320C64X_GRP_FUNIT_M:
47	2.25k	unit = TMS320C64X_FUNIT_M;
48	2.25k	break;
49	19.4k	case TMS320C64X_GRP_FUNIT_S:
50	19.4k	unit = TMS320C64X_FUNIT_S;
51	19.4k	break;
52	1.58k	case TMS320C64X_GRP_FUNIT_NO:
53	1.58k	unit = TMS320C64X_FUNIT_NO;
54	1.58k	break;
55	45.6k	}
56	45.6k	if (unit != 0)
57	45.6k	break;
58	45.6k	}
59	45.6k	tms320c64x->funit.unit = unit;
60
61	45.6k	SStream_Init(&ss);
62	45.6k	if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
63	26.6k	SStream_concat(
64	26.6k	&ss, "[%c%s]\|",
65	26.6k	(tms320c64x->condition.zero == 1) ? '!' : '\|',
66	26.6k	cs_reg_name(ud, tms320c64x->condition.reg));
67
68		// Sorry for all the fixes below. I don't have time to add more helper SStream functions.
69		// Before that they messed around with the private buffer of the stream.
70		// So it is better now. But still not efficient.
71	45.6k	op_str_ptr = strchr(SStream_rbuf(insn_asm), '\t');
72
73	45.6k	if ((op_str_ptr != NULL) &&
74	44.4k	(((p2 = strchr(op_str_ptr, '[')) != NULL) \|\|
75	36.9k	((p2 = strchr(op_str_ptr, '(')) != NULL))) {
76	32.5k	while ((p2 > op_str_ptr) &&
77	32.5k	((p2 != 'a') && (p2 != 'b')))
78	24.7k	p2--;
79	7.87k	if (p2 == op_str_ptr) {
80	0	SStream_Flush(insn_asm, NULL);
81	0	SStream_concat0(insn_asm, "Invalid!");
82	0	return;
83	0	}
84	7.87k	if (*p2 == 'a')
85	4.38k	strncpy(tmp, "1T", sizeof(tmp));
86	3.49k	else
87	3.49k	strncpy(tmp, "2T", sizeof(tmp));
88	37.8k	} else {
89	37.8k	tmp[0] = '\0';
90	37.8k	}
91	45.6k	SStream mnem_post = { 0 };
92	45.6k	SStream_Init(&mnem_post);
93	45.6k	switch (tms320c64x->funit.unit) {
94	11.1k	case TMS320C64X_FUNIT_D:
95	11.1k	SStream_concat(&mnem_post, ".D%s%u", tmp,
96	11.1k	tms320c64x->funit.side);
97	11.1k	break;
98	11.3k	case TMS320C64X_FUNIT_L:
99	11.3k	SStream_concat(&mnem_post, ".L%s%u", tmp,
100	11.3k	tms320c64x->funit.side);
101	11.3k	break;
102	2.25k	case TMS320C64X_FUNIT_M:
103	2.25k	SStream_concat(&mnem_post, ".M%s%u", tmp,
104	2.25k	tms320c64x->funit.side);
105	2.25k	break;
106	19.4k	case TMS320C64X_FUNIT_S:
107	19.4k	SStream_concat(&mnem_post, ".S%s%u", tmp,
108	19.4k	tms320c64x->funit.side);
109	19.4k	break;
110	45.6k	}
111	45.6k	if (tms320c64x->funit.crosspath > 0)
112	14.1k	SStream_concat0(&mnem_post, "X");
113
114	45.6k	if (op_str_ptr != NULL) {
115		// There is an op_str
116	44.4k	SStream_concat1(&mnem_post, '\t');
117	44.4k	SStream_replc_str(insn_asm, '\t',
118	44.4k	SStream_rbuf(&mnem_post));
119	44.4k	}
120
121	45.6k	if (tms320c64x->parallel != 0)
122	21.7k	SStream_concat0(insn_asm, "\t\|\|");
123	45.6k	SStream_concat0(&ss, SStream_rbuf(insn_asm));
124	45.6k	SStream_Flush(insn_asm, NULL);
125	45.6k	SStream_concat0(insn_asm, SStream_rbuf(&ss));
126	45.6k	}
127	45.6k	}
128
129		#define PRINT_ALIAS_INSTR
130		#include "TMS320C64xGenAsmWriter.inc"
131
132		#define GET_INSTRINFO_ENUM
133		#include "TMS320C64xGenInstrInfo.inc"
134
135		static void printOperand(MCInst MI, unsigned OpNo, SStream O)
136	82.3k	{
137	82.3k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
138	82.3k	unsigned reg;
139
140	82.3k	if (MCOperand_isReg(Op)) {
141	59.7k	reg = MCOperand_getReg(Op);
142	59.7k	if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) &&
143	2.77k	(OpNo == 1)) {
144	1.38k	switch (reg) {
145	422	case TMS320C64X_REG_EFR:
146	422	SStream_concat0(O, "EFR");
147	422	break;
148	325	case TMS320C64X_REG_IFR:
149	325	SStream_concat0(O, "IFR");
150	325	break;
151	642	default:
152	642	SStream_concat0(O, getRegisterName(reg));
153	642	break;
154	1.38k	}
155	58.4k	} else {
156	58.4k	SStream_concat0(O, getRegisterName(reg));
157	58.4k	}
158
159	59.7k	if (MI->csh->detail_opt) {
160	59.7k	MI->flat_insn->detail->tms320c64x
161	59.7k	.operands[MI->flat_insn->detail->tms320c64x
162	59.7k	.op_count]
163	59.7k	.type = TMS320C64X_OP_REG;
164	59.7k	MI->flat_insn->detail->tms320c64x
165	59.7k	.operands[MI->flat_insn->detail->tms320c64x
166	59.7k	.op_count]
167	59.7k	.reg = reg;
168	59.7k	MI->flat_insn->detail->tms320c64x.op_count++;
169	59.7k	}
170	59.7k	} else if (MCOperand_isImm(Op)) {
171	22.5k	int64_t Imm = MCOperand_getImm(Op);
172
173	22.5k	if (Imm >= 0) {
174	17.3k	if (Imm > HEX_THRESHOLD)
175	9.29k	SStream_concat(O, "0x%" PRIx64, Imm);
176	8.05k	else
177	8.05k	SStream_concat(O, "%" PRIu64, Imm);
178	17.3k	} else {
179	5.24k	if (Imm < -HEX_THRESHOLD)
180	3.30k	SStream_concat(O, "-0x%" PRIx64, -Imm);
181	1.93k	else
182	1.93k	SStream_concat(O, "-%" PRIu64, -Imm);
183	5.24k	}
184
185	22.5k	if (MI->csh->detail_opt) {
186	22.5k	MI->flat_insn->detail->tms320c64x
187	22.5k	.operands[MI->flat_insn->detail->tms320c64x
188	22.5k	.op_count]
189	22.5k	.type = TMS320C64X_OP_IMM;
190	22.5k	MI->flat_insn->detail->tms320c64x
191	22.5k	.operands[MI->flat_insn->detail->tms320c64x
192	22.5k	.op_count]
193	22.5k	.imm = Imm;
194	22.5k	MI->flat_insn->detail->tms320c64x.op_count++;
195	22.5k	}
196	22.5k	}
197	82.3k	}
198
199		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O)
200	4.38k	{
201	4.38k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
202	4.38k	int64_t Val = MCOperand_getImm(Op);
203	4.38k	unsigned scaled, base, offset, mode, unit;
204	4.38k	cs_tms320c64x *tms320c64x;
205	4.38k	char st, nd;
206
207	4.38k	scaled = (Val >> 19) & 1;
208	4.38k	base = (Val >> 12) & 0x7f;
209	4.38k	offset = (Val >> 5) & 0x7f;
210	4.38k	mode = (Val >> 1) & 0xf;
211	4.38k	unit = Val & 1;
212
213	4.38k	if (scaled) {
214	4.00k	st = '[';
215	4.00k	nd = ']';
216	4.00k	} else {
217	376	st = '(';
218	376	nd = ')';
219	376	}
220
221	4.38k	switch (mode) {
222	473	case 0:
223	473	SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st,
224	473	offset, nd);
225	473	break;
226	308	case 1:
227	308	SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st,
228	308	offset, nd);
229	308	break;
230	300	case 4:
231	300	SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st,
232	300	getRegisterName(offset), nd);
233	300	break;
234	286	case 5:
235	286	SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st,
236	286	getRegisterName(offset), nd);
237	286	break;
238	461	case 8:
239	461	SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st,
240	461	offset, nd);
241	461	break;
242	241	case 9:
243	241	SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st,
244	241	offset, nd);
245	241	break;
246	474	case 10:
247	474	SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st,
248	474	offset, nd);
249	474	break;
250	564	case 11:
251	564	SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st,
252	564	offset, nd);
253	564	break;
254	470	case 12:
255	470	SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st,
256	470	getRegisterName(offset), nd);
257	470	break;
258	344	case 13:
259	344	SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st,
260	344	getRegisterName(offset), nd);
261	344	break;
262	233	case 14:
263	233	SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st,
264	233	getRegisterName(offset), nd);
265	233	break;
266	228	case 15:
267	228	SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st,
268	228	getRegisterName(offset), nd);
269	228	break;
270	4.38k	}
271
272	4.38k	if (MI->csh->detail_opt) {
273	4.38k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
274
275	4.38k	tms320c64x->operands[tms320c64x->op_count].type =
276	4.38k	TMS320C64X_OP_MEM;
277	4.38k	tms320c64x->operands[tms320c64x->op_count].mem.base = base;
278	4.38k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
279	4.38k	tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
280	4.38k	tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
281	4.38k	switch (mode) {
282	473	case 0:
283	473	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
284	473	TMS320C64X_MEM_DISP_CONSTANT;
285	473	tms320c64x->operands[tms320c64x->op_count]
286	473	.mem.direction = TMS320C64X_MEM_DIR_BW;
287	473	tms320c64x->operands[tms320c64x->op_count].mem.modify =
288	473	TMS320C64X_MEM_MOD_NO;
289	473	break;
290	308	case 1:
291	308	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
292	308	TMS320C64X_MEM_DISP_CONSTANT;
293	308	tms320c64x->operands[tms320c64x->op_count]
294	308	.mem.direction = TMS320C64X_MEM_DIR_FW;
295	308	tms320c64x->operands[tms320c64x->op_count].mem.modify =
296	308	TMS320C64X_MEM_MOD_NO;
297	308	break;
298	300	case 4:
299	300	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
300	300	TMS320C64X_MEM_DISP_REGISTER;
301	300	tms320c64x->operands[tms320c64x->op_count]
302	300	.mem.direction = TMS320C64X_MEM_DIR_BW;
303	300	tms320c64x->operands[tms320c64x->op_count].mem.modify =
304	300	TMS320C64X_MEM_MOD_NO;
305	300	break;
306	286	case 5:
307	286	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
308	286	TMS320C64X_MEM_DISP_REGISTER;
309	286	tms320c64x->operands[tms320c64x->op_count]
310	286	.mem.direction = TMS320C64X_MEM_DIR_FW;
311	286	tms320c64x->operands[tms320c64x->op_count].mem.modify =
312	286	TMS320C64X_MEM_MOD_NO;
313	286	break;
314	461	case 8:
315	461	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
316	461	TMS320C64X_MEM_DISP_CONSTANT;
317	461	tms320c64x->operands[tms320c64x->op_count]
318	461	.mem.direction = TMS320C64X_MEM_DIR_BW;
319	461	tms320c64x->operands[tms320c64x->op_count].mem.modify =
320	461	TMS320C64X_MEM_MOD_PRE;
321	461	break;
322	241	case 9:
323	241	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
324	241	TMS320C64X_MEM_DISP_CONSTANT;
325	241	tms320c64x->operands[tms320c64x->op_count]
326	241	.mem.direction = TMS320C64X_MEM_DIR_FW;
327	241	tms320c64x->operands[tms320c64x->op_count].mem.modify =
328	241	TMS320C64X_MEM_MOD_PRE;
329	241	break;
330	474	case 10:
331	474	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
332	474	TMS320C64X_MEM_DISP_CONSTANT;
333	474	tms320c64x->operands[tms320c64x->op_count]
334	474	.mem.direction = TMS320C64X_MEM_DIR_BW;
335	474	tms320c64x->operands[tms320c64x->op_count].mem.modify =
336	474	TMS320C64X_MEM_MOD_POST;
337	474	break;
338	564	case 11:
339	564	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
340	564	TMS320C64X_MEM_DISP_CONSTANT;
341	564	tms320c64x->operands[tms320c64x->op_count]
342	564	.mem.direction = TMS320C64X_MEM_DIR_FW;
343	564	tms320c64x->operands[tms320c64x->op_count].mem.modify =
344	564	TMS320C64X_MEM_MOD_POST;
345	564	break;
346	470	case 12:
347	470	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
348	470	TMS320C64X_MEM_DISP_REGISTER;
349	470	tms320c64x->operands[tms320c64x->op_count]
350	470	.mem.direction = TMS320C64X_MEM_DIR_BW;
351	470	tms320c64x->operands[tms320c64x->op_count].mem.modify =
352	470	TMS320C64X_MEM_MOD_PRE;
353	470	break;
354	344	case 13:
355	344	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
356	344	TMS320C64X_MEM_DISP_REGISTER;
357	344	tms320c64x->operands[tms320c64x->op_count]
358	344	.mem.direction = TMS320C64X_MEM_DIR_FW;
359	344	tms320c64x->operands[tms320c64x->op_count].mem.modify =
360	344	TMS320C64X_MEM_MOD_PRE;
361	344	break;
362	233	case 14:
363	233	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
364	233	TMS320C64X_MEM_DISP_REGISTER;
365	233	tms320c64x->operands[tms320c64x->op_count]
366	233	.mem.direction = TMS320C64X_MEM_DIR_BW;
367	233	tms320c64x->operands[tms320c64x->op_count].mem.modify =
368	233	TMS320C64X_MEM_MOD_POST;
369	233	break;
370	228	case 15:
371	228	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
372	228	TMS320C64X_MEM_DISP_REGISTER;
373	228	tms320c64x->operands[tms320c64x->op_count]
374	228	.mem.direction = TMS320C64X_MEM_DIR_FW;
375	228	tms320c64x->operands[tms320c64x->op_count].mem.modify =
376	228	TMS320C64X_MEM_MOD_POST;
377	228	break;
378	4.38k	}
379	4.38k	tms320c64x->op_count++;
380	4.38k	}
381	4.38k	}
382
383		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O)
384	3.49k	{
385	3.49k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
386	3.49k	int64_t Val = MCOperand_getImm(Op);
387	3.49k	uint16_t offset;
388	3.49k	unsigned basereg;
389	3.49k	cs_tms320c64x *tms320c64x;
390
391	3.49k	basereg = Val & 0x7f;
392	3.49k	offset = (Val >> 7) & 0x7fff;
393	3.49k	SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);
394
395	3.49k	if (MI->csh->detail_opt) {
396	3.49k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
397
398	3.49k	tms320c64x->operands[tms320c64x->op_count].type =
399	3.49k	TMS320C64X_OP_MEM;
400	3.49k	tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
401	3.49k	tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
402	3.49k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
403	3.49k	tms320c64x->operands[tms320c64x->op_count].mem.disptype =
404	3.49k	TMS320C64X_MEM_DISP_CONSTANT;
405	3.49k	tms320c64x->operands[tms320c64x->op_count].mem.direction =
406	3.49k	TMS320C64X_MEM_DIR_FW;
407	3.49k	tms320c64x->operands[tms320c64x->op_count].mem.modify =
408	3.49k	TMS320C64X_MEM_MOD_NO;
409	3.49k	tms320c64x->op_count++;
410	3.49k	}
411	3.49k	}
412
413		static void printRegPair(MCInst MI, unsigned OpNo, SStream O)
414	14.1k	{
415	14.1k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
416	14.1k	unsigned reg = MCOperand_getReg(Op);
417	14.1k	cs_tms320c64x *tms320c64x;
418
419	14.1k	SStream_concat(O, "%s:%s", getRegisterName(reg + 1),
420	14.1k	getRegisterName(reg));
421
422	14.1k	if (MI->csh->detail_opt) {
423	14.1k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
424
425	14.1k	tms320c64x->operands[tms320c64x->op_count].type =
426	14.1k	TMS320C64X_OP_REGPAIR;
427	14.1k	tms320c64x->operands[tms320c64x->op_count].reg = reg;
428	14.1k	tms320c64x->op_count++;
429	14.1k	}
430	14.1k	}
431
432		static bool printAliasInstruction(MCInst MI, SStream O, MCRegisterInfo *MRI)
433	45.6k	{
434	45.6k	unsigned opcode = MCInst_getOpcode(MI);
435	45.6k	MCOperand *op;
436
437	45.6k	switch (opcode) {
438		/* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
439	208	case TMS320C64x_ADD_d2_rir:
440		/* ADD.L -i, x, y -> SUB.L x, i, y */
441	455	case TMS320C64x_ADD_l1_irr:
442	1.09k	case TMS320C64x_ADD_l1_ipp:
443		/* ADD.S -i, x, y -> SUB.S x, i, y */
444	1.32k	case TMS320C64x_ADD_s1_irr:
445	1.32k	if ((MCInst_getNumOperands(MI) == 3) &&
446	1.32k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
447	1.32k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
448	1.32k	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
449	1.32k	(MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
450	313	MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
451	313	op = MCInst_getOperand(MI, 2);
452	313	MCOperand_setImm(op, -MCOperand_getImm(op));
453
454	313	SStream_concat0(O, "SUB\t");
455	313	printOperand(MI, 1, O);
456	313	SStream_concat0(O, ", ");
457	313	printOperand(MI, 2, O);
458	313	SStream_concat0(O, ", ");
459	313	printOperand(MI, 0, O);
460
461	313	return true;
462	313	}
463	1.01k	break;
464	45.6k	}
465	45.3k	switch (opcode) {
466		/* ADD.D 0, x, y -> MV.D x, y */
467	273	case TMS320C64x_ADD_d1_rir:
468		/* OR.D x, 0, y -> MV.D x, y */
469	533	case TMS320C64x_OR_d2_rir:
470		/* ADD.L 0, x, y -> MV.L x, y */
471	759	case TMS320C64x_ADD_l1_irr:
472	1.11k	case TMS320C64x_ADD_l1_ipp:
473		/* OR.L 0, x, y -> MV.L x, y */
474	1.32k	case TMS320C64x_OR_l1_irr:
475		/* ADD.S 0, x, y -> MV.S x, y */
476	1.54k	case TMS320C64x_ADD_s1_irr:
477		/* OR.S 0, x, y -> MV.S x, y */
478	1.74k	case TMS320C64x_OR_s1_irr:
479	1.74k	if ((MCInst_getNumOperands(MI) == 3) &&
480	1.74k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
481	1.74k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
482	1.74k	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
483	1.74k	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
484	451	MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
485	451	MI->size--;
486
487	451	SStream_concat0(O, "MV\t");
488	451	printOperand(MI, 1, O);
489	451	SStream_concat0(O, ", ");
490	451	printOperand(MI, 0, O);
491
492	451	return true;
493	451	}
494	1.29k	break;
495	45.3k	}
496	44.9k	switch (opcode) {
497		/* XOR.D -1, x, y -> NOT.D x, y */
498	338	case TMS320C64x_XOR_d2_rir:
499		/* XOR.L -1, x, y -> NOT.L x, y */
500	605	case TMS320C64x_XOR_l1_irr:
501		/* XOR.S -1, x, y -> NOT.S x, y */
502	842	case TMS320C64x_XOR_s1_irr:
503	842	if ((MCInst_getNumOperands(MI) == 3) &&
504	842	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
505	842	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
506	842	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
507	842	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
508	313	MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
509	313	MI->size--;
510
511	313	SStream_concat0(O, "NOT\t");
512	313	printOperand(MI, 1, O);
513	313	SStream_concat0(O, ", ");
514	313	printOperand(MI, 0, O);
515
516	313	return true;
517	313	}
518	529	break;
519	44.9k	}
520	44.6k	switch (opcode) {
521		/* MVK.D 0, x -> ZERO.D x */
522	689	case TMS320C64x_MVK_d1_rr:
523		/* MVK.L 0, x -> ZERO.L x */
524	2.18k	case TMS320C64x_MVK_l2_ir:
525	2.18k	if ((MCInst_getNumOperands(MI) == 2) &&
526	2.18k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
527	2.18k	MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
528	2.18k	(MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
529	1.12k	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
530	1.12k	MI->size--;
531
532	1.12k	SStream_concat0(O, "ZERO\t");
533	1.12k	printOperand(MI, 0, O);
534
535	1.12k	return true;
536	1.12k	}
537	1.05k	break;
538	44.6k	}
539	43.4k	switch (opcode) {
540		/* SUB.L x, x, y -> ZERO.L y */
541	78	case TMS320C64x_SUB_l1_rrp_x1:
542		/* SUB.S x, x, y -> ZERO.S y */
543	791	case TMS320C64x_SUB_s1_rrr:
544	791	if ((MCInst_getNumOperands(MI) == 3) &&
545	791	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
546	791	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
547	791	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
548	791	(MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
549	791	MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
550	395	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
551	395	MI->size -= 2;
552
553	395	SStream_concat0(O, "ZERO\t");
554	395	printOperand(MI, 0, O);
555
556	395	return true;
557	395	}
558	396	break;
559	43.4k	}
560	43.0k	switch (opcode) {
561		/* SUB.L 0, x, y -> NEG.L x, y */
562	274	case TMS320C64x_SUB_l1_irr:
563	513	case TMS320C64x_SUB_l1_ipp:
564		/* SUB.S 0, x, y -> NEG.S x, y */
565	584	case TMS320C64x_SUB_s1_irr:
566	584	if ((MCInst_getNumOperands(MI) == 3) &&
567	584	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
568	584	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
569	584	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
570	584	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
571	82	MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
572	82	MI->size--;
573
574	82	SStream_concat0(O, "NEG\t");
575	82	printOperand(MI, 1, O);
576	82	SStream_concat0(O, ", ");
577	82	printOperand(MI, 0, O);
578
579	82	return true;
580	82	}
581	502	break;
582	43.0k	}
583	43.0k	switch (opcode) {
584		/* PACKLH2.L x, x, y -> SWAP2.L x, y */
585	407	case TMS320C64x_PACKLH2_l1_rrr_x2:
586		/* PACKLH2.S x, x, y -> SWAP2.S x, y */
587	617	case TMS320C64x_PACKLH2_s1_rrr:
588	617	if ((MCInst_getNumOperands(MI) == 3) &&
589	617	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
590	617	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
591	617	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
592	617	(MCOperand_getReg(MCInst_getOperand(MI, 1)) ==
593	617	MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
594	197	MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
595	197	MI->size--;
596
597	197	SStream_concat0(O, "SWAP2\t");
598	197	printOperand(MI, 1, O);
599	197	SStream_concat0(O, ", ");
600	197	printOperand(MI, 0, O);
601
602	197	return true;
603	197	}
604	420	break;
605	43.0k	}
606	42.8k	switch (opcode) {
607		/* NOP 16 -> IDLE */
608		/* NOP 1 -> NOP */
609	1.58k	case TMS320C64x_NOP_n:
610	1.58k	if ((MCInst_getNumOperands(MI) == 1) &&
611	1.58k	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
612	1.58k	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
613	156	MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
614	156	MI->size--;
615
616	156	SStream_concat0(O, "IDLE");
617
618	156	return true;
619	156	}
620	1.42k	if ((MCInst_getNumOperands(MI) == 1) &&
621	1.42k	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
622	1.42k	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
623	1.09k	MI->size--;
624
625	1.09k	SStream_concat0(O, "NOP");
626
627	1.09k	return true;
628	1.09k	}
629	334	break;
630	42.8k	}
631
632	41.5k	return false;
633	42.8k	}
634
635		void TMS320C64x_printInst(MCInst MI, SStream O, void *Info)
636	45.6k	{
637	45.6k	if (!printAliasInstruction(MI, O, Info))
638	41.5k	printInstruction(MI, O, Info);
639	45.6k	}
640
641		#endif