Coverage Report

Created: 2023-09-25 06:24

/src/capstonenext/arch/ARM/ARMDisassembler.c
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Source (jump to first uncovered line)
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/*    Rot127 <unisono@quyllur.org> 2022-2023 */
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/* Automatically translated source file from LLVM. */
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/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
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/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
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/* Only small edits allowed. */
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/* For multiple similiar edits, please create a Patch for the translator. */
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/* Capstone's C++ file translator: */
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/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include <capstone/platform.h>
24
#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "../../LEB128.h"
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#include "../../MCDisassembler.h"
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#include "../../MCFixedLenDisassembler.h"
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#include "../../MCInst.h"
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#include "../../MCInstrDesc.h"
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#include "../../MCRegisterInfo.h"
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#include "../../MathExtras.h"
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#include "../../cs_priv.h"
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#include "../../utils.h"
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#include "ARMLinkage.h"
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#include "ARMAddressingModes.h"
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#include "ARMBaseInfo.h"
40
#include "ARMDisassemblerExtension.h"
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#include "ARMMapping.h"
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#define GET_INSTRINFO_MC_DESC
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#include "ARMGenInstrInfo.inc"
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16.6k
#define CONCAT(a, b) CONCAT_(a, b)
47
16.6k
#define CONCAT_(a, b) a##_##b
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#define DEBUG_TYPE "arm-disassembler"
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// Handles the condition code status of instructions in IT blocks
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;
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;
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/// ARM disassembler for all ARM platforms.;
57
static DecodeStatus getInstruction(csh ud, const uint8_t *Bytes, size_t ByteLen,
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           MCInst *MI, uint16_t *Size, uint64_t Address,
59
           void *Info);
60
DecodeStatus getARMInstruction(csh ud, const uint8_t *Bytes, size_t ByteLen,
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             MCInst *MI, uint16_t *Size, uint64_t Address,
62
             void *Info);
63
DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t ByteLen,
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         MCInst *MI, uint16_t *Size, uint64_t Address,
65
         void *Info);
66
DecodeStatus AddThumbPredicate(MCInst *);
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void UpdateThumbVFPPredicate(DecodeStatus, MCInst *);
68
;
69
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// end anonymous namespace
71
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// Forward declare these because the autogenerated code will reference them.
73
// Definitions are further down.
74
static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo,
75
             uint64_t Address,
76
             const void *Decoder);
77
static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst *Inst, unsigned RegNo,
78
                 uint64_t Address,
79
                 const void *Decoder);
80
static DecodeStatus DecodetGPROddRegisterClass(MCInst *Inst, unsigned RegNo,
81
                 uint64_t Address,
82
                 const void *Decoder);
83
static DecodeStatus DecodetGPREvenRegisterClass(MCInst *Inst, unsigned RegNo,
84
            uint64_t Address,
85
            const void *Decoder);
86
static DecodeStatus
87
DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst *Inst, unsigned RegNo,
88
          uint64_t Address, const void *Decoder);
89
static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo,
90
                 uint64_t Address,
91
                 const void *Decoder);
92
static DecodeStatus DecodeGPRnospRegisterClass(MCInst *Inst, unsigned RegNo,
93
                 uint64_t Address,
94
                 const void *Decoder);
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static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo,
96
               uint64_t Address,
97
               const void *Decoder);
98
static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst *Inst, unsigned RegNo,
99
             uint64_t Address,
100
             const void *Decoder);
101
static DecodeStatus DecodeGPRwithZRnospRegisterClass(MCInst *Inst,
102
                 unsigned RegNo,
103
                 uint64_t Address,
104
                 const void *Decoder);
105
static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo,
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              uint64_t Address,
107
              const void *Decoder);
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static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo,
109
               uint64_t Address,
110
               const void *Decoder);
111
static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo,
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              uint64_t Address,
113
              const void *Decoder);
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static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo,
115
                 uint64_t Address,
116
                 const void *Decoder);
117
static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst *Inst, unsigned RegNo,
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               uint64_t Address,
119
               const void *Decoder);
120
static DecodeStatus DecodeGPRspRegisterClass(MCInst *Inst, unsigned RegNo,
121
               uint64_t Address,
122
               const void *Decoder);
123
static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo,
124
             uint64_t Address,
125
             const void *Decoder);
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static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo,
127
             uint64_t Address,
128
             const void *Decoder);
129
static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo,
130
             uint64_t Address,
131
             const void *Decoder);
132
static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo,
133
               uint64_t Address,
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               const void *Decoder);
135
static DecodeStatus DecodeSPR_8RegisterClass(MCInst *Inst, unsigned RegNo,
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               uint64_t Address,
137
               const void *Decoder);
138
static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo,
139
            uint64_t Address,
140
            const void *Decoder);
141
static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo,
142
             uint64_t Address,
143
             const void *Decoder);
144
static DecodeStatus DecodeMQPRRegisterClass(MCInst *Inst, unsigned RegNo,
145
              uint64_t Address,
146
              const void *Decoder);
147
static DecodeStatus DecodeMQQPRRegisterClass(MCInst *Inst, unsigned RegNo,
148
               uint64_t Address,
149
               const void *Decoder);
150
static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst *Inst, unsigned RegNo,
151
                 uint64_t Address,
152
                 const void *Decoder);
153
static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
154
               uint64_t Address,
155
               const void *Decoder);
156
static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, unsigned RegNo,
157
               uint64_t Address,
158
               const void *Decoder);
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static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val,
161
             uint64_t Address,
162
             const void *Decoder);
163
static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val,
164
               uint64_t Address, const void *Decoder);
165
static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val,
166
           uint64_t Address, const void *Decoder);
167
static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val,
168
              uint64_t Address,
169
              const void *Decoder);
170
static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val,
171
              uint64_t Address,
172
              const void *Decoder);
173
174
static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn,
175
                uint64_t Address,
176
                const void *Decoder);
177
static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
178
              uint64_t Address,
179
              const void *Decoder);
180
static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn,
181
              uint64_t Address,
182
              const void *Decoder);
183
static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn,
184
            uint64_t Address,
185
            const void *Decoder);
186
static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn,
187
                 uint64_t Address,
188
                 const void *Decoder);
189
static DecodeStatus DecodeTSBInstruction(MCInst *Inst, unsigned Insn,
190
           uint64_t Address, const void *Decoder);
191
static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn,
192
            uint64_t Address,
193
            const void *Decoder);
194
static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn,
195
            uint64_t Address,
196
            const void *Decoder);
197
198
static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst,
199
                unsigned Insn,
200
                uint64_t Adddress,
201
                const void *Decoder);
202
static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn,
203
               uint64_t Address,
204
               const void *Decoder);
205
static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn,
206
                uint64_t Address,
207
                const void *Decoder);
208
static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn,
209
            uint64_t Address,
210
            const void *Decoder);
211
static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn,
212
            uint64_t Address,
213
            const void *Decoder);
214
static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn,
215
           uint64_t Address, const void *Decoder);
216
static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn,
217
           uint64_t Address, const void *Decoder);
218
static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn,
219
              uint64_t Address,
220
              const void *Decoder);
221
static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn,
222
             uint64_t Address,
223
             const void *Decoder);
224
static DecodeStatus DecodeT2HintSpaceInstruction(MCInst *Inst, unsigned Insn,
225
             uint64_t Address,
226
             const void *Decoder);
227
static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val,
228
                 uint64_t Address,
229
                 const void *Decoder);
230
static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val,
231
             uint64_t Address,
232
             const void *Decoder);
233
static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val,
234
                 uint64_t Address,
235
                 const void *Decoder);
236
static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val,
237
             uint64_t Address,
238
             const void *Decoder);
239
static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn,
240
           uint64_t Address, const void *Decoder);
241
static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn,
242
                 uint64_t Address,
243
                 const void *Decoder);
244
static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val,
245
             uint64_t Address,
246
             const void *Decoder);
247
static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Val,
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              uint64_t Address,
249
              const void *Decoder);
250
static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Val,
251
              uint64_t Address,
252
              const void *Decoder);
253
static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Val,
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              uint64_t Address,
255
              const void *Decoder);
256
static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Val,
257
              uint64_t Address,
258
              const void *Decoder);
259
static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Val,
260
           uint64_t Address, const void *Decoder);
261
static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Val,
262
           uint64_t Address, const void *Decoder);
263
static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Val,
264
               uint64_t Address,
265
               const void *Decoder);
266
static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Val,
267
               uint64_t Address,
268
               const void *Decoder);
269
static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Val,
270
               uint64_t Address,
271
               const void *Decoder);
272
static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Val,
273
               uint64_t Address,
274
               const void *Decoder);
275
static DecodeStatus DecodeVMOVModImmInstruction(MCInst *Inst, unsigned Val,
276
            uint64_t Address,
277
            const void *Decoder);
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static DecodeStatus DecodeMVEModImmInstruction(MCInst *Inst, unsigned Val,
279
                 uint64_t Address,
280
                 const void *Decoder);
281
static DecodeStatus DecodeMVEVADCInstruction(MCInst *Inst, unsigned Insn,
282
               uint64_t Address,
283
               const void *Decoder);
284
static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Val,
285
               uint64_t Address,
286
               const void *Decoder);
287
static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val,
288
           uint64_t Address, const void *Decoder);
289
static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val,
290
            uint64_t Address,
291
            const void *Decoder);
292
static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val,
293
            uint64_t Address,
294
            const void *Decoder);
295
static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val,
296
            uint64_t Address,
297
            const void *Decoder);
298
static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn,
299
           uint64_t Address, const void *Decoder);
300
static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn,
301
             uint64_t Address, const void *Decoder);
302
static DecodeStatus DecodeMveAddrModeRQ(MCInst *Inst, unsigned Insn,
303
          uint64_t Address, const void *Decoder);
304
#define DECLARE_DecodeMveAddrModeQ(shift) \
305
  static DecodeStatus CONCAT(DecodeMveAddrModeQ, shift)( \
306
    MCInst * Inst, unsigned Insn, uint64_t Address, \
307
    const void *Decoder);
308
DECLARE_DecodeMveAddrModeQ(2) DECLARE_DecodeMveAddrModeQ(3)
309
310
  static DecodeStatus
311
  DecodeCoprocessor(MCInst *Inst, unsigned Insn, uint64_t Address,
312
        const void *Decoder);
313
static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn,
314
             uint64_t Address,
315
             const void *Decoder);
316
static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn,
317
            uint64_t Address,
318
            const void *Decoder);
319
static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn, uint64_t Address,
320
          const void *Decoder);
321
static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Insn,
322
            uint64_t Address, const void *Decoder);
323
static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn,
324
          uint64_t Address, const void *Decoder);
325
static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn,
326
           uint64_t Address, const void *Decoder);
327
static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn,
328
            uint64_t Address, const void *Decoder);
329
static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn,
330
            uint64_t Address, const void *Decoder);
331
static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn,
332
            uint64_t Address, const void *Decoder);
333
static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn,
334
            uint64_t Address, const void *Decoder);
335
static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, uint64_t Address,
336
         const void *Decoder);
337
static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, uint64_t Address,
338
         const void *Decoder);
339
static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, uint64_t Address,
340
         const void *Decoder);
341
static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, uint64_t Address,
342
         const void *Decoder);
343
static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, uint64_t Address,
344
         const void *Decoder);
345
static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, uint64_t Address,
346
         const void *Decoder);
347
static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, uint64_t Address,
348
         const void *Decoder);
349
static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, uint64_t Address,
350
         const void *Decoder);
351
static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, uint64_t Address,
352
          const void *Decoder);
353
static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, uint64_t Address,
354
          const void *Decoder);
355
static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, uint64_t Address,
356
             const void *Decoder);
357
static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, uint64_t Address,
358
        const void *Decoder);
359
static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, uint64_t Address,
360
        const void *Decoder);
361
static DecodeStatus DecodeVCVTImmOperand(MCInst *Inst, unsigned Insn,
362
           uint64_t Address, const void *Decoder);
363
static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst,
364
                   unsigned Val,
365
                   uint64_t Address,
366
                   const void *Decoder);
367
368
static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn,
369
               uint64_t Address,
370
               const void *Decoder);
371
static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val,
372
           uint64_t Address, const void *Decoder);
373
static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val,
374
              uint64_t Address, const void *Decoder);
375
static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val,
376
              uint64_t Address,
377
              const void *Decoder);
378
static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val,
379
            uint64_t Address,
380
            const void *Decoder);
381
static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val,
382
            uint64_t Address,
383
            const void *Decoder);
384
static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val,
385
            uint64_t Address,
386
            const void *Decoder);
387
static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val,
388
            uint64_t Address,
389
            const void *Decoder);
390
static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val,
391
            uint64_t Address,
392
            const void *Decoder);
393
static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Val,
394
              uint64_t Address, const void *Decoder);
395
static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn,
396
             uint64_t Address, const void *Decoder);
397
static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn,
398
              uint64_t Address, const void *Decoder);
399
static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, uint64_t Address,
400
          const void *Decoder);
401
static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn,
402
              uint64_t Address, const void *Decoder);
403
static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, uint64_t Address,
404
           const void *Decoder);
405
static DecodeStatus DecodeT2Imm7S4(MCInst *Inst, unsigned Val, uint64_t Address,
406
           const void *Decoder);
407
static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val,
408
             uint64_t Address,
409
             const void *Decoder);
410
static DecodeStatus DecodeT2AddrModeImm7s4(MCInst *Inst, unsigned Val,
411
             uint64_t Address,
412
             const void *Decoder);
413
static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst, unsigned Val,
414
            uint64_t Address,
415
            const void *Decoder);
416
static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, uint64_t Address,
417
         const void *Decoder);
418
#define DECLARE_DecodeT2Imm7(shift) \
419
  static DecodeStatus CONCAT(DecodeT2Imm7, shift)(MCInst * Inst, \
420
              unsigned Val, \
421
              uint64_t Address, \
422
              const void *Decoder);
423
DECLARE_DecodeT2Imm7(0) DECLARE_DecodeT2Imm7(1) DECLARE_DecodeT2Imm7(2)
424
425
  static DecodeStatus
426
  DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, uint64_t Address,
427
           const void *Decoder);
428
#define DECLARE_DecodeTAddrModeImm7(shift) \
429
  static DecodeStatus CONCAT(DecodeTAddrModeImm7, shift)( \
430
    MCInst * Inst, unsigned Val, uint64_t Address, \
431
    const void *Decoder);
432
DECLARE_DecodeTAddrModeImm7(0) DECLARE_DecodeTAddrModeImm7(1)
433
434
#define DECLARE_DecodeT2AddrModeImm7(shift, WriteBack) \
435
  static DecodeStatus CONCAT(DecodeT2AddrModeImm7, \
436
           CONCAT(shift, WriteBack))( \
437
    MCInst * Inst, unsigned Val, uint64_t Address, \
438
    const void *Decoder);
439
  DECLARE_DecodeT2AddrModeImm7(0, 0) DECLARE_DecodeT2AddrModeImm7(1, 0)
440
    DECLARE_DecodeT2AddrModeImm7(2, 0)
441
      DECLARE_DecodeT2AddrModeImm7(0, 1)
442
        DECLARE_DecodeT2AddrModeImm7(1, 1)
443
          DECLARE_DecodeT2AddrModeImm7(2, 1)
444
445
            static DecodeStatus
446
  DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val, uint64_t Address,
447
          const void *Decoder);
448
static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn,
449
          uint64_t Address, const void *Decoder);
450
static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn,
451
           uint64_t Address, const void *Decoder);
452
static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn,
453
            uint64_t Address,
454
            const void *Decoder);
455
static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Insn,
456
           uint64_t Address, const void *Decoder);
457
static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val,
458
            uint64_t Address,
459
            const void *Decoder);
460
static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Val,
461
             uint64_t Address,
462
             const void *Decoder);
463
static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Val,
464
                 uint64_t Address,
465
                 const void *Decoder);
466
static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, uint64_t Address,
467
          const void *Decoder);
468
static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val,
469
            uint64_t Address,
470
            const void *Decoder);
471
static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val,
472
                 uint64_t Address,
473
                 const void *Decoder);
474
static DecodeStatus DecodeIT(MCInst *Inst, unsigned Val, uint64_t Address,
475
           const void *Decoder);
476
static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn,
477
                 uint64_t Address,
478
                 const void *Decoder);
479
static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn,
480
                 uint64_t Address,
481
                 const void *Decoder);
482
static DecodeStatus DecodeT2Adr(MCInst *Inst, unsigned Val, uint64_t Address,
483
        const void *Decoder);
484
static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Val,
485
            uint64_t Address, const void *Decoder);
486
static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, unsigned Val,
487
                uint64_t Address,
488
                const void *Decoder);
489
490
static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, uint64_t Address,
491
            const void *Decoder);
492
static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val,
493
              uint64_t Address,
494
              const void *Decoder);
495
static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val,
496
           uint64_t Address, const void *Decoder);
497
498
#define DECLARE_DecodeBFLabelOperand(isSigned, isNeg, zeroPermitted, size) \
499
  static DecodeStatus CONCAT( \
500
    DecodeBFLabelOperand, \
501
    CONCAT(isSigned, CONCAT(isNeg, CONCAT(zeroPermitted, size))))( \
502
    MCInst * Inst, unsigned val, uint64_t Address, \
503
    const void *Decoder);
504
DECLARE_DecodeBFLabelOperand(false, false, false,
505
           4) DECLARE_DecodeBFLabelOperand(true, false, true,
506
                   18)
507
  DECLARE_DecodeBFLabelOperand(true, false, true, 12)
508
    DECLARE_DecodeBFLabelOperand(true, false, true, 16)
509
      DECLARE_DecodeBFLabelOperand(false, true, true, 11)
510
        DECLARE_DecodeBFLabelOperand(false, false, true,
511
                   11)
512
513
          static DecodeStatus
514
  DecodeBFAfterTargetOperand(MCInst *Inst, unsigned val, uint64_t Address,
515
           const void *Decoder);
516
static DecodeStatus DecodePredNoALOperand(MCInst *Inst, unsigned Val,
517
            uint64_t Address,
518
            const void *Decoder);
519
static DecodeStatus DecodeLOLoop(MCInst *Inst, unsigned Insn, uint64_t Address,
520
         const void *Decoder);
521
static DecodeStatus DecodeLongShiftOperand(MCInst *Inst, unsigned Val,
522
             uint64_t Address,
523
             const void *Decoder);
524
static DecodeStatus DecodeVSCCLRM(MCInst *Inst, unsigned Insn, uint64_t Address,
525
          const void *Decoder);
526
static DecodeStatus DecodeVPTMaskOperand(MCInst *Inst, unsigned Val,
527
           uint64_t Address, const void *Decoder);
528
static DecodeStatus DecodeVpredROperand(MCInst *Inst, unsigned Val,
529
          uint64_t Address, const void *Decoder);
530
static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst *Inst,
531
                  unsigned Val,
532
                  uint64_t Address,
533
                  const void *Decoder);
534
static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst *Inst,
535
                  unsigned Val,
536
                  uint64_t Address,
537
                  const void *Decoder);
538
static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst *Inst,
539
                  unsigned Val,
540
                  uint64_t Address,
541
                  const void *Decoder);
542
static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst *Inst,
543
                   unsigned Val,
544
                   uint64_t Address,
545
                   const void *Decoder);
546
#define DECLARE_DecodeVSTRVLDR_SYSREG(Writeback) \
547
  static DecodeStatus CONCAT(DecodeVSTRVLDR_SYSREG, Writeback)( \
548
    MCInst * Inst, unsigned Insn, uint64_t Address, \
549
    const void *Decoder);
550
DECLARE_DecodeVSTRVLDR_SYSREG(false) DECLARE_DecodeVSTRVLDR_SYSREG(true)
551
552
#define DECLARE_DecodeMVE_MEM_1_pre(shift) \
553
  static DecodeStatus CONCAT(DecodeMVE_MEM_1_pre, shift)( \
554
    MCInst * Inst, unsigned Val, uint64_t Address, \
555
    const void *Decoder);
556
  DECLARE_DecodeMVE_MEM_1_pre(0) DECLARE_DecodeMVE_MEM_1_pre(1)
557
558
#define DECLARE_DecodeMVE_MEM_2_pre(shift) \
559
  static DecodeStatus CONCAT(DecodeMVE_MEM_2_pre, shift)( \
560
    MCInst * Inst, unsigned Val, uint64_t Address, \
561
    const void *Decoder);
562
    DECLARE_DecodeMVE_MEM_2_pre(0) DECLARE_DecodeMVE_MEM_2_pre(
563
      1) DECLARE_DecodeMVE_MEM_2_pre(2)
564
565
#define DECLARE_DecodeMVE_MEM_3_pre(shift) \
566
  static DecodeStatus CONCAT(DecodeMVE_MEM_3_pre, shift)( \
567
    MCInst * Inst, unsigned Val, uint64_t Address, \
568
    const void *Decoder);
569
      DECLARE_DecodeMVE_MEM_3_pre(
570
        2) DECLARE_DecodeMVE_MEM_3_pre(3)
571
572
#define DECLARE_DecodePowerTwoOperand(MinLog, MaxLog) \
573
  static DecodeStatus CONCAT(DecodePowerTwoOperand, \
574
           CONCAT(MinLog, MaxLog))( \
575
    MCInst * Inst, unsigned Val, uint64_t Address, \
576
    const void *Decoder);
577
        DECLARE_DecodePowerTwoOperand(0, 3)
578
579
#define DECLARE_DecodeMVEPairVectorIndexOperand(start) \
580
  static DecodeStatus CONCAT(DecodeMVEPairVectorIndexOperand, start)( \
581
    MCInst * Inst, unsigned Val, uint64_t Address, \
582
    const void *Decoder);
583
          DECLARE_DecodeMVEPairVectorIndexOperand(
584
            2)
585
            DECLARE_DecodeMVEPairVectorIndexOperand(
586
              0)
587
588
              static DecodeStatus
589
  DecodeMVEVMOVQtoDReg(MCInst *Inst, unsigned Insn, uint64_t Address,
590
           const void *Decoder);
591
static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst *Inst, unsigned Insn,
592
           uint64_t Address, const void *Decoder);
593
static DecodeStatus DecodeMVEVCVTt1fp(MCInst *Inst, unsigned Insn,
594
              uint64_t Address, const void *Decoder);
595
typedef DecodeStatus OperandDecoder(MCInst *Inst, unsigned Val,
596
            uint64_t Address, const void *Decoder);
597
#define DECLARE_DecodeMVEVCMP(scalar, predicate_decoder) \
598
  static DecodeStatus CONCAT(DecodeMVEVCMP, \
599
           CONCAT(scalar, predicate_decoder))( \
600
    MCInst * Inst, unsigned Insn, uint64_t Address, \
601
    const void *Decoder);
602
DECLARE_DecodeMVEVCMP(false, DecodeRestrictedIPredicateOperand) DECLARE_DecodeMVEVCMP(
603
  false, DecodeRestrictedUPredicateOperand)
604
  DECLARE_DecodeMVEVCMP(false, DecodeRestrictedSPredicateOperand)
605
    DECLARE_DecodeMVEVCMP(true, DecodeRestrictedIPredicateOperand)
606
      DECLARE_DecodeMVEVCMP(true,
607
                DecodeRestrictedUPredicateOperand)
608
        DECLARE_DecodeMVEVCMP(
609
          true, DecodeRestrictedSPredicateOperand)
610
          DECLARE_DecodeMVEVCMP(
611
            false,
612
            DecodeRestrictedFPPredicateOperand)
613
            DECLARE_DecodeMVEVCMP(
614
              true,
615
              DecodeRestrictedFPPredicateOperand)
616
617
              static DecodeStatus
618
  DecodeMveVCTP(MCInst *Inst, unsigned Insn, uint64_t Address,
619
          const void *Decoder);
620
static DecodeStatus DecodeMVEVPNOT(MCInst *Inst, unsigned Insn,
621
           uint64_t Address, const void *Decoder);
622
static DecodeStatus DecodeMVEOverlappingLongShift(MCInst *Inst, unsigned Insn,
623
              uint64_t Address,
624
              const void *Decoder);
625
static DecodeStatus DecodeT2AddSubSPImm(MCInst *Inst, unsigned Insn,
626
          uint64_t Address, const void *Decoder);
627
628
#include "ARMGenDisassemblerTables.inc"
629
630
// Post-decoding checks
631
static DecodeStatus checkDecodedInstruction(MCInst *MI, uint32_t Insn,
632
              DecodeStatus Result)
633
216k
{
634
216k
  switch (MCInst_getOpcode(MI)) {
635
98
  case ARM_HVC: {
636
    // HVC is undefined if condition = 0xf otherwise upredictable
637
    // if condition != 0xe
638
98
    uint32_t Cond = (Insn >> 28) & 0xF;
639
98
    if (Cond == 0xF)
640
2
      return MCDisassembler_Fail;
641
96
    if (Cond != 0xE)
642
74
      return MCDisassembler_SoftFail;
643
22
    return Result;
644
96
  }
645
1.16k
  case ARM_t2ADDri:
646
2.04k
  case ARM_t2ADDri12:
647
2.27k
  case ARM_t2ADDrr:
648
2.59k
  case ARM_t2ADDrs:
649
3.34k
  case ARM_t2SUBri:
650
3.77k
  case ARM_t2SUBri12:
651
4.00k
  case ARM_t2SUBrr:
652
4.33k
  case ARM_t2SUBrs:
653
4.33k
    if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP &&
654
4.33k
        MCOperand_getReg(MCInst_getOperand(MI, (1))) != ARM_SP)
655
678
      return MCDisassembler_SoftFail;
656
3.65k
    return Result;
657
211k
  default:
658
211k
    return Result;
659
216k
  }
660
216k
}
661
662
static DecodeStatus getInstruction(csh ud, const uint8_t *Bytes,
663
           size_t BytesLen, MCInst *MI, uint16_t *Size,
664
           uint64_t Address, void *Info)
665
1.22M
{
666
1.22M
  DecodeStatus Result = MCDisassembler_Fail;
667
1.22M
  if (MI->csh->mode & CS_MODE_THUMB)
668
1.07M
    Result = getThumbInstruction(ud, Bytes, BytesLen, MI, Size,
669
1.07M
               Address, Info);
670
145k
  else
671
145k
    Result = getARMInstruction(ud, Bytes, BytesLen, MI, Size,
672
145k
             Address, Info);
673
1.22M
  MCInst_handleWriteback(MI, ARMInsts);
674
1.22M
  return Result;
675
1.22M
}
676
677
static inline uint32_t endianSensitiveOpcode32(MCInst *MI, const uint8_t *Bytes)
678
144k
{
679
144k
  uint32_t Insn;
680
144k
  if (MODE_IS_BIG_ENDIAN(MI->csh->mode))
681
0
    Insn = (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
682
0
           ((uint32_t)Bytes[0] << 24);
683
144k
  else
684
144k
    Insn = ((uint32_t)Bytes[3] << 24) | (Bytes[2] << 16) |
685
144k
           (Bytes[1] << 8) | (Bytes[0] << 0);
686
144k
  return Insn;
687
144k
}
688
689
static inline uint16_t endianSensitiveOpcode16(MCInst *MI, const uint8_t *Bytes)
690
1.38M
{
691
1.38M
  uint16_t Insn;
692
1.38M
  if (MODE_IS_BIG_ENDIAN(MI->csh->mode))
693
0
    Insn = (Bytes[0] << 8) | Bytes[1];
694
1.38M
  else
695
1.38M
    Insn = (Bytes[1] << 8) | Bytes[0];
696
697
1.38M
  return Insn;
698
1.38M
}
699
700
DecodeStatus getARMInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
701
             MCInst *MI, uint16_t *Size, uint64_t Address,
702
             void *Info)
703
145k
{
704
  // We want to read exactly 4 bytes of data.
705
145k
  if (BytesLen < 4) {
706
1.38k
    *Size = 0;
707
1.38k
    return MCDisassembler_Fail;
708
1.38k
  }
709
710
  // Encoded as a 32-bit word in the stream.
711
144k
  uint32_t Insn = endianSensitiveOpcode32(MI, Bytes);
712
713
  // Calling the auto-generated decoder function.
714
144k
  DecodeStatus Result =
715
144k
    decodeInstruction_4(DecoderTableARM32, MI, Insn, Address);
716
144k
  if (Result != MCDisassembler_Fail) {
717
113k
    *Size = 4;
718
113k
    return checkDecodedInstruction(MI, Insn, Result);
719
113k
  }
720
721
30.9k
  typedef struct DecodeTable {
722
30.9k
    const uint8_t *P;
723
30.9k
    bool DecodePred;
724
30.9k
  } DecodeTable;
725
726
30.9k
  const DecodeTable Tables[] = {
727
30.9k
    { DecoderTableVFP32, false },
728
30.9k
    { DecoderTableVFPV832, false },
729
30.9k
    { DecoderTableNEONData32, true },
730
30.9k
    { DecoderTableNEONLoadStore32, true },
731
30.9k
    { DecoderTableNEONDup32, true },
732
30.9k
    { DecoderTablev8NEON32, false },
733
30.9k
    { DecoderTablev8Crypto32, false },
734
30.9k
  };
735
736
177k
  for (int i = 0; i < (sizeof(Tables) / sizeof(Tables[0])); ++i) {
737
158k
    MCInst_clear(MI);
738
158k
    DecodeTable Table = Tables[i];
739
158k
    Result = decodeInstruction_4(Table.P, MI, Insn, Address);
740
158k
    if (Result != MCDisassembler_Fail) {
741
11.6k
      *Size = 4;
742
      // Add a fake predicate operand, because we share these instruction
743
      // definitions with Thumb2 where these instructions are predicable.
744
11.6k
      if (Table.DecodePred &&
745
11.6k
          !DecodePredicateOperand(MI, 0xE, Address, Table.P))
746
0
        return MCDisassembler_Fail;
747
11.6k
      return Result;
748
11.6k
    }
749
158k
  }
750
751
19.2k
  Result = decodeInstruction_4(DecoderTableCoProc32, MI, Insn, Address);
752
19.2k
  if (Result != MCDisassembler_Fail) {
753
18.7k
    *Size = 4;
754
18.7k
    return checkDecodedInstruction(MI, Insn, Result);
755
18.7k
  }
756
757
571
  *Size = 4;
758
571
  return MCDisassembler_Fail;
759
19.2k
}
760
761
extern const MCInstrDesc ARMInsts[];
762
763
/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
764
/// immediate Value in the MCInst.  The immediate Value has had any PC
765
/// adjustment made by the caller.  If the instruction is a branch instruction
766
/// then isBranch is true, else false.  If the getOpInfo() function was set as
767
/// part of the setupForSymbolicDisassembly() call then that function is called
768
/// to get any symbolic information at the Address for this instruction.  If
769
/// that returns non-zero then the symbolic information it returns is used to
770
/// create an MCExpr and that is added as an operand to the MCInst.  If
771
/// getOpInfo() returns zero and isBranch is true then a symbol look up for
772
/// Value is done and if a symbol is found an MCExpr is created with that, else
773
/// an MCExpr with Value is created.  This function returns true if it adds an
774
/// operand to the MCInst and false otherwise.
775
static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
776
             bool isBranch, uint64_t InstSize,
777
             MCInst *MI, const void *Decoder)
778
62.0k
{
779
  // FIXME: Does it make sense for value to be negative?
780
  // return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address,
781
  //         isBranch, /*Offset=*/0, /*OpSize=*/0,
782
  //         InstSize);
783
62.0k
  return false;
784
62.0k
}
785
786
/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
787
/// referenced by a load instruction with the base register that is the Pc.
788
/// These can often be values in a literal pool near the Address of the
789
/// instruction.  The Address of the instruction and its immediate Value are
790
/// used as a possible literal pool entry.  The SymbolLookUp call back will
791
/// return the name of a symbol referenced by the literal pool's entry if
792
/// the referenced address is that of a symbol.  Or it will return a pointer to
793
/// a literal 'C' string if the referenced address of the literal pool's entry
794
/// is an address into a section with 'C' string literals.
795
static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
796
              const void *Decoder)
797
21.0k
{
798
  // Decoder->tryAddingPcLoadReferenceComment(Value, Address);
799
21.0k
}
800
801
// Thumb1 instructions don't have explicit S bits.  Rather, they
802
// implicitly set CPSR.  Since it's not represented in the encoding, the
803
// auto-generated decoder won't inject the CPSR operand.  We need to fix
804
// that as a post-pass.
805
static void AddThumb1SBit(MCInst *MI, bool InITBlock)
806
316k
{
807
316k
  const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
808
316k
  unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
809
316k
  unsigned i;
810
811
642k
  for (i = 0; i < NumOps; ++i) {
812
637k
    if (i == MCInst_getNumOperands(MI))
813
0
      break;
814
637k
    if (MCOperandInfo_isOptionalDef(&OpInfo[i]) &&
815
637k
        OpInfo[i].RegClass == ARM_CCRRegClassID) {
816
311k
      if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i - 1]))
817
0
        continue;
818
311k
      MCInst_insert0(MI, i,
819
311k
               MCOperand_CreateReg1(
820
311k
                 MI, (InITBlock ? 0 : ARM_CPSR)));
821
311k
      return;
822
311k
    }
823
637k
  }
824
825
4.90k
  MCInst_insert0(MI, i,
826
4.90k
           MCOperand_CreateReg1(MI, (InITBlock ? 0 : ARM_CPSR)));
827
4.90k
}
828
829
static bool isVectorPredicable(unsigned Opcode)
830
2.76M
{
831
2.76M
  const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
832
2.76M
  unsigned short NumOps = ARMInsts[Opcode].NumOperands;
833
17.3M
  for (unsigned i = 0; i < NumOps; ++i) {
834
14.7M
    if (ARM_isVpred(OpInfo[i].OperandType))
835
119k
      return true;
836
14.7M
  }
837
2.64M
  return false;
838
2.76M
}
839
840
// Most Thumb instructions don't have explicit predicates in the
841
// encoding, but rather get their predicates from IT context.  We need
842
// to fix up the predicate operands using this context information as a
843
// post-pass.
844
DecodeStatus AddThumbPredicate(MCInst *MI)
845
1.05M
{
846
1.05M
  DecodeStatus S = MCDisassembler_Success;
847
848
  // A few instructions actually have predicates encoded in them.  Don't
849
  // try to overwrite it if we're seeing one of those.
850
1.05M
  switch (MCInst_getOpcode(MI)) {
851
21.5k
  case ARM_tBcc:
852
24.6k
  case ARM_t2Bcc:
853
27.0k
  case ARM_tCBZ:
854
29.2k
  case ARM_tCBNZ:
855
29.7k
  case ARM_tCPS:
856
29.7k
  case ARM_t2CPS3p:
857
30.1k
  case ARM_t2CPS2p:
858
30.3k
  case ARM_t2CPS1p:
859
30.4k
  case ARM_t2CSEL:
860
30.5k
  case ARM_t2CSINC:
861
30.7k
  case ARM_t2CSINV:
862
31.5k
  case ARM_t2CSNEG:
863
124k
  case ARM_tMOVSr:
864
124k
  case ARM_tSETEND:
865
    // Some instructions (mostly conditional branches) are not
866
    // allowed in IT blocks.
867
124k
    if (ITBlock_instrInITBlock(&(MI->csh->ITBlock)))
868
1.34k
      S = MCDisassembler_SoftFail;
869
123k
    else
870
123k
      return MCDisassembler_Success;
871
1.34k
    break;
872
1.34k
  case ARM_t2HINT:
873
736
    if (MCOperand_getImm(MCInst_getOperand(MI, (0))) == 0x10 &&
874
736
        (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureRAS)) != 0)
875
0
      S = MCDisassembler_SoftFail;
876
736
    break;
877
15.5k
  case ARM_tB:
878
16.7k
  case ARM_t2B:
879
16.8k
  case ARM_t2TBB:
880
17.1k
  case ARM_t2TBH:
881
    // Some instructions (mostly unconditional branches) can
882
    // only appears at the end of, or outside of, an IT.
883
17.1k
    if (ITBlock_instrInITBlock(&(MI->csh->ITBlock)) &&
884
17.1k
        !ITBlock_instrLastInITBlock(&(MI->csh->ITBlock)))
885
945
      S = MCDisassembler_SoftFail;
886
17.1k
    break;
887
909k
  default:
888
909k
    break;
889
1.05M
  }
890
891
  // Warn on non-VPT predicable instruction in a VPT block and a VPT
892
  // predicable instruction in an IT block
893
928k
  if ((!isVectorPredicable(MCInst_getOpcode(MI)) &&
894
928k
       VPTBlock_instrInVPTBlock(&(MI->csh->VPTBlock))) ||
895
928k
      (isVectorPredicable(MCInst_getOpcode(MI)) &&
896
906k
       ITBlock_instrInITBlock(&(MI->csh->ITBlock))))
897
23.9k
    S = MCDisassembler_SoftFail;
898
899
  // If we're in an IT/VPT block, base the predicate on that.  Otherwise,
900
  // assume a predicate of AL.
901
928k
  unsigned CC = ARMCC_AL;
902
928k
  unsigned VCC = ARMVCC_None;
903
928k
  if (ITBlock_instrInITBlock(&(MI->csh->ITBlock))) {
904
26.8k
    CC = ITBlock_getITCC(&(MI->csh->ITBlock));
905
26.8k
    ITBlock_advanceITState(&(MI->csh->ITBlock));
906
902k
  } else if (VPTBlock_instrInVPTBlock(&(MI->csh->VPTBlock))) {
907
25.0k
    VCC = VPTBlock_getVPTPred(&(MI->csh->VPTBlock));
908
25.0k
    VPTBlock_advanceVPTState(&(MI->csh->VPTBlock));
909
25.0k
  }
910
911
928k
  const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
912
928k
  unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
913
914
928k
  unsigned i;
915
3.82M
  for (i = 0; i < NumOps; ++i) {
916
3.79M
    if (MCOperandInfo_isPredicate(&OpInfo[i]) ||
917
3.79M
        i == MCInst_getNumOperands(MI))
918
891k
      break;
919
3.79M
  }
920
921
928k
  if (MCInst_isPredicable(&ARMInsts[MCInst_getOpcode(MI)])) {
922
854k
    MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, (CC)));
923
924
854k
    if (CC == ARMCC_AL)
925
840k
      MCInst_insert0(MI, i + 1,
926
840k
               MCOperand_CreateReg1(MI, (0)));
927
14.7k
    else
928
14.7k
      MCInst_insert0(MI, i + 1,
929
14.7k
               MCOperand_CreateReg1(MI, (ARM_CPSR)));
930
854k
  } else if (CC != ARMCC_AL) {
931
8.51k
    Check(&S, MCDisassembler_SoftFail);
932
8.51k
  }
933
934
928k
  unsigned VCCPos;
935
5.57M
  for (VCCPos = 0; VCCPos < NumOps; ++VCCPos) {
936
4.94M
    if (ARM_isVpred(OpInfo[VCCPos].OperandType) ||
937
4.94M
        VCCPos == MCInst_getNumOperands(MI))
938
295k
      break;
939
4.94M
  }
940
941
928k
  if (isVectorPredicable(MCInst_getOpcode(MI))) {
942
39.9k
    MCInst_insert0(MI, VCCPos, MCOperand_CreateImm1(MI, (VCC)));
943
944
39.9k
    if (VCC == ARMVCC_None)
945
35.7k
      MCInst_insert0(MI, VCCPos + 1,
946
35.7k
               MCOperand_CreateReg1(MI, (0)));
947
4.19k
    else
948
4.19k
      MCInst_insert0(MI, VCCPos + 1,
949
4.19k
               MCOperand_CreateReg1(MI, (ARM_P0)));
950
39.9k
    MCInst_insert0(MI, VCCPos + 2, MCOperand_CreateReg1(MI, (0)));
951
39.9k
    if (OpInfo[VCCPos].OperandType == ARM_OP_VPRED_R) {
952
9.50k
      int TiedOp = MCOperandInfo_getOperandConstraint(
953
9.50k
        &ARMInsts[MCInst_getOpcode(MI)], VCCPos + 3,
954
9.50k
        MCOI_TIED_TO);
955
9.50k
      assert(TiedOp >= 0 &&
956
9.50k
             "Inactive register in vpred_r is not tied to an output!");
957
      // Copy the operand to ensure it's not invalidated when MI grows.
958
9.50k
      MCOperand *Op = malloc(sizeof(MCOperand));
959
9.50k
      memcpy(Op, MCInst_getOperand(MI, TiedOp),
960
9.50k
             sizeof(MCOperand));
961
9.50k
      MCInst_insert0(MI, VCCPos + 3, Op);
962
9.50k
      free(Op);
963
9.50k
    }
964
889k
  } else if (VCC != ARMVCC_None) {
965
20.8k
    Check(&S, MCDisassembler_SoftFail);
966
20.8k
  }
967
968
928k
  return S;
969
928k
}
970
971
// Thumb VFP instructions are a special case.  Because we share their
972
// encodings between ARM and Thumb modes, and they are predicable in ARM
973
// mode, the auto-generated decoder will give them an (incorrect)
974
// predicate operand.  We need to rewrite these operands based on the IT
975
// context as a post-pass.
976
void UpdateThumbVFPPredicate(DecodeStatus S, MCInst *MI)
977
14.1k
{
978
14.1k
  unsigned CC;
979
14.1k
  CC = ITBlock_getITCC(&(MI->csh->ITBlock));
980
14.1k
  if (CC == 0xF)
981
94
    CC = ARMCC_AL;
982
14.1k
  if (ITBlock_instrInITBlock(&(MI->csh->ITBlock)))
983
477
    ITBlock_advanceITState(&(MI->csh->ITBlock));
984
13.6k
  else if (VPTBlock_instrInVPTBlock(&(MI->csh->VPTBlock))) {
985
281
    CC = VPTBlock_getVPTPred(&(MI->csh->VPTBlock));
986
281
    VPTBlock_advanceVPTState(&(MI->csh->VPTBlock));
987
281
  }
988
989
14.1k
  const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
990
14.1k
  unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
991
46.0k
  for (unsigned i = 0; i < NumOps; ++i) {
992
46.0k
    if (MCOperandInfo_isPredicate(&OpInfo[i])) {
993
14.1k
      if (CC != ARMCC_AL &&
994
14.1k
          !MCInst_isPredicable(
995
634
            &ARMInsts[MCInst_getOpcode(MI)]))
996
0
        Check(&S, MCDisassembler_SoftFail);
997
14.1k
      MCOperand_setImm(MCInst_getOperand(MI, i), CC);
998
999
14.1k
      if (CC == ARMCC_AL)
1000
13.4k
        MCOperand_setReg(MCInst_getOperand(MI, i + 1),
1001
13.4k
             0);
1002
634
      else
1003
634
        MCOperand_setReg(MCInst_getOperand(MI, i + 1),
1004
634
             ARM_CPSR);
1005
1006
14.1k
      return;
1007
14.1k
    }
1008
46.0k
  }
1009
14.1k
}
1010
1011
DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
1012
         MCInst *MI, uint16_t *Size, uint64_t Address,
1013
         void *Info)
1014
1.07M
{
1015
  // We want to read exactly 2 bytes of data.
1016
1.07M
  if (BytesLen < 2) {
1017
3.02k
    *Size = 0;
1018
3.02k
    return MCDisassembler_Fail;
1019
3.02k
  }
1020
1021
1.07M
  uint16_t Insn16 = endianSensitiveOpcode16(MI, Bytes);
1022
1.07M
  DecodeStatus Result =
1023
1.07M
    decodeInstruction_2(DecoderTableThumb16, MI, Insn16, Address);
1024
1.07M
  if (Result != MCDisassembler_Fail) {
1025
486k
    *Size = 2;
1026
486k
    Check(&Result, AddThumbPredicate(MI));
1027
486k
    return Result;
1028
486k
  }
1029
1030
585k
  Result = decodeInstruction_2(DecoderTableThumbSBit16, MI, Insn16,
1031
585k
             Address);
1032
585k
  if (Result) {
1033
255k
    *Size = 2;
1034
255k
    bool InITBlock = ITBlock_instrInITBlock(&(MI->csh->ITBlock));
1035
255k
    Check(&Result, AddThumbPredicate(MI));
1036
255k
    AddThumb1SBit(MI, InITBlock);
1037
255k
    return Result;
1038
255k
  }
1039
1040
329k
  Result = decodeInstruction_2(DecoderTableThumb216, MI, Insn16, Address);
1041
329k
  if (Result != MCDisassembler_Fail) {
1042
11.2k
    *Size = 2;
1043
1044
    // Nested IT blocks are UNPREDICTABLE.  Must be checked before we add
1045
    // the Thumb predicate.
1046
11.2k
    if (MCInst_getOpcode(MI) == ARM_t2IT &&
1047
11.2k
        ITBlock_instrInITBlock(&(MI->csh->ITBlock)))
1048
6.69k
      Result = MCDisassembler_SoftFail;
1049
1050
11.2k
    Check(&Result, AddThumbPredicate(MI));
1051
1052
    // If we find an IT instruction, we need to parse its condition
1053
    // code and mask operands so that we can apply them correctly
1054
    // to the subsequent instructions.
1055
11.2k
    if (MCInst_getOpcode(MI) == ARM_t2IT) {
1056
11.2k
      unsigned Firstcond =
1057
11.2k
        MCOperand_getImm(MCInst_getOperand(MI, (0)));
1058
11.2k
      unsigned Mask =
1059
11.2k
        MCOperand_getImm(MCInst_getOperand(MI, (1)));
1060
11.2k
      ITBlock_setITState(&(MI->csh->ITBlock), (char)Firstcond,
1061
11.2k
             (char)Mask);
1062
1063
      // An IT instruction that would give a 'NV' predicate is
1064
      // unpredictable. if (Firstcond == ARMCC_AL && !isPowerOf2_32(Mask))
1065
      //  SStream_concat0(CS, "unpredictable IT predicate sequence");
1066
11.2k
    }
1067
1068
11.2k
    return Result;
1069
11.2k
  }
1070
1071
  // We want to read exactly 4 bytes of data.
1072
318k
  if (BytesLen < 4) {
1073
822
    *Size = 0;
1074
822
    return MCDisassembler_Fail;
1075
822
  }
1076
317k
  uint32_t Insn32 = (uint32_t)Insn16 << 16 |
1077
317k
        endianSensitiveOpcode16(MI, Bytes + 2);
1078
1079
317k
  Result = decodeInstruction_4(DecoderTableMVE32, MI, Insn32, Address);
1080
317k
  if (Result != MCDisassembler_Fail) {
1081
51.2k
    *Size = 4;
1082
1083
    // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
1084
    // the VPT predicate.
1085
51.2k
    if (isVPTOpcode(MCInst_getOpcode(MI)) &&
1086
51.2k
        VPTBlock_instrInVPTBlock(&(MI->csh->VPTBlock)))
1087
5.07k
      Result = MCDisassembler_SoftFail;
1088
1089
51.2k
    Check(&Result, AddThumbPredicate(MI));
1090
1091
51.2k
    if (isVPTOpcode(MCInst_getOpcode(MI))) {
1092
9.69k
      unsigned Mask =
1093
9.69k
        MCOperand_getImm(MCInst_getOperand(MI, (0)));
1094
9.69k
      VPTBlock_setVPTState(&(MI->csh->VPTBlock), Mask);
1095
9.69k
    }
1096
1097
51.2k
    return Result;
1098
51.2k
  }
1099
1100
265k
  Result = decodeInstruction_4(DecoderTableThumb32, MI, Insn32, Address);
1101
265k
  if (Result != MCDisassembler_Fail) {
1102
3.89k
    *Size = 4;
1103
3.89k
    bool InITBlock = ITBlock_instrInITBlock(&(MI->csh->ITBlock));
1104
3.89k
    Check(&Result, AddThumbPredicate(MI));
1105
3.89k
    AddThumb1SBit(MI, InITBlock);
1106
3.89k
    return Result;
1107
3.89k
  }
1108
1109
262k
  Result = decodeInstruction_4(DecoderTableThumb232, MI, Insn32, Address);
1110
262k
  if (Result != MCDisassembler_Fail) {
1111
83.9k
    *Size = 4;
1112
83.9k
    Check(&Result, AddThumbPredicate(MI));
1113
83.9k
    return checkDecodedInstruction(MI, Insn32, Result);
1114
83.9k
  }
1115
1116
178k
  if (fieldFromInstruction_4(Insn32, 28, 4) == 0xE) {
1117
54.7k
    Result = decodeInstruction_4(DecoderTableVFP32, MI, Insn32,
1118
54.7k
               Address);
1119
54.7k
    if (Result != MCDisassembler_Fail) {
1120
14.1k
      *Size = 4;
1121
14.1k
      UpdateThumbVFPPredicate(Result, MI);
1122
14.1k
      return Result;
1123
14.1k
    }
1124
54.7k
  }
1125
1126
164k
  Result = decodeInstruction_4(DecoderTableVFPV832, MI, Insn32, Address);
1127
164k
  if (Result != MCDisassembler_Fail) {
1128
3.28k
    *Size = 4;
1129
3.28k
    return Result;
1130
3.28k
  }
1131
1132
160k
  if (fieldFromInstruction_4(Insn32, 28, 4) == 0xE) {
1133
40.5k
    Result = decodeInstruction_4(DecoderTableNEONDup32, MI, Insn32,
1134
40.5k
               Address);
1135
40.5k
    if (Result != MCDisassembler_Fail) {
1136
2.13k
      *Size = 4;
1137
2.13k
      Check(&Result, AddThumbPredicate(MI));
1138
2.13k
      return Result;
1139
2.13k
    }
1140
40.5k
  }
1141
1142
158k
  if (fieldFromInstruction_4(Insn32, 24, 8) == 0xF9) {
1143
58.0k
    uint32_t NEONLdStInsn = Insn32;
1144
58.0k
    NEONLdStInsn &= 0xF0FFFFFF;
1145
58.0k
    NEONLdStInsn |= 0x04000000;
1146
58.0k
    Result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI,
1147
58.0k
               NEONLdStInsn, Address);
1148
58.0k
    if (Result != MCDisassembler_Fail) {
1149
57.8k
      *Size = 4;
1150
57.8k
      Check(&Result, AddThumbPredicate(MI));
1151
57.8k
      return Result;
1152
57.8k
    }
1153
58.0k
  }
1154
1155
100k
  if (fieldFromInstruction_4(Insn32, 24, 4) == 0xF) {
1156
38.9k
    uint32_t NEONDataInsn = Insn32;
1157
38.9k
    NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
1158
38.9k
    NEONDataInsn |= (NEONDataInsn & 0x10000000) >>
1159
38.9k
        4;      // Move bit 28 to bit 24
1160
38.9k
    NEONDataInsn |= 0x12000000; // Set bits 28 and 25
1161
38.9k
    Result = decodeInstruction_4(DecoderTableNEONData32, MI,
1162
38.9k
               NEONDataInsn, Address);
1163
38.9k
    if (Result != MCDisassembler_Fail) {
1164
38.2k
      *Size = 4;
1165
38.2k
      Check(&Result, AddThumbPredicate(MI));
1166
38.2k
      return Result;
1167
38.2k
    }
1168
1169
756
    uint32_t NEONCryptoInsn = Insn32;
1170
756
    NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
1171
756
    NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >>
1172
756
          4;        // Move bit 28 to bit 24
1173
756
    NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
1174
756
    Result = decodeInstruction_4(DecoderTablev8Crypto32, MI,
1175
756
               NEONCryptoInsn, Address);
1176
756
    if (Result != MCDisassembler_Fail) {
1177
69
      *Size = 4;
1178
69
      return Result;
1179
69
    }
1180
1181
687
    uint32_t NEONv8Insn = Insn32;
1182
687
    NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
1183
687
    Result = decodeInstruction_4(DecoderTablev8NEON32, MI,
1184
687
               NEONv8Insn, Address);
1185
687
    if (Result != MCDisassembler_Fail) {
1186
283
      *Size = 4;
1187
283
      return Result;
1188
283
    }
1189
687
  }
1190
1191
62.1k
  uint32_t Coproc = fieldFromInstruction_4(Insn32, 8, 4);
1192
62.1k
  const uint8_t *DecoderTable = ARM_isCDECoproc(Coproc, MI) ?
1193
0
                DecoderTableThumb2CDE32 :
1194
62.1k
                DecoderTableThumb2CoProc32;
1195
62.1k
  Result = decodeInstruction_4(DecoderTable, MI, Insn32, Address);
1196
62.1k
  if (Result != MCDisassembler_Fail) {
1197
61.0k
    *Size = 4;
1198
61.0k
    Check(&Result, AddThumbPredicate(MI));
1199
61.0k
    return Result;
1200
61.0k
  }
1201
1202
1.14k
  *Size = 0;
1203
1.14k
  return MCDisassembler_Fail;
1204
62.1k
}
1205
1206
static const uint16_t GPRDecoderTable[] = { ARM_R0,  ARM_R1, ARM_R2,  ARM_R3,
1207
              ARM_R4,  ARM_R5, ARM_R6,  ARM_R7,
1208
              ARM_R8,  ARM_R9, ARM_R10, ARM_R11,
1209
              ARM_R12, ARM_SP, ARM_LR,  ARM_PC };
1210
1211
static const uint16_t CLRMGPRDecoderTable[] = {
1212
  ARM_R0, ARM_R1, ARM_R2,  ARM_R3,  ARM_R4,  ARM_R5, ARM_R6, ARM_R7,
1213
  ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, 0,    ARM_LR, ARM_APSR
1214
};
1215
1216
static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo,
1217
             uint64_t Address,
1218
             const void *Decoder)
1219
2.70M
{
1220
2.70M
  if (RegNo > 15)
1221
13
    return MCDisassembler_Fail;
1222
1223
2.70M
  unsigned Register = GPRDecoderTable[RegNo];
1224
2.70M
  MCOperand_CreateReg0(Inst, (Register));
1225
2.70M
  return MCDisassembler_Success;
1226
2.70M
}
1227
1228
static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst *Inst, unsigned RegNo,
1229
                 uint64_t Address,
1230
                 const void *Decoder)
1231
1.35k
{
1232
1.35k
  if (RegNo > 15)
1233
0
    return MCDisassembler_Fail;
1234
1235
1.35k
  unsigned Register = CLRMGPRDecoderTable[RegNo];
1236
1.35k
  if (Register == 0)
1237
0
    return MCDisassembler_Fail;
1238
1239
1.35k
  MCOperand_CreateReg0(Inst, (Register));
1240
1.35k
  return MCDisassembler_Success;
1241
1.35k
}
1242
1243
static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo,
1244
                 uint64_t Address,
1245
                 const void *Decoder)
1246
113k
{
1247
113k
  DecodeStatus S = MCDisassembler_Success;
1248
1249
113k
  if (RegNo == 15)
1250
21.1k
    S = MCDisassembler_SoftFail;
1251
1252
113k
  Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1253
1254
113k
  return S;
1255
113k
}
1256
1257
static DecodeStatus DecodeGPRnospRegisterClass(MCInst *Inst, unsigned RegNo,
1258
                 uint64_t Address,
1259
                 const void *Decoder)
1260
440
{
1261
440
  DecodeStatus S = MCDisassembler_Success;
1262
1263
440
  if (RegNo == 13)
1264
224
    S = MCDisassembler_SoftFail;
1265
1266
440
  Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1267
1268
440
  return S;
1269
440
}
1270
1271
static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo,
1272
               uint64_t Address,
1273
               const void *Decoder)
1274
6.55k
{
1275
6.55k
  DecodeStatus S = MCDisassembler_Success;
1276
1277
6.55k
  if (RegNo == 15) {
1278
1.49k
    MCOperand_CreateReg0(Inst, (ARM_APSR_NZCV));
1279
1.49k
    return MCDisassembler_Success;
1280
1.49k
  }
1281
1282
5.06k
  Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1283
5.06k
  return S;
1284
6.55k
}
1285
1286
static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst *Inst, unsigned RegNo,
1287
             uint64_t Address,
1288
             const void *Decoder)
1289
9.37k
{
1290
9.37k
  DecodeStatus S = MCDisassembler_Success;
1291
1292
9.37k
  if (RegNo == 15) {
1293
3.49k
    MCOperand_CreateReg0(Inst, (ARM_ZR));
1294
3.49k
    return MCDisassembler_Success;
1295
3.49k
  }
1296
1297
5.87k
  if (RegNo == 13)
1298
518
    Check(&S, MCDisassembler_SoftFail);
1299
1300
5.87k
  Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1301
5.87k
  return S;
1302
9.37k
}
1303
1304
static DecodeStatus DecodeGPRwithZRnospRegisterClass(MCInst *Inst,
1305
                 unsigned RegNo,
1306
                 uint64_t Address,
1307
                 const void *Decoder)
1308
2.27k
{
1309
2.27k
  DecodeStatus S = MCDisassembler_Success;
1310
2.27k
  if (RegNo == 13)
1311
3
    return MCDisassembler_Fail;
1312
2.27k
  Check(&S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
1313
2.27k
  return S;
1314
2.27k
}
1315
1316
static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo,
1317
              uint64_t Address,
1318
              const void *Decoder)
1319
1.53M
{
1320
1.53M
  if (RegNo > 7)
1321
0
    return MCDisassembler_Fail;
1322
1.53M
  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
1323
1.53M
}
1324
1325
static const uint16_t GPRPairDecoderTable[] = { ARM_R0_R1, ARM_R2_R3,
1326
            ARM_R4_R5, ARM_R6_R7,
1327
            ARM_R8_R9, ARM_R10_R11,
1328
            ARM_R12_SP };
1329
1330
static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo,
1331
                 uint64_t Address,
1332
                 const void *Decoder)
1333
1.06k
{
1334
1.06k
  DecodeStatus S = MCDisassembler_Success;
1335
1336
  // According to the Arm ARM RegNo = 14 is undefined, but we return fail
1337
  // rather than SoftFail as there is no GPRPair table entry for index 7.
1338
1.06k
  if (RegNo > 13)
1339
3
    return MCDisassembler_Fail;
1340
1341
1.06k
  if (RegNo & 1)
1342
642
    S = MCDisassembler_SoftFail;
1343
1344
1.06k
  unsigned RegisterPair = GPRPairDecoderTable[RegNo / 2];
1345
1.06k
  MCOperand_CreateReg0(Inst, (RegisterPair));
1346
1.06k
  return S;
1347
1.06k
}
1348
1349
static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst *Inst, unsigned RegNo,
1350
               uint64_t Address,
1351
               const void *Decoder)
1352
0
{
1353
0
  if (RegNo > 13)
1354
0
    return MCDisassembler_Fail;
1355
1356
0
  unsigned RegisterPair = GPRPairDecoderTable[RegNo / 2];
1357
0
  MCOperand_CreateReg0(Inst, (RegisterPair));
1358
1359
0
  if ((RegNo & 1) || RegNo > 10)
1360
0
    return MCDisassembler_SoftFail;
1361
0
  return MCDisassembler_Success;
1362
0
}
1363
1364
static DecodeStatus DecodeGPRspRegisterClass(MCInst *Inst, unsigned RegNo,
1365
               uint64_t Address,
1366
               const void *Decoder)
1367
1.91k
{
1368
1.91k
  if (RegNo != 13)
1369
0
    return MCDisassembler_Fail;
1370
1371
1.91k
  unsigned Register = GPRDecoderTable[RegNo];
1372
1.91k
  MCOperand_CreateReg0(Inst, (Register));
1373
1.91k
  return MCDisassembler_Success;
1374
1.91k
}
1375
1376
static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo,
1377
               uint64_t Address,
1378
               const void *Decoder)
1379
717
{
1380
717
  unsigned Register = 0;
1381
717
  switch (RegNo) {
1382
682
  case 0:
1383
682
    Register = ARM_R0;
1384
682
    break;
1385
24
  case 1:
1386
24
    Register = ARM_R1;
1387
24
    break;
1388
1
  case 2:
1389
1
    Register = ARM_R2;
1390
1
    break;
1391
1
  case 3:
1392
1
    Register = ARM_R3;
1393
1
    break;
1394
0
  case 9:
1395
0
    Register = ARM_R9;
1396
0
    break;
1397
4
  case 12:
1398
4
    Register = ARM_R12;
1399
4
    break;
1400
5
  default:
1401
5
    return MCDisassembler_Fail;
1402
717
  }
1403
1404
712
  MCOperand_CreateReg0(Inst, (Register));
1405
712
  return MCDisassembler_Success;
1406
717
}
1407
1408
static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo,
1409
              uint64_t Address,
1410
              const void *Decoder)
1411
181k
{
1412
181k
  DecodeStatus S = MCDisassembler_Success;
1413
1414
181k
  if ((RegNo == 13 &&
1415
181k
       !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) ||
1416
181k
      RegNo == 15)
1417
43.5k
    S = MCDisassembler_SoftFail;
1418
1419
181k
  Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1420
181k
  return S;
1421
181k
}
1422
1423
static const uint16_t SPRDecoderTable[] = {
1424
  ARM_S0,  ARM_S1,  ARM_S2,  ARM_S3,  ARM_S4,  ARM_S5,  ARM_S6,  ARM_S7,
1425
  ARM_S8,  ARM_S9,  ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15,
1426
  ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23,
1427
  ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31
1428
};
1429
1430
static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo,
1431
             uint64_t Address,
1432
             const void *Decoder)
1433
64.7k
{
1434
64.7k
  if (RegNo > 31)
1435
3
    return MCDisassembler_Fail;
1436
1437
64.7k
  unsigned Register = SPRDecoderTable[RegNo];
1438
64.7k
  MCOperand_CreateReg0(Inst, (Register));
1439
64.7k
  return MCDisassembler_Success;
1440
64.7k
}
1441
1442
static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo,
1443
             uint64_t Address,
1444
             const void *Decoder)
1445
12.6k
{
1446
12.6k
  return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1447
12.6k
}
1448
1449
static const uint16_t DPRDecoderTable[] = {
1450
  ARM_D0,  ARM_D1,  ARM_D2,  ARM_D3,  ARM_D4,  ARM_D5,  ARM_D6,  ARM_D7,
1451
  ARM_D8,  ARM_D9,  ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15,
1452
  ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23,
1453
  ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31
1454
};
1455
1456
static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo,
1457
             uint64_t Address,
1458
             const void *Decoder)
1459
223k
{
1460
223k
  bool hasD32 = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureD32);
1461
1462
223k
  if (RegNo > 31 || (!hasD32 && RegNo > 15))
1463
18
    return MCDisassembler_Fail;
1464
1465
223k
  unsigned Register = DPRDecoderTable[RegNo];
1466
223k
  MCOperand_CreateReg0(Inst, (Register));
1467
223k
  return MCDisassembler_Success;
1468
223k
}
1469
1470
static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo,
1471
               uint64_t Address,
1472
               const void *Decoder)
1473
2.75k
{
1474
2.75k
  if (RegNo > 7)
1475
0
    return MCDisassembler_Fail;
1476
2.75k
  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1477
2.75k
}
1478
1479
static DecodeStatus DecodeSPR_8RegisterClass(MCInst *Inst, unsigned RegNo,
1480
               uint64_t Address,
1481
               const void *Decoder)
1482
206
{
1483
206
  if (RegNo > 15)
1484
0
    return MCDisassembler_Fail;
1485
206
  return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1486
206
}
1487
1488
static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo,
1489
            uint64_t Address,
1490
            const void *Decoder)
1491
4.82k
{
1492
4.82k
  if (RegNo > 15)
1493
0
    return MCDisassembler_Fail;
1494
4.82k
  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1495
4.82k
}
1496
1497
static const uint16_t QPRDecoderTable[] = {
1498
  ARM_Q0, ARM_Q1, ARM_Q2,  ARM_Q3,  ARM_Q4,  ARM_Q5,  ARM_Q6,  ARM_Q7,
1499
  ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15
1500
};
1501
1502
static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo,
1503
             uint64_t Address,
1504
             const void *Decoder)
1505
59.6k
{
1506
59.6k
  if (RegNo > 31 || (RegNo & 1) != 0)
1507
3.47k
    return MCDisassembler_Fail;
1508
56.1k
  RegNo >>= 1;
1509
1510
56.1k
  unsigned Register = QPRDecoderTable[RegNo];
1511
56.1k
  MCOperand_CreateReg0(Inst, (Register));
1512
56.1k
  return MCDisassembler_Success;
1513
59.6k
}
1514
1515
static const uint16_t DPairDecoderTable[] = {
1516
  ARM_Q0,  ARM_D1_D2,   ARM_Q1,  ARM_D3_D4,   ARM_Q2,  ARM_D5_D6,
1517
  ARM_Q3,  ARM_D7_D8,   ARM_Q4,  ARM_D9_D10,  ARM_Q5,  ARM_D11_D12,
1518
  ARM_Q6,  ARM_D13_D14, ARM_Q7,  ARM_D15_D16, ARM_Q8,  ARM_D17_D18,
1519
  ARM_Q9,  ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24,
1520
  ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30,
1521
  ARM_Q15
1522
};
1523
1524
static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
1525
               uint64_t Address,
1526
               const void *Decoder)
1527
13.3k
{
1528
13.3k
  if (RegNo > 30)
1529
8
    return MCDisassembler_Fail;
1530
1531
13.3k
  unsigned Register = DPairDecoderTable[RegNo];
1532
13.3k
  MCOperand_CreateReg0(Inst, (Register));
1533
13.3k
  return MCDisassembler_Success;
1534
13.3k
}
1535
1536
static const uint16_t DPairSpacedDecoderTable[] = {
1537
  ARM_D0_D2,   ARM_D1_D3,   ARM_D2_D4,   ARM_D3_D5,   ARM_D4_D6,
1538
  ARM_D5_D7,   ARM_D6_D8,   ARM_D7_D9,   ARM_D8_D10,  ARM_D9_D11,
1539
  ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16,
1540
  ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21,
1541
  ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26,
1542
  ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31
1543
};
1544
1545
static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, unsigned RegNo,
1546
               uint64_t Address,
1547
               const void *Decoder)
1548
7.14k
{
1549
7.14k
  if (RegNo > 29)
1550
17
    return MCDisassembler_Fail;
1551
1552
7.13k
  unsigned Register = DPairSpacedDecoderTable[RegNo];
1553
7.13k
  MCOperand_CreateReg0(Inst, (Register));
1554
7.13k
  return MCDisassembler_Success;
1555
7.14k
}
1556
1557
static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val,
1558
             uint64_t Address,
1559
             const void *Decoder)
1560
168k
{
1561
168k
  DecodeStatus S = MCDisassembler_Success;
1562
168k
  if (Val == 0xF)
1563
5.31k
    return MCDisassembler_Fail;
1564
  // AL predicate is not allowed on Thumb1 branches.
1565
163k
  if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE)
1566
0
    return MCDisassembler_Fail;
1567
163k
  if (Val != ARMCC_AL &&
1568
163k
      !MCInst_isPredicable(&ARMInsts[MCInst_getOpcode(Inst)]))
1569
0
    Check(&S, MCDisassembler_SoftFail);
1570
163k
  MCOperand_CreateImm0(Inst, (Val));
1571
163k
  if (Val == ARMCC_AL) {
1572
23.6k
    MCOperand_CreateReg0(Inst, (0));
1573
23.6k
  } else
1574
139k
    MCOperand_CreateReg0(Inst, (ARM_CPSR));
1575
163k
  return S;
1576
163k
}
1577
1578
static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val,
1579
               uint64_t Address, const void *Decoder)
1580
60.8k
{
1581
60.8k
  if (Val)
1582
20.0k
    MCOperand_CreateReg0(Inst, (ARM_CPSR));
1583
40.7k
  else
1584
40.7k
    MCOperand_CreateReg0(Inst, (0));
1585
60.8k
  return MCDisassembler_Success;
1586
60.8k
}
1587
1588
static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val,
1589
            uint64_t Address, const void *Decoder)
1590
22.2k
{
1591
22.2k
  DecodeStatus S = MCDisassembler_Success;
1592
1593
22.2k
  unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
1594
22.2k
  unsigned type = fieldFromInstruction_4(Val, 5, 2);
1595
22.2k
  unsigned imm = fieldFromInstruction_4(Val, 7, 5);
1596
1597
  // Register-immediate
1598
22.2k
  if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1599
0
    return MCDisassembler_Fail;
1600
1601
22.2k
  ARM_AM_ShiftOpc Shift = ARM_AM_lsl;
1602
22.2k
  switch (type) {
1603
7.70k
  case 0:
1604
7.70k
    Shift = ARM_AM_lsl;
1605
7.70k
    break;
1606
3.71k
  case 1:
1607
3.71k
    Shift = ARM_AM_lsr;
1608
3.71k
    break;
1609
5.14k
  case 2:
1610
5.14k
    Shift = ARM_AM_asr;
1611
5.14k
    break;
1612
5.68k
  case 3:
1613
5.68k
    Shift = ARM_AM_ror;
1614
5.68k
    break;
1615
22.2k
  }
1616
1617
22.2k
  if (Shift == ARM_AM_ror && imm == 0)
1618
1.55k
    Shift = ARM_AM_rrx;
1619
1620
22.2k
  unsigned Op = Shift | (imm << 3);
1621
22.2k
  MCOperand_CreateImm0(Inst, (Op));
1622
1623
22.2k
  return S;
1624
22.2k
}
1625
1626
static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val,
1627
            uint64_t Address, const void *Decoder)
1628
7.72k
{
1629
7.72k
  DecodeStatus S = MCDisassembler_Success;
1630
1631
7.72k
  unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
1632
7.72k
  unsigned type = fieldFromInstruction_4(Val, 5, 2);
1633
7.72k
  unsigned Rs = fieldFromInstruction_4(Val, 8, 4);
1634
1635
  // Register-register
1636
7.72k
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1637
0
    return MCDisassembler_Fail;
1638
7.72k
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1639
0
    return MCDisassembler_Fail;
1640
1641
7.72k
  ARM_AM_ShiftOpc Shift = ARM_AM_lsl;
1642
7.72k
  switch (type) {
1643
2.63k
  case 0:
1644
2.63k
    Shift = ARM_AM_lsl;
1645
2.63k
    break;
1646
1.66k
  case 1:
1647
1.66k
    Shift = ARM_AM_lsr;
1648
1.66k
    break;
1649
1.93k
  case 2:
1650
1.93k
    Shift = ARM_AM_asr;
1651
1.93k
    break;
1652
1.50k
  case 3:
1653
1.50k
    Shift = ARM_AM_ror;
1654
1.50k
    break;
1655
7.72k
  }
1656
1657
7.72k
  MCOperand_CreateImm0(Inst, (Shift));
1658
1659
7.72k
  return S;
1660
7.72k
}
1661
1662
static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val,
1663
           uint64_t Address, const void *Decoder)
1664
41.0k
{
1665
41.0k
  DecodeStatus S = MCDisassembler_Success;
1666
1667
41.0k
  bool NeedDisjointWriteback = false;
1668
41.0k
  unsigned WritebackReg = 0;
1669
41.0k
  bool CLRM = false;
1670
41.0k
  switch (MCInst_getOpcode(Inst)) {
1671
37.5k
  default:
1672
37.5k
    break;
1673
37.5k
  case ARM_LDMIA_UPD:
1674
1.33k
  case ARM_LDMDB_UPD:
1675
1.77k
  case ARM_LDMIB_UPD:
1676
2.26k
  case ARM_LDMDA_UPD:
1677
2.52k
  case ARM_t2LDMIA_UPD:
1678
2.76k
  case ARM_t2LDMDB_UPD:
1679
2.85k
  case ARM_t2STMIA_UPD:
1680
3.25k
  case ARM_t2STMDB_UPD:
1681
3.25k
    NeedDisjointWriteback = true;
1682
3.25k
    WritebackReg = MCOperand_getReg(MCInst_getOperand(Inst, (0)));
1683
3.25k
    break;
1684
231
  case ARM_t2CLRM:
1685
231
    CLRM = true;
1686
231
    break;
1687
41.0k
  }
1688
1689
  // Empty register lists are not allowed.
1690
41.0k
  if (Val == 0)
1691
38
    return MCDisassembler_Fail;
1692
697k
  for (unsigned i = 0; i < 16; ++i) {
1693
656k
    if (Val & (1 << i)) {
1694
204k
      if (CLRM) {
1695
1.35k
        if (!Check(&S, DecodeCLRMGPRRegisterClass(
1696
1.35k
                   Inst, i, Address,
1697
1.35k
                   Decoder))) {
1698
0
          return MCDisassembler_Fail;
1699
0
        }
1700
203k
      } else {
1701
203k
        if (!Check(&S, DecodeGPRRegisterClass(Inst, i,
1702
203k
                      Address,
1703
203k
                      Decoder)))
1704
0
          return MCDisassembler_Fail;
1705
        // Writeback not allowed if Rn is in the target list.
1706
203k
        if (NeedDisjointWriteback &&
1707
203k
            WritebackReg ==
1708
20.3k
              MCOperand_getReg(&(
1709
20.3k
                Inst->Operands[Inst->size -
1710
20.3k
                   1])))
1711
894
          Check(&S, MCDisassembler_SoftFail);
1712
203k
      }
1713
204k
    }
1714
656k
  }
1715
1716
41.0k
  return S;
1717
41.0k
}
1718
1719
static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val,
1720
              uint64_t Address,
1721
              const void *Decoder)
1722
1.80k
{
1723
1.80k
  DecodeStatus S = MCDisassembler_Success;
1724
1725
1.80k
  unsigned Vd = fieldFromInstruction_4(Val, 8, 5);
1726
1.80k
  unsigned regs = fieldFromInstruction_4(Val, 0, 8);
1727
1728
  // In case of unpredictable encoding, tweak the operands.
1729
1.80k
  if (regs == 0 || (Vd + regs) > 32) {
1730
1.51k
    regs = Vd + regs > 32 ? 32 - Vd : regs;
1731
1.51k
    regs = regs > 1u ? regs : 1u;
1732
1.51k
    S = MCDisassembler_SoftFail;
1733
1.51k
  }
1734
1735
1.80k
  if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1736
0
    return MCDisassembler_Fail;
1737
30.8k
  for (unsigned i = 0; i < (regs - 1); ++i) {
1738
29.0k
    if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address,
1739
29.0k
                  Decoder)))
1740
0
      return MCDisassembler_Fail;
1741
29.0k
  }
1742
1743
1.80k
  return S;
1744
1.80k
}
1745
1746
static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val,
1747
              uint64_t Address,
1748
              const void *Decoder)
1749
1.54k
{
1750
1.54k
  DecodeStatus S = MCDisassembler_Success;
1751
1752
1.54k
  unsigned Vd = fieldFromInstruction_4(Val, 8, 5);
1753
1.54k
  unsigned regs = fieldFromInstruction_4(Val, 1, 7);
1754
1755
  // In case of unpredictable encoding, tweak the operands.
1756
1.54k
  if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1757
1.17k
    regs = Vd + regs > 32 ? 32 - Vd : regs;
1758
1.17k
    regs = regs > 1u ? regs : 1u;
1759
1.17k
    regs = regs < 16u ? regs : 16u;
1760
1.17k
    S = MCDisassembler_SoftFail;
1761
1.17k
  }
1762
1763
1.54k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1764
0
    return MCDisassembler_Fail;
1765
17.2k
  for (unsigned i = 0; i < (regs - 1); ++i) {
1766
15.6k
    if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address,
1767
15.6k
                  Decoder)))
1768
0
      return MCDisassembler_Fail;
1769
15.6k
  }
1770
1771
1.54k
  return S;
1772
1.54k
}
1773
1774
static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val,
1775
                uint64_t Address,
1776
                const void *Decoder)
1777
1.81k
{
1778
  // This operand encodes a mask of contiguous zeros between a specified MSB
1779
  // and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
1780
  // the mask of all bits LSB-and-lower, and then xor them to create
1781
  // the mask of that's all ones on [msb, lsb].  Finally we not it to
1782
  // create the final mask.
1783
1.81k
  unsigned msb = fieldFromInstruction_4(Val, 5, 5);
1784
1.81k
  unsigned lsb = fieldFromInstruction_4(Val, 0, 5);
1785
1786
1.81k
  DecodeStatus S = MCDisassembler_Success;
1787
1.81k
  if (lsb > msb) {
1788
1.01k
    Check(&S, MCDisassembler_SoftFail);
1789
    // The check above will cause the warning for the "potentially undefined
1790
    // instruction encoding" but we can't build a bad MCOperand value here
1791
    // with a lsb > msb or else printing the MCInst will cause a crash.
1792
1.01k
    lsb = msb;
1793
1.01k
  }
1794
1795
1.81k
  uint32_t msb_mask = 0xFFFFFFFF;
1796
1.81k
  if (msb != 31)
1797
1.65k
    msb_mask = (1U << (msb + 1)) - 1;
1798
1.81k
  uint32_t lsb_mask = (1U << lsb) - 1;
1799
1800
1.81k
  MCOperand_CreateImm0(Inst, (~(msb_mask ^ lsb_mask)));
1801
1.81k
  return S;
1802
1.81k
}
1803
1804
static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
1805
              uint64_t Address,
1806
              const void *Decoder)
1807
39.3k
{
1808
39.3k
  DecodeStatus S = MCDisassembler_Success;
1809
1810
39.3k
  unsigned P = fieldFromInstruction_4(Insn, 24, 1);
1811
39.3k
  unsigned W = fieldFromInstruction_4(Insn, 21, 1);
1812
39.3k
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1813
39.3k
  unsigned CRd = fieldFromInstruction_4(Insn, 12, 4);
1814
39.3k
  unsigned coproc = fieldFromInstruction_4(Insn, 8, 4);
1815
39.3k
  unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
1816
39.3k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1817
39.3k
  unsigned U = fieldFromInstruction_4(Insn, 23, 1);
1818
1819
  // Pre-Indexed implies writeback to Rn
1820
39.3k
  bool IsPreIndexed = (P == 1) && (W == 1);
1821
1822
39.3k
  switch (MCInst_getOpcode(Inst)) {
1823
277
  case ARM_LDC_OFFSET:
1824
546
  case ARM_LDC_PRE:
1825
1.57k
  case ARM_LDC_POST:
1826
1.96k
  case ARM_LDC_OPTION:
1827
2.56k
  case ARM_LDCL_OFFSET:
1828
3.32k
  case ARM_LDCL_PRE:
1829
4.25k
  case ARM_LDCL_POST:
1830
5.80k
  case ARM_LDCL_OPTION:
1831
6.69k
  case ARM_STC_OFFSET:
1832
7.09k
  case ARM_STC_PRE:
1833
7.72k
  case ARM_STC_POST:
1834
8.04k
  case ARM_STC_OPTION:
1835
8.36k
  case ARM_STCL_OFFSET:
1836
9.30k
  case ARM_STCL_PRE:
1837
9.63k
  case ARM_STCL_POST:
1838
9.85k
  case ARM_STCL_OPTION:
1839
10.3k
  case ARM_t2LDC_OFFSET:
1840
10.8k
  case ARM_t2LDC_PRE:
1841
11.4k
  case ARM_t2LDC_POST:
1842
11.6k
  case ARM_t2LDC_OPTION:
1843
11.9k
  case ARM_t2LDCL_OFFSET:
1844
12.9k
  case ARM_t2LDCL_PRE:
1845
13.5k
  case ARM_t2LDCL_POST:
1846
14.2k
  case ARM_t2LDCL_OPTION:
1847
15.2k
  case ARM_t2STC_OFFSET:
1848
16.7k
  case ARM_t2STC_PRE:
1849
17.4k
  case ARM_t2STC_POST:
1850
17.6k
  case ARM_t2STC_OPTION:
1851
18.0k
  case ARM_t2STCL_OFFSET:
1852
19.6k
  case ARM_t2STCL_PRE:
1853
20.7k
  case ARM_t2STCL_POST:
1854
20.9k
  case ARM_t2STCL_OPTION:
1855
22.0k
  case ARM_t2LDC2_OFFSET:
1856
22.6k
  case ARM_t2LDC2L_OFFSET:
1857
23.1k
  case ARM_t2LDC2_PRE:
1858
23.9k
  case ARM_t2LDC2L_PRE:
1859
26.1k
  case ARM_t2STC2_OFFSET:
1860
27.0k
  case ARM_t2STC2L_OFFSET:
1861
27.9k
  case ARM_t2STC2_PRE:
1862
28.5k
  case ARM_t2STC2L_PRE:
1863
28.6k
  case ARM_LDC2_OFFSET:
1864
28.9k
  case ARM_LDC2L_OFFSET:
1865
29.1k
  case ARM_LDC2_PRE:
1866
29.4k
  case ARM_LDC2L_PRE:
1867
29.8k
  case ARM_STC2_OFFSET:
1868
30.0k
  case ARM_STC2L_OFFSET:
1869
30.2k
  case ARM_STC2_PRE:
1870
30.5k
  case ARM_STC2L_PRE:
1871
31.2k
  case ARM_t2LDC2_OPTION:
1872
32.0k
  case ARM_t2STC2_OPTION:
1873
33.3k
  case ARM_t2LDC2_POST:
1874
34.2k
  case ARM_t2LDC2L_POST:
1875
35.3k
  case ARM_t2STC2_POST:
1876
36.9k
  case ARM_t2STC2L_POST:
1877
37.2k
  case ARM_LDC2_POST:
1878
37.9k
  case ARM_LDC2L_POST:
1879
38.2k
  case ARM_STC2_POST:
1880
38.5k
  case ARM_STC2L_POST:
1881
38.5k
    if (coproc == 0xA || coproc == 0xB ||
1882
38.5k
        (ARM_getFeatureBits(Inst->csh->mode,
1883
38.5k
          ARM_HasV8_1MMainlineOps) &&
1884
38.5k
         (coproc == 0x8 || coproc == 0x9 || coproc == 0xA ||
1885
54
          coproc == 0xB || coproc == 0xE || coproc == 0xF)))
1886
53
      return MCDisassembler_Fail;
1887
38.4k
    break;
1888
38.4k
  default:
1889
828
    break;
1890
39.3k
  }
1891
1892
39.3k
  if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && (coproc != 14))
1893
37
    return MCDisassembler_Fail;
1894
1895
39.2k
  if (IsPreIndexed)
1896
    // Dummy operand for Rn_wb.
1897
10.8k
    MCOperand_CreateImm0(Inst, (0));
1898
1899
39.2k
  MCOperand_CreateImm0(Inst, (coproc));
1900
39.2k
  MCOperand_CreateImm0(Inst, (CRd));
1901
39.2k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1902
0
    return MCDisassembler_Fail;
1903
1904
39.2k
  switch (MCInst_getOpcode(Inst)) {
1905
1.13k
  case ARM_t2LDC2_OFFSET:
1906
1.71k
  case ARM_t2LDC2L_OFFSET:
1907
2.18k
  case ARM_t2LDC2_PRE:
1908
3.01k
  case ARM_t2LDC2L_PRE:
1909
5.16k
  case ARM_t2STC2_OFFSET:
1910
6.07k
  case ARM_t2STC2L_OFFSET:
1911
6.99k
  case ARM_t2STC2_PRE:
1912
7.57k
  case ARM_t2STC2L_PRE:
1913
7.68k
  case ARM_LDC2_OFFSET:
1914
7.95k
  case ARM_LDC2L_OFFSET:
1915
8.18k
  case ARM_LDC2_PRE:
1916
8.48k
  case ARM_LDC2L_PRE:
1917
8.90k
  case ARM_STC2_OFFSET:
1918
9.10k
  case ARM_STC2L_OFFSET:
1919
9.33k
  case ARM_STC2_PRE:
1920
9.60k
  case ARM_STC2L_PRE:
1921
10.0k
  case ARM_t2LDC_OFFSET:
1922
10.3k
  case ARM_t2LDCL_OFFSET:
1923
10.8k
  case ARM_t2LDC_PRE:
1924
11.8k
  case ARM_t2LDCL_PRE:
1925
12.8k
  case ARM_t2STC_OFFSET:
1926
13.2k
  case ARM_t2STCL_OFFSET:
1927
14.7k
  case ARM_t2STC_PRE:
1928
16.3k
  case ARM_t2STCL_PRE:
1929
16.6k
  case ARM_LDC_OFFSET:
1930
17.2k
  case ARM_LDCL_OFFSET:
1931
17.4k
  case ARM_LDC_PRE:
1932
18.2k
  case ARM_LDCL_PRE:
1933
19.1k
  case ARM_STC_OFFSET:
1934
19.4k
  case ARM_STCL_OFFSET:
1935
19.8k
  case ARM_STC_PRE:
1936
20.7k
  case ARM_STCL_PRE:
1937
20.7k
    imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, imm);
1938
20.7k
    MCOperand_CreateImm0(Inst, (imm));
1939
20.7k
    break;
1940
1.30k
  case ARM_t2LDC2_POST:
1941
2.16k
  case ARM_t2LDC2L_POST:
1942
3.27k
  case ARM_t2STC2_POST:
1943
4.85k
  case ARM_t2STC2L_POST:
1944
5.11k
  case ARM_LDC2_POST:
1945
5.84k
  case ARM_LDC2L_POST:
1946
6.13k
  case ARM_STC2_POST:
1947
6.44k
  case ARM_STC2L_POST:
1948
7.01k
  case ARM_t2LDC_POST:
1949
7.66k
  case ARM_t2LDCL_POST:
1950
8.35k
  case ARM_t2STC_POST:
1951
9.39k
  case ARM_t2STCL_POST:
1952
10.4k
  case ARM_LDC_POST:
1953
11.3k
  case ARM_LDCL_POST:
1954
11.9k
  case ARM_STC_POST:
1955
12.3k
  case ARM_STCL_POST:
1956
12.3k
    imm |= U << 8;
1957
    // fall through
1958
18.5k
  default:
1959
    // The 'option' variant doesn't encode 'U' in the immediate since
1960
    // the immediate is unsigned [0,255].
1961
18.5k
    MCOperand_CreateImm0(Inst, (imm));
1962
18.5k
    break;
1963
39.2k
  }
1964
1965
39.2k
  switch (MCInst_getOpcode(Inst)) {
1966
277
  case ARM_LDC_OFFSET:
1967
545
  case ARM_LDC_PRE:
1968
1.57k
  case ARM_LDC_POST:
1969
1.96k
  case ARM_LDC_OPTION:
1970
2.55k
  case ARM_LDCL_OFFSET:
1971
3.30k
  case ARM_LDCL_PRE:
1972
4.23k
  case ARM_LDCL_POST:
1973
5.78k
  case ARM_LDCL_OPTION:
1974
6.66k
  case ARM_STC_OFFSET:
1975
7.06k
  case ARM_STC_PRE:
1976
7.69k
  case ARM_STC_POST:
1977
8.00k
  case ARM_STC_OPTION:
1978
8.33k
  case ARM_STCL_OFFSET:
1979
9.26k
  case ARM_STCL_PRE:
1980
9.59k
  case ARM_STCL_POST:
1981
9.81k
  case ARM_STCL_OPTION:
1982
9.81k
    if (!Check(&S, DecodePredicateOperand(Inst, pred, Address,
1983
9.81k
                  Decoder)))
1984
0
      return MCDisassembler_Fail;
1985
9.81k
    break;
1986
29.4k
  default:
1987
29.4k
    break;
1988
39.2k
  }
1989
1990
39.2k
  return S;
1991
39.2k
}
1992
1993
static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn,
1994
              uint64_t Address,
1995
              const void *Decoder)
1996
17.7k
{
1997
17.7k
  DecodeStatus S = MCDisassembler_Success;
1998
1999
17.7k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
2000
17.7k
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
2001
17.7k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
2002
17.7k
  unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
2003
17.7k
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2004
17.7k
  unsigned reg = fieldFromInstruction_4(Insn, 25, 1);
2005
17.7k
  unsigned P = fieldFromInstruction_4(Insn, 24, 1);
2006
17.7k
  unsigned W = fieldFromInstruction_4(Insn, 21, 1);
2007
2008
  // On stores, the writeback operand precedes Rt.
2009
17.7k
  switch (MCInst_getOpcode(Inst)) {
2010
2.42k
  case ARM_STR_POST_IMM:
2011
3.98k
  case ARM_STR_POST_REG:
2012
5.33k
  case ARM_STRB_POST_IMM:
2013
5.87k
  case ARM_STRB_POST_REG:
2014
6.93k
  case ARM_STRT_POST_REG:
2015
7.84k
  case ARM_STRT_POST_IMM:
2016
8.64k
  case ARM_STRBT_POST_REG:
2017
10.3k
  case ARM_STRBT_POST_IMM:
2018
10.3k
    if (!Check(&S,
2019
10.3k
         DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2020
0
      return MCDisassembler_Fail;
2021
10.3k
    break;
2022
10.3k
  default:
2023
7.44k
    break;
2024
17.7k
  }
2025
2026
17.7k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2027
0
    return MCDisassembler_Fail;
2028
2029
  // On loads, the writeback operand comes after Rt.
2030
17.7k
  switch (MCInst_getOpcode(Inst)) {
2031
1.99k
  case ARM_LDR_POST_IMM:
2032
2.57k
  case ARM_LDR_POST_REG:
2033
3.44k
  case ARM_LDRB_POST_IMM:
2034
4.04k
  case ARM_LDRB_POST_REG:
2035
4.98k
  case ARM_LDRBT_POST_REG:
2036
6.24k
  case ARM_LDRBT_POST_IMM:
2037
6.60k
  case ARM_LDRT_POST_REG:
2038
7.44k
  case ARM_LDRT_POST_IMM:
2039
7.44k
    if (!Check(&S,
2040
7.44k
         DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2041
0
      return MCDisassembler_Fail;
2042
7.44k
    break;
2043
10.3k
  default:
2044
10.3k
    break;
2045
17.7k
  }
2046
2047
17.7k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2048
0
    return MCDisassembler_Fail;
2049
2050
17.7k
  ARM_AM_AddrOpc Op = ARM_AM_add;
2051
17.7k
  if (!fieldFromInstruction_4(Insn, 23, 1))
2052
10.9k
    Op = ARM_AM_sub;
2053
2054
17.7k
  bool writeback = (P == 0) || (W == 1);
2055
17.7k
  unsigned idx_mode = 0;
2056
17.7k
  if (P && writeback)
2057
0
    idx_mode = ARMII_IndexModePre;
2058
17.7k
  else if (!P && writeback)
2059
17.7k
    idx_mode = ARMII_IndexModePost;
2060
2061
17.7k
  if (writeback && (Rn == 15 || Rn == Rt))
2062
2.98k
    S = MCDisassembler_SoftFail; // UNPREDICTABLE
2063
2064
17.7k
  if (reg) {
2065
6.42k
    if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address,
2066
6.42k
                Decoder)))
2067
0
      return MCDisassembler_Fail;
2068
6.42k
    ARM_AM_ShiftOpc Opc = ARM_AM_lsl;
2069
6.42k
    switch (fieldFromInstruction_4(Insn, 5, 2)) {
2070
2.43k
    case 0:
2071
2.43k
      Opc = ARM_AM_lsl;
2072
2.43k
      break;
2073
1.69k
    case 1:
2074
1.69k
      Opc = ARM_AM_lsr;
2075
1.69k
      break;
2076
750
    case 2:
2077
750
      Opc = ARM_AM_asr;
2078
750
      break;
2079
1.55k
    case 3:
2080
1.55k
      Opc = ARM_AM_ror;
2081
1.55k
      break;
2082
0
    default:
2083
0
      return MCDisassembler_Fail;
2084
6.42k
    }
2085
6.42k
    unsigned amt = fieldFromInstruction_4(Insn, 7, 5);
2086
6.42k
    if (Opc == ARM_AM_ror && amt == 0)
2087
394
      Opc = ARM_AM_rrx;
2088
6.42k
    unsigned imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode);
2089
2090
6.42k
    MCOperand_CreateImm0(Inst, (imm));
2091
11.3k
  } else {
2092
11.3k
    MCOperand_CreateReg0(Inst, (0));
2093
11.3k
    unsigned tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode);
2094
11.3k
    MCOperand_CreateImm0(Inst, (tmp));
2095
11.3k
  }
2096
2097
17.7k
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2098
1.84k
    return MCDisassembler_Fail;
2099
2100
15.9k
  return S;
2101
17.7k
}
2102
2103
static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val,
2104
            uint64_t Address, const void *Decoder)
2105
6.30k
{
2106
6.30k
  DecodeStatus S = MCDisassembler_Success;
2107
2108
6.30k
  unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
2109
6.30k
  unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
2110
6.30k
  unsigned type = fieldFromInstruction_4(Val, 5, 2);
2111
6.30k
  unsigned imm = fieldFromInstruction_4(Val, 7, 5);
2112
6.30k
  unsigned U = fieldFromInstruction_4(Val, 12, 1);
2113
2114
6.30k
  ARM_AM_ShiftOpc ShOp = ARM_AM_lsl;
2115
6.30k
  switch (type) {
2116
1.84k
  case 0:
2117
1.84k
    ShOp = ARM_AM_lsl;
2118
1.84k
    break;
2119
738
  case 1:
2120
738
    ShOp = ARM_AM_lsr;
2121
738
    break;
2122
1.81k
  case 2:
2123
1.81k
    ShOp = ARM_AM_asr;
2124
1.81k
    break;
2125
1.90k
  case 3:
2126
1.90k
    ShOp = ARM_AM_ror;
2127
1.90k
    break;
2128
6.30k
  }
2129
2130
6.30k
  if (ShOp == ARM_AM_ror && imm == 0)
2131
410
    ShOp = ARM_AM_rrx;
2132
2133
6.30k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2134
0
    return MCDisassembler_Fail;
2135
6.30k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2136
0
    return MCDisassembler_Fail;
2137
6.30k
  unsigned shift;
2138
6.30k
  if (U)
2139
2.77k
    shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0);
2140
3.53k
  else
2141
3.53k
    shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0);
2142
6.30k
  MCOperand_CreateImm0(Inst, (shift));
2143
2144
6.30k
  return S;
2145
6.30k
}
2146
2147
static DecodeStatus DecodeTSBInstruction(MCInst *Inst, unsigned Insn,
2148
           uint64_t Address, const void *Decoder)
2149
377
{
2150
377
  if (MCInst_getOpcode(Inst) != ARM_TSB &&
2151
377
      MCInst_getOpcode(Inst) != ARM_t2TSB)
2152
0
    return MCDisassembler_Fail;
2153
2154
  // The "csync" operand is not encoded into the "tsb" instruction (as this is
2155
  // the only available operand), but LLVM expects the instruction to have one
2156
  // operand, so we need to add the csync when decoding.
2157
377
  MCOperand_CreateImm0(Inst, (ARM_TSB_CSYNC));
2158
377
  return MCDisassembler_Success;
2159
377
}
2160
2161
static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn,
2162
                 uint64_t Address,
2163
                 const void *Decoder)
2164
16.6k
{
2165
16.6k
  DecodeStatus S = MCDisassembler_Success;
2166
2167
16.6k
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
2168
16.6k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
2169
16.6k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
2170
16.6k
  unsigned type = fieldFromInstruction_4(Insn, 22, 1);
2171
16.6k
  unsigned imm = fieldFromInstruction_4(Insn, 8, 4);
2172
16.6k
  unsigned U = ((~fieldFromInstruction_4(Insn, 23, 1)) & 1) << 8;
2173
16.6k
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2174
16.6k
  unsigned W = fieldFromInstruction_4(Insn, 21, 1);
2175
16.6k
  unsigned P = fieldFromInstruction_4(Insn, 24, 1);
2176
16.6k
  unsigned Rt2 = Rt + 1;
2177
2178
16.6k
  bool writeback = (W == 1) | (P == 0);
2179
2180
  // For {LD,ST}RD, Rt must be even, else undefined.
2181
16.6k
  switch (MCInst_getOpcode(Inst)) {
2182
657
  case ARM_STRD:
2183
1.47k
  case ARM_STRD_PRE:
2184
3.51k
  case ARM_STRD_POST:
2185
4.18k
  case ARM_LDRD:
2186
4.81k
  case ARM_LDRD_PRE:
2187
6.27k
  case ARM_LDRD_POST:
2188
6.27k
    if (Rt & 0x1)
2189
2.11k
      S = MCDisassembler_SoftFail;
2190
6.27k
    break;
2191
10.3k
  default:
2192
10.3k
    break;
2193
16.6k
  }
2194
16.6k
  switch (MCInst_getOpcode(Inst)) {
2195
657
  case ARM_STRD:
2196
1.47k
  case ARM_STRD_PRE:
2197
3.51k
  case ARM_STRD_POST:
2198
3.51k
    if (P == 0 && W == 1)
2199
0
      S = MCDisassembler_SoftFail;
2200
2201
3.51k
    if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2202
1.52k
      S = MCDisassembler_SoftFail;
2203
3.51k
    if (type && Rm == 15)
2204
172
      S = MCDisassembler_SoftFail;
2205
3.51k
    if (Rt2 == 15)
2206
129
      S = MCDisassembler_SoftFail;
2207
3.51k
    if (!type && fieldFromInstruction_4(Insn, 8, 4))
2208
1.90k
      S = MCDisassembler_SoftFail;
2209
3.51k
    break;
2210
687
  case ARM_STRH:
2211
1.15k
  case ARM_STRH_PRE:
2212
2.73k
  case ARM_STRH_POST:
2213
2.73k
    if (Rt == 15)
2214
264
      S = MCDisassembler_SoftFail;
2215
2.73k
    if (writeback && (Rn == 15 || Rn == Rt))
2216
697
      S = MCDisassembler_SoftFail;
2217
2.73k
    if (!type && Rm == 15)
2218
669
      S = MCDisassembler_SoftFail;
2219
2.73k
    break;
2220
668
  case ARM_LDRD:
2221
1.30k
  case ARM_LDRD_PRE:
2222
2.76k
  case ARM_LDRD_POST:
2223
2.76k
    if (type && Rn == 15) {
2224
242
      if (Rt2 == 15)
2225
75
        S = MCDisassembler_SoftFail;
2226
242
      break;
2227
242
    }
2228
2.52k
    if (P == 0 && W == 1)
2229
0
      S = MCDisassembler_SoftFail;
2230
2.52k
    if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2231
906
      S = MCDisassembler_SoftFail;
2232
2.52k
    if (!type && writeback && Rn == 15)
2233
108
      S = MCDisassembler_SoftFail;
2234
2.52k
    if (writeback && (Rn == Rt || Rn == Rt2))
2235
941
      S = MCDisassembler_SoftFail;
2236
2.52k
    break;
2237
997
  case ARM_LDRH:
2238
2.20k
  case ARM_LDRH_PRE:
2239
3.06k
  case ARM_LDRH_POST:
2240
3.06k
    if (type && Rn == 15) {
2241
409
      if (Rt == 15)
2242
95
        S = MCDisassembler_SoftFail;
2243
409
      break;
2244
409
    }
2245
2.65k
    if (Rt == 15)
2246
122
      S = MCDisassembler_SoftFail;
2247
2.65k
    if (!type && Rm == 15)
2248
393
      S = MCDisassembler_SoftFail;
2249
2.65k
    if (!type && writeback && (Rn == 15 || Rn == Rt))
2250
964
      S = MCDisassembler_SoftFail;
2251
2.65k
    break;
2252
298
  case ARM_LDRSH:
2253
1.02k
  case ARM_LDRSH_PRE:
2254
1.34k
  case ARM_LDRSH_POST:
2255
2.23k
  case ARM_LDRSB:
2256
2.82k
  case ARM_LDRSB_PRE:
2257
4.57k
  case ARM_LDRSB_POST:
2258
4.57k
    if (type && Rn == 15) {
2259
232
      if (Rt == 15)
2260
98
        S = MCDisassembler_SoftFail;
2261
232
      break;
2262
232
    }
2263
4.34k
    if (type && (Rt == 15 || (writeback && Rn == Rt)))
2264
373
      S = MCDisassembler_SoftFail;
2265
4.34k
    if (!type && (Rt == 15 || Rm == 15))
2266
641
      S = MCDisassembler_SoftFail;
2267
4.34k
    if (!type && writeback && (Rn == 15 || Rn == Rt))
2268
254
      S = MCDisassembler_SoftFail;
2269
4.34k
    break;
2270
0
  default:
2271
0
    break;
2272
16.6k
  }
2273
2274
16.6k
  if (writeback) { // Writeback
2275
12.4k
    if (P)
2276
4.44k
      U |= ARMII_IndexModePre << 9;
2277
8.01k
    else
2278
8.01k
      U |= ARMII_IndexModePost << 9;
2279
2280
    // On stores, the writeback operand precedes Rt.
2281
12.4k
    switch (MCInst_getOpcode(Inst)) {
2282
0
    case ARM_STRD:
2283
822
    case ARM_STRD_PRE:
2284
2.85k
    case ARM_STRD_POST:
2285
2.85k
    case ARM_STRH:
2286
3.32k
    case ARM_STRH_PRE:
2287
4.90k
    case ARM_STRH_POST:
2288
4.90k
      if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address,
2289
4.90k
                    Decoder)))
2290
0
        return MCDisassembler_Fail;
2291
4.90k
      break;
2292
7.55k
    default:
2293
7.55k
      break;
2294
12.4k
    }
2295
12.4k
  }
2296
2297
16.6k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2298
0
    return MCDisassembler_Fail;
2299
16.6k
  switch (MCInst_getOpcode(Inst)) {
2300
657
  case ARM_STRD:
2301
1.47k
  case ARM_STRD_PRE:
2302
3.51k
  case ARM_STRD_POST:
2303
4.18k
  case ARM_LDRD:
2304
4.81k
  case ARM_LDRD_PRE:
2305
6.27k
  case ARM_LDRD_POST:
2306
6.27k
    if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt + 1, Address,
2307
6.27k
                  Decoder)))
2308
13
      return MCDisassembler_Fail;
2309
6.26k
    break;
2310
10.3k
  default:
2311
10.3k
    break;
2312
16.6k
  }
2313
2314
16.6k
  if (writeback) {
2315
    // On loads, the writeback operand comes after Rt.
2316
12.4k
    switch (MCInst_getOpcode(Inst)) {
2317
0
    case ARM_LDRD:
2318
633
    case ARM_LDRD_PRE:
2319
2.09k
    case ARM_LDRD_POST:
2320
2.09k
    case ARM_LDRH:
2321
3.30k
    case ARM_LDRH_PRE:
2322
4.16k
    case ARM_LDRH_POST:
2323
4.16k
    case ARM_LDRSH:
2324
4.88k
    case ARM_LDRSH_PRE:
2325
5.20k
    case ARM_LDRSH_POST:
2326
5.20k
    case ARM_LDRSB:
2327
5.79k
    case ARM_LDRSB_PRE:
2328
7.54k
    case ARM_LDRSB_POST:
2329
7.54k
    case ARM_LDRHTr:
2330
7.54k
    case ARM_LDRSBTr:
2331
7.54k
      if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address,
2332
7.54k
                    Decoder)))
2333
0
        return MCDisassembler_Fail;
2334
7.54k
      break;
2335
7.54k
    default:
2336
4.89k
      break;
2337
12.4k
    }
2338
12.4k
  }
2339
2340
16.6k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2341
0
    return MCDisassembler_Fail;
2342
2343
16.6k
  if (type) {
2344
6.48k
    MCOperand_CreateReg0(Inst, (0));
2345
6.48k
    MCOperand_CreateImm0(Inst, (U | (imm << 4) | Rm));
2346
10.1k
  } else {
2347
10.1k
    if (!Check(&S,
2348
10.1k
         DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2349
0
      return MCDisassembler_Fail;
2350
10.1k
    MCOperand_CreateImm0(Inst, (U));
2351
10.1k
  }
2352
2353
16.6k
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2354
11
    return MCDisassembler_Fail;
2355
2356
16.6k
  return S;
2357
16.6k
}
2358
2359
static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn,
2360
           uint64_t Address, const void *Decoder)
2361
1.05k
{
2362
1.05k
  DecodeStatus S = MCDisassembler_Success;
2363
2364
1.05k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
2365
1.05k
  unsigned mode = fieldFromInstruction_4(Insn, 23, 2);
2366
2367
1.05k
  switch (mode) {
2368
312
  case 0:
2369
312
    mode = ARM_AM_da;
2370
312
    break;
2371
123
  case 1:
2372
123
    mode = ARM_AM_ia;
2373
123
    break;
2374
186
  case 2:
2375
186
    mode = ARM_AM_db;
2376
186
    break;
2377
432
  case 3:
2378
432
    mode = ARM_AM_ib;
2379
432
    break;
2380
1.05k
  }
2381
2382
1.05k
  MCOperand_CreateImm0(Inst, (mode));
2383
1.05k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2384
0
    return MCDisassembler_Fail;
2385
2386
1.05k
  return S;
2387
1.05k
}
2388
2389
static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn,
2390
            uint64_t Address, const void *Decoder)
2391
1.23k
{
2392
1.23k
  DecodeStatus S = MCDisassembler_Success;
2393
2394
1.23k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2395
1.23k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
2396
1.23k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
2397
1.23k
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2398
2399
1.23k
  if (pred == 0xF)
2400
724
    return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2401
2402
514
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2403
0
    return MCDisassembler_Fail;
2404
514
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2405
0
    return MCDisassembler_Fail;
2406
514
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2407
0
    return MCDisassembler_Fail;
2408
514
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2409
0
    return MCDisassembler_Fail;
2410
514
  return S;
2411
514
}
2412
2413
static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst,
2414
                unsigned Insn,
2415
                uint64_t Address,
2416
                const void *Decoder)
2417
8.91k
{
2418
8.91k
  DecodeStatus S = MCDisassembler_Success;
2419
2420
8.91k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
2421
8.91k
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2422
8.91k
  unsigned reglist = fieldFromInstruction_4(Insn, 0, 16);
2423
2424
8.91k
  if (pred == 0xF) {
2425
    // Ambiguous with RFE and SRS
2426
1.08k
    switch (MCInst_getOpcode(Inst)) {
2427
0
    case ARM_LDMDA:
2428
0
      MCInst_setOpcode(Inst, (ARM_RFEDA));
2429
0
      break;
2430
312
    case ARM_LDMDA_UPD:
2431
312
      MCInst_setOpcode(Inst, (ARM_RFEDA_UPD));
2432
312
      break;
2433
0
    case ARM_LDMDB:
2434
0
      MCInst_setOpcode(Inst, (ARM_RFEDB));
2435
0
      break;
2436
186
    case ARM_LDMDB_UPD:
2437
186
      MCInst_setOpcode(Inst, (ARM_RFEDB_UPD));
2438
186
      break;
2439
0
    case ARM_LDMIA:
2440
0
      MCInst_setOpcode(Inst, (ARM_RFEIA));
2441
0
      break;
2442
123
    case ARM_LDMIA_UPD:
2443
123
      MCInst_setOpcode(Inst, (ARM_RFEIA_UPD));
2444
123
      break;
2445
0
    case ARM_LDMIB:
2446
0
      MCInst_setOpcode(Inst, (ARM_RFEIB));
2447
0
      break;
2448
432
    case ARM_LDMIB_UPD:
2449
432
      MCInst_setOpcode(Inst, (ARM_RFEIB_UPD));
2450
432
      break;
2451
0
    case ARM_STMDA:
2452
0
      MCInst_setOpcode(Inst, (ARM_SRSDA));
2453
0
      break;
2454
3
    case ARM_STMDA_UPD:
2455
3
      MCInst_setOpcode(Inst, (ARM_SRSDA_UPD));
2456
3
      break;
2457
0
    case ARM_STMDB:
2458
0
      MCInst_setOpcode(Inst, (ARM_SRSDB));
2459
0
      break;
2460
3
    case ARM_STMDB_UPD:
2461
3
      MCInst_setOpcode(Inst, (ARM_SRSDB_UPD));
2462
3
      break;
2463
0
    case ARM_STMIA:
2464
0
      MCInst_setOpcode(Inst, (ARM_SRSIA));
2465
0
      break;
2466
6
    case ARM_STMIA_UPD:
2467
6
      MCInst_setOpcode(Inst, (ARM_SRSIA_UPD));
2468
6
      break;
2469
0
    case ARM_STMIB:
2470
0
      MCInst_setOpcode(Inst, (ARM_SRSIB));
2471
0
      break;
2472
1
    case ARM_STMIB_UPD:
2473
1
      MCInst_setOpcode(Inst, (ARM_SRSIB_UPD));
2474
1
      break;
2475
17
    default:
2476
17
      return MCDisassembler_Fail;
2477
1.08k
    }
2478
2479
    // For stores (which become SRS's, the only operand is the mode.
2480
1.06k
    if (fieldFromInstruction_4(Insn, 20, 1) == 0) {
2481
      // Check SRS encoding constraints
2482
13
      if (!(fieldFromInstruction_4(Insn, 22, 1) == 1 &&
2483
13
            fieldFromInstruction_4(Insn, 20, 1) == 0))
2484
13
        return MCDisassembler_Fail;
2485
2486
0
      MCOperand_CreateImm0(
2487
0
        Inst, (fieldFromInstruction_4(Insn, 0, 4)));
2488
0
      return S;
2489
13
    }
2490
2491
1.05k
    return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
2492
1.06k
  }
2493
2494
7.83k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2495
0
    return MCDisassembler_Fail;
2496
7.83k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2497
0
    return MCDisassembler_Fail; // Tied
2498
7.83k
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2499
0
    return MCDisassembler_Fail;
2500
7.83k
  if (!Check(&S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
2501
8
    return MCDisassembler_Fail;
2502
2503
7.82k
  return S;
2504
7.83k
}
2505
2506
// Check for UNPREDICTABLE predicated ESB instruction
2507
static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn,
2508
            uint64_t Address, const void *Decoder)
2509
1.39k
{
2510
1.39k
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2511
1.39k
  unsigned imm8 = fieldFromInstruction_4(Insn, 0, 8);
2512
2513
1.39k
  DecodeStatus S = MCDisassembler_Success;
2514
2515
1.39k
  MCOperand_CreateImm0(Inst, (imm8));
2516
2517
1.39k
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2518
134
    return MCDisassembler_Fail;
2519
2520
  // ESB is unpredictable if pred != AL. Without the RAS extension, it is a
2521
  // NOP, so all predicates should be allowed.
2522
1.25k
  if (imm8 == 0x10 && pred != 0xe &&
2523
1.25k
      ((ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureRAS)) != 0))
2524
0
    S = MCDisassembler_SoftFail;
2525
2526
1.25k
  return S;
2527
1.39k
}
2528
2529
static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn,
2530
           uint64_t Address, const void *Decoder)
2531
2.37k
{
2532
2.37k
  unsigned imod = fieldFromInstruction_4(Insn, 18, 2);
2533
2.37k
  unsigned M = fieldFromInstruction_4(Insn, 17, 1);
2534
2.37k
  unsigned iflags = fieldFromInstruction_4(Insn, 6, 3);
2535
2.37k
  unsigned mode = fieldFromInstruction_4(Insn, 0, 5);
2536
2537
2.37k
  DecodeStatus S = MCDisassembler_Success;
2538
2539
  // This decoder is called from multiple location that do not check
2540
  // the full encoding is valid before they do.
2541
2.37k
  if (fieldFromInstruction_4(Insn, 5, 1) != 0 ||
2542
2.37k
      fieldFromInstruction_4(Insn, 16, 1) != 0 ||
2543
2.37k
      fieldFromInstruction_4(Insn, 20, 8) != 0x10)
2544
9
    return MCDisassembler_Fail;
2545
2546
  // imod == '01' --> UNPREDICTABLE
2547
  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2548
  // return failure here.  The '01' imod value is unprintable, so there's
2549
  // nothing useful we could do even if we returned UNPREDICTABLE.
2550
2551
2.36k
  if (imod == 1)
2552
2
    return MCDisassembler_Fail;
2553
2554
2.36k
  if (imod && M) {
2555
262
    MCInst_setOpcode(Inst, (ARM_CPS3p));
2556
262
    MCOperand_CreateImm0(Inst, (imod));
2557
262
    MCOperand_CreateImm0(Inst, (iflags));
2558
262
    MCOperand_CreateImm0(Inst, (mode));
2559
2.09k
  } else if (imod && !M) {
2560
584
    MCInst_setOpcode(Inst, (ARM_CPS2p));
2561
584
    MCOperand_CreateImm0(Inst, (imod));
2562
584
    MCOperand_CreateImm0(Inst, (iflags));
2563
584
    if (mode)
2564
266
      S = MCDisassembler_SoftFail;
2565
1.51k
  } else if (!imod && M) {
2566
1.05k
    MCInst_setOpcode(Inst, (ARM_CPS1p));
2567
1.05k
    MCOperand_CreateImm0(Inst, (mode));
2568
1.05k
    if (iflags)
2569
982
      S = MCDisassembler_SoftFail;
2570
1.05k
  } else {
2571
    // imod == '00' && M == '0' --> UNPREDICTABLE
2572
465
    MCInst_setOpcode(Inst, (ARM_CPS1p));
2573
465
    MCOperand_CreateImm0(Inst, (mode));
2574
465
    S = MCDisassembler_SoftFail;
2575
465
  }
2576
2577
2.36k
  return S;
2578
2.36k
}
2579
2580
static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn,
2581
             uint64_t Address,
2582
             const void *Decoder)
2583
1.03k
{
2584
1.03k
  unsigned imod = fieldFromInstruction_4(Insn, 9, 2);
2585
1.03k
  unsigned M = fieldFromInstruction_4(Insn, 8, 1);
2586
1.03k
  unsigned iflags = fieldFromInstruction_4(Insn, 5, 3);
2587
1.03k
  unsigned mode = fieldFromInstruction_4(Insn, 0, 5);
2588
2589
1.03k
  DecodeStatus S = MCDisassembler_Success;
2590
2591
  // imod == '01' --> UNPREDICTABLE
2592
  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2593
  // return failure here.  The '01' imod value is unprintable, so there's
2594
  // nothing useful we could do even if we returned UNPREDICTABLE.
2595
2596
1.03k
  if (imod == 1)
2597
3
    return MCDisassembler_Fail;
2598
2599
1.03k
  if (imod && M) {
2600
117
    MCInst_setOpcode(Inst, (ARM_t2CPS3p));
2601
117
    MCOperand_CreateImm0(Inst, (imod));
2602
117
    MCOperand_CreateImm0(Inst, (iflags));
2603
117
    MCOperand_CreateImm0(Inst, (mode));
2604
918
  } else if (imod && !M) {
2605
440
    MCInst_setOpcode(Inst, (ARM_t2CPS2p));
2606
440
    MCOperand_CreateImm0(Inst, (imod));
2607
440
    MCOperand_CreateImm0(Inst, (iflags));
2608
440
    if (mode)
2609
0
      S = MCDisassembler_SoftFail;
2610
478
  } else if (!imod && M) {
2611
478
    MCInst_setOpcode(Inst, (ARM_t2CPS1p));
2612
478
    MCOperand_CreateImm0(Inst, (mode));
2613
478
    if (iflags)
2614
238
      S = MCDisassembler_SoftFail;
2615
478
  } else {
2616
    // imod == '00' && M == '0' --> this is a HINT instruction
2617
0
    int imm = fieldFromInstruction_4(Insn, 0, 8);
2618
    // HINT are defined only for immediate in [0..4]
2619
0
    if (imm > 4)
2620
0
      return MCDisassembler_Fail;
2621
0
    MCInst_setOpcode(Inst, (ARM_t2HINT));
2622
0
    MCOperand_CreateImm0(Inst, (imm));
2623
0
  }
2624
2625
1.03k
  return S;
2626
1.03k
}
2627
2628
static DecodeStatus DecodeT2HintSpaceInstruction(MCInst *Inst, unsigned Insn,
2629
             uint64_t Address,
2630
             const void *Decoder)
2631
1.36k
{
2632
1.36k
  unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
2633
2634
1.36k
  unsigned Opcode = ARM_t2HINT;
2635
2636
1.36k
  if (imm == 0x0D) {
2637
69
    Opcode = ARM_t2PACBTI;
2638
1.29k
  } else if (imm == 0x1D) {
2639
71
    Opcode = ARM_t2PAC;
2640
1.22k
  } else if (imm == 0x2D) {
2641
224
    Opcode = ARM_t2AUT;
2642
997
  } else if (imm == 0x0F) {
2643
261
    Opcode = ARM_t2BTI;
2644
261
  }
2645
2646
1.36k
  MCInst_setOpcode(Inst, (Opcode));
2647
1.36k
  if (Opcode == ARM_t2HINT) {
2648
736
    MCOperand_CreateImm0(Inst, (imm));
2649
736
  }
2650
2651
1.36k
  return MCDisassembler_Success;
2652
1.36k
}
2653
2654
static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn,
2655
               uint64_t Address,
2656
               const void *Decoder)
2657
1.57k
{
2658
1.57k
  DecodeStatus S = MCDisassembler_Success;
2659
2660
1.57k
  unsigned Rd = fieldFromInstruction_4(Insn, 8, 4);
2661
1.57k
  unsigned imm = 0;
2662
2663
1.57k
  imm |= (fieldFromInstruction_4(Insn, 0, 8) << 0);
2664
1.57k
  imm |= (fieldFromInstruction_4(Insn, 12, 3) << 8);
2665
1.57k
  imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12);
2666
1.57k
  imm |= (fieldFromInstruction_4(Insn, 26, 1) << 11);
2667
2668
1.57k
  if (MCInst_getOpcode(Inst) == ARM_t2MOVTi16)
2669
1.27k
    if (!Check(&S,
2670
1.27k
         DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2671
0
      return MCDisassembler_Fail;
2672
1.57k
  if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2673
0
    return MCDisassembler_Fail;
2674
2675
1.57k
  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2676
1.57k
    MCOperand_CreateImm0(Inst, (imm));
2677
2678
1.57k
  return S;
2679
1.57k
}
2680
2681
static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn,
2682
                uint64_t Address,
2683
                const void *Decoder)
2684
2.00k
{
2685
2.00k
  DecodeStatus S = MCDisassembler_Success;
2686
2687
2.00k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2688
2.00k
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2689
2.00k
  unsigned imm = 0;
2690
2691
2.00k
  imm |= (fieldFromInstruction_4(Insn, 0, 12) << 0);
2692
2.00k
  imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12);
2693
2694
2.00k
  if (MCInst_getOpcode(Inst) == ARM_MOVTi16)
2695
674
    if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address,
2696
674
                Decoder)))
2697
0
      return MCDisassembler_Fail;
2698
2699
2.00k
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2700
0
    return MCDisassembler_Fail;
2701
2702
2.00k
  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2703
2.00k
    MCOperand_CreateImm0(Inst, (imm));
2704
2705
2.00k
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2706
309
    return MCDisassembler_Fail;
2707
2708
1.69k
  return S;
2709
2.00k
}
2710
2711
static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn,
2712
            uint64_t Address, const void *Decoder)
2713
2.88k
{
2714
2.88k
  DecodeStatus S = MCDisassembler_Success;
2715
2716
2.88k
  unsigned Rd = fieldFromInstruction_4(Insn, 16, 4);
2717
2.88k
  unsigned Rn = fieldFromInstruction_4(Insn, 0, 4);
2718
2.88k
  unsigned Rm = fieldFromInstruction_4(Insn, 8, 4);
2719
2.88k
  unsigned Ra = fieldFromInstruction_4(Insn, 12, 4);
2720
2.88k
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2721
2722
2.88k
  if (pred == 0xF)
2723
807
    return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2724
2725
2.07k
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2726
0
    return MCDisassembler_Fail;
2727
2.07k
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2728
0
    return MCDisassembler_Fail;
2729
2.07k
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2730
0
    return MCDisassembler_Fail;
2731
2.07k
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2732
0
    return MCDisassembler_Fail;
2733
2734
2.07k
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2735
0
    return MCDisassembler_Fail;
2736
2737
2.07k
  return S;
2738
2.07k
}
2739
2740
static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn,
2741
           uint64_t Address, const void *Decoder)
2742
1.08k
{
2743
1.08k
  DecodeStatus S = MCDisassembler_Success;
2744
2745
1.08k
  unsigned Pred = fieldFromInstruction_4(Insn, 28, 4);
2746
1.08k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
2747
1.08k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
2748
2749
1.08k
  if (Pred == 0xF)
2750
771
    return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2751
2752
318
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2753
0
    return MCDisassembler_Fail;
2754
318
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2755
0
    return MCDisassembler_Fail;
2756
318
  if (!Check(&S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2757
0
    return MCDisassembler_Fail;
2758
2759
318
  return S;
2760
318
}
2761
2762
static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn,
2763
              uint64_t Address,
2764
              const void *Decoder)
2765
771
{
2766
771
  DecodeStatus S = MCDisassembler_Success;
2767
2768
771
  unsigned Imm = fieldFromInstruction_4(Insn, 9, 1);
2769
2770
771
  if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1aOps) ||
2771
771
      !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops))
2772
2
    return MCDisassembler_Fail;
2773
2774
  // Decoder can be called from DecodeTST, which does not check the full
2775
  // encoding is valid.
2776
769
  if (fieldFromInstruction_4(Insn, 20, 12) != 0xf11 ||
2777
769
      fieldFromInstruction_4(Insn, 4, 4) != 0)
2778
0
    return MCDisassembler_Fail;
2779
769
  if (fieldFromInstruction_4(Insn, 10, 10) != 0 ||
2780
769
      fieldFromInstruction_4(Insn, 0, 4) != 0)
2781
718
    S = MCDisassembler_SoftFail;
2782
2783
769
  MCInst_setOpcode(Inst, (ARM_SETPAN));
2784
769
  MCOperand_CreateImm0(Inst, (Imm));
2785
2786
769
  return S;
2787
769
}
2788
2789
static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val,
2790
                 uint64_t Address,
2791
                 const void *Decoder)
2792
7.08k
{
2793
7.08k
  DecodeStatus S = MCDisassembler_Success;
2794
2795
7.08k
  unsigned add = fieldFromInstruction_4(Val, 12, 1);
2796
7.08k
  unsigned imm = fieldFromInstruction_4(Val, 0, 12);
2797
7.08k
  unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
2798
2799
7.08k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2800
0
    return MCDisassembler_Fail;
2801
2802
7.08k
  if (!add)
2803
4.40k
    imm *= -1;
2804
7.08k
  if (imm == 0 && !add)
2805
447
    imm = INT32_MIN;
2806
7.08k
  MCOperand_CreateImm0(Inst, (imm));
2807
7.08k
  if (Rn == 15)
2808
473
    tryAddingPcLoadReferenceComment(Address, Address + imm + 8,
2809
473
            Decoder);
2810
2811
7.08k
  return S;
2812
7.08k
}
2813
2814
static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val,
2815
             uint64_t Address,
2816
             const void *Decoder)
2817
1.08k
{
2818
1.08k
  DecodeStatus S = MCDisassembler_Success;
2819
2820
1.08k
  unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
2821
  // U == 1 to add imm, 0 to subtract it.
2822
1.08k
  unsigned U = fieldFromInstruction_4(Val, 8, 1);
2823
1.08k
  unsigned imm = fieldFromInstruction_4(Val, 0, 8);
2824
2825
1.08k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2826
0
    return MCDisassembler_Fail;
2827
2828
1.08k
  if (U)
2829
393
    MCOperand_CreateImm0(Inst, (ARM_AM_getAM5Opc(ARM_AM_add, imm)));
2830
692
  else
2831
692
    MCOperand_CreateImm0(Inst, (ARM_AM_getAM5Opc(ARM_AM_sub, imm)));
2832
2833
1.08k
  return S;
2834
1.08k
}
2835
2836
static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val,
2837
                 uint64_t Address,
2838
                 const void *Decoder)
2839
1.05k
{
2840
1.05k
  DecodeStatus S = MCDisassembler_Success;
2841
2842
1.05k
  unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
2843
  // U == 1 to add imm, 0 to subtract it.
2844
1.05k
  unsigned U = fieldFromInstruction_4(Val, 8, 1);
2845
1.05k
  unsigned imm = fieldFromInstruction_4(Val, 0, 8);
2846
2847
1.05k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2848
0
    return MCDisassembler_Fail;
2849
2850
1.05k
  if (U)
2851
493
    MCOperand_CreateImm0(Inst,
2852
493
             (ARM_AM_getAM5FP16Opc(ARM_AM_add, imm)));
2853
560
  else
2854
560
    MCOperand_CreateImm0(Inst,
2855
560
             (ARM_AM_getAM5FP16Opc(ARM_AM_sub, imm)));
2856
2857
1.05k
  return S;
2858
1.05k
}
2859
2860
static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val,
2861
             uint64_t Address,
2862
             const void *Decoder)
2863
8.18k
{
2864
8.18k
  return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2865
8.18k
}
2866
2867
static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn,
2868
           uint64_t Address, const void *Decoder)
2869
1.16k
{
2870
1.16k
  DecodeStatus Status = MCDisassembler_Success;
2871
2872
  // Note the J1 and J2 values are from the encoded instruction.  So here
2873
  // change them to I1 and I2 values via as documented:
2874
  // I1 = NOT(J1 EOR S);
2875
  // I2 = NOT(J2 EOR S);
2876
  // and build the imm32 with one trailing zero as documented:
2877
  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2878
1.16k
  unsigned S = fieldFromInstruction_4(Insn, 26, 1);
2879
1.16k
  unsigned J1 = fieldFromInstruction_4(Insn, 13, 1);
2880
1.16k
  unsigned J2 = fieldFromInstruction_4(Insn, 11, 1);
2881
1.16k
  unsigned I1 = !(J1 ^ S);
2882
1.16k
  unsigned I2 = !(J2 ^ S);
2883
1.16k
  unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10);
2884
1.16k
  unsigned imm11 = fieldFromInstruction_4(Insn, 0, 11);
2885
1.16k
  unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) |
2886
1.16k
           imm11;
2887
1.16k
  int imm32 = SignExtend32((tmp << 1), 25);
2888
1.16k
  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, true, 4,
2889
1.16k
              Inst, Decoder))
2890
1.16k
    MCOperand_CreateImm0(Inst, (imm32));
2891
2892
1.16k
  return Status;
2893
1.16k
}
2894
2895
static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn,
2896
                 uint64_t Address,
2897
                 const void *Decoder)
2898
5.07k
{
2899
5.07k
  DecodeStatus S = MCDisassembler_Success;
2900
2901
5.07k
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2902
5.07k
  unsigned imm = fieldFromInstruction_4(Insn, 0, 24) << 2;
2903
2904
5.07k
  if (pred == 0xF) {
2905
565
    MCInst_setOpcode(Inst, (ARM_BLXi));
2906
565
    imm |= fieldFromInstruction_4(Insn, 24, 1) << 1;
2907
565
    if (!tryAddingSymbolicOperand(
2908
565
          Address, Address + SignExtend32((imm), 26) + 8,
2909
565
          true, 4, Inst, Decoder))
2910
565
      MCOperand_CreateImm0(Inst, (SignExtend32((imm), 26)));
2911
565
    return S;
2912
565
  }
2913
2914
4.50k
  if (!tryAddingSymbolicOperand(Address,
2915
4.50k
              Address + SignExtend32((imm), 26) + 8,
2916
4.50k
              true, 4, Inst, Decoder))
2917
4.50k
    MCOperand_CreateImm0(Inst, (SignExtend32((imm), 26)));
2918
2919
  // We already have BL_pred for BL w/ predicate, no need to add addition
2920
  // predicate opreands for BL
2921
4.50k
  if (MCInst_getOpcode(Inst) != ARM_BL)
2922
4.24k
    if (!Check(&S, DecodePredicateOperand(Inst, pred, Address,
2923
4.24k
                  Decoder)))
2924
0
      return MCDisassembler_Fail;
2925
2926
4.50k
  return S;
2927
4.50k
}
2928
2929
static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val,
2930
             uint64_t Address,
2931
             const void *Decoder)
2932
47.0k
{
2933
47.0k
  DecodeStatus S = MCDisassembler_Success;
2934
2935
47.0k
  unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
2936
47.0k
  unsigned align = fieldFromInstruction_4(Val, 4, 2);
2937
2938
47.0k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2939
0
    return MCDisassembler_Fail;
2940
47.0k
  if (!align)
2941
26.7k
    MCOperand_CreateImm0(Inst, (0));
2942
20.3k
  else
2943
20.3k
    MCOperand_CreateImm0(Inst, (4 << align));
2944
2945
47.0k
  return S;
2946
47.0k
}
2947
2948
static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn,
2949
           uint64_t Address, const void *Decoder)
2950
15.9k
{
2951
15.9k
  DecodeStatus S = MCDisassembler_Success;
2952
2953
15.9k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2954
15.9k
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
2955
15.9k
  unsigned wb = fieldFromInstruction_4(Insn, 16, 4);
2956
15.9k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
2957
15.9k
  Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4;
2958
15.9k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
2959
2960
  // First output register
2961
15.9k
  switch (MCInst_getOpcode(Inst)) {
2962
99
  case ARM_VLD1q16:
2963
166
  case ARM_VLD1q32:
2964
247
  case ARM_VLD1q64:
2965
452
  case ARM_VLD1q8:
2966
529
  case ARM_VLD1q16wb_fixed:
2967
648
  case ARM_VLD1q16wb_register:
2968
1.08k
  case ARM_VLD1q32wb_fixed:
2969
1.21k
  case ARM_VLD1q32wb_register:
2970
1.42k
  case ARM_VLD1q64wb_fixed:
2971
1.51k
  case ARM_VLD1q64wb_register:
2972
1.73k
  case ARM_VLD1q8wb_fixed:
2973
1.95k
  case ARM_VLD1q8wb_register:
2974
2.26k
  case ARM_VLD2d16:
2975
2.33k
  case ARM_VLD2d32:
2976
2.43k
  case ARM_VLD2d8:
2977
2.58k
  case ARM_VLD2d16wb_fixed:
2978
2.69k
  case ARM_VLD2d16wb_register:
2979
2.77k
  case ARM_VLD2d32wb_fixed:
2980
3.03k
  case ARM_VLD2d32wb_register:
2981
3.30k
  case ARM_VLD2d8wb_fixed:
2982
3.46k
  case ARM_VLD2d8wb_register:
2983
3.46k
    if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address,
2984
3.46k
              Decoder)))
2985
2
      return MCDisassembler_Fail;
2986
3.46k
    break;
2987
3.46k
  case ARM_VLD2b16:
2988
258
  case ARM_VLD2b32:
2989
366
  case ARM_VLD2b8:
2990
440
  case ARM_VLD2b16wb_fixed:
2991
528
  case ARM_VLD2b16wb_register:
2992
730
  case ARM_VLD2b32wb_fixed:
2993
1.07k
  case ARM_VLD2b32wb_register:
2994
1.18k
  case ARM_VLD2b8wb_fixed:
2995
1.60k
  case ARM_VLD2b8wb_register:
2996
1.60k
    if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address,
2997
1.60k
                    Decoder)))
2998
5
      return MCDisassembler_Fail;
2999
1.59k
    break;
3000
10.9k
  default:
3001
10.9k
    if (!Check(&S,
3002
10.9k
         DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3003
0
      return MCDisassembler_Fail;
3004
15.9k
  }
3005
3006
  // Second output register
3007
15.9k
  switch (MCInst_getOpcode(Inst)) {
3008
73
  case ARM_VLD3d8:
3009
161
  case ARM_VLD3d16:
3010
388
  case ARM_VLD3d32:
3011
823
  case ARM_VLD3d8_UPD:
3012
920
  case ARM_VLD3d16_UPD:
3013
1.13k
  case ARM_VLD3d32_UPD:
3014
1.25k
  case ARM_VLD4d8:
3015
1.48k
  case ARM_VLD4d16:
3016
1.70k
  case ARM_VLD4d32:
3017
2.25k
  case ARM_VLD4d8_UPD:
3018
2.42k
  case ARM_VLD4d16_UPD:
3019
2.84k
  case ARM_VLD4d32_UPD:
3020
2.84k
    if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32,
3021
2.84k
                  Address, Decoder)))
3022
0
      return MCDisassembler_Fail;
3023
2.84k
    break;
3024
2.84k
  case ARM_VLD3q8:
3025
439
  case ARM_VLD3q16:
3026
692
  case ARM_VLD3q32:
3027
782
  case ARM_VLD3q8_UPD:
3028
915
  case ARM_VLD3q16_UPD:
3029
1.09k
  case ARM_VLD3q32_UPD:
3030
1.17k
  case ARM_VLD4q8:
3031
1.60k
  case ARM_VLD4q16:
3032
1.80k
  case ARM_VLD4q32:
3033
2.20k
  case ARM_VLD4q8_UPD:
3034
2.55k
  case ARM_VLD4q16_UPD:
3035
2.87k
  case ARM_VLD4q32_UPD:
3036
2.87k
    if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32,
3037
2.87k
                  Address, Decoder)))
3038
0
      return MCDisassembler_Fail;
3039
2.87k
    break;
3040
10.2k
  default:
3041
10.2k
    break;
3042
15.9k
  }
3043
3044
  // Third output register
3045
15.9k
  switch (MCInst_getOpcode(Inst)) {
3046
73
  case ARM_VLD3d8:
3047
161
  case ARM_VLD3d16:
3048
388
  case ARM_VLD3d32:
3049
823
  case ARM_VLD3d8_UPD:
3050
920
  case ARM_VLD3d16_UPD:
3051
1.13k
  case ARM_VLD3d32_UPD:
3052
1.25k
  case ARM_VLD4d8:
3053
1.48k
  case ARM_VLD4d16:
3054
1.70k
  case ARM_VLD4d32:
3055
2.25k
  case ARM_VLD4d8_UPD:
3056
2.42k
  case ARM_VLD4d16_UPD:
3057
2.84k
  case ARM_VLD4d32_UPD:
3058
2.84k
    if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32,
3059
2.84k
                  Address, Decoder)))
3060
0
      return MCDisassembler_Fail;
3061
2.84k
    break;
3062
2.84k
  case ARM_VLD3q8:
3063
439
  case ARM_VLD3q16:
3064
692
  case ARM_VLD3q32:
3065
782
  case ARM_VLD3q8_UPD:
3066
915
  case ARM_VLD3q16_UPD:
3067
1.09k
  case ARM_VLD3q32_UPD:
3068
1.17k
  case ARM_VLD4q8:
3069
1.60k
  case ARM_VLD4q16:
3070
1.80k
  case ARM_VLD4q32:
3071
2.20k
  case ARM_VLD4q8_UPD:
3072
2.55k
  case ARM_VLD4q16_UPD:
3073
2.87k
  case ARM_VLD4q32_UPD:
3074
2.87k
    if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32,
3075
2.87k
                  Address, Decoder)))
3076
0
      return MCDisassembler_Fail;
3077
2.87k
    break;
3078
10.2k
  default:
3079
10.2k
    break;
3080
15.9k
  }
3081
3082
  // Fourth output register
3083
15.9k
  switch (MCInst_getOpcode(Inst)) {
3084
120
  case ARM_VLD4d8:
3085
353
  case ARM_VLD4d16:
3086
567
  case ARM_VLD4d32:
3087
1.11k
  case ARM_VLD4d8_UPD:
3088
1.28k
  case ARM_VLD4d16_UPD:
3089
1.71k
  case ARM_VLD4d32_UPD:
3090
1.71k
    if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32,
3091
1.71k
                  Address, Decoder)))
3092
0
      return MCDisassembler_Fail;
3093
1.71k
    break;
3094
1.71k
  case ARM_VLD4q8:
3095
503
  case ARM_VLD4q16:
3096
707
  case ARM_VLD4q32:
3097
1.10k
  case ARM_VLD4q8_UPD:
3098
1.45k
  case ARM_VLD4q16_UPD:
3099
1.77k
  case ARM_VLD4q32_UPD:
3100
1.77k
    if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32,
3101
1.77k
                  Address, Decoder)))
3102
0
      return MCDisassembler_Fail;
3103
1.77k
    break;
3104
12.5k
  default:
3105
12.5k
    break;
3106
15.9k
  }
3107
3108
  // Writeback operand
3109
15.9k
  switch (MCInst_getOpcode(Inst)) {
3110
323
  case ARM_VLD1d8wb_fixed:
3111
601
  case ARM_VLD1d16wb_fixed:
3112
828
  case ARM_VLD1d32wb_fixed:
3113
908
  case ARM_VLD1d64wb_fixed:
3114
1.19k
  case ARM_VLD1d8wb_register:
3115
1.40k
  case ARM_VLD1d16wb_register:
3116
1.50k
  case ARM_VLD1d32wb_register:
3117
1.58k
  case ARM_VLD1d64wb_register:
3118
1.81k
  case ARM_VLD1q8wb_fixed:
3119
1.88k
  case ARM_VLD1q16wb_fixed:
3120
2.32k
  case ARM_VLD1q32wb_fixed:
3121
2.53k
  case ARM_VLD1q64wb_fixed:
3122
2.75k
  case ARM_VLD1q8wb_register:
3123
2.87k
  case ARM_VLD1q16wb_register:
3124
3.00k
  case ARM_VLD1q32wb_register:
3125
3.08k
  case ARM_VLD1q64wb_register:
3126
3.29k
  case ARM_VLD1d8Twb_fixed:
3127
3.37k
  case ARM_VLD1d8Twb_register:
3128
3.44k
  case ARM_VLD1d16Twb_fixed:
3129
3.52k
  case ARM_VLD1d16Twb_register:
3130
3.64k
  case ARM_VLD1d32Twb_fixed:
3131
3.86k
  case ARM_VLD1d32Twb_register:
3132
3.94k
  case ARM_VLD1d64Twb_fixed:
3133
4.15k
  case ARM_VLD1d64Twb_register:
3134
4.30k
  case ARM_VLD1d8Qwb_fixed:
3135
4.59k
  case ARM_VLD1d8Qwb_register:
3136
4.80k
  case ARM_VLD1d16Qwb_fixed:
3137
5.03k
  case ARM_VLD1d16Qwb_register:
3138
5.11k
  case ARM_VLD1d32Qwb_fixed:
3139
5.32k
  case ARM_VLD1d32Qwb_register:
3140
5.53k
  case ARM_VLD1d64Qwb_fixed:
3141
5.60k
  case ARM_VLD1d64Qwb_register:
3142
5.87k
  case ARM_VLD2d8wb_fixed:
3143
6.02k
  case ARM_VLD2d16wb_fixed:
3144
6.10k
  case ARM_VLD2d32wb_fixed:
3145
6.19k
  case ARM_VLD2q8wb_fixed:
3146
6.43k
  case ARM_VLD2q16wb_fixed:
3147
6.50k
  case ARM_VLD2q32wb_fixed:
3148
6.66k
  case ARM_VLD2d8wb_register:
3149
6.78k
  case ARM_VLD2d16wb_register:
3150
7.03k
  case ARM_VLD2d32wb_register:
3151
7.35k
  case ARM_VLD2q8wb_register:
3152
7.48k
  case ARM_VLD2q16wb_register:
3153
7.57k
  case ARM_VLD2q32wb_register:
3154
7.67k
  case ARM_VLD2b8wb_fixed:
3155
7.75k
  case ARM_VLD2b16wb_fixed:
3156
7.95k
  case ARM_VLD2b32wb_fixed:
3157
8.37k
  case ARM_VLD2b8wb_register:
3158
8.45k
  case ARM_VLD2b16wb_register:
3159
8.80k
  case ARM_VLD2b32wb_register:
3160
8.80k
    MCOperand_CreateImm0(Inst, (0));
3161
8.80k
    break;
3162
435
  case ARM_VLD3d8_UPD:
3163
532
  case ARM_VLD3d16_UPD:
3164
748
  case ARM_VLD3d32_UPD:
3165
838
  case ARM_VLD3q8_UPD:
3166
971
  case ARM_VLD3q16_UPD:
3167
1.15k
  case ARM_VLD3q32_UPD:
3168
1.70k
  case ARM_VLD4d8_UPD:
3169
1.87k
  case ARM_VLD4d16_UPD:
3170
2.29k
  case ARM_VLD4d32_UPD:
3171
2.69k
  case ARM_VLD4q8_UPD:
3172
3.04k
  case ARM_VLD4q16_UPD:
3173
3.36k
  case ARM_VLD4q32_UPD:
3174
3.36k
    if (!Check(&S,
3175
3.36k
         DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3176
0
      return MCDisassembler_Fail;
3177
3.36k
    break;
3178
3.82k
  default:
3179
3.82k
    break;
3180
15.9k
  }
3181
3182
  // AddrMode6 Base (register+alignment)
3183
15.9k
  if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3184
0
    return MCDisassembler_Fail;
3185
3186
  // AddrMode6 Offset (register)
3187
15.9k
  switch (MCInst_getOpcode(Inst)) {
3188
10.4k
  default:
3189
    // The below have been updated to have explicit am6offset split
3190
    // between fixed and register offset. For those instructions not
3191
    // yet updated, we need to add an additional reg0 operand for the
3192
    // fixed variant.
3193
    //
3194
    // The fixed offset encodes as Rm == 0xd, so we check for that.
3195
10.4k
    if (Rm == 0xd) {
3196
675
      MCOperand_CreateReg0(Inst, (0));
3197
675
      break;
3198
675
    }
3199
    // Fall through to handle the register offset variant.
3200
    // fall through
3201
10.1k
  case ARM_VLD1d8wb_fixed:
3202
10.4k
  case ARM_VLD1d16wb_fixed:
3203
10.6k
  case ARM_VLD1d32wb_fixed:
3204
10.7k
  case ARM_VLD1d64wb_fixed:
3205
10.9k
  case ARM_VLD1d8Twb_fixed:
3206
11.0k
  case ARM_VLD1d16Twb_fixed:
3207
11.1k
  case ARM_VLD1d32Twb_fixed:
3208
11.2k
  case ARM_VLD1d64Twb_fixed:
3209
11.3k
  case ARM_VLD1d8Qwb_fixed:
3210
11.5k
  case ARM_VLD1d16Qwb_fixed:
3211
11.6k
  case ARM_VLD1d32Qwb_fixed:
3212
11.8k
  case ARM_VLD1d64Qwb_fixed:
3213
12.1k
  case ARM_VLD1d8wb_register:
3214
12.3k
  case ARM_VLD1d16wb_register:
3215
12.4k
  case ARM_VLD1d32wb_register:
3216
12.5k
  case ARM_VLD1d64wb_register:
3217
12.7k
  case ARM_VLD1q8wb_fixed:
3218
12.8k
  case ARM_VLD1q16wb_fixed:
3219
13.2k
  case ARM_VLD1q32wb_fixed:
3220
13.4k
  case ARM_VLD1q64wb_fixed:
3221
13.6k
  case ARM_VLD1q8wb_register:
3222
13.8k
  case ARM_VLD1q16wb_register:
3223
13.9k
  case ARM_VLD1q32wb_register:
3224
14.0k
  case ARM_VLD1q64wb_register:
3225
    // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3226
    // variant encodes Rm == 0xf. Anything else is a register offset post-
3227
    // increment and we need to add the register operand to the instruction.
3228
14.0k
    if (Rm != 0xD && Rm != 0xF &&
3229
14.0k
        !Check(&S,
3230
7.21k
         DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3231
0
      return MCDisassembler_Fail;
3232
14.0k
    break;
3233
14.0k
  case ARM_VLD2d8wb_fixed:
3234
420
  case ARM_VLD2d16wb_fixed:
3235
502
  case ARM_VLD2d32wb_fixed:
3236
608
  case ARM_VLD2b8wb_fixed:
3237
682
  case ARM_VLD2b16wb_fixed:
3238
884
  case ARM_VLD2b32wb_fixed:
3239
970
  case ARM_VLD2q8wb_fixed:
3240
1.21k
  case ARM_VLD2q16wb_fixed:
3241
1.28k
  case ARM_VLD2q32wb_fixed:
3242
1.28k
    break;
3243
15.9k
  }
3244
3245
15.9k
  return S;
3246
15.9k
}
3247
3248
static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn,
3249
              uint64_t Address,
3250
              const void *Decoder)
3251
17.1k
{
3252
17.1k
  unsigned type = fieldFromInstruction_4(Insn, 8, 4);
3253
17.1k
  unsigned align = fieldFromInstruction_4(Insn, 4, 2);
3254
17.1k
  if (type == 6 && (align & 2))
3255
3
    return MCDisassembler_Fail;
3256
17.1k
  if (type == 7 && (align & 2))
3257
0
    return MCDisassembler_Fail;
3258
17.1k
  if (type == 10 && align == 3)
3259
2
    return MCDisassembler_Fail;
3260
3261
17.1k
  unsigned load = fieldFromInstruction_4(Insn, 21, 1);
3262
17.1k
  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) :
3263
17.1k
          DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3264
17.1k
}
3265
3266
static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn,
3267
              uint64_t Address,
3268
              const void *Decoder)
3269
12.7k
{
3270
12.7k
  unsigned size = fieldFromInstruction_4(Insn, 6, 2);
3271
12.7k
  if (size == 3)
3272
0
    return MCDisassembler_Fail;
3273
3274
12.7k
  unsigned type = fieldFromInstruction_4(Insn, 8, 4);
3275
12.7k
  unsigned align = fieldFromInstruction_4(Insn, 4, 2);
3276
12.7k
  if (type == 8 && align == 3)
3277
3
    return MCDisassembler_Fail;
3278
12.7k
  if (type == 9 && align == 3)
3279
1
    return MCDisassembler_Fail;
3280
3281
12.7k
  unsigned load = fieldFromInstruction_4(Insn, 21, 1);
3282
12.7k
  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) :
3283
12.7k
          DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3284
12.7k
}
3285
3286
static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn,
3287
              uint64_t Address,
3288
              const void *Decoder)
3289
8.14k
{
3290
8.14k
  unsigned size = fieldFromInstruction_4(Insn, 6, 2);
3291
8.14k
  if (size == 3)
3292
0
    return MCDisassembler_Fail;
3293
3294
8.14k
  unsigned align = fieldFromInstruction_4(Insn, 4, 2);
3295
8.14k
  if (align & 2)
3296
0
    return MCDisassembler_Fail;
3297
3298
8.14k
  unsigned load = fieldFromInstruction_4(Insn, 21, 1);
3299
8.14k
  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) :
3300
8.14k
          DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3301
8.14k
}
3302
3303
static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Insn,
3304
              uint64_t Address,
3305
              const void *Decoder)
3306
8.98k
{
3307
8.98k
  unsigned size = fieldFromInstruction_4(Insn, 6, 2);
3308
8.98k
  if (size == 3)
3309
0
    return MCDisassembler_Fail;
3310
3311
8.98k
  unsigned load = fieldFromInstruction_4(Insn, 21, 1);
3312
8.98k
  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) :
3313
8.98k
          DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3314
8.98k
}
3315
3316
static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn,
3317
           uint64_t Address, const void *Decoder)
3318
26.3k
{
3319
26.3k
  DecodeStatus S = MCDisassembler_Success;
3320
3321
26.3k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3322
26.3k
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3323
26.3k
  unsigned wb = fieldFromInstruction_4(Insn, 16, 4);
3324
26.3k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3325
26.3k
  Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4;
3326
26.3k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
3327
3328
  // Writeback Operand
3329
26.3k
  switch (MCInst_getOpcode(Inst)) {
3330
202
  case ARM_VST1d8wb_fixed:
3331
630
  case ARM_VST1d16wb_fixed:
3332
730
  case ARM_VST1d32wb_fixed:
3333
885
  case ARM_VST1d64wb_fixed:
3334
976
  case ARM_VST1d8wb_register:
3335
1.28k
  case ARM_VST1d16wb_register:
3336
1.61k
  case ARM_VST1d32wb_register:
3337
1.69k
  case ARM_VST1d64wb_register:
3338
2.21k
  case ARM_VST1q8wb_fixed:
3339
2.30k
  case ARM_VST1q16wb_fixed:
3340
2.39k
  case ARM_VST1q32wb_fixed:
3341
2.71k
  case ARM_VST1q64wb_fixed:
3342
3.05k
  case ARM_VST1q8wb_register:
3343
3.30k
  case ARM_VST1q16wb_register:
3344
3.40k
  case ARM_VST1q32wb_register:
3345
3.58k
  case ARM_VST1q64wb_register:
3346
3.69k
  case ARM_VST1d8Twb_fixed:
3347
3.91k
  case ARM_VST1d16Twb_fixed:
3348
3.98k
  case ARM_VST1d32Twb_fixed:
3349
4.23k
  case ARM_VST1d64Twb_fixed:
3350
4.40k
  case ARM_VST1d8Twb_register:
3351
4.84k
  case ARM_VST1d16Twb_register:
3352
5.03k
  case ARM_VST1d32Twb_register:
3353
5.12k
  case ARM_VST1d64Twb_register:
3354
5.39k
  case ARM_VST1d8Qwb_fixed:
3355
5.55k
  case ARM_VST1d16Qwb_fixed:
3356
5.93k
  case ARM_VST1d32Qwb_fixed:
3357
6.02k
  case ARM_VST1d64Qwb_fixed:
3358
6.36k
  case ARM_VST1d8Qwb_register:
3359
6.66k
  case ARM_VST1d16Qwb_register:
3360
6.93k
  case ARM_VST1d32Qwb_register:
3361
7.19k
  case ARM_VST1d64Qwb_register:
3362
7.49k
  case ARM_VST2d8wb_fixed:
3363
7.61k
  case ARM_VST2d16wb_fixed:
3364
7.90k
  case ARM_VST2d32wb_fixed:
3365
8.25k
  case ARM_VST2d8wb_register:
3366
8.35k
  case ARM_VST2d16wb_register:
3367
8.45k
  case ARM_VST2d32wb_register:
3368
8.56k
  case ARM_VST2q8wb_fixed:
3369
9.47k
  case ARM_VST2q16wb_fixed:
3370
9.76k
  case ARM_VST2q32wb_fixed:
3371
9.92k
  case ARM_VST2q8wb_register:
3372
10.2k
  case ARM_VST2q16wb_register:
3373
10.5k
  case ARM_VST2q32wb_register:
3374
10.8k
  case ARM_VST2b8wb_fixed:
3375
11.0k
  case ARM_VST2b16wb_fixed:
3376
11.5k
  case ARM_VST2b32wb_fixed:
3377
12.0k
  case ARM_VST2b8wb_register:
3378
12.3k
  case ARM_VST2b16wb_register:
3379
12.7k
  case ARM_VST2b32wb_register:
3380
12.7k
    if (Rm == 0xF)
3381
0
      return MCDisassembler_Fail;
3382
12.7k
    MCOperand_CreateImm0(Inst, (0));
3383
12.7k
    break;
3384
740
  case ARM_VST3d8_UPD:
3385
911
  case ARM_VST3d16_UPD:
3386
1.59k
  case ARM_VST3d32_UPD:
3387
2.21k
  case ARM_VST3q8_UPD:
3388
2.47k
  case ARM_VST3q16_UPD:
3389
2.74k
  case ARM_VST3q32_UPD:
3390
3.79k
  case ARM_VST4d8_UPD:
3391
4.52k
  case ARM_VST4d16_UPD:
3392
4.93k
  case ARM_VST4d32_UPD:
3393
5.33k
  case ARM_VST4q8_UPD:
3394
5.45k
  case ARM_VST4q16_UPD:
3395
5.65k
  case ARM_VST4q32_UPD:
3396
5.65k
    if (!Check(&S,
3397
5.65k
         DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3398
0
      return MCDisassembler_Fail;
3399
5.65k
    break;
3400
8.02k
  default:
3401
8.02k
    break;
3402
26.3k
  }
3403
3404
  // AddrMode6 Base (register+alignment)
3405
26.3k
  if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3406
0
    return MCDisassembler_Fail;
3407
3408
  // AddrMode6 Offset (register)
3409
26.3k
  switch (MCInst_getOpcode(Inst)) {
3410
19.8k
  default:
3411
19.8k
    if (Rm == 0xD)
3412
1.08k
      MCOperand_CreateReg0(Inst, (0));
3413
18.7k
    else if (Rm != 0xF) {
3414
10.7k
      if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address,
3415
10.7k
                    Decoder)))
3416
0
        return MCDisassembler_Fail;
3417
10.7k
    }
3418
19.8k
    break;
3419
19.8k
  case ARM_VST1d8wb_fixed:
3420
630
  case ARM_VST1d16wb_fixed:
3421
730
  case ARM_VST1d32wb_fixed:
3422
885
  case ARM_VST1d64wb_fixed:
3423
1.40k
  case ARM_VST1q8wb_fixed:
3424
1.49k
  case ARM_VST1q16wb_fixed:
3425
1.58k
  case ARM_VST1q32wb_fixed:
3426
1.90k
  case ARM_VST1q64wb_fixed:
3427
2.01k
  case ARM_VST1d8Twb_fixed:
3428
2.23k
  case ARM_VST1d16Twb_fixed:
3429
2.30k
  case ARM_VST1d32Twb_fixed:
3430
2.56k
  case ARM_VST1d64Twb_fixed:
3431
2.84k
  case ARM_VST1d8Qwb_fixed:
3432
3.00k
  case ARM_VST1d16Qwb_fixed:
3433
3.38k
  case ARM_VST1d32Qwb_fixed:
3434
3.46k
  case ARM_VST1d64Qwb_fixed:
3435
3.77k
  case ARM_VST2d8wb_fixed:
3436
3.88k
  case ARM_VST2d16wb_fixed:
3437
4.17k
  case ARM_VST2d32wb_fixed:
3438
4.27k
  case ARM_VST2q8wb_fixed:
3439
5.18k
  case ARM_VST2q16wb_fixed:
3440
5.48k
  case ARM_VST2q32wb_fixed:
3441
5.77k
  case ARM_VST2b8wb_fixed:
3442
5.95k
  case ARM_VST2b16wb_fixed:
3443
6.52k
  case ARM_VST2b32wb_fixed:
3444
6.52k
    break;
3445
26.3k
  }
3446
3447
  // First input register
3448
26.3k
  switch (MCInst_getOpcode(Inst)) {
3449
523
  case ARM_VST1q16:
3450
962
  case ARM_VST1q32:
3451
1.08k
  case ARM_VST1q64:
3452
1.41k
  case ARM_VST1q8:
3453
1.50k
  case ARM_VST1q16wb_fixed:
3454
1.74k
  case ARM_VST1q16wb_register:
3455
1.83k
  case ARM_VST1q32wb_fixed:
3456
1.93k
  case ARM_VST1q32wb_register:
3457
2.26k
  case ARM_VST1q64wb_fixed:
3458
2.44k
  case ARM_VST1q64wb_register:
3459
2.96k
  case ARM_VST1q8wb_fixed:
3460
3.30k
  case ARM_VST1q8wb_register:
3461
3.64k
  case ARM_VST2d16:
3462
3.85k
  case ARM_VST2d32:
3463
4.16k
  case ARM_VST2d8:
3464
4.27k
  case ARM_VST2d16wb_fixed:
3465
4.37k
  case ARM_VST2d16wb_register:
3466
4.66k
  case ARM_VST2d32wb_fixed:
3467
4.76k
  case ARM_VST2d32wb_register:
3468
5.06k
  case ARM_VST2d8wb_fixed:
3469
5.42k
  case ARM_VST2d8wb_register:
3470
5.42k
    if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address,
3471
5.42k
              Decoder)))
3472
1
      return MCDisassembler_Fail;
3473
5.42k
    break;
3474
5.42k
  case ARM_VST2b16:
3475
644
  case ARM_VST2b32:
3476
851
  case ARM_VST2b8:
3477
1.03k
  case ARM_VST2b16wb_fixed:
3478
1.30k
  case ARM_VST2b16wb_register:
3479
1.86k
  case ARM_VST2b32wb_fixed:
3480
2.21k
  case ARM_VST2b32wb_register:
3481
2.50k
  case ARM_VST2b8wb_fixed:
3482
3.02k
  case ARM_VST2b8wb_register:
3483
3.02k
    if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address,
3484
3.02k
                    Decoder)))
3485
3
      return MCDisassembler_Fail;
3486
3.02k
    break;
3487
17.9k
  default:
3488
17.9k
    if (!Check(&S,
3489
17.9k
         DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3490
0
      return MCDisassembler_Fail;
3491
26.3k
  }
3492
3493
  // Second input register
3494
26.3k
  switch (MCInst_getOpcode(Inst)) {
3495
225
  case ARM_VST3d8:
3496
828
  case ARM_VST3d16:
3497
1.04k
  case ARM_VST3d32:
3498
1.78k
  case ARM_VST3d8_UPD:
3499
1.95k
  case ARM_VST3d16_UPD:
3500
2.63k
  case ARM_VST3d32_UPD:
3501
2.89k
  case ARM_VST4d8:
3502
3.17k
  case ARM_VST4d16:
3503
3.46k
  case ARM_VST4d32:
3504
4.51k
  case ARM_VST4d8_UPD:
3505
5.25k
  case ARM_VST4d16_UPD:
3506
5.65k
  case ARM_VST4d32_UPD:
3507
5.65k
    if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32,
3508
5.65k
                  Address, Decoder)))
3509
0
      return MCDisassembler_Fail;
3510
5.65k
    break;
3511
5.65k
  case ARM_VST3q8:
3512
1.26k
  case ARM_VST3q16:
3513
1.44k
  case ARM_VST3q32:
3514
2.06k
  case ARM_VST3q8_UPD:
3515
2.32k
  case ARM_VST3q16_UPD:
3516
2.59k
  case ARM_VST3q32_UPD:
3517
2.96k
  case ARM_VST4q8:
3518
3.10k
  case ARM_VST4q16:
3519
3.37k
  case ARM_VST4q32:
3520
3.78k
  case ARM_VST4q8_UPD:
3521
3.90k
  case ARM_VST4q16_UPD:
3522
4.09k
  case ARM_VST4q32_UPD:
3523
4.09k
    if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32,
3524
4.09k
                  Address, Decoder)))
3525
0
      return MCDisassembler_Fail;
3526
4.09k
    break;
3527
16.6k
  default:
3528
16.6k
    break;
3529
26.3k
  }
3530
3531
  // Third input register
3532
26.3k
  switch (MCInst_getOpcode(Inst)) {
3533
225
  case ARM_VST3d8:
3534
828
  case ARM_VST3d16:
3535
1.04k
  case ARM_VST3d32:
3536
1.78k
  case ARM_VST3d8_UPD:
3537
1.95k
  case ARM_VST3d16_UPD:
3538
2.63k
  case ARM_VST3d32_UPD:
3539
2.89k
  case ARM_VST4d8:
3540
3.17k
  case ARM_VST4d16:
3541
3.46k
  case ARM_VST4d32:
3542
4.51k
  case ARM_VST4d8_UPD:
3543
5.25k
  case ARM_VST4d16_UPD:
3544
5.65k
  case ARM_VST4d32_UPD:
3545
5.65k
    if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32,
3546
5.65k
                  Address, Decoder)))
3547
0
      return MCDisassembler_Fail;
3548
5.65k
    break;
3549
5.65k
  case ARM_VST3q8:
3550
1.26k
  case ARM_VST3q16:
3551
1.44k
  case ARM_VST3q32:
3552
2.06k
  case ARM_VST3q8_UPD:
3553
2.32k
  case ARM_VST3q16_UPD:
3554
2.59k
  case ARM_VST3q32_UPD:
3555
2.96k
  case ARM_VST4q8:
3556
3.10k
  case ARM_VST4q16:
3557
3.37k
  case ARM_VST4q32:
3558
3.78k
  case ARM_VST4q8_UPD:
3559
3.90k
  case ARM_VST4q16_UPD:
3560
4.09k
  case ARM_VST4q32_UPD:
3561
4.09k
    if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32,
3562
4.09k
                  Address, Decoder)))
3563
0
      return MCDisassembler_Fail;
3564
4.09k
    break;
3565
16.6k
  default:
3566
16.6k
    break;
3567
26.3k
  }
3568
3569
  // Fourth input register
3570
26.3k
  switch (MCInst_getOpcode(Inst)) {
3571
265
  case ARM_VST4d8:
3572
537
  case ARM_VST4d16:
3573
832
  case ARM_VST4d32:
3574
1.88k
  case ARM_VST4d8_UPD:
3575
2.61k
  case ARM_VST4d16_UPD:
3576
3.02k
  case ARM_VST4d32_UPD:
3577
3.02k
    if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32,
3578
3.02k
                  Address, Decoder)))
3579
0
      return MCDisassembler_Fail;
3580
3.02k
    break;
3581
3.02k
  case ARM_VST4q8:
3582
514
  case ARM_VST4q16:
3583
783
  case ARM_VST4q32:
3584
1.18k
  case ARM_VST4q8_UPD:
3585
1.30k
  case ARM_VST4q16_UPD:
3586
1.50k
  case ARM_VST4q32_UPD:
3587
1.50k
    if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32,
3588
1.50k
                  Address, Decoder)))
3589
0
      return MCDisassembler_Fail;
3590
1.50k
    break;
3591
21.8k
  default:
3592
21.8k
    break;
3593
26.3k
  }
3594
3595
26.3k
  return S;
3596
26.3k
}
3597
3598
static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn,
3599
               uint64_t Address,
3600
               const void *Decoder)
3601
1.18k
{
3602
1.18k
  DecodeStatus S = MCDisassembler_Success;
3603
3604
1.18k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3605
1.18k
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3606
1.18k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3607
1.18k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
3608
1.18k
  unsigned align = fieldFromInstruction_4(Insn, 4, 1);
3609
1.18k
  unsigned size = fieldFromInstruction_4(Insn, 6, 2);
3610
3611
1.18k
  if (size == 0 && align == 1)
3612
1
    return MCDisassembler_Fail;
3613
1.18k
  align *= (1 << size);
3614
3615
1.18k
  switch (MCInst_getOpcode(Inst)) {
3616
0
  case ARM_VLD1DUPq16:
3617
0
  case ARM_VLD1DUPq32:
3618
6
  case ARM_VLD1DUPq8:
3619
19
  case ARM_VLD1DUPq16wb_fixed:
3620
62
  case ARM_VLD1DUPq16wb_register:
3621
69
  case ARM_VLD1DUPq32wb_fixed:
3622
350
  case ARM_VLD1DUPq32wb_register:
3623
391
  case ARM_VLD1DUPq8wb_fixed:
3624
397
  case ARM_VLD1DUPq8wb_register:
3625
397
    if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address,
3626
397
              Decoder)))
3627
2
      return MCDisassembler_Fail;
3628
395
    break;
3629
783
  default:
3630
783
    if (!Check(&S,
3631
783
         DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3632
0
      return MCDisassembler_Fail;
3633
783
    break;
3634
1.18k
  }
3635
1.17k
  if (Rm != 0xF) {
3636
531
    if (!Check(&S,
3637
531
         DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3638
0
      return MCDisassembler_Fail;
3639
531
  }
3640
3641
1.17k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3642
0
    return MCDisassembler_Fail;
3643
1.17k
  MCOperand_CreateImm0(Inst, (align));
3644
3645
  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3646
  // variant encodes Rm == 0xf. Anything else is a register offset post-
3647
  // increment and we need to add the register operand to the instruction.
3648
1.17k
  if (Rm != 0xD && Rm != 0xF &&
3649
1.17k
      !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3650
0
    return MCDisassembler_Fail;
3651
3652
1.17k
  return S;
3653
1.17k
}
3654
3655
static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn,
3656
               uint64_t Address,
3657
               const void *Decoder)
3658
4.48k
{
3659
4.48k
  DecodeStatus S = MCDisassembler_Success;
3660
3661
4.48k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3662
4.48k
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3663
4.48k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3664
4.48k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
3665
4.48k
  unsigned align = fieldFromInstruction_4(Insn, 4, 1);
3666
4.48k
  unsigned size = 1 << fieldFromInstruction_4(Insn, 6, 2);
3667
4.48k
  align *= 2 * size;
3668
3669
4.48k
  switch (MCInst_getOpcode(Inst)) {
3670
369
  case ARM_VLD2DUPd16:
3671
663
  case ARM_VLD2DUPd32:
3672
741
  case ARM_VLD2DUPd8:
3673
1.14k
  case ARM_VLD2DUPd16wb_fixed:
3674
1.89k
  case ARM_VLD2DUPd16wb_register:
3675
2.07k
  case ARM_VLD2DUPd32wb_fixed:
3676
2.28k
  case ARM_VLD2DUPd32wb_register:
3677
2.54k
  case ARM_VLD2DUPd8wb_fixed:
3678
2.63k
  case ARM_VLD2DUPd8wb_register:
3679
2.63k
    if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address,
3680
2.63k
              Decoder)))
3681
1
      return MCDisassembler_Fail;
3682
2.63k
    break;
3683
2.63k
  case ARM_VLD2DUPd16x2:
3684
345
  case ARM_VLD2DUPd32x2:
3685
433
  case ARM_VLD2DUPd8x2:
3686
723
  case ARM_VLD2DUPd16x2wb_fixed:
3687
864
  case ARM_VLD2DUPd16x2wb_register:
3688
967
  case ARM_VLD2DUPd32x2wb_fixed:
3689
1.37k
  case ARM_VLD2DUPd32x2wb_register:
3690
1.67k
  case ARM_VLD2DUPd8x2wb_fixed:
3691
1.84k
  case ARM_VLD2DUPd8x2wb_register:
3692
1.84k
    if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address,
3693
1.84k
                    Decoder)))
3694
3
      return MCDisassembler_Fail;
3695
1.84k
    break;
3696
1.84k
  default:
3697
0
    if (!Check(&S,
3698
0
         DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3699
0
      return MCDisassembler_Fail;
3700
0
    break;
3701
4.48k
  }
3702
3703
4.47k
  if (Rm != 0xF)
3704
3.30k
    MCOperand_CreateImm0(Inst, (0));
3705
3706
4.47k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3707
0
    return MCDisassembler_Fail;
3708
4.47k
  MCOperand_CreateImm0(Inst, (align));
3709
3710
4.47k
  if (Rm != 0xD && Rm != 0xF) {
3711
1.76k
    if (!Check(&S,
3712
1.76k
         DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3713
0
      return MCDisassembler_Fail;
3714
1.76k
  }
3715
3716
4.47k
  return S;
3717
4.47k
}
3718
3719
static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn,
3720
               uint64_t Address,
3721
               const void *Decoder)
3722
619
{
3723
619
  DecodeStatus S = MCDisassembler_Success;
3724
3725
619
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3726
619
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3727
619
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3728
619
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
3729
619
  unsigned inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
3730
3731
619
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3732
0
    return MCDisassembler_Fail;
3733
619
  if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address,
3734
619
                Decoder)))
3735
0
    return MCDisassembler_Fail;
3736
619
  if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2 * inc) % 32,
3737
619
                Address, Decoder)))
3738
0
    return MCDisassembler_Fail;
3739
619
  if (Rm != 0xF) {
3740
416
    if (!Check(&S,
3741
416
         DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3742
0
      return MCDisassembler_Fail;
3743
416
  }
3744
3745
619
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3746
0
    return MCDisassembler_Fail;
3747
619
  MCOperand_CreateImm0(Inst, (0));
3748
3749
619
  if (Rm == 0xD)
3750
191
    MCOperand_CreateReg0(Inst, (0));
3751
428
  else if (Rm != 0xF) {
3752
225
    if (!Check(&S,
3753
225
         DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3754
0
      return MCDisassembler_Fail;
3755
225
  }
3756
3757
619
  return S;
3758
619
}
3759
3760
static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn,
3761
               uint64_t Address,
3762
               const void *Decoder)
3763
2.02k
{
3764
2.02k
  DecodeStatus S = MCDisassembler_Success;
3765
3766
2.02k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3767
2.02k
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3768
2.02k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3769
2.02k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
3770
2.02k
  unsigned size = fieldFromInstruction_4(Insn, 6, 2);
3771
2.02k
  unsigned inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
3772
2.02k
  unsigned align = fieldFromInstruction_4(Insn, 4, 1);
3773
3774
2.02k
  if (size == 0x3) {
3775
565
    if (align == 0)
3776
5
      return MCDisassembler_Fail;
3777
560
    align = 16;
3778
1.46k
  } else {
3779
1.46k
    if (size == 2) {
3780
950
      align *= 8;
3781
950
    } else {
3782
511
      size = 1 << size;
3783
511
      align *= 4 * size;
3784
511
    }
3785
1.46k
  }
3786
3787
2.02k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3788
0
    return MCDisassembler_Fail;
3789
2.02k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address,
3790
2.02k
                Decoder)))
3791
0
    return MCDisassembler_Fail;
3792
2.02k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2 * inc) % 32,
3793
2.02k
                Address, Decoder)))
3794
0
    return MCDisassembler_Fail;
3795
2.02k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3 * inc) % 32,
3796
2.02k
                Address, Decoder)))
3797
0
    return MCDisassembler_Fail;
3798
2.02k
  if (Rm != 0xF) {
3799
1.70k
    if (!Check(&S,
3800
1.70k
         DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3801
0
      return MCDisassembler_Fail;
3802
1.70k
  }
3803
3804
2.02k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3805
0
    return MCDisassembler_Fail;
3806
2.02k
  MCOperand_CreateImm0(Inst, (align));
3807
3808
2.02k
  if (Rm == 0xD)
3809
897
    MCOperand_CreateReg0(Inst, (0));
3810
1.12k
  else if (Rm != 0xF) {
3811
810
    if (!Check(&S,
3812
810
         DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3813
0
      return MCDisassembler_Fail;
3814
810
  }
3815
3816
2.02k
  return S;
3817
2.02k
}
3818
3819
static DecodeStatus DecodeVMOVModImmInstruction(MCInst *Inst, unsigned Insn,
3820
            uint64_t Address,
3821
            const void *Decoder)
3822
4.79k
{
3823
4.79k
  DecodeStatus S = MCDisassembler_Success;
3824
3825
4.79k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3826
4.79k
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3827
4.79k
  unsigned imm = fieldFromInstruction_4(Insn, 0, 4);
3828
4.79k
  imm |= fieldFromInstruction_4(Insn, 16, 3) << 4;
3829
4.79k
  imm |= fieldFromInstruction_4(Insn, 24, 1) << 7;
3830
4.79k
  imm |= fieldFromInstruction_4(Insn, 8, 4) << 8;
3831
4.79k
  imm |= fieldFromInstruction_4(Insn, 5, 1) << 12;
3832
4.79k
  unsigned Q = fieldFromInstruction_4(Insn, 6, 1);
3833
3834
4.79k
  if (Q) {
3835
2.50k
    if (!Check(&S,
3836
2.50k
         DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3837
5
      return MCDisassembler_Fail;
3838
2.50k
  } else {
3839
2.29k
    if (!Check(&S,
3840
2.29k
         DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3841
0
      return MCDisassembler_Fail;
3842
2.29k
  }
3843
3844
4.79k
  MCOperand_CreateImm0(Inst, (imm));
3845
3846
4.79k
  switch (MCInst_getOpcode(Inst)) {
3847
96
  case ARM_VORRiv4i16:
3848
458
  case ARM_VORRiv2i32:
3849
537
  case ARM_VBICiv4i16:
3850
842
  case ARM_VBICiv2i32:
3851
842
    if (!Check(&S,
3852
842
         DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3853
0
      return MCDisassembler_Fail;
3854
842
    break;
3855
842
  case ARM_VORRiv8i16:
3856
674
  case ARM_VORRiv4i32:
3857
978
  case ARM_VBICiv8i16:
3858
1.39k
  case ARM_VBICiv4i32:
3859
1.39k
    if (!Check(&S,
3860
1.39k
         DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3861
0
      return MCDisassembler_Fail;
3862
1.39k
    break;
3863
2.55k
  default:
3864
2.55k
    break;
3865
4.79k
  }
3866
3867
4.79k
  return S;
3868
4.79k
}
3869
3870
static DecodeStatus DecodeMVEModImmInstruction(MCInst *Inst, unsigned Insn,
3871
                 uint64_t Address,
3872
                 const void *Decoder)
3873
1.12k
{
3874
1.12k
  DecodeStatus S = MCDisassembler_Success;
3875
3876
1.12k
  unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) |
3877
1.12k
           fieldFromInstruction_4(Insn, 13, 3));
3878
1.12k
  unsigned cmode = fieldFromInstruction_4(Insn, 8, 4);
3879
1.12k
  unsigned imm = fieldFromInstruction_4(Insn, 0, 4);
3880
1.12k
  imm |= fieldFromInstruction_4(Insn, 16, 3) << 4;
3881
1.12k
  imm |= fieldFromInstruction_4(Insn, 28, 1) << 7;
3882
1.12k
  imm |= cmode << 8;
3883
1.12k
  imm |= fieldFromInstruction_4(Insn, 5, 1) << 12;
3884
3885
1.12k
  if (cmode == 0xF && MCInst_getOpcode(Inst) == ARM_MVE_VMVNimmi32)
3886
2
    return MCDisassembler_Fail;
3887
3888
1.12k
  if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3889
765
    return MCDisassembler_Fail;
3890
3891
356
  MCOperand_CreateImm0(Inst, (imm));
3892
3893
356
  MCOperand_CreateImm0(Inst, (ARMVCC_None));
3894
356
  MCOperand_CreateReg0(Inst, (0));
3895
356
  MCOperand_CreateImm0(Inst, (0));
3896
3897
356
  return S;
3898
1.12k
}
3899
3900
static DecodeStatus DecodeMVEVADCInstruction(MCInst *Inst, unsigned Insn,
3901
               uint64_t Address,
3902
               const void *Decoder)
3903
886
{
3904
886
  DecodeStatus S = MCDisassembler_Success;
3905
3906
886
  unsigned Qd = fieldFromInstruction_4(Insn, 13, 3);
3907
886
  Qd |= fieldFromInstruction_4(Insn, 22, 1) << 3;
3908
886
  if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3909
249
    return MCDisassembler_Fail;
3910
637
  MCOperand_CreateReg0(Inst, (ARM_FPSCR_NZCV));
3911
3912
637
  unsigned Qn = fieldFromInstruction_4(Insn, 17, 3);
3913
637
  Qn |= fieldFromInstruction_4(Insn, 7, 1) << 3;
3914
637
  if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
3915
87
    return MCDisassembler_Fail;
3916
550
  unsigned Qm = fieldFromInstruction_4(Insn, 1, 3);
3917
550
  Qm |= fieldFromInstruction_4(Insn, 5, 1) << 3;
3918
550
  if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3919
76
    return MCDisassembler_Fail;
3920
474
  if (!fieldFromInstruction_4(Insn, 12,
3921
474
            1)) // I bit clear => need input FPSCR
3922
405
    MCOperand_CreateReg0(Inst, (ARM_FPSCR_NZCV));
3923
474
  MCOperand_CreateImm0(Inst, (Qd));
3924
3925
474
  return S;
3926
550
}
3927
3928
static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn,
3929
               uint64_t Address,
3930
               const void *Decoder)
3931
132
{
3932
132
  DecodeStatus S = MCDisassembler_Success;
3933
3934
132
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3935
132
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3936
132
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
3937
132
  Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4;
3938
132
  unsigned size = fieldFromInstruction_4(Insn, 18, 2);
3939
3940
132
  if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3941
2
    return MCDisassembler_Fail;
3942
130
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3943
0
    return MCDisassembler_Fail;
3944
130
  MCOperand_CreateImm0(Inst, (8 << size));
3945
3946
130
  return S;
3947
130
}
3948
3949
static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val,
3950
           uint64_t Address, const void *Decoder)
3951
3.32k
{
3952
3.32k
  MCOperand_CreateImm0(Inst, (8 - Val));
3953
3.32k
  return MCDisassembler_Success;
3954
3.32k
}
3955
3956
static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val,
3957
            uint64_t Address, const void *Decoder)
3958
1.46k
{
3959
1.46k
  MCOperand_CreateImm0(Inst, (16 - Val));
3960
1.46k
  return MCDisassembler_Success;
3961
1.46k
}
3962
3963
static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val,
3964
            uint64_t Address, const void *Decoder)
3965
2.34k
{
3966
2.34k
  MCOperand_CreateImm0(Inst, (32 - Val));
3967
2.34k
  return MCDisassembler_Success;
3968
2.34k
}
3969
3970
static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val,
3971
            uint64_t Address, const void *Decoder)
3972
1.21k
{
3973
1.21k
  MCOperand_CreateImm0(Inst, (64 - Val));
3974
1.21k
  return MCDisassembler_Success;
3975
1.21k
}
3976
3977
static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn,
3978
           uint64_t Address, const void *Decoder)
3979
1.97k
{
3980
1.97k
  DecodeStatus S = MCDisassembler_Success;
3981
3982
1.97k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3983
1.97k
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3984
1.97k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3985
1.97k
  Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4;
3986
1.97k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
3987
1.97k
  Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4;
3988
1.97k
  unsigned op = fieldFromInstruction_4(Insn, 6, 1);
3989
3990
1.97k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3991
0
    return MCDisassembler_Fail;
3992
1.97k
  if (op) {
3993
762
    if (!Check(&S,
3994
762
         DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3995
0
      return MCDisassembler_Fail; // Writeback
3996
762
  }
3997
3998
1.97k
  switch (MCInst_getOpcode(Inst)) {
3999
343
  case ARM_VTBL2:
4000
615
  case ARM_VTBX2:
4001
615
    if (!Check(&S, DecodeDPairRegisterClass(Inst, Rn, Address,
4002
615
              Decoder)))
4003
2
      return MCDisassembler_Fail;
4004
613
    break;
4005
1.35k
  default:
4006
1.35k
    if (!Check(&S,
4007
1.35k
         DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
4008
0
      return MCDisassembler_Fail;
4009
1.97k
  }
4010
4011
1.96k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
4012
0
    return MCDisassembler_Fail;
4013
4014
1.96k
  return S;
4015
1.96k
}
4016
4017
static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn,
4018
               uint64_t Address,
4019
               const void *Decoder)
4020
49.3k
{
4021
49.3k
  DecodeStatus S = MCDisassembler_Success;
4022
4023
49.3k
  unsigned dst = fieldFromInstruction_2(Insn, 8, 3);
4024
49.3k
  unsigned imm = fieldFromInstruction_2(Insn, 0, 8);
4025
4026
49.3k
  if (!Check(&S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
4027
0
    return MCDisassembler_Fail;
4028
4029
49.3k
  switch (MCInst_getOpcode(Inst)) {
4030
0
  default:
4031
0
    return MCDisassembler_Fail;
4032
24.3k
  case ARM_tADR:
4033
24.3k
    break; // tADR does not explicitly represent the PC as an operand.
4034
24.9k
  case ARM_tADDrSPi:
4035
24.9k
    MCOperand_CreateReg0(Inst, (ARM_SP));
4036
24.9k
    break;
4037
49.3k
  }
4038
4039
49.3k
  MCOperand_CreateImm0(Inst, (imm));
4040
49.3k
  return S;
4041
49.3k
}
4042
4043
static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val,
4044
           uint64_t Address, const void *Decoder)
4045
15.5k
{
4046
15.5k
  if (!tryAddingSymbolicOperand(
4047
15.5k
        Address, Address + SignExtend32((Val << 1), 12) + 4, true,
4048
15.5k
        2, Inst, Decoder))
4049
15.5k
    MCOperand_CreateImm0(Inst, (SignExtend32((Val << 1), 12)));
4050
15.5k
  return MCDisassembler_Success;
4051
15.5k
}
4052
4053
static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val,
4054
              uint64_t Address, const void *Decoder)
4055
3.10k
{
4056
3.10k
  if (!tryAddingSymbolicOperand(Address,
4057
3.10k
              Address + SignExtend32((Val), 21) + 4,
4058
3.10k
              true, 4, Inst, Decoder))
4059
3.10k
    MCOperand_CreateImm0(Inst, (SignExtend32((Val), 21)));
4060
3.10k
  return MCDisassembler_Success;
4061
3.10k
}
4062
4063
static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val,
4064
              uint64_t Address,
4065
              const void *Decoder)
4066
4.64k
{
4067
4.64k
  if (!tryAddingSymbolicOperand(Address, Address + (Val << 1) + 4, true,
4068
4.64k
              2, Inst, Decoder))
4069
4.64k
    MCOperand_CreateImm0(Inst, (Val << 1));
4070
4.64k
  return MCDisassembler_Success;
4071
4.64k
}
4072
4073
static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val,
4074
            uint64_t Address, const void *Decoder)
4075
31.4k
{
4076
31.4k
  DecodeStatus S = MCDisassembler_Success;
4077
4078
31.4k
  unsigned Rn = fieldFromInstruction_4(Val, 0, 3);
4079
31.4k
  unsigned Rm = fieldFromInstruction_4(Val, 3, 3);
4080
4081
31.4k
  if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4082
0
    return MCDisassembler_Fail;
4083
31.4k
  if (!Check(&S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
4084
0
    return MCDisassembler_Fail;
4085
4086
31.4k
  return S;
4087
31.4k
}
4088
4089
static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val,
4090
            uint64_t Address, const void *Decoder)
4091
190k
{
4092
190k
  DecodeStatus S = MCDisassembler_Success;
4093
4094
190k
  unsigned Rn = fieldFromInstruction_4(Val, 0, 3);
4095
190k
  unsigned imm = fieldFromInstruction_4(Val, 3, 5);
4096
4097
190k
  if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4098
0
    return MCDisassembler_Fail;
4099
190k
  MCOperand_CreateImm0(Inst, (imm));
4100
4101
190k
  return S;
4102
190k
}
4103
4104
static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val,
4105
            uint64_t Address, const void *Decoder)
4106
25.2k
{
4107
25.2k
  unsigned imm = Val << 2;
4108
4109
25.2k
  MCOperand_CreateImm0(Inst, (imm));
4110
25.2k
  tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4,
4111
25.2k
          Decoder);
4112
4113
25.2k
  return MCDisassembler_Success;
4114
25.2k
}
4115
4116
static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val,
4117
            uint64_t Address, const void *Decoder)
4118
32.7k
{
4119
32.7k
  MCOperand_CreateReg0(Inst, (ARM_SP));
4120
32.7k
  MCOperand_CreateImm0(Inst, (Val));
4121
4122
32.7k
  return MCDisassembler_Success;
4123
32.7k
}
4124
4125
static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val,
4126
            uint64_t Address, const void *Decoder)
4127
1.79k
{
4128
1.79k
  DecodeStatus S = MCDisassembler_Success;
4129
4130
1.79k
  unsigned Rn = fieldFromInstruction_4(Val, 6, 4);
4131
1.79k
  unsigned Rm = fieldFromInstruction_4(Val, 2, 4);
4132
1.79k
  unsigned imm = fieldFromInstruction_4(Val, 0, 2);
4133
4134
  // Thumb stores cannot use PC as dest register.
4135
1.79k
  switch (MCInst_getOpcode(Inst)) {
4136
159
  case ARM_t2STRHs:
4137
369
  case ARM_t2STRBs:
4138
1.12k
  case ARM_t2STRs:
4139
1.12k
    if (Rn == 15)
4140
2
      return MCDisassembler_Fail;
4141
1.12k
    break;
4142
1.12k
  default:
4143
676
    break;
4144
1.79k
  }
4145
4146
1.79k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4147
0
    return MCDisassembler_Fail;
4148
1.79k
  if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4149
0
    return MCDisassembler_Fail;
4150
1.79k
  MCOperand_CreateImm0(Inst, (imm));
4151
4152
1.79k
  return S;
4153
1.79k
}
4154
4155
static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn,
4156
              uint64_t Address, const void *Decoder)
4157
1.44k
{
4158
1.44k
  DecodeStatus S = MCDisassembler_Success;
4159
4160
1.44k
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4161
1.44k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4162
4163
1.44k
  bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP);
4164
1.44k
  bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops);
4165
4166
1.44k
  if (Rn == 15) {
4167
770
    switch (MCInst_getOpcode(Inst)) {
4168
118
    case ARM_t2LDRBs:
4169
118
      MCInst_setOpcode(Inst, (ARM_t2LDRBpci));
4170
118
      break;
4171
200
    case ARM_t2LDRHs:
4172
200
      MCInst_setOpcode(Inst, (ARM_t2LDRHpci));
4173
200
      break;
4174
97
    case ARM_t2LDRSHs:
4175
97
      MCInst_setOpcode(Inst, (ARM_t2LDRSHpci));
4176
97
      break;
4177
80
    case ARM_t2LDRSBs:
4178
80
      MCInst_setOpcode(Inst, (ARM_t2LDRSBpci));
4179
80
      break;
4180
97
    case ARM_t2LDRs:
4181
97
      MCInst_setOpcode(Inst, (ARM_t2LDRpci));
4182
97
      break;
4183
111
    case ARM_t2PLDs:
4184
111
      MCInst_setOpcode(Inst, (ARM_t2PLDpci));
4185
111
      break;
4186
66
    case ARM_t2PLIs:
4187
66
      MCInst_setOpcode(Inst, (ARM_t2PLIpci));
4188
66
      break;
4189
1
    default:
4190
1
      return MCDisassembler_Fail;
4191
770
    }
4192
4193
769
    return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4194
770
  }
4195
4196
677
  if (Rt == 15) {
4197
485
    switch (MCInst_getOpcode(Inst)) {
4198
1
    case ARM_t2LDRSHs:
4199
1
      return MCDisassembler_Fail;
4200
0
    case ARM_t2LDRHs:
4201
0
      MCInst_setOpcode(Inst, (ARM_t2PLDWs));
4202
0
      break;
4203
0
    case ARM_t2LDRSBs:
4204
0
      MCInst_setOpcode(Inst, (ARM_t2PLIs));
4205
0
      break;
4206
484
    default:
4207
484
      break;
4208
485
    }
4209
485
  }
4210
4211
676
  switch (MCInst_getOpcode(Inst)) {
4212
333
  case ARM_t2PLDs:
4213
333
    break;
4214
84
  case ARM_t2PLIs:
4215
84
    if (!hasV7Ops)
4216
0
      return MCDisassembler_Fail;
4217
84
    break;
4218
84
  case ARM_t2PLDWs:
4219
67
    if (!hasV7Ops || !hasMP)
4220
0
      return MCDisassembler_Fail;
4221
67
    break;
4222
192
  default:
4223
192
    if (!Check(&S,
4224
192
         DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4225
0
      return MCDisassembler_Fail;
4226
676
  }
4227
4228
676
  unsigned addrmode = fieldFromInstruction_4(Insn, 4, 2);
4229
676
  addrmode |= fieldFromInstruction_4(Insn, 0, 4) << 2;
4230
676
  addrmode |= fieldFromInstruction_4(Insn, 16, 4) << 6;
4231
676
  if (!Check(&S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
4232
0
    return MCDisassembler_Fail;
4233
4234
676
  return S;
4235
676
}
4236
4237
static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn,
4238
             uint64_t Address, const void *Decoder)
4239
2.02k
{
4240
2.02k
  DecodeStatus S = MCDisassembler_Success;
4241
4242
2.02k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4243
2.02k
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4244
2.02k
  unsigned U = fieldFromInstruction_4(Insn, 9, 1);
4245
2.02k
  unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
4246
2.02k
  imm |= (U << 8);
4247
2.02k
  imm |= (Rn << 9);
4248
2.02k
  unsigned add = fieldFromInstruction_4(Insn, 9, 1);
4249
4250
2.02k
  bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP);
4251
2.02k
  bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops);
4252
4253
2.02k
  if (Rn == 15) {
4254
1.41k
    switch (MCInst_getOpcode(Inst)) {
4255
329
    case ARM_t2LDRi8:
4256
329
      MCInst_setOpcode(Inst, (ARM_t2LDRpci));
4257
329
      break;
4258
191
    case ARM_t2LDRBi8:
4259
191
      MCInst_setOpcode(Inst, (ARM_t2LDRBpci));
4260
191
      break;
4261
137
    case ARM_t2LDRSBi8:
4262
137
      MCInst_setOpcode(Inst, (ARM_t2LDRSBpci));
4263
137
      break;
4264
53
    case ARM_t2LDRHi8:
4265
53
      MCInst_setOpcode(Inst, (ARM_t2LDRHpci));
4266
53
      break;
4267
225
    case ARM_t2LDRSHi8:
4268
225
      MCInst_setOpcode(Inst, (ARM_t2LDRSHpci));
4269
225
      break;
4270
103
    case ARM_t2PLDi8:
4271
103
      MCInst_setOpcode(Inst, (ARM_t2PLDpci));
4272
103
      break;
4273
380
    case ARM_t2PLIi8:
4274
380
      MCInst_setOpcode(Inst, (ARM_t2PLIpci));
4275
380
      break;
4276
1
    default:
4277
1
      return MCDisassembler_Fail;
4278
1.41k
    }
4279
1.41k
    return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4280
1.41k
  }
4281
4282
602
  if (Rt == 15) {
4283
384
    switch (MCInst_getOpcode(Inst)) {
4284
2
    case ARM_t2LDRSHi8:
4285
2
      return MCDisassembler_Fail;
4286
0
    case ARM_t2LDRHi8:
4287
0
      if (!add)
4288
0
        MCInst_setOpcode(Inst, (ARM_t2PLDWi8));
4289
0
      break;
4290
0
    case ARM_t2LDRSBi8:
4291
0
      MCInst_setOpcode(Inst, (ARM_t2PLIi8));
4292
0
      break;
4293
382
    default:
4294
382
      break;
4295
384
    }
4296
384
  }
4297
4298
600
  switch (MCInst_getOpcode(Inst)) {
4299
68
  case ARM_t2PLDi8:
4300
68
    break;
4301
85
  case ARM_t2PLIi8:
4302
85
    if (!hasV7Ops)
4303
0
      return MCDisassembler_Fail;
4304
85
    break;
4305
216
  case ARM_t2PLDWi8:
4306
216
    if (!hasV7Ops || !hasMP)
4307
0
      return MCDisassembler_Fail;
4308
216
    break;
4309
231
  default:
4310
231
    if (!Check(&S,
4311
231
         DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4312
0
      return MCDisassembler_Fail;
4313
600
  }
4314
4315
600
  if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4316
0
    return MCDisassembler_Fail;
4317
600
  return S;
4318
600
}
4319
4320
static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn,
4321
              uint64_t Address, const void *Decoder)
4322
4.70k
{
4323
4.70k
  DecodeStatus S = MCDisassembler_Success;
4324
4325
4.70k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4326
4.70k
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4327
4.70k
  unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
4328
4.70k
  imm |= (Rn << 13);
4329
4330
4.70k
  bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP);
4331
4.70k
  bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops);
4332
4333
4.70k
  if (Rn == 15) {
4334
2.06k
    switch (MCInst_getOpcode(Inst)) {
4335
123
    case ARM_t2LDRi12:
4336
123
      MCInst_setOpcode(Inst, (ARM_t2LDRpci));
4337
123
      break;
4338
430
    case ARM_t2LDRHi12:
4339
430
      MCInst_setOpcode(Inst, (ARM_t2LDRHpci));
4340
430
      break;
4341
419
    case ARM_t2LDRSHi12:
4342
419
      MCInst_setOpcode(Inst, (ARM_t2LDRSHpci));
4343
419
      break;
4344
92
    case ARM_t2LDRBi12:
4345
92
      MCInst_setOpcode(Inst, (ARM_t2LDRBpci));
4346
92
      break;
4347
503
    case ARM_t2LDRSBi12:
4348
503
      MCInst_setOpcode(Inst, (ARM_t2LDRSBpci));
4349
503
      break;
4350
121
    case ARM_t2PLDi12:
4351
121
      MCInst_setOpcode(Inst, (ARM_t2PLDpci));
4352
121
      break;
4353
373
    case ARM_t2PLIi12:
4354
373
      MCInst_setOpcode(Inst, (ARM_t2PLIpci));
4355
373
      break;
4356
3
    default:
4357
3
      return MCDisassembler_Fail;
4358
2.06k
    }
4359
2.06k
    return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4360
2.06k
  }
4361
4362
2.64k
  if (Rt == 15) {
4363
842
    switch (MCInst_getOpcode(Inst)) {
4364
1
    case ARM_t2LDRSHi12:
4365
1
      return MCDisassembler_Fail;
4366
0
    case ARM_t2LDRHi12:
4367
0
      MCInst_setOpcode(Inst, (ARM_t2PLDWi12));
4368
0
      break;
4369
0
    case ARM_t2LDRSBi12:
4370
0
      MCInst_setOpcode(Inst, (ARM_t2PLIi12));
4371
0
      break;
4372
841
    default:
4373
841
      break;
4374
842
    }
4375
842
  }
4376
4377
2.64k
  switch (MCInst_getOpcode(Inst)) {
4378
497
  case ARM_t2PLDi12:
4379
497
    break;
4380
235
  case ARM_t2PLIi12:
4381
235
    if (!hasV7Ops)
4382
0
      return MCDisassembler_Fail;
4383
235
    break;
4384
235
  case ARM_t2PLDWi12:
4385
93
    if (!hasV7Ops || !hasMP)
4386
0
      return MCDisassembler_Fail;
4387
93
    break;
4388
1.81k
  default:
4389
1.81k
    if (!Check(&S,
4390
1.81k
         DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4391
0
      return MCDisassembler_Fail;
4392
2.64k
  }
4393
4394
2.64k
  if (!Check(&S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
4395
0
    return MCDisassembler_Fail;
4396
2.64k
  return S;
4397
2.64k
}
4398
4399
static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, uint64_t Address,
4400
          const void *Decoder)
4401
3.08k
{
4402
3.08k
  DecodeStatus S = MCDisassembler_Success;
4403
4404
3.08k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4405
3.08k
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4406
3.08k
  unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
4407
3.08k
  imm |= (Rn << 9);
4408
4409
3.08k
  if (Rn == 15) {
4410
1.26k
    switch (MCInst_getOpcode(Inst)) {
4411
282
    case ARM_t2LDRT:
4412
282
      MCInst_setOpcode(Inst, (ARM_t2LDRpci));
4413
282
      break;
4414
304
    case ARM_t2LDRBT:
4415
304
      MCInst_setOpcode(Inst, (ARM_t2LDRBpci));
4416
304
      break;
4417
476
    case ARM_t2LDRHT:
4418
476
      MCInst_setOpcode(Inst, (ARM_t2LDRHpci));
4419
476
      break;
4420
135
    case ARM_t2LDRSBT:
4421
135
      MCInst_setOpcode(Inst, (ARM_t2LDRSBpci));
4422
135
      break;
4423
71
    case ARM_t2LDRSHT:
4424
71
      MCInst_setOpcode(Inst, (ARM_t2LDRSHpci));
4425
71
      break;
4426
0
    default:
4427
0
      return MCDisassembler_Fail;
4428
1.26k
    }
4429
1.26k
    return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4430
1.26k
  }
4431
4432
1.81k
  if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4433
0
    return MCDisassembler_Fail;
4434
1.81k
  if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4435
0
    return MCDisassembler_Fail;
4436
1.81k
  return S;
4437
1.81k
}
4438
4439
static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn,
4440
              uint64_t Address, const void *Decoder)
4441
10.2k
{
4442
10.2k
  DecodeStatus S = MCDisassembler_Success;
4443
4444
10.2k
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4445
10.2k
  unsigned U = fieldFromInstruction_4(Insn, 23, 1);
4446
10.2k
  int imm = fieldFromInstruction_4(Insn, 0, 12);
4447
4448
10.2k
  bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops);
4449
4450
10.2k
  if (Rt == 15) {
4451
3.19k
    switch (MCInst_getOpcode(Inst)) {
4452
686
    case ARM_t2LDRBpci:
4453
795
    case ARM_t2LDRHpci:
4454
795
      MCInst_setOpcode(Inst, (ARM_t2PLDpci));
4455
795
      break;
4456
88
    case ARM_t2LDRSBpci:
4457
88
      MCInst_setOpcode(Inst, (ARM_t2PLIpci));
4458
88
      break;
4459
12
    case ARM_t2LDRSHpci:
4460
12
      return MCDisassembler_Fail;
4461
2.29k
    default:
4462
2.29k
      break;
4463
3.19k
    }
4464
3.19k
  }
4465
4466
10.2k
  switch (MCInst_getOpcode(Inst)) {
4467
1.22k
  case ARM_t2PLDpci:
4468
1.22k
    break;
4469
1.61k
  case ARM_t2PLIpci:
4470
1.61k
    if (!hasV7Ops)
4471
0
      return MCDisassembler_Fail;
4472
1.61k
    break;
4473
7.43k
  default:
4474
7.43k
    if (!Check(&S,
4475
7.43k
         DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4476
0
      return MCDisassembler_Fail;
4477
10.2k
  }
4478
4479
10.2k
  if (!U) {
4480
    // Special case for #-0.
4481
8.21k
    if (imm == 0)
4482
434
      imm = INT32_MIN;
4483
7.78k
    else
4484
7.78k
      imm = -imm;
4485
8.21k
  }
4486
10.2k
  MCOperand_CreateImm0(Inst, (imm));
4487
4488
10.2k
  return S;
4489
10.2k
}
4490
4491
static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, uint64_t Address,
4492
           const void *Decoder)
4493
12.9k
{
4494
12.9k
  if (Val == 0)
4495
873
    MCOperand_CreateImm0(Inst, (INT32_MIN));
4496
12.0k
  else {
4497
12.0k
    int imm = Val & 0xFF;
4498
4499
12.0k
    if (!(Val & 0x100))
4500
3.61k
      imm *= -1;
4501
12.0k
    MCOperand_CreateImm0(Inst, (imm * 4));
4502
12.0k
  }
4503
4504
12.9k
  return MCDisassembler_Success;
4505
12.9k
}
4506
4507
static DecodeStatus DecodeT2Imm7S4(MCInst *Inst, unsigned Val, uint64_t Address,
4508
           const void *Decoder)
4509
3.97k
{
4510
3.97k
  if (Val == 0)
4511
151
    MCOperand_CreateImm0(Inst, (INT32_MIN));
4512
3.82k
  else {
4513
3.82k
    int imm = Val & 0x7F;
4514
4515
3.82k
    if (!(Val & 0x80))
4516
2.28k
      imm *= -1;
4517
3.82k
    MCOperand_CreateImm0(Inst, (imm * 4));
4518
3.82k
  }
4519
4520
3.97k
  return MCDisassembler_Success;
4521
3.97k
}
4522
4523
static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val,
4524
             uint64_t Address,
4525
             const void *Decoder)
4526
10.1k
{
4527
10.1k
  DecodeStatus S = MCDisassembler_Success;
4528
4529
10.1k
  unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
4530
10.1k
  unsigned imm = fieldFromInstruction_4(Val, 0, 9);
4531
4532
10.1k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4533
0
    return MCDisassembler_Fail;
4534
10.1k
  if (!Check(&S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
4535
0
    return MCDisassembler_Fail;
4536
4537
10.1k
  return S;
4538
10.1k
}
4539
4540
static DecodeStatus DecodeT2AddrModeImm7s4(MCInst *Inst, unsigned Val,
4541
             uint64_t Address,
4542
             const void *Decoder)
4543
3.97k
{
4544
3.97k
  DecodeStatus S = MCDisassembler_Success;
4545
4546
3.97k
  unsigned Rn = fieldFromInstruction_4(Val, 8, 4);
4547
3.97k
  unsigned imm = fieldFromInstruction_4(Val, 0, 8);
4548
4549
3.97k
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4550
0
    return MCDisassembler_Fail;
4551
3.97k
  if (!Check(&S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
4552
0
    return MCDisassembler_Fail;
4553
4554
3.97k
  return S;
4555
3.97k
}
4556
4557
static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst, unsigned Val,
4558
            uint64_t Address,
4559
            const void *Decoder)
4560
862
{
4561
862
  DecodeStatus S = MCDisassembler_Success;
4562
4563
862
  unsigned Rn = fieldFromInstruction_4(Val, 8, 4);
4564
862
  unsigned imm = fieldFromInstruction_4(Val, 0, 8);
4565
4566
862
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4567
0
    return MCDisassembler_Fail;
4568
4569
862
  MCOperand_CreateImm0(Inst, (imm));
4570
4571
862
  return S;
4572
862
}
4573
4574
static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, uint64_t Address,
4575
         const void *Decoder)
4576
7.92k
{
4577
7.92k
  int imm = Val & 0xFF;
4578
7.92k
  if (Val == 0)
4579
761
    imm = INT32_MIN;
4580
7.16k
  else if (!(Val & 0x100))
4581
3.38k
    imm *= -1;
4582
7.92k
  MCOperand_CreateImm0(Inst, (imm));
4583
4584
7.92k
  return MCDisassembler_Success;
4585
7.92k
}
4586
4587
#define DEFINE_DecodeT2Imm7(shift) \
4588
  static DecodeStatus CONCAT(DecodeT2Imm7, shift)(MCInst * Inst, \
4589
              unsigned Val, \
4590
              uint64_t Address, \
4591
              const void *Decoder) \
4592
12.4k
  { \
4593
12.4k
    int imm = Val & 0x7F; \
4594
12.4k
    if (Val == 0) \
4595
12.4k
      imm = INT32_MIN; \
4596
12.4k
    else if (!(Val & 0x80)) \
4597
8.39k
      imm *= -1; \
4598
12.4k
    if (imm != INT32_MIN) \
4599
12.4k
      imm *= (1U << shift); \
4600
12.4k
    MCOperand_CreateImm0(Inst, (imm)); \
4601
12.4k
\
4602
12.4k
    return MCDisassembler_Success; \
4603
12.4k
  }
ARMDisassembler.c:DecodeT2Imm7_0
Line
Count
Source
4592
5.18k
  { \
4593
5.18k
    int imm = Val & 0x7F; \
4594
5.18k
    if (Val == 0) \
4595
5.18k
      imm = INT32_MIN; \
4596
5.18k
    else if (!(Val & 0x80)) \
4597
2.99k
      imm *= -1; \
4598
5.18k
    if (imm != INT32_MIN) \
4599
5.18k
      imm *= (1U << shift); \
4600
5.18k
    MCOperand_CreateImm0(Inst, (imm)); \
4601
5.18k
\
4602
5.18k
    return MCDisassembler_Success; \
4603
5.18k
  }
ARMDisassembler.c:DecodeT2Imm7_1
Line
Count
Source
4592
3.83k
  { \
4593
3.83k
    int imm = Val & 0x7F; \
4594
3.83k
    if (Val == 0) \
4595
3.83k
      imm = INT32_MIN; \
4596
3.83k
    else if (!(Val & 0x80)) \
4597
3.13k
      imm *= -1; \
4598
3.83k
    if (imm != INT32_MIN) \
4599
3.83k
      imm *= (1U << shift); \
4600
3.83k
    MCOperand_CreateImm0(Inst, (imm)); \
4601
3.83k
\
4602
3.83k
    return MCDisassembler_Success; \
4603
3.83k
  }
ARMDisassembler.c:DecodeT2Imm7_2
Line
Count
Source
4592
3.43k
  { \
4593
3.43k
    int imm = Val & 0x7F; \
4594
3.43k
    if (Val == 0) \
4595
3.43k
      imm = INT32_MIN; \
4596
3.43k
    else if (!(Val & 0x80)) \
4597
2.26k
      imm *= -1; \
4598
3.43k
    if (imm != INT32_MIN) \
4599
3.43k
      imm *= (1U << shift); \
4600
3.43k
    MCOperand_CreateImm0(Inst, (imm)); \
4601
3.43k
\
4602
3.43k
    return MCDisassembler_Success; \
4603
3.43k
  }
4604
DEFINE_DecodeT2Imm7(0) DEFINE_DecodeT2Imm7(1) DEFINE_DecodeT2Imm7(2)
4605
4606
  static DecodeStatus
4607
  DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, uint64_t Address,
4608
           const void *Decoder)
4609
7.93k
{
4610
7.93k
  DecodeStatus S = MCDisassembler_Success;
4611
4612
7.93k
  unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
4613
7.93k
  unsigned imm = fieldFromInstruction_4(Val, 0, 9);
4614
4615
  // Thumb stores cannot use PC as dest register.
4616
7.93k
  switch (MCInst_getOpcode(Inst)) {
4617
195
  case ARM_t2STRT:
4618
774
  case ARM_t2STRBT:
4619
932
  case ARM_t2STRHT:
4620
1.16k
  case ARM_t2STRi8:
4621
1.60k
  case ARM_t2STRHi8:
4622
2.20k
  case ARM_t2STRBi8:
4623
2.20k
    if (Rn == 15)
4624
4
      return MCDisassembler_Fail;
4625
2.20k
    break;
4626
5.72k
  default:
4627
5.72k
    break;
4628
7.93k
  }
4629
4630
  // Some instructions always use an additive offset.
4631
7.92k
  switch (MCInst_getOpcode(Inst)) {
4632
181
  case ARM_t2LDRT:
4633
592
  case ARM_t2LDRBT:
4634
1.07k
  case ARM_t2LDRHT:
4635
1.27k
  case ARM_t2LDRSBT:
4636
1.81k
  case ARM_t2LDRSHT:
4637
2.00k
  case ARM_t2STRT:
4638
2.58k
  case ARM_t2STRBT:
4639
2.74k
  case ARM_t2STRHT:
4640
2.74k
    imm |= 0x100;
4641
2.74k
    break;
4642
5.18k
  default:
4643
5.18k
    break;
4644
7.92k
  }
4645
4646
7.92k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4647
0
    return MCDisassembler_Fail;
4648
7.92k
  if (!Check(&S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
4649
0
    return MCDisassembler_Fail;
4650
4651
7.92k
  return S;
4652
7.92k
}
4653
4654
#define DEFINE_DecodeTAddrModeImm7(shift) \
4655
  static DecodeStatus CONCAT(DecodeTAddrModeImm7, shift)( \
4656
    MCInst * Inst, unsigned Val, uint64_t Address, \
4657
    const void *Decoder) \
4658
2.76k
  { \
4659
2.76k
    DecodeStatus S = MCDisassembler_Success; \
4660
2.76k
\
4661
2.76k
    unsigned Rn = fieldFromInstruction_4(Val, 8, 3); \
4662
2.76k
    unsigned imm = fieldFromInstruction_4(Val, 0, 8); \
4663
2.76k
\
4664
2.76k
    if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, \
4665
2.76k
                   Decoder))) \
4666
2.76k
      return MCDisassembler_Fail; \
4667
2.76k
    if (!Check(&S, CONCAT(DecodeT2Imm7, shift)(Inst, imm, Address, \
4668
2.76k
                 Decoder))) \
4669
2.76k
      return MCDisassembler_Fail; \
4670
2.76k
\
4671
2.76k
    return S; \
4672
2.76k
  }
ARMDisassembler.c:DecodeTAddrModeImm7_0
Line
Count
Source
4658
1.20k
  { \
4659
1.20k
    DecodeStatus S = MCDisassembler_Success; \
4660
1.20k
\
4661
1.20k
    unsigned Rn = fieldFromInstruction_4(Val, 8, 3); \
4662
1.20k
    unsigned imm = fieldFromInstruction_4(Val, 0, 8); \
4663
1.20k
\
4664
1.20k
    if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, \
4665
1.20k
                   Decoder))) \
4666
1.20k
      return MCDisassembler_Fail; \
4667
1.20k
    if (!Check(&S, CONCAT(DecodeT2Imm7, shift)(Inst, imm, Address, \
4668
1.20k
                 Decoder))) \
4669
1.20k
      return MCDisassembler_Fail; \
4670
1.20k
\
4671
1.20k
    return S; \
4672
1.20k
  }
ARMDisassembler.c:DecodeTAddrModeImm7_1
Line
Count
Source
4658
1.55k
  { \
4659
1.55k
    DecodeStatus S = MCDisassembler_Success; \
4660
1.55k
\
4661
1.55k
    unsigned Rn = fieldFromInstruction_4(Val, 8, 3); \
4662
1.55k
    unsigned imm = fieldFromInstruction_4(Val, 0, 8); \
4663
1.55k
\
4664
1.55k
    if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, \
4665
1.55k
                   Decoder))) \
4666
1.55k
      return MCDisassembler_Fail; \
4667
1.55k
    if (!Check(&S, CONCAT(DecodeT2Imm7, shift)(Inst, imm, Address, \
4668
1.55k
                 Decoder))) \
4669
1.55k
      return MCDisassembler_Fail; \
4670
1.55k
\
4671
1.55k
    return S; \
4672
1.55k
  }
4673
DEFINE_DecodeTAddrModeImm7(0) DEFINE_DecodeTAddrModeImm7(1)
4674
4675
#define DEFINE_DecodeT2AddrModeImm7(shift, WriteBack) \
4676
  static DecodeStatus CONCAT(DecodeT2AddrModeImm7, \
4677
           CONCAT(shift, WriteBack))( \
4678
    MCInst * Inst, unsigned Val, uint64_t Address, \
4679
    const void *Decoder) \
4680
6.27k
  { \
4681
6.27k
    DecodeStatus S = MCDisassembler_Success; \
4682
6.27k
\
4683
6.27k
    unsigned Rn = fieldFromInstruction_4(Val, 8, 4); \
4684
6.27k
    unsigned imm = fieldFromInstruction_4(Val, 0, 8); \
4685
6.27k
    if (WriteBack) { \
4686
3.67k
      if (!Check(&S, DecoderGPRRegisterClass( \
4687
3.67k
                 Inst, Rn, Address, Decoder))) \
4688
3.67k
        return MCDisassembler_Fail; \
4689
3.67k
    } else if (!Check(&S, DecodeGPRnopcRegisterClass( \
4690
2.60k
                Inst, Rn, Address, Decoder))) \
4691
2.60k
      return MCDisassembler_Fail; \
4692
6.27k
    if (!Check(&S, CONCAT(DecodeT2Imm7, shift)(Inst, imm, Address, \
4693
6.27k
                 Decoder))) \
4694
6.27k
      return MCDisassembler_Fail; \
4695
6.27k
\
4696
6.27k
    return S; \
4697
6.27k
  }
ARMDisassembler.c:DecodeT2AddrModeImm7_0_0
Line
Count
Source
4680
1.11k
  { \
4681
1.11k
    DecodeStatus S = MCDisassembler_Success; \
4682
1.11k
\
4683
1.11k
    unsigned Rn = fieldFromInstruction_4(Val, 8, 4); \
4684
1.11k
    unsigned imm = fieldFromInstruction_4(Val, 0, 8); \
4685
1.11k
    if (WriteBack) { \
4686
0
      if (!Check(&S, DecoderGPRRegisterClass( \
4687
0
                 Inst, Rn, Address, Decoder))) \
4688
0
        return MCDisassembler_Fail; \
4689
1.11k
    } else if (!Check(&S, DecodeGPRnopcRegisterClass( \
4690
1.11k
                Inst, Rn, Address, Decoder))) \
4691
1.11k
      return MCDisassembler_Fail; \
4692
1.11k
    if (!Check(&S, CONCAT(DecodeT2Imm7, shift)(Inst, imm, Address, \
4693
1.11k
                 Decoder))) \
4694
1.11k
      return MCDisassembler_Fail; \
4695
1.11k
\
4696
1.11k
    return S; \
4697
1.11k
  }
ARMDisassembler.c:DecodeT2AddrModeImm7_1_0
Line
Count
Source
4680
672
  { \
4681
672
    DecodeStatus S = MCDisassembler_Success; \
4682
672
\
4683
672
    unsigned Rn = fieldFromInstruction_4(Val, 8, 4); \
4684
672
    unsigned imm = fieldFromInstruction_4(Val, 0, 8); \
4685
672
    if (WriteBack) { \
4686
0
      if (!Check(&S, DecoderGPRRegisterClass( \
4687
0
                 Inst, Rn, Address, Decoder))) \
4688
0
        return MCDisassembler_Fail; \
4689
672
    } else if (!Check(&S, DecodeGPRnopcRegisterClass( \
4690
672
                Inst, Rn, Address, Decoder))) \
4691
672
      return MCDisassembler_Fail; \
4692
672
    if (!Check(&S, CONCAT(DecodeT2Imm7, shift)(Inst, imm, Address, \
4693
672
                 Decoder))) \
4694
672
      return MCDisassembler_Fail; \
4695
672
\
4696
672
    return S; \
4697
672
  }
ARMDisassembler.c:DecodeT2AddrModeImm7_0_1
Line
Count
Source
4680
1.39k
  { \
4681
1.39k
    DecodeStatus S = MCDisassembler_Success; \
4682
1.39k
\
4683
1.39k
    unsigned Rn = fieldFromInstruction_4(Val, 8, 4); \
4684
1.39k
    unsigned imm = fieldFromInstruction_4(Val, 0, 8); \
4685
1.39k
    if (WriteBack) { \
4686
1.39k
      if (!Check(&S, DecoderGPRRegisterClass( \
4687
1.39k
                 Inst, Rn, Address, Decoder))) \
4688
1.39k
        return MCDisassembler_Fail; \
4689
1.39k
    } else if (!Check(&S, DecodeGPRnopcRegisterClass( \
4690
0
                Inst, Rn, Address, Decoder))) \
4691
0
      return MCDisassembler_Fail; \
4692
1.39k
    if (!Check(&S, CONCAT(DecodeT2Imm7, shift)(Inst, imm, Address, \
4693
1.39k
                 Decoder))) \
4694
1.39k
      return MCDisassembler_Fail; \
4695
1.39k
\
4696
1.39k
    return S; \
4697
1.39k
  }
ARMDisassembler.c:DecodeT2AddrModeImm7_1_1
Line
Count
Source
4680
558
  { \
4681
558
    DecodeStatus S = MCDisassembler_Success; \
4682
558
\
4683
558
    unsigned Rn = fieldFromInstruction_4(Val, 8, 4); \
4684
558
    unsigned imm = fieldFromInstruction_4(Val, 0, 8); \
4685
558
    if (WriteBack) { \
4686
558
      if (!Check(&S, DecoderGPRRegisterClass( \
4687
558
                 Inst, Rn, Address, Decoder))) \
4688
558
        return MCDisassembler_Fail; \
4689
558
    } else if (!Check(&S, DecodeGPRnopcRegisterClass( \
4690
0
                Inst, Rn, Address, Decoder))) \
4691
0
      return MCDisassembler_Fail; \
4692
558
    if (!Check(&S, CONCAT(DecodeT2Imm7, shift)(Inst, imm, Address, \
4693
558
                 Decoder))) \
4694
558
      return MCDisassembler_Fail; \
4695
558
\
4696
558
    return S; \
4697
558
  }
ARMDisassembler.c:DecodeT2AddrModeImm7_2_0
Line
Count
Source
4680
819
  { \
4681
819
    DecodeStatus S = MCDisassembler_Success; \
4682
819
\
4683
819
    unsigned Rn = fieldFromInstruction_4(Val, 8, 4); \
4684
819
    unsigned imm = fieldFromInstruction_4(Val, 0, 8); \
4685
819
    if (WriteBack) { \
4686
0
      if (!Check(&S, DecoderGPRRegisterClass( \
4687
0
                 Inst, Rn, Address, Decoder))) \
4688
0
        return MCDisassembler_Fail; \
4689
819
    } else if (!Check(&S, DecodeGPRnopcRegisterClass( \
4690
819
                Inst, Rn, Address, Decoder))) \
4691
819
      return MCDisassembler_Fail; \
4692
819
    if (!Check(&S, CONCAT(DecodeT2Imm7, shift)(Inst, imm, Address, \
4693
819
                 Decoder))) \
4694
819
      return MCDisassembler_Fail; \
4695
819
\
4696
819
    return S; \
4697
819
  }
ARMDisassembler.c:DecodeT2AddrModeImm7_2_1
Line
Count
Source
4680
1.72k
  { \
4681
1.72k
    DecodeStatus S = MCDisassembler_Success; \
4682
1.72k
\
4683
1.72k
    unsigned Rn = fieldFromInstruction_4(Val, 8, 4); \
4684
1.72k
    unsigned imm = fieldFromInstruction_4(Val, 0, 8); \
4685
1.72k
    if (WriteBack) { \
4686
1.72k
      if (!Check(&S, DecoderGPRRegisterClass( \
4687
1.72k
                 Inst, Rn, Address, Decoder))) \
4688
1.72k
        return MCDisassembler_Fail; \
4689
1.72k
    } else if (!Check(&S, DecodeGPRnopcRegisterClass( \
4690
0
                Inst, Rn, Address, Decoder))) \
4691
0
      return MCDisassembler_Fail; \
4692
1.72k
    if (!Check(&S, CONCAT(DecodeT2Imm7, shift)(Inst, imm, Address, \
4693
1.72k
                 Decoder))) \
4694
1.72k
      return MCDisassembler_Fail; \
4695
1.72k
\
4696
1.72k
    return S; \
4697
1.72k
  }
4698
  DEFINE_DecodeT2AddrModeImm7(0, 0) DEFINE_DecodeT2AddrModeImm7(1, 0)
4699
    DEFINE_DecodeT2AddrModeImm7(2, 0)
4700
      DEFINE_DecodeT2AddrModeImm7(0, 1)
4701
        DEFINE_DecodeT2AddrModeImm7(1, 1)
4702
          DEFINE_DecodeT2AddrModeImm7(2, 1)
4703
4704
            static DecodeStatus
4705
  DecodeT2LdStPre(MCInst *Inst, unsigned Insn, uint64_t Address,
4706
      const void *Decoder)
4707
6.55k
{
4708
6.55k
  DecodeStatus S = MCDisassembler_Success;
4709
4710
6.55k
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4711
6.55k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4712
6.55k
  unsigned addr = fieldFromInstruction_4(Insn, 0, 8);
4713
6.55k
  addr |= fieldFromInstruction_4(Insn, 9, 1) << 8;
4714
6.55k
  addr |= Rn << 9;
4715
6.55k
  unsigned load = fieldFromInstruction_4(Insn, 20, 1);
4716
4717
6.55k
  if (Rn == 15) {
4718
3.24k
    switch (MCInst_getOpcode(Inst)) {
4719
106
    case ARM_t2LDR_PRE:
4720
348
    case ARM_t2LDR_POST:
4721
348
      MCInst_setOpcode(Inst, (ARM_t2LDRpci));
4722
348
      break;
4723
953
    case ARM_t2LDRB_PRE:
4724
1.31k
    case ARM_t2LDRB_POST:
4725
1.31k
      MCInst_setOpcode(Inst, (ARM_t2LDRBpci));
4726
1.31k
      break;
4727
300
    case ARM_t2LDRH_PRE:
4728
439
    case ARM_t2LDRH_POST:
4729
439
      MCInst_setOpcode(Inst, (ARM_t2LDRHpci));
4730
439
      break;
4731
94
    case ARM_t2LDRSB_PRE:
4732
633
    case ARM_t2LDRSB_POST:
4733
633
      if (Rt == 15)
4734
541
        MCInst_setOpcode(Inst, (ARM_t2PLIpci));
4735
92
      else
4736
92
        MCInst_setOpcode(Inst, (ARM_t2LDRSBpci));
4737
633
      break;
4738
276
    case ARM_t2LDRSH_PRE:
4739
506
    case ARM_t2LDRSH_POST:
4740
506
      MCInst_setOpcode(Inst, (ARM_t2LDRSHpci));
4741
506
      break;
4742
2
    default:
4743
2
      return MCDisassembler_Fail;
4744
3.24k
    }
4745
3.24k
    return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4746
3.24k
  }
4747
4748
3.31k
  if (!load) {
4749
1.57k
    if (!Check(&S,
4750
1.57k
         DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4751
0
      return MCDisassembler_Fail;
4752
1.57k
  }
4753
4754
3.31k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4755
0
    return MCDisassembler_Fail;
4756
4757
3.31k
  if (load) {
4758
1.74k
    if (!Check(&S,
4759
1.74k
         DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4760
0
      return MCDisassembler_Fail;
4761
1.74k
  }
4762
4763
3.31k
  if (!Check(&S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
4764
0
    return MCDisassembler_Fail;
4765
4766
3.31k
  return S;
4767
3.31k
}
4768
4769
static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val,
4770
            uint64_t Address, const void *Decoder)
4771
3.81k
{
4772
3.81k
  DecodeStatus S = MCDisassembler_Success;
4773
4774
3.81k
  unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
4775
3.81k
  unsigned imm = fieldFromInstruction_4(Val, 0, 12);
4776
4777
  // Thumb stores cannot use PC as dest register.
4778
3.81k
  switch (MCInst_getOpcode(Inst)) {
4779
228
  case ARM_t2STRi12:
4780
1.09k
  case ARM_t2STRBi12:
4781
1.59k
  case ARM_t2STRHi12:
4782
1.59k
    if (Rn == 15)
4783
2
      return MCDisassembler_Fail;
4784
1.59k
    break;
4785
2.22k
  default:
4786
2.22k
    break;
4787
3.81k
  }
4788
4789
3.81k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4790
0
    return MCDisassembler_Fail;
4791
3.81k
  MCOperand_CreateImm0(Inst, (imm));
4792
4793
3.81k
  return S;
4794
3.81k
}
4795
4796
static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Insn,
4797
          uint64_t Address, const void *Decoder)
4798
2.93k
{
4799
2.93k
  unsigned imm = fieldFromInstruction_2(Insn, 0, 7);
4800
4801
2.93k
  MCOperand_CreateReg0(Inst, (ARM_SP));
4802
2.93k
  MCOperand_CreateReg0(Inst, (ARM_SP));
4803
2.93k
  MCOperand_CreateImm0(Inst, (imm));
4804
4805
2.93k
  return MCDisassembler_Success;
4806
2.93k
}
4807
4808
static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn,
4809
          uint64_t Address, const void *Decoder)
4810
1.25k
{
4811
1.25k
  DecodeStatus S = MCDisassembler_Success;
4812
4813
1.25k
  if (MCInst_getOpcode(Inst) == ARM_tADDrSP) {
4814
804
    unsigned Rdm = fieldFromInstruction_2(Insn, 0, 3);
4815
804
    Rdm |= fieldFromInstruction_2(Insn, 7, 1) << 3;
4816
4817
804
    if (!Check(&S,
4818
804
         DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4819
0
      return MCDisassembler_Fail;
4820
804
    MCOperand_CreateReg0(Inst, (ARM_SP));
4821
804
    if (!Check(&S,
4822
804
         DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4823
0
      return MCDisassembler_Fail;
4824
804
  } else if (MCInst_getOpcode(Inst) == ARM_tADDspr) {
4825
450
    unsigned Rm = fieldFromInstruction_2(Insn, 3, 4);
4826
4827
450
    MCOperand_CreateReg0(Inst, (ARM_SP));
4828
450
    MCOperand_CreateReg0(Inst, (ARM_SP));
4829
450
    if (!Check(&S,
4830
450
         DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4831
0
      return MCDisassembler_Fail;
4832
450
  }
4833
4834
1.25k
  return S;
4835
1.25k
}
4836
4837
static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn,
4838
           uint64_t Address, const void *Decoder)
4839
502
{
4840
502
  unsigned imod = fieldFromInstruction_2(Insn, 4, 1) | 0x2;
4841
502
  unsigned flags = fieldFromInstruction_2(Insn, 0, 3);
4842
4843
502
  MCOperand_CreateImm0(Inst, (imod));
4844
502
  MCOperand_CreateImm0(Inst, (flags));
4845
4846
502
  return MCDisassembler_Success;
4847
502
}
4848
4849
static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn,
4850
             uint64_t Address, const void *Decoder)
4851
2.35k
{
4852
2.35k
  DecodeStatus S = MCDisassembler_Success;
4853
2.35k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4854
2.35k
  unsigned add = fieldFromInstruction_4(Insn, 4, 1);
4855
4856
2.35k
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
4857
0
    return MCDisassembler_Fail;
4858
2.35k
  MCOperand_CreateImm0(Inst, (add));
4859
4860
2.35k
  return S;
4861
2.35k
}
4862
4863
static DecodeStatus DecodeMveAddrModeRQ(MCInst *Inst, unsigned Insn,
4864
          uint64_t Address, const void *Decoder)
4865
613
{
4866
613
  DecodeStatus S = MCDisassembler_Success;
4867
613
  unsigned Rn = fieldFromInstruction_4(Insn, 3, 4);
4868
613
  unsigned Qm = fieldFromInstruction_4(Insn, 0, 3);
4869
4870
613
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4871
0
    return MCDisassembler_Fail;
4872
613
  if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4873
0
    return MCDisassembler_Fail;
4874
4875
613
  return S;
4876
613
}
4877
4878
#define DEFINE_DecodeMveAddrModeQ(shift) \
4879
  static DecodeStatus CONCAT(DecodeMveAddrModeQ, shift)( \
4880
    MCInst * Inst, unsigned Insn, uint64_t Address, \
4881
    const void *Decoder) \
4882
2.05k
  { \
4883
2.05k
    DecodeStatus S = MCDisassembler_Success; \
4884
2.05k
    unsigned Qm = fieldFromInstruction_4(Insn, 8, 3); \
4885
2.05k
    int imm = fieldFromInstruction_4(Insn, 0, 7); \
4886
2.05k
\
4887
2.05k
    if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, \
4888
2.05k
                   Decoder))) \
4889
2.05k
      return MCDisassembler_Fail; \
4890
2.05k
\
4891
2.05k
    if (!fieldFromInstruction_4(Insn, 7, 1)) { \
4892
1.46k
      if (imm == 0) \
4893
1.46k
        imm = INT32_MIN; \
4894
1.46k
      else \
4895
1.46k
        imm *= -1; \
4896
1.46k
    } \
4897
2.05k
    if (imm != INT32_MIN) \
4898
2.05k
      imm *= (1U << shift); \
4899
2.05k
    MCOperand_CreateImm0(Inst, (imm)); \
4900
2.05k
\
4901
2.05k
    return S; \
4902
2.05k
  }
ARMDisassembler.c:DecodeMveAddrModeQ_2
Line
Count
Source
4882
943
  { \
4883
943
    DecodeStatus S = MCDisassembler_Success; \
4884
943
    unsigned Qm = fieldFromInstruction_4(Insn, 8, 3); \
4885
943
    int imm = fieldFromInstruction_4(Insn, 0, 7); \
4886
943
\
4887
943
    if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, \
4888
943
                   Decoder))) \
4889
943
      return MCDisassembler_Fail; \
4890
943
\
4891
943
    if (!fieldFromInstruction_4(Insn, 7, 1)) { \
4892
634
      if (imm == 0) \
4893
634
        imm = INT32_MIN; \
4894
634
      else \
4895
634
        imm *= -1; \
4896
634
    } \
4897
943
    if (imm != INT32_MIN) \
4898
943
      imm *= (1U << shift); \
4899
943
    MCOperand_CreateImm0(Inst, (imm)); \
4900
943
\
4901
943
    return S; \
4902
943
  }
ARMDisassembler.c:DecodeMveAddrModeQ_3
Line
Count
Source
4882
1.11k
  { \
4883
1.11k
    DecodeStatus S = MCDisassembler_Success; \
4884
1.11k
    unsigned Qm = fieldFromInstruction_4(Insn, 8, 3); \
4885
1.11k
    int imm = fieldFromInstruction_4(Insn, 0, 7); \
4886
1.11k
\
4887
1.11k
    if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, \
4888
1.11k
                   Decoder))) \
4889
1.11k
      return MCDisassembler_Fail; \
4890
1.11k
\
4891
1.11k
    if (!fieldFromInstruction_4(Insn, 7, 1)) { \
4892
834
      if (imm == 0) \
4893
834
        imm = INT32_MIN; \
4894
834
      else \
4895
834
        imm *= -1; \
4896
834
    } \
4897
1.11k
    if (imm != INT32_MIN) \
4898
1.11k
      imm *= (1U << shift); \
4899
1.11k
    MCOperand_CreateImm0(Inst, (imm)); \
4900
1.11k
\
4901
1.11k
    return S; \
4902
1.11k
  }
4903
DEFINE_DecodeMveAddrModeQ(2) DEFINE_DecodeMveAddrModeQ(3)
4904
4905
  static DecodeStatus
4906
  DecodeThumbBLXOffset(MCInst *Inst, unsigned Val, uint64_t Address,
4907
           const void *Decoder)
4908
807
{
4909
  // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
4910
  // Note only one trailing zero not two.  Also the J1 and J2 values are from
4911
  // the encoded instruction.  So here change to I1 and I2 values via:
4912
  // I1 = NOT(J1 EOR S);
4913
  // I2 = NOT(J2 EOR S);
4914
  // and build the imm32 with two trailing zeros as documented:
4915
  // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
4916
807
  unsigned S = (Val >> 23) & 1;
4917
807
  unsigned J1 = (Val >> 22) & 1;
4918
807
  unsigned J2 = (Val >> 21) & 1;
4919
807
  unsigned I1 = !(J1 ^ S);
4920
807
  unsigned I2 = !(J2 ^ S);
4921
807
  unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4922
807
  int imm32 = SignExtend32((tmp << 1), 25);
4923
4924
807
  if (!tryAddingSymbolicOperand(Address, (Address & ~2u) + imm32 + 4,
4925
807
              true, 4, Inst, Decoder))
4926
807
    MCOperand_CreateImm0(Inst, (imm32));
4927
807
  return MCDisassembler_Success;
4928
807
}
4929
4930
static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Val,
4931
              uint64_t Address, const void *Decoder)
4932
41.3k
{
4933
41.3k
  if (Val == 0xA || Val == 0xB)
4934
396
    return MCDisassembler_Fail;
4935
4936
41.0k
  if (!isValidCoprocessorNumber(Inst, Val))
4937
39
    return MCDisassembler_Fail;
4938
4939
40.9k
  MCOperand_CreateImm0(Inst, (Val));
4940
40.9k
  return MCDisassembler_Success;
4941
41.0k
}
4942
4943
static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Insn,
4944
             uint64_t Address,
4945
             const void *Decoder)
4946
477
{
4947
477
  DecodeStatus S = MCDisassembler_Success;
4948
4949
477
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4950
477
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4951
4952
477
  if (Rn == 13 && !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops))
4953
114
    S = MCDisassembler_SoftFail;
4954
477
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4955
0
    return MCDisassembler_Fail;
4956
477
  if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4957
0
    return MCDisassembler_Fail;
4958
477
  return S;
4959
477
}
4960
4961
static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn,
4962
                 uint64_t Address,
4963
                 const void *Decoder)
4964
4.06k
{
4965
4.06k
  DecodeStatus S = MCDisassembler_Success;
4966
4967
4.06k
  unsigned pred = fieldFromInstruction_4(Insn, 22, 4);
4968
4.06k
  if (pred == 0xE || pred == 0xF) {
4969
352
    unsigned opc = fieldFromInstruction_4(Insn, 4, 28);
4970
352
    switch (opc) {
4971
352
    default:
4972
352
      return MCDisassembler_Fail;
4973
0
    case 0xf3bf8f4:
4974
0
      MCInst_setOpcode(Inst, (ARM_t2DSB));
4975
0
      break;
4976
0
    case 0xf3bf8f5:
4977
0
      MCInst_setOpcode(Inst, (ARM_t2DMB));
4978
0
      break;
4979
0
    case 0xf3bf8f6:
4980
0
      MCInst_setOpcode(Inst, (ARM_t2ISB));
4981
0
      break;
4982
352
    }
4983
4984
0
    unsigned imm = fieldFromInstruction_4(Insn, 0, 4);
4985
0
    return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4986
352
  }
4987
4988
3.71k
  unsigned brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1;
4989
3.71k
  brtarget |= fieldFromInstruction_4(Insn, 11, 1) << 19;
4990
3.71k
  brtarget |= fieldFromInstruction_4(Insn, 13, 1) << 18;
4991
3.71k
  brtarget |= fieldFromInstruction_4(Insn, 16, 6) << 12;
4992
3.71k
  brtarget |= fieldFromInstruction_4(Insn, 26, 1) << 20;
4993
4994
3.71k
  if (!Check(&S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4995
0
    return MCDisassembler_Fail;
4996
3.71k
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4997
0
    return MCDisassembler_Fail;
4998
4999
3.71k
  return S;
5000
3.71k
}
5001
5002
// Decode a shifted immediate operand.  These basically consist
5003
// of an 8-bit value, and a 4-bit directive that specifies either
5004
// a splat operation or a rotation.
5005
static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, uint64_t Address,
5006
          const void *Decoder)
5007
7.74k
{
5008
7.74k
  unsigned ctrl = fieldFromInstruction_4(Val, 10, 2);
5009
7.74k
  if (ctrl == 0) {
5010
4.85k
    unsigned byte = fieldFromInstruction_4(Val, 8, 2);
5011
4.85k
    unsigned imm = fieldFromInstruction_4(Val, 0, 8);
5012
4.85k
    switch (byte) {
5013
2.26k
    case 0:
5014
2.26k
      MCOperand_CreateImm0(Inst, (imm));
5015
2.26k
      break;
5016
1.21k
    case 1:
5017
1.21k
      MCOperand_CreateImm0(Inst, ((imm << 16) | imm));
5018
1.21k
      break;
5019
1.05k
    case 2:
5020
1.05k
      MCOperand_CreateImm0(Inst, ((imm << 24) | (imm << 8)));
5021
1.05k
      break;
5022
317
    case 3:
5023
317
      MCOperand_CreateImm0(Inst, ((imm << 24) | (imm << 16) |
5024
317
                (imm << 8) | imm));
5025
317
      break;
5026
4.85k
    }
5027
4.85k
  } else {
5028
2.89k
    unsigned unrot = fieldFromInstruction_4(Val, 0, 7) | 0x80;
5029
2.89k
    unsigned rot = fieldFromInstruction_4(Val, 7, 5);
5030
2.89k
    unsigned imm = (unrot >> rot) | (unrot << ((32 - rot) & 31));
5031
2.89k
    MCOperand_CreateImm0(Inst, (imm));
5032
2.89k
  }
5033
5034
7.74k
  return MCDisassembler_Success;
5035
7.74k
}
5036
5037
static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val,
5038
            uint64_t Address,
5039
            const void *Decoder)
5040
21.5k
{
5041
21.5k
  if (!tryAddingSymbolicOperand(Address,
5042
21.5k
              Address + SignExtend32((Val << 1), 9) + 4,
5043
21.5k
              true, 2, Inst, Decoder))
5044
21.5k
    MCOperand_CreateImm0(Inst, (SignExtend32((Val << 1), 9)));
5045
21.5k
  return MCDisassembler_Success;
5046
21.5k
}
5047
5048
static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val,
5049
                 uint64_t Address,
5050
                 const void *Decoder)
5051
3.09k
{
5052
  // Val is passed in as S:J1:J2:imm10:imm11
5053
  // Note no trailing zero after imm11.  Also the J1 and J2 values are from
5054
  // the encoded instruction.  So here change to I1 and I2 values via:
5055
  // I1 = NOT(J1 EOR S);
5056
  // I2 = NOT(J2 EOR S);
5057
  // and build the imm32 with one trailing zero as documented:
5058
  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
5059
3.09k
  unsigned S = (Val >> 23) & 1;
5060
3.09k
  unsigned J1 = (Val >> 22) & 1;
5061
3.09k
  unsigned J2 = (Val >> 21) & 1;
5062
3.09k
  unsigned I1 = !(J1 ^ S);
5063
3.09k
  unsigned I2 = !(J2 ^ S);
5064
3.09k
  unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
5065
3.09k
  int imm32 = SignExtend32((tmp << 1), 25);
5066
5067
3.09k
  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, true, 4,
5068
3.09k
              Inst, Decoder))
5069
3.09k
    MCOperand_CreateImm0(Inst, (imm32));
5070
3.09k
  return MCDisassembler_Success;
5071
3.09k
}
5072
5073
static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Val,
5074
             uint64_t Address,
5075
             const void *Decoder)
5076
2.84k
{
5077
2.84k
  if (Val & ~0xf)
5078
0
    return MCDisassembler_Fail;
5079
5080
2.84k
  MCOperand_CreateImm0(Inst, (Val));
5081
2.84k
  return MCDisassembler_Success;
5082
2.84k
}
5083
5084
static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val,
5085
            uint64_t Address,
5086
            const void *Decoder)
5087
476
{
5088
476
  if (Val & ~0xf)
5089
0
    return MCDisassembler_Fail;
5090
5091
476
  MCOperand_CreateImm0(Inst, (Val));
5092
476
  return MCDisassembler_Success;
5093
476
}
5094
5095
static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val, uint64_t Address,
5096
          const void *Decoder)
5097
10.3k
{
5098
10.3k
  DecodeStatus S = MCDisassembler_Success;
5099
5100
10.3k
  if (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMClass)) {
5101
8.34k
    unsigned ValLow = Val & 0xff;
5102
5103
    // Validate the SYSm value first.
5104
8.34k
    switch (ValLow) {
5105
431
    case 0:  // apsr
5106
713
    case 1:  // iapsr
5107
915
    case 2:  // eapsr
5108
1.16k
    case 3:  // xpsr
5109
1.28k
    case 5:  // ipsr
5110
1.59k
    case 6:  // epsr
5111
1.84k
    case 7:  // iepsr
5112
1.93k
    case 8:  // msp
5113
2.21k
    case 9:  // psp
5114
2.35k
    case 16: // primask
5115
2.42k
    case 20: // control
5116
2.42k
      break;
5117
74
    case 17: // basepri
5118
187
    case 18: // basepri_max
5119
257
    case 19: // faultmask
5120
257
      if (!(ARM_getFeatureBits(Inst->csh->mode,
5121
257
             ARM_HasV7Ops)))
5122
        // Values basepri, basepri_max and faultmask are only valid for
5123
        // v7m.
5124
0
        return MCDisassembler_Fail;
5125
257
      break;
5126
257
    case 0x8a: // msplim_ns
5127
330
    case 0x8b: // psplim_ns
5128
435
    case 0x91: // basepri_ns
5129
550
    case 0x93: // faultmask_ns
5130
550
      if (!(ARM_getFeatureBits(Inst->csh->mode,
5131
550
             ARM_HasV8MMainlineOps)))
5132
0
        return MCDisassembler_Fail;
5133
      // fall through
5134
845
    case 10:   // msplim
5135
913
    case 11:   // psplim
5136
1.12k
    case 0x88: // msp_ns
5137
1.67k
    case 0x89: // psp_ns
5138
1.75k
    case 0x90: // primask_ns
5139
1.84k
    case 0x94: // control_ns
5140
2.04k
    case 0x98: // sp_ns
5141
2.04k
      if (!(ARM_getFeatureBits(Inst->csh->mode,
5142
2.04k
             ARM_Feature8MSecExt)))
5143
0
        return MCDisassembler_Fail;
5144
2.04k
      break;
5145
2.04k
    case 0x20: // pac_key_p_0
5146
155
    case 0x21: // pac_key_p_1
5147
237
    case 0x22: // pac_key_p_2
5148
439
    case 0x23: // pac_key_p_3
5149
540
    case 0x24: // pac_key_u_0
5150
736
    case 0x25: // pac_key_u_1
5151
804
    case 0x26: // pac_key_u_2
5152
882
    case 0x27: // pac_key_u_3
5153
1.47k
    case 0xa0: // pac_key_p_0_ns
5154
1.54k
    case 0xa1: // pac_key_p_1_ns
5155
1.60k
    case 0xa2: // pac_key_p_2_ns
5156
1.90k
    case 0xa3: // pac_key_p_3_ns
5157
2.10k
    case 0xa4: // pac_key_u_0_ns
5158
2.50k
    case 0xa5: // pac_key_u_1_ns
5159
2.57k
    case 0xa6: // pac_key_u_2_ns
5160
2.77k
    case 0xa7: // pac_key_u_3_ns
5161
2.77k
      if (!(ARM_getFeatureBits(Inst->csh->mode,
5162
2.77k
             ARM_FeaturePACBTI)))
5163
0
        return MCDisassembler_Fail;
5164
2.77k
      break;
5165
2.77k
    default:
5166
      // Architecturally defined as unpredictable
5167
856
      S = MCDisassembler_SoftFail;
5168
856
      break;
5169
8.34k
    }
5170
5171
8.34k
    if (MCInst_getOpcode(Inst) == ARM_t2MSR_M) {
5172
5.76k
      unsigned Mask = fieldFromInstruction_4(Val, 10, 2);
5173
5.76k
      if (!(ARM_getFeatureBits(Inst->csh->mode,
5174
5.76k
             ARM_HasV7Ops))) {
5175
        // The ARMv6-M MSR bits {11-10} can be only 0b10, other values
5176
        // are unpredictable.
5177
0
        if (Mask != 2)
5178
0
          S = MCDisassembler_SoftFail;
5179
5.76k
      } else {
5180
        // The ARMv7-M architecture stores an additional 2-bit mask
5181
        // value in MSR bits {11-10}. The mask is used only with apsr,
5182
        // iapsr, eapsr and xpsr, it has to be 0b10 in other cases. Bit
5183
        // mask{1} indicates if the NZCVQ bits should be moved by the
5184
        // instruction. Bit mask{0} indicates the move for the GE{3:0}
5185
        // bits, the mask{0} bit can be set only if the processor
5186
        // includes the DSP extension.
5187
5.76k
        if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
5188
5.76k
            (!(ARM_getFeatureBits(Inst->csh->mode,
5189
1.76k
                ARM_FeatureDSP)) &&
5190
1.76k
             (Mask & 1)))
5191
4.00k
          S = MCDisassembler_SoftFail;
5192
5.76k
      }
5193
5.76k
    }
5194
8.34k
  } else {
5195
    // A/R class
5196
1.96k
    if (Val == 0)
5197
215
      return MCDisassembler_Fail;
5198
1.96k
  }
5199
10.0k
  MCOperand_CreateImm0(Inst, (Val));
5200
10.0k
  return S;
5201
10.3k
}
5202
5203
static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Val,
5204
            uint64_t Address, const void *Decoder)
5205
1.30k
{
5206
1.30k
  unsigned R = fieldFromInstruction_4(Val, 5, 1);
5207
1.30k
  unsigned SysM = fieldFromInstruction_4(Val, 0, 5);
5208
5209
  // The table of encodings for these banked registers comes from B9.2.3 of
5210
  // the ARM ARM. There are patterns, but nothing regular enough to make this
5211
  // logic neater. So by fiat, these values are UNPREDICTABLE:
5212
1.30k
  if (!ARMBankedReg_lookupBankedRegByEncoding((R << 5) | SysM))
5213
57
    return MCDisassembler_Fail;
5214
5215
1.24k
  MCOperand_CreateImm0(Inst, (Val));
5216
1.24k
  return MCDisassembler_Success;
5217
1.30k
}
5218
5219
static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn,
5220
          uint64_t Address, const void *Decoder)
5221
696
{
5222
696
  DecodeStatus S = MCDisassembler_Success;
5223
5224
696
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
5225
696
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5226
696
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
5227
5228
696
  if (Rn == 0xF)
5229
284
    S = MCDisassembler_SoftFail;
5230
5231
696
  if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
5232
1
    return MCDisassembler_Fail;
5233
695
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5234
0
    return MCDisassembler_Fail;
5235
695
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5236
3
    return MCDisassembler_Fail;
5237
5238
692
  return S;
5239
695
}
5240
5241
static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn,
5242
           uint64_t Address, const void *Decoder)
5243
801
{
5244
801
  DecodeStatus S = MCDisassembler_Success;
5245
5246
801
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
5247
801
  unsigned Rt = fieldFromInstruction_4(Insn, 0, 4);
5248
801
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5249
801
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
5250
5251
801
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
5252
0
    return MCDisassembler_Fail;
5253
5254
801
  if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt + 1)
5255
693
    S = MCDisassembler_SoftFail;
5256
5257
801
  if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
5258
2
    return MCDisassembler_Fail;
5259
799
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5260
0
    return MCDisassembler_Fail;
5261
799
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5262
2
    return MCDisassembler_Fail;
5263
5264
797
  return S;
5265
799
}
5266
5267
static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn,
5268
            uint64_t Address, const void *Decoder)
5269
2.93k
{
5270
2.93k
  DecodeStatus S = MCDisassembler_Success;
5271
5272
2.93k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5273
2.93k
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
5274
2.93k
  unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
5275
2.93k
  imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
5276
2.93k
  imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
5277
2.93k
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
5278
5279
2.93k
  if (Rn == 0xF || Rn == Rt)
5280
732
    S = MCDisassembler_SoftFail;
5281
5282
2.93k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5283
0
    return MCDisassembler_Fail;
5284
2.93k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5285
0
    return MCDisassembler_Fail;
5286
2.93k
  if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
5287
0
    return MCDisassembler_Fail;
5288
2.93k
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5289
15
    return MCDisassembler_Fail;
5290
5291
2.92k
  return S;
5292
2.93k
}
5293
5294
static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn,
5295
            uint64_t Address, const void *Decoder)
5296
1.43k
{
5297
1.43k
  DecodeStatus S = MCDisassembler_Success;
5298
5299
1.43k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5300
1.43k
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
5301
1.43k
  unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
5302
1.43k
  imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
5303
1.43k
  imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
5304
1.43k
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
5305
1.43k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
5306
5307
1.43k
  if (Rn == 0xF || Rn == Rt)
5308
724
    S = MCDisassembler_SoftFail;
5309
1.43k
  if (Rm == 0xF)
5310
112
    S = MCDisassembler_SoftFail;
5311
5312
1.43k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5313
0
    return MCDisassembler_Fail;
5314
1.43k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5315
0
    return MCDisassembler_Fail;
5316
1.43k
  if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
5317
0
    return MCDisassembler_Fail;
5318
1.43k
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5319
2
    return MCDisassembler_Fail;
5320
5321
1.43k
  return S;
5322
1.43k
}
5323
5324
static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn,
5325
            uint64_t Address, const void *Decoder)
5326
3.14k
{
5327
3.14k
  DecodeStatus S = MCDisassembler_Success;
5328
5329
3.14k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5330
3.14k
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
5331
3.14k
  unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
5332
3.14k
  imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
5333
3.14k
  imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
5334
3.14k
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
5335
5336
3.14k
  if (Rn == 0xF || Rn == Rt)
5337
577
    S = MCDisassembler_SoftFail;
5338
5339
3.14k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5340
0
    return MCDisassembler_Fail;
5341
3.14k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5342
0
    return MCDisassembler_Fail;
5343
3.14k
  if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
5344
0
    return MCDisassembler_Fail;
5345
3.14k
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5346
2
    return MCDisassembler_Fail;
5347
5348
3.14k
  return S;
5349
3.14k
}
5350
5351
static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn,
5352
            uint64_t Address, const void *Decoder)
5353
2.10k
{
5354
2.10k
  DecodeStatus S = MCDisassembler_Success;
5355
5356
2.10k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5357
2.10k
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
5358
2.10k
  unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
5359
2.10k
  imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
5360
2.10k
  imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
5361
2.10k
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
5362
5363
2.10k
  if (Rn == 0xF || Rn == Rt)
5364
760
    S = MCDisassembler_SoftFail;
5365
5366
2.10k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5367
0
    return MCDisassembler_Fail;
5368
2.10k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5369
0
    return MCDisassembler_Fail;
5370
2.10k
  if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
5371
0
    return MCDisassembler_Fail;
5372
2.10k
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5373
2
    return MCDisassembler_Fail;
5374
5375
2.10k
  return S;
5376
2.10k
}
5377
5378
static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, uint64_t Address,
5379
         const void *Decoder)
5380
1.58k
{
5381
1.58k
  DecodeStatus S = MCDisassembler_Success;
5382
5383
1.58k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5384
1.58k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
5385
1.58k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
5386
1.58k
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
5387
1.58k
  unsigned size = fieldFromInstruction_4(Insn, 10, 2);
5388
5389
1.58k
  unsigned align = 0;
5390
1.58k
  unsigned index = 0;
5391
1.58k
  switch (size) {
5392
0
  default:
5393
0
    return MCDisassembler_Fail;
5394
559
  case 0:
5395
559
    if (fieldFromInstruction_4(Insn, 4, 1))
5396
0
      return MCDisassembler_Fail; // UNDEFINED
5397
559
    index = fieldFromInstruction_4(Insn, 5, 3);
5398
559
    break;
5399
691
  case 1:
5400
691
    if (fieldFromInstruction_4(Insn, 5, 1))
5401
2
      return MCDisassembler_Fail; // UNDEFINED
5402
689
    index = fieldFromInstruction_4(Insn, 6, 2);
5403
689
    if (fieldFromInstruction_4(Insn, 4, 1))
5404
300
      align = 2;
5405
689
    break;
5406
333
  case 2:
5407
333
    if (fieldFromInstruction_4(Insn, 6, 1))
5408
0
      return MCDisassembler_Fail; // UNDEFINED
5409
333
    index = fieldFromInstruction_4(Insn, 7, 1);
5410
5411
333
    switch (fieldFromInstruction_4(Insn, 4, 2)) {
5412
244
    case 0:
5413
244
      align = 0;
5414
244
      break;
5415
86
    case 3:
5416
86
      align = 4;
5417
86
      break;
5418
3
    default:
5419
3
      return MCDisassembler_Fail;
5420
333
    }
5421
330
    break;
5422
1.58k
  }
5423
5424
1.57k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5425
0
    return MCDisassembler_Fail;
5426
1.57k
  if (Rm != 0xF) { // Writeback
5427
1.08k
    if (!Check(&S,
5428
1.08k
         DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5429
0
      return MCDisassembler_Fail;
5430
1.08k
  }
5431
1.57k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5432
0
    return MCDisassembler_Fail;
5433
1.57k
  MCOperand_CreateImm0(Inst, (align));
5434
1.57k
  if (Rm != 0xF) {
5435
1.08k
    if (Rm != 0xD) {
5436
639
      if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address,
5437
639
                    Decoder)))
5438
0
        return MCDisassembler_Fail;
5439
639
    } else
5440
448
      MCOperand_CreateReg0(Inst, (0));
5441
1.08k
  }
5442
5443
1.57k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5444
0
    return MCDisassembler_Fail;
5445
1.57k
  MCOperand_CreateImm0(Inst, (index));
5446
5447
1.57k
  return S;
5448
1.57k
}
5449
5450
static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, uint64_t Address,
5451
         const void *Decoder)
5452
1.55k
{
5453
1.55k
  DecodeStatus S = MCDisassembler_Success;
5454
5455
1.55k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5456
1.55k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
5457
1.55k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
5458
1.55k
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
5459
1.55k
  unsigned size = fieldFromInstruction_4(Insn, 10, 2);
5460
5461
1.55k
  unsigned align = 0;
5462
1.55k
  unsigned index = 0;
5463
1.55k
  switch (size) {
5464
0
  default:
5465
0
    return MCDisassembler_Fail;
5466
495
  case 0:
5467
495
    if (fieldFromInstruction_4(Insn, 4, 1))
5468
0
      return MCDisassembler_Fail; // UNDEFINED
5469
495
    index = fieldFromInstruction_4(Insn, 5, 3);
5470
495
    break;
5471
769
  case 1:
5472
769
    if (fieldFromInstruction_4(Insn, 5, 1))
5473
0
      return MCDisassembler_Fail; // UNDEFINED
5474
769
    index = fieldFromInstruction_4(Insn, 6, 2);
5475
769
    if (fieldFromInstruction_4(Insn, 4, 1))
5476
253
      align = 2;
5477
769
    break;
5478
294
  case 2:
5479
294
    if (fieldFromInstruction_4(Insn, 6, 1))
5480
0
      return MCDisassembler_Fail; // UNDEFINED
5481
294
    index = fieldFromInstruction_4(Insn, 7, 1);
5482
5483
294
    switch (fieldFromInstruction_4(Insn, 4, 2)) {
5484
145
    case 0:
5485
145
      align = 0;
5486
145
      break;
5487
145
    case 3:
5488
145
      align = 4;
5489
145
      break;
5490
4
    default:
5491
4
      return MCDisassembler_Fail;
5492
294
    }
5493
290
    break;
5494
1.55k
  }
5495
5496
1.55k
  if (Rm != 0xF) { // Writeback
5497
1.03k
    if (!Check(&S,
5498
1.03k
         DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5499
0
      return MCDisassembler_Fail;
5500
1.03k
  }
5501
1.55k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5502
0
    return MCDisassembler_Fail;
5503
1.55k
  MCOperand_CreateImm0(Inst, (align));
5504
1.55k
  if (Rm != 0xF) {
5505
1.03k
    if (Rm != 0xD) {
5506
444
      if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address,
5507
444
                    Decoder)))
5508
0
        return MCDisassembler_Fail;
5509
444
    } else
5510
588
      MCOperand_CreateReg0(Inst, (0));
5511
1.03k
  }
5512
5513
1.55k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5514
0
    return MCDisassembler_Fail;
5515
1.55k
  MCOperand_CreateImm0(Inst, (index));
5516
5517
1.55k
  return S;
5518
1.55k
}
5519
5520
static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, uint64_t Address,
5521
         const void *Decoder)
5522
2.61k
{
5523
2.61k
  DecodeStatus S = MCDisassembler_Success;
5524
5525
2.61k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5526
2.61k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
5527
2.61k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
5528
2.61k
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
5529
2.61k
  unsigned size = fieldFromInstruction_4(Insn, 10, 2);
5530
5531
2.61k
  unsigned align = 0;
5532
2.61k
  unsigned index = 0;
5533
2.61k
  unsigned inc = 1;
5534
2.61k
  switch (size) {
5535
0
  default:
5536
0
    return MCDisassembler_Fail;
5537
1.15k
  case 0:
5538
1.15k
    index = fieldFromInstruction_4(Insn, 5, 3);
5539
1.15k
    if (fieldFromInstruction_4(Insn, 4, 1))
5540
700
      align = 2;
5541
1.15k
    break;
5542
976
  case 1:
5543
976
    index = fieldFromInstruction_4(Insn, 6, 2);
5544
976
    if (fieldFromInstruction_4(Insn, 4, 1))
5545
157
      align = 4;
5546
976
    if (fieldFromInstruction_4(Insn, 5, 1))
5547
605
      inc = 2;
5548
976
    break;
5549
483
  case 2:
5550
483
    if (fieldFromInstruction_4(Insn, 5, 1))
5551
0
      return MCDisassembler_Fail; // UNDEFINED
5552
483
    index = fieldFromInstruction_4(Insn, 7, 1);
5553
483
    if (fieldFromInstruction_4(Insn, 4, 1) != 0)
5554
321
      align = 8;
5555
483
    if (fieldFromInstruction_4(Insn, 6, 1))
5556
124
      inc = 2;
5557
483
    break;
5558
2.61k
  }
5559
5560
2.61k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5561
0
    return MCDisassembler_Fail;
5562
2.61k
  if (!Check(&S,
5563
2.61k
       DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
5564
2
    return MCDisassembler_Fail;
5565
2.60k
  if (Rm != 0xF) { // Writeback
5566
1.67k
    if (!Check(&S,
5567
1.67k
         DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5568
0
      return MCDisassembler_Fail;
5569
1.67k
  }
5570
2.60k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5571
0
    return MCDisassembler_Fail;
5572
2.60k
  MCOperand_CreateImm0(Inst, (align));
5573
2.60k
  if (Rm != 0xF) {
5574
1.67k
    if (Rm != 0xD) {
5575
1.20k
      if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address,
5576
1.20k
                    Decoder)))
5577
0
        return MCDisassembler_Fail;
5578
1.20k
    } else
5579
470
      MCOperand_CreateReg0(Inst, (0));
5580
1.67k
  }
5581
5582
2.60k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5583
0
    return MCDisassembler_Fail;
5584
2.60k
  if (!Check(&S,
5585
2.60k
       DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
5586
0
    return MCDisassembler_Fail;
5587
2.60k
  MCOperand_CreateImm0(Inst, (index));
5588
5589
2.60k
  return S;
5590
2.60k
}
5591
5592
static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, uint64_t Address,
5593
         const void *Decoder)
5594
3.34k
{
5595
3.34k
  DecodeStatus S = MCDisassembler_Success;
5596
5597
3.34k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5598
3.34k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
5599
3.34k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
5600
3.34k
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
5601
3.34k
  unsigned size = fieldFromInstruction_4(Insn, 10, 2);
5602
5603
3.34k
  unsigned align = 0;
5604
3.34k
  unsigned index = 0;
5605
3.34k
  unsigned inc = 1;
5606
3.34k
  switch (size) {
5607
0
  default:
5608
0
    return MCDisassembler_Fail;
5609
1.06k
  case 0:
5610
1.06k
    index = fieldFromInstruction_4(Insn, 5, 3);
5611
1.06k
    if (fieldFromInstruction_4(Insn, 4, 1))
5612
542
      align = 2;
5613
1.06k
    break;
5614
1.22k
  case 1:
5615
1.22k
    index = fieldFromInstruction_4(Insn, 6, 2);
5616
1.22k
    if (fieldFromInstruction_4(Insn, 4, 1))
5617
495
      align = 4;
5618
1.22k
    if (fieldFromInstruction_4(Insn, 5, 1))
5619
308
      inc = 2;
5620
1.22k
    break;
5621
1.05k
  case 2:
5622
1.05k
    if (fieldFromInstruction_4(Insn, 5, 1))
5623
0
      return MCDisassembler_Fail; // UNDEFINED
5624
1.05k
    index = fieldFromInstruction_4(Insn, 7, 1);
5625
1.05k
    if (fieldFromInstruction_4(Insn, 4, 1) != 0)
5626
515
      align = 8;
5627
1.05k
    if (fieldFromInstruction_4(Insn, 6, 1))
5628
564
      inc = 2;
5629
1.05k
    break;
5630
3.34k
  }
5631
5632
3.34k
  if (Rm != 0xF) { // Writeback
5633
2.06k
    if (!Check(&S,
5634
2.06k
         DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5635
0
      return MCDisassembler_Fail;
5636
2.06k
  }
5637
3.34k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5638
0
    return MCDisassembler_Fail;
5639
3.34k
  MCOperand_CreateImm0(Inst, (align));
5640
3.34k
  if (Rm != 0xF) {
5641
2.06k
    if (Rm != 0xD) {
5642
1.31k
      if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address,
5643
1.31k
                    Decoder)))
5644
0
        return MCDisassembler_Fail;
5645
1.31k
    } else
5646
757
      MCOperand_CreateReg0(Inst, (0));
5647
2.06k
  }
5648
5649
3.34k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5650
0
    return MCDisassembler_Fail;
5651
3.34k
  if (!Check(&S,
5652
3.34k
       DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
5653
3
    return MCDisassembler_Fail;
5654
3.34k
  MCOperand_CreateImm0(Inst, (index));
5655
5656
3.34k
  return S;
5657
3.34k
}
5658
5659
static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, uint64_t Address,
5660
         const void *Decoder)
5661
1.82k
{
5662
1.82k
  DecodeStatus S = MCDisassembler_Success;
5663
5664
1.82k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5665
1.82k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
5666
1.82k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
5667
1.82k
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
5668
1.82k
  unsigned size = fieldFromInstruction_4(Insn, 10, 2);
5669
5670
1.82k
  unsigned align = 0;
5671
1.82k
  unsigned index = 0;
5672
1.82k
  unsigned inc = 1;
5673
1.82k
  switch (size) {
5674
0
  default:
5675
0
    return MCDisassembler_Fail;
5676
353
  case 0:
5677
353
    if (fieldFromInstruction_4(Insn, 4, 1))
5678
0
      return MCDisassembler_Fail; // UNDEFINED
5679
353
    index = fieldFromInstruction_4(Insn, 5, 3);
5680
353
    break;
5681
1.04k
  case 1:
5682
1.04k
    if (fieldFromInstruction_4(Insn, 4, 1))
5683
0
      return MCDisassembler_Fail; // UNDEFINED
5684
1.04k
    index = fieldFromInstruction_4(Insn, 6, 2);
5685
1.04k
    if (fieldFromInstruction_4(Insn, 5, 1))
5686
315
      inc = 2;
5687
1.04k
    break;
5688
433
  case 2:
5689
433
    if (fieldFromInstruction_4(Insn, 4, 2))
5690
0
      return MCDisassembler_Fail; // UNDEFINED
5691
433
    index = fieldFromInstruction_4(Insn, 7, 1);
5692
433
    if (fieldFromInstruction_4(Insn, 6, 1))
5693
313
      inc = 2;
5694
433
    break;
5695
1.82k
  }
5696
5697
1.82k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5698
0
    return MCDisassembler_Fail;
5699
1.82k
  if (!Check(&S,
5700
1.82k
       DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
5701
3
    return MCDisassembler_Fail;
5702
1.82k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address,
5703
1.82k
                Decoder)))
5704
2
    return MCDisassembler_Fail;
5705
5706
1.82k
  if (Rm != 0xF) { // Writeback
5707
1.49k
    if (!Check(&S,
5708
1.49k
         DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5709
0
      return MCDisassembler_Fail;
5710
1.49k
  }
5711
1.82k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5712
0
    return MCDisassembler_Fail;
5713
1.82k
  MCOperand_CreateImm0(Inst, (align));
5714
1.82k
  if (Rm != 0xF) {
5715
1.49k
    if (Rm != 0xD) {
5716
652
      if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address,
5717
652
                    Decoder)))
5718
0
        return MCDisassembler_Fail;
5719
652
    } else
5720
845
      MCOperand_CreateReg0(Inst, (0));
5721
1.49k
  }
5722
5723
1.82k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5724
0
    return MCDisassembler_Fail;
5725
1.82k
  if (!Check(&S,
5726
1.82k
       DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
5727
0
    return MCDisassembler_Fail;
5728
1.82k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address,
5729
1.82k
                Decoder)))
5730
0
    return MCDisassembler_Fail;
5731
1.82k
  MCOperand_CreateImm0(Inst, (index));
5732
5733
1.82k
  return S;
5734
1.82k
}
5735
5736
static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, uint64_t Address,
5737
         const void *Decoder)
5738
1.77k
{
5739
1.77k
  DecodeStatus S = MCDisassembler_Success;
5740
5741
1.77k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5742
1.77k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
5743
1.77k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
5744
1.77k
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
5745
1.77k
  unsigned size = fieldFromInstruction_4(Insn, 10, 2);
5746
5747
1.77k
  unsigned align = 0;
5748
1.77k
  unsigned index = 0;
5749
1.77k
  unsigned inc = 1;
5750
1.77k
  switch (size) {
5751
0
  default:
5752
0
    return MCDisassembler_Fail;
5753
431
  case 0:
5754
431
    if (fieldFromInstruction_4(Insn, 4, 1))
5755
0
      return MCDisassembler_Fail; // UNDEFINED
5756
431
    index = fieldFromInstruction_4(Insn, 5, 3);
5757
431
    break;
5758
496
  case 1:
5759
496
    if (fieldFromInstruction_4(Insn, 4, 1))
5760
0
      return MCDisassembler_Fail; // UNDEFINED
5761
496
    index = fieldFromInstruction_4(Insn, 6, 2);
5762
496
    if (fieldFromInstruction_4(Insn, 5, 1))
5763
131
      inc = 2;
5764
496
    break;
5765
846
  case 2:
5766
846
    if (fieldFromInstruction_4(Insn, 4, 2))
5767
0
      return MCDisassembler_Fail; // UNDEFINED
5768
846
    index = fieldFromInstruction_4(Insn, 7, 1);
5769
846
    if (fieldFromInstruction_4(Insn, 6, 1))
5770
360
      inc = 2;
5771
846
    break;
5772
1.77k
  }
5773
5774
1.77k
  if (Rm != 0xF) { // Writeback
5775
801
    if (!Check(&S,
5776
801
         DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5777
0
      return MCDisassembler_Fail;
5778
801
  }
5779
1.77k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5780
0
    return MCDisassembler_Fail;
5781
1.77k
  MCOperand_CreateImm0(Inst, (align));
5782
1.77k
  if (Rm != 0xF) {
5783
801
    if (Rm != 0xD) {
5784
602
      if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address,
5785
602
                    Decoder)))
5786
0
        return MCDisassembler_Fail;
5787
602
    } else
5788
199
      MCOperand_CreateReg0(Inst, (0));
5789
801
  }
5790
5791
1.77k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5792
0
    return MCDisassembler_Fail;
5793
1.77k
  if (!Check(&S,
5794
1.77k
       DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
5795
2
    return MCDisassembler_Fail;
5796
1.77k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address,
5797
1.77k
                Decoder)))
5798
2
    return MCDisassembler_Fail;
5799
1.76k
  MCOperand_CreateImm0(Inst, (index));
5800
5801
1.76k
  return S;
5802
1.77k
}
5803
5804
static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, uint64_t Address,
5805
         const void *Decoder)
5806
2.95k
{
5807
2.95k
  DecodeStatus S = MCDisassembler_Success;
5808
5809
2.95k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5810
2.95k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
5811
2.95k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
5812
2.95k
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
5813
2.95k
  unsigned size = fieldFromInstruction_4(Insn, 10, 2);
5814
5815
2.95k
  unsigned align = 0;
5816
2.95k
  unsigned index = 0;
5817
2.95k
  unsigned inc = 1;
5818
2.95k
  switch (size) {
5819
0
  default:
5820
0
    return MCDisassembler_Fail;
5821
1.10k
  case 0:
5822
1.10k
    if (fieldFromInstruction_4(Insn, 4, 1))
5823
317
      align = 4;
5824
1.10k
    index = fieldFromInstruction_4(Insn, 5, 3);
5825
1.10k
    break;
5826
1.31k
  case 1:
5827
1.31k
    if (fieldFromInstruction_4(Insn, 4, 1))
5828
654
      align = 8;
5829
1.31k
    index = fieldFromInstruction_4(Insn, 6, 2);
5830
1.31k
    if (fieldFromInstruction_4(Insn, 5, 1))
5831
444
      inc = 2;
5832
1.31k
    break;
5833
539
  case 2:
5834
539
    switch (fieldFromInstruction_4(Insn, 4, 2)) {
5835
347
    case 0:
5836
347
      align = 0;
5837
347
      break;
5838
4
    case 3:
5839
4
      return MCDisassembler_Fail;
5840
188
    default:
5841
188
      align = 4 << fieldFromInstruction_4(Insn, 4, 2);
5842
188
      break;
5843
539
    }
5844
5845
535
    index = fieldFromInstruction_4(Insn, 7, 1);
5846
535
    if (fieldFromInstruction_4(Insn, 6, 1))
5847
209
      inc = 2;
5848
535
    break;
5849
2.95k
  }
5850
5851
2.95k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5852
0
    return MCDisassembler_Fail;
5853
2.95k
  if (!Check(&S,
5854
2.95k
       DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
5855
1
    return MCDisassembler_Fail;
5856
2.95k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address,
5857
2.95k
                Decoder)))
5858
2
    return MCDisassembler_Fail;
5859
2.94k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3 * inc, Address,
5860
2.94k
                Decoder)))
5861
1
    return MCDisassembler_Fail;
5862
5863
2.94k
  if (Rm != 0xF) { // Writeback
5864
1.79k
    if (!Check(&S,
5865
1.79k
         DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5866
0
      return MCDisassembler_Fail;
5867
1.79k
  }
5868
2.94k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5869
0
    return MCDisassembler_Fail;
5870
2.94k
  MCOperand_CreateImm0(Inst, (align));
5871
2.94k
  if (Rm != 0xF) {
5872
1.79k
    if (Rm != 0xD) {
5873
1.28k
      if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address,
5874
1.28k
                    Decoder)))
5875
0
        return MCDisassembler_Fail;
5876
1.28k
    } else
5877
514
      MCOperand_CreateReg0(Inst, (0));
5878
1.79k
  }
5879
5880
2.94k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5881
0
    return MCDisassembler_Fail;
5882
2.94k
  if (!Check(&S,
5883
2.94k
       DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
5884
0
    return MCDisassembler_Fail;
5885
2.94k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address,
5886
2.94k
                Decoder)))
5887
0
    return MCDisassembler_Fail;
5888
2.94k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3 * inc, Address,
5889
2.94k
                Decoder)))
5890
0
    return MCDisassembler_Fail;
5891
2.94k
  MCOperand_CreateImm0(Inst, (index));
5892
5893
2.94k
  return S;
5894
2.94k
}
5895
5896
static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, uint64_t Address,
5897
         const void *Decoder)
5898
3.28k
{
5899
3.28k
  DecodeStatus S = MCDisassembler_Success;
5900
5901
3.28k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5902
3.28k
  unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
5903
3.28k
  unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
5904
3.28k
  Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
5905
3.28k
  unsigned size = fieldFromInstruction_4(Insn, 10, 2);
5906
5907
3.28k
  unsigned align = 0;
5908
3.28k
  unsigned index = 0;
5909
3.28k
  unsigned inc = 1;
5910
3.28k
  switch (size) {
5911
0
  default:
5912
0
    return MCDisassembler_Fail;
5913
898
  case 0:
5914
898
    if (fieldFromInstruction_4(Insn, 4, 1))
5915
293
      align = 4;
5916
898
    index = fieldFromInstruction_4(Insn, 5, 3);
5917
898
    break;
5918
1.24k
  case 1:
5919
1.24k
    if (fieldFromInstruction_4(Insn, 4, 1))
5920
611
      align = 8;
5921
1.24k
    index = fieldFromInstruction_4(Insn, 6, 2);
5922
1.24k
    if (fieldFromInstruction_4(Insn, 5, 1))
5923
292
      inc = 2;
5924
1.24k
    break;
5925
1.14k
  case 2:
5926
1.14k
    switch (fieldFromInstruction_4(Insn, 4, 2)) {
5927
856
    case 0:
5928
856
      align = 0;
5929
856
      break;
5930
2
    case 3:
5931
2
      return MCDisassembler_Fail;
5932
285
    default:
5933
285
      align = 4 << fieldFromInstruction_4(Insn, 4, 2);
5934
285
      break;
5935
1.14k
    }
5936
5937
1.14k
    index = fieldFromInstruction_4(Insn, 7, 1);
5938
1.14k
    if (fieldFromInstruction_4(Insn, 6, 1))
5939
565
      inc = 2;
5940
1.14k
    break;
5941
3.28k
  }
5942
5943
3.28k
  if (Rm != 0xF) { // Writeback
5944
1.56k
    if (!Check(&S,
5945
1.56k
         DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5946
0
      return MCDisassembler_Fail;
5947
1.56k
  }
5948
3.28k
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5949
0
    return MCDisassembler_Fail;
5950
3.28k
  MCOperand_CreateImm0(Inst, (align));
5951
3.28k
  if (Rm != 0xF) {
5952
1.56k
    if (Rm != 0xD) {
5953
1.14k
      if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address,
5954
1.14k
                    Decoder)))
5955
0
        return MCDisassembler_Fail;
5956
1.14k
    } else
5957
428
      MCOperand_CreateReg0(Inst, (0));
5958
1.56k
  }
5959
5960
3.28k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5961
0
    return MCDisassembler_Fail;
5962
3.28k
  if (!Check(&S,
5963
3.28k
       DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
5964
2
    return MCDisassembler_Fail;
5965
3.27k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address,
5966
3.27k
                Decoder)))
5967
1
    return MCDisassembler_Fail;
5968
3.27k
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3 * inc, Address,
5969
3.27k
                Decoder)))
5970
2
    return MCDisassembler_Fail;
5971
3.27k
  MCOperand_CreateImm0(Inst, (index));
5972
5973
3.27k
  return S;
5974
3.27k
}
5975
5976
static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, uint64_t Address,
5977
          const void *Decoder)
5978
461
{
5979
461
  DecodeStatus S = MCDisassembler_Success;
5980
461
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
5981
461
  unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
5982
461
  unsigned Rm = fieldFromInstruction_4(Insn, 5, 1);
5983
461
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
5984
461
  Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1;
5985
5986
461
  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5987
252
    S = MCDisassembler_SoftFail;
5988
5989
461
  if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm, Address, Decoder)))
5990
0
    return MCDisassembler_Fail;
5991
461
  if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder)))
5992
1
    return MCDisassembler_Fail;
5993
460
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5994
0
    return MCDisassembler_Fail;
5995
460
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5996
0
    return MCDisassembler_Fail;
5997
460
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5998
2
    return MCDisassembler_Fail;
5999
6000
458
  return S;
6001
460
}
6002
6003
static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, uint64_t Address,
6004
          const void *Decoder)
6005
557
{
6006
557
  DecodeStatus S = MCDisassembler_Success;
6007
557
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
6008
557
  unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
6009
557
  unsigned Rm = fieldFromInstruction_4(Insn, 5, 1);
6010
557
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
6011
557
  Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1;
6012
6013
557
  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
6014
452
    S = MCDisassembler_SoftFail;
6015
6016
557
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
6017
0
    return MCDisassembler_Fail;
6018
557
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
6019
0
    return MCDisassembler_Fail;
6020
557
  if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm, Address, Decoder)))
6021
0
    return MCDisassembler_Fail;
6022
557
  if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder)))
6023
2
    return MCDisassembler_Fail;
6024
555
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
6025
3
    return MCDisassembler_Fail;
6026
6027
552
  return S;
6028
555
}
6029
6030
static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn, uint64_t Address,
6031
           const void *Decoder)
6032
11.2k
{
6033
11.2k
  DecodeStatus S = MCDisassembler_Success;
6034
11.2k
  unsigned pred = fieldFromInstruction_4(Insn, 4, 4);
6035
11.2k
  unsigned mask = fieldFromInstruction_4(Insn, 0, 4);
6036
6037
11.2k
  if (pred == 0xF) {
6038
1.55k
    pred = 0xE;
6039
1.55k
    S = MCDisassembler_SoftFail;
6040
1.55k
  }
6041
6042
11.2k
  if (mask == 0x0)
6043
0
    return MCDisassembler_Fail;
6044
6045
  // IT masks are encoded as a sequence of replacement low-order bits
6046
  // for the condition code. So if the low bit of the starting
6047
  // condition code is 1, then we have to flip all the bits above the
6048
  // terminating bit (which is the lowest 1 bit).
6049
11.2k
  if (pred & 1) {
6050
5.92k
    unsigned LowBit = mask & -mask;
6051
5.92k
    unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
6052
5.92k
    mask ^= BitsAboveLowBit;
6053
5.92k
  }
6054
6055
11.2k
  MCOperand_CreateImm0(Inst, (pred));
6056
11.2k
  MCOperand_CreateImm0(Inst, (mask));
6057
11.2k
  return S;
6058
11.2k
}
6059
6060
static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn,
6061
                 uint64_t Address,
6062
                 const void *Decoder)
6063
3.54k
{
6064
3.54k
  DecodeStatus S = MCDisassembler_Success;
6065
6066
3.54k
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
6067
3.54k
  unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4);
6068
3.54k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
6069
3.54k
  unsigned addr = fieldFromInstruction_4(Insn, 0, 8);
6070
3.54k
  unsigned W = fieldFromInstruction_4(Insn, 21, 1);
6071
3.54k
  unsigned U = fieldFromInstruction_4(Insn, 23, 1);
6072
3.54k
  unsigned P = fieldFromInstruction_4(Insn, 24, 1);
6073
3.54k
  bool writeback = (W == 1) | (P == 0);
6074
6075
3.54k
  addr |= (U << 8) | (Rn << 9);
6076
6077
3.54k
  if (writeback && (Rn == Rt || Rn == Rt2))
6078
1.65k
    Check(&S, MCDisassembler_SoftFail);
6079
3.54k
  if (Rt == Rt2)
6080
523
    Check(&S, MCDisassembler_SoftFail);
6081
6082
  // Rt
6083
3.54k
  if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
6084
0
    return MCDisassembler_Fail;
6085
  // Rt2
6086
3.54k
  if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
6087
0
    return MCDisassembler_Fail;
6088
  // Writeback operand
6089
3.54k
  if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
6090
0
    return MCDisassembler_Fail;
6091
  // addr
6092
3.54k
  if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
6093
0
    return MCDisassembler_Fail;
6094
6095
3.54k
  return S;
6096
3.54k
}
6097
6098
static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn,
6099
                 uint64_t Address,
6100
                 const void *Decoder)
6101
5.44k
{
6102
5.44k
  DecodeStatus S = MCDisassembler_Success;
6103
6104
5.44k
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
6105
5.44k
  unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4);
6106
5.44k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
6107
5.44k
  unsigned addr = fieldFromInstruction_4(Insn, 0, 8);
6108
5.44k
  unsigned W = fieldFromInstruction_4(Insn, 21, 1);
6109
5.44k
  unsigned U = fieldFromInstruction_4(Insn, 23, 1);
6110
5.44k
  unsigned P = fieldFromInstruction_4(Insn, 24, 1);
6111
5.44k
  bool writeback = (W == 1) | (P == 0);
6112
6113
5.44k
  addr |= (U << 8) | (Rn << 9);
6114
6115
5.44k
  if (writeback && (Rn == Rt || Rn == Rt2))
6116
1.73k
    Check(&S, MCDisassembler_SoftFail);
6117
6118
  // Writeback operand
6119
5.44k
  if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
6120
0
    return MCDisassembler_Fail;
6121
  // Rt
6122
5.44k
  if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
6123
0
    return MCDisassembler_Fail;
6124
  // Rt2
6125
5.44k
  if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
6126
0
    return MCDisassembler_Fail;
6127
  // addr
6128
5.44k
  if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
6129
0
    return MCDisassembler_Fail;
6130
6131
5.44k
  return S;
6132
5.44k
}
6133
6134
static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn, uint64_t Address,
6135
        const void *Decoder)
6136
1.57k
{
6137
1.57k
  unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1);
6138
1.57k
  unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1);
6139
1.57k
  if (sign1 != sign2)
6140
1
    return MCDisassembler_Fail;
6141
1.57k
  const unsigned Rd = fieldFromInstruction_4(Insn, 8, 4);
6142
6143
1.57k
  DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder);
6144
6145
1.57k
  unsigned Val = fieldFromInstruction_4(Insn, 0, 8);
6146
1.57k
  Val |= fieldFromInstruction_4(Insn, 12, 3) << 8;
6147
1.57k
  Val |= fieldFromInstruction_4(Insn, 26, 1) << 11;
6148
  // If sign, then it is decreasing the address.
6149
1.57k
  if (sign1) {
6150
    // Following ARMv7 Architecture Manual, when the offset
6151
    // is zero, it is decoded as a subw, not as a adr.w
6152
1.03k
    if (!Val) {
6153
193
      MCInst_setOpcode(Inst, (ARM_t2SUBri12));
6154
193
      MCOperand_CreateReg0(Inst, (ARM_PC));
6155
193
    } else
6156
844
      Val = -Val;
6157
1.03k
  }
6158
1.57k
  MCOperand_CreateImm0(Inst, (Val));
6159
1.57k
  return S;
6160
1.57k
}
6161
6162
static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val,
6163
                uint64_t Address,
6164
                const void *Decoder)
6165
1.54k
{
6166
1.54k
  DecodeStatus S = MCDisassembler_Success;
6167
6168
  // Shift of "asr #32" is not allowed in Thumb2 mode.
6169
1.54k
  if (Val == 0x20)
6170
1
    S = MCDisassembler_Fail;
6171
1.54k
  MCOperand_CreateImm0(Inst, (Val));
6172
1.54k
  return S;
6173
1.54k
}
6174
6175
static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, uint64_t Address,
6176
             const void *Decoder)
6177
1.05k
{
6178
1.05k
  unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
6179
1.05k
  unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4);
6180
1.05k
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
6181
1.05k
  unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
6182
6183
1.05k
  if (pred == 0xF)
6184
238
    return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
6185
6186
813
  DecodeStatus S = MCDisassembler_Success;
6187
6188
813
  if (Rt == Rn || Rn == Rt2)
6189
264
    S = MCDisassembler_SoftFail;
6190
6191
813
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
6192
0
    return MCDisassembler_Fail;
6193
813
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
6194
0
    return MCDisassembler_Fail;
6195
813
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
6196
0
    return MCDisassembler_Fail;
6197
813
  if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
6198
0
    return MCDisassembler_Fail;
6199
6200
813
  return S;
6201
813
}
6202
6203
static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, uint64_t Address,
6204
        const void *Decoder)
6205
1.72k
{
6206
1.72k
  bool hasFullFP16 =
6207
1.72k
    ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16);
6208
6209
1.72k
  unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
6210
1.72k
  Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
6211
1.72k
  unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
6212
1.72k
  Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
6213
1.72k
  unsigned imm = fieldFromInstruction_4(Insn, 16, 6);
6214
1.72k
  unsigned cmode = fieldFromInstruction_4(Insn, 8, 4);
6215
1.72k
  unsigned op = fieldFromInstruction_4(Insn, 5, 1);
6216
6217
1.72k
  DecodeStatus S = MCDisassembler_Success;
6218
6219
  // If the top 3 bits of imm are clear, this is a VMOV (immediate)
6220
1.72k
  if (!(imm & 0x38)) {
6221
723
    if (cmode == 0xF) {
6222
127
      if (op == 1)
6223
2
        return MCDisassembler_Fail;
6224
125
      MCInst_setOpcode(Inst, (ARM_VMOVv2f32));
6225
125
    }
6226
721
    if (hasFullFP16) {
6227
721
      if (cmode == 0xE) {
6228
0
        if (op == 1) {
6229
0
          MCInst_setOpcode(Inst, (ARM_VMOVv1i64));
6230
0
        } else {
6231
0
          MCInst_setOpcode(Inst, (ARM_VMOVv8i8));
6232
0
        }
6233
0
      }
6234
721
      if (cmode == 0xD) {
6235
443
        if (op == 1) {
6236
320
          MCInst_setOpcode(Inst, (ARM_VMVNv2i32));
6237
320
        } else {
6238
123
          MCInst_setOpcode(Inst, (ARM_VMOVv2i32));
6239
123
        }
6240
443
      }
6241
721
      if (cmode == 0xC) {
6242
153
        if (op == 1) {
6243
74
          MCInst_setOpcode(Inst, (ARM_VMVNv2i32));
6244
79
        } else {
6245
79
          MCInst_setOpcode(Inst, (ARM_VMOVv2i32));
6246
79
        }
6247
153
      }
6248
721
    }
6249
721
    return DecodeVMOVModImmInstruction(Inst, Insn, Address,
6250
721
               Decoder);
6251
723
  }
6252
6253
998
  if (!(imm & 0x20))
6254
8
    return MCDisassembler_Fail;
6255
6256
990
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
6257
0
    return MCDisassembler_Fail;
6258
990
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
6259
0
    return MCDisassembler_Fail;
6260
990
  MCOperand_CreateImm0(Inst, (64 - imm));
6261
6262
990
  return S;
6263
990
}
6264
6265
static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, uint64_t Address,
6266
        const void *Decoder)
6267
1.40k
{
6268
1.40k
  bool hasFullFP16 =
6269
1.40k
    ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16);
6270
6271
1.40k
  unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
6272
1.40k
  Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
6273
1.40k
  unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
6274
1.40k
  Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
6275
1.40k
  unsigned imm = fieldFromInstruction_4(Insn, 16, 6);
6276
1.40k
  unsigned cmode = fieldFromInstruction_4(Insn, 8, 4);
6277
1.40k
  unsigned op = fieldFromInstruction_4(Insn, 5, 1);
6278
6279
1.40k
  DecodeStatus S = MCDisassembler_Success;
6280
6281
  // If the top 3 bits of imm are clear, this is a VMOV (immediate)
6282
1.40k
  if (!(imm & 0x38)) {
6283
923
    if (cmode == 0xF) {
6284
165
      if (op == 1)
6285
3
        return MCDisassembler_Fail;
6286
162
      MCInst_setOpcode(Inst, (ARM_VMOVv4f32));
6287
162
    }
6288
920
    if (hasFullFP16) {
6289
920
      if (cmode == 0xE) {
6290
0
        if (op == 1) {
6291
0
          MCInst_setOpcode(Inst, (ARM_VMOVv2i64));
6292
0
        } else {
6293
0
          MCInst_setOpcode(Inst, (ARM_VMOVv16i8));
6294
0
        }
6295
0
      }
6296
920
      if (cmode == 0xD) {
6297
390
        if (op == 1) {
6298
158
          MCInst_setOpcode(Inst, (ARM_VMVNv4i32));
6299
232
        } else {
6300
232
          MCInst_setOpcode(Inst, (ARM_VMOVv4i32));
6301
232
        }
6302
390
      }
6303
920
      if (cmode == 0xC) {
6304
368
        if (op == 1) {
6305
71
          MCInst_setOpcode(Inst, (ARM_VMVNv4i32));
6306
297
        } else {
6307
297
          MCInst_setOpcode(Inst, (ARM_VMOVv4i32));
6308
297
        }
6309
368
      }
6310
920
    }
6311
920
    return DecodeVMOVModImmInstruction(Inst, Insn, Address,
6312
920
               Decoder);
6313
923
  }
6314
6315
477
  if (!(imm & 0x20))
6316
1
    return MCDisassembler_Fail;
6317
6318
476
  if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
6319
1
    return MCDisassembler_Fail;
6320
475
  if (!Check(&S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
6321
2
    return MCDisassembler_Fail;
6322
473
  MCOperand_CreateImm0(Inst, (64 - imm));
6323
6324
473
  return S;
6325
475
}
6326
6327
static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst,
6328
                   unsigned Insn,
6329
                   uint64_t Address,
6330
                   const void *Decoder)
6331
190
{
6332
190
  unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
6333
190
  Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
6334
190
  unsigned Vn = (fieldFromInstruction_4(Insn, 16, 4) << 0);
6335
190
  Vn |= (fieldFromInstruction_4(Insn, 7, 1) << 4);
6336
190
  unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
6337
190
  Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
6338
190
  unsigned q = (fieldFromInstruction_4(Insn, 6, 1) << 0);
6339
190
  unsigned rotate = (fieldFromInstruction_4(Insn, 20, 2) << 0);
6340
6341
190
  DecodeStatus S = MCDisassembler_Success;
6342
6343
190
  typedef DecodeStatus (*DecoderFunction)(MCInst *Inst, unsigned RegNo,
6344
190
            uint64_t Address,
6345
190
            const void *Decoder);
6346
6347
190
  DecoderFunction DestRegDecoder = q ? DecodeQPRRegisterClass :
6348
190
               DecodeDPRRegisterClass;
6349
6350
190
  if (!Check(&S, DestRegDecoder(Inst, Vd, Address, Decoder)))
6351
1
    return MCDisassembler_Fail;
6352
189
  if (!Check(&S, DestRegDecoder(Inst, Vd, Address, Decoder)))
6353
0
    return MCDisassembler_Fail;
6354
189
  if (!Check(&S, DestRegDecoder(Inst, Vn, Address, Decoder)))
6355
1
    return MCDisassembler_Fail;
6356
188
  if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
6357
0
    return MCDisassembler_Fail;
6358
  // The lane index does not have any bits in the encoding, because it can
6359
  // only be 0.
6360
188
  MCOperand_CreateImm0(Inst, (0));
6361
188
  MCOperand_CreateImm0(Inst, (rotate));
6362
6363
188
  return S;
6364
188
}
6365
6366
static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, uint64_t Address,
6367
            const void *Decoder)
6368
2.12k
{
6369
2.12k
  DecodeStatus S = MCDisassembler_Success;
6370
6371
2.12k
  unsigned Rn = fieldFromInstruction_4(Val, 16, 4);
6372
2.12k
  unsigned Rt = fieldFromInstruction_4(Val, 12, 4);
6373
2.12k
  unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
6374
2.12k
  Rm |= (fieldFromInstruction_4(Val, 23, 1) << 4);
6375
2.12k
  unsigned Cond = fieldFromInstruction_4(Val, 28, 4);
6376
6377
2.12k
  if (fieldFromInstruction_4(Val, 8, 4) != 0 || Rn == Rt)
6378
1.00k
    S = MCDisassembler_SoftFail;
6379
6380
2.12k
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
6381
0
    return MCDisassembler_Fail;
6382
2.12k
  if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
6383
0
    return MCDisassembler_Fail;
6384
2.12k
  if (!Check(&S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
6385
0
    return MCDisassembler_Fail;
6386
2.12k
  if (!Check(&S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
6387
0
    return MCDisassembler_Fail;
6388
2.12k
  if (!Check(&S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
6389
3
    return MCDisassembler_Fail;
6390
6391
2.12k
  return S;
6392
2.12k
}
6393
6394
static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val,
6395
              uint64_t Address,
6396
              const void *Decoder)
6397
1.64k
{
6398
1.64k
  DecodeStatus S = MCDisassembler_Success;
6399
6400
1.64k
  unsigned CRm = fieldFromInstruction_4(Val, 0, 4);
6401
1.64k
  unsigned opc1 = fieldFromInstruction_4(Val, 4, 4);
6402
1.64k
  unsigned cop = fieldFromInstruction_4(Val, 8, 4);
6403
1.64k
  unsigned Rt = fieldFromInstruction_4(Val, 12, 4);
6404
1.64k
  unsigned Rt2 = fieldFromInstruction_4(Val, 16, 4);
6405
6406
1.64k
  if ((cop & ~0x1) == 0xa)
6407
10
    return MCDisassembler_Fail;
6408
6409
1.63k
  if (Rt == Rt2)
6410
502
    S = MCDisassembler_SoftFail;
6411
6412
  // We have to check if the instruction is MRRC2
6413
  // or MCRR2 when constructing the operands for
6414
  // Inst. Reason is because MRRC2 stores to two
6415
  // registers so it's tablegen desc has has two
6416
  // outputs whereas MCRR doesn't store to any
6417
  // registers so all of it's operands are listed
6418
  // as inputs, therefore the operand order for
6419
  // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
6420
  // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
6421
6422
1.63k
  if (MCInst_getOpcode(Inst) == ARM_MRRC2) {
6423
680
    if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address,
6424
680
                Decoder)))
6425
0
      return MCDisassembler_Fail;
6426
680
    if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address,
6427
680
                Decoder)))
6428
0
      return MCDisassembler_Fail;
6429
680
  }
6430
1.63k
  MCOperand_CreateImm0(Inst, (cop));
6431
1.63k
  MCOperand_CreateImm0(Inst, (opc1));
6432
1.63k
  if (MCInst_getOpcode(Inst) == ARM_MCRR2) {
6433
955
    if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address,
6434
955
                Decoder)))
6435
0
      return MCDisassembler_Fail;
6436
955
    if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address,
6437
955
                Decoder)))
6438
0
      return MCDisassembler_Fail;
6439
955
  }
6440
1.63k
  MCOperand_CreateImm0(Inst, (CRm));
6441
6442
1.63k
  return S;
6443
1.63k
}
6444
6445
static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val,
6446
           uint64_t Address, const void *Decoder)
6447
2.10k
{
6448
2.10k
  DecodeStatus S = MCDisassembler_Success;
6449
6450
  // Add explicit operand for the destination sysreg, for cases where
6451
  // we have to model it for code generation purposes.
6452
2.10k
  switch (MCInst_getOpcode(Inst)) {
6453
37
  case ARM_VMSR_FPSCR_NZCVQC:
6454
37
    MCOperand_CreateReg0(Inst, (ARM_FPSCR_NZCV));
6455
37
    break;
6456
0
  case ARM_VMSR_P0:
6457
0
    MCOperand_CreateReg0(Inst, (ARM_VPR));
6458
0
    break;
6459
2.10k
  }
6460
6461
2.10k
  if (MCInst_getOpcode(Inst) != ARM_FMSTAT) {
6462
2.06k
    unsigned Rt = fieldFromInstruction_4(Val, 12, 4);
6463
6464
2.06k
    if (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) &&
6465
2.06k
        !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) {
6466
1.54k
      if (Rt == 13 || Rt == 15)
6467
280
        S = MCDisassembler_SoftFail;
6468
1.54k
      Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address,
6469
1.54k
               Decoder));
6470
1.54k
    } else
6471
519
      Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address,
6472
519
                   Decoder));
6473
2.06k
  }
6474
6475
  // Add explicit operand for the source sysreg, similarly to above.
6476
2.10k
  switch (MCInst_getOpcode(Inst)) {
6477
18
  case ARM_VMRS_FPSCR_NZCVQC:
6478
18
    MCOperand_CreateReg0(Inst, (ARM_FPSCR_NZCV));
6479
18
    break;
6480
0
  case ARM_VMRS_P0:
6481
0
    MCOperand_CreateReg0(Inst, (ARM_VPR));
6482
0
    break;
6483
2.10k
  }
6484
6485
2.10k
  if (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb)) {
6486
1.94k
    MCOperand_CreateImm0(Inst, (ARMCC_AL));
6487
1.94k
    MCOperand_CreateReg0(Inst, (0));
6488
1.94k
  } else {
6489
153
    unsigned pred = fieldFromInstruction_4(Val, 28, 4);
6490
153
    if (!Check(&S, DecodePredicateOperand(Inst, pred, Address,
6491
153
                  Decoder)))
6492
1
      return MCDisassembler_Fail;
6493
153
  }
6494
6495
2.10k
  return S;
6496
2.10k
}
6497
6498
#define DEFINE_DecodeBFLabelOperand(isSigned, isNeg, zeroPermitted, size) \
6499
  static DecodeStatus CONCAT( \
6500
    DecodeBFLabelOperand, \
6501
    CONCAT(isSigned, CONCAT(isNeg, CONCAT(zeroPermitted, size))))( \
6502
    MCInst * Inst, unsigned Val, uint64_t Address, \
6503
    const void *Decoder) \
6504
3.28k
  { \
6505
3.28k
    DecodeStatus S = MCDisassembler_Success; \
6506
3.28k
    if (Val == 0 && !zeroPermitted) \
6507
3.28k
      S = MCDisassembler_Fail; \
6508
3.28k
\
6509
3.28k
    uint64_t DecVal; \
6510
3.28k
    if (isSigned) \
6511
3.28k
      DecVal = SignExtend32((Val << 1), size + 1); \
6512
3.28k
    else \
6513
3.28k
      DecVal = (Val << 1); \
6514
3.28k
\
6515
3.28k
    if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, \
6516
3.28k
                true, 4, Inst, Decoder)) \
6517
3.28k
      MCOperand_CreateImm0(Inst, \
6518
3.28k
               (isNeg ? -DecVal : DecVal)); \
6519
3.28k
    return S; \
6520
3.28k
  }
ARMDisassembler.c:DecodeBFLabelOperand_0_1_1_11
Line
Count
Source
6504
465
  { \
6505
465
    DecodeStatus S = MCDisassembler_Success; \
6506
465
    if (Val == 0 && !zeroPermitted) \
6507
465
      S = MCDisassembler_Fail; \
6508
465
\
6509
465
    uint64_t DecVal; \
6510
465
    if (isSigned) \
6511
465
      DecVal = SignExtend32((Val << 1), size + 1); \
6512
465
    else \
6513
465
      DecVal = (Val << 1); \
6514
465
\
6515
465
    if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, \
6516
465
                true, 4, Inst, Decoder)) \
6517
465
      MCOperand_CreateImm0(Inst, \
6518
465
               (isNeg ? -DecVal : DecVal)); \
6519
465
    return S; \
6520
465
  }
ARMDisassembler.c:DecodeBFLabelOperand_0_0_1_11
Line
Count
Source
6504
1.01k
  { \
6505
1.01k
    DecodeStatus S = MCDisassembler_Success; \
6506
1.01k
    if (Val == 0 && !zeroPermitted) \
6507
1.01k
      S = MCDisassembler_Fail; \
6508
1.01k
\
6509
1.01k
    uint64_t DecVal; \
6510
1.01k
    if (isSigned) \
6511
1.01k
      DecVal = SignExtend32((Val << 1), size + 1); \
6512
1.01k
    else \
6513
1.01k
      DecVal = (Val << 1); \
6514
1.01k
\
6515
1.01k
    if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, \
6516
1.01k
                true, 4, Inst, Decoder)) \
6517
1.01k
      MCOperand_CreateImm0(Inst, \
6518
1.01k
               (isNeg ? -DecVal : DecVal)); \
6519
1.01k
    return S; \
6520
1.01k
  }
ARMDisassembler.c:DecodeBFLabelOperand_0_0_0_4
Line
Count
Source
6504
938
  { \
6505
938
    DecodeStatus S = MCDisassembler_Success; \
6506
938
    if (Val == 0 && !zeroPermitted) \
6507
938
      S = MCDisassembler_Fail; \
6508
938
\
6509
938
    uint64_t DecVal; \
6510
938
    if (isSigned) \
6511
938
      DecVal = SignExtend32((Val << 1), size + 1); \
6512
938
    else \
6513
938
      DecVal = (Val << 1); \
6514
938
\
6515
938
    if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, \
6516
938
                true, 4, Inst, Decoder)) \
6517
938
      MCOperand_CreateImm0(Inst, \
6518
938
               (isNeg ? -DecVal : DecVal)); \
6519
938
    return S; \
6520
938
  }
ARMDisassembler.c:DecodeBFLabelOperand_1_0_1_18
Line
Count
Source
6504
493
  { \
6505
493
    DecodeStatus S = MCDisassembler_Success; \
6506
493
    if (Val == 0 && !zeroPermitted) \
6507
493
      S = MCDisassembler_Fail; \
6508
493
\
6509
493
    uint64_t DecVal; \
6510
493
    if (isSigned) \
6511
493
      DecVal = SignExtend32((Val << 1), size + 1); \
6512
493
    else \
6513
493
      DecVal = (Val << 1); \
6514
493
\
6515
493
    if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, \
6516
493
                true, 4, Inst, Decoder)) \
6517
493
      MCOperand_CreateImm0(Inst, \
6518
493
               (isNeg ? -DecVal : DecVal)); \
6519
493
    return S; \
6520
493
  }
ARMDisassembler.c:DecodeBFLabelOperand_1_0_1_12
Line
Count
Source
6504
232
  { \
6505
232
    DecodeStatus S = MCDisassembler_Success; \
6506
232
    if (Val == 0 && !zeroPermitted) \
6507
232
      S = MCDisassembler_Fail; \
6508
232
\
6509
232
    uint64_t DecVal; \
6510
232
    if (isSigned) \
6511
232
      DecVal = SignExtend32((Val << 1), size + 1); \
6512
232
    else \
6513
232
      DecVal = (Val << 1); \
6514
232
\
6515
232
    if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, \
6516
232
                true, 4, Inst, Decoder)) \
6517
232
      MCOperand_CreateImm0(Inst, \
6518
232
               (isNeg ? -DecVal : DecVal)); \
6519
232
    return S; \
6520
232
  }
ARMDisassembler.c:DecodeBFLabelOperand_1_0_1_16
Line
Count
Source
6504
142
  { \
6505
142
    DecodeStatus S = MCDisassembler_Success; \
6506
142
    if (Val == 0 && !zeroPermitted) \
6507
142
      S = MCDisassembler_Fail; \
6508
142
\
6509
142
    uint64_t DecVal; \
6510
142
    if (isSigned) \
6511
142
      DecVal = SignExtend32((Val << 1), size + 1); \
6512
142
    else \
6513
142
      DecVal = (Val << 1); \
6514
142
\
6515
142
    if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, \
6516
142
                true, 4, Inst, Decoder)) \
6517
142
      MCOperand_CreateImm0(Inst, \
6518
142
               (isNeg ? -DecVal : DecVal)); \
6519
142
    return S; \
6520
142
  }
6521
DEFINE_DecodeBFLabelOperand(false, false, false, 4)
6522
  DEFINE_DecodeBFLabelOperand(true, false, true,
6523
            18) DEFINE_DecodeBFLabelOperand(true, false,
6524
                    true, 12)
6525
    DEFINE_DecodeBFLabelOperand(true, false, true, 16)
6526
      DEFINE_DecodeBFLabelOperand(false, true, true, 11)
6527
        DEFINE_DecodeBFLabelOperand(false, false, true,
6528
                  11)
6529
6530
          static DecodeStatus
6531
  DecodeBFAfterTargetOperand(MCInst *Inst, unsigned Val, uint64_t Address,
6532
           const void *Decoder)
6533
232
{
6534
232
  uint64_t LocImm = MCOperand_getImm(MCInst_getOperand(Inst, (0)));
6535
232
  Val = LocImm + (2 << Val);
6536
232
  if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst,
6537
232
              Decoder))
6538
232
    MCOperand_CreateImm0(Inst, (Val));
6539
232
  return MCDisassembler_Success;
6540
232
}
6541
6542
static DecodeStatus DecodePredNoALOperand(MCInst *Inst, unsigned Val,
6543
            uint64_t Address, const void *Decoder)
6544
1.36k
{
6545
1.36k
  if (Val >= ARMCC_AL) // also exclude the non-condition NV
6546
3
    return MCDisassembler_Fail;
6547
1.36k
  MCOperand_CreateImm0(Inst, (Val));
6548
1.36k
  return MCDisassembler_Success;
6549
1.36k
}
6550
6551
static DecodeStatus DecodeLOLoop(MCInst *Inst, unsigned Insn, uint64_t Address,
6552
         const void *Decoder)
6553
2.77k
{
6554
2.77k
  DecodeStatus S = MCDisassembler_Success;
6555
6556
2.77k
  if (MCInst_getOpcode(Inst) == ARM_MVE_LCTP)
6557
0
    return S;
6558
6559
2.77k
  unsigned Imm = fieldFromInstruction_4(Insn, 11, 1) |
6560
2.77k
           fieldFromInstruction_4(Insn, 1, 10) << 1;
6561
2.77k
  switch (MCInst_getOpcode(Inst)) {
6562
200
  case ARM_t2LEUpdate:
6563
268
  case ARM_MVE_LETP:
6564
268
    MCOperand_CreateReg0(Inst, (ARM_LR));
6565
268
    MCOperand_CreateReg0(Inst, (ARM_LR));
6566
    // fall through
6567
465
  case ARM_t2LE:
6568
465
    if (!Check(&S, CONCAT(DecodeBFLabelOperand,
6569
465
              CONCAT(false,
6570
465
               CONCAT(true, CONCAT(true, 11))))(
6571
465
               Inst, Imm, Address, Decoder)))
6572
0
      return MCDisassembler_Fail;
6573
465
    break;
6574
465
  case ARM_t2WLS:
6575
530
  case ARM_MVE_WLSTP_8:
6576
599
  case ARM_MVE_WLSTP_16:
6577
809
  case ARM_MVE_WLSTP_32:
6578
1.01k
  case ARM_MVE_WLSTP_64:
6579
1.01k
    MCOperand_CreateReg0(Inst, (ARM_LR));
6580
1.01k
    if (!Check(&S,
6581
1.01k
         DecoderGPRRegisterClass(
6582
1.01k
           Inst, fieldFromInstruction_4(Insn, 16, 4),
6583
1.01k
           Address, Decoder)) ||
6584
1.01k
        !Check(&S, CONCAT(DecodeBFLabelOperand,
6585
1.01k
              CONCAT(false,
6586
1.01k
               CONCAT(false, CONCAT(true, 11))))(
6587
1.01k
               Inst, Imm, Address, Decoder)))
6588
0
      return MCDisassembler_Fail;
6589
1.01k
    break;
6590
1.01k
  case ARM_t2DLS:
6591
843
  case ARM_MVE_DLSTP_8:
6592
943
  case ARM_MVE_DLSTP_16:
6593
1.12k
  case ARM_MVE_DLSTP_32:
6594
1.29k
  case ARM_MVE_DLSTP_64: {
6595
1.29k
    unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
6596
1.29k
    if (Rn == 0xF) {
6597
      // Enforce all the rest of the instruction bits in LCTP, which
6598
      // won't have been reliably checked based on LCTP's own tablegen
6599
      // record, because we came to this decode by a roundabout route.
6600
404
      uint32_t CanonicalLCTP = 0xF00FE001,
6601
404
         SBZMask = 0x00300FFE;
6602
404
      if ((Insn & ~SBZMask) != CanonicalLCTP)
6603
1
        return MCDisassembler_Fail; // a mandatory bit is wrong: hard
6604
          // fail
6605
403
      if (Insn != CanonicalLCTP)
6606
56
        Check(&S,
6607
56
              MCDisassembler_SoftFail); // an SBZ bit is wrong: soft fail
6608
6609
403
      MCInst_setOpcode(Inst, (ARM_MVE_LCTP));
6610
886
    } else {
6611
886
      MCOperand_CreateReg0(Inst, (ARM_LR));
6612
886
      if (!Check(&S,
6613
886
           DecoderGPRRegisterClass(
6614
886
             Inst,
6615
886
             fieldFromInstruction_4(Insn, 16, 4),
6616
886
             Address, Decoder)))
6617
0
        return MCDisassembler_Fail;
6618
886
    }
6619
1.28k
    break;
6620
1.29k
  }
6621
2.77k
  }
6622
2.76k
  return S;
6623
2.77k
}
6624
6625
static DecodeStatus DecodeLongShiftOperand(MCInst *Inst, unsigned Val,
6626
             uint64_t Address,
6627
             const void *Decoder)
6628
413
{
6629
413
  DecodeStatus S = MCDisassembler_Success;
6630
6631
413
  if (Val == 0)
6632
104
    Val = 32;
6633
6634
413
  MCOperand_CreateImm0(Inst, (Val));
6635
6636
413
  return S;
6637
413
}
6638
6639
static DecodeStatus DecodetGPROddRegisterClass(MCInst *Inst, unsigned RegNo,
6640
                 uint64_t Address,
6641
                 const void *Decoder)
6642
8.25k
{
6643
8.25k
  if ((RegNo) + 1 > 11)
6644
1.67k
    return MCDisassembler_Fail;
6645
6646
6.58k
  unsigned Register = GPRDecoderTable[(RegNo) + 1];
6647
6.58k
  MCOperand_CreateReg0(Inst, (Register));
6648
6.58k
  return MCDisassembler_Success;
6649
8.25k
}
6650
6651
static DecodeStatus DecodetGPREvenRegisterClass(MCInst *Inst, unsigned RegNo,
6652
            uint64_t Address,
6653
            const void *Decoder)
6654
12.6k
{
6655
12.6k
  if ((RegNo) > 14)
6656
0
    return MCDisassembler_Fail;
6657
6658
12.6k
  unsigned Register = GPRDecoderTable[(RegNo)];
6659
12.6k
  MCOperand_CreateReg0(Inst, (Register));
6660
12.6k
  return MCDisassembler_Success;
6661
12.6k
}
6662
6663
static DecodeStatus DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst *Inst,
6664
                  unsigned RegNo,
6665
                  uint64_t Address,
6666
                  const void *Decoder)
6667
0
{
6668
0
  if (RegNo == 15) {
6669
0
    MCOperand_CreateReg0(Inst, (ARM_APSR_NZCV));
6670
0
    return MCDisassembler_Success;
6671
0
  }
6672
6673
0
  unsigned Register = GPRDecoderTable[RegNo];
6674
0
  MCOperand_CreateReg0(Inst, (Register));
6675
6676
0
  if (RegNo == 13)
6677
0
    return MCDisassembler_SoftFail;
6678
6679
0
  return MCDisassembler_Success;
6680
0
}
6681
6682
static DecodeStatus DecodeVSCCLRM(MCInst *Inst, unsigned Insn, uint64_t Address,
6683
          const void *Decoder)
6684
176
{
6685
176
  DecodeStatus S = MCDisassembler_Success;
6686
6687
176
  MCOperand_CreateImm0(Inst, (ARMCC_AL));
6688
176
  MCOperand_CreateReg0(Inst, (0));
6689
176
  if (MCInst_getOpcode(Inst) == ARM_VSCCLRMD) {
6690
81
    unsigned reglist = (fieldFromInstruction_4(Insn, 1, 7) << 1) |
6691
81
           (fieldFromInstruction_4(Insn, 12, 4) << 8) |
6692
81
           (fieldFromInstruction_4(Insn, 22, 1) << 12);
6693
81
    if (!Check(&S, DecodeDPRRegListOperand(Inst, reglist, Address,
6694
81
                   Decoder))) {
6695
0
      return MCDisassembler_Fail;
6696
0
    }
6697
95
  } else {
6698
95
    unsigned reglist = fieldFromInstruction_4(Insn, 0, 8) |
6699
95
           (fieldFromInstruction_4(Insn, 22, 1) << 8) |
6700
95
           (fieldFromInstruction_4(Insn, 12, 4) << 9);
6701
95
    if (!Check(&S, DecodeSPRRegListOperand(Inst, reglist, Address,
6702
95
                   Decoder))) {
6703
0
      return MCDisassembler_Fail;
6704
0
    }
6705
95
  }
6706
176
  MCOperand_CreateReg0(Inst, (ARM_VPR));
6707
6708
176
  return S;
6709
176
}
6710
6711
static DecodeStatus DecodeMQPRRegisterClass(MCInst *Inst, unsigned RegNo,
6712
              uint64_t Address,
6713
              const void *Decoder)
6714
119k
{
6715
119k
  if (RegNo > 7)
6716
17.4k
    return MCDisassembler_Fail;
6717
6718
101k
  unsigned Register = QPRDecoderTable[RegNo];
6719
101k
  MCOperand_CreateReg0(Inst, (Register));
6720
101k
  return MCDisassembler_Success;
6721
119k
}
6722
6723
static const uint16_t QQPRDecoderTable[] = { ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3,
6724
               ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6,
6725
               ARM_Q6_Q7 };
6726
6727
static DecodeStatus DecodeMQQPRRegisterClass(MCInst *Inst, unsigned RegNo,
6728
               uint64_t Address,
6729
               const void *Decoder)
6730
1.95k
{
6731
1.95k
  if (RegNo > 6)
6732
723
    return MCDisassembler_Fail;
6733
6734
1.23k
  unsigned Register = QQPRDecoderTable[RegNo];
6735
1.23k
  MCOperand_CreateReg0(Inst, (Register));
6736
1.23k
  return MCDisassembler_Success;
6737
1.95k
}
6738
6739
static const uint16_t QQQQPRDecoderTable[] = { ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4,
6740
                 ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6,
6741
                 ARM_Q4_Q5_Q6_Q7 };
6742
6743
static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst *Inst, unsigned RegNo,
6744
                 uint64_t Address,
6745
                 const void *Decoder)
6746
1.47k
{
6747
1.47k
  if (RegNo > 4)
6748
668
    return MCDisassembler_Fail;
6749
6750
807
  unsigned Register = QQQQPRDecoderTable[RegNo];
6751
807
  MCOperand_CreateReg0(Inst, (Register));
6752
807
  return MCDisassembler_Success;
6753
1.47k
}
6754
6755
static DecodeStatus DecodeVPTMaskOperand(MCInst *Inst, unsigned Val,
6756
           uint64_t Address, const void *Decoder)
6757
10.9k
{
6758
10.9k
  DecodeStatus S = MCDisassembler_Success;
6759
6760
  // Parse VPT mask and encode it in the MCInst as an immediate with the same
6761
  // format as the it_mask.  That is, from the second 'e|t' encode 'e' as 1
6762
  // and 't' as 0 and finish with a 1.
6763
10.9k
  unsigned Imm = 0;
6764
  // We always start with a 't'.
6765
10.9k
  unsigned CurBit = 0;
6766
38.1k
  for (int i = 3; i >= 0; --i) {
6767
    // If the bit we are looking at is not the same as last one, invert the
6768
    // CurBit, if it is the same leave it as is.
6769
38.1k
    CurBit ^= (Val >> i) & 1U;
6770
6771
    // Encode the CurBit at the right place in the immediate.
6772
38.1k
    Imm |= (CurBit << i);
6773
6774
    // If we are done, finish the encoding with a 1.
6775
38.1k
    if ((Val & ~(~0U << i)) == 0) {
6776
10.9k
      Imm |= 1U << i;
6777
10.9k
      break;
6778
10.9k
    }
6779
38.1k
  }
6780
6781
10.9k
  MCOperand_CreateImm0(Inst, (Imm));
6782
6783
10.9k
  return S;
6784
10.9k
}
6785
6786
static DecodeStatus DecodeVpredROperand(MCInst *Inst, unsigned RegNo,
6787
          uint64_t Address, const void *Decoder)
6788
7.05k
{
6789
  // The vpred_r operand type includes an MQPR register field derived
6790
  // from the encoding. But we don't actually want to add an operand
6791
  // to the MCInst at this stage, because AddThumbPredicate will do it
6792
  // later, and will infer the register number from the TIED_TO
6793
  // constraint. So this is a deliberately empty decoder method that
6794
  // will inhibit the auto-generated disassembly code from adding an
6795
  // operand at all.
6796
7.05k
  return MCDisassembler_Success;
6797
7.05k
}
6798
6799
static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst *Inst,
6800
                  unsigned Val,
6801
                  uint64_t Address,
6802
                  const void *Decoder)
6803
3.29k
{
6804
3.29k
  MCOperand_CreateImm0(Inst, ((Val & 0x1) == 0 ? ARMCC_EQ : ARMCC_NE));
6805
3.29k
  return MCDisassembler_Success;
6806
3.29k
}
6807
6808
static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst *Inst,
6809
                  unsigned Val,
6810
                  uint64_t Address,
6811
                  const void *Decoder)
6812
3.02k
{
6813
3.02k
  unsigned Code;
6814
3.02k
  switch (Val & 0x3) {
6815
956
  case 0:
6816
956
    Code = ARMCC_GE;
6817
956
    break;
6818
79
  case 1:
6819
79
    Code = ARMCC_LT;
6820
79
    break;
6821
943
  case 2:
6822
943
    Code = ARMCC_GT;
6823
943
    break;
6824
1.04k
  case 3:
6825
1.04k
    Code = ARMCC_LE;
6826
1.04k
    break;
6827
3.02k
  }
6828
3.02k
  MCOperand_CreateImm0(Inst, (Code));
6829
3.02k
  return MCDisassembler_Success;
6830
3.02k
}
6831
6832
static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst *Inst,
6833
                  unsigned Val,
6834
                  uint64_t Address,
6835
                  const void *Decoder)
6836
3.69k
{
6837
3.69k
  MCOperand_CreateImm0(Inst, ((Val & 0x1) == 0 ? ARMCC_HS : ARMCC_HI));
6838
3.69k
  return MCDisassembler_Success;
6839
3.69k
}
6840
6841
static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst *Inst,
6842
                   unsigned Val,
6843
                   uint64_t Address,
6844
                   const void *Decoder)
6845
4.12k
{
6846
4.12k
  unsigned Code;
6847
4.12k
  switch (Val) {
6848
1.20k
  default:
6849
1.20k
    return MCDisassembler_Fail;
6850
1.23k
  case 0:
6851
1.23k
    Code = ARMCC_EQ;
6852
1.23k
    break;
6853
398
  case 1:
6854
398
    Code = ARMCC_NE;
6855
398
    break;
6856
699
  case 4:
6857
699
    Code = ARMCC_GE;
6858
699
    break;
6859
154
  case 5:
6860
154
    Code = ARMCC_LT;
6861
154
    break;
6862
218
  case 6:
6863
218
    Code = ARMCC_GT;
6864
218
    break;
6865
223
  case 7:
6866
223
    Code = ARMCC_LE;
6867
223
    break;
6868
4.12k
  }
6869
6870
2.92k
  MCOperand_CreateImm0(Inst, (Code));
6871
2.92k
  return MCDisassembler_Success;
6872
4.12k
}
6873
6874
static DecodeStatus DecodeVCVTImmOperand(MCInst *Inst, unsigned Val,
6875
           uint64_t Address, const void *Decoder)
6876
1.61k
{
6877
1.61k
  DecodeStatus S = MCDisassembler_Success;
6878
6879
1.61k
  unsigned DecodedVal = 64 - Val;
6880
6881
1.61k
  switch (MCInst_getOpcode(Inst)) {
6882
198
  case ARM_MVE_VCVTf16s16_fix:
6883
424
  case ARM_MVE_VCVTs16f16_fix:
6884
687
  case ARM_MVE_VCVTf16u16_fix:
6885
784
  case ARM_MVE_VCVTu16f16_fix:
6886
784
    if (DecodedVal > 16)
6887
0
      return MCDisassembler_Fail;
6888
784
    break;
6889
784
  case ARM_MVE_VCVTf32s32_fix:
6890
167
  case ARM_MVE_VCVTs32f32_fix:
6891
545
  case ARM_MVE_VCVTf32u32_fix:
6892
835
  case ARM_MVE_VCVTu32f32_fix:
6893
835
    if (DecodedVal > 32)
6894
0
      return MCDisassembler_Fail;
6895
835
    break;
6896
1.61k
  }
6897
6898
1.61k
  MCOperand_CreateImm0(Inst, (64 - Val));
6899
6900
1.61k
  return S;
6901
1.61k
}
6902
6903
static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode)
6904
3.97k
{
6905
3.97k
  switch (Opcode) {
6906
0
  case ARM_VSTR_P0_off:
6907
0
  case ARM_VSTR_P0_pre:
6908
0
  case ARM_VSTR_P0_post:
6909
0
  case ARM_VLDR_P0_off:
6910
0
  case ARM_VLDR_P0_pre:
6911
0
  case ARM_VLDR_P0_post:
6912
0
    return ARM_P0;
6913
3.97k
  default:
6914
3.97k
    return 0;
6915
3.97k
  }
6916
3.97k
}
6917
6918
#define DEFINE_DecodeVSTRVLDR_SYSREG(Writeback) \
6919
  static DecodeStatus CONCAT(DecodeVSTRVLDR_SYSREG, Writeback)( \
6920
    MCInst * Inst, unsigned Val, uint64_t Address, \
6921
    const void *Decoder) \
6922
3.97k
  { \
6923
3.97k
    switch (MCInst_getOpcode(Inst)) { \
6924
326
    case ARM_VSTR_FPSCR_pre: \
6925
398
    case ARM_VSTR_FPSCR_NZCVQC_pre: \
6926
574
    case ARM_VLDR_FPSCR_pre: \
6927
697
    case ARM_VLDR_FPSCR_NZCVQC_pre: \
6928
906
    case ARM_VSTR_FPSCR_off: \
6929
996
    case ARM_VSTR_FPSCR_NZCVQC_off: \
6930
1.17k
    case ARM_VLDR_FPSCR_off: \
6931
1.89k
    case ARM_VLDR_FPSCR_NZCVQC_off: \
6932
1.96k
    case ARM_VSTR_FPSCR_post: \
6933
1.99k
    case ARM_VSTR_FPSCR_NZCVQC_post: \
6934
2.07k
    case ARM_VLDR_FPSCR_post: \
6935
2.14k
    case ARM_VLDR_FPSCR_NZCVQC_post: \
6936
2.14k
\
6937
2.14k
      if (!ARM_getFeatureBits(Inst->csh->mode, \
6938
2.14k
            ARM_HasMVEIntegerOps) && \
6939
2.14k
          !ARM_getFeatureBits(Inst->csh->mode, \
6940
2.14k
            ARM_FeatureVFP2)) \
6941
2.14k
        return MCDisassembler_Fail; \
6942
3.97k
    } \
6943
3.97k
\
6944
3.97k
    DecodeStatus S = MCDisassembler_Success; \
6945
3.97k
    unsigned Sysreg = \
6946
3.97k
      FixedRegForVSTRVLDR_SYSREG(MCInst_getOpcode(Inst)); \
6947
3.97k
    if (Sysreg) \
6948
3.97k
      MCOperand_CreateReg0(Inst, (Sysreg)); \
6949
3.97k
    unsigned Rn = fieldFromInstruction_4(Val, 16, 4); \
6950
3.97k
    unsigned addr = fieldFromInstruction_4(Val, 0, 7) | \
6951
3.97k
        (fieldFromInstruction_4(Val, 23, 1) << 7) | \
6952
3.97k
        (Rn << 8); \
6953
3.97k
\
6954
3.97k
    if (Writeback) { \
6955
2.34k
      if (!Check(&S, DecodeGPRnopcRegisterClass( \
6956
2.34k
                 Inst, Rn, Address, Decoder))) \
6957
2.34k
        return MCDisassembler_Fail; \
6958
2.34k
    } \
6959
3.97k
    if (!Check(&S, DecodeT2AddrModeImm7s4(Inst, addr, Address, \
6960
3.97k
                  Decoder))) \
6961
3.97k
      return MCDisassembler_Fail; \
6962
3.97k
\
6963
3.97k
    MCOperand_CreateImm0(Inst, (ARMCC_AL)); \
6964
3.97k
    MCOperand_CreateReg0(Inst, (0)); \
6965
3.97k
\
6966
3.97k
    return S; \
6967
3.97k
  }
ARMDisassembler.c:DecodeVSTRVLDR_SYSREG_0
Line
Count
Source
6922
1.63k
  { \
6923
1.63k
    switch (MCInst_getOpcode(Inst)) { \
6924
0
    case ARM_VSTR_FPSCR_pre: \
6925
0
    case ARM_VSTR_FPSCR_NZCVQC_pre: \
6926
0
    case ARM_VLDR_FPSCR_pre: \
6927
0
    case ARM_VLDR_FPSCR_NZCVQC_pre: \
6928
209
    case ARM_VSTR_FPSCR_off: \
6929
299
    case ARM_VSTR_FPSCR_NZCVQC_off: \
6930
476
    case ARM_VLDR_FPSCR_off: \
6931
1.19k
    case ARM_VLDR_FPSCR_NZCVQC_off: \
6932
1.19k
    case ARM_VSTR_FPSCR_post: \
6933
1.19k
    case ARM_VSTR_FPSCR_NZCVQC_post: \
6934
1.19k
    case ARM_VLDR_FPSCR_post: \
6935
1.19k
    case ARM_VLDR_FPSCR_NZCVQC_post: \
6936
1.19k
\
6937
1.19k
      if (!ARM_getFeatureBits(Inst->csh->mode, \
6938
1.19k
            ARM_HasMVEIntegerOps) && \
6939
1.19k
          !ARM_getFeatureBits(Inst->csh->mode, \
6940
1.19k
            ARM_FeatureVFP2)) \
6941
1.19k
        return MCDisassembler_Fail; \
6942
1.63k
    } \
6943
1.63k
\
6944
1.63k
    DecodeStatus S = MCDisassembler_Success; \
6945
1.63k
    unsigned Sysreg = \
6946
1.63k
      FixedRegForVSTRVLDR_SYSREG(MCInst_getOpcode(Inst)); \
6947
1.63k
    if (Sysreg) \
6948
1.63k
      MCOperand_CreateReg0(Inst, (Sysreg)); \
6949
1.63k
    unsigned Rn = fieldFromInstruction_4(Val, 16, 4); \
6950
1.63k
    unsigned addr = fieldFromInstruction_4(Val, 0, 7) | \
6951
1.63k
        (fieldFromInstruction_4(Val, 23, 1) << 7) | \
6952
1.63k
        (Rn << 8); \
6953
1.63k
\
6954
1.63k
    if (Writeback) { \
6955
0
      if (!Check(&S, DecodeGPRnopcRegisterClass( \
6956
0
                 Inst, Rn, Address, Decoder))) \
6957
0
        return MCDisassembler_Fail; \
6958
0
    } \
6959
1.63k
    if (!Check(&S, DecodeT2AddrModeImm7s4(Inst, addr, Address, \
6960
1.63k
                  Decoder))) \
6961
1.63k
      return MCDisassembler_Fail; \
6962
1.63k
\
6963
1.63k
    MCOperand_CreateImm0(Inst, (ARMCC_AL)); \
6964
1.63k
    MCOperand_CreateReg0(Inst, (0)); \
6965
1.63k
\
6966
1.63k
    return S; \
6967
1.63k
  }
ARMDisassembler.c:DecodeVSTRVLDR_SYSREG_1
Line
Count
Source
6922
2.34k
  { \
6923
2.34k
    switch (MCInst_getOpcode(Inst)) { \
6924
326
    case ARM_VSTR_FPSCR_pre: \
6925
398
    case ARM_VSTR_FPSCR_NZCVQC_pre: \
6926
574
    case ARM_VLDR_FPSCR_pre: \
6927
697
    case ARM_VLDR_FPSCR_NZCVQC_pre: \
6928
697
    case ARM_VSTR_FPSCR_off: \
6929
697
    case ARM_VSTR_FPSCR_NZCVQC_off: \
6930
697
    case ARM_VLDR_FPSCR_off: \
6931
697
    case ARM_VLDR_FPSCR_NZCVQC_off: \
6932
767
    case ARM_VSTR_FPSCR_post: \
6933
802
    case ARM_VSTR_FPSCR_NZCVQC_post: \
6934
876
    case ARM_VLDR_FPSCR_post: \
6935
945
    case ARM_VLDR_FPSCR_NZCVQC_post: \
6936
945
\
6937
945
      if (!ARM_getFeatureBits(Inst->csh->mode, \
6938
945
            ARM_HasMVEIntegerOps) && \
6939
945
          !ARM_getFeatureBits(Inst->csh->mode, \
6940
945
            ARM_FeatureVFP2)) \
6941
945
        return MCDisassembler_Fail; \
6942
2.34k
    } \
6943
2.34k
\
6944
2.34k
    DecodeStatus S = MCDisassembler_Success; \
6945
2.34k
    unsigned Sysreg = \
6946
2.34k
      FixedRegForVSTRVLDR_SYSREG(MCInst_getOpcode(Inst)); \
6947
2.34k
    if (Sysreg) \
6948
2.34k
      MCOperand_CreateReg0(Inst, (Sysreg)); \
6949
2.34k
    unsigned Rn = fieldFromInstruction_4(Val, 16, 4); \
6950
2.34k
    unsigned addr = fieldFromInstruction_4(Val, 0, 7) | \
6951
2.34k
        (fieldFromInstruction_4(Val, 23, 1) << 7) | \
6952
2.34k
        (Rn << 8); \
6953
2.34k
\
6954
2.34k
    if (Writeback) { \
6955
2.34k
      if (!Check(&S, DecodeGPRnopcRegisterClass( \
6956
2.34k
                 Inst, Rn, Address, Decoder))) \
6957
2.34k
        return MCDisassembler_Fail; \
6958
2.34k
    } \
6959
2.34k
    if (!Check(&S, DecodeT2AddrModeImm7s4(Inst, addr, Address, \
6960
2.34k
                  Decoder))) \
6961
2.34k
      return MCDisassembler_Fail; \
6962
2.34k
\
6963
2.34k
    MCOperand_CreateImm0(Inst, (ARMCC_AL)); \
6964
2.34k
    MCOperand_CreateReg0(Inst, (0)); \
6965
2.34k
\
6966
2.34k
    return S; \
6967
2.34k
  }
6968
DEFINE_DecodeVSTRVLDR_SYSREG(false) DEFINE_DecodeVSTRVLDR_SYSREG(true)
6969
6970
  static inline DecodeStatus
6971
  DecodeMVE_MEM_pre(MCInst *Inst, unsigned Val, uint64_t Address,
6972
        const void *Decoder, unsigned Rn,
6973
        OperandDecoder RnDecoder, OperandDecoder AddrDecoder)
6974
6.14k
{
6975
6.14k
  DecodeStatus S = MCDisassembler_Success;
6976
6977
6.14k
  unsigned Qd = fieldFromInstruction_4(Val, 13, 3);
6978
6.14k
  unsigned addr = fieldFromInstruction_4(Val, 0, 7) |
6979
6.14k
      (fieldFromInstruction_4(Val, 23, 1) << 7) | (Rn << 8);
6980
6981
6.14k
  if (!Check(&S, RnDecoder(Inst, Rn, Address, Decoder)))
6982
0
    return MCDisassembler_Fail;
6983
6.14k
  if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6984
0
    return MCDisassembler_Fail;
6985
6.14k
  if (!Check(&S, AddrDecoder(Inst, addr, Address, Decoder)))
6986
0
    return MCDisassembler_Fail;
6987
6988
6.14k
  return S;
6989
6.14k
}
6990
6991
#define DEFINE_DecodeMVE_MEM_1_pre(shift) \
6992
  static DecodeStatus CONCAT(DecodeMVE_MEM_1_pre, shift)( \
6993
    MCInst * Inst, unsigned Val, uint64_t Address, \
6994
    const void *Decoder) \
6995
1.49k
  { \
6996
1.49k
    return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, \
6997
1.49k
           fieldFromInstruction_4(Val, 16, 3), \
6998
1.49k
           DecodetGPRRegisterClass, \
6999
1.49k
           CONCAT(DecodeTAddrModeImm7, shift)); \
7000
1.49k
  }
ARMDisassembler.c:DecodeMVE_MEM_1_pre_0
Line
Count
Source
6995
780
  { \
6996
780
    return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, \
6997
780
           fieldFromInstruction_4(Val, 16, 3), \
6998
780
           DecodetGPRRegisterClass, \
6999
780
           CONCAT(DecodeTAddrModeImm7, shift)); \
7000
780
  }
ARMDisassembler.c:DecodeMVE_MEM_1_pre_1
Line
Count
Source
6995
715
  { \
6996
715
    return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, \
6997
715
           fieldFromInstruction_4(Val, 16, 3), \
6998
715
           DecodetGPRRegisterClass, \
6999
715
           CONCAT(DecodeTAddrModeImm7, shift)); \
7000
715
  }
7001
DEFINE_DecodeMVE_MEM_1_pre(0) DEFINE_DecodeMVE_MEM_1_pre(1)
7002
7003
#define DEFINE_DecodeMVE_MEM_2_pre(shift) \
7004
  static DecodeStatus CONCAT(DecodeMVE_MEM_2_pre, shift)( \
7005
    MCInst * Inst, unsigned Val, uint64_t Address, \
7006
    const void *Decoder) \
7007
3.67k
  { \
7008
3.67k
    return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, \
7009
3.67k
           fieldFromInstruction_4(Val, 16, 4), \
7010
3.67k
           DecoderGPRRegisterClass, \
7011
3.67k
           CONCAT(DecodeT2AddrModeImm7, \
7012
3.67k
            CONCAT(shift, 1))); \
7013
3.67k
  }
ARMDisassembler.c:DecodeMVE_MEM_2_pre_0
Line
Count
Source
7007
1.39k
  { \
7008
1.39k
    return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, \
7009
1.39k
           fieldFromInstruction_4(Val, 16, 4), \
7010
1.39k
           DecoderGPRRegisterClass, \
7011
1.39k
           CONCAT(DecodeT2AddrModeImm7, \
7012
1.39k
            CONCAT(shift, 1))); \
7013
1.39k
  }
ARMDisassembler.c:DecodeMVE_MEM_2_pre_1
Line
Count
Source
7007
558
  { \
7008
558
    return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, \
7009
558
           fieldFromInstruction_4(Val, 16, 4), \
7010
558
           DecoderGPRRegisterClass, \
7011
558
           CONCAT(DecodeT2AddrModeImm7, \
7012
558
            CONCAT(shift, 1))); \
7013
558
  }
ARMDisassembler.c:DecodeMVE_MEM_2_pre_2
Line
Count
Source
7007
1.72k
  { \
7008
1.72k
    return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, \
7009
1.72k
           fieldFromInstruction_4(Val, 16, 4), \
7010
1.72k
           DecoderGPRRegisterClass, \
7011
1.72k
           CONCAT(DecodeT2AddrModeImm7, \
7012
1.72k
            CONCAT(shift, 1))); \
7013
1.72k
  }
7014
  DEFINE_DecodeMVE_MEM_2_pre(0) DEFINE_DecodeMVE_MEM_2_pre(
7015
    1) DEFINE_DecodeMVE_MEM_2_pre(2)
7016
7017
#define DEFINE_DecodeMVE_MEM_3_pre(shift) \
7018
  static DecodeStatus CONCAT(DecodeMVE_MEM_3_pre, shift)( \
7019
    MCInst * Inst, unsigned Val, uint64_t Address, \
7020
    const void *Decoder) \
7021
969
  { \
7022
969
    return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, \
7023
969
           fieldFromInstruction_4(Val, 17, 3), \
7024
969
           DecodeMQPRRegisterClass, \
7025
969
           CONCAT(DecodeMveAddrModeQ, shift)); \
7026
969
  }
ARMDisassembler.c:DecodeMVE_MEM_3_pre_2
Line
Count
Source
7021
559
  { \
7022
559
    return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, \
7023
559
           fieldFromInstruction_4(Val, 17, 3), \
7024
559
           DecodeMQPRRegisterClass, \
7025
559
           CONCAT(DecodeMveAddrModeQ, shift)); \
7026
559
  }
ARMDisassembler.c:DecodeMVE_MEM_3_pre_3
Line
Count
Source
7021
410
  { \
7022
410
    return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, \
7023
410
           fieldFromInstruction_4(Val, 17, 3), \
7024
410
           DecodeMQPRRegisterClass, \
7025
410
           CONCAT(DecodeMveAddrModeQ, shift)); \
7026
410
  }
7027
    DEFINE_DecodeMVE_MEM_3_pre(2) DEFINE_DecodeMVE_MEM_3_pre(3)
7028
7029
#define DEFINE_DecodePowerTwoOperand(MinLog, MaxLog) \
7030
  static DecodeStatus CONCAT(DecodePowerTwoOperand, \
7031
           CONCAT(MinLog, MaxLog))( \
7032
    MCInst * Inst, unsigned Val, uint64_t Address, \
7033
    const void *Decoder) \
7034
1.27k
  { \
7035
1.27k
    DecodeStatus S = MCDisassembler_Success; \
7036
1.27k
\
7037
1.27k
    if (Val < MinLog || Val > MaxLog) \
7038
1.27k
      return MCDisassembler_Fail; \
7039
1.27k
\
7040
1.27k
    MCOperand_CreateImm0(Inst, (1LL << Val)); \
7041
1.27k
    return S; \
7042
1.27k
  }
7043
      DEFINE_DecodePowerTwoOperand(0, 3)
7044
7045
#define DEFINE_DecodeMVEPairVectorIndexOperand(start) \
7046
  static DecodeStatus CONCAT(DecodeMVEPairVectorIndexOperand, start)( \
7047
    MCInst * Inst, unsigned Val, uint64_t Address, \
7048
    const void *Decoder) \
7049
0
  { \
7050
0
    DecodeStatus S = MCDisassembler_Success; \
7051
0
\
7052
0
    MCOperand_CreateImm0(Inst, (start + Val)); \
7053
0
\
7054
0
    return S; \
7055
0
  }
Unexecuted instantiation: ARMDisassembler.c:DecodeMVEPairVectorIndexOperand_2
Unexecuted instantiation: ARMDisassembler.c:DecodeMVEPairVectorIndexOperand_0
7056
        DEFINE_DecodeMVEPairVectorIndexOperand(2)
7057
          DEFINE_DecodeMVEPairVectorIndexOperand(0)
7058
7059
            static DecodeStatus
7060
  DecodeMVEVMOVQtoDReg(MCInst *Inst, unsigned Insn, uint64_t Address,
7061
           const void *Decoder)
7062
0
{
7063
0
  DecodeStatus S = MCDisassembler_Success;
7064
0
  unsigned Rt = fieldFromInstruction_4(Insn, 0, 4);
7065
0
  unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
7066
0
  unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) |
7067
0
           fieldFromInstruction_4(Insn, 13, 3));
7068
0
  unsigned index = fieldFromInstruction_4(Insn, 4, 1);
7069
7070
0
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
7071
0
    return MCDisassembler_Fail;
7072
0
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
7073
0
    return MCDisassembler_Fail;
7074
0
  if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
7075
0
    return MCDisassembler_Fail;
7076
0
  if (!Check(&S, CONCAT(DecodeMVEPairVectorIndexOperand,
7077
0
            2)(Inst, index, Address, Decoder)))
7078
0
    return MCDisassembler_Fail;
7079
0
  if (!Check(&S, CONCAT(DecodeMVEPairVectorIndexOperand,
7080
0
            0)(Inst, index, Address, Decoder)))
7081
0
    return MCDisassembler_Fail;
7082
7083
0
  return S;
7084
0
}
7085
7086
static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst *Inst, unsigned Insn,
7087
           uint64_t Address, const void *Decoder)
7088
0
{
7089
0
  DecodeStatus S = MCDisassembler_Success;
7090
0
  unsigned Rt = fieldFromInstruction_4(Insn, 0, 4);
7091
0
  unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
7092
0
  unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) |
7093
0
           fieldFromInstruction_4(Insn, 13, 3));
7094
0
  unsigned index = fieldFromInstruction_4(Insn, 4, 1);
7095
7096
0
  if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
7097
0
    return MCDisassembler_Fail;
7098
0
  if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
7099
0
    return MCDisassembler_Fail;
7100
0
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
7101
0
    return MCDisassembler_Fail;
7102
0
  if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
7103
0
    return MCDisassembler_Fail;
7104
0
  if (!Check(&S, CONCAT(DecodeMVEPairVectorIndexOperand,
7105
0
            2)(Inst, index, Address, Decoder)))
7106
0
    return MCDisassembler_Fail;
7107
0
  if (!Check(&S, CONCAT(DecodeMVEPairVectorIndexOperand,
7108
0
            0)(Inst, index, Address, Decoder)))
7109
0
    return MCDisassembler_Fail;
7110
7111
0
  return S;
7112
0
}
7113
7114
static DecodeStatus DecodeMVEOverlappingLongShift(MCInst *Inst, unsigned Insn,
7115
              uint64_t Address,
7116
              const void *Decoder)
7117
0
{
7118
0
  DecodeStatus S = MCDisassembler_Success;
7119
7120
0
  unsigned RdaLo = fieldFromInstruction_4(Insn, 17, 3) << 1;
7121
0
  unsigned RdaHi = fieldFromInstruction_4(Insn, 9, 3) << 1;
7122
0
  unsigned Rm = fieldFromInstruction_4(Insn, 12, 4);
7123
7124
0
  if (RdaHi == 14) {
7125
    // This value of RdaHi (really indicating pc, because RdaHi has to
7126
    // be an odd-numbered register, so the low bit will be set by the
7127
    // decode function below) indicates that we must decode as SQRSHR
7128
    // or UQRSHL, which both have a single Rda register field with all
7129
    // four bits.
7130
0
    unsigned Rda = fieldFromInstruction_4(Insn, 16, 4);
7131
7132
0
    switch (MCInst_getOpcode(Inst)) {
7133
0
    case ARM_MVE_ASRLr:
7134
0
    case ARM_MVE_SQRSHRL:
7135
0
      MCInst_setOpcode(Inst, (ARM_MVE_SQRSHR));
7136
0
      break;
7137
0
    case ARM_MVE_LSLLr:
7138
0
    case ARM_MVE_UQRSHLL:
7139
0
      MCInst_setOpcode(Inst, (ARM_MVE_UQRSHL));
7140
0
      break;
7141
0
    default:
7142
      // llvm_unreachable("Unexpected starting opcode!");
7143
0
      break;
7144
0
    }
7145
7146
    // Rda as output parameter
7147
0
    if (!Check(&S, DecoderGPRRegisterClass(Inst, Rda, Address,
7148
0
                   Decoder)))
7149
0
      return MCDisassembler_Fail;
7150
7151
    // Rda again as input parameter
7152
0
    if (!Check(&S, DecoderGPRRegisterClass(Inst, Rda, Address,
7153
0
                   Decoder)))
7154
0
      return MCDisassembler_Fail;
7155
7156
    // Rm, the amount to shift by
7157
0
    if (!Check(&S,
7158
0
         DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
7159
0
      return MCDisassembler_Fail;
7160
7161
0
    if (fieldFromInstruction_4(Insn, 6, 3) != 4)
7162
0
      return MCDisassembler_SoftFail;
7163
7164
0
    if (Rda == Rm)
7165
0
      return MCDisassembler_SoftFail;
7166
7167
0
    return S;
7168
0
  }
7169
7170
  // Otherwise, we decode as whichever opcode our caller has already
7171
  // put into Inst. Those all look the same:
7172
7173
  // RdaLo,RdaHi as output parameters
7174
0
  if (!Check(&S,
7175
0
       DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
7176
0
    return MCDisassembler_Fail;
7177
0
  if (!Check(&S,
7178
0
       DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
7179
0
    return MCDisassembler_Fail;
7180
7181
  // RdaLo,RdaHi again as input parameters
7182
0
  if (!Check(&S,
7183
0
       DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
7184
0
    return MCDisassembler_Fail;
7185
0
  if (!Check(&S,
7186
0
       DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
7187
0
    return MCDisassembler_Fail;
7188
7189
  // Rm, the amount to shift by
7190
0
  if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
7191
0
    return MCDisassembler_Fail;
7192
7193
0
  if (MCInst_getOpcode(Inst) == ARM_MVE_SQRSHRL ||
7194
0
      MCInst_getOpcode(Inst) == ARM_MVE_UQRSHLL) {
7195
0
    unsigned Saturate = fieldFromInstruction_4(Insn, 7, 1);
7196
    // Saturate, the bit position for saturation
7197
0
    MCOperand_CreateImm0(Inst, (Saturate));
7198
0
  }
7199
7200
0
  return S;
7201
0
}
7202
7203
static DecodeStatus DecodeMVEVCVTt1fp(MCInst *Inst, unsigned Insn,
7204
              uint64_t Address, const void *Decoder)
7205
1.88k
{
7206
1.88k
  DecodeStatus S = MCDisassembler_Success;
7207
1.88k
  unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) |
7208
1.88k
           fieldFromInstruction_4(Insn, 13, 3));
7209
1.88k
  unsigned Qm = ((fieldFromInstruction_4(Insn, 5, 1) << 3) |
7210
1.88k
           fieldFromInstruction_4(Insn, 1, 3));
7211
1.88k
  unsigned imm6 = fieldFromInstruction_4(Insn, 16, 6);
7212
7213
1.88k
  if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
7214
120
    return MCDisassembler_Fail;
7215
1.76k
  if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
7216
148
    return MCDisassembler_Fail;
7217
1.61k
  if (!Check(&S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
7218
0
    return MCDisassembler_Fail;
7219
7220
1.61k
  return S;
7221
1.61k
}
7222
7223
#define DEFINE_DecodeMVEVCMP(scalar, predicate_decoder) \
7224
  static DecodeStatus CONCAT(DecodeMVEVCMP, \
7225
           CONCAT(scalar, predicate_decoder))( \
7226
    MCInst * Inst, unsigned Insn, uint64_t Address, \
7227
    const void *Decoder) \
7228
5.04k
  { \
7229
5.04k
    DecodeStatus S = MCDisassembler_Success; \
7230
5.04k
    MCOperand_CreateReg0(Inst, (ARM_VPR)); \
7231
5.04k
    unsigned Qn = fieldFromInstruction_4(Insn, 17, 3); \
7232
5.04k
    if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, \
7233
5.04k
                   Decoder))) \
7234
5.04k
      return MCDisassembler_Fail; \
7235
5.04k
\
7236
5.04k
    unsigned fc; \
7237
5.04k
\
7238
5.04k
    if (scalar) { \
7239
2.54k
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7240
2.54k
           fieldFromInstruction_4(Insn, 7, 1) | \
7241
2.54k
           fieldFromInstruction_4(Insn, 5, 1) << 1; \
7242
2.54k
      unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); \
7243
2.54k
      if (!Check(&S, DecodeGPRwithZRRegisterClass( \
7244
2.54k
                 Inst, Rm, Address, Decoder))) \
7245
2.54k
        return MCDisassembler_Fail; \
7246
2.54k
    } else { \
7247
2.50k
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7248
2.50k
           fieldFromInstruction_4(Insn, 7, 1) | \
7249
2.50k
           fieldFromInstruction_4(Insn, 0, 1) << 1; \
7250
2.50k
      unsigned Qm = fieldFromInstruction_4(Insn, 5, 1) \
7251
2.50k
                << 4 | \
7252
2.50k
              fieldFromInstruction_4(Insn, 1, 3); \
7253
2.50k
      if (!Check(&S, DecodeMQPRRegisterClass( \
7254
2.50k
                 Inst, Qm, Address, Decoder))) \
7255
2.50k
        return MCDisassembler_Fail; \
7256
2.50k
    } \
7257
5.04k
\
7258
5.04k
    if (!Check(&S, predicate_decoder(Inst, fc, Address, Decoder))) \
7259
4.13k
      return MCDisassembler_Fail; \
7260
4.13k
\
7261
4.13k
    MCOperand_CreateImm0(Inst, (ARMVCC_None)); \
7262
3.31k
    MCOperand_CreateReg0(Inst, (0)); \
7263
3.31k
    MCOperand_CreateImm0(Inst, (0)); \
7264
3.31k
\
7265
3.31k
    return S; \
7266
4.13k
  }
ARMDisassembler.c:DecodeMVEVCMP_0_DecodeRestrictedIPredicateOperand
Line
Count
Source
7228
555
  { \
7229
555
    DecodeStatus S = MCDisassembler_Success; \
7230
555
    MCOperand_CreateReg0(Inst, (ARM_VPR)); \
7231
555
    unsigned Qn = fieldFromInstruction_4(Insn, 17, 3); \
7232
555
    if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, \
7233
555
                   Decoder))) \
7234
555
      return MCDisassembler_Fail; \
7235
555
\
7236
555
    unsigned fc; \
7237
555
\
7238
555
    if (scalar) { \
7239
0
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7240
0
           fieldFromInstruction_4(Insn, 7, 1) | \
7241
0
           fieldFromInstruction_4(Insn, 5, 1) << 1; \
7242
0
      unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); \
7243
0
      if (!Check(&S, DecodeGPRwithZRRegisterClass( \
7244
0
                 Inst, Rm, Address, Decoder))) \
7245
0
        return MCDisassembler_Fail; \
7246
555
    } else { \
7247
555
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7248
555
           fieldFromInstruction_4(Insn, 7, 1) | \
7249
555
           fieldFromInstruction_4(Insn, 0, 1) << 1; \
7250
555
      unsigned Qm = fieldFromInstruction_4(Insn, 5, 1) \
7251
555
                << 4 | \
7252
555
              fieldFromInstruction_4(Insn, 1, 3); \
7253
555
      if (!Check(&S, DecodeMQPRRegisterClass( \
7254
555
                 Inst, Qm, Address, Decoder))) \
7255
555
        return MCDisassembler_Fail; \
7256
555
    } \
7257
555
\
7258
555
    if (!Check(&S, predicate_decoder(Inst, fc, Address, Decoder))) \
7259
358
      return MCDisassembler_Fail; \
7260
358
\
7261
358
    MCOperand_CreateImm0(Inst, (ARMVCC_None)); \
7262
358
    MCOperand_CreateReg0(Inst, (0)); \
7263
358
    MCOperand_CreateImm0(Inst, (0)); \
7264
358
\
7265
358
    return S; \
7266
358
  }
ARMDisassembler.c:DecodeMVEVCMP_0_DecodeRestrictedUPredicateOperand
Line
Count
Source
7228
296
  { \
7229
296
    DecodeStatus S = MCDisassembler_Success; \
7230
296
    MCOperand_CreateReg0(Inst, (ARM_VPR)); \
7231
296
    unsigned Qn = fieldFromInstruction_4(Insn, 17, 3); \
7232
296
    if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, \
7233
296
                   Decoder))) \
7234
296
      return MCDisassembler_Fail; \
7235
296
\
7236
296
    unsigned fc; \
7237
296
\
7238
296
    if (scalar) { \
7239
0
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7240
0
           fieldFromInstruction_4(Insn, 7, 1) | \
7241
0
           fieldFromInstruction_4(Insn, 5, 1) << 1; \
7242
0
      unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); \
7243
0
      if (!Check(&S, DecodeGPRwithZRRegisterClass( \
7244
0
                 Inst, Rm, Address, Decoder))) \
7245
0
        return MCDisassembler_Fail; \
7246
296
    } else { \
7247
296
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7248
296
           fieldFromInstruction_4(Insn, 7, 1) | \
7249
296
           fieldFromInstruction_4(Insn, 0, 1) << 1; \
7250
296
      unsigned Qm = fieldFromInstruction_4(Insn, 5, 1) \
7251
296
                << 4 | \
7252
296
              fieldFromInstruction_4(Insn, 1, 3); \
7253
296
      if (!Check(&S, DecodeMQPRRegisterClass( \
7254
296
                 Inst, Qm, Address, Decoder))) \
7255
296
        return MCDisassembler_Fail; \
7256
296
    } \
7257
296
\
7258
296
    if (!Check(&S, predicate_decoder(Inst, fc, Address, Decoder))) \
7259
84
      return MCDisassembler_Fail; \
7260
84
\
7261
84
    MCOperand_CreateImm0(Inst, (ARMVCC_None)); \
7262
84
    MCOperand_CreateReg0(Inst, (0)); \
7263
84
    MCOperand_CreateImm0(Inst, (0)); \
7264
84
\
7265
84
    return S; \
7266
84
  }
ARMDisassembler.c:DecodeMVEVCMP_0_DecodeRestrictedSPredicateOperand
Line
Count
Source
7228
538
  { \
7229
538
    DecodeStatus S = MCDisassembler_Success; \
7230
538
    MCOperand_CreateReg0(Inst, (ARM_VPR)); \
7231
538
    unsigned Qn = fieldFromInstruction_4(Insn, 17, 3); \
7232
538
    if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, \
7233
538
                   Decoder))) \
7234
538
      return MCDisassembler_Fail; \
7235
538
\
7236
538
    unsigned fc; \
7237
538
\
7238
538
    if (scalar) { \
7239
0
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7240
0
           fieldFromInstruction_4(Insn, 7, 1) | \
7241
0
           fieldFromInstruction_4(Insn, 5, 1) << 1; \
7242
0
      unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); \
7243
0
      if (!Check(&S, DecodeGPRwithZRRegisterClass( \
7244
0
                 Inst, Rm, Address, Decoder))) \
7245
0
        return MCDisassembler_Fail; \
7246
538
    } else { \
7247
538
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7248
538
           fieldFromInstruction_4(Insn, 7, 1) | \
7249
538
           fieldFromInstruction_4(Insn, 0, 1) << 1; \
7250
538
      unsigned Qm = fieldFromInstruction_4(Insn, 5, 1) \
7251
538
                << 4 | \
7252
538
              fieldFromInstruction_4(Insn, 1, 3); \
7253
538
      if (!Check(&S, DecodeMQPRRegisterClass( \
7254
538
                 Inst, Qm, Address, Decoder))) \
7255
538
        return MCDisassembler_Fail; \
7256
538
    } \
7257
538
\
7258
538
    if (!Check(&S, predicate_decoder(Inst, fc, Address, Decoder))) \
7259
286
      return MCDisassembler_Fail; \
7260
286
\
7261
286
    MCOperand_CreateImm0(Inst, (ARMVCC_None)); \
7262
286
    MCOperand_CreateReg0(Inst, (0)); \
7263
286
    MCOperand_CreateImm0(Inst, (0)); \
7264
286
\
7265
286
    return S; \
7266
286
  }
ARMDisassembler.c:DecodeMVEVCMP_1_DecodeRestrictedIPredicateOperand
Line
Count
Source
7228
336
  { \
7229
336
    DecodeStatus S = MCDisassembler_Success; \
7230
336
    MCOperand_CreateReg0(Inst, (ARM_VPR)); \
7231
336
    unsigned Qn = fieldFromInstruction_4(Insn, 17, 3); \
7232
336
    if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, \
7233
336
                   Decoder))) \
7234
336
      return MCDisassembler_Fail; \
7235
336
\
7236
336
    unsigned fc; \
7237
336
\
7238
336
    if (scalar) { \
7239
336
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7240
336
           fieldFromInstruction_4(Insn, 7, 1) | \
7241
336
           fieldFromInstruction_4(Insn, 5, 1) << 1; \
7242
336
      unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); \
7243
336
      if (!Check(&S, DecodeGPRwithZRRegisterClass( \
7244
336
                 Inst, Rm, Address, Decoder))) \
7245
336
        return MCDisassembler_Fail; \
7246
336
    } else { \
7247
0
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7248
0
           fieldFromInstruction_4(Insn, 7, 1) | \
7249
0
           fieldFromInstruction_4(Insn, 0, 1) << 1; \
7250
0
      unsigned Qm = fieldFromInstruction_4(Insn, 5, 1) \
7251
0
                << 4 | \
7252
0
              fieldFromInstruction_4(Insn, 1, 3); \
7253
0
      if (!Check(&S, DecodeMQPRRegisterClass( \
7254
0
                 Inst, Qm, Address, Decoder))) \
7255
0
        return MCDisassembler_Fail; \
7256
0
    } \
7257
336
\
7258
336
    if (!Check(&S, predicate_decoder(Inst, fc, Address, Decoder))) \
7259
336
      return MCDisassembler_Fail; \
7260
336
\
7261
336
    MCOperand_CreateImm0(Inst, (ARMVCC_None)); \
7262
336
    MCOperand_CreateReg0(Inst, (0)); \
7263
336
    MCOperand_CreateImm0(Inst, (0)); \
7264
336
\
7265
336
    return S; \
7266
336
  }
ARMDisassembler.c:DecodeMVEVCMP_1_DecodeRestrictedUPredicateOperand
Line
Count
Source
7228
350
  { \
7229
350
    DecodeStatus S = MCDisassembler_Success; \
7230
350
    MCOperand_CreateReg0(Inst, (ARM_VPR)); \
7231
350
    unsigned Qn = fieldFromInstruction_4(Insn, 17, 3); \
7232
350
    if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, \
7233
350
                   Decoder))) \
7234
350
      return MCDisassembler_Fail; \
7235
350
\
7236
350
    unsigned fc; \
7237
350
\
7238
350
    if (scalar) { \
7239
350
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7240
350
           fieldFromInstruction_4(Insn, 7, 1) | \
7241
350
           fieldFromInstruction_4(Insn, 5, 1) << 1; \
7242
350
      unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); \
7243
350
      if (!Check(&S, DecodeGPRwithZRRegisterClass( \
7244
350
                 Inst, Rm, Address, Decoder))) \
7245
350
        return MCDisassembler_Fail; \
7246
350
    } else { \
7247
0
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7248
0
           fieldFromInstruction_4(Insn, 7, 1) | \
7249
0
           fieldFromInstruction_4(Insn, 0, 1) << 1; \
7250
0
      unsigned Qm = fieldFromInstruction_4(Insn, 5, 1) \
7251
0
                << 4 | \
7252
0
              fieldFromInstruction_4(Insn, 1, 3); \
7253
0
      if (!Check(&S, DecodeMQPRRegisterClass( \
7254
0
                 Inst, Qm, Address, Decoder))) \
7255
0
        return MCDisassembler_Fail; \
7256
0
    } \
7257
350
\
7258
350
    if (!Check(&S, predicate_decoder(Inst, fc, Address, Decoder))) \
7259
350
      return MCDisassembler_Fail; \
7260
350
\
7261
350
    MCOperand_CreateImm0(Inst, (ARMVCC_None)); \
7262
350
    MCOperand_CreateReg0(Inst, (0)); \
7263
350
    MCOperand_CreateImm0(Inst, (0)); \
7264
350
\
7265
350
    return S; \
7266
350
  }
ARMDisassembler.c:DecodeMVEVCMP_1_DecodeRestrictedSPredicateOperand
Line
Count
Source
7228
906
  { \
7229
906
    DecodeStatus S = MCDisassembler_Success; \
7230
906
    MCOperand_CreateReg0(Inst, (ARM_VPR)); \
7231
906
    unsigned Qn = fieldFromInstruction_4(Insn, 17, 3); \
7232
906
    if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, \
7233
906
                   Decoder))) \
7234
906
      return MCDisassembler_Fail; \
7235
906
\
7236
906
    unsigned fc; \
7237
906
\
7238
906
    if (scalar) { \
7239
906
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7240
906
           fieldFromInstruction_4(Insn, 7, 1) | \
7241
906
           fieldFromInstruction_4(Insn, 5, 1) << 1; \
7242
906
      unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); \
7243
906
      if (!Check(&S, DecodeGPRwithZRRegisterClass( \
7244
906
                 Inst, Rm, Address, Decoder))) \
7245
906
        return MCDisassembler_Fail; \
7246
906
    } else { \
7247
0
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7248
0
           fieldFromInstruction_4(Insn, 7, 1) | \
7249
0
           fieldFromInstruction_4(Insn, 0, 1) << 1; \
7250
0
      unsigned Qm = fieldFromInstruction_4(Insn, 5, 1) \
7251
0
                << 4 | \
7252
0
              fieldFromInstruction_4(Insn, 1, 3); \
7253
0
      if (!Check(&S, DecodeMQPRRegisterClass( \
7254
0
                 Inst, Qm, Address, Decoder))) \
7255
0
        return MCDisassembler_Fail; \
7256
0
    } \
7257
906
\
7258
906
    if (!Check(&S, predicate_decoder(Inst, fc, Address, Decoder))) \
7259
906
      return MCDisassembler_Fail; \
7260
906
\
7261
906
    MCOperand_CreateImm0(Inst, (ARMVCC_None)); \
7262
906
    MCOperand_CreateReg0(Inst, (0)); \
7263
906
    MCOperand_CreateImm0(Inst, (0)); \
7264
906
\
7265
906
    return S; \
7266
906
  }
ARMDisassembler.c:DecodeMVEVCMP_0_DecodeRestrictedFPPredicateOperand
Line
Count
Source
7228
1.11k
  { \
7229
1.11k
    DecodeStatus S = MCDisassembler_Success; \
7230
1.11k
    MCOperand_CreateReg0(Inst, (ARM_VPR)); \
7231
1.11k
    unsigned Qn = fieldFromInstruction_4(Insn, 17, 3); \
7232
1.11k
    if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, \
7233
1.11k
                   Decoder))) \
7234
1.11k
      return MCDisassembler_Fail; \
7235
1.11k
\
7236
1.11k
    unsigned fc; \
7237
1.11k
\
7238
1.11k
    if (scalar) { \
7239
0
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7240
0
           fieldFromInstruction_4(Insn, 7, 1) | \
7241
0
           fieldFromInstruction_4(Insn, 5, 1) << 1; \
7242
0
      unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); \
7243
0
      if (!Check(&S, DecodeGPRwithZRRegisterClass( \
7244
0
                 Inst, Rm, Address, Decoder))) \
7245
0
        return MCDisassembler_Fail; \
7246
1.11k
    } else { \
7247
1.11k
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7248
1.11k
           fieldFromInstruction_4(Insn, 7, 1) | \
7249
1.11k
           fieldFromInstruction_4(Insn, 0, 1) << 1; \
7250
1.11k
      unsigned Qm = fieldFromInstruction_4(Insn, 5, 1) \
7251
1.11k
                << 4 | \
7252
1.11k
              fieldFromInstruction_4(Insn, 1, 3); \
7253
1.11k
      if (!Check(&S, DecodeMQPRRegisterClass( \
7254
1.11k
                 Inst, Qm, Address, Decoder))) \
7255
1.11k
        return MCDisassembler_Fail; \
7256
1.11k
    } \
7257
1.11k
\
7258
1.11k
    if (!Check(&S, predicate_decoder(Inst, fc, Address, Decoder))) \
7259
868
      return MCDisassembler_Fail; \
7260
868
\
7261
868
    MCOperand_CreateImm0(Inst, (ARMVCC_None)); \
7262
436
    MCOperand_CreateReg0(Inst, (0)); \
7263
436
    MCOperand_CreateImm0(Inst, (0)); \
7264
436
\
7265
436
    return S; \
7266
868
  }
ARMDisassembler.c:DecodeMVEVCMP_1_DecodeRestrictedFPPredicateOperand
Line
Count
Source
7228
951
  { \
7229
951
    DecodeStatus S = MCDisassembler_Success; \
7230
951
    MCOperand_CreateReg0(Inst, (ARM_VPR)); \
7231
951
    unsigned Qn = fieldFromInstruction_4(Insn, 17, 3); \
7232
951
    if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, \
7233
951
                   Decoder))) \
7234
951
      return MCDisassembler_Fail; \
7235
951
\
7236
951
    unsigned fc; \
7237
951
\
7238
951
    if (scalar) { \
7239
951
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7240
951
           fieldFromInstruction_4(Insn, 7, 1) | \
7241
951
           fieldFromInstruction_4(Insn, 5, 1) << 1; \
7242
951
      unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); \
7243
951
      if (!Check(&S, DecodeGPRwithZRRegisterClass( \
7244
951
                 Inst, Rm, Address, Decoder))) \
7245
951
        return MCDisassembler_Fail; \
7246
951
    } else { \
7247
0
      fc = fieldFromInstruction_4(Insn, 12, 1) << 2 | \
7248
0
           fieldFromInstruction_4(Insn, 7, 1) | \
7249
0
           fieldFromInstruction_4(Insn, 0, 1) << 1; \
7250
0
      unsigned Qm = fieldFromInstruction_4(Insn, 5, 1) \
7251
0
                << 4 | \
7252
0
              fieldFromInstruction_4(Insn, 1, 3); \
7253
0
      if (!Check(&S, DecodeMQPRRegisterClass( \
7254
0
                 Inst, Qm, Address, Decoder))) \
7255
0
        return MCDisassembler_Fail; \
7256
0
    } \
7257
951
\
7258
951
    if (!Check(&S, predicate_decoder(Inst, fc, Address, Decoder))) \
7259
951
      return MCDisassembler_Fail; \
7260
951
\
7261
951
    MCOperand_CreateImm0(Inst, (ARMVCC_None)); \
7262
554
    MCOperand_CreateReg0(Inst, (0)); \
7263
554
    MCOperand_CreateImm0(Inst, (0)); \
7264
554
\
7265
554
    return S; \
7266
951
  }
7267
DEFINE_DecodeMVEVCMP(false, DecodeRestrictedIPredicateOperand) DEFINE_DecodeMVEVCMP(
7268
  false, DecodeRestrictedUPredicateOperand)
7269
  DEFINE_DecodeMVEVCMP(false, DecodeRestrictedSPredicateOperand)
7270
    DEFINE_DecodeMVEVCMP(true, DecodeRestrictedIPredicateOperand)
7271
      DEFINE_DecodeMVEVCMP(true,
7272
               DecodeRestrictedUPredicateOperand)
7273
        DEFINE_DecodeMVEVCMP(
7274
          true, DecodeRestrictedSPredicateOperand)
7275
          DEFINE_DecodeMVEVCMP(
7276
            false,
7277
            DecodeRestrictedFPPredicateOperand)
7278
            DEFINE_DecodeMVEVCMP(
7279
              true,
7280
              DecodeRestrictedFPPredicateOperand)
7281
7282
              static DecodeStatus
7283
  DecodeMveVCTP(MCInst *Inst, unsigned Insn, uint64_t Address,
7284
          const void *Decoder)
7285
426
{
7286
426
  DecodeStatus S = MCDisassembler_Success;
7287
426
  MCOperand_CreateReg0(Inst, (ARM_VPR));
7288
426
  unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
7289
426
  if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
7290
0
    return MCDisassembler_Fail;
7291
426
  return S;
7292
426
}
7293
7294
static DecodeStatus DecodeMVEVPNOT(MCInst *Inst, unsigned Insn,
7295
           uint64_t Address, const void *Decoder)
7296
66
{
7297
66
  DecodeStatus S = MCDisassembler_Success;
7298
66
  MCOperand_CreateReg0(Inst, (ARM_VPR));
7299
66
  MCOperand_CreateReg0(Inst, (ARM_VPR));
7300
66
  return S;
7301
66
}
7302
7303
static DecodeStatus DecodeT2AddSubSPImm(MCInst *Inst, unsigned Insn,
7304
          uint64_t Address, const void *Decoder)
7305
959
{
7306
959
  const unsigned Rd = fieldFromInstruction_4(Insn, 8, 4);
7307
959
  const unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
7308
959
  const unsigned Imm12 = fieldFromInstruction_4(Insn, 26, 1) << 11 |
7309
959
             fieldFromInstruction_4(Insn, 12, 3) << 8 |
7310
959
             fieldFromInstruction_4(Insn, 0, 8);
7311
959
  const unsigned TypeT3 = fieldFromInstruction_4(Insn, 25, 1);
7312
959
  unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1);
7313
959
  unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1);
7314
959
  unsigned S = fieldFromInstruction_4(Insn, 20, 1);
7315
959
  if (sign1 != sign2)
7316
0
    return MCDisassembler_Fail;
7317
7318
  // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm)
7319
959
  DecodeStatus DS = MCDisassembler_Success;
7320
959
  if ((!Check(&DS, DecodeGPRspRegisterClass(Inst, Rd, Address,
7321
959
              Decoder))) || // dst
7322
959
      (!Check(&DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder))))
7323
0
    return MCDisassembler_Fail;
7324
959
  if (TypeT3) {
7325
218
    MCInst_setOpcode(Inst,
7326
218
         (sign1 ? ARM_t2SUBspImm12 : ARM_t2ADDspImm12));
7327
218
    MCOperand_CreateImm0(Inst, (Imm12)); // zext imm12
7328
741
  } else {
7329
741
    MCInst_setOpcode(Inst,
7330
741
         (sign1 ? ARM_t2SUBspImm : ARM_t2ADDspImm));
7331
741
    if (!Check(&DS, DecodeT2SOImm(Inst, Imm12, Address,
7332
741
                Decoder)))      // imm12
7333
0
      return MCDisassembler_Fail;
7334
741
    if (!Check(&DS, DecodeCCOutOperand(Inst, S, Address,
7335
741
               Decoder))) // cc_out
7336
0
      return MCDisassembler_Fail;
7337
741
  }
7338
7339
959
  return DS;
7340
959
}
7341
7342
DecodeStatus ARM_LLVM_getInstruction(csh handle, const uint8_t *code,
7343
             size_t code_len, MCInst *instr,
7344
             uint16_t *size, uint64_t address,
7345
             void *info)
7346
1.22M
{
7347
1.22M
  return getInstruction(handle, code, code_len, instr, size, address,
7348
1.22M
            info);
7349
1.22M
}