Coverage Report

Created: 2023-09-25 06:24

/src/capstonenext/arch/Mips/MipsDisassembler.c
Line
Count
Source (jump to first uncovered line)
1
//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
10
// This file is part of the Mips Disassembler.
11
//
12
//===----------------------------------------------------------------------===//
13
14
/* Capstone Disassembly Engine */
15
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
16
17
#ifdef CAPSTONE_HAS_MIPS
18
19
#include <stdio.h>
20
#include <string.h>
21
22
#include "capstone/platform.h"
23
24
#include "MipsDisassembler.h"
25
26
#include "../../utils.h"
27
28
#include "../../MCRegisterInfo.h"
29
#include "../../SStream.h"
30
31
#include "../../MathExtras.h"
32
33
//#include "Mips.h"
34
//#include "MipsRegisterInfo.h"
35
//#include "MipsSubtarget.h"
36
#include "../../MCFixedLenDisassembler.h"
37
#include "../../MCInst.h"
38
//#include "llvm/MC/MCSubtargetInfo.h"
39
#include "../../MCRegisterInfo.h"
40
#include "../../MCDisassembler.h"
41
42
// Forward declare these because the autogenerated code will reference them.
43
// Definitions are further down.
44
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
45
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
46
47
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
48
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
49
50
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst,
51
    unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
52
53
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst,
54
    unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
55
56
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst,
57
    unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
58
59
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
60
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
61
62
static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
63
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
64
65
static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst,
66
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
67
68
static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
69
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
70
71
static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
72
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
73
74
static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
75
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
76
77
static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
78
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
79
80
static DecodeStatus DecodeCCRegisterClass(MCInst *Inst,
81
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
82
83
static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
84
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
85
86
static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
87
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
88
89
static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
90
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
91
92
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
93
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
94
95
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
96
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
97
98
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
99
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
100
101
static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
102
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
103
104
static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
105
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
106
107
static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
108
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
109
110
static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
111
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
112
113
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
114
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
115
116
static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
117
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
118
119
static DecodeStatus DecodeBranchTarget(MCInst *Inst,
120
    unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
121
122
static DecodeStatus DecodeJumpTarget(MCInst *Inst,
123
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
124
125
static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
126
    unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
127
128
static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
129
    unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
130
131
// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
132
// shifted left by 1 bit.
133
static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst,
134
    unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
135
136
// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
137
// shifted left by 1 bit.
138
static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst,
139
    unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
140
141
// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
142
// shifted left by 1 bit.
143
static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
144
    unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
145
146
// DecodeJumpTargetMM - Decode microMIPS jump target, which is
147
// shifted left by 1 bit.
148
static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
149
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
150
151
static DecodeStatus DecodeMem(MCInst *Inst,
152
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
153
154
static DecodeStatus DecodeCacheOp(MCInst *Inst,
155
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
156
157
static DecodeStatus DecodeCacheOpR6(MCInst *Inst,
158
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
159
160
static DecodeStatus DecodeCacheOpMM(MCInst *Inst,
161
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
162
163
static DecodeStatus DecodeSyncI(MCInst *Inst,
164
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
165
166
static DecodeStatus DecodeMSA128Mem(MCInst *Inst,
167
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
168
169
static DecodeStatus DecodeMemMMImm4(MCInst *Inst,
170
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
171
172
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst,
173
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
174
175
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst,
176
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
177
178
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst,
179
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
180
181
static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
182
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
183
184
static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
185
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
186
187
static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn,
188
    uint64_t Address, const MCRegisterInfo *Decoder);
189
190
static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn,
191
    uint64_t Address, MCRegisterInfo *Decoder);
192
193
static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn,
194
    uint64_t Address, MCRegisterInfo *Decoder);
195
196
static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn,
197
    uint64_t Address, MCRegisterInfo *Decoder);
198
199
static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
200
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
201
202
static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst,
203
    unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
204
205
static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst,
206
    unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
207
208
static DecodeStatus DecodeLiSimm7(MCInst *Inst,
209
    unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
210
211
static DecodeStatus DecodeSimm4(MCInst *Inst,
212
    unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
213
214
static DecodeStatus DecodeSimm16(MCInst *Inst,
215
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
216
217
// Decode the immediate field of an LSA instruction which
218
// is off by one.
219
static DecodeStatus DecodeLSAImm(MCInst *Inst,
220
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
221
222
static DecodeStatus DecodeInsSize(MCInst *Inst,
223
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
224
225
static DecodeStatus DecodeExtSize(MCInst *Inst,
226
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
227
228
static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
229
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
230
231
static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
232
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
233
234
static DecodeStatus DecodeSimm9SP(MCInst *Inst,
235
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
236
237
static DecodeStatus DecodeANDI16Imm(MCInst *Inst,
238
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
239
240
static DecodeStatus DecodeUImm5lsl2(MCInst *Inst,
241
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
242
243
static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst,
244
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
245
246
/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
247
/// handle.
248
static DecodeStatus DecodeINSVE_DF_4(MCInst *MI,
249
    uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
250
251
static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI,
252
    uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
253
254
static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI,
255
    uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
256
257
static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI,
258
    uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
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260
static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI,
261
    uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
262
263
static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI,
264
    uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
265
266
static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI,
267
    uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
268
269
static DecodeStatus DecodeRegListOperand(MCInst *Inst,
270
    uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
271
272
static DecodeStatus DecodeRegListOperand16(MCInst *Inst,
273
    uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
274
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static DecodeStatus DecodeMovePRegPair(MCInst *Inst,
276
    uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
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#define GET_SUBTARGETINFO_ENUM
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#include "MipsGenSubtargetInfo.inc"
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// Hacky: enable all features for disassembler
282
static uint64_t getFeatureBits(int mode)
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213k
{
284
213k
  uint64_t Bits = (uint64_t)-1; // include every features at first
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  // By default we do not support Mips1
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213k
  Bits &= ~Mips_FeatureMips1;
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  // No MicroMips
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213k
  Bits &= ~Mips_FeatureMicroMips;
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  // ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate()
293
  // some features are mutually execlusive
294
213k
  if (mode & CS_MODE_16) {
295
    //Bits &= ~Mips_FeatureMips32r2;
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    //Bits &= ~Mips_FeatureMips32;
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    //Bits &= ~Mips_FeatureFPIdx;
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    //Bits &= ~Mips_FeatureBitCount;
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    //Bits &= ~Mips_FeatureSwap;
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    //Bits &= ~Mips_FeatureSEInReg;
301
    //Bits &= ~Mips_FeatureMips64r2;
302
    //Bits &= ~Mips_FeatureFP64Bit;
303
213k
  } else if (mode & CS_MODE_32) {
304
44.0k
    Bits &= ~Mips_FeatureMips16;
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44.0k
    Bits &= ~Mips_FeatureFP64Bit;
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44.0k
    Bits &= ~Mips_FeatureMips64r2;
307
44.0k
    Bits &= ~Mips_FeatureMips32r6;
308
44.0k
    Bits &= ~Mips_FeatureMips64r6;
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169k
  } else if (mode & CS_MODE_64) {
310
116k
    Bits &= ~Mips_FeatureMips16;
311
116k
    Bits &= ~Mips_FeatureMips64r6;
312
116k
    Bits &= ~Mips_FeatureMips32r6;
313
116k
  } else if (mode & CS_MODE_MIPS32R6) {
314
52.7k
    Bits |= Mips_FeatureMips32r6;
315
52.7k
    Bits &= ~Mips_FeatureMips16;
316
52.7k
    Bits &= ~Mips_FeatureFP64Bit;
317
52.7k
    Bits &= ~Mips_FeatureMips64r6;
318
52.7k
    Bits &= ~Mips_FeatureMips64r2;
319
52.7k
  }
320
321
213k
  if (mode & CS_MODE_MICRO) {
322
42.2k
    Bits |= Mips_FeatureMicroMips;
323
42.2k
    Bits &= ~Mips_FeatureMips4_32r2;
324
42.2k
    Bits &= ~Mips_FeatureMips2;
325
42.2k
  }
326
327
213k
  return Bits;
328
213k
}
329
330
#include "MipsGenDisassemblerTables.inc"
331
332
#define GET_REGINFO_ENUM
333
#include "MipsGenRegisterInfo.inc"
334
335
#define GET_REGINFO_MC_DESC
336
#include "MipsGenRegisterInfo.inc"
337
338
#define GET_INSTRINFO_ENUM
339
#include "MipsGenInstrInfo.inc"
340
341
void Mips_init(MCRegisterInfo *MRI)
342
4.56k
{
343
  // InitMCRegisterInfo(MipsRegDesc, 394, RA, PC,
344
  //    MipsMCRegisterClasses, 62,
345
  //    MipsRegUnitRoots,
346
  //    273,
347
  //    MipsRegDiffLists,
348
  //    MipsLaneMaskLists,
349
  //    MipsRegStrings,
350
  //    MipsRegClassStrings,
351
  //    MipsSubRegIdxLists,
352
  //    12,
353
  //    MipsSubRegIdxRanges,
354
  //    MipsRegEncodingTable);
355
356
357
4.56k
  MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394,
358
4.56k
      0, 0,
359
4.56k
      MipsMCRegisterClasses, 62,
360
4.56k
      0, 0,
361
4.56k
      MipsRegDiffLists,
362
4.56k
      0,
363
4.56k
      MipsSubRegIdxLists, 12,
364
4.56k
      0);
365
4.56k
}
366
367
/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
368
/// according to the given endianess.
369
static void readInstruction16(unsigned char *code, uint32_t *insn,
370
    bool isBigEndian)
371
30.8k
{
372
  // We want to read exactly 2 Bytes of data.
373
30.8k
  if (isBigEndian)
374
11.8k
    *insn = (code[0] << 8) | code[1];
375
19.0k
  else
376
19.0k
    *insn = (code[1] << 8) | code[0];
377
30.8k
}
378
379
/// readInstruction - read four bytes from the MemoryObject
380
/// and return 32 bit word sorted according to the given endianess
381
static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips)
382
120k
{
383
  // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
384
  // always precede the low 16 bits in the instruction stream (that is, they
385
  // are placed at lower addresses in the instruction stream).
386
  //
387
  // microMIPS byte ordering:
388
  //   Big-endian:    0 | 1 | 2 | 3
389
  //   Little-endian: 1 | 0 | 3 | 2
390
391
  // We want to read exactly 4 Bytes of data.
392
120k
  if (isBigEndian) {
393
    // Encoded as a big-endian 32-bit word in the stream.
394
59.9k
    *insn =
395
59.9k
      (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24);
396
60.1k
  } else {
397
60.1k
    if (isMicroMips) {
398
6.26k
      *insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) |
399
6.26k
        ((uint32_t) code[1] << 24);
400
53.9k
    } else {
401
53.9k
      *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) |
402
53.9k
        ((uint32_t) code[3] << 24);
403
53.9k
    }
404
60.1k
  }
405
120k
}
406
407
static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
408
    const uint8_t *code, size_t code_len,
409
    uint16_t *Size,
410
    uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI)
411
140k
{
412
140k
  uint32_t Insn;
413
140k
  DecodeStatus Result;
414
415
140k
  if (instr->flat_insn->detail) {
416
140k
    memset(instr->flat_insn->detail, 0, offsetof(cs_detail, mips)+sizeof(cs_mips));
417
140k
  }
418
419
140k
  if (mode & CS_MODE_MICRO) {
420
30.9k
    if (code_len < 2)
421
      // not enough data
422
151
      return MCDisassembler_Fail;
423
424
30.8k
    readInstruction16((unsigned char*)code, &Insn, isBigEndian);
425
426
    // Calling the auto-generated decoder function.
427
30.8k
    Result = decodeInstruction(DecoderTableMicroMips16, instr, Insn, Address, MRI, mode);
428
30.8k
    if (Result != MCDisassembler_Fail) {
429
19.2k
      *Size = 2;
430
19.2k
      return Result;
431
19.2k
    }
432
433
11.5k
    if (code_len < 4)
434
      // not enough data
435
99
      return MCDisassembler_Fail;
436
437
11.4k
    readInstruction32((unsigned char*)code, &Insn, isBigEndian, true);
438
439
    //DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
440
    // Calling the auto-generated decoder function.
441
11.4k
    Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, MRI, mode);
442
11.4k
    if (Result != MCDisassembler_Fail) {
443
11.3k
      *Size = 4;
444
11.3k
      return Result;
445
11.3k
    }
446
129
    return MCDisassembler_Fail;
447
11.4k
  }
448
449
109k
  if (code_len < 4)
450
    // not enough data
451
1.11k
    return MCDisassembler_Fail;
452
453
108k
  readInstruction32((unsigned char*)code, &Insn, isBigEndian, false);
454
455
108k
  if ((mode & CS_MODE_MIPS2) && ((mode & CS_MODE_MIPS3) == 0)) {
456
    // DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
457
0
    Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode);
458
0
    if (Result != MCDisassembler_Fail) {
459
0
      *Size = 4;
460
0
      return Result;
461
0
    }
462
0
  }
463
464
108k
  if ((mode & CS_MODE_MIPS32R6) && (mode & CS_MODE_MIPS64)) {
465
    // DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
466
0
    Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
467
0
        Address, MRI, mode);
468
0
    if (Result != MCDisassembler_Fail) {
469
0
      *Size = 4;
470
0
      return Result;
471
0
    }
472
0
  }
473
474
108k
  if (mode & CS_MODE_MIPS32R6) {
475
    // DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
476
22.8k
    Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
477
22.8k
        Address, MRI, mode);
478
22.8k
    if (Result != MCDisassembler_Fail) {
479
10.6k
      *Size = 4;
480
10.6k
      return Result;
481
10.6k
    }
482
22.8k
  }
483
484
98.0k
  if (mode & CS_MODE_MIPS64) {
485
    // DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
486
66.4k
    Result = decodeInstruction(DecoderTableMips6432, instr, Insn,
487
66.4k
        Address, MRI, mode);
488
66.4k
    if (Result != MCDisassembler_Fail) {
489
15.9k
      *Size = 4;
490
15.9k
      return Result;
491
15.9k
    }
492
66.4k
  }
493
494
  // DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
495
  // Calling the auto-generated decoder function.
496
82.0k
  Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode);
497
82.0k
  if (Result != MCDisassembler_Fail) {
498
81.3k
    *Size = 4;
499
81.3k
    return Result;
500
81.3k
  }
501
502
699
  return MCDisassembler_Fail;
503
82.0k
}
504
505
bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr,
506
    uint16_t *size, uint64_t address, void *info)
507
140k
{
508
140k
  cs_struct *handle = (cs_struct *)(uintptr_t)ud;
509
510
140k
  DecodeStatus status = MipsDisassembler_getInstruction(handle->mode, instr,
511
140k
      code, code_len,
512
140k
      size,
513
140k
      address, MODE_IS_BIG_ENDIAN(handle->mode), (MCRegisterInfo *)info);
514
515
140k
  return status == MCDisassembler_Success;
516
140k
}
517
518
static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
519
246k
{
520
246k
  const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
521
246k
  return rc->RegsBegin[RegNo];
522
246k
}
523
524
static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn,
525
    uint64_t Address, const MCRegisterInfo *Decoder)
526
452
{
527
452
  typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, const MCRegisterInfo *);
528
  // The size of the n field depends on the element size
529
  // The register class also depends on this.
530
452
  uint32_t tmp = fieldFromInstruction(insn, 17, 5);
531
452
  unsigned NSize = 0;
532
452
  DecodeFN RegDecoder = NULL;
533
534
452
  if ((tmp & 0x18) == 0x00) { // INSVE_B
535
213
    NSize = 4;
536
213
    RegDecoder = DecodeMSA128BRegisterClass;
537
239
  } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
538
33
    NSize = 3;
539
33
    RegDecoder = DecodeMSA128HRegisterClass;
540
206
  } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
541
94
    NSize = 2;
542
94
    RegDecoder = DecodeMSA128WRegisterClass;
543
112
  } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
544
112
    NSize = 1;
545
112
    RegDecoder = DecodeMSA128DRegisterClass;
546
112
  } //else llvm_unreachable("Invalid encoding");
547
548
  //assert(NSize != 0 && RegDecoder != nullptr);
549
452
  if (NSize == 0 || RegDecoder == NULL)
550
0
    return MCDisassembler_Fail;
551
552
  // $wd
553
452
  tmp = fieldFromInstruction(insn, 6, 5);
554
452
  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
555
0
    return MCDisassembler_Fail;
556
557
  // $wd_in
558
452
  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
559
0
    return MCDisassembler_Fail;
560
561
  // $n
562
452
  tmp = fieldFromInstruction(insn, 16, NSize);
563
452
  MCOperand_CreateImm0(MI, tmp);
564
565
  // $ws
566
452
  tmp = fieldFromInstruction(insn, 11, 5);
567
452
  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
568
0
    return MCDisassembler_Fail;
569
570
  // $n2
571
452
  MCOperand_CreateImm0(MI, 0);
572
573
452
  return MCDisassembler_Success;
574
452
}
575
576
static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn,
577
    uint64_t Address, const MCRegisterInfo *Decoder)
578
1.30k
{
579
  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
580
  // (otherwise we would have matched the ADDI instruction from the earlier
581
  // ISA's instead).
582
  //
583
  // We have:
584
  //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
585
  //      BOVC if rs >= rt
586
  //      BEQZALC if rs == 0 && rt != 0
587
  //      BEQC if rs < rt && rs != 0
588
589
1.30k
  uint32_t Rs = fieldFromInstruction(insn, 21, 5);
590
1.30k
  uint32_t Rt = fieldFromInstruction(insn, 16, 5);
591
1.30k
  uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
592
1.30k
  bool HasRs = false;
593
594
1.30k
  if (Rs >= Rt) {
595
638
    MCInst_setOpcode(MI, Mips_BOVC);
596
638
    HasRs = true;
597
664
  } else if (Rs != 0 && Rs < Rt) {
598
541
    MCInst_setOpcode(MI, Mips_BEQC);
599
541
    HasRs = true;
600
541
  } else
601
123
    MCInst_setOpcode(MI, Mips_BEQZALC);
602
603
1.30k
  if (HasRs)
604
1.17k
    MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
605
606
1.30k
  MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
607
1.30k
  MCOperand_CreateImm0(MI, Imm);
608
609
1.30k
  return MCDisassembler_Success;
610
1.30k
}
611
612
static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn,
613
    uint64_t Address, const MCRegisterInfo *Decoder)
614
1.22k
{
615
  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
616
  // (otherwise we would have matched the ADDI instruction from the earlier
617
  // ISA's instead).
618
  //
619
  // We have:
620
  //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
621
  //      BNVC if rs >= rt
622
  //      BNEZALC if rs == 0 && rt != 0
623
  //      BNEC if rs < rt && rs != 0
624
625
1.22k
  uint32_t Rs = fieldFromInstruction(insn, 21, 5);
626
1.22k
  uint32_t Rt = fieldFromInstruction(insn, 16, 5);
627
1.22k
  uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
628
1.22k
  bool HasRs = false;
629
630
1.22k
  if (Rs >= Rt) {
631
642
    MCInst_setOpcode(MI, Mips_BNVC);
632
642
    HasRs = true;
633
642
  } else if (Rs != 0 && Rs < Rt) {
634
441
    MCInst_setOpcode(MI, Mips_BNEC);
635
441
    HasRs = true;
636
441
  } else
637
142
    MCInst_setOpcode(MI, Mips_BNEZALC);
638
639
1.22k
  if (HasRs)
640
1.08k
    MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
641
642
1.22k
  MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
643
1.22k
  MCOperand_CreateImm0(MI, Imm);
644
645
1.22k
  return MCDisassembler_Success;
646
1.22k
}
647
648
static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn,
649
    uint64_t Address, const MCRegisterInfo *Decoder)
650
889
{
651
  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
652
  // (otherwise we would have matched the BLEZL instruction from the earlier
653
  // ISA's instead).
654
  //
655
  // We have:
656
  //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
657
  //      Invalid if rs == 0
658
  //      BLEZC   if rs == 0  && rt != 0
659
  //      BGEZC   if rs == rt && rt != 0
660
  //      BGEC    if rs != rt && rs != 0  && rt != 0
661
662
889
  uint32_t Rs = fieldFromInstruction(insn, 21, 5);
663
889
  uint32_t Rt = fieldFromInstruction(insn, 16, 5);
664
889
  uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
665
889
  bool HasRs = false;
666
667
889
  if (Rt == 0)
668
3
    return MCDisassembler_Fail;
669
886
  else if (Rs == 0)
670
297
    MCInst_setOpcode(MI, Mips_BLEZC);
671
589
  else if (Rs == Rt)
672
103
    MCInst_setOpcode(MI, Mips_BGEZC);
673
486
  else {
674
486
    HasRs = true;
675
486
    MCInst_setOpcode(MI, Mips_BGEC);
676
486
  }
677
678
886
  if (HasRs)
679
486
    MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
680
681
886
  MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
682
683
886
  MCOperand_CreateImm0(MI, Imm);
684
685
886
  return MCDisassembler_Success;
686
889
}
687
688
static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn,
689
    uint64_t Address, const MCRegisterInfo *Decoder)
690
493
{
691
  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
692
  // (otherwise we would have matched the BGTZL instruction from the earlier
693
  // ISA's instead).
694
  //
695
  // We have:
696
  //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
697
  //      Invalid if rs == 0
698
  //      BGTZC   if rs == 0  && rt != 0
699
  //      BLTZC   if rs == rt && rt != 0
700
  //      BLTC    if rs != rt && rs != 0  && rt != 0
701
702
493
  bool HasRs = false;
703
704
493
  uint32_t Rs = fieldFromInstruction(insn, 21, 5);
705
493
  uint32_t Rt = fieldFromInstruction(insn, 16, 5);
706
493
  uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
707
708
493
  if (Rt == 0)
709
2
    return MCDisassembler_Fail;
710
491
  else if (Rs == 0)
711
102
    MCInst_setOpcode(MI, Mips_BGTZC);
712
389
  else if (Rs == Rt)
713
88
    MCInst_setOpcode(MI, Mips_BLTZC);
714
301
  else {
715
301
    MCInst_setOpcode(MI, Mips_BLTC);
716
301
    HasRs = true;
717
301
  }
718
719
491
  if (HasRs)
720
301
    MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
721
722
491
  MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
723
491
  MCOperand_CreateImm0(MI, Imm);
724
725
491
  return MCDisassembler_Success;
726
493
}
727
728
static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn,
729
    uint64_t Address, const MCRegisterInfo *Decoder)
730
1.20k
{
731
  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
732
  // (otherwise we would have matched the BGTZ instruction from the earlier
733
  // ISA's instead).
734
  //
735
  // We have:
736
  //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
737
  //      BGTZ    if rt == 0
738
  //      BGTZALC if rs == 0 && rt != 0
739
  //      BLTZALC if rs != 0 && rs == rt
740
  //      BLTUC   if rs != 0 && rs != rt
741
742
1.20k
  uint32_t Rs = fieldFromInstruction(insn, 21, 5);
743
1.20k
  uint32_t Rt = fieldFromInstruction(insn, 16, 5);
744
1.20k
  uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
745
1.20k
  bool HasRs = false;
746
1.20k
  bool HasRt = false;
747
748
1.20k
  if (Rt == 0) {
749
204
    MCInst_setOpcode(MI, Mips_BGTZ);
750
204
    HasRs = true;
751
996
  } else if (Rs == 0) {
752
291
    MCInst_setOpcode(MI, Mips_BGTZALC);
753
291
    HasRt = true;
754
705
  } else if (Rs == Rt) {
755
116
    MCInst_setOpcode(MI, Mips_BLTZALC);
756
116
    HasRs = true;
757
589
  } else {
758
589
    MCInst_setOpcode(MI, Mips_BLTUC);
759
589
    HasRs = true;
760
589
    HasRt = true;
761
589
  }
762
763
1.20k
  if (HasRs)
764
909
    MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
765
766
1.20k
  if (HasRt)
767
880
    MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
768
769
1.20k
  MCOperand_CreateImm0(MI, Imm);
770
771
1.20k
  return MCDisassembler_Success;
772
1.20k
}
773
774
static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn,
775
    uint64_t Address, const MCRegisterInfo *Decoder)
776
1.35k
{
777
  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
778
  // (otherwise we would have matched the BLEZL instruction from the earlier
779
  // ISA's instead).
780
  //
781
  // We have:
782
  //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
783
  //      Invalid   if rs == 0
784
  //      BLEZALC   if rs == 0  && rt != 0
785
  //      BGEZALC   if rs == rt && rt != 0
786
  //      BGEUC     if rs != rt && rs != 0  && rt != 0
787
788
1.35k
  uint32_t Rs = fieldFromInstruction(insn, 21, 5);
789
1.35k
  uint32_t Rt = fieldFromInstruction(insn, 16, 5);
790
1.35k
  uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
791
1.35k
  bool HasRs = false;
792
793
1.35k
  if (Rt == 0)
794
490
    return MCDisassembler_Fail;
795
866
  else if (Rs == 0)
796
251
    MCInst_setOpcode(MI, Mips_BLEZALC);
797
615
  else if (Rs == Rt)
798
83
    MCInst_setOpcode(MI, Mips_BGEZALC);
799
532
  else {
800
532
    HasRs = true;
801
532
    MCInst_setOpcode(MI, Mips_BGEUC);
802
532
  }
803
804
866
  if (HasRs)
805
532
    MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
806
807
866
  MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
808
809
866
  MCOperand_CreateImm0(MI, Imm);
810
811
866
  return MCDisassembler_Success;
812
1.35k
}
813
814
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
815
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
816
0
{
817
0
  return MCDisassembler_Fail;
818
0
}
819
820
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
821
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
822
15.8k
{
823
15.8k
  unsigned Reg;
824
825
15.8k
  if (RegNo > 31)
826
0
    return MCDisassembler_Fail;
827
828
15.8k
  Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo);
829
15.8k
  MCOperand_CreateReg0(Inst, Reg);
830
15.8k
  return MCDisassembler_Success;
831
15.8k
}
832
833
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst,
834
    unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
835
19.1k
{
836
19.1k
  unsigned Reg;
837
838
19.1k
  if (RegNo > 7)
839
0
    return MCDisassembler_Fail;
840
841
19.1k
  Reg = getReg(Decoder, Mips_GPRMM16RegClassID, RegNo);
842
19.1k
  MCOperand_CreateReg0(Inst, Reg);
843
19.1k
  return MCDisassembler_Success;
844
19.1k
}
845
846
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst,
847
    unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
848
1.54k
{
849
1.54k
  unsigned Reg;
850
851
1.54k
  if (RegNo > 7)
852
0
    return MCDisassembler_Fail;
853
854
1.54k
  Reg = getReg(Decoder, Mips_GPRMM16ZeroRegClassID, RegNo);
855
1.54k
  MCOperand_CreateReg0(Inst, Reg);
856
1.54k
  return MCDisassembler_Success;
857
1.54k
}
858
859
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst,
860
    unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
861
1.07k
{
862
1.07k
  unsigned Reg;
863
864
1.07k
  if (RegNo > 7)
865
0
    return MCDisassembler_Fail;
866
867
1.07k
  Reg = getReg(Decoder, Mips_GPRMM16MovePRegClassID, RegNo);
868
1.07k
  MCOperand_CreateReg0(Inst, Reg);
869
1.07k
  return MCDisassembler_Success;
870
1.07k
}
871
872
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
873
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
874
88.7k
{
875
88.7k
  unsigned Reg;
876
877
88.7k
  if (RegNo > 31)
878
0
    return MCDisassembler_Fail;
879
880
88.7k
  Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo);
881
88.7k
  MCOperand_CreateReg0(Inst, Reg);
882
88.7k
  return MCDisassembler_Success;
883
88.7k
}
884
885
static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
886
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
887
3.23k
{
888
  // if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
889
3.23k
  if (Inst->csh->mode & CS_MODE_MIPS64)
890
714
    return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
891
892
2.52k
  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
893
3.23k
}
894
895
static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst,
896
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
897
2.75k
{
898
2.75k
  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
899
2.75k
}
900
901
static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
902
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
903
6.19k
{
904
6.19k
  unsigned Reg;
905
906
6.19k
  if (RegNo > 31)
907
0
    return MCDisassembler_Fail;
908
909
6.19k
  Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo);
910
6.19k
  MCOperand_CreateReg0(Inst, Reg);
911
6.19k
  return MCDisassembler_Success;
912
6.19k
}
913
914
static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
915
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
916
4.88k
{
917
4.88k
  unsigned Reg;
918
919
4.88k
  if (RegNo > 31)
920
0
    return MCDisassembler_Fail;
921
922
4.88k
  Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo);
923
4.88k
  MCOperand_CreateReg0(Inst, Reg);
924
4.88k
  return MCDisassembler_Success;
925
4.88k
}
926
927
static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
928
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
929
234
{
930
234
  unsigned Reg;
931
932
234
  if (RegNo > 31)
933
0
    return MCDisassembler_Fail;
934
935
234
  Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo);
936
234
  MCOperand_CreateReg0(Inst, Reg);
937
234
  return MCDisassembler_Success;
938
234
}
939
940
static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
941
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
942
3.30k
{
943
3.30k
  unsigned Reg;
944
945
3.30k
  if (RegNo > 7)
946
0
    return MCDisassembler_Fail;
947
948
3.30k
  Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo);
949
3.30k
  MCOperand_CreateReg0(Inst, Reg);
950
3.30k
  return MCDisassembler_Success;
951
3.30k
}
952
953
static DecodeStatus DecodeCCRegisterClass(MCInst *Inst,
954
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
955
4.62k
{
956
4.62k
  unsigned Reg;
957
958
4.62k
  if (RegNo > 7)
959
0
    return MCDisassembler_Fail;
960
961
4.62k
  Reg = getReg(Decoder, Mips_CCRegClassID, RegNo);
962
4.62k
  MCOperand_CreateReg0(Inst, Reg);
963
4.62k
  return MCDisassembler_Success;
964
4.62k
}
965
966
static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
967
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
968
223
{
969
223
  unsigned Reg;
970
971
223
  if (RegNo > 31)
972
0
    return MCDisassembler_Fail;
973
974
223
  Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo);
975
223
  MCOperand_CreateReg0(Inst, Reg);
976
223
  return MCDisassembler_Success;
977
223
}
978
979
static DecodeStatus DecodeMem(MCInst *Inst,
980
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
981
13.6k
{
982
13.6k
  int Offset = SignExtend32(Insn & 0xffff, 16);
983
13.6k
  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
984
13.6k
  unsigned Base = fieldFromInstruction(Insn, 21, 5);
985
13.6k
  int opcode = MCInst_getOpcode(Inst);
986
987
13.6k
  Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
988
13.6k
  Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
989
990
13.6k
  if (opcode == Mips_SC || opcode == Mips_SCD) {
991
2.22k
    MCOperand_CreateReg0(Inst, Reg);
992
2.22k
  }
993
994
13.6k
  MCOperand_CreateReg0(Inst, Reg);
995
13.6k
  MCOperand_CreateReg0(Inst, Base);
996
13.6k
  MCOperand_CreateImm0(Inst, Offset);
997
998
13.6k
  return MCDisassembler_Success;
999
13.6k
}
1000
1001
static DecodeStatus DecodeCacheOp(MCInst *Inst,
1002
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1003
906
{
1004
906
  int Offset = SignExtend32(Insn & 0xffff, 16);
1005
906
  unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1006
906
  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1007
1008
906
  Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1009
1010
906
  MCOperand_CreateReg0(Inst, Base);
1011
906
  MCOperand_CreateImm0(Inst, Offset);
1012
906
  MCOperand_CreateImm0(Inst, Hint);
1013
1014
906
  return MCDisassembler_Success;
1015
906
}
1016
1017
static DecodeStatus DecodeCacheOpMM(MCInst *Inst,
1018
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1019
221
{
1020
221
  int Offset = SignExtend32(Insn & 0xfff, 12);
1021
221
  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1022
221
  unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1023
1024
221
  Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1025
1026
221
  MCOperand_CreateReg0(Inst, Base);
1027
221
  MCOperand_CreateImm0(Inst, Offset);
1028
221
  MCOperand_CreateImm0(Inst, Hint);
1029
1030
221
  return MCDisassembler_Success;
1031
221
}
1032
1033
static DecodeStatus DecodeCacheOpR6(MCInst *Inst,
1034
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1035
207
{
1036
207
  int Offset = fieldFromInstruction(Insn, 7, 9);
1037
207
  unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1038
207
  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1039
1040
207
  Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1041
1042
207
  MCOperand_CreateReg0(Inst, Base);
1043
207
  MCOperand_CreateImm0(Inst, Offset);
1044
207
  MCOperand_CreateImm0(Inst, Hint);
1045
1046
207
  return MCDisassembler_Success;
1047
207
}
1048
1049
static DecodeStatus DecodeSyncI(MCInst *Inst,
1050
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1051
311
{
1052
311
  int Offset = SignExtend32(Insn & 0xffff, 16);
1053
311
  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1054
1055
311
  Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1056
1057
311
  MCOperand_CreateReg0(Inst, Base);
1058
311
  MCOperand_CreateImm0(Inst, Offset);
1059
1060
311
  return MCDisassembler_Success;
1061
311
}
1062
1063
static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn,
1064
    uint64_t Address, const MCRegisterInfo *Decoder)
1065
2.66k
{
1066
2.66k
  int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10);
1067
2.66k
  unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1068
2.66k
  unsigned Base = fieldFromInstruction(Insn, 11, 5);
1069
1070
2.66k
  Reg = getReg(Decoder, Mips_MSA128BRegClassID, Reg);
1071
2.66k
  Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1072
1073
2.66k
  MCOperand_CreateReg0(Inst, Reg);
1074
2.66k
  MCOperand_CreateReg0(Inst, Base);
1075
  // MCOperand_CreateImm0(Inst, Offset);
1076
1077
  // The immediate field of an LD/ST instruction is scaled which means it must
1078
  // be multiplied (when decoding) by the size (in bytes) of the instructions'
1079
  // data format.
1080
  // .b - 1 byte
1081
  // .h - 2 bytes
1082
  // .w - 4 bytes
1083
  // .d - 8 bytes
1084
2.66k
  switch(MCInst_getOpcode(Inst)) {
1085
0
    default:
1086
      //assert (0 && "Unexpected instruction");
1087
0
      return MCDisassembler_Fail;
1088
0
      break;
1089
604
    case Mips_LD_B:
1090
940
    case Mips_ST_B:
1091
940
      MCOperand_CreateImm0(Inst, Offset);
1092
940
      break;
1093
487
    case Mips_LD_H:
1094
726
    case Mips_ST_H:
1095
726
      MCOperand_CreateImm0(Inst, Offset * 2);
1096
726
      break;
1097
351
    case Mips_LD_W:
1098
480
    case Mips_ST_W:
1099
480
      MCOperand_CreateImm0(Inst, Offset * 4);
1100
480
      break;
1101
284
    case Mips_LD_D:
1102
523
    case Mips_ST_D:
1103
523
      MCOperand_CreateImm0(Inst, Offset * 8);
1104
523
      break;
1105
2.66k
  }
1106
1107
2.66k
  return MCDisassembler_Success;
1108
2.66k
}
1109
1110
static DecodeStatus DecodeMemMMImm4(MCInst *Inst,
1111
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1112
4.00k
{
1113
4.00k
  unsigned Offset = Insn & 0xf;
1114
4.00k
  unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1115
4.00k
  unsigned Base = fieldFromInstruction(Insn, 4, 3);
1116
1117
4.00k
  switch (MCInst_getOpcode(Inst)) {
1118
1.18k
    case Mips_LBU16_MM:
1119
1.99k
    case Mips_LHU16_MM:
1120
2.45k
    case Mips_LW16_MM:
1121
2.45k
      if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1122
2.45k
          == MCDisassembler_Fail)
1123
0
        return MCDisassembler_Fail;
1124
2.45k
      break;
1125
2.45k
    case Mips_SB16_MM:
1126
1.06k
    case Mips_SH16_MM:
1127
1.54k
    case Mips_SW16_MM:
1128
1.54k
      if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1129
1.54k
          == MCDisassembler_Fail)
1130
0
        return MCDisassembler_Fail;
1131
1.54k
      break;
1132
4.00k
  }
1133
1134
4.00k
  if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1135
4.00k
      == MCDisassembler_Fail)
1136
0
    return MCDisassembler_Fail;
1137
1138
4.00k
  switch (MCInst_getOpcode(Inst)) {
1139
1.18k
    case Mips_LBU16_MM:
1140
1.18k
      if (Offset == 0xf)
1141
264
        MCOperand_CreateImm0(Inst, -1);
1142
925
      else
1143
925
        MCOperand_CreateImm0(Inst, Offset);
1144
1.18k
      break;
1145
626
    case Mips_SB16_MM:
1146
626
      MCOperand_CreateImm0(Inst, Offset);
1147
626
      break;
1148
803
    case Mips_LHU16_MM:
1149
1.24k
    case Mips_SH16_MM:
1150
1.24k
      MCOperand_CreateImm0(Inst, Offset << 1);
1151
1.24k
      break;
1152
466
    case Mips_LW16_MM:
1153
940
    case Mips_SW16_MM:
1154
940
      MCOperand_CreateImm0(Inst, Offset << 2);
1155
940
      break;
1156
4.00k
  }
1157
1158
4.00k
  return MCDisassembler_Success;
1159
4.00k
}
1160
1161
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst,
1162
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1163
686
{
1164
686
  unsigned Offset = Insn & 0x1F;
1165
686
  unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1166
1167
686
  Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
1168
1169
686
  MCOperand_CreateReg0(Inst, Reg);
1170
686
  MCOperand_CreateReg0(Inst, Mips_SP);
1171
686
  MCOperand_CreateImm0(Inst, Offset << 2);
1172
1173
686
  return MCDisassembler_Success;
1174
686
}
1175
1176
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst,
1177
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1178
974
{
1179
974
  unsigned Offset = Insn & 0x7F;
1180
974
  unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1181
1182
974
  Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
1183
1184
974
  MCOperand_CreateReg0(Inst, Reg);
1185
974
  MCOperand_CreateReg0(Inst, Mips_GP);
1186
974
  MCOperand_CreateImm0(Inst, Offset << 2);
1187
1188
974
  return MCDisassembler_Success;
1189
974
}
1190
1191
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst,
1192
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1193
799
{
1194
799
  int Offset = SignExtend32(Insn & 0xf, 4);
1195
1196
799
  if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == MCDisassembler_Fail)
1197
0
    return MCDisassembler_Fail;
1198
1199
799
  MCOperand_CreateReg0(Inst, Mips_SP);
1200
799
  MCOperand_CreateImm0(Inst, Offset * 4);
1201
1202
799
  return MCDisassembler_Success;
1203
799
}
1204
1205
static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
1206
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1207
1.61k
{
1208
1.61k
  int Offset = SignExtend32(Insn & 0x0fff, 12);
1209
1.61k
  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1210
1.61k
  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1211
1212
1.61k
  Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
1213
1.61k
  Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1214
1215
1.61k
  switch (MCInst_getOpcode(Inst)) {
1216
388
    case Mips_SWM32_MM:
1217
961
    case Mips_LWM32_MM:
1218
961
      if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1219
961
          == MCDisassembler_Fail)
1220
2
        return MCDisassembler_Fail;
1221
959
      MCOperand_CreateReg0(Inst, Base);
1222
959
      MCOperand_CreateImm0(Inst, Offset);
1223
959
      break;
1224
95
    case Mips_SC_MM:
1225
95
      MCOperand_CreateReg0(Inst, Reg);
1226
      // fallthrough
1227
656
    default:
1228
656
      MCOperand_CreateReg0(Inst, Reg);
1229
656
      if (MCInst_getOpcode(Inst) == Mips_LWP_MM || MCInst_getOpcode(Inst) == Mips_SWP_MM)
1230
289
        MCOperand_CreateReg0(Inst, Reg + 1);
1231
1232
656
      MCOperand_CreateReg0(Inst, Base);
1233
656
      MCOperand_CreateImm0(Inst, Offset);
1234
1.61k
  }
1235
1236
1.61k
  return MCDisassembler_Success;
1237
1.61k
}
1238
1239
static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
1240
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1241
2.36k
{
1242
2.36k
  int Offset = SignExtend32(Insn & 0xffff, 16);
1243
2.36k
  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1244
2.36k
  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1245
1246
2.36k
  Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
1247
2.36k
  Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1248
1249
2.36k
  MCOperand_CreateReg0(Inst, Reg);
1250
2.36k
  MCOperand_CreateReg0(Inst, Base);
1251
2.36k
  MCOperand_CreateImm0(Inst, Offset);
1252
1253
2.36k
  return MCDisassembler_Success;
1254
2.36k
}
1255
1256
static DecodeStatus DecodeFMem(MCInst *Inst,
1257
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1258
3.17k
{
1259
3.17k
  int Offset = SignExtend32(Insn & 0xffff, 16);
1260
3.17k
  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1261
3.17k
  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1262
1263
3.17k
  Reg = getReg(Decoder, Mips_FGR64RegClassID, Reg);
1264
3.17k
  Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1265
1266
3.17k
  MCOperand_CreateReg0(Inst, Reg);
1267
3.17k
  MCOperand_CreateReg0(Inst, Base);
1268
3.17k
  MCOperand_CreateImm0(Inst, Offset);
1269
1270
3.17k
  return MCDisassembler_Success;
1271
3.17k
}
1272
1273
static DecodeStatus DecodeFMem2(MCInst *Inst,
1274
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1275
876
{
1276
876
  int Offset = SignExtend32(Insn & 0xffff, 16);
1277
876
  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1278
876
  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1279
1280
876
  Reg = getReg(Decoder, Mips_COP2RegClassID, Reg);
1281
876
  Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1282
1283
876
  MCOperand_CreateReg0(Inst, Reg);
1284
876
  MCOperand_CreateReg0(Inst, Base);
1285
876
  MCOperand_CreateImm0(Inst, Offset);
1286
1287
876
  return MCDisassembler_Success;
1288
876
}
1289
1290
static DecodeStatus DecodeFMem3(MCInst *Inst,
1291
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1292
0
{
1293
0
  int Offset = SignExtend32(Insn & 0xffff, 16);
1294
0
  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1295
0
  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1296
1297
0
  Reg = getReg(Decoder, Mips_COP3RegClassID, Reg);
1298
0
  Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1299
1300
0
  MCOperand_CreateReg0(Inst, Reg);
1301
0
  MCOperand_CreateReg0(Inst, Base);
1302
0
  MCOperand_CreateImm0(Inst, Offset);
1303
1304
0
  return MCDisassembler_Success;
1305
0
}
1306
1307
static DecodeStatus DecodeFMemCop2R6(MCInst *Inst,
1308
    unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1309
711
{
1310
711
  int Offset = SignExtend32(Insn & 0x07ff, 11);
1311
711
  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1312
711
  unsigned Base = fieldFromInstruction(Insn, 11, 5);
1313
1314
711
  Reg = getReg(Decoder, Mips_COP2RegClassID, Reg);
1315
711
  Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1316
1317
711
  MCOperand_CreateReg0(Inst, Reg);
1318
711
  MCOperand_CreateReg0(Inst, Base);
1319
711
  MCOperand_CreateImm0(Inst, Offset);
1320
1321
711
  return MCDisassembler_Success;
1322
711
}
1323
1324
static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
1325
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1326
322
{
1327
322
  int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9);
1328
322
  unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1329
322
  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1330
1331
322
  Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt);
1332
322
  Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1333
1334
322
  if (MCInst_getOpcode(Inst) == Mips_SC_R6 ||
1335
322
      MCInst_getOpcode(Inst) == Mips_SCD_R6) {
1336
240
    MCOperand_CreateReg0(Inst, Rt);
1337
240
  }
1338
1339
322
  MCOperand_CreateReg0(Inst, Rt);
1340
322
  MCOperand_CreateReg0(Inst, Base);
1341
322
  MCOperand_CreateImm0(Inst, Offset);
1342
1343
322
  return MCDisassembler_Success;
1344
322
}
1345
1346
static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
1347
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1348
128
{
1349
  // Currently only hardware register 29 is supported.
1350
128
  if (RegNo != 29)
1351
5
    return  MCDisassembler_Fail;
1352
1353
123
  MCOperand_CreateReg0(Inst, Mips_HWR29);
1354
1355
123
  return MCDisassembler_Success;
1356
128
}
1357
1358
static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
1359
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1360
2.16k
{
1361
2.16k
  unsigned Reg;
1362
1363
2.16k
  if (RegNo > 30 || RegNo % 2)
1364
32
    return MCDisassembler_Fail;
1365
1366
2.12k
  Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2);
1367
2.12k
  MCOperand_CreateReg0(Inst, Reg);
1368
1369
2.12k
  return MCDisassembler_Success;
1370
2.16k
}
1371
1372
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
1373
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1374
1.21k
{
1375
1.21k
  unsigned Reg;
1376
1377
1.21k
  if (RegNo >= 4)
1378
0
    return MCDisassembler_Fail;
1379
1380
1.21k
  Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo);
1381
1.21k
  MCOperand_CreateReg0(Inst, Reg);
1382
1.21k
  return MCDisassembler_Success;
1383
1.21k
}
1384
1385
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
1386
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1387
161
{
1388
161
  unsigned Reg;
1389
1390
161
  if (RegNo >= 4)
1391
0
    return MCDisassembler_Fail;
1392
1393
161
  Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo);
1394
161
  MCOperand_CreateReg0(Inst, Reg);
1395
1396
161
  return MCDisassembler_Success;
1397
161
}
1398
1399
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
1400
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1401
904
{
1402
904
  unsigned Reg;
1403
1404
904
  if (RegNo >= 4)
1405
0
    return MCDisassembler_Fail;
1406
1407
904
  Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo);
1408
904
  MCOperand_CreateReg0(Inst, Reg);
1409
1410
904
  return MCDisassembler_Success;
1411
904
}
1412
1413
static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
1414
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1415
11.0k
{
1416
11.0k
  unsigned Reg;
1417
1418
11.0k
  if (RegNo > 31)
1419
0
    return MCDisassembler_Fail;
1420
1421
11.0k
  Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo);
1422
11.0k
  MCOperand_CreateReg0(Inst, Reg);
1423
1424
11.0k
  return MCDisassembler_Success;
1425
11.0k
}
1426
1427
static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
1428
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1429
5.69k
{
1430
5.69k
  unsigned Reg;
1431
1432
5.69k
  if (RegNo > 31)
1433
0
    return MCDisassembler_Fail;
1434
1435
5.69k
  Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo);
1436
5.69k
  MCOperand_CreateReg0(Inst, Reg);
1437
1438
5.69k
  return MCDisassembler_Success;
1439
5.69k
}
1440
1441
static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
1442
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1443
6.99k
{
1444
6.99k
  unsigned Reg;
1445
1446
6.99k
  if (RegNo > 31)
1447
0
    return MCDisassembler_Fail;
1448
1449
6.99k
  Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo);
1450
6.99k
  MCOperand_CreateReg0(Inst, Reg);
1451
1452
6.99k
  return MCDisassembler_Success;
1453
6.99k
}
1454
1455
static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
1456
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1457
7.70k
{
1458
7.70k
  unsigned Reg;
1459
1460
7.70k
  if (RegNo > 31)
1461
0
    return MCDisassembler_Fail;
1462
1463
7.70k
  Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo);
1464
7.70k
  MCOperand_CreateReg0(Inst, Reg);
1465
1466
7.70k
  return MCDisassembler_Success;
1467
7.70k
}
1468
1469
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
1470
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1471
114
{
1472
114
  unsigned Reg;
1473
1474
114
  if (RegNo > 7)
1475
3
    return MCDisassembler_Fail;
1476
1477
111
  Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo);
1478
111
  MCOperand_CreateReg0(Inst, Reg);
1479
1480
111
  return MCDisassembler_Success;
1481
114
}
1482
1483
static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
1484
    unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
1485
215
{
1486
215
  unsigned Reg;
1487
1488
215
  if (RegNo > 31)
1489
0
    return MCDisassembler_Fail;
1490
1491
215
  Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo);
1492
215
  MCOperand_CreateReg0(Inst, Reg);
1493
1494
215
  return MCDisassembler_Success;
1495
215
}
1496
1497
static DecodeStatus DecodeBranchTarget(MCInst *Inst,
1498
    unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
1499
17.5k
{
1500
17.5k
  uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4;
1501
17.5k
  MCOperand_CreateImm0(Inst, TargetAddress);
1502
1503
17.5k
  return MCDisassembler_Success;
1504
17.5k
}
1505
1506
static DecodeStatus DecodeJumpTarget(MCInst *Inst,
1507
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1508
4.57k
{
1509
4.57k
  uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF);
1510
4.57k
  MCOperand_CreateImm0(Inst, TargetAddress);
1511
1512
4.57k
  return MCDisassembler_Success;
1513
4.57k
}
1514
1515
static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
1516
    unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
1517
488
{
1518
488
  int32_t BranchOffset = SignExtend32(Offset, 21) * 4;
1519
1520
488
  MCOperand_CreateImm0(Inst, BranchOffset);
1521
1522
488
  return MCDisassembler_Success;
1523
488
}
1524
1525
static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
1526
    unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
1527
505
{
1528
505
  int32_t BranchOffset = SignExtend32(Offset, 26) * 4;
1529
1530
505
  MCOperand_CreateImm0(Inst, BranchOffset);
1531
505
  return MCDisassembler_Success;
1532
505
}
1533
1534
static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst,
1535
    unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
1536
547
{
1537
547
  int32_t BranchOffset = SignExtend32(Offset, 7) * 2;
1538
547
  MCOperand_CreateImm0(Inst, BranchOffset);
1539
547
  return MCDisassembler_Success;
1540
547
}
1541
1542
static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst,
1543
    unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
1544
559
{
1545
559
  int32_t BranchOffset = SignExtend32(Offset, 10) * 2;
1546
559
  MCOperand_CreateImm0(Inst, BranchOffset);
1547
559
  return MCDisassembler_Success;
1548
559
}
1549
1550
static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
1551
    unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
1552
677
{
1553
677
  int32_t BranchOffset = SignExtend32(Offset, 16) * 2;
1554
677
  MCOperand_CreateImm0(Inst, BranchOffset);
1555
1556
677
  return MCDisassembler_Success;
1557
677
}
1558
1559
static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
1560
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1561
752
{
1562
752
  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1563
752
  MCOperand_CreateImm0(Inst, JumpOffset);
1564
1565
752
  return MCDisassembler_Success;
1566
752
}
1567
1568
static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst,
1569
    unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
1570
1.16k
{
1571
1.16k
  if (Value == 0)
1572
247
    MCOperand_CreateImm0(Inst, 1);
1573
913
  else if (Value == 0x7)
1574
251
    MCOperand_CreateImm0(Inst, -1);
1575
662
  else
1576
662
    MCOperand_CreateImm0(Inst, Value << 2);
1577
1578
1.16k
  return MCDisassembler_Success;
1579
1.16k
}
1580
1581
static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst,
1582
    unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
1583
1.81k
{
1584
1.81k
  MCOperand_CreateImm0(Inst, Value << 2);
1585
1586
1.81k
  return MCDisassembler_Success;
1587
1.81k
}
1588
1589
static DecodeStatus DecodeLiSimm7(MCInst *Inst,
1590
    unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
1591
865
{
1592
865
  if (Value == 0x7F)
1593
77
    MCOperand_CreateImm0(Inst, -1);
1594
788
  else
1595
788
    MCOperand_CreateImm0(Inst, Value);
1596
1597
865
  return MCDisassembler_Success;
1598
865
}
1599
1600
static DecodeStatus DecodeSimm4(MCInst *Inst,
1601
    unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
1602
816
{
1603
816
  MCOperand_CreateImm0(Inst, SignExtend32(Value, 4));
1604
1605
816
  return MCDisassembler_Success;
1606
816
}
1607
1608
static DecodeStatus DecodeSimm16(MCInst *Inst,
1609
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1610
7.60k
{
1611
7.60k
  MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16));
1612
1613
7.60k
  return MCDisassembler_Success;
1614
7.60k
}
1615
1616
static DecodeStatus DecodeLSAImm(MCInst *Inst,
1617
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1618
337
{
1619
  // We add one to the immediate field as it was encoded as 'imm - 1'.
1620
337
  MCOperand_CreateImm0(Inst, Insn + 1);
1621
1622
337
  return MCDisassembler_Success;
1623
337
}
1624
1625
static DecodeStatus DecodeInsSize(MCInst *Inst,
1626
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1627
834
{
1628
  // First we need to grab the pos(lsb) from MCInst.
1629
834
  int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2));
1630
834
  int Size = (int) Insn - Pos + 1;
1631
834
  MCOperand_CreateImm0(Inst, SignExtend32(Size, 16));
1632
1633
834
  return MCDisassembler_Success;
1634
834
}
1635
1636
static DecodeStatus DecodeExtSize(MCInst *Inst,
1637
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1638
922
{
1639
922
  int Size = (int)Insn  + 1;
1640
1641
922
  MCOperand_CreateImm0(Inst, SignExtend32(Size, 16));
1642
1643
922
  return MCDisassembler_Success;
1644
922
}
1645
1646
static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
1647
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1648
283
{
1649
283
  MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4);
1650
1651
283
  return MCDisassembler_Success;
1652
283
}
1653
1654
static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
1655
    unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
1656
0
{
1657
0
  MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8);
1658
1659
0
  return MCDisassembler_Success;
1660
0
}
1661
1662
static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn,
1663
    uint64_t Address, MCRegisterInfo *Decoder)
1664
1.61k
{
1665
1.61k
  int32_t DecodedValue;
1666
1667
1.61k
  switch (Insn) {
1668
91
    case 0: DecodedValue = 256; break;
1669
454
    case 1: DecodedValue = 257; break;
1670
217
    case 510: DecodedValue = -258; break;
1671
220
    case 511: DecodedValue = -257; break;
1672
635
    default: DecodedValue = SignExtend32(Insn, 9); break;
1673
1.61k
  }
1674
1.61k
  MCOperand_CreateImm0(Inst, DecodedValue * 4);
1675
1676
1.61k
  return MCDisassembler_Success;
1677
1.61k
}
1678
1679
static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn,
1680
    uint64_t Address, MCRegisterInfo *Decoder)
1681
493
{
1682
  // Insn must be >= 0, since it is unsigned that condition is always true.
1683
  // assert(Insn < 16);
1684
493
  int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1685
493
    255, 32768, 65535};
1686
1687
493
  if (Insn >= 16)
1688
0
    return MCDisassembler_Fail;
1689
1690
493
  MCOperand_CreateImm0(Inst, DecodedValues[Insn]);
1691
1692
493
  return MCDisassembler_Success;
1693
493
}
1694
1695
static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, unsigned Insn,
1696
    uint64_t Address, MCRegisterInfo *Decoder)
1697
216
{
1698
216
  MCOperand_CreateImm0(Inst, Insn << 2);
1699
1700
216
  return MCDisassembler_Success;
1701
216
}
1702
1703
static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn,
1704
    uint64_t Address, const MCRegisterInfo *Decoder)
1705
961
{
1706
961
  unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5,
1707
961
    Mips_S6, Mips_FP};
1708
961
  unsigned RegNum;
1709
961
  unsigned int i;
1710
1711
961
  unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1712
  // Empty register lists are not allowed.
1713
961
  if (RegLst == 0)
1714
2
    return MCDisassembler_Fail;
1715
1716
959
  RegNum = RegLst & 0xf;
1717
6.70k
  for (i = 0; i < MIN(RegNum, ARR_SIZE(Regs)); i++)
1718
5.74k
    MCOperand_CreateReg0(Inst, Regs[i]);
1719
1720
959
  if (RegLst & 0x10)
1721
487
    MCOperand_CreateReg0(Inst, Mips_RA);
1722
1723
959
  return MCDisassembler_Success;
1724
961
}
1725
1726
static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn,
1727
    uint64_t Address, MCRegisterInfo *Decoder)
1728
799
{
1729
799
  unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3};
1730
799
  unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1731
799
  unsigned RegNum = RegLst & 0x3;
1732
799
  unsigned int i;
1733
1734
2.58k
  for (i = 0; i <= RegNum; i++)
1735
1.78k
    MCOperand_CreateReg0(Inst, Regs[i]);
1736
1737
799
  MCOperand_CreateReg0(Inst, Mips_RA);
1738
1739
799
  return MCDisassembler_Success;
1740
799
}
1741
1742
static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned Insn,
1743
    uint64_t Address, MCRegisterInfo *Decoder)
1744
537
{
1745
537
  unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1746
1747
537
  switch (RegPair) {
1748
0
    default:
1749
0
      return MCDisassembler_Fail;
1750
537
    case 0:
1751
537
      MCOperand_CreateReg0(Inst, Mips_A1);
1752
537
      MCOperand_CreateReg0(Inst, Mips_A2);
1753
537
      break;
1754
0
    case 1:
1755
0
      MCOperand_CreateReg0(Inst, Mips_A1);
1756
0
      MCOperand_CreateReg0(Inst, Mips_A3);
1757
0
      break;
1758
0
    case 2:
1759
0
      MCOperand_CreateReg0(Inst, Mips_A2);
1760
0
      MCOperand_CreateReg0(Inst, Mips_A3);
1761
0
      break;
1762
0
    case 3:
1763
0
      MCOperand_CreateReg0(Inst, Mips_A0);
1764
0
      MCOperand_CreateReg0(Inst, Mips_S5);
1765
0
      break;
1766
0
    case 4:
1767
0
      MCOperand_CreateReg0(Inst, Mips_A0);
1768
0
      MCOperand_CreateReg0(Inst, Mips_S6);
1769
0
      break;
1770
0
    case 5:
1771
0
      MCOperand_CreateReg0(Inst, Mips_A0);
1772
0
      MCOperand_CreateReg0(Inst, Mips_A1);
1773
0
      break;
1774
0
    case 6:
1775
0
      MCOperand_CreateReg0(Inst, Mips_A0);
1776
0
      MCOperand_CreateReg0(Inst, Mips_A2);
1777
0
      break;
1778
0
    case 7:
1779
0
      MCOperand_CreateReg0(Inst, Mips_A0);
1780
0
      MCOperand_CreateReg0(Inst, Mips_A3);
1781
0
      break;
1782
537
  }
1783
1784
537
  return MCDisassembler_Success;
1785
537
}
1786
1787
static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn,
1788
    uint64_t Address, MCRegisterInfo *Decoder)
1789
555
{
1790
555
  MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) * 4);
1791
555
  return MCDisassembler_Success;
1792
555
}
1793
1794
#endif