Coverage Report

Created: 2023-09-25 06:24

/src/capstonenext/arch/PowerPC/PPCInstrInfo.h
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Source (jump to first uncovered line)
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Rot127 <unisono@quyllur.org> 2022-2023 */
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#ifndef CS_PPC_INSTRINFO_H
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#define CS_PPC_INSTRINFO_H
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#include "PPCMCTargetDesc.h"
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extern const MCInstrDesc PPCInsts[];
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static bool isVFRegister(unsigned Reg)
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9.30k
{
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  return Reg >= PPC_VF0 && Reg <= PPC_VF31;
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}
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static bool isVRRegister(unsigned Reg)
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{
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  return Reg >= PPC_V0 && Reg <= PPC_V31;
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}
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/// getRegNumForOperand - some operands use different numbering schemes
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/// for the same registers. For example, a VSX instruction may have any of
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/// vs0-vs63 allocated whereas an Altivec instruction could only have
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/// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
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/// register number needed for the opcode/operand number combination.
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/// The operand number argument will be useful when we need to extend this
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/// to instructions that use both Altivec and VSX numbering (for different
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/// operands).
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static unsigned PPCInstrInfo_getRegNumForOperand(const MCInstrDesc *Desc,
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             unsigned Reg, unsigned OpNo)
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127k
{
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  int16_t regClass = Desc->OpInfo[OpNo].RegClass;
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  switch (regClass) {
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  // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
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  // VSX32-VSX63 during encoding/disassembling
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  case PPC_VSSRCRegClassID:
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  case PPC_VSFRCRegClassID:
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    if (isVFRegister(Reg))
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      return PPC_VSX32 + (Reg - PPC_VF0);
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    break;
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  // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
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  // VSX32-VSX63 during encoding/disassembling
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  case PPC_VSRCRegClassID:
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    if (isVRRegister(Reg))
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      return PPC_VSX32 + (Reg - PPC_V0);
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    break;
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  // Other RegClass doesn't need mapping
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111k
  default:
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    break;
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  }
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  return Reg;
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}
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#endif // CS_PPC_INSTRINFO_H